1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_api.h"
35 #include "ixgbe_common.h"
36 #include "ixgbe_phy.h"
38 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
39 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
40 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
41 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
42 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
43 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
44 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
45 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
46 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
47 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
48 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
49 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
53 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
54 * @hw: pointer to the hardware structure
57 * Returns an error code on error.
59 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
63 status = ixgbe_clock_out_i2c_byte(hw, byte);
66 return ixgbe_get_i2c_ack(hw);
70 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
71 * @hw: pointer to the hardware structure
72 * @byte: pointer to a u8 to receive the byte
74 * Returns an error code on error.
76 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
80 status = ixgbe_clock_in_i2c_byte(hw, byte);
84 return ixgbe_clock_out_i2c_bit(hw, false);
88 * ixgbe_ones_comp_byte_add - Perform one's complement addition
92 * Returns one's complement 8-bit sum.
94 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
96 u16 sum = add1 + add2;
98 sum = (sum & 0xFF) + (sum >> 8);
103 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
104 * @hw: pointer to the hardware structure
105 * @addr: I2C bus address to read from
106 * @reg: I2C device register to read from
107 * @val: pointer to location to receive read value
108 * @lock: true if to take and release semaphore
110 * Returns an error code on error.
112 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
115 u32 swfw_mask = hw->phy.phy_semaphore_mask;
124 if (hw->mac.type >= ixgbe_mac_X550)
126 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
127 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
130 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
131 return IXGBE_ERR_SWFW_SYNC;
133 /* Device Address and write indication */
134 if (ixgbe_out_i2c_byte_ack(hw, addr))
136 /* Write bits 14:8 */
137 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
140 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
143 if (ixgbe_out_i2c_byte_ack(hw, csum))
145 /* Re-start condition */
147 /* Device Address and read indication */
148 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
151 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
154 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
157 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
160 if (ixgbe_clock_out_i2c_bit(hw, false))
164 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
165 *val = (high_bits << 8) | low_bits;
169 ixgbe_i2c_bus_clear(hw);
171 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
173 if (retry < max_retry)
174 DEBUGOUT("I2C byte read combined error - Retrying.\n");
176 DEBUGOUT("I2C byte read combined error.\n");
177 } while (retry < max_retry);
179 return IXGBE_ERR_I2C;
183 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
184 * @hw: pointer to the hardware structure
185 * @addr: I2C bus address to write to
186 * @reg: I2C device register to write to
187 * @val: value to write
188 * @lock: true if to take and release semaphore
190 * Returns an error code on error.
192 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
195 u32 swfw_mask = hw->phy.phy_semaphore_mask;
201 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
202 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
203 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
204 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
207 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
208 return IXGBE_ERR_SWFW_SYNC;
210 /* Device Address and write indication */
211 if (ixgbe_out_i2c_byte_ack(hw, addr))
213 /* Write bits 14:8 */
214 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
217 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
219 /* Write data 15:8 */
220 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
223 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
226 if (ixgbe_out_i2c_byte_ack(hw, csum))
230 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
234 ixgbe_i2c_bus_clear(hw);
236 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
238 if (retry < max_retry)
239 DEBUGOUT("I2C byte write combined error - Retrying.\n");
241 DEBUGOUT("I2C byte write combined error.\n");
242 } while (retry < max_retry);
244 return IXGBE_ERR_I2C;
248 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
249 * @hw: pointer to the hardware structure
251 * Initialize the function pointers.
253 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
255 struct ixgbe_phy_info *phy = &hw->phy;
257 DEBUGFUNC("ixgbe_init_phy_ops_generic");
260 phy->ops.identify = ixgbe_identify_phy_generic;
261 phy->ops.reset = ixgbe_reset_phy_generic;
262 phy->ops.read_reg = ixgbe_read_phy_reg_generic;
263 phy->ops.write_reg = ixgbe_write_phy_reg_generic;
264 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
265 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
266 phy->ops.setup_link = ixgbe_setup_phy_link_generic;
267 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
268 phy->ops.check_link = NULL;
269 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
270 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
271 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
272 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
273 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
274 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
275 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
276 phy->ops.identify_sfp = ixgbe_identify_module_generic;
277 phy->sfp_type = ixgbe_sfp_type_unknown;
278 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
279 phy->ops.write_i2c_byte_unlocked =
280 ixgbe_write_i2c_byte_generic_unlocked;
281 phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
282 return IXGBE_SUCCESS;
286 * ixgbe_probe_phy - Probe a single address for a PHY
287 * @hw: pointer to hardware structure
288 * @phy_addr: PHY address to probe
290 * Returns true if PHY found
292 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
296 if (!ixgbe_validate_phy_addr(hw, phy_addr))
299 if (ixgbe_get_phy_id(hw))
302 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
304 if (hw->phy.type == ixgbe_phy_unknown) {
305 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
306 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
308 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
309 IXGBE_MDIO_PHY_1000BASET_ABILITY))
310 hw->phy.type = ixgbe_phy_cu_unknown;
312 hw->phy.type = ixgbe_phy_generic;
319 * ixgbe_identify_phy_generic - Get physical layer module
320 * @hw: pointer to hardware structure
322 * Determines the physical layer module found on the current adapter.
324 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
326 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
329 DEBUGFUNC("ixgbe_identify_phy_generic");
331 if (!hw->phy.phy_semaphore_mask) {
333 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
335 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
338 if (hw->phy.type != ixgbe_phy_unknown)
339 return IXGBE_SUCCESS;
341 if (hw->phy.nw_mng_if_sel) {
342 phy_addr = (hw->phy.nw_mng_if_sel &
343 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
344 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
345 if (ixgbe_probe_phy(hw, phy_addr))
346 return IXGBE_SUCCESS;
348 return IXGBE_ERR_PHY_ADDR_INVALID;
351 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
352 if (ixgbe_probe_phy(hw, phy_addr)) {
353 status = IXGBE_SUCCESS;
358 /* Certain media types do not have a phy so an address will not
359 * be found and the code will take this path. Caller has to
360 * decide if it is an error or not.
362 if (status != IXGBE_SUCCESS)
369 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
370 * @hw: pointer to the hardware structure
372 * This function checks the MMNGC.MNG_VETO bit to see if there are
373 * any constraints on link from manageability. For MAC's that don't
374 * have this bit just return faluse since the link can not be blocked
377 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
381 DEBUGFUNC("ixgbe_check_reset_blocked");
383 /* If we don't have this bit, it can't be blocking */
384 if (hw->mac.type == ixgbe_mac_82598EB)
387 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
388 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
389 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
390 "MNG_VETO bit detected.\n");
398 * ixgbe_validate_phy_addr - Determines phy address is valid
399 * @hw: pointer to hardware structure
402 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
407 DEBUGFUNC("ixgbe_validate_phy_addr");
409 hw->phy.addr = phy_addr;
410 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
411 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
413 if (phy_id != 0xFFFF && phy_id != 0x0)
420 * ixgbe_get_phy_id - Get the phy type
421 * @hw: pointer to hardware structure
424 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
430 DEBUGFUNC("ixgbe_get_phy_id");
432 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
433 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
436 if (status == IXGBE_SUCCESS) {
437 hw->phy.id = (u32)(phy_id_high << 16);
438 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
439 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
441 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
442 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
448 * ixgbe_get_phy_type_from_id - Get the phy type
449 * @phy_id: PHY ID information
452 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
454 enum ixgbe_phy_type phy_type;
456 DEBUGFUNC("ixgbe_get_phy_type_from_id");
460 phy_type = ixgbe_phy_tn;
466 phy_type = ixgbe_phy_aq;
469 phy_type = ixgbe_phy_qt;
472 phy_type = ixgbe_phy_nl;
476 phy_type = ixgbe_phy_x550em_ext_t;
478 case IXGBE_M88E1500_E_PHY_ID:
479 case IXGBE_M88E1543_E_PHY_ID:
480 phy_type = ixgbe_phy_m88;
483 phy_type = ixgbe_phy_unknown;
490 * ixgbe_reset_phy_generic - Performs a PHY reset
491 * @hw: pointer to hardware structure
493 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
497 s32 status = IXGBE_SUCCESS;
499 DEBUGFUNC("ixgbe_reset_phy_generic");
501 if (hw->phy.type == ixgbe_phy_unknown)
502 status = ixgbe_identify_phy_generic(hw);
504 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
507 /* Don't reset PHY if it's shut down due to overtemp. */
508 if (!hw->phy.reset_if_overtemp &&
509 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
512 /* Blocked by MNG FW so bail */
513 if (ixgbe_check_reset_blocked(hw))
517 * Perform soft PHY reset to the PHY_XS.
518 * This will cause a soft reset to the PHY
520 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
521 IXGBE_MDIO_PHY_XS_DEV_TYPE,
522 IXGBE_MDIO_PHY_XS_RESET);
525 * Poll for reset bit to self-clear indicating reset is complete.
526 * Some PHYs could take up to 3 seconds to complete and need about
527 * 1.7 usec delay after the reset is complete.
529 for (i = 0; i < 30; i++) {
531 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
532 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
533 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
539 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
540 status = IXGBE_ERR_RESET_FAILED;
541 ERROR_REPORT1(IXGBE_ERROR_POLLING,
542 "PHY reset polling failed to complete.\n");
550 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
552 * @hw: pointer to hardware structure
553 * @reg_addr: 32 bit address of PHY register to read
554 * @phy_data: Pointer to read data from PHY register
556 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
559 u32 i, data, command;
561 /* Setup and write the address cycle command */
562 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
563 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
564 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
565 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
567 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
570 * Check every 10 usec to see if the address cycle completed.
571 * The MDI Command bit will clear when the operation is
574 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
577 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
578 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
583 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
584 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
585 return IXGBE_ERR_PHY;
589 * Address cycle complete, setup and write the read
592 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
593 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
594 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
595 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
597 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
600 * Check every 10 usec to see if the address cycle
601 * completed. The MDI Command bit will clear when the
602 * operation is complete
604 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
607 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
608 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
612 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
613 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
614 return IXGBE_ERR_PHY;
618 * Read operation is complete. Get the data
621 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
622 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
623 *phy_data = (u16)(data);
625 return IXGBE_SUCCESS;
629 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
630 * using the SWFW lock - this function is needed in most cases
631 * @hw: pointer to hardware structure
632 * @reg_addr: 32 bit address of PHY register to read
633 * @phy_data: Pointer to read data from PHY register
635 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
636 u32 device_type, u16 *phy_data)
639 u32 gssr = hw->phy.phy_semaphore_mask;
641 DEBUGFUNC("ixgbe_read_phy_reg_generic");
643 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
644 return IXGBE_ERR_SWFW_SYNC;
646 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
648 hw->mac.ops.release_swfw_sync(hw, gssr);
654 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
656 * @hw: pointer to hardware structure
657 * @reg_addr: 32 bit PHY register to write
658 * @device_type: 5 bit device type
659 * @phy_data: Data to write to the PHY register
661 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
662 u32 device_type, u16 phy_data)
666 /* Put the data in the MDI single read and write data register*/
667 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
669 /* Setup and write the address cycle command */
670 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
671 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
672 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
673 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
675 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
678 * Check every 10 usec to see if the address cycle completed.
679 * The MDI Command bit will clear when the operation is
682 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
685 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
686 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
690 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
691 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
692 return IXGBE_ERR_PHY;
696 * Address cycle complete, setup and write the write
699 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
700 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
701 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
702 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
704 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
707 * Check every 10 usec to see if the address cycle
708 * completed. The MDI Command bit will clear when the
709 * operation is complete
711 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
714 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
715 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
719 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
720 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
721 return IXGBE_ERR_PHY;
724 return IXGBE_SUCCESS;
728 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
729 * using SWFW lock- this function is needed in most cases
730 * @hw: pointer to hardware structure
731 * @reg_addr: 32 bit PHY register to write
732 * @device_type: 5 bit device type
733 * @phy_data: Data to write to the PHY register
735 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
736 u32 device_type, u16 phy_data)
739 u32 gssr = hw->phy.phy_semaphore_mask;
741 DEBUGFUNC("ixgbe_write_phy_reg_generic");
743 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
744 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
746 hw->mac.ops.release_swfw_sync(hw, gssr);
748 status = IXGBE_ERR_SWFW_SYNC;
755 * ixgbe_setup_phy_link_generic - Set and restart auto-neg
756 * @hw: pointer to hardware structure
758 * Restart auto-negotiation and PHY and waits for completion.
760 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
762 s32 status = IXGBE_SUCCESS;
763 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
764 bool autoneg = false;
765 ixgbe_link_speed speed;
767 DEBUGFUNC("ixgbe_setup_phy_link_generic");
769 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
771 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
772 /* Set or unset auto-negotiation 10G advertisement */
773 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
774 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
777 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
778 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
779 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
781 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
782 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
786 if (hw->mac.type == ixgbe_mac_X550) {
787 if (speed & IXGBE_LINK_SPEED_5GB_FULL) {
788 /* Set or unset auto-negotiation 5G advertisement */
789 hw->phy.ops.read_reg(hw,
790 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
791 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
794 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
795 if (hw->phy.autoneg_advertised &
796 IXGBE_LINK_SPEED_5GB_FULL)
797 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
799 hw->phy.ops.write_reg(hw,
800 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
801 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
805 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) {
806 /* Set or unset auto-negotiation 2.5G advertisement */
807 hw->phy.ops.read_reg(hw,
808 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
809 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
812 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
813 if (hw->phy.autoneg_advertised &
814 IXGBE_LINK_SPEED_2_5GB_FULL)
815 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
817 hw->phy.ops.write_reg(hw,
818 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
819 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
824 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
825 /* Set or unset auto-negotiation 1G advertisement */
826 hw->phy.ops.read_reg(hw,
827 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
828 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
831 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
832 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
833 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
835 hw->phy.ops.write_reg(hw,
836 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
837 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
841 if (speed & IXGBE_LINK_SPEED_100_FULL) {
842 /* Set or unset auto-negotiation 100M advertisement */
843 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
844 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
847 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
848 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
849 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
850 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
852 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
853 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
857 /* Blocked by MNG FW so don't reset PHY */
858 if (ixgbe_check_reset_blocked(hw))
861 /* Restart PHY auto-negotiation. */
862 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
863 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
865 autoneg_reg |= IXGBE_MII_RESTART;
867 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
868 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
874 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
875 * @hw: pointer to hardware structure
876 * @speed: new link speed
878 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
879 ixgbe_link_speed speed,
880 bool autoneg_wait_to_complete)
882 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
884 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
887 * Clear autoneg_advertised and set new values based on input link
890 hw->phy.autoneg_advertised = 0;
892 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
893 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
895 if (speed & IXGBE_LINK_SPEED_5GB_FULL)
896 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
898 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
899 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
901 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
902 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
904 if (speed & IXGBE_LINK_SPEED_100_FULL)
905 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
907 if (speed & IXGBE_LINK_SPEED_10_FULL)
908 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
910 /* Setup link based on the new speed settings */
911 ixgbe_setup_phy_link(hw);
913 return IXGBE_SUCCESS;
917 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
918 * @hw: pointer to hardware structure
920 * Determines the supported link capabilities by reading the PHY auto
921 * negotiation register.
923 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
928 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
929 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
934 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
935 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
936 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
937 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
938 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
939 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
941 switch (hw->mac.type) {
943 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
944 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
946 case ixgbe_mac_X550EM_x:
947 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
957 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
958 * @hw: pointer to hardware structure
959 * @speed: pointer to link speed
960 * @autoneg: boolean auto-negotiation value
962 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
963 ixgbe_link_speed *speed,
966 s32 status = IXGBE_SUCCESS;
968 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
971 if (!hw->phy.speeds_supported)
972 status = ixgbe_get_copper_speeds_supported(hw);
974 *speed = hw->phy.speeds_supported;
979 * ixgbe_check_phy_link_tnx - Determine link and speed status
980 * @hw: pointer to hardware structure
982 * Reads the VS1 register to determine if link is up and the current speed for
985 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
988 s32 status = IXGBE_SUCCESS;
990 u32 max_time_out = 10;
995 DEBUGFUNC("ixgbe_check_phy_link_tnx");
997 /* Initialize speed and link to default case */
999 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1002 * Check current speed and link status of the PHY register.
1003 * This is a vendor specific register and may have to
1004 * be changed for other copper PHYs.
1006 for (time_out = 0; time_out < max_time_out; time_out++) {
1008 status = hw->phy.ops.read_reg(hw,
1009 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1010 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1012 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1013 phy_speed = phy_data &
1014 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1015 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1018 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1019 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1028 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1029 * @hw: pointer to hardware structure
1031 * Restart auto-negotiation and PHY and waits for completion.
1033 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1035 s32 status = IXGBE_SUCCESS;
1036 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1037 bool autoneg = false;
1038 ixgbe_link_speed speed;
1040 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1042 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1044 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1045 /* Set or unset auto-negotiation 10G advertisement */
1046 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1047 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1050 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1051 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1052 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1054 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1055 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1059 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1060 /* Set or unset auto-negotiation 1G advertisement */
1061 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1062 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1065 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1066 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1067 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1069 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1070 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1074 if (speed & IXGBE_LINK_SPEED_100_FULL) {
1075 /* Set or unset auto-negotiation 100M advertisement */
1076 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1077 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1080 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1081 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1082 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1084 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1085 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1089 /* Blocked by MNG FW so don't reset PHY */
1090 if (ixgbe_check_reset_blocked(hw))
1093 /* Restart PHY auto-negotiation. */
1094 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1095 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1097 autoneg_reg |= IXGBE_MII_RESTART;
1099 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1100 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1106 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1107 * @hw: pointer to hardware structure
1108 * @firmware_version: pointer to the PHY Firmware Version
1110 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1111 u16 *firmware_version)
1115 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1117 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1118 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1125 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1126 * @hw: pointer to hardware structure
1127 * @firmware_version: pointer to the PHY Firmware Version
1129 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1130 u16 *firmware_version)
1134 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1136 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1137 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1144 * ixgbe_reset_phy_nl - Performs a PHY reset
1145 * @hw: pointer to hardware structure
1147 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1149 u16 phy_offset, control, eword, edata, block_crc;
1150 bool end_data = false;
1151 u16 list_offset, data_offset;
1153 s32 ret_val = IXGBE_SUCCESS;
1156 DEBUGFUNC("ixgbe_reset_phy_nl");
1158 /* Blocked by MNG FW so bail */
1159 if (ixgbe_check_reset_blocked(hw))
1162 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1163 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1165 /* reset the PHY and poll for completion */
1166 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1167 IXGBE_MDIO_PHY_XS_DEV_TYPE,
1168 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1170 for (i = 0; i < 100; i++) {
1171 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1172 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1173 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1178 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1179 DEBUGOUT("PHY reset did not complete.\n");
1180 ret_val = IXGBE_ERR_PHY;
1184 /* Get init offsets */
1185 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1187 if (ret_val != IXGBE_SUCCESS)
1190 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1194 * Read control word from PHY init contents offset
1196 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1199 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1200 IXGBE_CONTROL_SHIFT_NL;
1201 edata = eword & IXGBE_DATA_MASK_NL;
1203 case IXGBE_DELAY_NL:
1205 DEBUGOUT1("DELAY: %d MS\n", edata);
1209 DEBUGOUT("DATA:\n");
1211 ret_val = hw->eeprom.ops.read(hw, data_offset,
1216 for (i = 0; i < edata; i++) {
1217 ret_val = hw->eeprom.ops.read(hw, data_offset,
1221 hw->phy.ops.write_reg(hw, phy_offset,
1222 IXGBE_TWINAX_DEV, eword);
1223 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1229 case IXGBE_CONTROL_NL:
1231 DEBUGOUT("CONTROL:\n");
1232 if (edata == IXGBE_CONTROL_EOL_NL) {
1235 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1238 DEBUGOUT("Bad control value\n");
1239 ret_val = IXGBE_ERR_PHY;
1244 DEBUGOUT("Bad control type\n");
1245 ret_val = IXGBE_ERR_PHY;
1254 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1255 "eeprom read at offset %d failed", data_offset);
1256 return IXGBE_ERR_PHY;
1260 * ixgbe_identify_module_generic - Identifies module type
1261 * @hw: pointer to hardware structure
1263 * Determines HW type and calls appropriate function.
1265 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1267 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1269 DEBUGFUNC("ixgbe_identify_module_generic");
1271 switch (hw->mac.ops.get_media_type(hw)) {
1272 case ixgbe_media_type_fiber:
1273 status = ixgbe_identify_sfp_module_generic(hw);
1276 case ixgbe_media_type_fiber_qsfp:
1277 status = ixgbe_identify_qsfp_module_generic(hw);
1281 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1282 status = IXGBE_ERR_SFP_NOT_PRESENT;
1290 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1291 * @hw: pointer to hardware structure
1293 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1295 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1297 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1299 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1301 u8 comp_codes_1g = 0;
1302 u8 comp_codes_10g = 0;
1303 u8 oui_bytes[3] = {0, 0, 0};
1306 u16 enforce_sfp = 0;
1308 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1310 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1311 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1312 status = IXGBE_ERR_SFP_NOT_PRESENT;
1316 /* LAN ID is needed for I2C access */
1317 hw->mac.ops.set_lan_id(hw);
1319 status = hw->phy.ops.read_i2c_eeprom(hw,
1320 IXGBE_SFF_IDENTIFIER,
1323 if (status != IXGBE_SUCCESS)
1324 goto err_read_i2c_eeprom;
1326 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1327 hw->phy.type = ixgbe_phy_sfp_unsupported;
1328 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1330 status = hw->phy.ops.read_i2c_eeprom(hw,
1331 IXGBE_SFF_1GBE_COMP_CODES,
1334 if (status != IXGBE_SUCCESS)
1335 goto err_read_i2c_eeprom;
1337 status = hw->phy.ops.read_i2c_eeprom(hw,
1338 IXGBE_SFF_10GBE_COMP_CODES,
1341 if (status != IXGBE_SUCCESS)
1342 goto err_read_i2c_eeprom;
1343 status = hw->phy.ops.read_i2c_eeprom(hw,
1344 IXGBE_SFF_CABLE_TECHNOLOGY,
1347 if (status != IXGBE_SUCCESS)
1348 goto err_read_i2c_eeprom;
1355 * 3 SFP_DA_CORE0 - 82599-specific
1356 * 4 SFP_DA_CORE1 - 82599-specific
1357 * 5 SFP_SR/LR_CORE0 - 82599-specific
1358 * 6 SFP_SR/LR_CORE1 - 82599-specific
1359 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1360 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1361 * 9 SFP_1g_cu_CORE0 - 82599-specific
1362 * 10 SFP_1g_cu_CORE1 - 82599-specific
1363 * 11 SFP_1g_sx_CORE0 - 82599-specific
1364 * 12 SFP_1g_sx_CORE1 - 82599-specific
1366 if (hw->mac.type == ixgbe_mac_82598EB) {
1367 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1368 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1369 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1370 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1371 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1372 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1374 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1376 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1377 if (hw->bus.lan_id == 0)
1379 ixgbe_sfp_type_da_cu_core0;
1382 ixgbe_sfp_type_da_cu_core1;
1383 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1384 hw->phy.ops.read_i2c_eeprom(
1385 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1388 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1389 if (hw->bus.lan_id == 0)
1391 ixgbe_sfp_type_da_act_lmt_core0;
1394 ixgbe_sfp_type_da_act_lmt_core1;
1397 ixgbe_sfp_type_unknown;
1399 } else if (comp_codes_10g &
1400 (IXGBE_SFF_10GBASESR_CAPABLE |
1401 IXGBE_SFF_10GBASELR_CAPABLE)) {
1402 if (hw->bus.lan_id == 0)
1404 ixgbe_sfp_type_srlr_core0;
1407 ixgbe_sfp_type_srlr_core1;
1408 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1409 if (hw->bus.lan_id == 0)
1411 ixgbe_sfp_type_1g_cu_core0;
1414 ixgbe_sfp_type_1g_cu_core1;
1415 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1416 if (hw->bus.lan_id == 0)
1418 ixgbe_sfp_type_1g_sx_core0;
1421 ixgbe_sfp_type_1g_sx_core1;
1422 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1423 if (hw->bus.lan_id == 0)
1425 ixgbe_sfp_type_1g_lx_core0;
1428 ixgbe_sfp_type_1g_lx_core1;
1430 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1434 if (hw->phy.sfp_type != stored_sfp_type)
1435 hw->phy.sfp_setup_needed = true;
1437 /* Determine if the SFP+ PHY is dual speed or not. */
1438 hw->phy.multispeed_fiber = false;
1439 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1440 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1441 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1442 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1443 hw->phy.multispeed_fiber = true;
1445 /* Determine PHY vendor */
1446 if (hw->phy.type != ixgbe_phy_nl) {
1447 hw->phy.id = identifier;
1448 status = hw->phy.ops.read_i2c_eeprom(hw,
1449 IXGBE_SFF_VENDOR_OUI_BYTE0,
1452 if (status != IXGBE_SUCCESS)
1453 goto err_read_i2c_eeprom;
1455 status = hw->phy.ops.read_i2c_eeprom(hw,
1456 IXGBE_SFF_VENDOR_OUI_BYTE1,
1459 if (status != IXGBE_SUCCESS)
1460 goto err_read_i2c_eeprom;
1462 status = hw->phy.ops.read_i2c_eeprom(hw,
1463 IXGBE_SFF_VENDOR_OUI_BYTE2,
1466 if (status != IXGBE_SUCCESS)
1467 goto err_read_i2c_eeprom;
1470 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1471 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1472 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1474 switch (vendor_oui) {
1475 case IXGBE_SFF_VENDOR_OUI_TYCO:
1476 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1478 ixgbe_phy_sfp_passive_tyco;
1480 case IXGBE_SFF_VENDOR_OUI_FTL:
1481 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1482 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1484 hw->phy.type = ixgbe_phy_sfp_ftl;
1486 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1487 hw->phy.type = ixgbe_phy_sfp_avago;
1489 case IXGBE_SFF_VENDOR_OUI_INTEL:
1490 hw->phy.type = ixgbe_phy_sfp_intel;
1493 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1495 ixgbe_phy_sfp_passive_unknown;
1496 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1498 ixgbe_phy_sfp_active_unknown;
1500 hw->phy.type = ixgbe_phy_sfp_unknown;
1505 /* Allow any DA cable vendor */
1506 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1507 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1508 status = IXGBE_SUCCESS;
1512 /* Verify supported 1G SFP modules */
1513 if (comp_codes_10g == 0 &&
1514 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1515 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1516 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1517 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1518 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1519 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1520 hw->phy.type = ixgbe_phy_sfp_unsupported;
1521 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1525 /* Anything else 82598-based is supported */
1526 if (hw->mac.type == ixgbe_mac_82598EB) {
1527 status = IXGBE_SUCCESS;
1531 ixgbe_get_device_caps(hw, &enforce_sfp);
1532 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1533 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1534 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1535 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1536 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1537 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1538 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1539 /* Make sure we're a supported PHY type */
1540 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1541 status = IXGBE_SUCCESS;
1543 if (hw->allow_unsupported_sfp == true) {
1544 EWARN(hw, "WARNING: Intel (R) Network "
1545 "Connections are quality tested "
1546 "using Intel (R) Ethernet Optics."
1547 " Using untested modules is not "
1548 "supported and may cause unstable"
1549 " operation or damage to the "
1550 "module or the adapter. Intel "
1551 "Corporation is not responsible "
1552 "for any harm caused by using "
1553 "untested modules.\n", status);
1554 status = IXGBE_SUCCESS;
1556 DEBUGOUT("SFP+ module not supported\n");
1558 ixgbe_phy_sfp_unsupported;
1559 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1563 status = IXGBE_SUCCESS;
1570 err_read_i2c_eeprom:
1571 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1572 if (hw->phy.type != ixgbe_phy_nl) {
1574 hw->phy.type = ixgbe_phy_unknown;
1576 return IXGBE_ERR_SFP_NOT_PRESENT;
1580 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1581 * @hw: pointer to hardware structure
1583 * Determines physical layer capabilities of the current SFP.
1585 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1587 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1588 u8 comp_codes_10g = 0;
1589 u8 comp_codes_1g = 0;
1591 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1593 hw->phy.ops.identify_sfp(hw);
1594 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1595 return physical_layer;
1597 switch (hw->phy.type) {
1598 case ixgbe_phy_sfp_passive_tyco:
1599 case ixgbe_phy_sfp_passive_unknown:
1600 case ixgbe_phy_qsfp_passive_unknown:
1601 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1603 case ixgbe_phy_sfp_ftl_active:
1604 case ixgbe_phy_sfp_active_unknown:
1605 case ixgbe_phy_qsfp_active_unknown:
1606 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1608 case ixgbe_phy_sfp_avago:
1609 case ixgbe_phy_sfp_ftl:
1610 case ixgbe_phy_sfp_intel:
1611 case ixgbe_phy_sfp_unknown:
1612 hw->phy.ops.read_i2c_eeprom(hw,
1613 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1614 hw->phy.ops.read_i2c_eeprom(hw,
1615 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1616 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1617 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1618 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1619 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1620 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1621 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1622 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1623 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1625 case ixgbe_phy_qsfp_intel:
1626 case ixgbe_phy_qsfp_unknown:
1627 hw->phy.ops.read_i2c_eeprom(hw,
1628 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1629 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1630 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1631 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1632 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1638 return physical_layer;
1642 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1643 * @hw: pointer to hardware structure
1645 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1647 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1649 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1651 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1653 u8 comp_codes_1g = 0;
1654 u8 comp_codes_10g = 0;
1655 u8 oui_bytes[3] = {0, 0, 0};
1656 u16 enforce_sfp = 0;
1658 u8 cable_length = 0;
1660 bool active_cable = false;
1662 DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1664 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1665 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1666 status = IXGBE_ERR_SFP_NOT_PRESENT;
1670 /* LAN ID is needed for I2C access */
1671 hw->mac.ops.set_lan_id(hw);
1673 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1676 if (status != IXGBE_SUCCESS)
1677 goto err_read_i2c_eeprom;
1679 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1680 hw->phy.type = ixgbe_phy_sfp_unsupported;
1681 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1685 hw->phy.id = identifier;
1687 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1690 if (status != IXGBE_SUCCESS)
1691 goto err_read_i2c_eeprom;
1693 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1696 if (status != IXGBE_SUCCESS)
1697 goto err_read_i2c_eeprom;
1699 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1700 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1701 if (hw->bus.lan_id == 0)
1702 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1704 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1705 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1706 IXGBE_SFF_10GBASELR_CAPABLE)) {
1707 if (hw->bus.lan_id == 0)
1708 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1710 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1712 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1713 active_cable = true;
1715 if (!active_cable) {
1716 /* check for active DA cables that pre-date
1718 hw->phy.ops.read_i2c_eeprom(hw,
1719 IXGBE_SFF_QSFP_CONNECTOR,
1722 hw->phy.ops.read_i2c_eeprom(hw,
1723 IXGBE_SFF_QSFP_CABLE_LENGTH,
1726 hw->phy.ops.read_i2c_eeprom(hw,
1727 IXGBE_SFF_QSFP_DEVICE_TECH,
1731 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1732 (cable_length > 0) &&
1733 ((device_tech >> 4) ==
1734 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1735 active_cable = true;
1739 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1740 if (hw->bus.lan_id == 0)
1742 ixgbe_sfp_type_da_act_lmt_core0;
1745 ixgbe_sfp_type_da_act_lmt_core1;
1747 /* unsupported module type */
1748 hw->phy.type = ixgbe_phy_sfp_unsupported;
1749 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1754 if (hw->phy.sfp_type != stored_sfp_type)
1755 hw->phy.sfp_setup_needed = true;
1757 /* Determine if the QSFP+ PHY is dual speed or not. */
1758 hw->phy.multispeed_fiber = false;
1759 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1760 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1761 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1762 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1763 hw->phy.multispeed_fiber = true;
1765 /* Determine PHY vendor for optical modules */
1766 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1767 IXGBE_SFF_10GBASELR_CAPABLE)) {
1768 status = hw->phy.ops.read_i2c_eeprom(hw,
1769 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1772 if (status != IXGBE_SUCCESS)
1773 goto err_read_i2c_eeprom;
1775 status = hw->phy.ops.read_i2c_eeprom(hw,
1776 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1779 if (status != IXGBE_SUCCESS)
1780 goto err_read_i2c_eeprom;
1782 status = hw->phy.ops.read_i2c_eeprom(hw,
1783 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1786 if (status != IXGBE_SUCCESS)
1787 goto err_read_i2c_eeprom;
1790 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1791 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1792 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1794 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1795 hw->phy.type = ixgbe_phy_qsfp_intel;
1797 hw->phy.type = ixgbe_phy_qsfp_unknown;
1799 ixgbe_get_device_caps(hw, &enforce_sfp);
1800 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1801 /* Make sure we're a supported PHY type */
1802 if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1803 status = IXGBE_SUCCESS;
1805 if (hw->allow_unsupported_sfp == true) {
1806 EWARN(hw, "WARNING: Intel (R) Network "
1807 "Connections are quality tested "
1808 "using Intel (R) Ethernet Optics."
1809 " Using untested modules is not "
1810 "supported and may cause unstable"
1811 " operation or damage to the "
1812 "module or the adapter. Intel "
1813 "Corporation is not responsible "
1814 "for any harm caused by using "
1815 "untested modules.\n", status);
1816 status = IXGBE_SUCCESS;
1818 DEBUGOUT("QSFP module not supported\n");
1820 ixgbe_phy_sfp_unsupported;
1821 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1825 status = IXGBE_SUCCESS;
1832 err_read_i2c_eeprom:
1833 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1835 hw->phy.type = ixgbe_phy_unknown;
1837 return IXGBE_ERR_SFP_NOT_PRESENT;
1842 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1843 * @hw: pointer to hardware structure
1844 * @list_offset: offset to the SFP ID list
1845 * @data_offset: offset to the SFP data block
1847 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1848 * so it returns the offsets to the phy init sequence block.
1850 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1855 u16 sfp_type = hw->phy.sfp_type;
1857 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1859 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1860 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1862 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1863 return IXGBE_ERR_SFP_NOT_PRESENT;
1865 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1866 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1867 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1870 * Limiting active cables and 1G Phys must be initialized as
1873 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1874 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1875 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1876 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1877 sfp_type = ixgbe_sfp_type_srlr_core0;
1878 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1879 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1880 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1881 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1882 sfp_type = ixgbe_sfp_type_srlr_core1;
1884 /* Read offset to PHY init contents */
1885 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1886 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1887 "eeprom read at offset %d failed",
1888 IXGBE_PHY_INIT_OFFSET_NL);
1889 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1892 if ((!*list_offset) || (*list_offset == 0xFFFF))
1893 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1895 /* Shift offset to first ID word */
1899 * Find the matching SFP ID in the EEPROM
1900 * and program the init sequence
1902 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1905 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1906 if (sfp_id == sfp_type) {
1908 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1910 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1911 DEBUGOUT("SFP+ module not supported\n");
1912 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1917 (*list_offset) += 2;
1918 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1923 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1924 DEBUGOUT("No matching SFP+ module found\n");
1925 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1928 return IXGBE_SUCCESS;
1931 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1932 "eeprom read at offset %d failed", *list_offset);
1933 return IXGBE_ERR_PHY;
1937 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1938 * @hw: pointer to hardware structure
1939 * @byte_offset: EEPROM byte offset to read
1940 * @eeprom_data: value read
1942 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1944 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1947 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1949 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1950 IXGBE_I2C_EEPROM_DEV_ADDR,
1955 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1956 * @hw: pointer to hardware structure
1957 * @byte_offset: byte offset at address 0xA2
1958 * @eeprom_data: value read
1960 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1962 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1965 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1966 IXGBE_I2C_EEPROM_DEV_ADDR2,
1971 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1972 * @hw: pointer to hardware structure
1973 * @byte_offset: EEPROM byte offset to write
1974 * @eeprom_data: value to write
1976 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1978 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1981 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1983 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1984 IXGBE_I2C_EEPROM_DEV_ADDR,
1989 * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1990 * @hw: pointer to hardware structure
1991 * @offset: eeprom offset to be read
1992 * @addr: I2C address to be read
1994 STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1996 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1997 offset == IXGBE_SFF_IDENTIFIER &&
1998 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2004 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
2005 * @hw: pointer to hardware structure
2006 * @byte_offset: byte offset to read
2008 * @lock: true if to take and release semaphore
2010 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2011 * a specified device address.
2013 STATIC s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2014 u8 dev_addr, u8 *data, bool lock)
2019 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2023 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2025 if (hw->mac.type >= ixgbe_mac_X550)
2027 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2028 max_retry = IXGBE_SFP_DETECT_RETRIES;
2031 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2032 return IXGBE_ERR_SWFW_SYNC;
2034 ixgbe_i2c_start(hw);
2036 /* Device Address and write indication */
2037 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2038 if (status != IXGBE_SUCCESS)
2041 status = ixgbe_get_i2c_ack(hw);
2042 if (status != IXGBE_SUCCESS)
2045 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2046 if (status != IXGBE_SUCCESS)
2049 status = ixgbe_get_i2c_ack(hw);
2050 if (status != IXGBE_SUCCESS)
2053 ixgbe_i2c_start(hw);
2055 /* Device Address and read indication */
2056 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2057 if (status != IXGBE_SUCCESS)
2060 status = ixgbe_get_i2c_ack(hw);
2061 if (status != IXGBE_SUCCESS)
2064 status = ixgbe_clock_in_i2c_byte(hw, data);
2065 if (status != IXGBE_SUCCESS)
2068 status = ixgbe_clock_out_i2c_bit(hw, nack);
2069 if (status != IXGBE_SUCCESS)
2074 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2075 return IXGBE_SUCCESS;
2078 ixgbe_i2c_bus_clear(hw);
2080 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2084 if (retry < max_retry)
2085 DEBUGOUT("I2C byte read error - Retrying.\n");
2087 DEBUGOUT("I2C byte read error.\n");
2089 } while (retry < max_retry);
2095 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2096 * @hw: pointer to hardware structure
2097 * @byte_offset: byte offset to read
2100 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2101 * a specified device address.
2103 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2104 u8 dev_addr, u8 *data)
2106 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2111 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2112 * @hw: pointer to hardware structure
2113 * @byte_offset: byte offset to read
2116 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2117 * a specified device address.
2119 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2120 u8 dev_addr, u8 *data)
2122 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2127 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2128 * @hw: pointer to hardware structure
2129 * @byte_offset: byte offset to write
2130 * @data: value to write
2131 * @lock: true if to take and release semaphore
2133 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2134 * a specified device address.
2136 STATIC s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2137 u8 dev_addr, u8 data, bool lock)
2142 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2144 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2146 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2148 return IXGBE_ERR_SWFW_SYNC;
2151 ixgbe_i2c_start(hw);
2153 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2154 if (status != IXGBE_SUCCESS)
2157 status = ixgbe_get_i2c_ack(hw);
2158 if (status != IXGBE_SUCCESS)
2161 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2162 if (status != IXGBE_SUCCESS)
2165 status = ixgbe_get_i2c_ack(hw);
2166 if (status != IXGBE_SUCCESS)
2169 status = ixgbe_clock_out_i2c_byte(hw, data);
2170 if (status != IXGBE_SUCCESS)
2173 status = ixgbe_get_i2c_ack(hw);
2174 if (status != IXGBE_SUCCESS)
2179 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2180 return IXGBE_SUCCESS;
2183 ixgbe_i2c_bus_clear(hw);
2185 if (retry < max_retry)
2186 DEBUGOUT("I2C byte write error - Retrying.\n");
2188 DEBUGOUT("I2C byte write error.\n");
2189 } while (retry < max_retry);
2192 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2198 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2199 * @hw: pointer to hardware structure
2200 * @byte_offset: byte offset to write
2201 * @data: value to write
2203 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2204 * a specified device address.
2206 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2207 u8 dev_addr, u8 data)
2209 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2214 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2215 * @hw: pointer to hardware structure
2216 * @byte_offset: byte offset to write
2217 * @data: value to write
2219 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2220 * a specified device address.
2222 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2223 u8 dev_addr, u8 data)
2225 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2230 * ixgbe_i2c_start - Sets I2C start condition
2231 * @hw: pointer to hardware structure
2233 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2234 * Set bit-bang mode on X550 hardware.
2236 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2238 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2240 DEBUGFUNC("ixgbe_i2c_start");
2242 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2244 /* Start condition must begin with data and clock high */
2245 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2246 ixgbe_raise_i2c_clk(hw, &i2cctl);
2248 /* Setup time for start condition (4.7us) */
2249 usec_delay(IXGBE_I2C_T_SU_STA);
2251 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2253 /* Hold time for start condition (4us) */
2254 usec_delay(IXGBE_I2C_T_HD_STA);
2256 ixgbe_lower_i2c_clk(hw, &i2cctl);
2258 /* Minimum low period of clock is 4.7 us */
2259 usec_delay(IXGBE_I2C_T_LOW);
2264 * ixgbe_i2c_stop - Sets I2C stop condition
2265 * @hw: pointer to hardware structure
2267 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2268 * Disables bit-bang mode and negates data output enable on X550
2271 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2273 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2274 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2275 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2276 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2278 DEBUGFUNC("ixgbe_i2c_stop");
2280 /* Stop condition must begin with data low and clock high */
2281 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2282 ixgbe_raise_i2c_clk(hw, &i2cctl);
2284 /* Setup time for stop condition (4us) */
2285 usec_delay(IXGBE_I2C_T_SU_STO);
2287 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2289 /* bus free time between stop and start (4.7us)*/
2290 usec_delay(IXGBE_I2C_T_BUF);
2292 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2293 i2cctl &= ~bb_en_bit;
2294 i2cctl |= data_oe_bit | clk_oe_bit;
2295 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2296 IXGBE_WRITE_FLUSH(hw);
2301 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2302 * @hw: pointer to hardware structure
2303 * @data: data byte to clock in
2305 * Clocks in one byte data via I2C data/clock
2307 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2312 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2315 for (i = 7; i >= 0; i--) {
2316 ixgbe_clock_in_i2c_bit(hw, &bit);
2320 return IXGBE_SUCCESS;
2324 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2325 * @hw: pointer to hardware structure
2326 * @data: data byte clocked out
2328 * Clocks out one byte data via I2C data/clock
2330 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2332 s32 status = IXGBE_SUCCESS;
2337 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2339 for (i = 7; i >= 0; i--) {
2340 bit = (data >> i) & 0x1;
2341 status = ixgbe_clock_out_i2c_bit(hw, bit);
2343 if (status != IXGBE_SUCCESS)
2347 /* Release SDA line (set high) */
2348 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2349 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2350 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2351 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2352 IXGBE_WRITE_FLUSH(hw);
2358 * ixgbe_get_i2c_ack - Polls for I2C ACK
2359 * @hw: pointer to hardware structure
2361 * Clocks in/out one bit via I2C data/clock
2363 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2365 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2366 s32 status = IXGBE_SUCCESS;
2368 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2372 DEBUGFUNC("ixgbe_get_i2c_ack");
2375 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2376 i2cctl |= data_oe_bit;
2377 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2378 IXGBE_WRITE_FLUSH(hw);
2380 ixgbe_raise_i2c_clk(hw, &i2cctl);
2382 /* Minimum high period of clock is 4us */
2383 usec_delay(IXGBE_I2C_T_HIGH);
2385 /* Poll for ACK. Note that ACK in I2C spec is
2386 * transition from 1 to 0 */
2387 for (i = 0; i < timeout; i++) {
2388 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2389 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2397 DEBUGOUT("I2C ack was not received.\n");
2398 status = IXGBE_ERR_I2C;
2401 ixgbe_lower_i2c_clk(hw, &i2cctl);
2403 /* Minimum low period of clock is 4.7 us */
2404 usec_delay(IXGBE_I2C_T_LOW);
2410 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2411 * @hw: pointer to hardware structure
2412 * @data: read data value
2414 * Clocks in one bit via I2C data/clock
2416 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2418 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2419 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2421 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2424 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2425 i2cctl |= data_oe_bit;
2426 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2427 IXGBE_WRITE_FLUSH(hw);
2429 ixgbe_raise_i2c_clk(hw, &i2cctl);
2431 /* Minimum high period of clock is 4us */
2432 usec_delay(IXGBE_I2C_T_HIGH);
2434 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2435 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2437 ixgbe_lower_i2c_clk(hw, &i2cctl);
2439 /* Minimum low period of clock is 4.7 us */
2440 usec_delay(IXGBE_I2C_T_LOW);
2442 return IXGBE_SUCCESS;
2446 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2447 * @hw: pointer to hardware structure
2448 * @data: data value to write
2450 * Clocks out one bit via I2C data/clock
2452 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2455 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2457 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2459 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2460 if (status == IXGBE_SUCCESS) {
2461 ixgbe_raise_i2c_clk(hw, &i2cctl);
2463 /* Minimum high period of clock is 4us */
2464 usec_delay(IXGBE_I2C_T_HIGH);
2466 ixgbe_lower_i2c_clk(hw, &i2cctl);
2468 /* Minimum low period of clock is 4.7 us.
2469 * This also takes care of the data hold time.
2471 usec_delay(IXGBE_I2C_T_LOW);
2473 status = IXGBE_ERR_I2C;
2474 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2475 "I2C data was not set to %X\n", data);
2482 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2483 * @hw: pointer to hardware structure
2484 * @i2cctl: Current value of I2CCTL register
2486 * Raises the I2C clock line '0'->'1'
2487 * Negates the I2C clock output enable on X550 hardware.
2489 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2491 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2493 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2496 DEBUGFUNC("ixgbe_raise_i2c_clk");
2499 *i2cctl |= clk_oe_bit;
2500 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2503 for (i = 0; i < timeout; i++) {
2504 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2506 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2507 IXGBE_WRITE_FLUSH(hw);
2508 /* SCL rise time (1000ns) */
2509 usec_delay(IXGBE_I2C_T_RISE);
2511 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2512 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2518 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2519 * @hw: pointer to hardware structure
2520 * @i2cctl: Current value of I2CCTL register
2522 * Lowers the I2C clock line '1'->'0'
2523 * Asserts the I2C clock output enable on X550 hardware.
2525 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2527 DEBUGFUNC("ixgbe_lower_i2c_clk");
2529 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2530 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2532 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2533 IXGBE_WRITE_FLUSH(hw);
2535 /* SCL fall time (300ns) */
2536 usec_delay(IXGBE_I2C_T_FALL);
2540 * ixgbe_set_i2c_data - Sets the I2C data bit
2541 * @hw: pointer to hardware structure
2542 * @i2cctl: Current value of I2CCTL register
2543 * @data: I2C data value (0 or 1) to set
2545 * Sets the I2C data bit
2546 * Asserts the I2C data output enable on X550 hardware.
2548 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2550 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2551 s32 status = IXGBE_SUCCESS;
2553 DEBUGFUNC("ixgbe_set_i2c_data");
2556 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2558 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2559 *i2cctl &= ~data_oe_bit;
2561 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2562 IXGBE_WRITE_FLUSH(hw);
2564 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2565 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2567 if (!data) /* Can't verify data in this case */
2568 return IXGBE_SUCCESS;
2570 *i2cctl |= data_oe_bit;
2571 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2572 IXGBE_WRITE_FLUSH(hw);
2575 /* Verify data was set correctly */
2576 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2577 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2578 status = IXGBE_ERR_I2C;
2579 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2580 "Error - I2C data was not set to %X.\n",
2588 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2589 * @hw: pointer to hardware structure
2590 * @i2cctl: Current value of I2CCTL register
2592 * Returns the I2C data bit value
2593 * Negates the I2C data output enable on X550 hardware.
2595 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2597 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2600 DEBUGFUNC("ixgbe_get_i2c_data");
2603 *i2cctl |= data_oe_bit;
2604 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2605 IXGBE_WRITE_FLUSH(hw);
2606 usec_delay(IXGBE_I2C_T_FALL);
2609 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2618 * ixgbe_i2c_bus_clear - Clears the I2C bus
2619 * @hw: pointer to hardware structure
2621 * Clears the I2C bus by sending nine clock pulses.
2622 * Used when data line is stuck low.
2624 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2629 DEBUGFUNC("ixgbe_i2c_bus_clear");
2631 ixgbe_i2c_start(hw);
2632 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2634 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2636 for (i = 0; i < 9; i++) {
2637 ixgbe_raise_i2c_clk(hw, &i2cctl);
2639 /* Min high period of clock is 4us */
2640 usec_delay(IXGBE_I2C_T_HIGH);
2642 ixgbe_lower_i2c_clk(hw, &i2cctl);
2644 /* Min low period of clock is 4.7us*/
2645 usec_delay(IXGBE_I2C_T_LOW);
2648 ixgbe_i2c_start(hw);
2650 /* Put the i2c bus back to default state */
2655 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2656 * @hw: pointer to hardware structure
2658 * Checks if the LASI temp alarm status was triggered due to overtemp
2660 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2662 s32 status = IXGBE_SUCCESS;
2665 DEBUGFUNC("ixgbe_tn_check_overtemp");
2667 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2670 /* Check that the LASI temp alarm status was triggered */
2671 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2672 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2674 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2677 status = IXGBE_ERR_OVERTEMP;
2678 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2684 * ixgbe_set_copper_phy_power - Control power for copper phy
2685 * @hw: pointer to hardware structure
2686 * @on: true for on, false for off
2688 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2693 if (!on && ixgbe_mng_present(hw))
2696 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2697 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2703 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2705 if (ixgbe_check_reset_blocked(hw))
2707 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2710 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2711 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,