drivers/net/ixgbe/base/ixgbe_phy.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2020 Intel Corporation
   3  */
   4
   5 #include "ixgbe_api.h"
   6 #include "ixgbe_common.h"
   7 #include "ixgbe_phy.h"
   8
   9 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
  10 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  11 STATIC void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  12 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  13 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  14 STATIC void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  15 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  16 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  17 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  18 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  19 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
  20 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
  21                                           u8 *sff8472_data);
  22
  23 /**
  24  * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
  25  * @hw: pointer to the hardware structure
  26  * @byte: byte to send
  27  *
  28  * Returns an error code on error.
  29  */
  30 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
  31 {
  32         s32 status;
  33
  34         status = ixgbe_clock_out_i2c_byte(hw, byte);
  35         if (status)
  36                 return status;
  37         return ixgbe_get_i2c_ack(hw);
  38 }
  39
  40 /**
  41  * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
  42  * @hw: pointer to the hardware structure
  43  * @byte: pointer to a u8 to receive the byte
  44  *
  45  * Returns an error code on error.
  46  */
  47 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
  48 {
  49         ixgbe_clock_in_i2c_byte(hw, byte);
  50         /* ACK */
  51         return ixgbe_clock_out_i2c_bit(hw, false);
  52 }
  53
  54 /**
  55  * ixgbe_ones_comp_byte_add - Perform one's complement addition
  56  * @add1: addend 1
  57  * @add2: addend 2
  58  *
  59  * Returns one's complement 8-bit sum.
  60  */
  61 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
  62 {
  63         u16 sum = add1 + add2;
  64
  65         sum = (sum & 0xFF) + (sum >> 8);
  66         return sum & 0xFF;
  67 }
  68
  69 /**
  70  * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
  71  * @hw: pointer to the hardware structure
  72  * @addr: I2C bus address to read from
  73  * @reg: I2C device register to read from
  74  * @val: pointer to location to receive read value
  75  * @lock: true if to take and release semaphore
  76  *
  77  * Returns an error code on error.
  78  */
  79 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
  80                                         u16 *val, bool lock)
  81 {
  82         u32 swfw_mask = hw->phy.phy_semaphore_mask;
  83         int max_retry = 3;
  84         int retry = 0;
  85         u8 csum_byte;
  86         u8 high_bits;
  87         u8 low_bits;
  88         u8 reg_high;
  89         u8 csum;
  90
  91         reg_high = ((reg >> 7) & 0xFE) | 1;     /* Indicate read combined */
  92         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
  93         csum = ~csum;
  94         do {
  95                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
  96                         return IXGBE_ERR_SWFW_SYNC;
  97                 ixgbe_i2c_start(hw);
  98                 /* Device Address and write indication */
  99                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 100                         goto fail;
 101                 /* Write bits 14:8 */
 102                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 103                         goto fail;
 104                 /* Write bits 7:0 */
 105                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 106                         goto fail;
 107                 /* Write csum */
 108                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 109                         goto fail;
 110                 /* Re-start condition */
 111                 ixgbe_i2c_start(hw);
 112                 /* Device Address and read indication */
 113                 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
 114                         goto fail;
 115                 /* Get upper bits */
 116                 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
 117                         goto fail;
 118                 /* Get low bits */
 119                 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
 120                         goto fail;
 121                 /* Get csum */
 122                 ixgbe_clock_in_i2c_byte(hw, &csum_byte);
 123                 /* NACK */
 124                 if (ixgbe_clock_out_i2c_bit(hw, false))
 125                         goto fail;
 126                 ixgbe_i2c_stop(hw);
 127                 if (lock)
 128                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 129                 *val = (high_bits << 8) | low_bits;
 130                 return 0;
 131
 132 fail:
 133                 ixgbe_i2c_bus_clear(hw);
 134                 if (lock)
 135                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 136                 if (retry < max_retry)
 137                         DEBUGOUT("I2C byte read combined error - Retrying.\n");
 138                 else
 139                         DEBUGOUT("I2C byte read combined error.\n");
 140                 retry++;
 141         } while (retry <= max_retry);
 142
 143         return IXGBE_ERR_I2C;
 144 }
 145
 146 /**
 147  * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
 148  * @hw: pointer to the hardware structure
 149  * @addr: I2C bus address to write to
 150  * @reg: I2C device register to write to
 151  * @val: value to write
 152  * @lock: true if to take and release semaphore
 153  *
 154  * Returns an error code on error.
 155  */
 156 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
 157                                          u16 val, bool lock)
 158 {
 159         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 160         int max_retry = 1;
 161         int retry = 0;
 162         u8 reg_high;
 163         u8 csum;
 164
 165         reg_high = (reg >> 7) & 0xFE;   /* Indicate write combined */
 166         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 167         csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
 168         csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
 169         csum = ~csum;
 170         do {
 171                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 172                         return IXGBE_ERR_SWFW_SYNC;
 173                 ixgbe_i2c_start(hw);
 174                 /* Device Address and write indication */
 175                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 176                         goto fail;
 177                 /* Write bits 14:8 */
 178                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 179                         goto fail;
 180                 /* Write bits 7:0 */
 181                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 182                         goto fail;
 183                 /* Write data 15:8 */
 184                 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
 185                         goto fail;
 186                 /* Write data 7:0 */
 187                 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
 188                         goto fail;
 189                 /* Write csum */
 190                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 191                         goto fail;
 192                 ixgbe_i2c_stop(hw);
 193                 if (lock)
 194                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 195                 return 0;
 196
 197 fail:
 198                 ixgbe_i2c_bus_clear(hw);
 199                 if (lock)
 200                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 201                 if (retry < max_retry)
 202                         DEBUGOUT("I2C byte write combined error - Retrying.\n");
 203                 else
 204                         DEBUGOUT("I2C byte write combined error.\n");
 205                 retry++;
 206         } while (retry <= max_retry);
 207
 208         return IXGBE_ERR_I2C;
 209 }
 210
 211 /**
 212  * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
 213  * @hw: pointer to the hardware structure
 214  *
 215  * Initialize the function pointers.
 216  **/
 217 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
 218 {
 219         struct ixgbe_phy_info *phy = &hw->phy;
 220
 221         DEBUGFUNC("ixgbe_init_phy_ops_generic");
 222
 223         /* PHY */
 224         phy->ops.identify = ixgbe_identify_phy_generic;
 225         phy->ops.reset = ixgbe_reset_phy_generic;
 226         phy->ops.read_reg = ixgbe_read_phy_reg_generic;
 227         phy->ops.write_reg = ixgbe_write_phy_reg_generic;
 228         phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
 229         phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
 230         phy->ops.setup_link = ixgbe_setup_phy_link_generic;
 231         phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
 232         phy->ops.check_link = NULL;
 233         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
 234         phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
 235         phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
 236         phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
 237         phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
 238         phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
 239         phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
 240         phy->ops.identify_sfp = ixgbe_identify_module_generic;
 241         phy->sfp_type = ixgbe_sfp_type_unknown;
 242         phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
 243         phy->ops.write_i2c_byte_unlocked =
 244                                 ixgbe_write_i2c_byte_generic_unlocked;
 245         phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
 246         return IXGBE_SUCCESS;
 247 }
 248
 249 /**
 250  * ixgbe_probe_phy - Probe a single address for a PHY
 251  * @hw: pointer to hardware structure
 252  * @phy_addr: PHY address to probe
 253  *
 254  * Returns true if PHY found
 255  */
 256 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
 257 {
 258         u16 ext_ability = 0;
 259
 260         if (!ixgbe_validate_phy_addr(hw, phy_addr)) {
 261                 DEBUGOUT1("Unable to validate PHY address 0x%04X\n",
 262                         phy_addr);
 263                 return false;
 264         }
 265
 266         if (ixgbe_get_phy_id(hw))
 267                 return false;
 268
 269         hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
 270
 271         if (hw->phy.type == ixgbe_phy_unknown) {
 272                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
 273                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
 274                 if (ext_ability &
 275                     (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 276                      IXGBE_MDIO_PHY_1000BASET_ABILITY))
 277                         hw->phy.type = ixgbe_phy_cu_unknown;
 278                 else
 279                         hw->phy.type = ixgbe_phy_generic;
 280         }
 281
 282         return true;
 283 }
 284
 285 /**
 286  * ixgbe_identify_phy_generic - Get physical layer module
 287  * @hw: pointer to hardware structure
 288  *
 289  * Determines the physical layer module found on the current adapter.
 290  **/
 291 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
 292 {
 293         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 294         u16 phy_addr;
 295
 296         DEBUGFUNC("ixgbe_identify_phy_generic");
 297
 298         if (!hw->phy.phy_semaphore_mask) {
 299                 if (hw->bus.lan_id)
 300                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 301                 else
 302                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 303         }
 304
 305         if (hw->phy.type != ixgbe_phy_unknown)
 306                 return IXGBE_SUCCESS;
 307
 308         if (hw->phy.nw_mng_if_sel) {
 309                 phy_addr = (hw->phy.nw_mng_if_sel &
 310                             IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
 311                            IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
 312                 if (ixgbe_probe_phy(hw, phy_addr))
 313                         return IXGBE_SUCCESS;
 314                 else
 315                         return IXGBE_ERR_PHY_ADDR_INVALID;
 316         }
 317
 318         for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
 319                 if (ixgbe_probe_phy(hw, phy_addr)) {
 320                         status = IXGBE_SUCCESS;
 321                         break;
 322                 }
 323         }
 324
 325         /* Certain media types do not have a phy so an address will not
 326          * be found and the code will take this path.  Caller has to
 327          * decide if it is an error or not.
 328          */
 329         if (status != IXGBE_SUCCESS)
 330                 hw->phy.addr = 0;
 331
 332         return status;
 333 }
 334
 335 /**
 336  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 337  * @hw: pointer to the hardware structure
 338  *
 339  * This function checks the MMNGC.MNG_VETO bit to see if there are
 340  * any constraints on link from manageability.  For MAC's that don't
 341  * have this bit just return faluse since the link can not be blocked
 342  * via this method.
 343  **/
 344 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 345 {
 346         u32 mmngc;
 347
 348         DEBUGFUNC("ixgbe_check_reset_blocked");
 349
 350         /* If we don't have this bit, it can't be blocking */
 351         if (hw->mac.type == ixgbe_mac_82598EB)
 352                 return false;
 353
 354         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 355         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 356                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
 357                               "MNG_VETO bit detected.\n");
 358                 return true;
 359         }
 360
 361         return false;
 362 }
 363
 364 /**
 365  * ixgbe_validate_phy_addr - Determines phy address is valid
 366  * @hw: pointer to hardware structure
 367  * @phy_addr: PHY address
 368  *
 369  **/
 370 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 371 {
 372         u16 phy_id = 0;
 373         bool valid = false;
 374
 375         DEBUGFUNC("ixgbe_validate_phy_addr");
 376
 377         hw->phy.addr = phy_addr;
 378         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 379                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 380
 381         if (phy_id != 0xFFFF && phy_id != 0x0)
 382                 valid = true;
 383
 384         DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id);
 385
 386         return valid;
 387 }
 388
 389 /**
 390  * ixgbe_get_phy_id - Get the phy type
 391  * @hw: pointer to hardware structure
 392  *
 393  **/
 394 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 395 {
 396         u32 status;
 397         u16 phy_id_high = 0;
 398         u16 phy_id_low = 0;
 399
 400         DEBUGFUNC("ixgbe_get_phy_id");
 401
 402         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 403                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 404                                       &phy_id_high);
 405
 406         if (status == IXGBE_SUCCESS) {
 407                 hw->phy.id = (u32)(phy_id_high << 16);
 408                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 409                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 410                                               &phy_id_low);
 411                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 412                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 413         }
 414         DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n",
 415                   phy_id_high, phy_id_low);
 416
 417         return status;
 418 }
 419
 420 /**
 421  * ixgbe_get_phy_type_from_id - Get the phy type
 422  * @phy_id: PHY ID information
 423  *
 424  **/
 425 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 426 {
 427         enum ixgbe_phy_type phy_type;
 428
 429         DEBUGFUNC("ixgbe_get_phy_type_from_id");
 430
 431         switch (phy_id) {
 432         case TN1010_PHY_ID:
 433                 phy_type = ixgbe_phy_tn;
 434                 break;
 435         case X550_PHY_ID2:
 436         case X550_PHY_ID3:
 437         case X540_PHY_ID:
 438                 phy_type = ixgbe_phy_aq;
 439                 break;
 440         case QT2022_PHY_ID:
 441                 phy_type = ixgbe_phy_qt;
 442                 break;
 443         case ATH_PHY_ID:
 444                 phy_type = ixgbe_phy_nl;
 445                 break;
 446         case X557_PHY_ID:
 447         case X557_PHY_ID2:
 448                 phy_type = ixgbe_phy_x550em_ext_t;
 449                 break;
 450         case IXGBE_M88E1500_E_PHY_ID:
 451         case IXGBE_M88E1543_E_PHY_ID:
 452                 phy_type = ixgbe_phy_ext_1g_t;
 453                 break;
 454         default:
 455                 phy_type = ixgbe_phy_unknown;
 456                 break;
 457         }
 458         return phy_type;
 459 }
 460
 461 /**
 462  * ixgbe_reset_phy_generic - Performs a PHY reset
 463  * @hw: pointer to hardware structure
 464  **/
 465 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 466 {
 467         u32 i;
 468         u16 ctrl = 0;
 469         s32 status = IXGBE_SUCCESS;
 470
 471         DEBUGFUNC("ixgbe_reset_phy_generic");
 472
 473         if (hw->phy.type == ixgbe_phy_unknown)
 474                 status = ixgbe_identify_phy_generic(hw);
 475
 476         if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 477                 goto out;
 478
 479         /* Don't reset PHY if it's shut down due to overtemp. */
 480         if (!hw->phy.reset_if_overtemp &&
 481             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 482                 goto out;
 483
 484         /* Blocked by MNG FW so bail */
 485         if (ixgbe_check_reset_blocked(hw))
 486                 goto out;
 487
 488         /*
 489          * Perform soft PHY reset to the PHY_XS.
 490          * This will cause a soft reset to the PHY
 491          */
 492         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 493                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 494                               IXGBE_MDIO_PHY_XS_RESET);
 495
 496         /*
 497          * Poll for reset bit to self-clear indicating reset is complete.
 498          * Some PHYs could take up to 3 seconds to complete and need about
 499          * 1.7 usec delay after the reset is complete.
 500          */
 501         for (i = 0; i < 30; i++) {
 502                 msec_delay(100);
 503                 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
 504                         status = hw->phy.ops.read_reg(hw,
 505                                                   IXGBE_MDIO_TX_VENDOR_ALARMS_3,
 506                                                   IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 507                                                   &ctrl);
 508                         if (status != IXGBE_SUCCESS)
 509                                 return status;
 510
 511                         if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
 512                                 usec_delay(2);
 513                                 break;
 514                         }
 515                 } else {
 516                         status = hw->phy.ops.read_reg(hw,
 517                                                      IXGBE_MDIO_PHY_XS_CONTROL,
 518                                                      IXGBE_MDIO_PHY_XS_DEV_TYPE,
 519                                                      &ctrl);
 520                         if (status != IXGBE_SUCCESS)
 521                                 return status;
 522
 523                         if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 524                                 usec_delay(2);
 525                                 break;
 526                         }
 527                 }
 528         }
 529
 530         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 531                 status = IXGBE_ERR_RESET_FAILED;
 532                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 533                              "PHY reset polling failed to complete.\n");
 534         }
 535
 536 out:
 537         return status;
 538 }
 539
 540 /**
 541  * ixgbe_restart_auto_neg - Restart auto negotiation on the PHY
 542  * @hw: pointer to hardware structure
 543  **/
 544 void ixgbe_restart_auto_neg(struct ixgbe_hw *hw)
 545 {
 546         u16 autoneg_reg;
 547
 548         /* Check if PHY reset is blocked by MNG FW */
 549         if (ixgbe_check_reset_blocked(hw))
 550                 return;
 551
 552         /* Restart PHY auto-negotiation. */
 553         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 554                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 555         autoneg_reg |= IXGBE_MII_RESTART;
 556         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 557                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 558 }
 559
 560 /**
 561  * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 562  * the SWFW lock
 563  * @hw: pointer to hardware structure
 564  * @reg_addr: 32 bit address of PHY register to read
 565  * @device_type: 5 bit device type
 566  * @phy_data: Pointer to read data from PHY register
 567  **/
 568 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 569                            u16 *phy_data)
 570 {
 571         u32 i, data, command;
 572
 573         /* Setup and write the address cycle command */
 574         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 575                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 576                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 577                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 578
 579         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 580
 581         /*
 582          * Check every 10 usec to see if the address cycle completed.
 583          * The MDI Command bit will clear when the operation is
 584          * complete
 585          */
 586         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 587                 usec_delay(10);
 588
 589                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 590                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 591                         break;
 592         }
 593
 594
 595         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 596                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
 597                 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n");
 598                 return IXGBE_ERR_PHY;
 599         }
 600
 601         /*
 602          * Address cycle complete, setup and write the read
 603          * command
 604          */
 605         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 606                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 607                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 608                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 609
 610         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 611
 612         /*
 613          * Check every 10 usec to see if the address cycle
 614          * completed. The MDI Command bit will clear when the
 615          * operation is complete
 616          */
 617         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 618                 usec_delay(10);
 619
 620                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 621                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 622                         break;
 623         }
 624
 625         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 626                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
 627                 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n");
 628                 return IXGBE_ERR_PHY;
 629         }
 630
 631         /*
 632          * Read operation is complete.  Get the data
 633          * from MSRWD
 634          */
 635         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 636         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 637         *phy_data = (u16)(data);
 638
 639         return IXGBE_SUCCESS;
 640 }
 641
 642 /**
 643  * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 644  * using the SWFW lock - this function is needed in most cases
 645  * @hw: pointer to hardware structure
 646  * @reg_addr: 32 bit address of PHY register to read
 647  * @device_type: 5 bit device type
 648  * @phy_data: Pointer to read data from PHY register
 649  **/
 650 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 651                                u32 device_type, u16 *phy_data)
 652 {
 653         s32 status;
 654         u32 gssr = hw->phy.phy_semaphore_mask;
 655
 656         DEBUGFUNC("ixgbe_read_phy_reg_generic");
 657
 658         if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
 659                 return IXGBE_ERR_SWFW_SYNC;
 660
 661         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
 662
 663         hw->mac.ops.release_swfw_sync(hw, gssr);
 664
 665         return status;
 666 }
 667
 668 /**
 669  * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 670  * without SWFW lock
 671  * @hw: pointer to hardware structure
 672  * @reg_addr: 32 bit PHY register to write
 673  * @device_type: 5 bit device type
 674  * @phy_data: Data to write to the PHY register
 675  **/
 676 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 677                                 u32 device_type, u16 phy_data)
 678 {
 679         u32 i, command;
 680
 681         /* Put the data in the MDI single read and write data register*/
 682         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 683
 684         /* Setup and write the address cycle command */
 685         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 686                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 687                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 688                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 689
 690         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 691
 692         /*
 693          * Check every 10 usec to see if the address cycle completed.
 694          * The MDI Command bit will clear when the operation is
 695          * complete
 696          */
 697         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 698                 usec_delay(10);
 699
 700                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 701                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 702                         break;
 703         }
 704
 705         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 706                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
 707                 return IXGBE_ERR_PHY;
 708         }
 709
 710         /*
 711          * Address cycle complete, setup and write the write
 712          * command
 713          */
 714         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 715                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 716                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 717                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 718
 719         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 720
 721         /*
 722          * Check every 10 usec to see if the address cycle
 723          * completed. The MDI Command bit will clear when the
 724          * operation is complete
 725          */
 726         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 727                 usec_delay(10);
 728
 729                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 730                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 731                         break;
 732         }
 733
 734         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 735                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
 736                 return IXGBE_ERR_PHY;
 737         }
 738
 739         return IXGBE_SUCCESS;
 740 }
 741
 742 /**
 743  * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 744  * using SWFW lock- this function is needed in most cases
 745  * @hw: pointer to hardware structure
 746  * @reg_addr: 32 bit PHY register to write
 747  * @device_type: 5 bit device type
 748  * @phy_data: Data to write to the PHY register
 749  **/
 750 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 751                                 u32 device_type, u16 phy_data)
 752 {
 753         s32 status;
 754         u32 gssr = hw->phy.phy_semaphore_mask;
 755
 756         DEBUGFUNC("ixgbe_write_phy_reg_generic");
 757
 758         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 759                 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
 760                                                  phy_data);
 761                 hw->mac.ops.release_swfw_sync(hw, gssr);
 762         } else {
 763                 status = IXGBE_ERR_SWFW_SYNC;
 764         }
 765
 766         return status;
 767 }
 768
 769 /**
 770  * ixgbe_setup_phy_link_generic - Set and restart auto-neg
 771  * @hw: pointer to hardware structure
 772  *
 773  * Restart auto-negotiation and PHY and waits for completion.
 774  **/
 775 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 776 {
 777         s32 status = IXGBE_SUCCESS;
 778         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 779         bool autoneg = false;
 780         ixgbe_link_speed speed;
 781
 782         DEBUGFUNC("ixgbe_setup_phy_link_generic");
 783
 784         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 785
 786         /* Set or unset auto-negotiation 10G advertisement */
 787         hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 788                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 789                              &autoneg_reg);
 790
 791         autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 792         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
 793             (speed & IXGBE_LINK_SPEED_10GB_FULL))
 794                 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 795
 796         hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 797                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 798                               autoneg_reg);
 799
 800         hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 801                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 802                              &autoneg_reg);
 803
 804         if (hw->mac.type == ixgbe_mac_X550) {
 805                 /* Set or unset auto-negotiation 5G advertisement */
 806                 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
 807                 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
 808                     (speed & IXGBE_LINK_SPEED_5GB_FULL))
 809                         autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
 810
 811                 /* Set or unset auto-negotiation 2.5G advertisement */
 812                 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
 813                 if ((hw->phy.autoneg_advertised &
 814                      IXGBE_LINK_SPEED_2_5GB_FULL) &&
 815                     (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
 816                         autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
 817         }
 818
 819         /* Set or unset auto-negotiation 1G advertisement */
 820         autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 821         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
 822             (speed & IXGBE_LINK_SPEED_1GB_FULL))
 823                 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 824
 825         hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 826                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 827                               autoneg_reg);
 828
 829         /* Set or unset auto-negotiation 100M advertisement */
 830         hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 831                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 832                              &autoneg_reg);
 833
 834         autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 835                          IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 836         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
 837             (speed & IXGBE_LINK_SPEED_100_FULL))
 838                 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 839
 840         hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 841                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 842                               autoneg_reg);
 843
 844         ixgbe_restart_auto_neg(hw);
 845         return status;
 846 }
 847
 848 /**
 849  * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 850  * @hw: pointer to hardware structure
 851  * @speed: new link speed
 852  * @autoneg_wait_to_complete: unused
 853  **/
 854 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 855                                        ixgbe_link_speed speed,
 856                                        bool autoneg_wait_to_complete)
 857 {
 858         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
 859
 860         DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
 861
 862         /*
 863          * Clear autoneg_advertised and set new values based on input link
 864          * speed.
 865          */
 866         hw->phy.autoneg_advertised = 0;
 867
 868         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 869                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 870
 871         if (speed & IXGBE_LINK_SPEED_5GB_FULL)
 872                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
 873
 874         if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
 875                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
 876
 877         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 878                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 879
 880         if (speed & IXGBE_LINK_SPEED_100_FULL)
 881                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 882
 883         if (speed & IXGBE_LINK_SPEED_10_FULL)
 884                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
 885
 886         /* Setup link based on the new speed settings */
 887         ixgbe_setup_phy_link(hw);
 888
 889         return IXGBE_SUCCESS;
 890 }
 891
 892 /**
 893  * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
 894  * @hw: pointer to hardware structure
 895  *
 896  * Determines the supported link capabilities by reading the PHY auto
 897  * negotiation register.
 898  **/
 899 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
 900 {
 901         s32 status;
 902         u16 speed_ability;
 903
 904         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 905                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 906                                       &speed_ability);
 907         if (status)
 908                 return status;
 909
 910         if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 911                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
 912         if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 913                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
 914         if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 915                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
 916
 917         switch (hw->mac.type) {
 918         case ixgbe_mac_X550:
 919                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
 920                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
 921                 break;
 922         case ixgbe_mac_X550EM_x:
 923         case ixgbe_mac_X550EM_a:
 924                 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
 925                 break;
 926         default:
 927                 break;
 928         }
 929
 930         return status;
 931 }
 932
 933 /**
 934  * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 935  * @hw: pointer to hardware structure
 936  * @speed: pointer to link speed
 937  * @autoneg: boolean auto-negotiation value
 938  **/
 939 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 940                                                ixgbe_link_speed *speed,
 941                                                bool *autoneg)
 942 {
 943         s32 status = IXGBE_SUCCESS;
 944
 945         DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
 946
 947         *autoneg = true;
 948         if (!hw->phy.speeds_supported)
 949                 status = ixgbe_get_copper_speeds_supported(hw);
 950
 951         *speed = hw->phy.speeds_supported;
 952         return status;
 953 }
 954
 955 /**
 956  * ixgbe_check_phy_link_tnx - Determine link and speed status
 957  * @hw: pointer to hardware structure
 958  * @speed: current link speed
 959  * @link_up: true is link is up, false otherwise
 960  *
 961  * Reads the VS1 register to determine if link is up and the current speed for
 962  * the PHY.
 963  **/
 964 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 965                              bool *link_up)
 966 {
 967         s32 status = IXGBE_SUCCESS;
 968         u32 time_out;
 969         u32 max_time_out = 10;
 970         u16 phy_link = 0;
 971         u16 phy_speed = 0;
 972         u16 phy_data = 0;
 973
 974         DEBUGFUNC("ixgbe_check_phy_link_tnx");
 975
 976         /* Initialize speed and link to default case */
 977         *link_up = false;
 978         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 979
 980         /*
 981          * Check current speed and link status of the PHY register.
 982          * This is a vendor specific register and may have to
 983          * be changed for other copper PHYs.
 984          */
 985         for (time_out = 0; time_out < max_time_out; time_out++) {
 986                 usec_delay(10);
 987                 status = hw->phy.ops.read_reg(hw,
 988                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
 989                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 990                                         &phy_data);
 991                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
 992                 phy_speed = phy_data &
 993                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
 994                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
 995                         *link_up = true;
 996                         if (phy_speed ==
 997                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
 998                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 999                         break;
1000                 }
1001         }
1002
1003         return status;
1004 }
1005
1006 /**
1007  *      ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1008  *      @hw: pointer to hardware structure
1009  *
1010  *      Restart auto-negotiation and PHY and waits for completion.
1011  **/
1012 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1013 {
1014         s32 status = IXGBE_SUCCESS;
1015         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1016         bool autoneg = false;
1017         ixgbe_link_speed speed;
1018
1019         DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1020
1021         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1022
1023         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1024                 /* Set or unset auto-negotiation 10G advertisement */
1025                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1026                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1027                                      &autoneg_reg);
1028
1029                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1030                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1031                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1032
1033                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1034                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1035                                       autoneg_reg);
1036         }
1037
1038         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1039                 /* Set or unset auto-negotiation 1G advertisement */
1040                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1041                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1042                                      &autoneg_reg);
1043
1044                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1045                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1046                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1047
1048                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1049                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1050                                       autoneg_reg);
1051         }
1052
1053         if (speed & IXGBE_LINK_SPEED_100_FULL) {
1054                 /* Set or unset auto-negotiation 100M advertisement */
1055                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1056                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1057                                      &autoneg_reg);
1058
1059                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1060                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1061                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1062
1063                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1064                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1065                                       autoneg_reg);
1066         }
1067
1068         ixgbe_restart_auto_neg(hw);
1069         return status;
1070 }
1071
1072 /**
1073  * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1074  * @hw: pointer to hardware structure
1075  * @firmware_version: pointer to the PHY Firmware Version
1076  **/
1077 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1078                                        u16 *firmware_version)
1079 {
1080         s32 status;
1081
1082         DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1083
1084         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1085                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1086                                       firmware_version);
1087
1088         return status;
1089 }
1090
1091 /**
1092  * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1093  * @hw: pointer to hardware structure
1094  * @firmware_version: pointer to the PHY Firmware Version
1095  **/
1096 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1097                                            u16 *firmware_version)
1098 {
1099         s32 status;
1100
1101         DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1102
1103         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1104                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1105                                       firmware_version);
1106
1107         return status;
1108 }
1109
1110 /**
1111  * ixgbe_reset_phy_nl - Performs a PHY reset
1112  * @hw: pointer to hardware structure
1113  **/
1114 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1115 {
1116         u16 phy_offset, control, eword, edata, block_crc;
1117         bool end_data = false;
1118         u16 list_offset, data_offset;
1119         u16 phy_data = 0;
1120         s32 ret_val = IXGBE_SUCCESS;
1121         u32 i;
1122
1123         DEBUGFUNC("ixgbe_reset_phy_nl");
1124
1125         /* Blocked by MNG FW so bail */
1126         if (ixgbe_check_reset_blocked(hw))
1127                 goto out;
1128
1129         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1130                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1131
1132         /* reset the PHY and poll for completion */
1133         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1134                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
1135                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1136
1137         for (i = 0; i < 100; i++) {
1138                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1139                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1140                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1141                         break;
1142                 msec_delay(10);
1143         }
1144
1145         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1146                 DEBUGOUT("PHY reset did not complete.\n");
1147                 ret_val = IXGBE_ERR_PHY;
1148                 goto out;
1149         }
1150
1151         /* Get init offsets */
1152         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1153                                                       &data_offset);
1154         if (ret_val != IXGBE_SUCCESS)
1155                 goto out;
1156
1157         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1158         data_offset++;
1159         while (!end_data) {
1160                 /*
1161                  * Read control word from PHY init contents offset
1162                  */
1163                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1164                 if (ret_val)
1165                         goto err_eeprom;
1166                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1167                            IXGBE_CONTROL_SHIFT_NL;
1168                 edata = eword & IXGBE_DATA_MASK_NL;
1169                 switch (control) {
1170                 case IXGBE_DELAY_NL:
1171                         data_offset++;
1172                         DEBUGOUT1("DELAY: %d MS\n", edata);
1173                         msec_delay(edata);
1174                         break;
1175                 case IXGBE_DATA_NL:
1176                         DEBUGOUT("DATA:\n");
1177                         data_offset++;
1178                         ret_val = hw->eeprom.ops.read(hw, data_offset,
1179                                                       &phy_offset);
1180                         if (ret_val)
1181                                 goto err_eeprom;
1182                         data_offset++;
1183                         for (i = 0; i < edata; i++) {
1184                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
1185                                                               &eword);
1186                                 if (ret_val)
1187                                         goto err_eeprom;
1188                                 hw->phy.ops.write_reg(hw, phy_offset,
1189                                                       IXGBE_TWINAX_DEV, eword);
1190                                 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1191                                           phy_offset);
1192                                 data_offset++;
1193                                 phy_offset++;
1194                         }
1195                         break;
1196                 case IXGBE_CONTROL_NL:
1197                         data_offset++;
1198                         DEBUGOUT("CONTROL:\n");
1199                         if (edata == IXGBE_CONTROL_EOL_NL) {
1200                                 DEBUGOUT("EOL\n");
1201                                 end_data = true;
1202                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
1203                                 DEBUGOUT("SOL\n");
1204                         } else {
1205                                 DEBUGOUT("Bad control value\n");
1206                                 ret_val = IXGBE_ERR_PHY;
1207                                 goto out;
1208                         }
1209                         break;
1210                 default:
1211                         DEBUGOUT("Bad control type\n");
1212                         ret_val = IXGBE_ERR_PHY;
1213                         goto out;
1214                 }
1215         }
1216
1217 out:
1218         return ret_val;
1219
1220 err_eeprom:
1221         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1222                       "eeprom read at offset %d failed", data_offset);
1223         return IXGBE_ERR_PHY;
1224 }
1225
1226 /**
1227  * ixgbe_identify_module_generic - Identifies module type
1228  * @hw: pointer to hardware structure
1229  *
1230  * Determines HW type and calls appropriate function.
1231  **/
1232 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1233 {
1234         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1235
1236         DEBUGFUNC("ixgbe_identify_module_generic");
1237
1238         switch (hw->mac.ops.get_media_type(hw)) {
1239         case ixgbe_media_type_fiber:
1240                 status = ixgbe_identify_sfp_module_generic(hw);
1241                 break;
1242
1243         case ixgbe_media_type_fiber_qsfp:
1244                 status = ixgbe_identify_qsfp_module_generic(hw);
1245                 break;
1246
1247         default:
1248                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1249                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1250                 break;
1251         }
1252
1253         return status;
1254 }
1255
1256 /**
1257  * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1258  * @hw: pointer to hardware structure
1259  *
1260  * Searches for and identifies the SFP module and assigns appropriate PHY type.
1261  **/
1262 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1263 {
1264         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1265         u32 vendor_oui = 0;
1266         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1267         u8 identifier = 0;
1268         u8 comp_codes_1g = 0;
1269         u8 comp_codes_10g = 0;
1270         u8 oui_bytes[3] = {0, 0, 0};
1271         u8 cable_tech = 0;
1272         u8 cable_spec = 0;
1273         u16 enforce_sfp = 0;
1274
1275         DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1276
1277         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1278                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1279                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1280                 goto out;
1281         }
1282
1283         /* LAN ID is needed for I2C access */
1284         hw->mac.ops.set_lan_id(hw);
1285
1286         status = hw->phy.ops.read_i2c_eeprom(hw,
1287                                              IXGBE_SFF_IDENTIFIER,
1288                                              &identifier);
1289
1290         if (status != IXGBE_SUCCESS)
1291                 goto err_read_i2c_eeprom;
1292
1293         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1294                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1295                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1296         } else {
1297                 status = hw->phy.ops.read_i2c_eeprom(hw,
1298                                                      IXGBE_SFF_1GBE_COMP_CODES,
1299                                                      &comp_codes_1g);
1300
1301                 if (status != IXGBE_SUCCESS)
1302                         goto err_read_i2c_eeprom;
1303
1304                 status = hw->phy.ops.read_i2c_eeprom(hw,
1305                                                      IXGBE_SFF_10GBE_COMP_CODES,
1306                                                      &comp_codes_10g);
1307
1308                 if (status != IXGBE_SUCCESS)
1309                         goto err_read_i2c_eeprom;
1310                 status = hw->phy.ops.read_i2c_eeprom(hw,
1311                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
1312                                                      &cable_tech);
1313
1314                 if (status != IXGBE_SUCCESS)
1315                         goto err_read_i2c_eeprom;
1316
1317                  /* ID Module
1318                   * =========
1319                   * 0   SFP_DA_CU
1320                   * 1   SFP_SR
1321                   * 2   SFP_LR
1322                   * 3   SFP_DA_CORE0 - 82599-specific
1323                   * 4   SFP_DA_CORE1 - 82599-specific
1324                   * 5   SFP_SR/LR_CORE0 - 82599-specific
1325                   * 6   SFP_SR/LR_CORE1 - 82599-specific
1326                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1327                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1328                   * 9   SFP_1g_cu_CORE0 - 82599-specific
1329                   * 10  SFP_1g_cu_CORE1 - 82599-specific
1330                   * 11  SFP_1g_sx_CORE0 - 82599-specific
1331                   * 12  SFP_1g_sx_CORE1 - 82599-specific
1332                   */
1333                 if (hw->mac.type == ixgbe_mac_82598EB) {
1334                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1335                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1336                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1337                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1338                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1339                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1340                         else
1341                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1342                 } else {
1343                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1344                                 if (hw->bus.lan_id == 0)
1345                                         hw->phy.sfp_type =
1346                                                      ixgbe_sfp_type_da_cu_core0;
1347                                 else
1348                                         hw->phy.sfp_type =
1349                                                      ixgbe_sfp_type_da_cu_core1;
1350                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1351                                 hw->phy.ops.read_i2c_eeprom(
1352                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1353                                                 &cable_spec);
1354                                 if (cable_spec &
1355                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1356                                         if (hw->bus.lan_id == 0)
1357                                                 hw->phy.sfp_type =
1358                                                 ixgbe_sfp_type_da_act_lmt_core0;
1359                                         else
1360                                                 hw->phy.sfp_type =
1361                                                 ixgbe_sfp_type_da_act_lmt_core1;
1362                                 } else {
1363                                         hw->phy.sfp_type =
1364                                                         ixgbe_sfp_type_unknown;
1365                                 }
1366                         } else if (comp_codes_10g &
1367                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1368                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1369                                 if (hw->bus.lan_id == 0)
1370                                         hw->phy.sfp_type =
1371                                                       ixgbe_sfp_type_srlr_core0;
1372                                 else
1373                                         hw->phy.sfp_type =
1374                                                       ixgbe_sfp_type_srlr_core1;
1375                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1376                                 if (hw->bus.lan_id == 0)
1377                                         hw->phy.sfp_type =
1378                                                 ixgbe_sfp_type_1g_cu_core0;
1379                                 else
1380                                         hw->phy.sfp_type =
1381                                                 ixgbe_sfp_type_1g_cu_core1;
1382                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1383                                 if (hw->bus.lan_id == 0)
1384                                         hw->phy.sfp_type =
1385                                                 ixgbe_sfp_type_1g_sx_core0;
1386                                 else
1387                                         hw->phy.sfp_type =
1388                                                 ixgbe_sfp_type_1g_sx_core1;
1389                         } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1390                                 if (hw->bus.lan_id == 0)
1391                                         hw->phy.sfp_type =
1392                                                 ixgbe_sfp_type_1g_lx_core0;
1393                                 else
1394                                         hw->phy.sfp_type =
1395                                                 ixgbe_sfp_type_1g_lx_core1;
1396                         } else if (comp_codes_1g & IXGBE_SFF_1GBASELHA_CAPABLE) {
1397                                 if (hw->bus.lan_id == 0)
1398                                         hw->phy.sfp_type =
1399                                                 ixgbe_sfp_type_1g_lha_core0;
1400                                 else
1401                                         hw->phy.sfp_type =
1402                                                 ixgbe_sfp_type_1g_lha_core1;
1403                         } else {
1404                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1405                         }
1406                 }
1407
1408                 if (hw->phy.sfp_type != stored_sfp_type)
1409                         hw->phy.sfp_setup_needed = true;
1410
1411                 /* Determine if the SFP+ PHY is dual speed or not. */
1412                 hw->phy.multispeed_fiber = false;
1413                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1414                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1415                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1416                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1417                         hw->phy.multispeed_fiber = true;
1418
1419                 /* Determine PHY vendor */
1420                 if (hw->phy.type != ixgbe_phy_nl) {
1421                         hw->phy.id = identifier;
1422                         status = hw->phy.ops.read_i2c_eeprom(hw,
1423                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1424                                                     &oui_bytes[0]);
1425
1426                         if (status != IXGBE_SUCCESS)
1427                                 goto err_read_i2c_eeprom;
1428
1429                         status = hw->phy.ops.read_i2c_eeprom(hw,
1430                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1431                                                     &oui_bytes[1]);
1432
1433                         if (status != IXGBE_SUCCESS)
1434                                 goto err_read_i2c_eeprom;
1435
1436                         status = hw->phy.ops.read_i2c_eeprom(hw,
1437                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1438                                                     &oui_bytes[2]);
1439
1440                         if (status != IXGBE_SUCCESS)
1441                                 goto err_read_i2c_eeprom;
1442
1443                         vendor_oui =
1444                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1445                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1446                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1447
1448                         switch (vendor_oui) {
1449                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1450                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1451                                         hw->phy.type =
1452                                                     ixgbe_phy_sfp_passive_tyco;
1453                                 break;
1454                         case IXGBE_SFF_VENDOR_OUI_FTL:
1455                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1456                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1457                                 else
1458                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1459                                 break;
1460                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1461                                 hw->phy.type = ixgbe_phy_sfp_avago;
1462                                 break;
1463                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1464                                 hw->phy.type = ixgbe_phy_sfp_intel;
1465                                 break;
1466                         default:
1467                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1468                                         hw->phy.type =
1469                                                  ixgbe_phy_sfp_passive_unknown;
1470                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1471                                         hw->phy.type =
1472                                                 ixgbe_phy_sfp_active_unknown;
1473                                 else
1474                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1475                                 break;
1476                         }
1477                 }
1478
1479                 /* Allow any DA cable vendor */
1480                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1481                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1482                         status = IXGBE_SUCCESS;
1483                         goto out;
1484                 }
1485
1486                 /* Verify supported 1G SFP modules */
1487                 if (comp_codes_10g == 0 &&
1488                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1489                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1490                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lha_core0 ||
1491                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lha_core1 ||
1492                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1493                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1494                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1495                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1496                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1497                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1498                         goto out;
1499                 }
1500
1501                 /* Anything else 82598-based is supported */
1502                 if (hw->mac.type == ixgbe_mac_82598EB) {
1503                         status = IXGBE_SUCCESS;
1504                         goto out;
1505                 }
1506
1507                 ixgbe_get_device_caps(hw, &enforce_sfp);
1508                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1509                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1510                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1511                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lha_core0 ||
1512                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lha_core1 ||
1513                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1514                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1515                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1516                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1517                         /* Make sure we're a supported PHY type */
1518                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1519                                 status = IXGBE_SUCCESS;
1520                         } else {
1521                                 if (hw->allow_unsupported_sfp == true) {
1522                                         EWARN(hw,
1523                                                 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. "
1524                                                 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
1525                                                 "Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1526                                         status = IXGBE_SUCCESS;
1527                                 } else {
1528                                         DEBUGOUT("SFP+ module not supported\n");
1529                                         hw->phy.type =
1530                                                 ixgbe_phy_sfp_unsupported;
1531                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1532                                 }
1533                         }
1534                 } else {
1535                         status = IXGBE_SUCCESS;
1536                 }
1537         }
1538
1539 out:
1540         return status;
1541
1542 err_read_i2c_eeprom:
1543         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1544         if (hw->phy.type != ixgbe_phy_nl) {
1545                 hw->phy.id = 0;
1546                 hw->phy.type = ixgbe_phy_unknown;
1547         }
1548         return IXGBE_ERR_SFP_NOT_PRESENT;
1549 }
1550
1551 /**
1552  * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1553  * @hw: pointer to hardware structure
1554  *
1555  * Determines physical layer capabilities of the current SFP.
1556  */
1557 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1558 {
1559         u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1560         u8 comp_codes_10g = 0;
1561         u8 comp_codes_1g = 0;
1562
1563         DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1564
1565         hw->phy.ops.identify_sfp(hw);
1566         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1567                 return physical_layer;
1568
1569         switch (hw->phy.type) {
1570         case ixgbe_phy_sfp_passive_tyco:
1571         case ixgbe_phy_sfp_passive_unknown:
1572         case ixgbe_phy_qsfp_passive_unknown:
1573                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1574                 break;
1575         case ixgbe_phy_sfp_ftl_active:
1576         case ixgbe_phy_sfp_active_unknown:
1577         case ixgbe_phy_qsfp_active_unknown:
1578                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1579                 break;
1580         case ixgbe_phy_sfp_avago:
1581         case ixgbe_phy_sfp_ftl:
1582         case ixgbe_phy_sfp_intel:
1583         case ixgbe_phy_sfp_unknown:
1584                 hw->phy.ops.read_i2c_eeprom(hw,
1585                       IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1586                 hw->phy.ops.read_i2c_eeprom(hw,
1587                       IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1588                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1589                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1590                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1591                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1592                 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1593                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1594                 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1595                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1596                 break;
1597         case ixgbe_phy_qsfp_intel:
1598         case ixgbe_phy_qsfp_unknown:
1599                 hw->phy.ops.read_i2c_eeprom(hw,
1600                       IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1601                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1602                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1603                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1604                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1605                 break;
1606         default:
1607                 break;
1608         }
1609
1610         return physical_layer;
1611 }
1612
1613 /**
1614  * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1615  * @hw: pointer to hardware structure
1616  *
1617  * Searches for and identifies the QSFP module and assigns appropriate PHY type
1618  **/
1619 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1620 {
1621         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1622         u32 vendor_oui = 0;
1623         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1624         u8 identifier = 0;
1625         u8 comp_codes_1g = 0;
1626         u8 comp_codes_10g = 0;
1627         u8 oui_bytes[3] = {0, 0, 0};
1628         u16 enforce_sfp = 0;
1629         u8 connector = 0;
1630         u8 cable_length = 0;
1631         u8 device_tech = 0;
1632         bool active_cable = false;
1633
1634         DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1635
1636         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1637                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1638                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1639                 goto out;
1640         }
1641
1642         /* LAN ID is needed for I2C access */
1643         hw->mac.ops.set_lan_id(hw);
1644
1645         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1646                                              &identifier);
1647
1648         if (status != IXGBE_SUCCESS)
1649                 goto err_read_i2c_eeprom;
1650
1651         if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1652                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1653                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1654                 goto out;
1655         }
1656
1657         hw->phy.id = identifier;
1658
1659         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1660                                              &comp_codes_10g);
1661
1662         if (status != IXGBE_SUCCESS)
1663                 goto err_read_i2c_eeprom;
1664
1665         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1666                                              &comp_codes_1g);
1667
1668         if (status != IXGBE_SUCCESS)
1669                 goto err_read_i2c_eeprom;
1670
1671         if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1672                 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1673                 if (hw->bus.lan_id == 0)
1674                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1675                 else
1676                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1677         } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1678                                      IXGBE_SFF_10GBASELR_CAPABLE)) {
1679                 if (hw->bus.lan_id == 0)
1680                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1681                 else
1682                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1683         } else {
1684                 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1685                         active_cable = true;
1686
1687                 if (!active_cable) {
1688                         /* check for active DA cables that pre-date
1689                          * SFF-8436 v3.6 */
1690                         hw->phy.ops.read_i2c_eeprom(hw,
1691                                         IXGBE_SFF_QSFP_CONNECTOR,
1692                                         &connector);
1693
1694                         hw->phy.ops.read_i2c_eeprom(hw,
1695                                         IXGBE_SFF_QSFP_CABLE_LENGTH,
1696                                         &cable_length);
1697
1698                         hw->phy.ops.read_i2c_eeprom(hw,
1699                                         IXGBE_SFF_QSFP_DEVICE_TECH,
1700                                         &device_tech);
1701
1702                         if ((connector ==
1703                                      IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1704                             (cable_length > 0) &&
1705                             ((device_tech >> 4) ==
1706                                      IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1707                                 active_cable = true;
1708                 }
1709
1710                 if (active_cable) {
1711                         hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1712                         if (hw->bus.lan_id == 0)
1713                                 hw->phy.sfp_type =
1714                                                 ixgbe_sfp_type_da_act_lmt_core0;
1715                         else
1716                                 hw->phy.sfp_type =
1717                                                 ixgbe_sfp_type_da_act_lmt_core1;
1718                 } else {
1719                         /* unsupported module type */
1720                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1721                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1722                         goto out;
1723                 }
1724         }
1725
1726         if (hw->phy.sfp_type != stored_sfp_type)
1727                 hw->phy.sfp_setup_needed = true;
1728
1729         /* Determine if the QSFP+ PHY is dual speed or not. */
1730         hw->phy.multispeed_fiber = false;
1731         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1732            (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1733            ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1734            (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1735                 hw->phy.multispeed_fiber = true;
1736
1737         /* Determine PHY vendor for optical modules */
1738         if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1739                               IXGBE_SFF_10GBASELR_CAPABLE))  {
1740                 status = hw->phy.ops.read_i2c_eeprom(hw,
1741                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1742                                             &oui_bytes[0]);
1743
1744                 if (status != IXGBE_SUCCESS)
1745                         goto err_read_i2c_eeprom;
1746
1747                 status = hw->phy.ops.read_i2c_eeprom(hw,
1748                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1749                                             &oui_bytes[1]);
1750
1751                 if (status != IXGBE_SUCCESS)
1752                         goto err_read_i2c_eeprom;
1753
1754                 status = hw->phy.ops.read_i2c_eeprom(hw,
1755                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1756                                             &oui_bytes[2]);
1757
1758                 if (status != IXGBE_SUCCESS)
1759                         goto err_read_i2c_eeprom;
1760
1761                 vendor_oui =
1762                   ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1763                    (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1764                    (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1765
1766                 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1767                         hw->phy.type = ixgbe_phy_qsfp_intel;
1768                 else
1769                         hw->phy.type = ixgbe_phy_qsfp_unknown;
1770
1771                 ixgbe_get_device_caps(hw, &enforce_sfp);
1772                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1773                         /* Make sure we're a supported PHY type */
1774                         if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1775                                 status = IXGBE_SUCCESS;
1776                         } else {
1777                                 if (hw->allow_unsupported_sfp == true) {
1778                                         EWARN(hw,
1779                                                 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. "
1780                                                 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
1781                                                 "Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1782                                         status = IXGBE_SUCCESS;
1783                                 } else {
1784                                         DEBUGOUT("QSFP module not supported\n");
1785                                         hw->phy.type =
1786                                                 ixgbe_phy_sfp_unsupported;
1787                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1788                                 }
1789                         }
1790                 } else {
1791                         status = IXGBE_SUCCESS;
1792                 }
1793         }
1794
1795 out:
1796         return status;
1797
1798 err_read_i2c_eeprom:
1799         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1800         hw->phy.id = 0;
1801         hw->phy.type = ixgbe_phy_unknown;
1802
1803         return IXGBE_ERR_SFP_NOT_PRESENT;
1804 }
1805
1806 /**
1807  * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1808  * @hw: pointer to hardware structure
1809  * @list_offset: offset to the SFP ID list
1810  * @data_offset: offset to the SFP data block
1811  *
1812  * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1813  * so it returns the offsets to the phy init sequence block.
1814  **/
1815 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1816                                         u16 *list_offset,
1817                                         u16 *data_offset)
1818 {
1819         u16 sfp_id;
1820         u16 sfp_type = hw->phy.sfp_type;
1821
1822         DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1823
1824         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1825                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1826
1827         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1828                 return IXGBE_ERR_SFP_NOT_PRESENT;
1829
1830         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1831             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1832                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1833
1834         /*
1835          * Limiting active cables and 1G Phys must be initialized as
1836          * SR modules
1837          */
1838         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1839             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1840             sfp_type == ixgbe_sfp_type_1g_lha_core0 ||
1841             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1842             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1843                 sfp_type = ixgbe_sfp_type_srlr_core0;
1844         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1845                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1846                  sfp_type == ixgbe_sfp_type_1g_lha_core1 ||
1847                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1848                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1849                 sfp_type = ixgbe_sfp_type_srlr_core1;
1850
1851         /* Read offset to PHY init contents */
1852         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1853                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1854                               "eeprom read at offset %d failed",
1855                               IXGBE_PHY_INIT_OFFSET_NL);
1856                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1857         }
1858
1859         if ((!*list_offset) || (*list_offset == 0xFFFF))
1860                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1861
1862         /* Shift offset to first ID word */
1863         (*list_offset)++;
1864
1865         /*
1866          * Find the matching SFP ID in the EEPROM
1867          * and program the init sequence
1868          */
1869         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1870                 goto err_phy;
1871
1872         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1873                 if (sfp_id == sfp_type) {
1874                         (*list_offset)++;
1875                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1876                                 goto err_phy;
1877                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1878                                 DEBUGOUT("SFP+ module not supported\n");
1879                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1880                         } else {
1881                                 break;
1882                         }
1883                 } else {
1884                         (*list_offset) += 2;
1885                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1886                                 goto err_phy;
1887                 }
1888         }
1889
1890         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1891                 DEBUGOUT("No matching SFP+ module found\n");
1892                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1893         }
1894
1895         return IXGBE_SUCCESS;
1896
1897 err_phy:
1898         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1899                       "eeprom read at offset %d failed", *list_offset);
1900         return IXGBE_ERR_PHY;
1901 }
1902
1903 /**
1904  * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1905  * @hw: pointer to hardware structure
1906  * @byte_offset: EEPROM byte offset to read
1907  * @eeprom_data: value read
1908  *
1909  * Performs byte read operation to SFP module's EEPROM over I2C interface.
1910  **/
1911 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1912                                   u8 *eeprom_data)
1913 {
1914         DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1915
1916         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1917                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1918                                          eeprom_data);
1919 }
1920
1921 /**
1922  * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1923  * @hw: pointer to hardware structure
1924  * @byte_offset: byte offset at address 0xA2
1925  * @sff8472_data: value read
1926  *
1927  * Performs byte read operation to SFP module's SFF-8472 data over I2C
1928  **/
1929 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1930                                           u8 *sff8472_data)
1931 {
1932         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1933                                          IXGBE_I2C_EEPROM_DEV_ADDR2,
1934                                          sff8472_data);
1935 }
1936
1937 /**
1938  * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1939  * @hw: pointer to hardware structure
1940  * @byte_offset: EEPROM byte offset to write
1941  * @eeprom_data: value to write
1942  *
1943  * Performs byte write operation to SFP module's EEPROM over I2C interface.
1944  **/
1945 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1946                                    u8 eeprom_data)
1947 {
1948         DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1949
1950         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1951                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1952                                           eeprom_data);
1953 }
1954
1955 /**
1956  * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1957  * @hw: pointer to hardware structure
1958  * @offset: eeprom offset to be read
1959  * @addr: I2C address to be read
1960  */
1961 STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1962 {
1963         if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1964             offset == IXGBE_SFF_IDENTIFIER &&
1965             hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1966                 return true;
1967         return false;
1968 }
1969
1970 /**
1971  * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1972  * @hw: pointer to hardware structure
1973  * @byte_offset: byte offset to read
1974  * @dev_addr: address to read from
1975  * @data: value read
1976  * @lock: true if to take and release semaphore
1977  *
1978  * Performs byte read operation to SFP module's EEPROM over I2C interface at
1979  * a specified device address.
1980  **/
1981 STATIC s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
1982                                            u8 dev_addr, u8 *data, bool lock)
1983 {
1984         s32 status;
1985         u32 max_retry = 10;
1986         u32 retry = 0;
1987         u32 swfw_mask = hw->phy.phy_semaphore_mask;
1988         bool nack = 1;
1989         *data = 0;
1990
1991         DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1992
1993         if (hw->mac.type >= ixgbe_mac_X550)
1994                 max_retry = 3;
1995         if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
1996                 max_retry = IXGBE_SFP_DETECT_RETRIES;
1997
1998         do {
1999                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2000                         return IXGBE_ERR_SWFW_SYNC;
2001
2002                 ixgbe_i2c_start(hw);
2003
2004                 /* Device Address and write indication */
2005                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2006                 if (status != IXGBE_SUCCESS)
2007                         goto fail;
2008
2009                 status = ixgbe_get_i2c_ack(hw);
2010                 if (status != IXGBE_SUCCESS)
2011                         goto fail;
2012
2013                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2014                 if (status != IXGBE_SUCCESS)
2015                         goto fail;
2016
2017                 status = ixgbe_get_i2c_ack(hw);
2018                 if (status != IXGBE_SUCCESS)
2019                         goto fail;
2020
2021                 ixgbe_i2c_start(hw);
2022
2023                 /* Device Address and read indication */
2024                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2025                 if (status != IXGBE_SUCCESS)
2026                         goto fail;
2027
2028                 status = ixgbe_get_i2c_ack(hw);
2029                 if (status != IXGBE_SUCCESS)
2030                         goto fail;
2031
2032                 ixgbe_clock_in_i2c_byte(hw, data);
2033
2034                 status = ixgbe_clock_out_i2c_bit(hw, nack);
2035                 if (status != IXGBE_SUCCESS)
2036                         goto fail;
2037
2038                 ixgbe_i2c_stop(hw);
2039                 if (lock)
2040                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2041                 return IXGBE_SUCCESS;
2042
2043 fail:
2044                 ixgbe_i2c_bus_clear(hw);
2045                 if (lock) {
2046                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2047                         msec_delay(100);
2048                 }
2049                 if (retry < max_retry)
2050                         DEBUGOUT("I2C byte read error - Retrying.\n");
2051                 else
2052                         DEBUGOUT("I2C byte read error.\n");
2053                 retry++;
2054         } while (retry <= max_retry);
2055
2056         return status;
2057 }
2058
2059 /**
2060  * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2061  * @hw: pointer to hardware structure
2062  * @byte_offset: byte offset to read
2063  * @dev_addr: address to read from
2064  * @data: value read
2065  *
2066  * Performs byte read operation to SFP module's EEPROM over I2C interface at
2067  * a specified device address.
2068  **/
2069 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2070                                 u8 dev_addr, u8 *data)
2071 {
2072         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2073                                                data, true);
2074 }
2075
2076 /**
2077  * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2078  * @hw: pointer to hardware structure
2079  * @byte_offset: byte offset to read
2080  * @dev_addr: address to read from
2081  * @data: value read
2082  *
2083  * Performs byte read operation to SFP module's EEPROM over I2C interface at
2084  * a specified device address.
2085  **/
2086 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2087                                          u8 dev_addr, u8 *data)
2088 {
2089         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2090                                                data, false);
2091 }
2092
2093 /**
2094  * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2095  * @hw: pointer to hardware structure
2096  * @byte_offset: byte offset to write
2097  * @dev_addr: address to write to
2098  * @data: value to write
2099  * @lock: true if to take and release semaphore
2100  *
2101  * Performs byte write operation to SFP module's EEPROM over I2C interface at
2102  * a specified device address.
2103  **/
2104 STATIC s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2105                                             u8 dev_addr, u8 data, bool lock)
2106 {
2107         s32 status;
2108         u32 max_retry = 1;
2109         u32 retry = 0;
2110         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2111
2112         DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2113
2114         if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2115             IXGBE_SUCCESS)
2116                 return IXGBE_ERR_SWFW_SYNC;
2117
2118         do {
2119                 ixgbe_i2c_start(hw);
2120
2121                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2122                 if (status != IXGBE_SUCCESS)
2123                         goto fail;
2124
2125                 status = ixgbe_get_i2c_ack(hw);
2126                 if (status != IXGBE_SUCCESS)
2127                         goto fail;
2128
2129                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2130                 if (status != IXGBE_SUCCESS)
2131                         goto fail;
2132
2133                 status = ixgbe_get_i2c_ack(hw);
2134                 if (status != IXGBE_SUCCESS)
2135                         goto fail;
2136
2137                 status = ixgbe_clock_out_i2c_byte(hw, data);
2138                 if (status != IXGBE_SUCCESS)
2139                         goto fail;
2140
2141                 status = ixgbe_get_i2c_ack(hw);
2142                 if (status != IXGBE_SUCCESS)
2143                         goto fail;
2144
2145                 ixgbe_i2c_stop(hw);
2146                 if (lock)
2147                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2148                 return IXGBE_SUCCESS;
2149
2150 fail:
2151                 ixgbe_i2c_bus_clear(hw);
2152                 if (retry < max_retry)
2153                         DEBUGOUT("I2C byte write error - Retrying.\n");
2154                 else
2155                         DEBUGOUT("I2C byte write error.\n");
2156                 retry++;
2157         } while (retry <= max_retry);
2158
2159         if (lock)
2160                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2161
2162         return status;
2163 }
2164
2165 /**
2166  * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2167  * @hw: pointer to hardware structure
2168  * @byte_offset: byte offset to write
2169  * @dev_addr: address to write to
2170  * @data: value to write
2171  *
2172  * Performs byte write operation to SFP module's EEPROM over I2C interface at
2173  * a specified device address.
2174  **/
2175 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2176                                  u8 dev_addr, u8 data)
2177 {
2178         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2179                                                 data, true);
2180 }
2181
2182 /**
2183  * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2184  * @hw: pointer to hardware structure
2185  * @byte_offset: byte offset to write
2186  * @dev_addr: address to write to
2187  * @data: value to write
2188  *
2189  * Performs byte write operation to SFP module's EEPROM over I2C interface at
2190  * a specified device address.
2191  **/
2192 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2193                                           u8 dev_addr, u8 data)
2194 {
2195         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2196                                                 data, false);
2197 }
2198
2199 /**
2200  * ixgbe_i2c_start - Sets I2C start condition
2201  * @hw: pointer to hardware structure
2202  *
2203  * Sets I2C start condition (High -> Low on SDA while SCL is High)
2204  * Set bit-bang mode on X550 hardware.
2205  **/
2206 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2207 {
2208         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2209
2210         DEBUGFUNC("ixgbe_i2c_start");
2211
2212         i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2213
2214         /* Start condition must begin with data and clock high */
2215         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2216         ixgbe_raise_i2c_clk(hw, &i2cctl);
2217
2218         /* Setup time for start condition (4.7us) */
2219         usec_delay(IXGBE_I2C_T_SU_STA);
2220
2221         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2222
2223         /* Hold time for start condition (4us) */
2224         usec_delay(IXGBE_I2C_T_HD_STA);
2225
2226         ixgbe_lower_i2c_clk(hw, &i2cctl);
2227
2228         /* Minimum low period of clock is 4.7 us */
2229         usec_delay(IXGBE_I2C_T_LOW);
2230
2231 }
2232
2233 /**
2234  * ixgbe_i2c_stop - Sets I2C stop condition
2235  * @hw: pointer to hardware structure
2236  *
2237  * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2238  * Disables bit-bang mode and negates data output enable on X550
2239  * hardware.
2240  **/
2241 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2242 {
2243         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2244         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2245         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2246         u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2247
2248         DEBUGFUNC("ixgbe_i2c_stop");
2249
2250         /* Stop condition must begin with data low and clock high */
2251         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2252         ixgbe_raise_i2c_clk(hw, &i2cctl);
2253
2254         /* Setup time for stop condition (4us) */
2255         usec_delay(IXGBE_I2C_T_SU_STO);
2256
2257         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2258
2259         /* bus free time between stop and start (4.7us)*/
2260         usec_delay(IXGBE_I2C_T_BUF);
2261
2262         if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2263                 i2cctl &= ~bb_en_bit;
2264                 i2cctl |= data_oe_bit | clk_oe_bit;
2265                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2266                 IXGBE_WRITE_FLUSH(hw);
2267         }
2268 }
2269
2270 /**
2271  * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2272  * @hw: pointer to hardware structure
2273  * @data: data byte to clock in
2274  *
2275  * Clocks in one byte data via I2C data/clock
2276  **/
2277 STATIC void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2278 {
2279         s32 i;
2280         bool bit = 0;
2281
2282         DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2283
2284         *data = 0;
2285         for (i = 7; i >= 0; i--) {
2286                 ixgbe_clock_in_i2c_bit(hw, &bit);
2287                 *data |= bit << i;
2288         }
2289 }
2290
2291 /**
2292  * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2293  * @hw: pointer to hardware structure
2294  * @data: data byte clocked out
2295  *
2296  * Clocks out one byte data via I2C data/clock
2297  **/
2298 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2299 {
2300         s32 status = IXGBE_SUCCESS;
2301         s32 i;
2302         u32 i2cctl;
2303         bool bit;
2304
2305         DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2306
2307         for (i = 7; i >= 0; i--) {
2308                 bit = (data >> i) & 0x1;
2309                 status = ixgbe_clock_out_i2c_bit(hw, bit);
2310
2311                 if (status != IXGBE_SUCCESS)
2312                         break;
2313         }
2314
2315         /* Release SDA line (set high) */
2316         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2317         i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2318         i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2319         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2320         IXGBE_WRITE_FLUSH(hw);
2321
2322         return status;
2323 }
2324
2325 /**
2326  * ixgbe_get_i2c_ack - Polls for I2C ACK
2327  * @hw: pointer to hardware structure
2328  *
2329  * Clocks in/out one bit via I2C data/clock
2330  **/
2331 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2332 {
2333         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2334         s32 status = IXGBE_SUCCESS;
2335         u32 i = 0;
2336         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2337         u32 timeout = 10;
2338         bool ack = 1;
2339
2340         DEBUGFUNC("ixgbe_get_i2c_ack");
2341
2342         if (data_oe_bit) {
2343                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2344                 i2cctl |= data_oe_bit;
2345                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2346                 IXGBE_WRITE_FLUSH(hw);
2347         }
2348         ixgbe_raise_i2c_clk(hw, &i2cctl);
2349
2350         /* Minimum high period of clock is 4us */
2351         usec_delay(IXGBE_I2C_T_HIGH);
2352
2353         /* Poll for ACK.  Note that ACK in I2C spec is
2354          * transition from 1 to 0 */
2355         for (i = 0; i < timeout; i++) {
2356                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2357                 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2358
2359                 usec_delay(1);
2360                 if (!ack)
2361                         break;
2362         }
2363
2364         if (ack) {
2365                 DEBUGOUT("I2C ack was not received.\n");
2366                 status = IXGBE_ERR_I2C;
2367         }
2368
2369         ixgbe_lower_i2c_clk(hw, &i2cctl);
2370
2371         /* Minimum low period of clock is 4.7 us */
2372         usec_delay(IXGBE_I2C_T_LOW);
2373
2374         return status;
2375 }
2376
2377 /**
2378  * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2379  * @hw: pointer to hardware structure
2380  * @data: read data value
2381  *
2382  * Clocks in one bit via I2C data/clock
2383  **/
2384 STATIC void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2385 {
2386         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2387         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2388
2389         DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2390
2391         if (data_oe_bit) {
2392                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2393                 i2cctl |= data_oe_bit;
2394                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2395                 IXGBE_WRITE_FLUSH(hw);
2396         }
2397         ixgbe_raise_i2c_clk(hw, &i2cctl);
2398
2399         /* Minimum high period of clock is 4us */
2400         usec_delay(IXGBE_I2C_T_HIGH);
2401
2402         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2403         *data = ixgbe_get_i2c_data(hw, &i2cctl);
2404
2405         ixgbe_lower_i2c_clk(hw, &i2cctl);
2406
2407         /* Minimum low period of clock is 4.7 us */
2408         usec_delay(IXGBE_I2C_T_LOW);
2409 }
2410
2411 /**
2412  * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2413  * @hw: pointer to hardware structure
2414  * @data: data value to write
2415  *
2416  * Clocks out one bit via I2C data/clock
2417  **/
2418 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2419 {
2420         s32 status;
2421         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2422
2423         DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2424
2425         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2426         if (status == IXGBE_SUCCESS) {
2427                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2428
2429                 /* Minimum high period of clock is 4us */
2430                 usec_delay(IXGBE_I2C_T_HIGH);
2431
2432                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2433
2434                 /* Minimum low period of clock is 4.7 us.
2435                  * This also takes care of the data hold time.
2436                  */
2437                 usec_delay(IXGBE_I2C_T_LOW);
2438         } else {
2439                 status = IXGBE_ERR_I2C;
2440                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2441                              "I2C data was not set to %X\n", data);
2442         }
2443
2444         return status;
2445 }
2446
2447 /**
2448  * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2449  * @hw: pointer to hardware structure
2450  * @i2cctl: Current value of I2CCTL register
2451  *
2452  * Raises the I2C clock line '0'->'1'
2453  * Negates the I2C clock output enable on X550 hardware.
2454  **/
2455 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2456 {
2457         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2458         u32 i = 0;
2459         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2460         u32 i2cctl_r = 0;
2461
2462         DEBUGFUNC("ixgbe_raise_i2c_clk");
2463
2464         if (clk_oe_bit) {
2465                 *i2cctl |= clk_oe_bit;
2466                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2467         }
2468
2469         for (i = 0; i < timeout; i++) {
2470                 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2471
2472                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2473                 IXGBE_WRITE_FLUSH(hw);
2474                 /* SCL rise time (1000ns) */
2475                 usec_delay(IXGBE_I2C_T_RISE);
2476
2477                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2478                 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2479                         break;
2480         }
2481 }
2482
2483 /**
2484  * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2485  * @hw: pointer to hardware structure
2486  * @i2cctl: Current value of I2CCTL register
2487  *
2488  * Lowers the I2C clock line '1'->'0'
2489  * Asserts the I2C clock output enable on X550 hardware.
2490  **/
2491 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2492 {
2493         DEBUGFUNC("ixgbe_lower_i2c_clk");
2494
2495         *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2496         *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2497
2498         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2499         IXGBE_WRITE_FLUSH(hw);
2500
2501         /* SCL fall time (300ns) */
2502         usec_delay(IXGBE_I2C_T_FALL);
2503 }
2504
2505 /**
2506  * ixgbe_set_i2c_data - Sets the I2C data bit
2507  * @hw: pointer to hardware structure
2508  * @i2cctl: Current value of I2CCTL register
2509  * @data: I2C data value (0 or 1) to set
2510  *
2511  * Sets the I2C data bit
2512  * Asserts the I2C data output enable on X550 hardware.
2513  **/
2514 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2515 {
2516         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2517         s32 status = IXGBE_SUCCESS;
2518
2519         DEBUGFUNC("ixgbe_set_i2c_data");
2520
2521         if (data)
2522                 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2523         else
2524                 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2525         *i2cctl &= ~data_oe_bit;
2526
2527         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2528         IXGBE_WRITE_FLUSH(hw);
2529
2530         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2531         usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2532
2533         if (!data)      /* Can't verify data in this case */
2534                 return IXGBE_SUCCESS;
2535         if (data_oe_bit) {
2536                 *i2cctl |= data_oe_bit;
2537                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2538                 IXGBE_WRITE_FLUSH(hw);
2539         }
2540
2541         /* Verify data was set correctly */
2542         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2543         if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2544                 status = IXGBE_ERR_I2C;
2545                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2546                              "Error - I2C data was not set to %X.\n",
2547                              data);
2548         }
2549
2550         return status;
2551 }
2552
2553 /**
2554  * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2555  * @hw: pointer to hardware structure
2556  * @i2cctl: Current value of I2CCTL register
2557  *
2558  * Returns the I2C data bit value
2559  * Negates the I2C data output enable on X550 hardware.
2560  **/
2561 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2562 {
2563         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2564         bool data;
2565
2566         DEBUGFUNC("ixgbe_get_i2c_data");
2567
2568         if (data_oe_bit) {
2569                 *i2cctl |= data_oe_bit;
2570                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2571                 IXGBE_WRITE_FLUSH(hw);
2572                 usec_delay(IXGBE_I2C_T_FALL);
2573         }
2574
2575         if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2576                 data = 1;
2577         else
2578                 data = 0;
2579
2580         return data;
2581 }
2582
2583 /**
2584  * ixgbe_i2c_bus_clear - Clears the I2C bus
2585  * @hw: pointer to hardware structure
2586  *
2587  * Clears the I2C bus by sending nine clock pulses.
2588  * Used when data line is stuck low.
2589  **/
2590 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2591 {
2592         u32 i2cctl;
2593         u32 i;
2594
2595         DEBUGFUNC("ixgbe_i2c_bus_clear");
2596
2597         ixgbe_i2c_start(hw);
2598         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2599
2600         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2601
2602         for (i = 0; i < 9; i++) {
2603                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2604
2605                 /* Min high period of clock is 4us */
2606                 usec_delay(IXGBE_I2C_T_HIGH);
2607
2608                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2609
2610                 /* Min low period of clock is 4.7us*/
2611                 usec_delay(IXGBE_I2C_T_LOW);
2612         }
2613
2614         ixgbe_i2c_start(hw);
2615
2616         /* Put the i2c bus back to default state */
2617         ixgbe_i2c_stop(hw);
2618 }
2619
2620 /**
2621  * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2622  * @hw: pointer to hardware structure
2623  *
2624  * Checks if the LASI temp alarm status was triggered due to overtemp
2625  **/
2626 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2627 {
2628         s32 status = IXGBE_SUCCESS;
2629         u16 phy_data = 0;
2630
2631         DEBUGFUNC("ixgbe_tn_check_overtemp");
2632
2633         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2634                 goto out;
2635
2636         /* Check that the LASI temp alarm status was triggered */
2637         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2638                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2639
2640         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2641                 goto out;
2642
2643         status = IXGBE_ERR_OVERTEMP;
2644         ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2645 out:
2646         return status;
2647 }
2648
2649 /**
2650  * ixgbe_set_copper_phy_power - Control power for copper phy
2651  * @hw: pointer to hardware structure
2652  * @on: true for on, false for off
2653  */
2654 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2655 {
2656         u32 status;
2657         u16 reg;
2658
2659         if (!on && ixgbe_mng_present(hw))
2660                 return 0;
2661
2662         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2663                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2664                                       &reg);
2665         if (status)
2666                 return status;
2667
2668         if (on) {
2669                 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2670         } else {
2671                 if (ixgbe_check_reset_blocked(hw))
2672                         return 0;
2673                 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2674         }
2675
2676         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2677                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2678                                        reg);
2679         return status;
2680 }