1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_api.h"
35 #include "ixgbe_common.h"
36 #include "ixgbe_phy.h"
38 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
39 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
40 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
41 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
42 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
43 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
44 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
45 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
46 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
47 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
48 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
49 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
53 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
54 * @hw: pointer to the hardware structure
57 * Returns an error code on error.
59 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
63 status = ixgbe_clock_out_i2c_byte(hw, byte);
66 return ixgbe_get_i2c_ack(hw);
70 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
71 * @hw: pointer to the hardware structure
72 * @byte: pointer to a u8 to receive the byte
74 * Returns an error code on error.
76 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
80 status = ixgbe_clock_in_i2c_byte(hw, byte);
84 return ixgbe_clock_out_i2c_bit(hw, false);
88 * ixgbe_ones_comp_byte_add - Perform one's complement addition
92 * Returns one's complement 8-bit sum.
94 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
96 u16 sum = add1 + add2;
98 sum = (sum & 0xFF) + (sum >> 8);
103 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
104 * @hw: pointer to the hardware structure
105 * @addr: I2C bus address to read from
106 * @reg: I2C device register to read from
107 * @val: pointer to location to receive read value
108 * @lock: true if to take and release semaphore
110 * Returns an error code on error.
112 STATIC s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
113 u16 reg, u16 *val, bool lock)
115 u32 swfw_mask = hw->phy.phy_semaphore_mask;
124 if (hw->mac.type >= ixgbe_mac_X550)
126 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
127 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
130 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
131 return IXGBE_ERR_SWFW_SYNC;
133 /* Device Address and write indication */
134 if (ixgbe_out_i2c_byte_ack(hw, addr))
136 /* Write bits 14:8 */
137 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
140 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
143 if (ixgbe_out_i2c_byte_ack(hw, csum))
145 /* Re-start condition */
147 /* Device Address and read indication */
148 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
151 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
154 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
157 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
160 if (ixgbe_clock_out_i2c_bit(hw, false))
164 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
165 *val = (high_bits << 8) | low_bits;
169 ixgbe_i2c_bus_clear(hw);
171 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
173 if (retry < max_retry)
174 DEBUGOUT("I2C byte read combined error - Retrying.\n");
176 DEBUGOUT("I2C byte read combined error.\n");
177 } while (retry < max_retry);
179 return IXGBE_ERR_I2C;
183 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
184 * @hw: pointer to the hardware structure
185 * @addr: I2C bus address to read from
186 * @reg: I2C device register to read from
187 * @val: pointer to location to receive read value
189 * Returns an error code on error.
191 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
194 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
198 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
199 * @hw: pointer to the hardware structure
200 * @addr: I2C bus address to read from
201 * @reg: I2C device register to read from
202 * @val: pointer to location to receive read value
204 * Returns an error code on error.
207 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
210 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
214 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
215 * @hw: pointer to the hardware structure
216 * @addr: I2C bus address to write to
217 * @reg: I2C device register to write to
218 * @val: value to write
219 * @lock: true if to take and release semaphore
221 * Returns an error code on error.
223 STATIC s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
224 u16 reg, u16 val, bool lock)
226 u32 swfw_mask = hw->phy.phy_semaphore_mask;
232 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
233 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
234 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
235 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
238 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
239 return IXGBE_ERR_SWFW_SYNC;
241 /* Device Address and write indication */
242 if (ixgbe_out_i2c_byte_ack(hw, addr))
244 /* Write bits 14:8 */
245 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
248 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
250 /* Write data 15:8 */
251 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
254 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
257 if (ixgbe_out_i2c_byte_ack(hw, csum))
261 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
265 ixgbe_i2c_bus_clear(hw);
267 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
269 if (retry < max_retry)
270 DEBUGOUT("I2C byte write combined error - Retrying.\n");
272 DEBUGOUT("I2C byte write combined error.\n");
273 } while (retry < max_retry);
275 return IXGBE_ERR_I2C;
279 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
280 * @hw: pointer to the hardware structure
281 * @addr: I2C bus address to write to
282 * @reg: I2C device register to write to
283 * @val: value to write
285 * Returns an error code on error.
287 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
288 u8 addr, u16 reg, u16 val)
290 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
294 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
295 * @hw: pointer to the hardware structure
296 * @addr: I2C bus address to write to
297 * @reg: I2C device register to write to
298 * @val: value to write
300 * Returns an error code on error.
303 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
304 u8 addr, u16 reg, u16 val)
306 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
310 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
311 * @hw: pointer to the hardware structure
313 * Initialize the function pointers.
315 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
317 struct ixgbe_phy_info *phy = &hw->phy;
319 DEBUGFUNC("ixgbe_init_phy_ops_generic");
322 phy->ops.identify = ixgbe_identify_phy_generic;
323 phy->ops.reset = ixgbe_reset_phy_generic;
324 phy->ops.read_reg = ixgbe_read_phy_reg_generic;
325 phy->ops.write_reg = ixgbe_write_phy_reg_generic;
326 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
327 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
328 phy->ops.setup_link = ixgbe_setup_phy_link_generic;
329 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
330 phy->ops.check_link = NULL;
331 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
332 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
333 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
334 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
335 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
336 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
337 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
338 phy->ops.identify_sfp = ixgbe_identify_module_generic;
339 phy->sfp_type = ixgbe_sfp_type_unknown;
340 phy->ops.read_i2c_combined = ixgbe_read_i2c_combined_generic;
341 phy->ops.write_i2c_combined = ixgbe_write_i2c_combined_generic;
342 phy->ops.read_i2c_combined_unlocked =
343 ixgbe_read_i2c_combined_generic_unlocked;
344 phy->ops.write_i2c_combined_unlocked =
345 ixgbe_write_i2c_combined_generic_unlocked;
346 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
347 phy->ops.write_i2c_byte_unlocked =
348 ixgbe_write_i2c_byte_generic_unlocked;
349 phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
350 return IXGBE_SUCCESS;
354 * ixgbe_identify_phy_generic - Get physical layer module
355 * @hw: pointer to hardware structure
357 * Determines the physical layer module found on the current adapter.
359 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
361 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
365 DEBUGFUNC("ixgbe_identify_phy_generic");
367 if (!hw->phy.phy_semaphore_mask) {
369 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
371 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
374 if (hw->phy.type == ixgbe_phy_unknown) {
375 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
376 if (ixgbe_validate_phy_addr(hw, phy_addr)) {
377 hw->phy.addr = phy_addr;
378 ixgbe_get_phy_id(hw);
380 ixgbe_get_phy_type_from_id(hw->phy.id);
382 if (hw->phy.type == ixgbe_phy_unknown) {
383 hw->phy.ops.read_reg(hw,
384 IXGBE_MDIO_PHY_EXT_ABILITY,
385 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
388 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
389 IXGBE_MDIO_PHY_1000BASET_ABILITY))
391 ixgbe_phy_cu_unknown;
397 status = IXGBE_SUCCESS;
402 /* Certain media types do not have a phy so an address will not
403 * be found and the code will take this path. Caller has to
404 * decide if it is an error or not.
406 if (status != IXGBE_SUCCESS) {
410 status = IXGBE_SUCCESS;
417 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
418 * @hw: pointer to the hardware structure
420 * This function checks the MMNGC.MNG_VETO bit to see if there are
421 * any constraints on link from manageability. For MAC's that don't
422 * have this bit just return faluse since the link can not be blocked
425 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
429 DEBUGFUNC("ixgbe_check_reset_blocked");
431 /* If we don't have this bit, it can't be blocking */
432 if (hw->mac.type == ixgbe_mac_82598EB)
435 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
436 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
437 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
438 "MNG_VETO bit detected.\n");
446 * ixgbe_validate_phy_addr - Determines phy address is valid
447 * @hw: pointer to hardware structure
450 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
455 DEBUGFUNC("ixgbe_validate_phy_addr");
457 hw->phy.addr = phy_addr;
458 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
459 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
461 if (phy_id != 0xFFFF && phy_id != 0x0)
468 * ixgbe_get_phy_id - Get the phy type
469 * @hw: pointer to hardware structure
472 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
478 DEBUGFUNC("ixgbe_get_phy_id");
480 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
481 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
484 if (status == IXGBE_SUCCESS) {
485 hw->phy.id = (u32)(phy_id_high << 16);
486 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
487 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
489 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
490 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
496 * ixgbe_get_phy_type_from_id - Get the phy type
497 * @phy_id: PHY ID information
500 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
502 enum ixgbe_phy_type phy_type;
504 DEBUGFUNC("ixgbe_get_phy_type_from_id");
508 phy_type = ixgbe_phy_tn;
514 phy_type = ixgbe_phy_aq;
517 phy_type = ixgbe_phy_qt;
520 phy_type = ixgbe_phy_nl;
523 phy_type = ixgbe_phy_x550em_ext_t;
526 phy_type = ixgbe_phy_unknown;
533 * ixgbe_reset_phy_generic - Performs a PHY reset
534 * @hw: pointer to hardware structure
536 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
540 s32 status = IXGBE_SUCCESS;
542 DEBUGFUNC("ixgbe_reset_phy_generic");
544 if (hw->phy.type == ixgbe_phy_unknown)
545 status = ixgbe_identify_phy_generic(hw);
547 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
550 /* Don't reset PHY if it's shut down due to overtemp. */
551 if (!hw->phy.reset_if_overtemp &&
552 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
555 /* Blocked by MNG FW so bail */
556 if (ixgbe_check_reset_blocked(hw))
560 * Perform soft PHY reset to the PHY_XS.
561 * This will cause a soft reset to the PHY
563 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
564 IXGBE_MDIO_PHY_XS_DEV_TYPE,
565 IXGBE_MDIO_PHY_XS_RESET);
568 * Poll for reset bit to self-clear indicating reset is complete.
569 * Some PHYs could take up to 3 seconds to complete and need about
570 * 1.7 usec delay after the reset is complete.
572 for (i = 0; i < 30; i++) {
574 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
575 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
576 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
582 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
583 status = IXGBE_ERR_RESET_FAILED;
584 ERROR_REPORT1(IXGBE_ERROR_POLLING,
585 "PHY reset polling failed to complete.\n");
593 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
595 * @hw: pointer to hardware structure
596 * @reg_addr: 32 bit address of PHY register to read
597 * @phy_data: Pointer to read data from PHY register
599 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
602 u32 i, data, command;
604 /* Setup and write the address cycle command */
605 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
606 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
607 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
608 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
610 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
613 * Check every 10 usec to see if the address cycle completed.
614 * The MDI Command bit will clear when the operation is
617 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
620 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
621 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
626 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
627 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
628 return IXGBE_ERR_PHY;
632 * Address cycle complete, setup and write the read
635 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
636 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
637 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
638 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
640 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
643 * Check every 10 usec to see if the address cycle
644 * completed. The MDI Command bit will clear when the
645 * operation is complete
647 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
650 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
651 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
655 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
656 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
657 return IXGBE_ERR_PHY;
661 * Read operation is complete. Get the data
664 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
665 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
666 *phy_data = (u16)(data);
668 return IXGBE_SUCCESS;
672 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
673 * using the SWFW lock - this function is needed in most cases
674 * @hw: pointer to hardware structure
675 * @reg_addr: 32 bit address of PHY register to read
676 * @phy_data: Pointer to read data from PHY register
678 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
679 u32 device_type, u16 *phy_data)
682 u32 gssr = hw->phy.phy_semaphore_mask;
684 DEBUGFUNC("ixgbe_read_phy_reg_generic");
686 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
687 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
689 hw->mac.ops.release_swfw_sync(hw, gssr);
691 status = IXGBE_ERR_SWFW_SYNC;
698 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
700 * @hw: pointer to hardware structure
701 * @reg_addr: 32 bit PHY register to write
702 * @device_type: 5 bit device type
703 * @phy_data: Data to write to the PHY register
705 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
706 u32 device_type, u16 phy_data)
710 /* Put the data in the MDI single read and write data register*/
711 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
713 /* Setup and write the address cycle command */
714 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
715 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
716 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
717 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
719 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
722 * Check every 10 usec to see if the address cycle completed.
723 * The MDI Command bit will clear when the operation is
726 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
729 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
730 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
734 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
735 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
736 return IXGBE_ERR_PHY;
740 * Address cycle complete, setup and write the write
743 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
744 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
745 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
746 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
748 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
751 * Check every 10 usec to see if the address cycle
752 * completed. The MDI Command bit will clear when the
753 * operation is complete
755 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
758 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
759 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
763 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
764 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
765 return IXGBE_ERR_PHY;
768 return IXGBE_SUCCESS;
772 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
773 * using SWFW lock- this function is needed in most cases
774 * @hw: pointer to hardware structure
775 * @reg_addr: 32 bit PHY register to write
776 * @device_type: 5 bit device type
777 * @phy_data: Data to write to the PHY register
779 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
780 u32 device_type, u16 phy_data)
783 u32 gssr = hw->phy.phy_semaphore_mask;
785 DEBUGFUNC("ixgbe_write_phy_reg_generic");
787 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
788 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
790 hw->mac.ops.release_swfw_sync(hw, gssr);
792 status = IXGBE_ERR_SWFW_SYNC;
799 * ixgbe_setup_phy_link_generic - Set and restart auto-neg
800 * @hw: pointer to hardware structure
802 * Restart auto-negotiation and PHY and waits for completion.
804 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
806 s32 status = IXGBE_SUCCESS;
807 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
808 bool autoneg = false;
809 ixgbe_link_speed speed;
811 DEBUGFUNC("ixgbe_setup_phy_link_generic");
813 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
815 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
816 /* Set or unset auto-negotiation 10G advertisement */
817 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
818 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
821 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
822 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
823 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
825 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
826 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
830 if (hw->mac.type == ixgbe_mac_X550) {
831 if (speed & IXGBE_LINK_SPEED_5GB_FULL) {
832 /* Set or unset auto-negotiation 5G advertisement */
833 hw->phy.ops.read_reg(hw,
834 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
835 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
838 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
839 if (hw->phy.autoneg_advertised &
840 IXGBE_LINK_SPEED_5GB_FULL)
841 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
843 hw->phy.ops.write_reg(hw,
844 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
845 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
849 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) {
850 /* Set or unset auto-negotiation 2.5G advertisement */
851 hw->phy.ops.read_reg(hw,
852 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
853 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
856 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
857 if (hw->phy.autoneg_advertised &
858 IXGBE_LINK_SPEED_2_5GB_FULL)
859 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
861 hw->phy.ops.write_reg(hw,
862 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
863 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
868 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
869 /* Set or unset auto-negotiation 1G advertisement */
870 hw->phy.ops.read_reg(hw,
871 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
872 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
875 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
876 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
877 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
879 hw->phy.ops.write_reg(hw,
880 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
881 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
885 if (speed & IXGBE_LINK_SPEED_100_FULL) {
886 /* Set or unset auto-negotiation 100M advertisement */
887 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
888 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
891 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
892 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
893 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
894 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
896 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
897 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
901 /* Blocked by MNG FW so don't reset PHY */
902 if (ixgbe_check_reset_blocked(hw))
905 /* Restart PHY auto-negotiation. */
906 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
907 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
909 autoneg_reg |= IXGBE_MII_RESTART;
911 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
912 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
918 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
919 * @hw: pointer to hardware structure
920 * @speed: new link speed
922 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
923 ixgbe_link_speed speed,
924 bool autoneg_wait_to_complete)
926 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
928 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
931 * Clear autoneg_advertised and set new values based on input link
934 hw->phy.autoneg_advertised = 0;
936 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
937 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
939 if (speed & IXGBE_LINK_SPEED_5GB_FULL)
940 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
942 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
943 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
945 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
946 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
948 if (speed & IXGBE_LINK_SPEED_100_FULL)
949 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
951 /* Setup link based on the new speed settings */
952 ixgbe_setup_phy_link(hw);
954 return IXGBE_SUCCESS;
958 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
959 * @hw: pointer to hardware structure
961 * Determines the supported link capabilities by reading the PHY auto
962 * negotiation register.
964 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
969 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
970 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
975 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
976 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
977 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
978 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
979 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
980 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
982 switch (hw->mac.type) {
984 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
985 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
987 case ixgbe_mac_X550EM_x:
988 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
998 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
999 * @hw: pointer to hardware structure
1000 * @speed: pointer to link speed
1001 * @autoneg: boolean auto-negotiation value
1003 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
1004 ixgbe_link_speed *speed,
1007 s32 status = IXGBE_SUCCESS;
1009 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
1012 if (!hw->phy.speeds_supported)
1013 status = ixgbe_get_copper_speeds_supported(hw);
1015 *speed = hw->phy.speeds_supported;
1020 * ixgbe_check_phy_link_tnx - Determine link and speed status
1021 * @hw: pointer to hardware structure
1023 * Reads the VS1 register to determine if link is up and the current speed for
1026 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1029 s32 status = IXGBE_SUCCESS;
1031 u32 max_time_out = 10;
1036 DEBUGFUNC("ixgbe_check_phy_link_tnx");
1038 /* Initialize speed and link to default case */
1040 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1043 * Check current speed and link status of the PHY register.
1044 * This is a vendor specific register and may have to
1045 * be changed for other copper PHYs.
1047 for (time_out = 0; time_out < max_time_out; time_out++) {
1049 status = hw->phy.ops.read_reg(hw,
1050 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1051 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1053 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1054 phy_speed = phy_data &
1055 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1056 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1059 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1060 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1069 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1070 * @hw: pointer to hardware structure
1072 * Restart auto-negotiation and PHY and waits for completion.
1074 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1076 s32 status = IXGBE_SUCCESS;
1077 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1078 bool autoneg = false;
1079 ixgbe_link_speed speed;
1081 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1083 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1085 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1086 /* Set or unset auto-negotiation 10G advertisement */
1087 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1088 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1091 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1092 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1093 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1095 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1096 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1100 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1101 /* Set or unset auto-negotiation 1G advertisement */
1102 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1103 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1106 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1107 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1108 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1110 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1111 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1115 if (speed & IXGBE_LINK_SPEED_100_FULL) {
1116 /* Set or unset auto-negotiation 100M advertisement */
1117 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1118 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1121 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1122 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1123 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1125 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1126 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1130 /* Blocked by MNG FW so don't reset PHY */
1131 if (ixgbe_check_reset_blocked(hw))
1134 /* Restart PHY auto-negotiation. */
1135 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1136 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1138 autoneg_reg |= IXGBE_MII_RESTART;
1140 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1141 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1147 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1148 * @hw: pointer to hardware structure
1149 * @firmware_version: pointer to the PHY Firmware Version
1151 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1152 u16 *firmware_version)
1156 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1158 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1159 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1166 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1167 * @hw: pointer to hardware structure
1168 * @firmware_version: pointer to the PHY Firmware Version
1170 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1171 u16 *firmware_version)
1175 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1177 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1178 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1185 * ixgbe_reset_phy_nl - Performs a PHY reset
1186 * @hw: pointer to hardware structure
1188 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1190 u16 phy_offset, control, eword, edata, block_crc;
1191 bool end_data = false;
1192 u16 list_offset, data_offset;
1194 s32 ret_val = IXGBE_SUCCESS;
1197 DEBUGFUNC("ixgbe_reset_phy_nl");
1199 /* Blocked by MNG FW so bail */
1200 if (ixgbe_check_reset_blocked(hw))
1203 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1204 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1206 /* reset the PHY and poll for completion */
1207 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1208 IXGBE_MDIO_PHY_XS_DEV_TYPE,
1209 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1211 for (i = 0; i < 100; i++) {
1212 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1213 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1214 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1219 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1220 DEBUGOUT("PHY reset did not complete.\n");
1221 ret_val = IXGBE_ERR_PHY;
1225 /* Get init offsets */
1226 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1228 if (ret_val != IXGBE_SUCCESS)
1231 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1235 * Read control word from PHY init contents offset
1237 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1240 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1241 IXGBE_CONTROL_SHIFT_NL;
1242 edata = eword & IXGBE_DATA_MASK_NL;
1244 case IXGBE_DELAY_NL:
1246 DEBUGOUT1("DELAY: %d MS\n", edata);
1250 DEBUGOUT("DATA:\n");
1252 ret_val = hw->eeprom.ops.read(hw, data_offset,
1257 for (i = 0; i < edata; i++) {
1258 ret_val = hw->eeprom.ops.read(hw, data_offset,
1262 hw->phy.ops.write_reg(hw, phy_offset,
1263 IXGBE_TWINAX_DEV, eword);
1264 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1270 case IXGBE_CONTROL_NL:
1272 DEBUGOUT("CONTROL:\n");
1273 if (edata == IXGBE_CONTROL_EOL_NL) {
1276 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1279 DEBUGOUT("Bad control value\n");
1280 ret_val = IXGBE_ERR_PHY;
1285 DEBUGOUT("Bad control type\n");
1286 ret_val = IXGBE_ERR_PHY;
1295 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1296 "eeprom read at offset %d failed", data_offset);
1297 return IXGBE_ERR_PHY;
1301 * ixgbe_identify_module_generic - Identifies module type
1302 * @hw: pointer to hardware structure
1304 * Determines HW type and calls appropriate function.
1306 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1308 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1310 DEBUGFUNC("ixgbe_identify_module_generic");
1312 switch (hw->mac.ops.get_media_type(hw)) {
1313 case ixgbe_media_type_fiber:
1314 status = ixgbe_identify_sfp_module_generic(hw);
1317 case ixgbe_media_type_fiber_qsfp:
1318 status = ixgbe_identify_qsfp_module_generic(hw);
1322 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1323 status = IXGBE_ERR_SFP_NOT_PRESENT;
1331 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1332 * @hw: pointer to hardware structure
1334 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1336 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1338 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1340 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1342 u8 comp_codes_1g = 0;
1343 u8 comp_codes_10g = 0;
1344 u8 oui_bytes[3] = {0, 0, 0};
1347 u16 enforce_sfp = 0;
1349 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1351 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1352 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1353 status = IXGBE_ERR_SFP_NOT_PRESENT;
1357 /* LAN ID is needed for I2C access */
1358 hw->mac.ops.set_lan_id(hw);
1360 status = hw->phy.ops.read_i2c_eeprom(hw,
1361 IXGBE_SFF_IDENTIFIER,
1364 if (status != IXGBE_SUCCESS)
1365 goto err_read_i2c_eeprom;
1367 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1368 hw->phy.type = ixgbe_phy_sfp_unsupported;
1369 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1371 status = hw->phy.ops.read_i2c_eeprom(hw,
1372 IXGBE_SFF_1GBE_COMP_CODES,
1375 if (status != IXGBE_SUCCESS)
1376 goto err_read_i2c_eeprom;
1378 status = hw->phy.ops.read_i2c_eeprom(hw,
1379 IXGBE_SFF_10GBE_COMP_CODES,
1382 if (status != IXGBE_SUCCESS)
1383 goto err_read_i2c_eeprom;
1384 status = hw->phy.ops.read_i2c_eeprom(hw,
1385 IXGBE_SFF_CABLE_TECHNOLOGY,
1388 if (status != IXGBE_SUCCESS)
1389 goto err_read_i2c_eeprom;
1396 * 3 SFP_DA_CORE0 - 82599-specific
1397 * 4 SFP_DA_CORE1 - 82599-specific
1398 * 5 SFP_SR/LR_CORE0 - 82599-specific
1399 * 6 SFP_SR/LR_CORE1 - 82599-specific
1400 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1401 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1402 * 9 SFP_1g_cu_CORE0 - 82599-specific
1403 * 10 SFP_1g_cu_CORE1 - 82599-specific
1404 * 11 SFP_1g_sx_CORE0 - 82599-specific
1405 * 12 SFP_1g_sx_CORE1 - 82599-specific
1407 if (hw->mac.type == ixgbe_mac_82598EB) {
1408 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1409 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1410 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1411 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1412 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1413 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1415 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1417 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1418 if (hw->bus.lan_id == 0)
1420 ixgbe_sfp_type_da_cu_core0;
1423 ixgbe_sfp_type_da_cu_core1;
1424 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1425 hw->phy.ops.read_i2c_eeprom(
1426 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1429 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1430 if (hw->bus.lan_id == 0)
1432 ixgbe_sfp_type_da_act_lmt_core0;
1435 ixgbe_sfp_type_da_act_lmt_core1;
1438 ixgbe_sfp_type_unknown;
1440 } else if (comp_codes_10g &
1441 (IXGBE_SFF_10GBASESR_CAPABLE |
1442 IXGBE_SFF_10GBASELR_CAPABLE)) {
1443 if (hw->bus.lan_id == 0)
1445 ixgbe_sfp_type_srlr_core0;
1448 ixgbe_sfp_type_srlr_core1;
1449 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1450 if (hw->bus.lan_id == 0)
1452 ixgbe_sfp_type_1g_cu_core0;
1455 ixgbe_sfp_type_1g_cu_core1;
1456 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1457 if (hw->bus.lan_id == 0)
1459 ixgbe_sfp_type_1g_sx_core0;
1462 ixgbe_sfp_type_1g_sx_core1;
1463 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1464 if (hw->bus.lan_id == 0)
1466 ixgbe_sfp_type_1g_lx_core0;
1469 ixgbe_sfp_type_1g_lx_core1;
1471 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1475 if (hw->phy.sfp_type != stored_sfp_type)
1476 hw->phy.sfp_setup_needed = true;
1478 /* Determine if the SFP+ PHY is dual speed or not. */
1479 hw->phy.multispeed_fiber = false;
1480 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1481 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1482 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1483 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1484 hw->phy.multispeed_fiber = true;
1486 /* Determine PHY vendor */
1487 if (hw->phy.type != ixgbe_phy_nl) {
1488 hw->phy.id = identifier;
1489 status = hw->phy.ops.read_i2c_eeprom(hw,
1490 IXGBE_SFF_VENDOR_OUI_BYTE0,
1493 if (status != IXGBE_SUCCESS)
1494 goto err_read_i2c_eeprom;
1496 status = hw->phy.ops.read_i2c_eeprom(hw,
1497 IXGBE_SFF_VENDOR_OUI_BYTE1,
1500 if (status != IXGBE_SUCCESS)
1501 goto err_read_i2c_eeprom;
1503 status = hw->phy.ops.read_i2c_eeprom(hw,
1504 IXGBE_SFF_VENDOR_OUI_BYTE2,
1507 if (status != IXGBE_SUCCESS)
1508 goto err_read_i2c_eeprom;
1511 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1512 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1513 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1515 switch (vendor_oui) {
1516 case IXGBE_SFF_VENDOR_OUI_TYCO:
1517 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1519 ixgbe_phy_sfp_passive_tyco;
1521 case IXGBE_SFF_VENDOR_OUI_FTL:
1522 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1523 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1525 hw->phy.type = ixgbe_phy_sfp_ftl;
1527 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1528 hw->phy.type = ixgbe_phy_sfp_avago;
1530 case IXGBE_SFF_VENDOR_OUI_INTEL:
1531 hw->phy.type = ixgbe_phy_sfp_intel;
1534 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1536 ixgbe_phy_sfp_passive_unknown;
1537 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1539 ixgbe_phy_sfp_active_unknown;
1541 hw->phy.type = ixgbe_phy_sfp_unknown;
1546 /* Allow any DA cable vendor */
1547 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1548 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1549 status = IXGBE_SUCCESS;
1553 /* Verify supported 1G SFP modules */
1554 if (comp_codes_10g == 0 &&
1555 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1556 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1557 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1558 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1559 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1560 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1561 hw->phy.type = ixgbe_phy_sfp_unsupported;
1562 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1566 /* Anything else 82598-based is supported */
1567 if (hw->mac.type == ixgbe_mac_82598EB) {
1568 status = IXGBE_SUCCESS;
1572 ixgbe_get_device_caps(hw, &enforce_sfp);
1573 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1574 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1575 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1576 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1577 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1578 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1579 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1580 /* Make sure we're a supported PHY type */
1581 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1582 status = IXGBE_SUCCESS;
1584 if (hw->allow_unsupported_sfp == true) {
1585 EWARN(hw, "WARNING: Intel (R) Network "
1586 "Connections are quality tested "
1587 "using Intel (R) Ethernet Optics."
1588 " Using untested modules is not "
1589 "supported and may cause unstable"
1590 " operation or damage to the "
1591 "module or the adapter. Intel "
1592 "Corporation is not responsible "
1593 "for any harm caused by using "
1594 "untested modules.\n", status);
1595 status = IXGBE_SUCCESS;
1597 DEBUGOUT("SFP+ module not supported\n");
1599 ixgbe_phy_sfp_unsupported;
1600 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1604 status = IXGBE_SUCCESS;
1611 err_read_i2c_eeprom:
1612 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1613 if (hw->phy.type != ixgbe_phy_nl) {
1615 hw->phy.type = ixgbe_phy_unknown;
1617 return IXGBE_ERR_SFP_NOT_PRESENT;
1621 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1622 * @hw: pointer to hardware structure
1624 * Determines physical layer capabilities of the current SFP.
1626 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1628 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1629 u8 comp_codes_10g = 0;
1630 u8 comp_codes_1g = 0;
1632 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1634 hw->phy.ops.identify_sfp(hw);
1635 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1636 return physical_layer;
1638 switch (hw->phy.type) {
1639 case ixgbe_phy_sfp_passive_tyco:
1640 case ixgbe_phy_sfp_passive_unknown:
1641 case ixgbe_phy_qsfp_passive_unknown:
1642 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1644 case ixgbe_phy_sfp_ftl_active:
1645 case ixgbe_phy_sfp_active_unknown:
1646 case ixgbe_phy_qsfp_active_unknown:
1647 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1649 case ixgbe_phy_sfp_avago:
1650 case ixgbe_phy_sfp_ftl:
1651 case ixgbe_phy_sfp_intel:
1652 case ixgbe_phy_sfp_unknown:
1653 hw->phy.ops.read_i2c_eeprom(hw,
1654 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1655 hw->phy.ops.read_i2c_eeprom(hw,
1656 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1657 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1658 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1659 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1660 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1661 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1662 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1663 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1664 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1666 case ixgbe_phy_qsfp_intel:
1667 case ixgbe_phy_qsfp_unknown:
1668 hw->phy.ops.read_i2c_eeprom(hw,
1669 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1670 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1671 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1672 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1673 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1679 return physical_layer;
1683 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1684 * @hw: pointer to hardware structure
1686 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1688 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1690 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1692 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1694 u8 comp_codes_1g = 0;
1695 u8 comp_codes_10g = 0;
1696 u8 oui_bytes[3] = {0, 0, 0};
1697 u16 enforce_sfp = 0;
1699 u8 cable_length = 0;
1701 bool active_cable = false;
1703 DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1705 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1706 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1707 status = IXGBE_ERR_SFP_NOT_PRESENT;
1711 /* LAN ID is needed for I2C access */
1712 hw->mac.ops.set_lan_id(hw);
1714 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1717 if (status != IXGBE_SUCCESS)
1718 goto err_read_i2c_eeprom;
1720 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1721 hw->phy.type = ixgbe_phy_sfp_unsupported;
1722 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1726 hw->phy.id = identifier;
1728 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1731 if (status != IXGBE_SUCCESS)
1732 goto err_read_i2c_eeprom;
1734 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1737 if (status != IXGBE_SUCCESS)
1738 goto err_read_i2c_eeprom;
1740 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1741 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1742 if (hw->bus.lan_id == 0)
1743 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1745 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1746 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1747 IXGBE_SFF_10GBASELR_CAPABLE)) {
1748 if (hw->bus.lan_id == 0)
1749 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1751 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1753 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1754 active_cable = true;
1756 if (!active_cable) {
1757 /* check for active DA cables that pre-date
1759 hw->phy.ops.read_i2c_eeprom(hw,
1760 IXGBE_SFF_QSFP_CONNECTOR,
1763 hw->phy.ops.read_i2c_eeprom(hw,
1764 IXGBE_SFF_QSFP_CABLE_LENGTH,
1767 hw->phy.ops.read_i2c_eeprom(hw,
1768 IXGBE_SFF_QSFP_DEVICE_TECH,
1772 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1773 (cable_length > 0) &&
1774 ((device_tech >> 4) ==
1775 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1776 active_cable = true;
1780 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1781 if (hw->bus.lan_id == 0)
1783 ixgbe_sfp_type_da_act_lmt_core0;
1786 ixgbe_sfp_type_da_act_lmt_core1;
1788 /* unsupported module type */
1789 hw->phy.type = ixgbe_phy_sfp_unsupported;
1790 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1795 if (hw->phy.sfp_type != stored_sfp_type)
1796 hw->phy.sfp_setup_needed = true;
1798 /* Determine if the QSFP+ PHY is dual speed or not. */
1799 hw->phy.multispeed_fiber = false;
1800 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1801 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1802 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1803 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1804 hw->phy.multispeed_fiber = true;
1806 /* Determine PHY vendor for optical modules */
1807 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1808 IXGBE_SFF_10GBASELR_CAPABLE)) {
1809 status = hw->phy.ops.read_i2c_eeprom(hw,
1810 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1813 if (status != IXGBE_SUCCESS)
1814 goto err_read_i2c_eeprom;
1816 status = hw->phy.ops.read_i2c_eeprom(hw,
1817 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1820 if (status != IXGBE_SUCCESS)
1821 goto err_read_i2c_eeprom;
1823 status = hw->phy.ops.read_i2c_eeprom(hw,
1824 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1827 if (status != IXGBE_SUCCESS)
1828 goto err_read_i2c_eeprom;
1831 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1832 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1833 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1835 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1836 hw->phy.type = ixgbe_phy_qsfp_intel;
1838 hw->phy.type = ixgbe_phy_qsfp_unknown;
1840 ixgbe_get_device_caps(hw, &enforce_sfp);
1841 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1842 /* Make sure we're a supported PHY type */
1843 if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1844 status = IXGBE_SUCCESS;
1846 if (hw->allow_unsupported_sfp == true) {
1847 EWARN(hw, "WARNING: Intel (R) Network "
1848 "Connections are quality tested "
1849 "using Intel (R) Ethernet Optics."
1850 " Using untested modules is not "
1851 "supported and may cause unstable"
1852 " operation or damage to the "
1853 "module or the adapter. Intel "
1854 "Corporation is not responsible "
1855 "for any harm caused by using "
1856 "untested modules.\n", status);
1857 status = IXGBE_SUCCESS;
1859 DEBUGOUT("QSFP module not supported\n");
1861 ixgbe_phy_sfp_unsupported;
1862 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1866 status = IXGBE_SUCCESS;
1873 err_read_i2c_eeprom:
1874 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1876 hw->phy.type = ixgbe_phy_unknown;
1878 return IXGBE_ERR_SFP_NOT_PRESENT;
1883 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1884 * @hw: pointer to hardware structure
1885 * @list_offset: offset to the SFP ID list
1886 * @data_offset: offset to the SFP data block
1888 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1889 * so it returns the offsets to the phy init sequence block.
1891 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1896 u16 sfp_type = hw->phy.sfp_type;
1898 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1900 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1901 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1903 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1904 return IXGBE_ERR_SFP_NOT_PRESENT;
1906 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1907 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1908 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1911 * Limiting active cables and 1G Phys must be initialized as
1914 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1915 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1916 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1917 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1918 sfp_type = ixgbe_sfp_type_srlr_core0;
1919 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1920 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1921 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1922 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1923 sfp_type = ixgbe_sfp_type_srlr_core1;
1925 /* Read offset to PHY init contents */
1926 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1927 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1928 "eeprom read at offset %d failed",
1929 IXGBE_PHY_INIT_OFFSET_NL);
1930 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1933 if ((!*list_offset) || (*list_offset == 0xFFFF))
1934 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1936 /* Shift offset to first ID word */
1940 * Find the matching SFP ID in the EEPROM
1941 * and program the init sequence
1943 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1946 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1947 if (sfp_id == sfp_type) {
1949 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1951 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1952 DEBUGOUT("SFP+ module not supported\n");
1953 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1958 (*list_offset) += 2;
1959 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1964 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1965 DEBUGOUT("No matching SFP+ module found\n");
1966 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1969 return IXGBE_SUCCESS;
1972 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1973 "eeprom read at offset %d failed", *list_offset);
1974 return IXGBE_ERR_PHY;
1978 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1979 * @hw: pointer to hardware structure
1980 * @byte_offset: EEPROM byte offset to read
1981 * @eeprom_data: value read
1983 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1985 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1988 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1990 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1991 IXGBE_I2C_EEPROM_DEV_ADDR,
1996 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1997 * @hw: pointer to hardware structure
1998 * @byte_offset: byte offset at address 0xA2
1999 * @eeprom_data: value read
2001 * Performs byte read operation to SFP module's SFF-8472 data over I2C
2003 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
2006 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
2007 IXGBE_I2C_EEPROM_DEV_ADDR2,
2012 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
2013 * @hw: pointer to hardware structure
2014 * @byte_offset: EEPROM byte offset to write
2015 * @eeprom_data: value to write
2017 * Performs byte write operation to SFP module's EEPROM over I2C interface.
2019 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
2022 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
2024 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
2025 IXGBE_I2C_EEPROM_DEV_ADDR,
2030 * ixgbe_is_sfp_probe - Returns true if SFP is being detected
2031 * @hw: pointer to hardware structure
2032 * @offset: eeprom offset to be read
2033 * @addr: I2C address to be read
2035 STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
2037 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
2038 offset == IXGBE_SFF_IDENTIFIER &&
2039 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2045 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
2046 * @hw: pointer to hardware structure
2047 * @byte_offset: byte offset to read
2049 * @lock: true if to take and release semaphore
2051 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2052 * a specified device address.
2054 STATIC s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2055 u8 dev_addr, u8 *data, bool lock)
2060 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2064 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2066 if (hw->mac.type >= ixgbe_mac_X550)
2068 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2069 max_retry = IXGBE_SFP_DETECT_RETRIES;
2072 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2073 return IXGBE_ERR_SWFW_SYNC;
2075 ixgbe_i2c_start(hw);
2077 /* Device Address and write indication */
2078 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2079 if (status != IXGBE_SUCCESS)
2082 status = ixgbe_get_i2c_ack(hw);
2083 if (status != IXGBE_SUCCESS)
2086 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2087 if (status != IXGBE_SUCCESS)
2090 status = ixgbe_get_i2c_ack(hw);
2091 if (status != IXGBE_SUCCESS)
2094 ixgbe_i2c_start(hw);
2096 /* Device Address and read indication */
2097 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2098 if (status != IXGBE_SUCCESS)
2101 status = ixgbe_get_i2c_ack(hw);
2102 if (status != IXGBE_SUCCESS)
2105 status = ixgbe_clock_in_i2c_byte(hw, data);
2106 if (status != IXGBE_SUCCESS)
2109 status = ixgbe_clock_out_i2c_bit(hw, nack);
2110 if (status != IXGBE_SUCCESS)
2115 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2116 return IXGBE_SUCCESS;
2119 ixgbe_i2c_bus_clear(hw);
2121 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2125 if (retry < max_retry)
2126 DEBUGOUT("I2C byte read error - Retrying.\n");
2128 DEBUGOUT("I2C byte read error.\n");
2130 } while (retry < max_retry);
2136 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2137 * @hw: pointer to hardware structure
2138 * @byte_offset: byte offset to read
2141 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2142 * a specified device address.
2144 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2145 u8 dev_addr, u8 *data)
2147 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2152 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2153 * @hw: pointer to hardware structure
2154 * @byte_offset: byte offset to read
2157 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2158 * a specified device address.
2160 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2161 u8 dev_addr, u8 *data)
2163 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2168 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2169 * @hw: pointer to hardware structure
2170 * @byte_offset: byte offset to write
2171 * @data: value to write
2172 * @lock: true if to take and release semaphore
2174 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2175 * a specified device address.
2177 STATIC s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2178 u8 dev_addr, u8 data, bool lock)
2183 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2185 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2187 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2189 return IXGBE_ERR_SWFW_SYNC;
2192 ixgbe_i2c_start(hw);
2194 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2195 if (status != IXGBE_SUCCESS)
2198 status = ixgbe_get_i2c_ack(hw);
2199 if (status != IXGBE_SUCCESS)
2202 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2203 if (status != IXGBE_SUCCESS)
2206 status = ixgbe_get_i2c_ack(hw);
2207 if (status != IXGBE_SUCCESS)
2210 status = ixgbe_clock_out_i2c_byte(hw, data);
2211 if (status != IXGBE_SUCCESS)
2214 status = ixgbe_get_i2c_ack(hw);
2215 if (status != IXGBE_SUCCESS)
2220 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2221 return IXGBE_SUCCESS;
2224 ixgbe_i2c_bus_clear(hw);
2226 if (retry < max_retry)
2227 DEBUGOUT("I2C byte write error - Retrying.\n");
2229 DEBUGOUT("I2C byte write error.\n");
2230 } while (retry < max_retry);
2233 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2239 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2240 * @hw: pointer to hardware structure
2241 * @byte_offset: byte offset to write
2242 * @data: value to write
2244 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2245 * a specified device address.
2247 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2248 u8 dev_addr, u8 data)
2250 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2255 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2256 * @hw: pointer to hardware structure
2257 * @byte_offset: byte offset to write
2258 * @data: value to write
2260 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2261 * a specified device address.
2263 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2264 u8 dev_addr, u8 data)
2266 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2271 * ixgbe_i2c_start - Sets I2C start condition
2272 * @hw: pointer to hardware structure
2274 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2275 * Set bit-bang mode on X550 hardware.
2277 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2279 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2281 DEBUGFUNC("ixgbe_i2c_start");
2283 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2285 /* Start condition must begin with data and clock high */
2286 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2287 ixgbe_raise_i2c_clk(hw, &i2cctl);
2289 /* Setup time for start condition (4.7us) */
2290 usec_delay(IXGBE_I2C_T_SU_STA);
2292 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2294 /* Hold time for start condition (4us) */
2295 usec_delay(IXGBE_I2C_T_HD_STA);
2297 ixgbe_lower_i2c_clk(hw, &i2cctl);
2299 /* Minimum low period of clock is 4.7 us */
2300 usec_delay(IXGBE_I2C_T_LOW);
2305 * ixgbe_i2c_stop - Sets I2C stop condition
2306 * @hw: pointer to hardware structure
2308 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2309 * Disables bit-bang mode and negates data output enable on X550
2312 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2314 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2315 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2316 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2317 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2319 DEBUGFUNC("ixgbe_i2c_stop");
2321 /* Stop condition must begin with data low and clock high */
2322 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2323 ixgbe_raise_i2c_clk(hw, &i2cctl);
2325 /* Setup time for stop condition (4us) */
2326 usec_delay(IXGBE_I2C_T_SU_STO);
2328 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2330 /* bus free time between stop and start (4.7us)*/
2331 usec_delay(IXGBE_I2C_T_BUF);
2333 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2334 i2cctl &= ~bb_en_bit;
2335 i2cctl |= data_oe_bit | clk_oe_bit;
2336 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2337 IXGBE_WRITE_FLUSH(hw);
2342 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2343 * @hw: pointer to hardware structure
2344 * @data: data byte to clock in
2346 * Clocks in one byte data via I2C data/clock
2348 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2353 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2356 for (i = 7; i >= 0; i--) {
2357 ixgbe_clock_in_i2c_bit(hw, &bit);
2361 return IXGBE_SUCCESS;
2365 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2366 * @hw: pointer to hardware structure
2367 * @data: data byte clocked out
2369 * Clocks out one byte data via I2C data/clock
2371 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2373 s32 status = IXGBE_SUCCESS;
2378 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2380 for (i = 7; i >= 0; i--) {
2381 bit = (data >> i) & 0x1;
2382 status = ixgbe_clock_out_i2c_bit(hw, bit);
2384 if (status != IXGBE_SUCCESS)
2388 /* Release SDA line (set high) */
2389 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2390 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2391 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2392 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2393 IXGBE_WRITE_FLUSH(hw);
2399 * ixgbe_get_i2c_ack - Polls for I2C ACK
2400 * @hw: pointer to hardware structure
2402 * Clocks in/out one bit via I2C data/clock
2404 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2406 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2407 s32 status = IXGBE_SUCCESS;
2409 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2413 DEBUGFUNC("ixgbe_get_i2c_ack");
2416 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2417 i2cctl |= data_oe_bit;
2418 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2419 IXGBE_WRITE_FLUSH(hw);
2421 ixgbe_raise_i2c_clk(hw, &i2cctl);
2423 /* Minimum high period of clock is 4us */
2424 usec_delay(IXGBE_I2C_T_HIGH);
2426 /* Poll for ACK. Note that ACK in I2C spec is
2427 * transition from 1 to 0 */
2428 for (i = 0; i < timeout; i++) {
2429 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2430 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2438 DEBUGOUT("I2C ack was not received.\n");
2439 status = IXGBE_ERR_I2C;
2442 ixgbe_lower_i2c_clk(hw, &i2cctl);
2444 /* Minimum low period of clock is 4.7 us */
2445 usec_delay(IXGBE_I2C_T_LOW);
2451 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2452 * @hw: pointer to hardware structure
2453 * @data: read data value
2455 * Clocks in one bit via I2C data/clock
2457 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2459 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2460 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2462 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2465 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2466 i2cctl |= data_oe_bit;
2467 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2468 IXGBE_WRITE_FLUSH(hw);
2470 ixgbe_raise_i2c_clk(hw, &i2cctl);
2472 /* Minimum high period of clock is 4us */
2473 usec_delay(IXGBE_I2C_T_HIGH);
2475 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2476 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2478 ixgbe_lower_i2c_clk(hw, &i2cctl);
2480 /* Minimum low period of clock is 4.7 us */
2481 usec_delay(IXGBE_I2C_T_LOW);
2483 return IXGBE_SUCCESS;
2487 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2488 * @hw: pointer to hardware structure
2489 * @data: data value to write
2491 * Clocks out one bit via I2C data/clock
2493 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2496 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2498 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2500 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2501 if (status == IXGBE_SUCCESS) {
2502 ixgbe_raise_i2c_clk(hw, &i2cctl);
2504 /* Minimum high period of clock is 4us */
2505 usec_delay(IXGBE_I2C_T_HIGH);
2507 ixgbe_lower_i2c_clk(hw, &i2cctl);
2509 /* Minimum low period of clock is 4.7 us.
2510 * This also takes care of the data hold time.
2512 usec_delay(IXGBE_I2C_T_LOW);
2514 status = IXGBE_ERR_I2C;
2515 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2516 "I2C data was not set to %X\n", data);
2523 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2524 * @hw: pointer to hardware structure
2525 * @i2cctl: Current value of I2CCTL register
2527 * Raises the I2C clock line '0'->'1'
2528 * Negates the I2C clock output enable on X550 hardware.
2530 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2532 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2534 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2537 DEBUGFUNC("ixgbe_raise_i2c_clk");
2540 *i2cctl |= clk_oe_bit;
2541 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2544 for (i = 0; i < timeout; i++) {
2545 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2547 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2548 IXGBE_WRITE_FLUSH(hw);
2549 /* SCL rise time (1000ns) */
2550 usec_delay(IXGBE_I2C_T_RISE);
2552 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2553 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2559 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2560 * @hw: pointer to hardware structure
2561 * @i2cctl: Current value of I2CCTL register
2563 * Lowers the I2C clock line '1'->'0'
2564 * Asserts the I2C clock output enable on X550 hardware.
2566 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2568 DEBUGFUNC("ixgbe_lower_i2c_clk");
2570 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2571 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2573 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2574 IXGBE_WRITE_FLUSH(hw);
2576 /* SCL fall time (300ns) */
2577 usec_delay(IXGBE_I2C_T_FALL);
2581 * ixgbe_set_i2c_data - Sets the I2C data bit
2582 * @hw: pointer to hardware structure
2583 * @i2cctl: Current value of I2CCTL register
2584 * @data: I2C data value (0 or 1) to set
2586 * Sets the I2C data bit
2587 * Asserts the I2C data output enable on X550 hardware.
2589 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2591 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2592 s32 status = IXGBE_SUCCESS;
2594 DEBUGFUNC("ixgbe_set_i2c_data");
2597 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2599 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2600 *i2cctl &= ~data_oe_bit;
2602 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2603 IXGBE_WRITE_FLUSH(hw);
2605 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2606 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2608 if (!data) /* Can't verify data in this case */
2609 return IXGBE_SUCCESS;
2611 *i2cctl |= data_oe_bit;
2612 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2613 IXGBE_WRITE_FLUSH(hw);
2616 /* Verify data was set correctly */
2617 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2618 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2619 status = IXGBE_ERR_I2C;
2620 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2621 "Error - I2C data was not set to %X.\n",
2629 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2630 * @hw: pointer to hardware structure
2631 * @i2cctl: Current value of I2CCTL register
2633 * Returns the I2C data bit value
2634 * Negates the I2C data output enable on X550 hardware.
2636 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2638 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2641 DEBUGFUNC("ixgbe_get_i2c_data");
2644 *i2cctl |= data_oe_bit;
2645 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2646 IXGBE_WRITE_FLUSH(hw);
2647 usec_delay(IXGBE_I2C_T_FALL);
2650 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2659 * ixgbe_i2c_bus_clear - Clears the I2C bus
2660 * @hw: pointer to hardware structure
2662 * Clears the I2C bus by sending nine clock pulses.
2663 * Used when data line is stuck low.
2665 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2670 DEBUGFUNC("ixgbe_i2c_bus_clear");
2672 ixgbe_i2c_start(hw);
2673 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2675 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2677 for (i = 0; i < 9; i++) {
2678 ixgbe_raise_i2c_clk(hw, &i2cctl);
2680 /* Min high period of clock is 4us */
2681 usec_delay(IXGBE_I2C_T_HIGH);
2683 ixgbe_lower_i2c_clk(hw, &i2cctl);
2685 /* Min low period of clock is 4.7us*/
2686 usec_delay(IXGBE_I2C_T_LOW);
2689 ixgbe_i2c_start(hw);
2691 /* Put the i2c bus back to default state */
2696 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2697 * @hw: pointer to hardware structure
2699 * Checks if the LASI temp alarm status was triggered due to overtemp
2701 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2703 s32 status = IXGBE_SUCCESS;
2706 DEBUGFUNC("ixgbe_tn_check_overtemp");
2708 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2711 /* Check that the LASI temp alarm status was triggered */
2712 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2713 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2715 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2718 status = IXGBE_ERR_OVERTEMP;
2719 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2725 * ixgbe_set_copper_phy_power - Control power for copper phy
2726 * @hw: pointer to hardware structure
2727 * @on: true for on, false for off
2729 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2734 if (!on && ixgbe_mng_present(hw))
2737 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2738 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2744 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2746 if (ixgbe_check_reset_blocked(hw))
2748 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2751 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2752 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,