drivers/net/ixgbe/base/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_api.h"
  35 #include "ixgbe_common.h"
  36 #include "ixgbe_phy.h"
  37
  38 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
  39 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  40 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  41 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  42 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  43 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  44 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  45 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  46 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  47 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  48 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
  49 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
  50                                           u8 *sff8472_data);
  51
  52 /**
  53  * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
  54  * @hw: pointer to the hardware structure
  55  * @byte: byte to send
  56  *
  57  * Returns an error code on error.
  58  */
  59 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
  60 {
  61         s32 status;
  62
  63         status = ixgbe_clock_out_i2c_byte(hw, byte);
  64         if (status)
  65                 return status;
  66         return ixgbe_get_i2c_ack(hw);
  67 }
  68
  69 /**
  70  * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
  71  * @hw: pointer to the hardware structure
  72  * @byte: pointer to a u8 to receive the byte
  73  *
  74  * Returns an error code on error.
  75  */
  76 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
  77 {
  78         s32 status;
  79
  80         status = ixgbe_clock_in_i2c_byte(hw, byte);
  81         if (status)
  82                 return status;
  83         /* ACK */
  84         return ixgbe_clock_out_i2c_bit(hw, false);
  85 }
  86
  87 /**
  88  * ixgbe_ones_comp_byte_add - Perform one's complement addition
  89  * @add1 - addend 1
  90  * @add2 - addend 2
  91  *
  92  * Returns one's complement 8-bit sum.
  93  */
  94 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
  95 {
  96         u16 sum = add1 + add2;
  97
  98         sum = (sum & 0xFF) + (sum >> 8);
  99         return sum & 0xFF;
 100 }
 101
 102 /**
 103  * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
 104  * @hw: pointer to the hardware structure
 105  * @addr: I2C bus address to read from
 106  * @reg: I2C device register to read from
 107  * @val: pointer to location to receive read value
 108  * @lock: true if to take and release semaphore
 109  *
 110  * Returns an error code on error.
 111  */
 112 STATIC s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
 113                                                u16 reg, u16 *val, bool lock)
 114 {
 115         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 116         int max_retry = 10;
 117         int retry = 0;
 118         u8 csum_byte;
 119         u8 high_bits;
 120         u8 low_bits;
 121         u8 reg_high;
 122         u8 csum;
 123
 124         reg_high = ((reg >> 7) & 0xFE) | 1;     /* Indicate read combined */
 125         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 126         csum = ~csum;
 127         do {
 128                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 129                         return IXGBE_ERR_SWFW_SYNC;
 130                 ixgbe_i2c_start(hw);
 131                 /* Device Address and write indication */
 132                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 133                         goto fail;
 134                 /* Write bits 14:8 */
 135                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 136                         goto fail;
 137                 /* Write bits 7:0 */
 138                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 139                         goto fail;
 140                 /* Write csum */
 141                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 142                         goto fail;
 143                 /* Re-start condition */
 144                 ixgbe_i2c_start(hw);
 145                 /* Device Address and read indication */
 146                 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
 147                         goto fail;
 148                 /* Get upper bits */
 149                 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
 150                         goto fail;
 151                 /* Get low bits */
 152                 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
 153                         goto fail;
 154                 /* Get csum */
 155                 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
 156                         goto fail;
 157                 /* NACK */
 158                 if (ixgbe_clock_out_i2c_bit(hw, false))
 159                         goto fail;
 160                 ixgbe_i2c_stop(hw);
 161                 if (lock)
 162                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 163                 *val = (high_bits << 8) | low_bits;
 164                 return 0;
 165
 166 fail:
 167                 ixgbe_i2c_bus_clear(hw);
 168                 if (lock)
 169                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 170                 retry++;
 171                 if (retry < max_retry)
 172                         DEBUGOUT("I2C byte read combined error - Retrying.\n");
 173                 else
 174                         DEBUGOUT("I2C byte read combined error.\n");
 175         } while (retry < max_retry);
 176
 177         return IXGBE_ERR_I2C;
 178 }
 179
 180 /**
 181  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 182  * @hw: pointer to the hardware structure
 183  * @addr: I2C bus address to read from
 184  * @reg: I2C device register to read from
 185  * @val: pointer to location to receive read value
 186  *
 187  * Returns an error code on error.
 188  **/
 189 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 190                                            u16 reg, u16 *val)
 191 {
 192         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 193 }
 194
 195 /**
 196  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 197  * @hw: pointer to the hardware structure
 198  * @addr: I2C bus address to read from
 199  * @reg: I2C device register to read from
 200  * @val: pointer to location to receive read value
 201  *
 202  * Returns an error code on error.
 203  **/
 204 STATIC s32
 205 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 206                                          u16 reg, u16 *val)
 207 {
 208         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 209 }
 210
 211 /**
 212  * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
 213  * @hw: pointer to the hardware structure
 214  * @addr: I2C bus address to write to
 215  * @reg: I2C device register to write to
 216  * @val: value to write
 217  * @lock: true if to take and release semaphore
 218  *
 219  * Returns an error code on error.
 220  */
 221 STATIC s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
 222                                                 u16 reg, u16 val, bool lock)
 223 {
 224         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 225         int max_retry = 1;
 226         int retry = 0;
 227         u8 reg_high;
 228         u8 csum;
 229
 230         reg_high = (reg >> 7) & 0xFE;   /* Indicate write combined */
 231         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 232         csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
 233         csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
 234         csum = ~csum;
 235         do {
 236                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 237                         return IXGBE_ERR_SWFW_SYNC;
 238                 ixgbe_i2c_start(hw);
 239                 /* Device Address and write indication */
 240                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 241                         goto fail;
 242                 /* Write bits 14:8 */
 243                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 244                         goto fail;
 245                 /* Write bits 7:0 */
 246                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 247                         goto fail;
 248                 /* Write data 15:8 */
 249                 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
 250                         goto fail;
 251                 /* Write data 7:0 */
 252                 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
 253                         goto fail;
 254                 /* Write csum */
 255                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 256                         goto fail;
 257                 ixgbe_i2c_stop(hw);
 258                 if (lock)
 259                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 260                 return 0;
 261
 262 fail:
 263                 ixgbe_i2c_bus_clear(hw);
 264                 if (lock)
 265                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 266                 retry++;
 267                 if (retry < max_retry)
 268                         DEBUGOUT("I2C byte write combined error - Retrying.\n");
 269                 else
 270                         DEBUGOUT("I2C byte write combined error.\n");
 271         } while (retry < max_retry);
 272
 273         return IXGBE_ERR_I2C;
 274 }
 275
 276 /**
 277  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 278  * @hw: pointer to the hardware structure
 279  * @addr: I2C bus address to write to
 280  * @reg: I2C device register to write to
 281  * @val: value to write
 282  *
 283  * Returns an error code on error.
 284  **/
 285 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 286                                             u8 addr, u16 reg, u16 val)
 287 {
 288         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 289 }
 290
 291 /**
 292  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 293  * @hw: pointer to the hardware structure
 294  * @addr: I2C bus address to write to
 295  * @reg: I2C device register to write to
 296  * @val: value to write
 297  *
 298  * Returns an error code on error.
 299  **/
 300 STATIC s32
 301 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 302                                           u8 addr, u16 reg, u16 val)
 303 {
 304         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 305 }
 306
 307 /**
 308  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
 309  *  @hw: pointer to the hardware structure
 310  *
 311  *  Initialize the function pointers.
 312  **/
 313 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
 314 {
 315         struct ixgbe_phy_info *phy = &hw->phy;
 316
 317         DEBUGFUNC("ixgbe_init_phy_ops_generic");
 318
 319         /* PHY */
 320         phy->ops.identify = ixgbe_identify_phy_generic;
 321         phy->ops.reset = ixgbe_reset_phy_generic;
 322         phy->ops.read_reg = ixgbe_read_phy_reg_generic;
 323         phy->ops.write_reg = ixgbe_write_phy_reg_generic;
 324         phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
 325         phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
 326         phy->ops.setup_link = ixgbe_setup_phy_link_generic;
 327         phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
 328         phy->ops.check_link = NULL;
 329         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
 330         phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
 331         phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
 332         phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
 333         phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
 334         phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
 335         phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
 336         phy->ops.identify_sfp = ixgbe_identify_module_generic;
 337         phy->sfp_type = ixgbe_sfp_type_unknown;
 338         phy->ops.read_i2c_combined = ixgbe_read_i2c_combined_generic;
 339         phy->ops.write_i2c_combined = ixgbe_write_i2c_combined_generic;
 340         phy->ops.read_i2c_combined_unlocked =
 341                                 ixgbe_read_i2c_combined_generic_unlocked;
 342         phy->ops.write_i2c_combined_unlocked =
 343                                 ixgbe_write_i2c_combined_generic_unlocked;
 344         phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
 345         phy->ops.write_i2c_byte_unlocked =
 346                                 ixgbe_write_i2c_byte_generic_unlocked;
 347         phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
 348         return IXGBE_SUCCESS;
 349 }
 350
 351 /**
 352  *  ixgbe_identify_phy_generic - Get physical layer module
 353  *  @hw: pointer to hardware structure
 354  *
 355  *  Determines the physical layer module found on the current adapter.
 356  **/
 357 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
 358 {
 359         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 360         u32 phy_addr;
 361         u16 ext_ability = 0;
 362
 363         DEBUGFUNC("ixgbe_identify_phy_generic");
 364
 365         if (!hw->phy.phy_semaphore_mask) {
 366                 if (hw->bus.lan_id)
 367                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 368                 else
 369                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 370         }
 371
 372         if (hw->phy.type == ixgbe_phy_unknown) {
 373                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
 374                         if (ixgbe_validate_phy_addr(hw, phy_addr)) {
 375                                 hw->phy.addr = phy_addr;
 376                                 ixgbe_get_phy_id(hw);
 377                                 hw->phy.type =
 378                                         ixgbe_get_phy_type_from_id(hw->phy.id);
 379
 380                                 if (hw->phy.type == ixgbe_phy_unknown) {
 381                                         hw->phy.ops.read_reg(hw,
 382                                                   IXGBE_MDIO_PHY_EXT_ABILITY,
 383                                                   IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 384                                                   &ext_ability);
 385                                         if (ext_ability &
 386                                             (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 387                                              IXGBE_MDIO_PHY_1000BASET_ABILITY))
 388                                                 hw->phy.type =
 389                                                          ixgbe_phy_cu_unknown;
 390                                         else
 391                                                 hw->phy.type =
 392                                                          ixgbe_phy_generic;
 393                                 }
 394
 395                                 status = IXGBE_SUCCESS;
 396                                 break;
 397                         }
 398                 }
 399
 400                 /* Certain media types do not have a phy so an address will not
 401                  * be found and the code will take this path.  Caller has to
 402                  * decide if it is an error or not.
 403                  */
 404                 if (status != IXGBE_SUCCESS) {
 405                         hw->phy.addr = 0;
 406                 }
 407         } else {
 408                 status = IXGBE_SUCCESS;
 409         }
 410
 411         return status;
 412 }
 413
 414 /**
 415  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 416  * @hw: pointer to the hardware structure
 417  *
 418  * This function checks the MMNGC.MNG_VETO bit to see if there are
 419  * any constraints on link from manageability.  For MAC's that don't
 420  * have this bit just return faluse since the link can not be blocked
 421  * via this method.
 422  **/
 423 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 424 {
 425         u32 mmngc;
 426
 427         DEBUGFUNC("ixgbe_check_reset_blocked");
 428
 429         /* If we don't have this bit, it can't be blocking */
 430         if (hw->mac.type == ixgbe_mac_82598EB)
 431                 return false;
 432
 433         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 434         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 435                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
 436                               "MNG_VETO bit detected.\n");
 437                 return true;
 438         }
 439
 440         return false;
 441 }
 442
 443 /**
 444  *  ixgbe_validate_phy_addr - Determines phy address is valid
 445  *  @hw: pointer to hardware structure
 446  *
 447  **/
 448 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 449 {
 450         u16 phy_id = 0;
 451         bool valid = false;
 452
 453         DEBUGFUNC("ixgbe_validate_phy_addr");
 454
 455         hw->phy.addr = phy_addr;
 456         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 457                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 458
 459         if (phy_id != 0xFFFF && phy_id != 0x0)
 460                 valid = true;
 461
 462         return valid;
 463 }
 464
 465 /**
 466  *  ixgbe_get_phy_id - Get the phy type
 467  *  @hw: pointer to hardware structure
 468  *
 469  **/
 470 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 471 {
 472         u32 status;
 473         u16 phy_id_high = 0;
 474         u16 phy_id_low = 0;
 475
 476         DEBUGFUNC("ixgbe_get_phy_id");
 477
 478         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 479                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 480                                       &phy_id_high);
 481
 482         if (status == IXGBE_SUCCESS) {
 483                 hw->phy.id = (u32)(phy_id_high << 16);
 484                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 485                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 486                                               &phy_id_low);
 487                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 488                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 489         }
 490         return status;
 491 }
 492
 493 /**
 494  *  ixgbe_get_phy_type_from_id - Get the phy type
 495  *  @hw: pointer to hardware structure
 496  *
 497  **/
 498 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 499 {
 500         enum ixgbe_phy_type phy_type;
 501
 502         DEBUGFUNC("ixgbe_get_phy_type_from_id");
 503
 504         switch (phy_id) {
 505         case TN1010_PHY_ID:
 506                 phy_type = ixgbe_phy_tn;
 507                 break;
 508         case X550_PHY_ID:
 509         case X540_PHY_ID:
 510                 phy_type = ixgbe_phy_aq;
 511                 break;
 512         case QT2022_PHY_ID:
 513                 phy_type = ixgbe_phy_qt;
 514                 break;
 515         case ATH_PHY_ID:
 516                 phy_type = ixgbe_phy_nl;
 517                 break;
 518         case X557_PHY_ID:
 519                 phy_type = ixgbe_phy_x550em_ext_t;
 520                 break;
 521         default:
 522                 phy_type = ixgbe_phy_unknown;
 523                 break;
 524         }
 525
 526         DEBUGOUT1("phy type found is %d\n", phy_type);
 527         return phy_type;
 528 }
 529
 530 /**
 531  *  ixgbe_reset_phy_generic - Performs a PHY reset
 532  *  @hw: pointer to hardware structure
 533  **/
 534 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 535 {
 536         u32 i;
 537         u16 ctrl = 0;
 538         s32 status = IXGBE_SUCCESS;
 539
 540         DEBUGFUNC("ixgbe_reset_phy_generic");
 541
 542         if (hw->phy.type == ixgbe_phy_unknown)
 543                 status = ixgbe_identify_phy_generic(hw);
 544
 545         if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 546                 goto out;
 547
 548         /* Don't reset PHY if it's shut down due to overtemp. */
 549         if (!hw->phy.reset_if_overtemp &&
 550             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 551                 goto out;
 552
 553         /* Blocked by MNG FW so bail */
 554         if (ixgbe_check_reset_blocked(hw))
 555                 goto out;
 556
 557         /*
 558          * Perform soft PHY reset to the PHY_XS.
 559          * This will cause a soft reset to the PHY
 560          */
 561         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 562                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 563                               IXGBE_MDIO_PHY_XS_RESET);
 564
 565         /*
 566          * Poll for reset bit to self-clear indicating reset is complete.
 567          * Some PHYs could take up to 3 seconds to complete and need about
 568          * 1.7 usec delay after the reset is complete.
 569          */
 570         for (i = 0; i < 30; i++) {
 571                 msec_delay(100);
 572                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 573                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
 574                 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 575                         usec_delay(2);
 576                         break;
 577                 }
 578         }
 579
 580         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 581                 status = IXGBE_ERR_RESET_FAILED;
 582                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 583                              "PHY reset polling failed to complete.\n");
 584         }
 585
 586 out:
 587         return status;
 588 }
 589
 590 /**
 591  *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 592  *  the SWFW lock
 593  *  @hw: pointer to hardware structure
 594  *  @reg_addr: 32 bit address of PHY register to read
 595  *  @phy_data: Pointer to read data from PHY register
 596  **/
 597 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 598                        u16 *phy_data)
 599 {
 600         u32 i, data, command;
 601
 602         /* Setup and write the address cycle command */
 603         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 604                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 605                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 606                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 607
 608         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 609
 610         /*
 611          * Check every 10 usec to see if the address cycle completed.
 612          * The MDI Command bit will clear when the operation is
 613          * complete
 614          */
 615         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 616                 usec_delay(10);
 617
 618                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 619                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 620                                 break;
 621         }
 622
 623
 624         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 625                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
 626                 return IXGBE_ERR_PHY;
 627         }
 628
 629         /*
 630          * Address cycle complete, setup and write the read
 631          * command
 632          */
 633         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 634                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 635                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 636                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 637
 638         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 639
 640         /*
 641          * Check every 10 usec to see if the address cycle
 642          * completed. The MDI Command bit will clear when the
 643          * operation is complete
 644          */
 645         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 646                 usec_delay(10);
 647
 648                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 649                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 650                         break;
 651         }
 652
 653         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 654                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
 655                 return IXGBE_ERR_PHY;
 656         }
 657
 658         /*
 659          * Read operation is complete.  Get the data
 660          * from MSRWD
 661          */
 662         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 663         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 664         *phy_data = (u16)(data);
 665
 666         return IXGBE_SUCCESS;
 667 }
 668
 669 /**
 670  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 671  *  using the SWFW lock - this function is needed in most cases
 672  *  @hw: pointer to hardware structure
 673  *  @reg_addr: 32 bit address of PHY register to read
 674  *  @phy_data: Pointer to read data from PHY register
 675  **/
 676 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 677                                u32 device_type, u16 *phy_data)
 678 {
 679         s32 status;
 680         u32 gssr = hw->phy.phy_semaphore_mask;
 681
 682         DEBUGFUNC("ixgbe_read_phy_reg_generic");
 683
 684         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 685                 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
 686                                                 phy_data);
 687                 hw->mac.ops.release_swfw_sync(hw, gssr);
 688         } else {
 689                 status = IXGBE_ERR_SWFW_SYNC;
 690         }
 691
 692         return status;
 693 }
 694
 695 /**
 696  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 697  *  without SWFW lock
 698  *  @hw: pointer to hardware structure
 699  *  @reg_addr: 32 bit PHY register to write
 700  *  @device_type: 5 bit device type
 701  *  @phy_data: Data to write to the PHY register
 702  **/
 703 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 704                                 u32 device_type, u16 phy_data)
 705 {
 706         u32 i, command;
 707
 708         /* Put the data in the MDI single read and write data register*/
 709         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 710
 711         /* Setup and write the address cycle command */
 712         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 713                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 714                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 715                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 716
 717         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 718
 719         /*
 720          * Check every 10 usec to see if the address cycle completed.
 721          * The MDI Command bit will clear when the operation is
 722          * complete
 723          */
 724         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 725                 usec_delay(10);
 726
 727                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 728                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 729                         break;
 730         }
 731
 732         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 733                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
 734                 return IXGBE_ERR_PHY;
 735         }
 736
 737         /*
 738          * Address cycle complete, setup and write the write
 739          * command
 740          */
 741         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 742                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 743                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 744                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 745
 746         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 747
 748         /*
 749          * Check every 10 usec to see if the address cycle
 750          * completed. The MDI Command bit will clear when the
 751          * operation is complete
 752          */
 753         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 754                 usec_delay(10);
 755
 756                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 757                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 758                         break;
 759         }
 760
 761         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 762                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
 763                 return IXGBE_ERR_PHY;
 764         }
 765
 766         return IXGBE_SUCCESS;
 767 }
 768
 769 /**
 770  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 771  *  using SWFW lock- this function is needed in most cases
 772  *  @hw: pointer to hardware structure
 773  *  @reg_addr: 32 bit PHY register to write
 774  *  @device_type: 5 bit device type
 775  *  @phy_data: Data to write to the PHY register
 776  **/
 777 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 778                                 u32 device_type, u16 phy_data)
 779 {
 780         s32 status;
 781         u32 gssr = hw->phy.phy_semaphore_mask;
 782
 783         DEBUGFUNC("ixgbe_write_phy_reg_generic");
 784
 785         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 786                 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
 787                                                  phy_data);
 788                 hw->mac.ops.release_swfw_sync(hw, gssr);
 789         } else {
 790                 status = IXGBE_ERR_SWFW_SYNC;
 791         }
 792
 793         return status;
 794 }
 795
 796 /**
 797  *  ixgbe_setup_phy_link_generic - Set and restart auto-neg
 798  *  @hw: pointer to hardware structure
 799  *
 800  *  Restart auto-negotiation and PHY and waits for completion.
 801  **/
 802 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 803 {
 804         s32 status = IXGBE_SUCCESS;
 805         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 806         bool autoneg = false;
 807         ixgbe_link_speed speed;
 808
 809         DEBUGFUNC("ixgbe_setup_phy_link_generic");
 810
 811         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 812
 813         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 814                 /* Set or unset auto-negotiation 10G advertisement */
 815                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 816                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 817                                      &autoneg_reg);
 818
 819                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 820                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 821                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 822
 823                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 824                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 825                                       autoneg_reg);
 826         }
 827
 828         if (hw->mac.type == ixgbe_mac_X550) {
 829                 if (speed & IXGBE_LINK_SPEED_5GB_FULL) {
 830                         /* Set or unset auto-negotiation 1G advertisement */
 831                         hw->phy.ops.read_reg(hw,
 832                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 833                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 834                                 &autoneg_reg);
 835
 836                         autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
 837                         if (hw->phy.autoneg_advertised &
 838                              IXGBE_LINK_SPEED_5GB_FULL)
 839                                 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
 840
 841                         hw->phy.ops.write_reg(hw,
 842                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 843                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 844                                 autoneg_reg);
 845                 }
 846
 847                 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) {
 848                         /* Set or unset auto-negotiation 1G advertisement */
 849                         hw->phy.ops.read_reg(hw,
 850                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 851                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 852                                 &autoneg_reg);
 853
 854                         autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
 855                         if (hw->phy.autoneg_advertised &
 856                             IXGBE_LINK_SPEED_2_5GB_FULL)
 857                                 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
 858
 859                         hw->phy.ops.write_reg(hw,
 860                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 861                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 862                                 autoneg_reg);
 863                 }
 864         }
 865
 866         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 867                 /* Set or unset auto-negotiation 1G advertisement */
 868                 hw->phy.ops.read_reg(hw,
 869                                      IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 870                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 871                                      &autoneg_reg);
 872
 873                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 874                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 875                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 876
 877                 hw->phy.ops.write_reg(hw,
 878                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 879                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 880                                       autoneg_reg);
 881         }
 882
 883         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 884                 /* Set or unset auto-negotiation 100M advertisement */
 885                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 886                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 887                                      &autoneg_reg);
 888
 889                 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 890                                  IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 891                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 892                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 893
 894                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 895                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 896                                       autoneg_reg);
 897         }
 898
 899         /* Blocked by MNG FW so don't reset PHY */
 900         if (ixgbe_check_reset_blocked(hw))
 901                 return status;
 902
 903         /* Restart PHY auto-negotiation. */
 904         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 905                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 906
 907         autoneg_reg |= IXGBE_MII_RESTART;
 908
 909         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 910                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 911
 912         return status;
 913 }
 914
 915 /**
 916  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 917  *  @hw: pointer to hardware structure
 918  *  @speed: new link speed
 919  **/
 920 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 921                                        ixgbe_link_speed speed,
 922                                        bool autoneg_wait_to_complete)
 923 {
 924         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
 925
 926         DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
 927
 928         /*
 929          * Clear autoneg_advertised and set new values based on input link
 930          * speed.
 931          */
 932         hw->phy.autoneg_advertised = 0;
 933
 934         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 935                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 936
 937         if (speed & IXGBE_LINK_SPEED_5GB_FULL)
 938                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
 939
 940         if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
 941                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
 942
 943         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 944                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 945
 946         if (speed & IXGBE_LINK_SPEED_100_FULL)
 947                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 948
 949         /* Setup link based on the new speed settings */
 950         hw->phy.ops.setup_link(hw);
 951
 952         return IXGBE_SUCCESS;
 953 }
 954
 955 /**
 956  *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 957  *  @hw: pointer to hardware structure
 958  *  @speed: pointer to link speed
 959  *  @autoneg: boolean auto-negotiation value
 960  *
 961  *  Determines the supported link capabilities by reading the PHY auto
 962  *  negotiation register.
 963  **/
 964 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 965                                                ixgbe_link_speed *speed,
 966                                                bool *autoneg)
 967 {
 968         s32 status;
 969         u16 speed_ability;
 970
 971         DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
 972
 973         *speed = 0;
 974         *autoneg = true;
 975
 976         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 977                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 978                                       &speed_ability);
 979
 980         if (status == IXGBE_SUCCESS) {
 981                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 982                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 983                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 984                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 985                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 986                         *speed |= IXGBE_LINK_SPEED_100_FULL;
 987         }
 988
 989         /* Internal PHY does not support 100 Mbps */
 990         if (hw->mac.type == ixgbe_mac_X550EM_x)
 991                 *speed &= ~IXGBE_LINK_SPEED_100_FULL;
 992
 993         if (hw->mac.type == ixgbe_mac_X550) {
 994                 *speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
 995                 *speed |= IXGBE_LINK_SPEED_5GB_FULL;
 996         }
 997
 998         return status;
 999 }
1000
1001 /**
1002  *  ixgbe_check_phy_link_tnx - Determine link and speed status
1003  *  @hw: pointer to hardware structure
1004  *
1005  *  Reads the VS1 register to determine if link is up and the current speed for
1006  *  the PHY.
1007  **/
1008 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1009                              bool *link_up)
1010 {
1011         s32 status = IXGBE_SUCCESS;
1012         u32 time_out;
1013         u32 max_time_out = 10;
1014         u16 phy_link = 0;
1015         u16 phy_speed = 0;
1016         u16 phy_data = 0;
1017
1018         DEBUGFUNC("ixgbe_check_phy_link_tnx");
1019
1020         /* Initialize speed and link to default case */
1021         *link_up = false;
1022         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1023
1024         /*
1025          * Check current speed and link status of the PHY register.
1026          * This is a vendor specific register and may have to
1027          * be changed for other copper PHYs.
1028          */
1029         for (time_out = 0; time_out < max_time_out; time_out++) {
1030                 usec_delay(10);
1031                 status = hw->phy.ops.read_reg(hw,
1032                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1033                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1034                                         &phy_data);
1035                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1036                 phy_speed = phy_data &
1037                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1038                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1039                         *link_up = true;
1040                         if (phy_speed ==
1041                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1042                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1043                         break;
1044                 }
1045         }
1046
1047         return status;
1048 }
1049
1050 /**
1051  *      ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1052  *      @hw: pointer to hardware structure
1053  *
1054  *      Restart auto-negotiation and PHY and waits for completion.
1055  **/
1056 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1057 {
1058         s32 status = IXGBE_SUCCESS;
1059         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1060         bool autoneg = false;
1061         ixgbe_link_speed speed;
1062
1063         DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1064
1065         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1066
1067         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1068                 /* Set or unset auto-negotiation 10G advertisement */
1069                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1070                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1071                                      &autoneg_reg);
1072
1073                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1074                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1075                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1076
1077                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1078                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1079                                       autoneg_reg);
1080         }
1081
1082         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1083                 /* Set or unset auto-negotiation 1G advertisement */
1084                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1085                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1086                                      &autoneg_reg);
1087
1088                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1089                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1090                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1091
1092                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1093                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1094                                       autoneg_reg);
1095         }
1096
1097         if (speed & IXGBE_LINK_SPEED_100_FULL) {
1098                 /* Set or unset auto-negotiation 100M advertisement */
1099                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1100                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1101                                      &autoneg_reg);
1102
1103                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1104                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1105                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1106
1107                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1108                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1109                                       autoneg_reg);
1110         }
1111
1112         /* Blocked by MNG FW so don't reset PHY */
1113         if (ixgbe_check_reset_blocked(hw))
1114                 return status;
1115
1116         /* Restart PHY auto-negotiation. */
1117         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1118                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1119
1120         autoneg_reg |= IXGBE_MII_RESTART;
1121
1122         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1123                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1124
1125         return status;
1126 }
1127
1128 /**
1129  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1130  *  @hw: pointer to hardware structure
1131  *  @firmware_version: pointer to the PHY Firmware Version
1132  **/
1133 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1134                                        u16 *firmware_version)
1135 {
1136         s32 status;
1137
1138         DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1139
1140         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1141                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1142                                       firmware_version);
1143
1144         return status;
1145 }
1146
1147 /**
1148  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1149  *  @hw: pointer to hardware structure
1150  *  @firmware_version: pointer to the PHY Firmware Version
1151  **/
1152 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1153                                            u16 *firmware_version)
1154 {
1155         s32 status;
1156
1157         DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1158
1159         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1160                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1161                                       firmware_version);
1162
1163         return status;
1164 }
1165
1166 /**
1167  *  ixgbe_reset_phy_nl - Performs a PHY reset
1168  *  @hw: pointer to hardware structure
1169  **/
1170 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1171 {
1172         u16 phy_offset, control, eword, edata, block_crc;
1173         bool end_data = false;
1174         u16 list_offset, data_offset;
1175         u16 phy_data = 0;
1176         s32 ret_val = IXGBE_SUCCESS;
1177         u32 i;
1178
1179         DEBUGFUNC("ixgbe_reset_phy_nl");
1180
1181         /* Blocked by MNG FW so bail */
1182         if (ixgbe_check_reset_blocked(hw))
1183                 goto out;
1184
1185         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1186                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1187
1188         /* reset the PHY and poll for completion */
1189         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1190                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
1191                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1192
1193         for (i = 0; i < 100; i++) {
1194                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1195                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1196                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1197                         break;
1198                 msec_delay(10);
1199         }
1200
1201         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1202                 DEBUGOUT("PHY reset did not complete.\n");
1203                 ret_val = IXGBE_ERR_PHY;
1204                 goto out;
1205         }
1206
1207         /* Get init offsets */
1208         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1209                                                       &data_offset);
1210         if (ret_val != IXGBE_SUCCESS)
1211                 goto out;
1212
1213         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1214         data_offset++;
1215         while (!end_data) {
1216                 /*
1217                  * Read control word from PHY init contents offset
1218                  */
1219                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1220                 if (ret_val)
1221                         goto err_eeprom;
1222                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1223                            IXGBE_CONTROL_SHIFT_NL;
1224                 edata = eword & IXGBE_DATA_MASK_NL;
1225                 switch (control) {
1226                 case IXGBE_DELAY_NL:
1227                         data_offset++;
1228                         DEBUGOUT1("DELAY: %d MS\n", edata);
1229                         msec_delay(edata);
1230                         break;
1231                 case IXGBE_DATA_NL:
1232                         DEBUGOUT("DATA:\n");
1233                         data_offset++;
1234                         ret_val = hw->eeprom.ops.read(hw, data_offset,
1235                                                       &phy_offset);
1236                         if (ret_val)
1237                                 goto err_eeprom;
1238                         data_offset++;
1239                         for (i = 0; i < edata; i++) {
1240                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
1241                                                               &eword);
1242                                 if (ret_val)
1243                                         goto err_eeprom;
1244                                 hw->phy.ops.write_reg(hw, phy_offset,
1245                                                       IXGBE_TWINAX_DEV, eword);
1246                                 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1247                                           phy_offset);
1248                                 data_offset++;
1249                                 phy_offset++;
1250                         }
1251                         break;
1252                 case IXGBE_CONTROL_NL:
1253                         data_offset++;
1254                         DEBUGOUT("CONTROL:\n");
1255                         if (edata == IXGBE_CONTROL_EOL_NL) {
1256                                 DEBUGOUT("EOL\n");
1257                                 end_data = true;
1258                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
1259                                 DEBUGOUT("SOL\n");
1260                         } else {
1261                                 DEBUGOUT("Bad control value\n");
1262                                 ret_val = IXGBE_ERR_PHY;
1263                                 goto out;
1264                         }
1265                         break;
1266                 default:
1267                         DEBUGOUT("Bad control type\n");
1268                         ret_val = IXGBE_ERR_PHY;
1269                         goto out;
1270                 }
1271         }
1272
1273 out:
1274         return ret_val;
1275
1276 err_eeprom:
1277         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1278                       "eeprom read at offset %d failed", data_offset);
1279         return IXGBE_ERR_PHY;
1280 }
1281
1282 /**
1283  *  ixgbe_identify_module_generic - Identifies module type
1284  *  @hw: pointer to hardware structure
1285  *
1286  *  Determines HW type and calls appropriate function.
1287  **/
1288 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1289 {
1290         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1291
1292         DEBUGFUNC("ixgbe_identify_module_generic");
1293
1294         switch (hw->mac.ops.get_media_type(hw)) {
1295         case ixgbe_media_type_fiber:
1296                 status = ixgbe_identify_sfp_module_generic(hw);
1297                 break;
1298
1299         case ixgbe_media_type_fiber_qsfp:
1300                 status = ixgbe_identify_qsfp_module_generic(hw);
1301                 break;
1302
1303         default:
1304                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1305                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1306                 break;
1307         }
1308
1309         return status;
1310 }
1311
1312 /**
1313  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
1314  *  @hw: pointer to hardware structure
1315  *
1316  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1317  **/
1318 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1319 {
1320         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1321         u32 vendor_oui = 0;
1322         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1323         u8 identifier = 0;
1324         u8 comp_codes_1g = 0;
1325         u8 comp_codes_10g = 0;
1326         u8 oui_bytes[3] = {0, 0, 0};
1327         u8 cable_tech = 0;
1328         u8 cable_spec = 0;
1329         u16 enforce_sfp = 0;
1330
1331         DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1332
1333         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1334                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1335                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1336                 goto out;
1337         }
1338
1339         /* LAN ID is needed for I2C access */
1340         hw->mac.ops.set_lan_id(hw);
1341
1342         status = hw->phy.ops.read_i2c_eeprom(hw,
1343                                              IXGBE_SFF_IDENTIFIER,
1344                                              &identifier);
1345
1346         if (status != IXGBE_SUCCESS)
1347                 goto err_read_i2c_eeprom;
1348
1349         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1350                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1351                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1352         } else {
1353                 status = hw->phy.ops.read_i2c_eeprom(hw,
1354                                                      IXGBE_SFF_1GBE_COMP_CODES,
1355                                                      &comp_codes_1g);
1356
1357                 if (status != IXGBE_SUCCESS)
1358                         goto err_read_i2c_eeprom;
1359
1360                 status = hw->phy.ops.read_i2c_eeprom(hw,
1361                                                      IXGBE_SFF_10GBE_COMP_CODES,
1362                                                      &comp_codes_10g);
1363
1364                 if (status != IXGBE_SUCCESS)
1365                         goto err_read_i2c_eeprom;
1366                 status = hw->phy.ops.read_i2c_eeprom(hw,
1367                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
1368                                                      &cable_tech);
1369
1370                 if (status != IXGBE_SUCCESS)
1371                         goto err_read_i2c_eeprom;
1372
1373                  /* ID Module
1374                   * =========
1375                   * 0   SFP_DA_CU
1376                   * 1   SFP_SR
1377                   * 2   SFP_LR
1378                   * 3   SFP_DA_CORE0 - 82599-specific
1379                   * 4   SFP_DA_CORE1 - 82599-specific
1380                   * 5   SFP_SR/LR_CORE0 - 82599-specific
1381                   * 6   SFP_SR/LR_CORE1 - 82599-specific
1382                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1383                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1384                   * 9   SFP_1g_cu_CORE0 - 82599-specific
1385                   * 10  SFP_1g_cu_CORE1 - 82599-specific
1386                   * 11  SFP_1g_sx_CORE0 - 82599-specific
1387                   * 12  SFP_1g_sx_CORE1 - 82599-specific
1388                   */
1389                 if (hw->mac.type == ixgbe_mac_82598EB) {
1390                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1391                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1392                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1393                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1394                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1395                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1396                         else
1397                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1398                 } else {
1399                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1400                                 if (hw->bus.lan_id == 0)
1401                                         hw->phy.sfp_type =
1402                                                      ixgbe_sfp_type_da_cu_core0;
1403                                 else
1404                                         hw->phy.sfp_type =
1405                                                      ixgbe_sfp_type_da_cu_core1;
1406                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1407                                 hw->phy.ops.read_i2c_eeprom(
1408                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1409                                                 &cable_spec);
1410                                 if (cable_spec &
1411                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1412                                         if (hw->bus.lan_id == 0)
1413                                                 hw->phy.sfp_type =
1414                                                 ixgbe_sfp_type_da_act_lmt_core0;
1415                                         else
1416                                                 hw->phy.sfp_type =
1417                                                 ixgbe_sfp_type_da_act_lmt_core1;
1418                                 } else {
1419                                         hw->phy.sfp_type =
1420                                                         ixgbe_sfp_type_unknown;
1421                                 }
1422                         } else if (comp_codes_10g &
1423                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1424                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1425                                 if (hw->bus.lan_id == 0)
1426                                         hw->phy.sfp_type =
1427                                                       ixgbe_sfp_type_srlr_core0;
1428                                 else
1429                                         hw->phy.sfp_type =
1430                                                       ixgbe_sfp_type_srlr_core1;
1431                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1432                                 if (hw->bus.lan_id == 0)
1433                                         hw->phy.sfp_type =
1434                                                 ixgbe_sfp_type_1g_cu_core0;
1435                                 else
1436                                         hw->phy.sfp_type =
1437                                                 ixgbe_sfp_type_1g_cu_core1;
1438                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1439                                 if (hw->bus.lan_id == 0)
1440                                         hw->phy.sfp_type =
1441                                                 ixgbe_sfp_type_1g_sx_core0;
1442                                 else
1443                                         hw->phy.sfp_type =
1444                                                 ixgbe_sfp_type_1g_sx_core1;
1445                         } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1446                                 if (hw->bus.lan_id == 0)
1447                                         hw->phy.sfp_type =
1448                                                 ixgbe_sfp_type_1g_lx_core0;
1449                                 else
1450                                         hw->phy.sfp_type =
1451                                                 ixgbe_sfp_type_1g_lx_core1;
1452                         } else {
1453                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1454                         }
1455                 }
1456
1457                 if (hw->phy.sfp_type != stored_sfp_type)
1458                         hw->phy.sfp_setup_needed = true;
1459
1460                 /* Determine if the SFP+ PHY is dual speed or not. */
1461                 hw->phy.multispeed_fiber = false;
1462                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1463                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1464                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1465                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1466                         hw->phy.multispeed_fiber = true;
1467
1468                 /* Determine PHY vendor */
1469                 if (hw->phy.type != ixgbe_phy_nl) {
1470                         hw->phy.id = identifier;
1471                         status = hw->phy.ops.read_i2c_eeprom(hw,
1472                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1473                                                     &oui_bytes[0]);
1474
1475                         if (status != IXGBE_SUCCESS)
1476                                 goto err_read_i2c_eeprom;
1477
1478                         status = hw->phy.ops.read_i2c_eeprom(hw,
1479                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1480                                                     &oui_bytes[1]);
1481
1482                         if (status != IXGBE_SUCCESS)
1483                                 goto err_read_i2c_eeprom;
1484
1485                         status = hw->phy.ops.read_i2c_eeprom(hw,
1486                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1487                                                     &oui_bytes[2]);
1488
1489                         if (status != IXGBE_SUCCESS)
1490                                 goto err_read_i2c_eeprom;
1491
1492                         vendor_oui =
1493                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1494                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1495                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1496
1497                         switch (vendor_oui) {
1498                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1499                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1500                                         hw->phy.type =
1501                                                     ixgbe_phy_sfp_passive_tyco;
1502                                 break;
1503                         case IXGBE_SFF_VENDOR_OUI_FTL:
1504                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1505                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1506                                 else
1507                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1508                                 break;
1509                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1510                                 hw->phy.type = ixgbe_phy_sfp_avago;
1511                                 break;
1512                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1513                                 hw->phy.type = ixgbe_phy_sfp_intel;
1514                                 break;
1515                         default:
1516                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1517                                         hw->phy.type =
1518                                                  ixgbe_phy_sfp_passive_unknown;
1519                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1520                                         hw->phy.type =
1521                                                 ixgbe_phy_sfp_active_unknown;
1522                                 else
1523                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1524                                 break;
1525                         }
1526                 }
1527
1528                 /* Allow any DA cable vendor */
1529                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1530                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1531                         status = IXGBE_SUCCESS;
1532                         goto out;
1533                 }
1534
1535                 /* Verify supported 1G SFP modules */
1536                 if (comp_codes_10g == 0 &&
1537                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1538                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1539                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1540                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1541                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1542                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1543                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1544                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1545                         goto out;
1546                 }
1547
1548                 /* Anything else 82598-based is supported */
1549                 if (hw->mac.type == ixgbe_mac_82598EB) {
1550                         status = IXGBE_SUCCESS;
1551                         goto out;
1552                 }
1553
1554                 ixgbe_get_device_caps(hw, &enforce_sfp);
1555                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1556                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1557                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1558                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1559                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1560                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1561                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1562                         /* Make sure we're a supported PHY type */
1563                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1564                                 status = IXGBE_SUCCESS;
1565                         } else {
1566                                 if (hw->allow_unsupported_sfp == true) {
1567                                         EWARN(hw, "WARNING: Intel (R) Network "
1568                                               "Connections are quality tested "
1569                                               "using Intel (R) Ethernet Optics."
1570                                               " Using untested modules is not "
1571                                               "supported and may cause unstable"
1572                                               " operation or damage to the "
1573                                               "module or the adapter. Intel "
1574                                               "Corporation is not responsible "
1575                                               "for any harm caused by using "
1576                                               "untested modules.\n", status);
1577                                         status = IXGBE_SUCCESS;
1578                                 } else {
1579                                         DEBUGOUT("SFP+ module not supported\n");
1580                                         hw->phy.type =
1581                                                 ixgbe_phy_sfp_unsupported;
1582                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1583                                 }
1584                         }
1585                 } else {
1586                         status = IXGBE_SUCCESS;
1587                 }
1588         }
1589
1590 out:
1591         return status;
1592
1593 err_read_i2c_eeprom:
1594         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1595         if (hw->phy.type != ixgbe_phy_nl) {
1596                 hw->phy.id = 0;
1597                 hw->phy.type = ixgbe_phy_unknown;
1598         }
1599         return IXGBE_ERR_SFP_NOT_PRESENT;
1600 }
1601
1602 /**
1603  *  ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1604  *  @hw: pointer to hardware structure
1605  *
1606  *  Determines physical layer capabilities of the current SFP.
1607  */
1608 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1609 {
1610         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1611         u8 comp_codes_10g = 0;
1612         u8 comp_codes_1g = 0;
1613
1614         DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1615
1616         hw->phy.ops.identify_sfp(hw);
1617         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1618                 return physical_layer;
1619
1620         switch (hw->phy.type) {
1621         case ixgbe_phy_sfp_passive_tyco:
1622         case ixgbe_phy_sfp_passive_unknown:
1623         case ixgbe_phy_qsfp_passive_unknown:
1624                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1625                 break;
1626         case ixgbe_phy_sfp_ftl_active:
1627         case ixgbe_phy_sfp_active_unknown:
1628         case ixgbe_phy_qsfp_active_unknown:
1629                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1630                 break;
1631         case ixgbe_phy_sfp_avago:
1632         case ixgbe_phy_sfp_ftl:
1633         case ixgbe_phy_sfp_intel:
1634         case ixgbe_phy_sfp_unknown:
1635                 hw->phy.ops.read_i2c_eeprom(hw,
1636                       IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1637                 hw->phy.ops.read_i2c_eeprom(hw,
1638                       IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1639                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1640                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1641                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1642                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1643                 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1644                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1645                 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1646                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1647                 break;
1648         case ixgbe_phy_qsfp_intel:
1649         case ixgbe_phy_qsfp_unknown:
1650                 hw->phy.ops.read_i2c_eeprom(hw,
1651                       IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1652                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1653                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1654                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1655                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1656                 break;
1657         default:
1658                 break;
1659         }
1660
1661         return physical_layer;
1662 }
1663
1664 /**
1665  *  ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1666  *  @hw: pointer to hardware structure
1667  *
1668  *  Searches for and identifies the QSFP module and assigns appropriate PHY type
1669  **/
1670 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1671 {
1672         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1673         u32 vendor_oui = 0;
1674         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1675         u8 identifier = 0;
1676         u8 comp_codes_1g = 0;
1677         u8 comp_codes_10g = 0;
1678         u8 oui_bytes[3] = {0, 0, 0};
1679         u16 enforce_sfp = 0;
1680         u8 connector = 0;
1681         u8 cable_length = 0;
1682         u8 device_tech = 0;
1683         bool active_cable = false;
1684
1685         DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1686
1687         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1688                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1689                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1690                 goto out;
1691         }
1692
1693         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1694                                              &identifier);
1695
1696         if (status != IXGBE_SUCCESS)
1697                 goto err_read_i2c_eeprom;
1698
1699         if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1700                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1701                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1702                 goto out;
1703         }
1704
1705         hw->phy.id = identifier;
1706
1707         /* LAN ID is needed for sfp_type determination */
1708         hw->mac.ops.set_lan_id(hw);
1709
1710         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1711                                              &comp_codes_10g);
1712
1713         if (status != IXGBE_SUCCESS)
1714                 goto err_read_i2c_eeprom;
1715
1716         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1717                                              &comp_codes_1g);
1718
1719         if (status != IXGBE_SUCCESS)
1720                 goto err_read_i2c_eeprom;
1721
1722         if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1723                 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1724                 if (hw->bus.lan_id == 0)
1725                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1726                 else
1727                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1728         } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1729                                      IXGBE_SFF_10GBASELR_CAPABLE)) {
1730                 if (hw->bus.lan_id == 0)
1731                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1732                 else
1733                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1734         } else {
1735                 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1736                         active_cable = true;
1737
1738                 if (!active_cable) {
1739                         /* check for active DA cables that pre-date
1740                          * SFF-8436 v3.6 */
1741                         hw->phy.ops.read_i2c_eeprom(hw,
1742                                         IXGBE_SFF_QSFP_CONNECTOR,
1743                                         &connector);
1744
1745                         hw->phy.ops.read_i2c_eeprom(hw,
1746                                         IXGBE_SFF_QSFP_CABLE_LENGTH,
1747                                         &cable_length);
1748
1749                         hw->phy.ops.read_i2c_eeprom(hw,
1750                                         IXGBE_SFF_QSFP_DEVICE_TECH,
1751                                         &device_tech);
1752
1753                         if ((connector ==
1754                                      IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1755                             (cable_length > 0) &&
1756                             ((device_tech >> 4) ==
1757                                      IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1758                                 active_cable = true;
1759                 }
1760
1761                 if (active_cable) {
1762                         hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1763                         if (hw->bus.lan_id == 0)
1764                                 hw->phy.sfp_type =
1765                                                 ixgbe_sfp_type_da_act_lmt_core0;
1766                         else
1767                                 hw->phy.sfp_type =
1768                                                 ixgbe_sfp_type_da_act_lmt_core1;
1769                 } else {
1770                         /* unsupported module type */
1771                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1772                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1773                         goto out;
1774                 }
1775         }
1776
1777         if (hw->phy.sfp_type != stored_sfp_type)
1778                 hw->phy.sfp_setup_needed = true;
1779
1780         /* Determine if the QSFP+ PHY is dual speed or not. */
1781         hw->phy.multispeed_fiber = false;
1782         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1783            (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1784            ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1785            (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1786                 hw->phy.multispeed_fiber = true;
1787
1788         /* Determine PHY vendor for optical modules */
1789         if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1790                               IXGBE_SFF_10GBASELR_CAPABLE))  {
1791                 status = hw->phy.ops.read_i2c_eeprom(hw,
1792                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1793                                             &oui_bytes[0]);
1794
1795                 if (status != IXGBE_SUCCESS)
1796                         goto err_read_i2c_eeprom;
1797
1798                 status = hw->phy.ops.read_i2c_eeprom(hw,
1799                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1800                                             &oui_bytes[1]);
1801
1802                 if (status != IXGBE_SUCCESS)
1803                         goto err_read_i2c_eeprom;
1804
1805                 status = hw->phy.ops.read_i2c_eeprom(hw,
1806                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1807                                             &oui_bytes[2]);
1808
1809                 if (status != IXGBE_SUCCESS)
1810                         goto err_read_i2c_eeprom;
1811
1812                 vendor_oui =
1813                   ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1814                    (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1815                    (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1816
1817                 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1818                         hw->phy.type = ixgbe_phy_qsfp_intel;
1819                 else
1820                         hw->phy.type = ixgbe_phy_qsfp_unknown;
1821
1822                 ixgbe_get_device_caps(hw, &enforce_sfp);
1823                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1824                         /* Make sure we're a supported PHY type */
1825                         if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1826                                 status = IXGBE_SUCCESS;
1827                         } else {
1828                                 if (hw->allow_unsupported_sfp == true) {
1829                                         EWARN(hw, "WARNING: Intel (R) Network "
1830                                               "Connections are quality tested "
1831                                               "using Intel (R) Ethernet Optics."
1832                                               " Using untested modules is not "
1833                                               "supported and may cause unstable"
1834                                               " operation or damage to the "
1835                                               "module or the adapter. Intel "
1836                                               "Corporation is not responsible "
1837                                               "for any harm caused by using "
1838                                               "untested modules.\n", status);
1839                                         status = IXGBE_SUCCESS;
1840                                 } else {
1841                                         DEBUGOUT("QSFP module not supported\n");
1842                                         hw->phy.type =
1843                                                 ixgbe_phy_sfp_unsupported;
1844                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1845                                 }
1846                         }
1847                 } else {
1848                         status = IXGBE_SUCCESS;
1849                 }
1850         }
1851
1852 out:
1853         return status;
1854
1855 err_read_i2c_eeprom:
1856         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1857         hw->phy.id = 0;
1858         hw->phy.type = ixgbe_phy_unknown;
1859
1860         return IXGBE_ERR_SFP_NOT_PRESENT;
1861 }
1862
1863
1864 /**
1865  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1866  *  @hw: pointer to hardware structure
1867  *  @list_offset: offset to the SFP ID list
1868  *  @data_offset: offset to the SFP data block
1869  *
1870  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1871  *  so it returns the offsets to the phy init sequence block.
1872  **/
1873 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1874                                         u16 *list_offset,
1875                                         u16 *data_offset)
1876 {
1877         u16 sfp_id;
1878         u16 sfp_type = hw->phy.sfp_type;
1879
1880         DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1881
1882         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1883                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1884
1885         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1886                 return IXGBE_ERR_SFP_NOT_PRESENT;
1887
1888         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1889             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1890                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1891
1892         /*
1893          * Limiting active cables and 1G Phys must be initialized as
1894          * SR modules
1895          */
1896         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1897             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1898             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1899             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1900                 sfp_type = ixgbe_sfp_type_srlr_core0;
1901         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1902                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1903                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1904                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1905                 sfp_type = ixgbe_sfp_type_srlr_core1;
1906
1907         /* Read offset to PHY init contents */
1908         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1909                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1910                               "eeprom read at offset %d failed",
1911                               IXGBE_PHY_INIT_OFFSET_NL);
1912                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1913         }
1914
1915         if ((!*list_offset) || (*list_offset == 0xFFFF))
1916                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1917
1918         /* Shift offset to first ID word */
1919         (*list_offset)++;
1920
1921         /*
1922          * Find the matching SFP ID in the EEPROM
1923          * and program the init sequence
1924          */
1925         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1926                 goto err_phy;
1927
1928         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1929                 if (sfp_id == sfp_type) {
1930                         (*list_offset)++;
1931                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1932                                 goto err_phy;
1933                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1934                                 DEBUGOUT("SFP+ module not supported\n");
1935                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1936                         } else {
1937                                 break;
1938                         }
1939                 } else {
1940                         (*list_offset) += 2;
1941                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1942                                 goto err_phy;
1943                 }
1944         }
1945
1946         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1947                 DEBUGOUT("No matching SFP+ module found\n");
1948                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1949         }
1950
1951         return IXGBE_SUCCESS;
1952
1953 err_phy:
1954         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1955                       "eeprom read at offset %d failed", *list_offset);
1956         return IXGBE_ERR_PHY;
1957 }
1958
1959 /**
1960  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1961  *  @hw: pointer to hardware structure
1962  *  @byte_offset: EEPROM byte offset to read
1963  *  @eeprom_data: value read
1964  *
1965  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1966  **/
1967 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1968                                   u8 *eeprom_data)
1969 {
1970         DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1971
1972         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1973                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1974                                          eeprom_data);
1975 }
1976
1977 /**
1978  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1979  *  @hw: pointer to hardware structure
1980  *  @byte_offset: byte offset at address 0xA2
1981  *  @eeprom_data: value read
1982  *
1983  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
1984  **/
1985 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1986                                           u8 *sff8472_data)
1987 {
1988         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1989                                          IXGBE_I2C_EEPROM_DEV_ADDR2,
1990                                          sff8472_data);
1991 }
1992
1993 /**
1994  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1995  *  @hw: pointer to hardware structure
1996  *  @byte_offset: EEPROM byte offset to write
1997  *  @eeprom_data: value to write
1998  *
1999  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
2000  **/
2001 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
2002                                    u8 eeprom_data)
2003 {
2004         DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
2005
2006         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
2007                                           IXGBE_I2C_EEPROM_DEV_ADDR,
2008                                           eeprom_data);
2009 }
2010
2011 /**
2012  * ixgbe_is_sfp_probe - Returns true if SFP is being detected
2013  * @hw: pointer to hardware structure
2014  * @offset: eeprom offset to be read
2015  * @addr: I2C address to be read
2016  */
2017 STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
2018 {
2019         if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
2020             offset == IXGBE_SFF_IDENTIFIER &&
2021             hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2022                 return true;
2023         return false;
2024 }
2025
2026 /**
2027  *  ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
2028  *  @hw: pointer to hardware structure
2029  *  @byte_offset: byte offset to read
2030  *  @data: value read
2031  *  @lock: true if to take and release semaphore
2032  *
2033  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2034  *  a specified device address.
2035  **/
2036 STATIC s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2037                                            u8 dev_addr, u8 *data, bool lock)
2038 {
2039         s32 status;
2040         u32 max_retry = 10;
2041         u32 retry = 0;
2042         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2043         bool nack = 1;
2044         *data = 0;
2045
2046         DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2047
2048         if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2049                 max_retry = IXGBE_SFP_DETECT_RETRIES;
2050
2051         do {
2052                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2053                         return IXGBE_ERR_SWFW_SYNC;
2054
2055                 ixgbe_i2c_start(hw);
2056
2057                 /* Device Address and write indication */
2058                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2059                 if (status != IXGBE_SUCCESS)
2060                         goto fail;
2061
2062                 status = ixgbe_get_i2c_ack(hw);
2063                 if (status != IXGBE_SUCCESS)
2064                         goto fail;
2065
2066                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2067                 if (status != IXGBE_SUCCESS)
2068                         goto fail;
2069
2070                 status = ixgbe_get_i2c_ack(hw);
2071                 if (status != IXGBE_SUCCESS)
2072                         goto fail;
2073
2074                 ixgbe_i2c_start(hw);
2075
2076                 /* Device Address and read indication */
2077                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2078                 if (status != IXGBE_SUCCESS)
2079                         goto fail;
2080
2081                 status = ixgbe_get_i2c_ack(hw);
2082                 if (status != IXGBE_SUCCESS)
2083                         goto fail;
2084
2085                 status = ixgbe_clock_in_i2c_byte(hw, data);
2086                 if (status != IXGBE_SUCCESS)
2087                         goto fail;
2088
2089                 status = ixgbe_clock_out_i2c_bit(hw, nack);
2090                 if (status != IXGBE_SUCCESS)
2091                         goto fail;
2092
2093                 ixgbe_i2c_stop(hw);
2094                 if (lock)
2095                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2096                 return IXGBE_SUCCESS;
2097
2098 fail:
2099                 ixgbe_i2c_bus_clear(hw);
2100                 if (lock) {
2101                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2102                         msec_delay(100);
2103                 }
2104                 retry++;
2105                 if (retry < max_retry)
2106                         DEBUGOUT("I2C byte read error - Retrying.\n");
2107                 else
2108                         DEBUGOUT("I2C byte read error.\n");
2109
2110         } while (retry < max_retry);
2111
2112         return status;
2113 }
2114
2115 /**
2116  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2117  *  @hw: pointer to hardware structure
2118  *  @byte_offset: byte offset to read
2119  *  @data: value read
2120  *
2121  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2122  *  a specified device address.
2123  **/
2124 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2125                                 u8 dev_addr, u8 *data)
2126 {
2127         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2128                                                data, true);
2129 }
2130
2131 /**
2132  *  ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2133  *  @hw: pointer to hardware structure
2134  *  @byte_offset: byte offset to read
2135  *  @data: value read
2136  *
2137  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2138  *  a specified device address.
2139  **/
2140 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2141                                          u8 dev_addr, u8 *data)
2142 {
2143         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2144                                                data, false);
2145 }
2146
2147 /**
2148  *  ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2149  *  @hw: pointer to hardware structure
2150  *  @byte_offset: byte offset to write
2151  *  @data: value to write
2152  *  @lock: true if to take and release semaphore
2153  *
2154  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2155  *  a specified device address.
2156  **/
2157 STATIC s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2158                                             u8 dev_addr, u8 data, bool lock)
2159 {
2160         s32 status;
2161         u32 max_retry = 1;
2162         u32 retry = 0;
2163         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2164
2165         DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2166
2167         if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2168             IXGBE_SUCCESS)
2169                 return IXGBE_ERR_SWFW_SYNC;
2170
2171         do {
2172                 ixgbe_i2c_start(hw);
2173
2174                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2175                 if (status != IXGBE_SUCCESS)
2176                         goto fail;
2177
2178                 status = ixgbe_get_i2c_ack(hw);
2179                 if (status != IXGBE_SUCCESS)
2180                         goto fail;
2181
2182                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2183                 if (status != IXGBE_SUCCESS)
2184                         goto fail;
2185
2186                 status = ixgbe_get_i2c_ack(hw);
2187                 if (status != IXGBE_SUCCESS)
2188                         goto fail;
2189
2190                 status = ixgbe_clock_out_i2c_byte(hw, data);
2191                 if (status != IXGBE_SUCCESS)
2192                         goto fail;
2193
2194                 status = ixgbe_get_i2c_ack(hw);
2195                 if (status != IXGBE_SUCCESS)
2196                         goto fail;
2197
2198                 ixgbe_i2c_stop(hw);
2199                 if (lock)
2200                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2201                 return IXGBE_SUCCESS;
2202
2203 fail:
2204                 ixgbe_i2c_bus_clear(hw);
2205                 retry++;
2206                 if (retry < max_retry)
2207                         DEBUGOUT("I2C byte write error - Retrying.\n");
2208                 else
2209                         DEBUGOUT("I2C byte write error.\n");
2210         } while (retry < max_retry);
2211
2212         if (lock)
2213                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2214
2215         return status;
2216 }
2217
2218 /**
2219  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2220  *  @hw: pointer to hardware structure
2221  *  @byte_offset: byte offset to write
2222  *  @data: value to write
2223  *
2224  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2225  *  a specified device address.
2226  **/
2227 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2228                                  u8 dev_addr, u8 data)
2229 {
2230         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2231                                                 data, true);
2232 }
2233
2234 /**
2235  *  ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2236  *  @hw: pointer to hardware structure
2237  *  @byte_offset: byte offset to write
2238  *  @data: value to write
2239  *
2240  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2241  *  a specified device address.
2242  **/
2243 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2244                                           u8 dev_addr, u8 data)
2245 {
2246         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2247                                                 data, false);
2248 }
2249
2250 /**
2251  *  ixgbe_i2c_start - Sets I2C start condition
2252  *  @hw: pointer to hardware structure
2253  *
2254  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
2255  *  Set bit-bang mode on X550 hardware.
2256  **/
2257 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2258 {
2259         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2260
2261         DEBUGFUNC("ixgbe_i2c_start");
2262
2263         i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2264
2265         /* Start condition must begin with data and clock high */
2266         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2267         ixgbe_raise_i2c_clk(hw, &i2cctl);
2268
2269         /* Setup time for start condition (4.7us) */
2270         usec_delay(IXGBE_I2C_T_SU_STA);
2271
2272         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2273
2274         /* Hold time for start condition (4us) */
2275         usec_delay(IXGBE_I2C_T_HD_STA);
2276
2277         ixgbe_lower_i2c_clk(hw, &i2cctl);
2278
2279         /* Minimum low period of clock is 4.7 us */
2280         usec_delay(IXGBE_I2C_T_LOW);
2281
2282 }
2283
2284 /**
2285  *  ixgbe_i2c_stop - Sets I2C stop condition
2286  *  @hw: pointer to hardware structure
2287  *
2288  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
2289  *  Disables bit-bang mode and negates data output enable on X550
2290  *  hardware.
2291  **/
2292 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2293 {
2294         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2295         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2296         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2297         u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2298
2299         DEBUGFUNC("ixgbe_i2c_stop");
2300
2301         /* Stop condition must begin with data low and clock high */
2302         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2303         ixgbe_raise_i2c_clk(hw, &i2cctl);
2304
2305         /* Setup time for stop condition (4us) */
2306         usec_delay(IXGBE_I2C_T_SU_STO);
2307
2308         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2309
2310         /* bus free time between stop and start (4.7us)*/
2311         usec_delay(IXGBE_I2C_T_BUF);
2312
2313         if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2314                 i2cctl &= ~bb_en_bit;
2315                 i2cctl |= data_oe_bit | clk_oe_bit;
2316                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2317                 IXGBE_WRITE_FLUSH(hw);
2318         }
2319 }
2320
2321 /**
2322  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2323  *  @hw: pointer to hardware structure
2324  *  @data: data byte to clock in
2325  *
2326  *  Clocks in one byte data via I2C data/clock
2327  **/
2328 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2329 {
2330         s32 i;
2331         bool bit = 0;
2332
2333         DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2334
2335         *data = 0;
2336         for (i = 7; i >= 0; i--) {
2337                 ixgbe_clock_in_i2c_bit(hw, &bit);
2338                 *data |= bit << i;
2339         }
2340
2341         return IXGBE_SUCCESS;
2342 }
2343
2344 /**
2345  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2346  *  @hw: pointer to hardware structure
2347  *  @data: data byte clocked out
2348  *
2349  *  Clocks out one byte data via I2C data/clock
2350  **/
2351 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2352 {
2353         s32 status = IXGBE_SUCCESS;
2354         s32 i;
2355         u32 i2cctl;
2356         bool bit;
2357
2358         DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2359
2360         for (i = 7; i >= 0; i--) {
2361                 bit = (data >> i) & 0x1;
2362                 status = ixgbe_clock_out_i2c_bit(hw, bit);
2363
2364                 if (status != IXGBE_SUCCESS)
2365                         break;
2366         }
2367
2368         /* Release SDA line (set high) */
2369         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2370         i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2371         i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2372         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2373         IXGBE_WRITE_FLUSH(hw);
2374
2375         return status;
2376 }
2377
2378 /**
2379  *  ixgbe_get_i2c_ack - Polls for I2C ACK
2380  *  @hw: pointer to hardware structure
2381  *
2382  *  Clocks in/out one bit via I2C data/clock
2383  **/
2384 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2385 {
2386         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2387         s32 status = IXGBE_SUCCESS;
2388         u32 i = 0;
2389         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2390         u32 timeout = 10;
2391         bool ack = 1;
2392
2393         DEBUGFUNC("ixgbe_get_i2c_ack");
2394
2395         if (data_oe_bit) {
2396                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2397                 i2cctl |= data_oe_bit;
2398                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2399                 IXGBE_WRITE_FLUSH(hw);
2400         }
2401         ixgbe_raise_i2c_clk(hw, &i2cctl);
2402
2403         /* Minimum high period of clock is 4us */
2404         usec_delay(IXGBE_I2C_T_HIGH);
2405
2406         /* Poll for ACK.  Note that ACK in I2C spec is
2407          * transition from 1 to 0 */
2408         for (i = 0; i < timeout; i++) {
2409                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2410                 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2411
2412                 usec_delay(1);
2413                 if (!ack)
2414                         break;
2415         }
2416
2417         if (ack) {
2418                 DEBUGOUT("I2C ack was not received.\n");
2419                 status = IXGBE_ERR_I2C;
2420         }
2421
2422         ixgbe_lower_i2c_clk(hw, &i2cctl);
2423
2424         /* Minimum low period of clock is 4.7 us */
2425         usec_delay(IXGBE_I2C_T_LOW);
2426
2427         return status;
2428 }
2429
2430 /**
2431  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2432  *  @hw: pointer to hardware structure
2433  *  @data: read data value
2434  *
2435  *  Clocks in one bit via I2C data/clock
2436  **/
2437 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2438 {
2439         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2440         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2441
2442         DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2443
2444         if (data_oe_bit) {
2445                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2446                 i2cctl |= data_oe_bit;
2447                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2448                 IXGBE_WRITE_FLUSH(hw);
2449         }
2450         ixgbe_raise_i2c_clk(hw, &i2cctl);
2451
2452         /* Minimum high period of clock is 4us */
2453         usec_delay(IXGBE_I2C_T_HIGH);
2454
2455         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2456         *data = ixgbe_get_i2c_data(hw, &i2cctl);
2457
2458         ixgbe_lower_i2c_clk(hw, &i2cctl);
2459
2460         /* Minimum low period of clock is 4.7 us */
2461         usec_delay(IXGBE_I2C_T_LOW);
2462
2463         return IXGBE_SUCCESS;
2464 }
2465
2466 /**
2467  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2468  *  @hw: pointer to hardware structure
2469  *  @data: data value to write
2470  *
2471  *  Clocks out one bit via I2C data/clock
2472  **/
2473 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2474 {
2475         s32 status;
2476         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2477
2478         DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2479
2480         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2481         if (status == IXGBE_SUCCESS) {
2482                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2483
2484                 /* Minimum high period of clock is 4us */
2485                 usec_delay(IXGBE_I2C_T_HIGH);
2486
2487                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2488
2489                 /* Minimum low period of clock is 4.7 us.
2490                  * This also takes care of the data hold time.
2491                  */
2492                 usec_delay(IXGBE_I2C_T_LOW);
2493         } else {
2494                 status = IXGBE_ERR_I2C;
2495                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2496                              "I2C data was not set to %X\n", data);
2497         }
2498
2499         return status;
2500 }
2501
2502 /**
2503  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2504  *  @hw: pointer to hardware structure
2505  *  @i2cctl: Current value of I2CCTL register
2506  *
2507  *  Raises the I2C clock line '0'->'1'
2508  *  Negates the I2C clock output enable on X550 hardware.
2509  **/
2510 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2511 {
2512         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2513         u32 i = 0;
2514         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2515         u32 i2cctl_r = 0;
2516
2517         DEBUGFUNC("ixgbe_raise_i2c_clk");
2518
2519         if (clk_oe_bit) {
2520                 *i2cctl |= clk_oe_bit;
2521                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2522         }
2523
2524         for (i = 0; i < timeout; i++) {
2525                 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2526
2527                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2528                 IXGBE_WRITE_FLUSH(hw);
2529                 /* SCL rise time (1000ns) */
2530                 usec_delay(IXGBE_I2C_T_RISE);
2531
2532                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2533                 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2534                         break;
2535         }
2536 }
2537
2538 /**
2539  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2540  *  @hw: pointer to hardware structure
2541  *  @i2cctl: Current value of I2CCTL register
2542  *
2543  *  Lowers the I2C clock line '1'->'0'
2544  *  Asserts the I2C clock output enable on X550 hardware.
2545  **/
2546 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2547 {
2548         DEBUGFUNC("ixgbe_lower_i2c_clk");
2549
2550         *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2551         *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2552
2553         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2554         IXGBE_WRITE_FLUSH(hw);
2555
2556         /* SCL fall time (300ns) */
2557         usec_delay(IXGBE_I2C_T_FALL);
2558 }
2559
2560 /**
2561  *  ixgbe_set_i2c_data - Sets the I2C data bit
2562  *  @hw: pointer to hardware structure
2563  *  @i2cctl: Current value of I2CCTL register
2564  *  @data: I2C data value (0 or 1) to set
2565  *
2566  *  Sets the I2C data bit
2567  *  Asserts the I2C data output enable on X550 hardware.
2568  **/
2569 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2570 {
2571         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2572         s32 status = IXGBE_SUCCESS;
2573
2574         DEBUGFUNC("ixgbe_set_i2c_data");
2575
2576         if (data)
2577                 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2578         else
2579                 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2580         *i2cctl &= ~data_oe_bit;
2581
2582         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2583         IXGBE_WRITE_FLUSH(hw);
2584
2585         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2586         usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2587
2588         if (!data)      /* Can't verify data in this case */
2589                 return IXGBE_SUCCESS;
2590         if (data_oe_bit) {
2591                 *i2cctl |= data_oe_bit;
2592                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2593                 IXGBE_WRITE_FLUSH(hw);
2594         }
2595
2596         /* Verify data was set correctly */
2597         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2598         if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2599                 status = IXGBE_ERR_I2C;
2600                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2601                              "Error - I2C data was not set to %X.\n",
2602                              data);
2603         }
2604
2605         return status;
2606 }
2607
2608 /**
2609  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
2610  *  @hw: pointer to hardware structure
2611  *  @i2cctl: Current value of I2CCTL register
2612  *
2613  *  Returns the I2C data bit value
2614  *  Negates the I2C data output enable on X550 hardware.
2615  **/
2616 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2617 {
2618         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2619         bool data;
2620
2621         DEBUGFUNC("ixgbe_get_i2c_data");
2622
2623         if (data_oe_bit) {
2624                 *i2cctl |= data_oe_bit;
2625                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2626                 IXGBE_WRITE_FLUSH(hw);
2627                 usec_delay(IXGBE_I2C_T_FALL);
2628         }
2629
2630         if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2631                 data = 1;
2632         else
2633                 data = 0;
2634
2635         return data;
2636 }
2637
2638 /**
2639  *  ixgbe_i2c_bus_clear - Clears the I2C bus
2640  *  @hw: pointer to hardware structure
2641  *
2642  *  Clears the I2C bus by sending nine clock pulses.
2643  *  Used when data line is stuck low.
2644  **/
2645 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2646 {
2647         u32 i2cctl;
2648         u32 i;
2649
2650         DEBUGFUNC("ixgbe_i2c_bus_clear");
2651
2652         ixgbe_i2c_start(hw);
2653         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2654
2655         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2656
2657         for (i = 0; i < 9; i++) {
2658                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2659
2660                 /* Min high period of clock is 4us */
2661                 usec_delay(IXGBE_I2C_T_HIGH);
2662
2663                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2664
2665                 /* Min low period of clock is 4.7us*/
2666                 usec_delay(IXGBE_I2C_T_LOW);
2667         }
2668
2669         ixgbe_i2c_start(hw);
2670
2671         /* Put the i2c bus back to default state */
2672         ixgbe_i2c_stop(hw);
2673 }
2674
2675 /**
2676  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2677  *  @hw: pointer to hardware structure
2678  *
2679  *  Checks if the LASI temp alarm status was triggered due to overtemp
2680  **/
2681 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2682 {
2683         s32 status = IXGBE_SUCCESS;
2684         u16 phy_data = 0;
2685
2686         DEBUGFUNC("ixgbe_tn_check_overtemp");
2687
2688         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2689                 goto out;
2690
2691         /* Check that the LASI temp alarm status was triggered */
2692         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2693                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2694
2695         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2696                 goto out;
2697
2698         status = IXGBE_ERR_OVERTEMP;
2699         ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2700 out:
2701         return status;
2702 }
2703
2704 /**
2705  * ixgbe_set_copper_phy_power - Control power for copper phy
2706  * @hw: pointer to hardware structure
2707  * @on: true for on, false for off
2708  */
2709 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2710 {
2711         u32 status;
2712         u16 reg;
2713
2714         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2715                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2716                                       &reg);
2717         if (status)
2718                 return status;
2719
2720         if (on) {
2721                 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2722         } else {
2723                 if (ixgbe_check_reset_blocked(hw))
2724                         return 0;
2725                 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2726         }
2727
2728         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2729                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2730                                        reg);
2731         return status;
2732 }