1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_api.h"
35 #include "ixgbe_common.h"
36 #include "ixgbe_phy.h"
38 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
39 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
40 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
41 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
42 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
43 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
44 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
45 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
46 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
47 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
48 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
49 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
53 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
54 * @hw: pointer to the hardware structure
57 * Returns an error code on error.
59 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
63 status = ixgbe_clock_out_i2c_byte(hw, byte);
66 return ixgbe_get_i2c_ack(hw);
70 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
71 * @hw: pointer to the hardware structure
72 * @byte: pointer to a u8 to receive the byte
74 * Returns an error code on error.
76 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
80 status = ixgbe_clock_in_i2c_byte(hw, byte);
84 return ixgbe_clock_out_i2c_bit(hw, false);
88 * ixgbe_ones_comp_byte_add - Perform one's complement addition
92 * Returns one's complement 8-bit sum.
94 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
96 u16 sum = add1 + add2;
98 sum = (sum & 0xFF) + (sum >> 8);
103 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
104 * @hw: pointer to the hardware structure
105 * @addr: I2C bus address to read from
106 * @reg: I2C device register to read from
107 * @val: pointer to location to receive read value
108 * @lock: true if to take and release semaphore
110 * Returns an error code on error.
112 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
115 u32 swfw_mask = hw->phy.phy_semaphore_mask;
124 if (hw->mac.type >= ixgbe_mac_X550)
126 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
127 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
130 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
131 return IXGBE_ERR_SWFW_SYNC;
133 /* Device Address and write indication */
134 if (ixgbe_out_i2c_byte_ack(hw, addr))
136 /* Write bits 14:8 */
137 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
140 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
143 if (ixgbe_out_i2c_byte_ack(hw, csum))
145 /* Re-start condition */
147 /* Device Address and read indication */
148 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
151 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
154 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
157 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
160 if (ixgbe_clock_out_i2c_bit(hw, false))
164 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
165 *val = (high_bits << 8) | low_bits;
169 ixgbe_i2c_bus_clear(hw);
171 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
173 if (retry < max_retry)
174 DEBUGOUT("I2C byte read combined error - Retrying.\n");
176 DEBUGOUT("I2C byte read combined error.\n");
177 } while (retry < max_retry);
179 return IXGBE_ERR_I2C;
183 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
184 * @hw: pointer to the hardware structure
185 * @addr: I2C bus address to write to
186 * @reg: I2C device register to write to
187 * @val: value to write
188 * @lock: true if to take and release semaphore
190 * Returns an error code on error.
192 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
195 u32 swfw_mask = hw->phy.phy_semaphore_mask;
201 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
202 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
203 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
204 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
207 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
208 return IXGBE_ERR_SWFW_SYNC;
210 /* Device Address and write indication */
211 if (ixgbe_out_i2c_byte_ack(hw, addr))
213 /* Write bits 14:8 */
214 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
217 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
219 /* Write data 15:8 */
220 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
223 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
226 if (ixgbe_out_i2c_byte_ack(hw, csum))
230 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
234 ixgbe_i2c_bus_clear(hw);
236 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
238 if (retry < max_retry)
239 DEBUGOUT("I2C byte write combined error - Retrying.\n");
241 DEBUGOUT("I2C byte write combined error.\n");
242 } while (retry < max_retry);
244 return IXGBE_ERR_I2C;
248 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
249 * @hw: pointer to the hardware structure
251 * Initialize the function pointers.
253 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
255 struct ixgbe_phy_info *phy = &hw->phy;
257 DEBUGFUNC("ixgbe_init_phy_ops_generic");
260 phy->ops.identify = ixgbe_identify_phy_generic;
261 phy->ops.reset = ixgbe_reset_phy_generic;
262 phy->ops.read_reg = ixgbe_read_phy_reg_generic;
263 phy->ops.write_reg = ixgbe_write_phy_reg_generic;
264 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
265 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
266 phy->ops.setup_link = ixgbe_setup_phy_link_generic;
267 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
268 phy->ops.check_link = NULL;
269 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
270 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
271 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
272 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
273 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
274 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
275 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
276 phy->ops.identify_sfp = ixgbe_identify_module_generic;
277 phy->sfp_type = ixgbe_sfp_type_unknown;
278 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
279 phy->ops.write_i2c_byte_unlocked =
280 ixgbe_write_i2c_byte_generic_unlocked;
281 phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
282 return IXGBE_SUCCESS;
286 * ixgbe_probe_phy - Probe a single address for a PHY
287 * @hw: pointer to hardware structure
288 * @phy_addr: PHY address to probe
290 * Returns true if PHY found
292 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
296 if (!ixgbe_validate_phy_addr(hw, phy_addr))
299 if (ixgbe_get_phy_id(hw))
302 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
304 if (hw->phy.type == ixgbe_phy_unknown) {
305 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
306 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
308 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
309 IXGBE_MDIO_PHY_1000BASET_ABILITY))
310 hw->phy.type = ixgbe_phy_cu_unknown;
312 hw->phy.type = ixgbe_phy_generic;
319 * ixgbe_identify_phy_generic - Get physical layer module
320 * @hw: pointer to hardware structure
322 * Determines the physical layer module found on the current adapter.
324 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
326 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
329 DEBUGFUNC("ixgbe_identify_phy_generic");
331 if (!hw->phy.phy_semaphore_mask) {
333 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
335 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
338 if (hw->phy.type != ixgbe_phy_unknown)
339 return IXGBE_SUCCESS;
341 if (hw->phy.nw_mng_if_sel) {
342 phy_addr = (hw->phy.nw_mng_if_sel &
343 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
344 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
345 if (ixgbe_probe_phy(hw, phy_addr))
346 return IXGBE_SUCCESS;
348 return IXGBE_ERR_PHY_ADDR_INVALID;
351 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
352 if (ixgbe_probe_phy(hw, phy_addr)) {
353 status = IXGBE_SUCCESS;
358 /* Certain media types do not have a phy so an address will not
359 * be found and the code will take this path. Caller has to
360 * decide if it is an error or not.
362 if (status != IXGBE_SUCCESS)
369 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
370 * @hw: pointer to the hardware structure
372 * This function checks the MMNGC.MNG_VETO bit to see if there are
373 * any constraints on link from manageability. For MAC's that don't
374 * have this bit just return faluse since the link can not be blocked
377 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
381 DEBUGFUNC("ixgbe_check_reset_blocked");
383 /* If we don't have this bit, it can't be blocking */
384 if (hw->mac.type == ixgbe_mac_82598EB)
387 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
388 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
389 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
390 "MNG_VETO bit detected.\n");
398 * ixgbe_validate_phy_addr - Determines phy address is valid
399 * @hw: pointer to hardware structure
402 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
407 DEBUGFUNC("ixgbe_validate_phy_addr");
409 hw->phy.addr = phy_addr;
410 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
411 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
413 if (phy_id != 0xFFFF && phy_id != 0x0)
420 * ixgbe_get_phy_id - Get the phy type
421 * @hw: pointer to hardware structure
424 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
430 DEBUGFUNC("ixgbe_get_phy_id");
432 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
433 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
436 if (status == IXGBE_SUCCESS) {
437 hw->phy.id = (u32)(phy_id_high << 16);
438 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
439 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
441 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
442 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
448 * ixgbe_get_phy_type_from_id - Get the phy type
449 * @phy_id: PHY ID information
452 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
454 enum ixgbe_phy_type phy_type;
456 DEBUGFUNC("ixgbe_get_phy_type_from_id");
460 phy_type = ixgbe_phy_tn;
466 phy_type = ixgbe_phy_aq;
469 phy_type = ixgbe_phy_qt;
472 phy_type = ixgbe_phy_nl;
476 phy_type = ixgbe_phy_x550em_ext_t;
478 case IXGBE_M88E1500_E_PHY_ID:
479 case IXGBE_M88E1543_E_PHY_ID:
480 phy_type = ixgbe_phy_m88;
483 phy_type = ixgbe_phy_unknown;
490 * ixgbe_reset_phy_generic - Performs a PHY reset
491 * @hw: pointer to hardware structure
493 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
497 s32 status = IXGBE_SUCCESS;
499 DEBUGFUNC("ixgbe_reset_phy_generic");
501 if (hw->phy.type == ixgbe_phy_unknown)
502 status = ixgbe_identify_phy_generic(hw);
504 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
507 /* Don't reset PHY if it's shut down due to overtemp. */
508 if (!hw->phy.reset_if_overtemp &&
509 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
512 /* Blocked by MNG FW so bail */
513 if (ixgbe_check_reset_blocked(hw))
517 * Perform soft PHY reset to the PHY_XS.
518 * This will cause a soft reset to the PHY
520 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
521 IXGBE_MDIO_PHY_XS_DEV_TYPE,
522 IXGBE_MDIO_PHY_XS_RESET);
525 * Poll for reset bit to self-clear indicating reset is complete.
526 * Some PHYs could take up to 3 seconds to complete and need about
527 * 1.7 usec delay after the reset is complete.
529 for (i = 0; i < 30; i++) {
531 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
532 status = hw->phy.ops.read_reg(hw,
533 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
534 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
536 if (status != IXGBE_SUCCESS)
539 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
544 status = hw->phy.ops.read_reg(hw,
545 IXGBE_MDIO_PHY_XS_CONTROL,
546 IXGBE_MDIO_PHY_XS_DEV_TYPE,
548 if (status != IXGBE_SUCCESS)
551 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
558 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
559 status = IXGBE_ERR_RESET_FAILED;
560 ERROR_REPORT1(IXGBE_ERROR_POLLING,
561 "PHY reset polling failed to complete.\n");
569 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
571 * @hw: pointer to hardware structure
572 * @reg_addr: 32 bit address of PHY register to read
573 * @phy_data: Pointer to read data from PHY register
575 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
578 u32 i, data, command;
580 /* Setup and write the address cycle command */
581 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
582 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
583 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
584 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
586 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
589 * Check every 10 usec to see if the address cycle completed.
590 * The MDI Command bit will clear when the operation is
593 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
596 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
597 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
602 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
603 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
604 return IXGBE_ERR_PHY;
608 * Address cycle complete, setup and write the read
611 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
612 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
613 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
614 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
616 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
619 * Check every 10 usec to see if the address cycle
620 * completed. The MDI Command bit will clear when the
621 * operation is complete
623 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
626 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
627 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
631 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
632 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
633 return IXGBE_ERR_PHY;
637 * Read operation is complete. Get the data
640 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
641 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
642 *phy_data = (u16)(data);
644 return IXGBE_SUCCESS;
648 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
649 * using the SWFW lock - this function is needed in most cases
650 * @hw: pointer to hardware structure
651 * @reg_addr: 32 bit address of PHY register to read
652 * @phy_data: Pointer to read data from PHY register
654 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
655 u32 device_type, u16 *phy_data)
658 u32 gssr = hw->phy.phy_semaphore_mask;
660 DEBUGFUNC("ixgbe_read_phy_reg_generic");
662 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
663 return IXGBE_ERR_SWFW_SYNC;
665 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
667 hw->mac.ops.release_swfw_sync(hw, gssr);
673 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
675 * @hw: pointer to hardware structure
676 * @reg_addr: 32 bit PHY register to write
677 * @device_type: 5 bit device type
678 * @phy_data: Data to write to the PHY register
680 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
681 u32 device_type, u16 phy_data)
685 /* Put the data in the MDI single read and write data register*/
686 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
688 /* Setup and write the address cycle command */
689 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
690 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
691 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
692 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
694 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
697 * Check every 10 usec to see if the address cycle completed.
698 * The MDI Command bit will clear when the operation is
701 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
704 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
705 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
709 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
710 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
711 return IXGBE_ERR_PHY;
715 * Address cycle complete, setup and write the write
718 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
719 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
720 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
721 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
723 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
726 * Check every 10 usec to see if the address cycle
727 * completed. The MDI Command bit will clear when the
728 * operation is complete
730 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
733 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
734 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
738 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
739 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
740 return IXGBE_ERR_PHY;
743 return IXGBE_SUCCESS;
747 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
748 * using SWFW lock- this function is needed in most cases
749 * @hw: pointer to hardware structure
750 * @reg_addr: 32 bit PHY register to write
751 * @device_type: 5 bit device type
752 * @phy_data: Data to write to the PHY register
754 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
755 u32 device_type, u16 phy_data)
758 u32 gssr = hw->phy.phy_semaphore_mask;
760 DEBUGFUNC("ixgbe_write_phy_reg_generic");
762 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
763 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
765 hw->mac.ops.release_swfw_sync(hw, gssr);
767 status = IXGBE_ERR_SWFW_SYNC;
774 * ixgbe_setup_phy_link_generic - Set and restart auto-neg
775 * @hw: pointer to hardware structure
777 * Restart auto-negotiation and PHY and waits for completion.
779 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
781 s32 status = IXGBE_SUCCESS;
782 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
783 bool autoneg = false;
784 ixgbe_link_speed speed;
786 DEBUGFUNC("ixgbe_setup_phy_link_generic");
788 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
790 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
791 /* Set or unset auto-negotiation 10G advertisement */
792 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
793 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
796 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
797 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
798 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
800 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
801 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
805 if (hw->mac.type == ixgbe_mac_X550) {
806 if (speed & IXGBE_LINK_SPEED_5GB_FULL) {
807 /* Set or unset auto-negotiation 5G advertisement */
808 hw->phy.ops.read_reg(hw,
809 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
810 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
813 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
814 if (hw->phy.autoneg_advertised &
815 IXGBE_LINK_SPEED_5GB_FULL)
816 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
818 hw->phy.ops.write_reg(hw,
819 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
820 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
824 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) {
825 /* Set or unset auto-negotiation 2.5G advertisement */
826 hw->phy.ops.read_reg(hw,
827 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
828 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
831 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
832 if (hw->phy.autoneg_advertised &
833 IXGBE_LINK_SPEED_2_5GB_FULL)
834 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
836 hw->phy.ops.write_reg(hw,
837 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
838 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
843 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
844 /* Set or unset auto-negotiation 1G advertisement */
845 hw->phy.ops.read_reg(hw,
846 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
847 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
850 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
851 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
852 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
854 hw->phy.ops.write_reg(hw,
855 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
856 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
860 if (speed & IXGBE_LINK_SPEED_100_FULL) {
861 /* Set or unset auto-negotiation 100M advertisement */
862 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
863 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
866 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
867 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
868 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
869 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
871 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
872 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
876 /* Blocked by MNG FW so don't reset PHY */
877 if (ixgbe_check_reset_blocked(hw))
880 /* Restart PHY auto-negotiation. */
881 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
882 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
884 autoneg_reg |= IXGBE_MII_RESTART;
886 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
887 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
893 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
894 * @hw: pointer to hardware structure
895 * @speed: new link speed
897 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
898 ixgbe_link_speed speed,
899 bool autoneg_wait_to_complete)
901 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
903 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
906 * Clear autoneg_advertised and set new values based on input link
909 hw->phy.autoneg_advertised = 0;
911 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
912 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
914 if (speed & IXGBE_LINK_SPEED_5GB_FULL)
915 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
917 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
918 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
920 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
921 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
923 if (speed & IXGBE_LINK_SPEED_100_FULL)
924 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
926 if (speed & IXGBE_LINK_SPEED_10_FULL)
927 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
929 /* Setup link based on the new speed settings */
930 ixgbe_setup_phy_link(hw);
932 return IXGBE_SUCCESS;
936 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
937 * @hw: pointer to hardware structure
939 * Determines the supported link capabilities by reading the PHY auto
940 * negotiation register.
942 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
947 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
948 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
953 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
954 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
955 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
956 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
957 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
958 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
960 switch (hw->mac.type) {
962 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
963 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
965 case ixgbe_mac_X550EM_x:
966 case ixgbe_mac_X550EM_a:
967 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
977 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
978 * @hw: pointer to hardware structure
979 * @speed: pointer to link speed
980 * @autoneg: boolean auto-negotiation value
982 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
983 ixgbe_link_speed *speed,
986 s32 status = IXGBE_SUCCESS;
988 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
991 if (!hw->phy.speeds_supported)
992 status = ixgbe_get_copper_speeds_supported(hw);
994 *speed = hw->phy.speeds_supported;
999 * ixgbe_check_phy_link_tnx - Determine link and speed status
1000 * @hw: pointer to hardware structure
1002 * Reads the VS1 register to determine if link is up and the current speed for
1005 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1008 s32 status = IXGBE_SUCCESS;
1010 u32 max_time_out = 10;
1015 DEBUGFUNC("ixgbe_check_phy_link_tnx");
1017 /* Initialize speed and link to default case */
1019 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1022 * Check current speed and link status of the PHY register.
1023 * This is a vendor specific register and may have to
1024 * be changed for other copper PHYs.
1026 for (time_out = 0; time_out < max_time_out; time_out++) {
1028 status = hw->phy.ops.read_reg(hw,
1029 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1030 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1032 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1033 phy_speed = phy_data &
1034 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1035 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1038 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1039 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1048 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1049 * @hw: pointer to hardware structure
1051 * Restart auto-negotiation and PHY and waits for completion.
1053 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1055 s32 status = IXGBE_SUCCESS;
1056 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1057 bool autoneg = false;
1058 ixgbe_link_speed speed;
1060 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1062 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1064 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1065 /* Set or unset auto-negotiation 10G advertisement */
1066 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1067 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1070 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1071 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1072 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1074 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1075 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1079 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1080 /* Set or unset auto-negotiation 1G advertisement */
1081 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1082 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1085 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1086 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1087 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1089 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1090 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1094 if (speed & IXGBE_LINK_SPEED_100_FULL) {
1095 /* Set or unset auto-negotiation 100M advertisement */
1096 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1097 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1100 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1101 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1102 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1104 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1105 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1109 /* Blocked by MNG FW so don't reset PHY */
1110 if (ixgbe_check_reset_blocked(hw))
1113 /* Restart PHY auto-negotiation. */
1114 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1115 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1117 autoneg_reg |= IXGBE_MII_RESTART;
1119 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1120 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1126 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1127 * @hw: pointer to hardware structure
1128 * @firmware_version: pointer to the PHY Firmware Version
1130 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1131 u16 *firmware_version)
1135 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1137 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1138 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1145 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1146 * @hw: pointer to hardware structure
1147 * @firmware_version: pointer to the PHY Firmware Version
1149 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1150 u16 *firmware_version)
1154 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1156 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1157 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1164 * ixgbe_reset_phy_nl - Performs a PHY reset
1165 * @hw: pointer to hardware structure
1167 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1169 u16 phy_offset, control, eword, edata, block_crc;
1170 bool end_data = false;
1171 u16 list_offset, data_offset;
1173 s32 ret_val = IXGBE_SUCCESS;
1176 DEBUGFUNC("ixgbe_reset_phy_nl");
1178 /* Blocked by MNG FW so bail */
1179 if (ixgbe_check_reset_blocked(hw))
1182 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1183 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1185 /* reset the PHY and poll for completion */
1186 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1187 IXGBE_MDIO_PHY_XS_DEV_TYPE,
1188 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1190 for (i = 0; i < 100; i++) {
1191 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1192 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1193 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1198 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1199 DEBUGOUT("PHY reset did not complete.\n");
1200 ret_val = IXGBE_ERR_PHY;
1204 /* Get init offsets */
1205 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1207 if (ret_val != IXGBE_SUCCESS)
1210 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1214 * Read control word from PHY init contents offset
1216 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1219 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1220 IXGBE_CONTROL_SHIFT_NL;
1221 edata = eword & IXGBE_DATA_MASK_NL;
1223 case IXGBE_DELAY_NL:
1225 DEBUGOUT1("DELAY: %d MS\n", edata);
1229 DEBUGOUT("DATA:\n");
1231 ret_val = hw->eeprom.ops.read(hw, data_offset,
1236 for (i = 0; i < edata; i++) {
1237 ret_val = hw->eeprom.ops.read(hw, data_offset,
1241 hw->phy.ops.write_reg(hw, phy_offset,
1242 IXGBE_TWINAX_DEV, eword);
1243 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1249 case IXGBE_CONTROL_NL:
1251 DEBUGOUT("CONTROL:\n");
1252 if (edata == IXGBE_CONTROL_EOL_NL) {
1255 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1258 DEBUGOUT("Bad control value\n");
1259 ret_val = IXGBE_ERR_PHY;
1264 DEBUGOUT("Bad control type\n");
1265 ret_val = IXGBE_ERR_PHY;
1274 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1275 "eeprom read at offset %d failed", data_offset);
1276 return IXGBE_ERR_PHY;
1280 * ixgbe_identify_module_generic - Identifies module type
1281 * @hw: pointer to hardware structure
1283 * Determines HW type and calls appropriate function.
1285 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1287 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1289 DEBUGFUNC("ixgbe_identify_module_generic");
1291 switch (hw->mac.ops.get_media_type(hw)) {
1292 case ixgbe_media_type_fiber:
1293 status = ixgbe_identify_sfp_module_generic(hw);
1296 case ixgbe_media_type_fiber_qsfp:
1297 status = ixgbe_identify_qsfp_module_generic(hw);
1301 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1302 status = IXGBE_ERR_SFP_NOT_PRESENT;
1310 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1311 * @hw: pointer to hardware structure
1313 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1315 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1317 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1319 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1321 u8 comp_codes_1g = 0;
1322 u8 comp_codes_10g = 0;
1323 u8 oui_bytes[3] = {0, 0, 0};
1326 u16 enforce_sfp = 0;
1328 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1330 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1331 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1332 status = IXGBE_ERR_SFP_NOT_PRESENT;
1336 /* LAN ID is needed for I2C access */
1337 hw->mac.ops.set_lan_id(hw);
1339 status = hw->phy.ops.read_i2c_eeprom(hw,
1340 IXGBE_SFF_IDENTIFIER,
1343 if (status != IXGBE_SUCCESS)
1344 goto err_read_i2c_eeprom;
1346 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1347 hw->phy.type = ixgbe_phy_sfp_unsupported;
1348 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1350 status = hw->phy.ops.read_i2c_eeprom(hw,
1351 IXGBE_SFF_1GBE_COMP_CODES,
1354 if (status != IXGBE_SUCCESS)
1355 goto err_read_i2c_eeprom;
1357 status = hw->phy.ops.read_i2c_eeprom(hw,
1358 IXGBE_SFF_10GBE_COMP_CODES,
1361 if (status != IXGBE_SUCCESS)
1362 goto err_read_i2c_eeprom;
1363 status = hw->phy.ops.read_i2c_eeprom(hw,
1364 IXGBE_SFF_CABLE_TECHNOLOGY,
1367 if (status != IXGBE_SUCCESS)
1368 goto err_read_i2c_eeprom;
1375 * 3 SFP_DA_CORE0 - 82599-specific
1376 * 4 SFP_DA_CORE1 - 82599-specific
1377 * 5 SFP_SR/LR_CORE0 - 82599-specific
1378 * 6 SFP_SR/LR_CORE1 - 82599-specific
1379 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1380 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1381 * 9 SFP_1g_cu_CORE0 - 82599-specific
1382 * 10 SFP_1g_cu_CORE1 - 82599-specific
1383 * 11 SFP_1g_sx_CORE0 - 82599-specific
1384 * 12 SFP_1g_sx_CORE1 - 82599-specific
1386 if (hw->mac.type == ixgbe_mac_82598EB) {
1387 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1388 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1389 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1390 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1391 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1392 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1394 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1396 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1397 if (hw->bus.lan_id == 0)
1399 ixgbe_sfp_type_da_cu_core0;
1402 ixgbe_sfp_type_da_cu_core1;
1403 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1404 hw->phy.ops.read_i2c_eeprom(
1405 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1408 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1409 if (hw->bus.lan_id == 0)
1411 ixgbe_sfp_type_da_act_lmt_core0;
1414 ixgbe_sfp_type_da_act_lmt_core1;
1417 ixgbe_sfp_type_unknown;
1419 } else if (comp_codes_10g &
1420 (IXGBE_SFF_10GBASESR_CAPABLE |
1421 IXGBE_SFF_10GBASELR_CAPABLE)) {
1422 if (hw->bus.lan_id == 0)
1424 ixgbe_sfp_type_srlr_core0;
1427 ixgbe_sfp_type_srlr_core1;
1428 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1429 if (hw->bus.lan_id == 0)
1431 ixgbe_sfp_type_1g_cu_core0;
1434 ixgbe_sfp_type_1g_cu_core1;
1435 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1436 if (hw->bus.lan_id == 0)
1438 ixgbe_sfp_type_1g_sx_core0;
1441 ixgbe_sfp_type_1g_sx_core1;
1442 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1443 if (hw->bus.lan_id == 0)
1445 ixgbe_sfp_type_1g_lx_core0;
1448 ixgbe_sfp_type_1g_lx_core1;
1450 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1454 if (hw->phy.sfp_type != stored_sfp_type)
1455 hw->phy.sfp_setup_needed = true;
1457 /* Determine if the SFP+ PHY is dual speed or not. */
1458 hw->phy.multispeed_fiber = false;
1459 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1460 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1461 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1462 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1463 hw->phy.multispeed_fiber = true;
1465 /* Determine PHY vendor */
1466 if (hw->phy.type != ixgbe_phy_nl) {
1467 hw->phy.id = identifier;
1468 status = hw->phy.ops.read_i2c_eeprom(hw,
1469 IXGBE_SFF_VENDOR_OUI_BYTE0,
1472 if (status != IXGBE_SUCCESS)
1473 goto err_read_i2c_eeprom;
1475 status = hw->phy.ops.read_i2c_eeprom(hw,
1476 IXGBE_SFF_VENDOR_OUI_BYTE1,
1479 if (status != IXGBE_SUCCESS)
1480 goto err_read_i2c_eeprom;
1482 status = hw->phy.ops.read_i2c_eeprom(hw,
1483 IXGBE_SFF_VENDOR_OUI_BYTE2,
1486 if (status != IXGBE_SUCCESS)
1487 goto err_read_i2c_eeprom;
1490 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1491 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1492 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1494 switch (vendor_oui) {
1495 case IXGBE_SFF_VENDOR_OUI_TYCO:
1496 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1498 ixgbe_phy_sfp_passive_tyco;
1500 case IXGBE_SFF_VENDOR_OUI_FTL:
1501 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1502 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1504 hw->phy.type = ixgbe_phy_sfp_ftl;
1506 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1507 hw->phy.type = ixgbe_phy_sfp_avago;
1509 case IXGBE_SFF_VENDOR_OUI_INTEL:
1510 hw->phy.type = ixgbe_phy_sfp_intel;
1513 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1515 ixgbe_phy_sfp_passive_unknown;
1516 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1518 ixgbe_phy_sfp_active_unknown;
1520 hw->phy.type = ixgbe_phy_sfp_unknown;
1525 /* Allow any DA cable vendor */
1526 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1527 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1528 status = IXGBE_SUCCESS;
1532 /* Verify supported 1G SFP modules */
1533 if (comp_codes_10g == 0 &&
1534 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1535 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1536 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1537 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1538 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1539 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1540 hw->phy.type = ixgbe_phy_sfp_unsupported;
1541 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1545 /* Anything else 82598-based is supported */
1546 if (hw->mac.type == ixgbe_mac_82598EB) {
1547 status = IXGBE_SUCCESS;
1551 ixgbe_get_device_caps(hw, &enforce_sfp);
1552 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1553 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1554 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1555 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1556 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1557 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1558 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1559 /* Make sure we're a supported PHY type */
1560 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1561 status = IXGBE_SUCCESS;
1563 if (hw->allow_unsupported_sfp == true) {
1564 EWARN(hw, "WARNING: Intel (R) Network "
1565 "Connections are quality tested "
1566 "using Intel (R) Ethernet Optics."
1567 " Using untested modules is not "
1568 "supported and may cause unstable"
1569 " operation or damage to the "
1570 "module or the adapter. Intel "
1571 "Corporation is not responsible "
1572 "for any harm caused by using "
1573 "untested modules.\n", status);
1574 status = IXGBE_SUCCESS;
1576 DEBUGOUT("SFP+ module not supported\n");
1578 ixgbe_phy_sfp_unsupported;
1579 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1583 status = IXGBE_SUCCESS;
1590 err_read_i2c_eeprom:
1591 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1592 if (hw->phy.type != ixgbe_phy_nl) {
1594 hw->phy.type = ixgbe_phy_unknown;
1596 return IXGBE_ERR_SFP_NOT_PRESENT;
1600 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1601 * @hw: pointer to hardware structure
1603 * Determines physical layer capabilities of the current SFP.
1605 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1607 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1608 u8 comp_codes_10g = 0;
1609 u8 comp_codes_1g = 0;
1611 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1613 hw->phy.ops.identify_sfp(hw);
1614 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1615 return physical_layer;
1617 switch (hw->phy.type) {
1618 case ixgbe_phy_sfp_passive_tyco:
1619 case ixgbe_phy_sfp_passive_unknown:
1620 case ixgbe_phy_qsfp_passive_unknown:
1621 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1623 case ixgbe_phy_sfp_ftl_active:
1624 case ixgbe_phy_sfp_active_unknown:
1625 case ixgbe_phy_qsfp_active_unknown:
1626 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1628 case ixgbe_phy_sfp_avago:
1629 case ixgbe_phy_sfp_ftl:
1630 case ixgbe_phy_sfp_intel:
1631 case ixgbe_phy_sfp_unknown:
1632 hw->phy.ops.read_i2c_eeprom(hw,
1633 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1634 hw->phy.ops.read_i2c_eeprom(hw,
1635 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1636 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1637 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1638 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1639 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1640 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1641 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1642 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1643 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1645 case ixgbe_phy_qsfp_intel:
1646 case ixgbe_phy_qsfp_unknown:
1647 hw->phy.ops.read_i2c_eeprom(hw,
1648 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1649 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1650 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1651 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1652 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1658 return physical_layer;
1662 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1663 * @hw: pointer to hardware structure
1665 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1667 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1669 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1671 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1673 u8 comp_codes_1g = 0;
1674 u8 comp_codes_10g = 0;
1675 u8 oui_bytes[3] = {0, 0, 0};
1676 u16 enforce_sfp = 0;
1678 u8 cable_length = 0;
1680 bool active_cable = false;
1682 DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1684 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1685 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1686 status = IXGBE_ERR_SFP_NOT_PRESENT;
1690 /* LAN ID is needed for I2C access */
1691 hw->mac.ops.set_lan_id(hw);
1693 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1696 if (status != IXGBE_SUCCESS)
1697 goto err_read_i2c_eeprom;
1699 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1700 hw->phy.type = ixgbe_phy_sfp_unsupported;
1701 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1705 hw->phy.id = identifier;
1707 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1710 if (status != IXGBE_SUCCESS)
1711 goto err_read_i2c_eeprom;
1713 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1716 if (status != IXGBE_SUCCESS)
1717 goto err_read_i2c_eeprom;
1719 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1720 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1721 if (hw->bus.lan_id == 0)
1722 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1724 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1725 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1726 IXGBE_SFF_10GBASELR_CAPABLE)) {
1727 if (hw->bus.lan_id == 0)
1728 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1730 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1732 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1733 active_cable = true;
1735 if (!active_cable) {
1736 /* check for active DA cables that pre-date
1738 hw->phy.ops.read_i2c_eeprom(hw,
1739 IXGBE_SFF_QSFP_CONNECTOR,
1742 hw->phy.ops.read_i2c_eeprom(hw,
1743 IXGBE_SFF_QSFP_CABLE_LENGTH,
1746 hw->phy.ops.read_i2c_eeprom(hw,
1747 IXGBE_SFF_QSFP_DEVICE_TECH,
1751 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1752 (cable_length > 0) &&
1753 ((device_tech >> 4) ==
1754 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1755 active_cable = true;
1759 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1760 if (hw->bus.lan_id == 0)
1762 ixgbe_sfp_type_da_act_lmt_core0;
1765 ixgbe_sfp_type_da_act_lmt_core1;
1767 /* unsupported module type */
1768 hw->phy.type = ixgbe_phy_sfp_unsupported;
1769 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1774 if (hw->phy.sfp_type != stored_sfp_type)
1775 hw->phy.sfp_setup_needed = true;
1777 /* Determine if the QSFP+ PHY is dual speed or not. */
1778 hw->phy.multispeed_fiber = false;
1779 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1780 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1781 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1782 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1783 hw->phy.multispeed_fiber = true;
1785 /* Determine PHY vendor for optical modules */
1786 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1787 IXGBE_SFF_10GBASELR_CAPABLE)) {
1788 status = hw->phy.ops.read_i2c_eeprom(hw,
1789 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1792 if (status != IXGBE_SUCCESS)
1793 goto err_read_i2c_eeprom;
1795 status = hw->phy.ops.read_i2c_eeprom(hw,
1796 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1799 if (status != IXGBE_SUCCESS)
1800 goto err_read_i2c_eeprom;
1802 status = hw->phy.ops.read_i2c_eeprom(hw,
1803 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1806 if (status != IXGBE_SUCCESS)
1807 goto err_read_i2c_eeprom;
1810 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1811 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1812 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1814 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1815 hw->phy.type = ixgbe_phy_qsfp_intel;
1817 hw->phy.type = ixgbe_phy_qsfp_unknown;
1819 ixgbe_get_device_caps(hw, &enforce_sfp);
1820 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1821 /* Make sure we're a supported PHY type */
1822 if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1823 status = IXGBE_SUCCESS;
1825 if (hw->allow_unsupported_sfp == true) {
1826 EWARN(hw, "WARNING: Intel (R) Network "
1827 "Connections are quality tested "
1828 "using Intel (R) Ethernet Optics."
1829 " Using untested modules is not "
1830 "supported and may cause unstable"
1831 " operation or damage to the "
1832 "module or the adapter. Intel "
1833 "Corporation is not responsible "
1834 "for any harm caused by using "
1835 "untested modules.\n", status);
1836 status = IXGBE_SUCCESS;
1838 DEBUGOUT("QSFP module not supported\n");
1840 ixgbe_phy_sfp_unsupported;
1841 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1845 status = IXGBE_SUCCESS;
1852 err_read_i2c_eeprom:
1853 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1855 hw->phy.type = ixgbe_phy_unknown;
1857 return IXGBE_ERR_SFP_NOT_PRESENT;
1862 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1863 * @hw: pointer to hardware structure
1864 * @list_offset: offset to the SFP ID list
1865 * @data_offset: offset to the SFP data block
1867 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1868 * so it returns the offsets to the phy init sequence block.
1870 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1875 u16 sfp_type = hw->phy.sfp_type;
1877 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1879 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1880 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1882 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1883 return IXGBE_ERR_SFP_NOT_PRESENT;
1885 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1886 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1887 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1890 * Limiting active cables and 1G Phys must be initialized as
1893 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1894 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1895 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1896 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1897 sfp_type = ixgbe_sfp_type_srlr_core0;
1898 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1899 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1900 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1901 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1902 sfp_type = ixgbe_sfp_type_srlr_core1;
1904 /* Read offset to PHY init contents */
1905 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1906 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1907 "eeprom read at offset %d failed",
1908 IXGBE_PHY_INIT_OFFSET_NL);
1909 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1912 if ((!*list_offset) || (*list_offset == 0xFFFF))
1913 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1915 /* Shift offset to first ID word */
1919 * Find the matching SFP ID in the EEPROM
1920 * and program the init sequence
1922 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1925 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1926 if (sfp_id == sfp_type) {
1928 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1930 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1931 DEBUGOUT("SFP+ module not supported\n");
1932 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1937 (*list_offset) += 2;
1938 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1943 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1944 DEBUGOUT("No matching SFP+ module found\n");
1945 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1948 return IXGBE_SUCCESS;
1951 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1952 "eeprom read at offset %d failed", *list_offset);
1953 return IXGBE_ERR_PHY;
1957 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1958 * @hw: pointer to hardware structure
1959 * @byte_offset: EEPROM byte offset to read
1960 * @eeprom_data: value read
1962 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1964 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1967 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1969 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1970 IXGBE_I2C_EEPROM_DEV_ADDR,
1975 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1976 * @hw: pointer to hardware structure
1977 * @byte_offset: byte offset at address 0xA2
1978 * @eeprom_data: value read
1980 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1982 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1985 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1986 IXGBE_I2C_EEPROM_DEV_ADDR2,
1991 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1992 * @hw: pointer to hardware structure
1993 * @byte_offset: EEPROM byte offset to write
1994 * @eeprom_data: value to write
1996 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1998 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
2001 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
2003 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
2004 IXGBE_I2C_EEPROM_DEV_ADDR,
2009 * ixgbe_is_sfp_probe - Returns true if SFP is being detected
2010 * @hw: pointer to hardware structure
2011 * @offset: eeprom offset to be read
2012 * @addr: I2C address to be read
2014 STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
2016 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
2017 offset == IXGBE_SFF_IDENTIFIER &&
2018 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2024 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
2025 * @hw: pointer to hardware structure
2026 * @byte_offset: byte offset to read
2028 * @lock: true if to take and release semaphore
2030 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2031 * a specified device address.
2033 STATIC s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2034 u8 dev_addr, u8 *data, bool lock)
2039 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2043 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2045 if (hw->mac.type >= ixgbe_mac_X550)
2047 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2048 max_retry = IXGBE_SFP_DETECT_RETRIES;
2051 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2052 return IXGBE_ERR_SWFW_SYNC;
2054 ixgbe_i2c_start(hw);
2056 /* Device Address and write indication */
2057 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2058 if (status != IXGBE_SUCCESS)
2061 status = ixgbe_get_i2c_ack(hw);
2062 if (status != IXGBE_SUCCESS)
2065 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2066 if (status != IXGBE_SUCCESS)
2069 status = ixgbe_get_i2c_ack(hw);
2070 if (status != IXGBE_SUCCESS)
2073 ixgbe_i2c_start(hw);
2075 /* Device Address and read indication */
2076 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2077 if (status != IXGBE_SUCCESS)
2080 status = ixgbe_get_i2c_ack(hw);
2081 if (status != IXGBE_SUCCESS)
2084 status = ixgbe_clock_in_i2c_byte(hw, data);
2085 if (status != IXGBE_SUCCESS)
2088 status = ixgbe_clock_out_i2c_bit(hw, nack);
2089 if (status != IXGBE_SUCCESS)
2094 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2095 return IXGBE_SUCCESS;
2098 ixgbe_i2c_bus_clear(hw);
2100 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2104 if (retry < max_retry)
2105 DEBUGOUT("I2C byte read error - Retrying.\n");
2107 DEBUGOUT("I2C byte read error.\n");
2109 } while (retry < max_retry);
2115 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2116 * @hw: pointer to hardware structure
2117 * @byte_offset: byte offset to read
2120 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2121 * a specified device address.
2123 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2124 u8 dev_addr, u8 *data)
2126 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2131 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2132 * @hw: pointer to hardware structure
2133 * @byte_offset: byte offset to read
2136 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2137 * a specified device address.
2139 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2140 u8 dev_addr, u8 *data)
2142 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2147 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2148 * @hw: pointer to hardware structure
2149 * @byte_offset: byte offset to write
2150 * @data: value to write
2151 * @lock: true if to take and release semaphore
2153 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2154 * a specified device address.
2156 STATIC s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2157 u8 dev_addr, u8 data, bool lock)
2162 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2164 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2166 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2168 return IXGBE_ERR_SWFW_SYNC;
2171 ixgbe_i2c_start(hw);
2173 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2174 if (status != IXGBE_SUCCESS)
2177 status = ixgbe_get_i2c_ack(hw);
2178 if (status != IXGBE_SUCCESS)
2181 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2182 if (status != IXGBE_SUCCESS)
2185 status = ixgbe_get_i2c_ack(hw);
2186 if (status != IXGBE_SUCCESS)
2189 status = ixgbe_clock_out_i2c_byte(hw, data);
2190 if (status != IXGBE_SUCCESS)
2193 status = ixgbe_get_i2c_ack(hw);
2194 if (status != IXGBE_SUCCESS)
2199 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2200 return IXGBE_SUCCESS;
2203 ixgbe_i2c_bus_clear(hw);
2205 if (retry < max_retry)
2206 DEBUGOUT("I2C byte write error - Retrying.\n");
2208 DEBUGOUT("I2C byte write error.\n");
2209 } while (retry < max_retry);
2212 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2218 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2219 * @hw: pointer to hardware structure
2220 * @byte_offset: byte offset to write
2221 * @data: value to write
2223 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2224 * a specified device address.
2226 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2227 u8 dev_addr, u8 data)
2229 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2234 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2235 * @hw: pointer to hardware structure
2236 * @byte_offset: byte offset to write
2237 * @data: value to write
2239 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2240 * a specified device address.
2242 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2243 u8 dev_addr, u8 data)
2245 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2250 * ixgbe_i2c_start - Sets I2C start condition
2251 * @hw: pointer to hardware structure
2253 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2254 * Set bit-bang mode on X550 hardware.
2256 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2258 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2260 DEBUGFUNC("ixgbe_i2c_start");
2262 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2264 /* Start condition must begin with data and clock high */
2265 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2266 ixgbe_raise_i2c_clk(hw, &i2cctl);
2268 /* Setup time for start condition (4.7us) */
2269 usec_delay(IXGBE_I2C_T_SU_STA);
2271 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2273 /* Hold time for start condition (4us) */
2274 usec_delay(IXGBE_I2C_T_HD_STA);
2276 ixgbe_lower_i2c_clk(hw, &i2cctl);
2278 /* Minimum low period of clock is 4.7 us */
2279 usec_delay(IXGBE_I2C_T_LOW);
2284 * ixgbe_i2c_stop - Sets I2C stop condition
2285 * @hw: pointer to hardware structure
2287 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2288 * Disables bit-bang mode and negates data output enable on X550
2291 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2293 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2294 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2295 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2296 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2298 DEBUGFUNC("ixgbe_i2c_stop");
2300 /* Stop condition must begin with data low and clock high */
2301 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2302 ixgbe_raise_i2c_clk(hw, &i2cctl);
2304 /* Setup time for stop condition (4us) */
2305 usec_delay(IXGBE_I2C_T_SU_STO);
2307 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2309 /* bus free time between stop and start (4.7us)*/
2310 usec_delay(IXGBE_I2C_T_BUF);
2312 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2313 i2cctl &= ~bb_en_bit;
2314 i2cctl |= data_oe_bit | clk_oe_bit;
2315 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2316 IXGBE_WRITE_FLUSH(hw);
2321 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2322 * @hw: pointer to hardware structure
2323 * @data: data byte to clock in
2325 * Clocks in one byte data via I2C data/clock
2327 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2332 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2335 for (i = 7; i >= 0; i--) {
2336 ixgbe_clock_in_i2c_bit(hw, &bit);
2340 return IXGBE_SUCCESS;
2344 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2345 * @hw: pointer to hardware structure
2346 * @data: data byte clocked out
2348 * Clocks out one byte data via I2C data/clock
2350 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2352 s32 status = IXGBE_SUCCESS;
2357 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2359 for (i = 7; i >= 0; i--) {
2360 bit = (data >> i) & 0x1;
2361 status = ixgbe_clock_out_i2c_bit(hw, bit);
2363 if (status != IXGBE_SUCCESS)
2367 /* Release SDA line (set high) */
2368 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2369 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2370 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2371 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2372 IXGBE_WRITE_FLUSH(hw);
2378 * ixgbe_get_i2c_ack - Polls for I2C ACK
2379 * @hw: pointer to hardware structure
2381 * Clocks in/out one bit via I2C data/clock
2383 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2385 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2386 s32 status = IXGBE_SUCCESS;
2388 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2392 DEBUGFUNC("ixgbe_get_i2c_ack");
2395 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2396 i2cctl |= data_oe_bit;
2397 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2398 IXGBE_WRITE_FLUSH(hw);
2400 ixgbe_raise_i2c_clk(hw, &i2cctl);
2402 /* Minimum high period of clock is 4us */
2403 usec_delay(IXGBE_I2C_T_HIGH);
2405 /* Poll for ACK. Note that ACK in I2C spec is
2406 * transition from 1 to 0 */
2407 for (i = 0; i < timeout; i++) {
2408 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2409 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2417 DEBUGOUT("I2C ack was not received.\n");
2418 status = IXGBE_ERR_I2C;
2421 ixgbe_lower_i2c_clk(hw, &i2cctl);
2423 /* Minimum low period of clock is 4.7 us */
2424 usec_delay(IXGBE_I2C_T_LOW);
2430 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2431 * @hw: pointer to hardware structure
2432 * @data: read data value
2434 * Clocks in one bit via I2C data/clock
2436 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2438 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2439 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2441 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2444 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2445 i2cctl |= data_oe_bit;
2446 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2447 IXGBE_WRITE_FLUSH(hw);
2449 ixgbe_raise_i2c_clk(hw, &i2cctl);
2451 /* Minimum high period of clock is 4us */
2452 usec_delay(IXGBE_I2C_T_HIGH);
2454 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2455 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2457 ixgbe_lower_i2c_clk(hw, &i2cctl);
2459 /* Minimum low period of clock is 4.7 us */
2460 usec_delay(IXGBE_I2C_T_LOW);
2462 return IXGBE_SUCCESS;
2466 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2467 * @hw: pointer to hardware structure
2468 * @data: data value to write
2470 * Clocks out one bit via I2C data/clock
2472 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2475 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2477 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2479 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2480 if (status == IXGBE_SUCCESS) {
2481 ixgbe_raise_i2c_clk(hw, &i2cctl);
2483 /* Minimum high period of clock is 4us */
2484 usec_delay(IXGBE_I2C_T_HIGH);
2486 ixgbe_lower_i2c_clk(hw, &i2cctl);
2488 /* Minimum low period of clock is 4.7 us.
2489 * This also takes care of the data hold time.
2491 usec_delay(IXGBE_I2C_T_LOW);
2493 status = IXGBE_ERR_I2C;
2494 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2495 "I2C data was not set to %X\n", data);
2502 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2503 * @hw: pointer to hardware structure
2504 * @i2cctl: Current value of I2CCTL register
2506 * Raises the I2C clock line '0'->'1'
2507 * Negates the I2C clock output enable on X550 hardware.
2509 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2511 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2513 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2516 DEBUGFUNC("ixgbe_raise_i2c_clk");
2519 *i2cctl |= clk_oe_bit;
2520 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2523 for (i = 0; i < timeout; i++) {
2524 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2526 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2527 IXGBE_WRITE_FLUSH(hw);
2528 /* SCL rise time (1000ns) */
2529 usec_delay(IXGBE_I2C_T_RISE);
2531 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2532 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2538 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2539 * @hw: pointer to hardware structure
2540 * @i2cctl: Current value of I2CCTL register
2542 * Lowers the I2C clock line '1'->'0'
2543 * Asserts the I2C clock output enable on X550 hardware.
2545 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2547 DEBUGFUNC("ixgbe_lower_i2c_clk");
2549 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2550 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2552 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2553 IXGBE_WRITE_FLUSH(hw);
2555 /* SCL fall time (300ns) */
2556 usec_delay(IXGBE_I2C_T_FALL);
2560 * ixgbe_set_i2c_data - Sets the I2C data bit
2561 * @hw: pointer to hardware structure
2562 * @i2cctl: Current value of I2CCTL register
2563 * @data: I2C data value (0 or 1) to set
2565 * Sets the I2C data bit
2566 * Asserts the I2C data output enable on X550 hardware.
2568 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2570 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2571 s32 status = IXGBE_SUCCESS;
2573 DEBUGFUNC("ixgbe_set_i2c_data");
2576 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2578 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2579 *i2cctl &= ~data_oe_bit;
2581 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2582 IXGBE_WRITE_FLUSH(hw);
2584 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2585 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2587 if (!data) /* Can't verify data in this case */
2588 return IXGBE_SUCCESS;
2590 *i2cctl |= data_oe_bit;
2591 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2592 IXGBE_WRITE_FLUSH(hw);
2595 /* Verify data was set correctly */
2596 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2597 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2598 status = IXGBE_ERR_I2C;
2599 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2600 "Error - I2C data was not set to %X.\n",
2608 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2609 * @hw: pointer to hardware structure
2610 * @i2cctl: Current value of I2CCTL register
2612 * Returns the I2C data bit value
2613 * Negates the I2C data output enable on X550 hardware.
2615 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2617 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2620 DEBUGFUNC("ixgbe_get_i2c_data");
2623 *i2cctl |= data_oe_bit;
2624 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2625 IXGBE_WRITE_FLUSH(hw);
2626 usec_delay(IXGBE_I2C_T_FALL);
2629 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2638 * ixgbe_i2c_bus_clear - Clears the I2C bus
2639 * @hw: pointer to hardware structure
2641 * Clears the I2C bus by sending nine clock pulses.
2642 * Used when data line is stuck low.
2644 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2649 DEBUGFUNC("ixgbe_i2c_bus_clear");
2651 ixgbe_i2c_start(hw);
2652 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2654 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2656 for (i = 0; i < 9; i++) {
2657 ixgbe_raise_i2c_clk(hw, &i2cctl);
2659 /* Min high period of clock is 4us */
2660 usec_delay(IXGBE_I2C_T_HIGH);
2662 ixgbe_lower_i2c_clk(hw, &i2cctl);
2664 /* Min low period of clock is 4.7us*/
2665 usec_delay(IXGBE_I2C_T_LOW);
2668 ixgbe_i2c_start(hw);
2670 /* Put the i2c bus back to default state */
2675 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2676 * @hw: pointer to hardware structure
2678 * Checks if the LASI temp alarm status was triggered due to overtemp
2680 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2682 s32 status = IXGBE_SUCCESS;
2685 DEBUGFUNC("ixgbe_tn_check_overtemp");
2687 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2690 /* Check that the LASI temp alarm status was triggered */
2691 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2692 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2694 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2697 status = IXGBE_ERR_OVERTEMP;
2698 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2704 * ixgbe_set_copper_phy_power - Control power for copper phy
2705 * @hw: pointer to hardware structure
2706 * @on: true for on, false for off
2708 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2713 if (!on && ixgbe_mng_present(hw))
2716 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2717 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2723 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2725 if (ixgbe_check_reset_blocked(hw))
2727 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2730 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2731 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,