net/sfc/base: fix a typo in unicast filter insertion comment
[dpdk.git] / drivers / net / ixgbe / base / ixgbe_phy.h
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2001-2018
3  */
4
5 #ifndef _IXGBE_PHY_H_
6 #define _IXGBE_PHY_H_
7
8 #include "ixgbe_type.h"
9 #define IXGBE_I2C_EEPROM_DEV_ADDR       0xA0
10 #define IXGBE_I2C_EEPROM_DEV_ADDR2      0xA2
11 #define IXGBE_I2C_EEPROM_BANK_LEN       0xFF
12
13 /* EEPROM byte offsets */
14 #define IXGBE_SFF_IDENTIFIER            0x0
15 #define IXGBE_SFF_IDENTIFIER_SFP        0x3
16 #define IXGBE_SFF_VENDOR_OUI_BYTE0      0x25
17 #define IXGBE_SFF_VENDOR_OUI_BYTE1      0x26
18 #define IXGBE_SFF_VENDOR_OUI_BYTE2      0x27
19 #define IXGBE_SFF_1GBE_COMP_CODES       0x6
20 #define IXGBE_SFF_10GBE_COMP_CODES      0x3
21 #define IXGBE_SFF_CABLE_TECHNOLOGY      0x8
22 #define IXGBE_SFF_CABLE_SPEC_COMP       0x3C
23 #define IXGBE_SFF_SFF_8472_SWAP         0x5C
24 #define IXGBE_SFF_SFF_8472_COMP         0x5E
25 #define IXGBE_SFF_SFF_8472_OSCB         0x6E
26 #define IXGBE_SFF_SFF_8472_ESCB         0x76
27 #define IXGBE_SFF_IDENTIFIER_QSFP_PLUS  0xD
28 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0 0xA5
29 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1 0xA6
30 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2 0xA7
31 #define IXGBE_SFF_QSFP_CONNECTOR        0x82
32 #define IXGBE_SFF_QSFP_10GBE_COMP       0x83
33 #define IXGBE_SFF_QSFP_1GBE_COMP        0x86
34 #define IXGBE_SFF_QSFP_CABLE_LENGTH     0x92
35 #define IXGBE_SFF_QSFP_DEVICE_TECH      0x93
36
37 /* Bitmasks */
38 #define IXGBE_SFF_DA_PASSIVE_CABLE      0x4
39 #define IXGBE_SFF_DA_ACTIVE_CABLE       0x8
40 #define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING       0x4
41 #define IXGBE_SFF_1GBASESX_CAPABLE      0x1
42 #define IXGBE_SFF_1GBASELX_CAPABLE      0x2
43 #define IXGBE_SFF_1GBASET_CAPABLE       0x8
44 #define IXGBE_SFF_10GBASESR_CAPABLE     0x10
45 #define IXGBE_SFF_10GBASELR_CAPABLE     0x20
46 #define IXGBE_SFF_SOFT_RS_SELECT_MASK   0x8
47 #define IXGBE_SFF_SOFT_RS_SELECT_10G    0x8
48 #define IXGBE_SFF_SOFT_RS_SELECT_1G     0x0
49 #define IXGBE_SFF_ADDRESSING_MODE       0x4
50 #define IXGBE_SFF_QSFP_DA_ACTIVE_CABLE  0x1
51 #define IXGBE_SFF_QSFP_DA_PASSIVE_CABLE 0x8
52 #define IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE  0x23
53 #define IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL   0x0
54 #define IXGBE_I2C_EEPROM_READ_MASK      0x100
55 #define IXGBE_I2C_EEPROM_STATUS_MASK    0x3
56 #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION    0x0
57 #define IXGBE_I2C_EEPROM_STATUS_PASS    0x1
58 #define IXGBE_I2C_EEPROM_STATUS_FAIL    0x2
59 #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS     0x3
60
61 #define IXGBE_CS4227                    0xBE    /* CS4227 address */
62 #define IXGBE_CS4227_GLOBAL_ID_LSB      0
63 #define IXGBE_CS4227_GLOBAL_ID_MSB      1
64 #define IXGBE_CS4227_SCRATCH            2
65 #define IXGBE_CS4227_GLOBAL_ID_VALUE    0x03E5
66 #define IXGBE_CS4227_EFUSE_PDF_SKU      0x19F
67 #define IXGBE_CS4223_SKU_ID             0x0010  /* Quad port */
68 #define IXGBE_CS4227_SKU_ID             0x0014  /* Dual port */
69 #define IXGBE_CS4227_RESET_PENDING      0x1357
70 #define IXGBE_CS4227_RESET_COMPLETE     0x5AA5
71 #define IXGBE_CS4227_RETRIES            15
72 #define IXGBE_CS4227_EFUSE_STATUS       0x0181
73 #define IXGBE_CS4227_LINE_SPARE22_MSB   0x12AD  /* Reg to program speed */
74 #define IXGBE_CS4227_LINE_SPARE24_LSB   0x12B0  /* Reg to program EDC */
75 #define IXGBE_CS4227_HOST_SPARE22_MSB   0x1AAD  /* Reg to program speed */
76 #define IXGBE_CS4227_HOST_SPARE24_LSB   0x1AB0  /* Reg to program EDC */
77 #define IXGBE_CS4227_EEPROM_STATUS      0x5001
78 #define IXGBE_CS4227_EEPROM_LOAD_OK     0x0001
79 #define IXGBE_CS4227_SPEED_1G           0x8000
80 #define IXGBE_CS4227_SPEED_10G          0
81 #define IXGBE_CS4227_EDC_MODE_CX1       0x0002
82 #define IXGBE_CS4227_EDC_MODE_SR        0x0004
83 #define IXGBE_CS4227_EDC_MODE_DIAG      0x0008
84 #define IXGBE_CS4227_RESET_HOLD         500     /* microseconds */
85 #define IXGBE_CS4227_RESET_DELAY        450     /* milliseconds */
86 #define IXGBE_CS4227_CHECK_DELAY        30      /* milliseconds */
87 #define IXGBE_PE                        0xE0    /* Port expander address */
88 #define IXGBE_PE_OUTPUT                 1       /* Output register offset */
89 #define IXGBE_PE_CONFIG                 3       /* Config register offset */
90 #define IXGBE_PE_BIT1                   (1 << 1)
91
92 /* Flow control defines */
93 #define IXGBE_TAF_SYM_PAUSE             0x400
94 #define IXGBE_TAF_ASM_PAUSE             0x800
95
96 /* Bit-shift macros */
97 #define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT        24
98 #define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT        16
99 #define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT        8
100
101 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
102 #define IXGBE_SFF_VENDOR_OUI_TYCO       0x00407600
103 #define IXGBE_SFF_VENDOR_OUI_FTL        0x00906500
104 #define IXGBE_SFF_VENDOR_OUI_AVAGO      0x00176A00
105 #define IXGBE_SFF_VENDOR_OUI_INTEL      0x001B2100
106
107 /* I2C SDA and SCL timing parameters for standard mode */
108 #define IXGBE_I2C_T_HD_STA      4
109 #define IXGBE_I2C_T_LOW         5
110 #define IXGBE_I2C_T_HIGH        4
111 #define IXGBE_I2C_T_SU_STA      5
112 #define IXGBE_I2C_T_HD_DATA     5
113 #define IXGBE_I2C_T_SU_DATA     1
114 #define IXGBE_I2C_T_RISE        1
115 #define IXGBE_I2C_T_FALL        1
116 #define IXGBE_I2C_T_SU_STO      4
117 #define IXGBE_I2C_T_BUF         5
118
119 #ifndef IXGBE_SFP_DETECT_RETRIES
120 #define IXGBE_SFP_DETECT_RETRIES        10
121
122 #endif /* IXGBE_SFP_DETECT_RETRIES */
123 #define IXGBE_TN_LASI_STATUS_REG        0x9005
124 #define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008
125
126 /* SFP+ SFF-8472 Compliance */
127 #define IXGBE_SFF_SFF_8472_UNSUP        0x00
128
129 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);
130 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
131 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
132 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
133 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
134 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
135 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
136                            u16 *phy_data);
137 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
138                             u16 phy_data);
139 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
140                                u32 device_type, u16 *phy_data);
141 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
142                                 u32 device_type, u16 phy_data);
143 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
144 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
145                                        ixgbe_link_speed speed,
146                                        bool autoneg_wait_to_complete);
147 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
148                                                ixgbe_link_speed *speed,
149                                                bool *autoneg);
150 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw);
151
152 /* PHY specific */
153 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
154                              ixgbe_link_speed *speed,
155                              bool *link_up);
156 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw);
157 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
158                                        u16 *firmware_version);
159 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
160                                            u16 *firmware_version);
161
162 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
163 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on);
164 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw);
165 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
166 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw);
167 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
168 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
169                                         u16 *list_offset,
170                                         u16 *data_offset);
171 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw);
172 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
173                                 u8 dev_addr, u8 *data);
174 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
175                                          u8 dev_addr, u8 *data);
176 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
177                                  u8 dev_addr, u8 data);
178 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
179                                           u8 dev_addr, u8 data);
180 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
181                                   u8 *eeprom_data);
182 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
183                                    u8 eeprom_data);
184 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
185 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg,
186                                         u16 *val, bool lock);
187 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg,
188                                          u16 val, bool lock);
189 #endif /* _IXGBE_PHY_H_ */