drivers/net/ixgbe/base/ixgbe_x540.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x540.h"
  35 #include "ixgbe_type.h"
  36 #include "ixgbe_api.h"
  37 #include "ixgbe_common.h"
  38 #include "ixgbe_phy.h"
  39
  40 #define IXGBE_X540_MAX_TX_QUEUES        128
  41 #define IXGBE_X540_MAX_RX_QUEUES        128
  42 #define IXGBE_X540_RAR_ENTRIES          128
  43 #define IXGBE_X540_MC_TBL_SIZE          128
  44 #define IXGBE_X540_VFT_TBL_SIZE         128
  45 #define IXGBE_X540_RX_PB_SIZE           384
  46
  47 STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
  48 STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
  49 STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
  50
  51 /**
  52  *  ixgbe_init_ops_X540 - Inits func ptrs and MAC type
  53  *  @hw: pointer to hardware structure
  54  *
  55  *  Initialize the function pointers and assign the MAC type for X540.
  56  *  Does not touch the hardware.
  57  **/
  58 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
  59 {
  60         struct ixgbe_mac_info *mac = &hw->mac;
  61         struct ixgbe_phy_info *phy = &hw->phy;
  62         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  63         s32 ret_val;
  64
  65         DEBUGFUNC("ixgbe_init_ops_X540");
  66
  67         ret_val = ixgbe_init_phy_ops_generic(hw);
  68         ret_val = ixgbe_init_ops_generic(hw);
  69
  70
  71         /* EEPROM */
  72         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
  73         eeprom->ops.read = ixgbe_read_eerd_X540;
  74         eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_X540;
  75         eeprom->ops.write = ixgbe_write_eewr_X540;
  76         eeprom->ops.write_buffer = ixgbe_write_eewr_buffer_X540;
  77         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X540;
  78         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X540;
  79         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X540;
  80
  81         /* PHY */
  82         phy->ops.init = ixgbe_init_phy_ops_generic;
  83         phy->ops.reset = NULL;
  84         phy->ops.set_phy_power = ixgbe_set_copper_phy_power;
  85
  86         /* MAC */
  87         mac->ops.reset_hw = ixgbe_reset_hw_X540;
  88         mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2;
  89         mac->ops.get_media_type = ixgbe_get_media_type_X540;
  90         mac->ops.get_supported_physical_layer =
  91                                     ixgbe_get_supported_physical_layer_X540;
  92         mac->ops.read_analog_reg8 = NULL;
  93         mac->ops.write_analog_reg8 = NULL;
  94         mac->ops.start_hw = ixgbe_start_hw_X540;
  95         mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic;
  96         mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic;
  97         mac->ops.get_device_caps = ixgbe_get_device_caps_generic;
  98         mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic;
  99         mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic;
 100         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X540;
 101         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X540;
 102         mac->ops.init_swfw_sync = ixgbe_init_swfw_sync_X540;
 103         mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic;
 104         mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic;
 105
 106         /* RAR, Multicast, VLAN */
 107         mac->ops.set_vmdq = ixgbe_set_vmdq_generic;
 108         mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic;
 109         mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic;
 110         mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic;
 111         mac->rar_highwater = 1;
 112         mac->ops.set_vfta = ixgbe_set_vfta_generic;
 113         mac->ops.set_vlvf = ixgbe_set_vlvf_generic;
 114         mac->ops.clear_vfta = ixgbe_clear_vfta_generic;
 115         mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic;
 116         mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing;
 117         mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing;
 118
 119         /* Link */
 120         mac->ops.get_link_capabilities =
 121                                 ixgbe_get_copper_link_capabilities_generic;
 122         mac->ops.setup_link = ixgbe_setup_mac_link_X540;
 123         mac->ops.setup_rxpba = ixgbe_set_rxpba_generic;
 124         mac->ops.check_link = ixgbe_check_mac_link_generic;
 125
 126
 127         mac->mcft_size          = IXGBE_X540_MC_TBL_SIZE;
 128         mac->vft_size           = IXGBE_X540_VFT_TBL_SIZE;
 129         mac->num_rar_entries    = IXGBE_X540_RAR_ENTRIES;
 130         mac->rx_pb_size         = IXGBE_X540_RX_PB_SIZE;
 131         mac->max_rx_queues      = IXGBE_X540_MAX_RX_QUEUES;
 132         mac->max_tx_queues      = IXGBE_X540_MAX_TX_QUEUES;
 133         mac->max_msix_vectors   = ixgbe_get_pcie_msix_count_generic(hw);
 134
 135         /*
 136          * FWSM register
 137          * ARC supported; valid only if manageability features are
 138          * enabled.
 139          */
 140         mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw))
 141                                      & IXGBE_FWSM_MODE_MASK);
 142
 143         hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
 144
 145         /* LEDs */
 146         mac->ops.blink_led_start = ixgbe_blink_led_start_X540;
 147         mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;
 148
 149         /* Manageability interface */
 150         mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic;
 151
 152         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
 153
 154         return ret_val;
 155 }
 156
 157 /**
 158  *  ixgbe_get_link_capabilities_X540 - Determines link capabilities
 159  *  @hw: pointer to hardware structure
 160  *  @speed: pointer to link speed
 161  *  @autoneg: true when autoneg or autotry is enabled
 162  *
 163  *  Determines the link capabilities by reading the AUTOC register.
 164  **/
 165 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
 166                                      ixgbe_link_speed *speed,
 167                                      bool *autoneg)
 168 {
 169         ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
 170
 171         return IXGBE_SUCCESS;
 172 }
 173
 174 /**
 175  *  ixgbe_get_media_type_X540 - Get media type
 176  *  @hw: pointer to hardware structure
 177  *
 178  *  Returns the media type (fiber, copper, backplane)
 179  **/
 180 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
 181 {
 182         UNREFERENCED_1PARAMETER(hw);
 183         return ixgbe_media_type_copper;
 184 }
 185
 186 /**
 187  *  ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities
 188  *  @hw: pointer to hardware structure
 189  *  @speed: new link speed
 190  *  @autoneg_wait_to_complete: true when waiting for completion is needed
 191  **/
 192 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
 193                               ixgbe_link_speed speed,
 194                               bool autoneg_wait_to_complete)
 195 {
 196         DEBUGFUNC("ixgbe_setup_mac_link_X540");
 197         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
 198 }
 199
 200 /**
 201  *  ixgbe_reset_hw_X540 - Perform hardware reset
 202  *  @hw: pointer to hardware structure
 203  *
 204  *  Resets the hardware by resetting the transmit and receive units, masks
 205  *  and clears all interrupts, and perform a reset.
 206  **/
 207 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
 208 {
 209         s32 status;
 210         u32 ctrl, i;
 211         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 212
 213         DEBUGFUNC("ixgbe_reset_hw_X540");
 214
 215         /* Call adapter stop to disable tx/rx and clear interrupts */
 216         status = hw->mac.ops.stop_adapter(hw);
 217         if (status != IXGBE_SUCCESS)
 218                 goto reset_hw_out;
 219
 220         /* flush pending Tx transactions */
 221         ixgbe_clear_tx_pending(hw);
 222
 223 mac_reset_top:
 224         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 225         if (status != IXGBE_SUCCESS) {
 226                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 227                         "semaphore failed with %d", status);
 228                 return IXGBE_ERR_SWFW_SYNC;
 229         }
 230         ctrl = IXGBE_CTRL_RST;
 231         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
 232         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
 233         IXGBE_WRITE_FLUSH(hw);
 234         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 235
 236         /* Poll for reset bit to self-clear indicating reset is complete */
 237         for (i = 0; i < 10; i++) {
 238                 usec_delay(1);
 239                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 240                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
 241                         break;
 242         }
 243
 244         if (ctrl & IXGBE_CTRL_RST_MASK) {
 245                 status = IXGBE_ERR_RESET_FAILED;
 246                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 247                              "Reset polling failed to complete.\n");
 248         }
 249         msec_delay(100);
 250
 251         /*
 252          * Double resets are required for recovery from certain error
 253          * conditions.  Between resets, it is necessary to stall to allow time
 254          * for any pending HW events to complete.
 255          */
 256         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
 257                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
 258                 goto mac_reset_top;
 259         }
 260
 261         /* Set the Rx packet buffer size. */
 262         IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
 263
 264         /* Store the permanent mac address */
 265         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
 266
 267         /*
 268          * Store MAC address from RAR0, clear receive address registers, and
 269          * clear the multicast table.  Also reset num_rar_entries to 128,
 270          * since we modify this value when programming the SAN MAC address.
 271          */
 272         hw->mac.num_rar_entries = 128;
 273         hw->mac.ops.init_rx_addrs(hw);
 274
 275         /* Store the permanent SAN mac address */
 276         hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
 277
 278         /* Add the SAN MAC address to the RAR only if it's a valid address */
 279         if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
 280                 /* Save the SAN MAC RAR index */
 281                 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
 282
 283                 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index,
 284                                     hw->mac.san_addr, 0, IXGBE_RAH_AV);
 285
 286                 /* clear VMDq pool/queue selection for this RAR */
 287                 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index,
 288                                        IXGBE_CLEAR_VMDQ_ALL);
 289
 290                 /* Reserve the last RAR for the SAN MAC address */
 291                 hw->mac.num_rar_entries--;
 292         }
 293
 294         /* Store the alternative WWNN/WWPN prefix */
 295         hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
 296                                    &hw->mac.wwpn_prefix);
 297
 298 reset_hw_out:
 299         return status;
 300 }
 301
 302 /**
 303  *  ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
 304  *  @hw: pointer to hardware structure
 305  *
 306  *  Starts the hardware using the generic start_hw function
 307  *  and the generation start_hw function.
 308  *  Then performs revision-specific operations, if any.
 309  **/
 310 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
 311 {
 312         s32 ret_val = IXGBE_SUCCESS;
 313
 314         DEBUGFUNC("ixgbe_start_hw_X540");
 315
 316         ret_val = ixgbe_start_hw_generic(hw);
 317         if (ret_val != IXGBE_SUCCESS)
 318                 goto out;
 319
 320         ret_val = ixgbe_start_hw_gen2(hw);
 321
 322 out:
 323         return ret_val;
 324 }
 325
 326 /**
 327  *  ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
 328  *  @hw: pointer to hardware structure
 329  *
 330  *  Determines physical layer capabilities of the current configuration.
 331  **/
 332 u64 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
 333 {
 334         u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
 335         u16 ext_ability = 0;
 336
 337         DEBUGFUNC("ixgbe_get_supported_physical_layer_X540");
 338
 339         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
 340         IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
 341         if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
 342                 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
 343         if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
 344                 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
 345         if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
 346                 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
 347
 348         return physical_layer;
 349 }
 350
 351 /**
 352  *  ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
 353  *  @hw: pointer to hardware structure
 354  *
 355  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 356  *  ixgbe_hw struct in order to set up EEPROM access.
 357  **/
 358 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
 359 {
 360         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 361         u32 eec;
 362         u16 eeprom_size;
 363
 364         DEBUGFUNC("ixgbe_init_eeprom_params_X540");
 365
 366         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 367                 eeprom->semaphore_delay = 10;
 368                 eeprom->type = ixgbe_flash;
 369
 370                 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
 371                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 372                                     IXGBE_EEC_SIZE_SHIFT);
 373                 eeprom->word_size = 1 << (eeprom_size +
 374                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 375
 376                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 377                           eeprom->type, eeprom->word_size);
 378         }
 379
 380         return IXGBE_SUCCESS;
 381 }
 382
 383 /**
 384  *  ixgbe_read_eerd_X540- Read EEPROM word using EERD
 385  *  @hw: pointer to hardware structure
 386  *  @offset: offset of  word in the EEPROM to read
 387  *  @data: word read from the EEPROM
 388  *
 389  *  Reads a 16 bit word from the EEPROM using the EERD register.
 390  **/
 391 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
 392 {
 393         s32 status = IXGBE_SUCCESS;
 394
 395         DEBUGFUNC("ixgbe_read_eerd_X540");
 396         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 397             IXGBE_SUCCESS) {
 398                 status = ixgbe_read_eerd_generic(hw, offset, data);
 399                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 400         } else {
 401                 status = IXGBE_ERR_SWFW_SYNC;
 402         }
 403
 404         return status;
 405 }
 406
 407 /**
 408  *  ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD
 409  *  @hw: pointer to hardware structure
 410  *  @offset: offset of  word in the EEPROM to read
 411  *  @words: number of words
 412  *  @data: word(s) read from the EEPROM
 413  *
 414  *  Reads a 16 bit word(s) from the EEPROM using the EERD register.
 415  **/
 416 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
 417                                 u16 offset, u16 words, u16 *data)
 418 {
 419         s32 status = IXGBE_SUCCESS;
 420
 421         DEBUGFUNC("ixgbe_read_eerd_buffer_X540");
 422         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 423             IXGBE_SUCCESS) {
 424                 status = ixgbe_read_eerd_buffer_generic(hw, offset,
 425                                                         words, data);
 426                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 427         } else {
 428                 status = IXGBE_ERR_SWFW_SYNC;
 429         }
 430
 431         return status;
 432 }
 433
 434 /**
 435  *  ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
 436  *  @hw: pointer to hardware structure
 437  *  @offset: offset of  word in the EEPROM to write
 438  *  @data: word write to the EEPROM
 439  *
 440  *  Write a 16 bit word to the EEPROM using the EEWR register.
 441  **/
 442 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
 443 {
 444         s32 status = IXGBE_SUCCESS;
 445
 446         DEBUGFUNC("ixgbe_write_eewr_X540");
 447         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 448             IXGBE_SUCCESS) {
 449                 status = ixgbe_write_eewr_generic(hw, offset, data);
 450                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 451         } else {
 452                 status = IXGBE_ERR_SWFW_SYNC;
 453         }
 454
 455         return status;
 456 }
 457
 458 /**
 459  *  ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
 460  *  @hw: pointer to hardware structure
 461  *  @offset: offset of  word in the EEPROM to write
 462  *  @words: number of words
 463  *  @data: word(s) write to the EEPROM
 464  *
 465  *  Write a 16 bit word(s) to the EEPROM using the EEWR register.
 466  **/
 467 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
 468                                  u16 offset, u16 words, u16 *data)
 469 {
 470         s32 status = IXGBE_SUCCESS;
 471
 472         DEBUGFUNC("ixgbe_write_eewr_buffer_X540");
 473         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 474             IXGBE_SUCCESS) {
 475                 status = ixgbe_write_eewr_buffer_generic(hw, offset,
 476                                                          words, data);
 477                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 478         } else {
 479                 status = IXGBE_ERR_SWFW_SYNC;
 480         }
 481
 482         return status;
 483 }
 484
 485 /**
 486  *  ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
 487  *
 488  *  This function does not use synchronization for EERD and EEWR. It can
 489  *  be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
 490  *
 491  *  @hw: pointer to hardware structure
 492  *
 493  *  Returns a negative error code on error, or the 16-bit checksum
 494  **/
 495 s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
 496 {
 497         u16 i, j;
 498         u16 checksum = 0;
 499         u16 length = 0;
 500         u16 pointer = 0;
 501         u16 word = 0;
 502         u16 ptr_start = IXGBE_PCIE_ANALOG_PTR;
 503
 504         /* Do not use hw->eeprom.ops.read because we do not want to take
 505          * the synchronization semaphores here. Instead use
 506          * ixgbe_read_eerd_generic
 507          */
 508
 509         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540");
 510
 511         /* Include 0x0 up to IXGBE_EEPROM_CHECKSUM; do not include the
 512          * checksum itself
 513          */
 514         for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
 515                 if (ixgbe_read_eerd_generic(hw, i, &word)) {
 516                         DEBUGOUT("EEPROM read failed\n");
 517                         return IXGBE_ERR_EEPROM;
 518                 }
 519                 checksum += word;
 520         }
 521
 522         /* Include all data from pointers 0x3, 0x6-0xE.  This excludes the
 523          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
 524          */
 525         for (i = ptr_start; i < IXGBE_FW_PTR; i++) {
 526                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
 527                         continue;
 528
 529                 if (ixgbe_read_eerd_generic(hw, i, &pointer)) {
 530                         DEBUGOUT("EEPROM read failed\n");
 531                         return IXGBE_ERR_EEPROM;
 532                 }
 533
 534                 /* Skip pointer section if the pointer is invalid. */
 535                 if (pointer == 0xFFFF || pointer == 0 ||
 536                     pointer >= hw->eeprom.word_size)
 537                         continue;
 538
 539                 if (ixgbe_read_eerd_generic(hw, pointer, &length)) {
 540                         DEBUGOUT("EEPROM read failed\n");
 541                         return IXGBE_ERR_EEPROM;
 542                 }
 543
 544                 /* Skip pointer section if length is invalid. */
 545                 if (length == 0xFFFF || length == 0 ||
 546                     (pointer + length) >= hw->eeprom.word_size)
 547                         continue;
 548
 549                 for (j = pointer + 1; j <= pointer + length; j++) {
 550                         if (ixgbe_read_eerd_generic(hw, j, &word)) {
 551                                 DEBUGOUT("EEPROM read failed\n");
 552                                 return IXGBE_ERR_EEPROM;
 553                         }
 554                         checksum += word;
 555                 }
 556         }
 557
 558         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
 559
 560         return (s32)checksum;
 561 }
 562
 563 /**
 564  *  ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
 565  *  @hw: pointer to hardware structure
 566  *  @checksum_val: calculated checksum
 567  *
 568  *  Performs checksum calculation and validates the EEPROM checksum.  If the
 569  *  caller does not need checksum_val, the value can be NULL.
 570  **/
 571 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
 572                                         u16 *checksum_val)
 573 {
 574         s32 status;
 575         u16 checksum;
 576         u16 read_checksum = 0;
 577
 578         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540");
 579
 580         /* Read the first word from the EEPROM. If this times out or fails, do
 581          * not continue or we could be in for a very long wait while every
 582          * EEPROM read fails
 583          */
 584         status = hw->eeprom.ops.read(hw, 0, &checksum);
 585         if (status) {
 586                 DEBUGOUT("EEPROM read failed\n");
 587                 return status;
 588         }
 589
 590         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
 591                 return IXGBE_ERR_SWFW_SYNC;
 592
 593         status = hw->eeprom.ops.calc_checksum(hw);
 594         if (status < 0)
 595                 goto out;
 596
 597         checksum = (u16)(status & 0xffff);
 598
 599         /* Do not use hw->eeprom.ops.read because we do not want to take
 600          * the synchronization semaphores twice here.
 601          */
 602         status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
 603                                          &read_checksum);
 604         if (status)
 605                 goto out;
 606
 607         /* Verify read checksum from EEPROM is the same as
 608          * calculated checksum
 609          */
 610         if (read_checksum != checksum) {
 611                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 612                              "Invalid EEPROM checksum");
 613                 status = IXGBE_ERR_EEPROM_CHECKSUM;
 614         }
 615
 616         /* If the user cares, return the calculated checksum */
 617         if (checksum_val)
 618                 *checksum_val = checksum;
 619
 620 out:
 621         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 622
 623         return status;
 624 }
 625
 626 /**
 627  * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
 628  * @hw: pointer to hardware structure
 629  *
 630  * After writing EEPROM to shadow RAM using EEWR register, software calculates
 631  * checksum and updates the EEPROM and instructs the hardware to update
 632  * the flash.
 633  **/
 634 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
 635 {
 636         s32 status;
 637         u16 checksum;
 638
 639         DEBUGFUNC("ixgbe_update_eeprom_checksum_X540");
 640
 641         /* Read the first word from the EEPROM. If this times out or fails, do
 642          * not continue or we could be in for a very long wait while every
 643          * EEPROM read fails
 644          */
 645         status = hw->eeprom.ops.read(hw, 0, &checksum);
 646         if (status) {
 647                 DEBUGOUT("EEPROM read failed\n");
 648                 return status;
 649         }
 650
 651         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
 652                 return IXGBE_ERR_SWFW_SYNC;
 653
 654         status = hw->eeprom.ops.calc_checksum(hw);
 655         if (status < 0)
 656                 goto out;
 657
 658         checksum = (u16)(status & 0xffff);
 659
 660         /* Do not use hw->eeprom.ops.write because we do not want to
 661          * take the synchronization semaphores twice here.
 662          */
 663         status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum);
 664         if (status)
 665                 goto out;
 666
 667         status = ixgbe_update_flash_X540(hw);
 668
 669 out:
 670         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 671
 672         return status;
 673 }
 674
 675 /**
 676  *  ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
 677  *  @hw: pointer to hardware structure
 678  *
 679  *  Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
 680  *  EEPROM from shadow RAM to the flash device.
 681  **/
 682 s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
 683 {
 684         u32 flup;
 685         s32 status;
 686
 687         DEBUGFUNC("ixgbe_update_flash_X540");
 688
 689         status = ixgbe_poll_flash_update_done_X540(hw);
 690         if (status == IXGBE_ERR_EEPROM) {
 691                 DEBUGOUT("Flash update time out\n");
 692                 goto out;
 693         }
 694
 695         flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)) | IXGBE_EEC_FLUP;
 696         IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup);
 697
 698         status = ixgbe_poll_flash_update_done_X540(hw);
 699         if (status == IXGBE_SUCCESS)
 700                 DEBUGOUT("Flash update complete\n");
 701         else
 702                 DEBUGOUT("Flash update time out\n");
 703
 704         if (hw->mac.type == ixgbe_mac_X540 && hw->revision_id == 0) {
 705                 flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
 706
 707                 if (flup & IXGBE_EEC_SEC1VAL) {
 708                         flup |= IXGBE_EEC_FLUP;
 709                         IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup);
 710                 }
 711
 712                 status = ixgbe_poll_flash_update_done_X540(hw);
 713                 if (status == IXGBE_SUCCESS)
 714                         DEBUGOUT("Flash update complete\n");
 715                 else
 716                         DEBUGOUT("Flash update time out\n");
 717         }
 718 out:
 719         return status;
 720 }
 721
 722 /**
 723  *  ixgbe_poll_flash_update_done_X540 - Poll flash update status
 724  *  @hw: pointer to hardware structure
 725  *
 726  *  Polls the FLUDONE (bit 26) of the EEC Register to determine when the
 727  *  flash update is done.
 728  **/
 729 STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
 730 {
 731         u32 i;
 732         u32 reg;
 733         s32 status = IXGBE_ERR_EEPROM;
 734
 735         DEBUGFUNC("ixgbe_poll_flash_update_done_X540");
 736
 737         for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
 738                 reg = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
 739                 if (reg & IXGBE_EEC_FLUDONE) {
 740                         status = IXGBE_SUCCESS;
 741                         break;
 742                 }
 743                 msec_delay(5);
 744         }
 745
 746         if (i == IXGBE_FLUDONE_ATTEMPTS)
 747                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 748                              "Flash update status polling timed out");
 749
 750         return status;
 751 }
 752
 753 /**
 754  *  ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
 755  *  @hw: pointer to hardware structure
 756  *  @mask: Mask to specify which semaphore to acquire
 757  *
 758  *  Acquires the SWFW semaphore thought the SW_FW_SYNC register for
 759  *  the specified function (CSR, PHY0, PHY1, NVM, Flash)
 760  **/
 761 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
 762 {
 763         u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK;
 764         u32 fwmask = swmask << 5;
 765         u32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK;
 766         u32 timeout = 200;
 767         u32 hwmask = 0;
 768         u32 swfw_sync;
 769         u32 i;
 770
 771         DEBUGFUNC("ixgbe_acquire_swfw_sync_X540");
 772
 773         if (swmask & IXGBE_GSSR_EEP_SM)
 774                 hwmask |= IXGBE_GSSR_FLASH_SM;
 775
 776         /* SW only mask doesn't have FW bit pair */
 777         if (mask & IXGBE_GSSR_SW_MNG_SM)
 778                 swmask |= IXGBE_GSSR_SW_MNG_SM;
 779
 780         swmask |= swi2c_mask;
 781         fwmask |= swi2c_mask << 2;
 782         for (i = 0; i < timeout; i++) {
 783                 /* SW NVM semaphore bit is used for access to all
 784                  * SW_FW_SYNC bits (not just NVM)
 785                  */
 786                 if (ixgbe_get_swfw_sync_semaphore(hw)) {
 787                         DEBUGOUT("Failed to get NVM access and register semaphore, returning IXGBE_ERR_SWFW_SYNC\n");
 788                         return IXGBE_ERR_SWFW_SYNC;
 789                 }
 790
 791                 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
 792                 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
 793                         swfw_sync |= swmask;
 794                         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw),
 795                                         swfw_sync);
 796                         ixgbe_release_swfw_sync_semaphore(hw);
 797                         return IXGBE_SUCCESS;
 798                 }
 799                 /* Firmware currently using resource (fwmask), hardware
 800                  * currently using resource (hwmask), or other software
 801                  * thread currently using resource (swmask)
 802                  */
 803                 ixgbe_release_swfw_sync_semaphore(hw);
 804                 msec_delay(5);
 805         }
 806
 807         /* Failed to get SW only semaphore */
 808         if (swmask == IXGBE_GSSR_SW_MNG_SM) {
 809                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 810                              "Failed to get SW only semaphore");
 811                 DEBUGOUT("Failed to get SW only semaphore, returning IXGBE_ERR_SWFW_SYNC\n");
 812                 return IXGBE_ERR_SWFW_SYNC;
 813         }
 814
 815         /* If the resource is not released by the FW/HW the SW can assume that
 816          * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
 817          * of the requested resource(s) while ignoring the corresponding FW/HW
 818          * bits in the SW_FW_SYNC register.
 819          */
 820         if (ixgbe_get_swfw_sync_semaphore(hw)) {
 821                 DEBUGOUT("Failed to get NVM sempahore and register semaphore while forcefully ignoring FW sempahore bit(s) and setting SW semaphore bit(s), returning IXGBE_ERR_SWFW_SYNC\n");
 822                 return IXGBE_ERR_SWFW_SYNC;
 823         }
 824         swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
 825         if (swfw_sync & (fwmask | hwmask)) {
 826                 swfw_sync |= swmask;
 827                 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync);
 828                 ixgbe_release_swfw_sync_semaphore(hw);
 829                 msec_delay(5);
 830                 return IXGBE_SUCCESS;
 831         }
 832         /* If the resource is not released by other SW the SW can assume that
 833          * the other SW malfunctions. In that case the SW should clear all SW
 834          * flags that it does not own and then repeat the whole process once
 835          * again.
 836          */
 837         if (swfw_sync & swmask) {
 838                 u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
 839                             IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM;
 840
 841                 if (swi2c_mask)
 842                         rmask |= IXGBE_GSSR_I2C_MASK;
 843                 ixgbe_release_swfw_sync_X540(hw, rmask);
 844                 ixgbe_release_swfw_sync_semaphore(hw);
 845                 DEBUGOUT("Resource not released by other SW, returning IXGBE_ERR_SWFW_SYNC\n");
 846                 return IXGBE_ERR_SWFW_SYNC;
 847         }
 848         ixgbe_release_swfw_sync_semaphore(hw);
 849         DEBUGOUT("Returning error IXGBE_ERR_SWFW_SYNC\n");
 850
 851         return IXGBE_ERR_SWFW_SYNC;
 852 }
 853
 854 /**
 855  *  ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
 856  *  @hw: pointer to hardware structure
 857  *  @mask: Mask to specify which semaphore to release
 858  *
 859  *  Releases the SWFW semaphore through the SW_FW_SYNC register
 860  *  for the specified function (CSR, PHY0, PHY1, EVM, Flash)
 861  **/
 862 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
 863 {
 864         u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM);
 865         u32 swfw_sync;
 866
 867         DEBUGFUNC("ixgbe_release_swfw_sync_X540");
 868
 869         if (mask & IXGBE_GSSR_I2C_MASK)
 870                 swmask |= mask & IXGBE_GSSR_I2C_MASK;
 871         ixgbe_get_swfw_sync_semaphore(hw);
 872
 873         swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
 874         swfw_sync &= ~swmask;
 875         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync);
 876
 877         ixgbe_release_swfw_sync_semaphore(hw);
 878         msec_delay(2);
 879 }
 880
 881 /**
 882  *  ixgbe_get_swfw_sync_semaphore - Get hardware semaphore
 883  *  @hw: pointer to hardware structure
 884  *
 885  *  Sets the hardware semaphores so SW/FW can gain control of shared resources
 886  **/
 887 STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
 888 {
 889         s32 status = IXGBE_ERR_EEPROM;
 890         u32 timeout = 2000;
 891         u32 i;
 892         u32 swsm;
 893
 894         DEBUGFUNC("ixgbe_get_swfw_sync_semaphore");
 895
 896         /* Get SMBI software semaphore between device drivers first */
 897         for (i = 0; i < timeout; i++) {
 898                 /*
 899                  * If the SMBI bit is 0 when we read it, then the bit will be
 900                  * set and we have the semaphore
 901                  */
 902                 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
 903                 if (!(swsm & IXGBE_SWSM_SMBI)) {
 904                         status = IXGBE_SUCCESS;
 905                         break;
 906                 }
 907                 usec_delay(50);
 908         }
 909
 910         /* Now get the semaphore between SW/FW through the REGSMP bit */
 911         if (status == IXGBE_SUCCESS) {
 912                 for (i = 0; i < timeout; i++) {
 913                         swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
 914                         if (!(swsm & IXGBE_SWFW_REGSMP))
 915                                 break;
 916
 917                         usec_delay(50);
 918                 }
 919
 920                 /*
 921                  * Release semaphores and return error if SW NVM semaphore
 922                  * was not granted because we don't have access to the EEPROM
 923                  */
 924                 if (i >= timeout) {
 925                         ERROR_REPORT1(IXGBE_ERROR_POLLING,
 926                                 "REGSMP Software NVM semaphore not granted.\n");
 927                         ixgbe_release_swfw_sync_semaphore(hw);
 928                         status = IXGBE_ERR_EEPROM;
 929                 }
 930         } else {
 931                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 932                              "Software semaphore SMBI between device drivers "
 933                              "not granted.\n");
 934         }
 935
 936         return status;
 937 }
 938
 939 /**
 940  *  ixgbe_release_swfw_sync_semaphore - Release hardware semaphore
 941  *  @hw: pointer to hardware structure
 942  *
 943  *  This function clears hardware semaphore bits.
 944  **/
 945 STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
 946 {
 947         u32 swsm;
 948
 949         DEBUGFUNC("ixgbe_release_swfw_sync_semaphore");
 950
 951         /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
 952
 953         swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
 954         swsm &= ~IXGBE_SWFW_REGSMP;
 955         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swsm);
 956
 957         swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
 958         swsm &= ~IXGBE_SWSM_SMBI;
 959         IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
 960
 961         IXGBE_WRITE_FLUSH(hw);
 962 }
 963
 964 /**
 965  *  ixgbe_init_swfw_sync_X540 - Release hardware semaphore
 966  *  @hw: pointer to hardware structure
 967  *
 968  *  This function reset hardware semaphore bits for a semaphore that may
 969  *  have be left locked due to a catastrophic failure.
 970  **/
 971 void ixgbe_init_swfw_sync_X540(struct ixgbe_hw *hw)
 972 {
 973         /* First try to grab the semaphore but we don't need to bother
 974          * looking to see whether we got the lock or  not since we do
 975          * the same thing regardless of whether we got the lock or not.
 976          * We got the lock - we release it.
 977          * We timeout trying to get the lock - we force its release.
 978          */
 979         ixgbe_get_swfw_sync_semaphore(hw);
 980         ixgbe_release_swfw_sync_semaphore(hw);
 981 }
 982
 983 /**
 984  * ixgbe_blink_led_start_X540 - Blink LED based on index.
 985  * @hw: pointer to hardware structure
 986  * @index: led number to blink
 987  *
 988  * Devices that implement the version 2 interface:
 989  *   X540
 990  **/
 991 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
 992 {
 993         u32 macc_reg;
 994         u32 ledctl_reg;
 995         ixgbe_link_speed speed;
 996         bool link_up;
 997
 998         DEBUGFUNC("ixgbe_blink_led_start_X540");
 999
1000         if (index > 3)
1001                 return IXGBE_ERR_PARAM;
1002
1003         /*
1004          * Link should be up in order for the blink bit in the LED control
1005          * register to work. Force link and speed in the MAC if link is down.
1006          * This will be reversed when we stop the blinking.
1007          */
1008         hw->mac.ops.check_link(hw, &speed, &link_up, false);
1009         if (link_up == false) {
1010                 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
1011                 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
1012                 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
1013         }
1014         /* Set the LED to LINK_UP + BLINK. */
1015         ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1016         ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
1017         ledctl_reg |= IXGBE_LED_BLINK(index);
1018         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
1019         IXGBE_WRITE_FLUSH(hw);
1020
1021         return IXGBE_SUCCESS;
1022 }
1023
1024 /**
1025  * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
1026  * @hw: pointer to hardware structure
1027  * @index: led number to stop blinking
1028  *
1029  * Devices that implement the version 2 interface:
1030  *   X540
1031  **/
1032 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
1033 {
1034         u32 macc_reg;
1035         u32 ledctl_reg;
1036
1037         if (index > 3)
1038                 return IXGBE_ERR_PARAM;
1039
1040         DEBUGFUNC("ixgbe_blink_led_stop_X540");
1041
1042         /* Restore the LED to its default value. */
1043         ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1044         ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
1045         ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
1046         ledctl_reg &= ~IXGBE_LED_BLINK(index);
1047         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
1048
1049         /* Unforce link and speed in the MAC. */
1050         macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
1051         macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
1052         IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
1053         IXGBE_WRITE_FLUSH(hw);
1054
1055         return IXGBE_SUCCESS;
1056 }