1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x540.h"
35 #include "ixgbe_type.h"
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
40 #define IXGBE_X540_MAX_TX_QUEUES 128
41 #define IXGBE_X540_MAX_RX_QUEUES 128
42 #define IXGBE_X540_RAR_ENTRIES 128
43 #define IXGBE_X540_MC_TBL_SIZE 128
44 #define IXGBE_X540_VFT_TBL_SIZE 128
45 #define IXGBE_X540_RX_PB_SIZE 384
47 STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
48 STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
49 STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
52 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type
53 * @hw: pointer to hardware structure
55 * Initialize the function pointers and assign the MAC type for X540.
56 * Does not touch the hardware.
58 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
60 struct ixgbe_mac_info *mac = &hw->mac;
61 struct ixgbe_phy_info *phy = &hw->phy;
62 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
65 DEBUGFUNC("ixgbe_init_ops_X540");
67 ret_val = ixgbe_init_phy_ops_generic(hw);
68 ret_val = ixgbe_init_ops_generic(hw);
72 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
73 eeprom->ops.read = ixgbe_read_eerd_X540;
74 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_X540;
75 eeprom->ops.write = ixgbe_write_eewr_X540;
76 eeprom->ops.write_buffer = ixgbe_write_eewr_buffer_X540;
77 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X540;
78 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X540;
79 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X540;
82 phy->ops.init = ixgbe_init_phy_ops_generic;
83 phy->ops.reset = NULL;
84 phy->ops.set_phy_power = ixgbe_set_copper_phy_power;
87 mac->ops.reset_hw = ixgbe_reset_hw_X540;
88 mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2;
89 mac->ops.get_media_type = ixgbe_get_media_type_X540;
90 mac->ops.get_supported_physical_layer =
91 ixgbe_get_supported_physical_layer_X540;
92 mac->ops.read_analog_reg8 = NULL;
93 mac->ops.write_analog_reg8 = NULL;
94 mac->ops.start_hw = ixgbe_start_hw_X540;
95 mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic;
96 mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic;
97 mac->ops.get_device_caps = ixgbe_get_device_caps_generic;
98 mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic;
99 mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic;
100 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X540;
101 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X540;
102 mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic;
103 mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic;
105 /* RAR, Multicast, VLAN */
106 mac->ops.set_vmdq = ixgbe_set_vmdq_generic;
107 mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic;
108 mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic;
109 mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic;
110 mac->rar_highwater = 1;
111 mac->ops.set_vfta = ixgbe_set_vfta_generic;
112 mac->ops.set_vlvf = ixgbe_set_vlvf_generic;
113 mac->ops.clear_vfta = ixgbe_clear_vfta_generic;
114 mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic;
115 mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing;
116 mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing;
119 mac->ops.get_link_capabilities =
120 ixgbe_get_copper_link_capabilities_generic;
121 mac->ops.setup_link = ixgbe_setup_mac_link_X540;
122 mac->ops.setup_rxpba = ixgbe_set_rxpba_generic;
123 mac->ops.check_link = ixgbe_check_mac_link_generic;
126 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE;
127 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE;
128 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES;
129 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE;
130 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES;
131 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES;
132 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
136 * ARC supported; valid only if manageability features are
139 mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw))
140 & IXGBE_FWSM_MODE_MASK);
142 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
145 mac->ops.blink_led_start = ixgbe_blink_led_start_X540;
146 mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;
148 /* Manageability interface */
149 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic;
151 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
157 * ixgbe_get_link_capabilities_X540 - Determines link capabilities
158 * @hw: pointer to hardware structure
159 * @speed: pointer to link speed
160 * @autoneg: true when autoneg or autotry is enabled
162 * Determines the link capabilities by reading the AUTOC register.
164 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
165 ixgbe_link_speed *speed,
168 ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
170 return IXGBE_SUCCESS;
174 * ixgbe_get_media_type_X540 - Get media type
175 * @hw: pointer to hardware structure
177 * Returns the media type (fiber, copper, backplane)
179 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
181 UNREFERENCED_1PARAMETER(hw);
182 return ixgbe_media_type_copper;
186 * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities
187 * @hw: pointer to hardware structure
188 * @speed: new link speed
189 * @autoneg_wait_to_complete: true when waiting for completion is needed
191 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
192 ixgbe_link_speed speed,
193 bool autoneg_wait_to_complete)
195 DEBUGFUNC("ixgbe_setup_mac_link_X540");
196 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
200 * ixgbe_reset_hw_X540 - Perform hardware reset
201 * @hw: pointer to hardware structure
203 * Resets the hardware by resetting the transmit and receive units, masks
204 * and clears all interrupts, and perform a reset.
206 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
211 DEBUGFUNC("ixgbe_reset_hw_X540");
213 /* Call adapter stop to disable tx/rx and clear interrupts */
214 status = hw->mac.ops.stop_adapter(hw);
215 if (status != IXGBE_SUCCESS)
218 /* flush pending Tx transactions */
219 ixgbe_clear_tx_pending(hw);
222 ctrl = IXGBE_CTRL_RST;
223 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
224 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
225 IXGBE_WRITE_FLUSH(hw);
227 /* Poll for reset bit to self-clear indicating reset is complete */
228 for (i = 0; i < 10; i++) {
230 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
231 if (!(ctrl & IXGBE_CTRL_RST_MASK))
235 if (ctrl & IXGBE_CTRL_RST_MASK) {
236 status = IXGBE_ERR_RESET_FAILED;
237 ERROR_REPORT1(IXGBE_ERROR_POLLING,
238 "Reset polling failed to complete.\n");
243 * Double resets are required for recovery from certain error
244 * conditions. Between resets, it is necessary to stall to allow time
245 * for any pending HW events to complete.
247 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
248 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
252 /* Set the Rx packet buffer size. */
253 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
255 /* Store the permanent mac address */
256 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
259 * Store MAC address from RAR0, clear receive address registers, and
260 * clear the multicast table. Also reset num_rar_entries to 128,
261 * since we modify this value when programming the SAN MAC address.
263 hw->mac.num_rar_entries = 128;
264 hw->mac.ops.init_rx_addrs(hw);
266 /* Store the permanent SAN mac address */
267 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
269 /* Add the SAN MAC address to the RAR only if it's a valid address */
270 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
271 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
272 hw->mac.san_addr, 0, IXGBE_RAH_AV);
274 /* Save the SAN MAC RAR index */
275 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
277 /* Reserve the last RAR for the SAN MAC address */
278 hw->mac.num_rar_entries--;
281 /* Store the alternative WWNN/WWPN prefix */
282 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
283 &hw->mac.wwpn_prefix);
290 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
291 * @hw: pointer to hardware structure
293 * Starts the hardware using the generic start_hw function
294 * and the generation start_hw function.
295 * Then performs revision-specific operations, if any.
297 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
299 s32 ret_val = IXGBE_SUCCESS;
301 DEBUGFUNC("ixgbe_start_hw_X540");
303 ret_val = ixgbe_start_hw_generic(hw);
304 if (ret_val != IXGBE_SUCCESS)
307 ret_val = ixgbe_start_hw_gen2(hw);
314 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
315 * @hw: pointer to hardware structure
317 * Determines physical layer capabilities of the current configuration.
319 u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
321 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
324 DEBUGFUNC("ixgbe_get_supported_physical_layer_X540");
326 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
327 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
328 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
329 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
330 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
331 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
332 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
333 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
335 return physical_layer;
339 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
340 * @hw: pointer to hardware structure
342 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
343 * ixgbe_hw struct in order to set up EEPROM access.
345 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
347 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
351 DEBUGFUNC("ixgbe_init_eeprom_params_X540");
353 if (eeprom->type == ixgbe_eeprom_uninitialized) {
354 eeprom->semaphore_delay = 10;
355 eeprom->type = ixgbe_flash;
357 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
358 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
359 IXGBE_EEC_SIZE_SHIFT);
360 eeprom->word_size = 1 << (eeprom_size +
361 IXGBE_EEPROM_WORD_SIZE_SHIFT);
363 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
364 eeprom->type, eeprom->word_size);
367 return IXGBE_SUCCESS;
371 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
372 * @hw: pointer to hardware structure
373 * @offset: offset of word in the EEPROM to read
374 * @data: word read from the EEPROM
376 * Reads a 16 bit word from the EEPROM using the EERD register.
378 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
380 s32 status = IXGBE_SUCCESS;
382 DEBUGFUNC("ixgbe_read_eerd_X540");
383 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
385 status = ixgbe_read_eerd_generic(hw, offset, data);
386 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
388 status = IXGBE_ERR_SWFW_SYNC;
395 * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD
396 * @hw: pointer to hardware structure
397 * @offset: offset of word in the EEPROM to read
398 * @words: number of words
399 * @data: word(s) read from the EEPROM
401 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
403 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
404 u16 offset, u16 words, u16 *data)
406 s32 status = IXGBE_SUCCESS;
408 DEBUGFUNC("ixgbe_read_eerd_buffer_X540");
409 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
411 status = ixgbe_read_eerd_buffer_generic(hw, offset,
413 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
415 status = IXGBE_ERR_SWFW_SYNC;
422 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
423 * @hw: pointer to hardware structure
424 * @offset: offset of word in the EEPROM to write
425 * @data: word write to the EEPROM
427 * Write a 16 bit word to the EEPROM using the EEWR register.
429 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
431 s32 status = IXGBE_SUCCESS;
433 DEBUGFUNC("ixgbe_write_eewr_X540");
434 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
436 status = ixgbe_write_eewr_generic(hw, offset, data);
437 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
439 status = IXGBE_ERR_SWFW_SYNC;
446 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
447 * @hw: pointer to hardware structure
448 * @offset: offset of word in the EEPROM to write
449 * @words: number of words
450 * @data: word(s) write to the EEPROM
452 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
454 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
455 u16 offset, u16 words, u16 *data)
457 s32 status = IXGBE_SUCCESS;
459 DEBUGFUNC("ixgbe_write_eewr_buffer_X540");
460 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
462 status = ixgbe_write_eewr_buffer_generic(hw, offset,
464 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
466 status = IXGBE_ERR_SWFW_SYNC;
473 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
475 * This function does not use synchronization for EERD and EEWR. It can
476 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
478 * @hw: pointer to hardware structure
480 * Returns a negative error code on error, or the 16-bit checksum
482 s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
489 u16 checksum_last_word = IXGBE_EEPROM_CHECKSUM;
490 u16 ptr_start = IXGBE_PCIE_ANALOG_PTR;
492 /* Do not use hw->eeprom.ops.read because we do not want to take
493 * the synchronization semaphores here. Instead use
494 * ixgbe_read_eerd_generic
497 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540");
499 /* Include 0x0-0x3F in the checksum */
500 for (i = 0; i <= checksum_last_word; i++) {
501 if (ixgbe_read_eerd_generic(hw, i, &word)) {
502 DEBUGOUT("EEPROM read failed\n");
503 return IXGBE_ERR_EEPROM;
505 if (i != IXGBE_EEPROM_CHECKSUM)
509 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the
510 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
512 for (i = ptr_start; i < IXGBE_FW_PTR; i++) {
513 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
516 if (ixgbe_read_eerd_generic(hw, i, &pointer)) {
517 DEBUGOUT("EEPROM read failed\n");
518 return IXGBE_ERR_EEPROM;
521 /* Skip pointer section if the pointer is invalid. */
522 if (pointer == 0xFFFF || pointer == 0 ||
523 pointer >= hw->eeprom.word_size)
526 if (ixgbe_read_eerd_generic(hw, pointer, &length)) {
527 DEBUGOUT("EEPROM read failed\n");
528 return IXGBE_ERR_EEPROM;
531 /* Skip pointer section if length is invalid. */
532 if (length == 0xFFFF || length == 0 ||
533 (pointer + length) >= hw->eeprom.word_size)
536 for (j = pointer + 1; j <= pointer + length; j++) {
537 if (ixgbe_read_eerd_generic(hw, j, &word)) {
538 DEBUGOUT("EEPROM read failed\n");
539 return IXGBE_ERR_EEPROM;
545 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
547 return (s32)checksum;
551 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
552 * @hw: pointer to hardware structure
553 * @checksum_val: calculated checksum
555 * Performs checksum calculation and validates the EEPROM checksum. If the
556 * caller does not need checksum_val, the value can be NULL.
558 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
563 u16 read_checksum = 0;
565 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540");
567 /* Read the first word from the EEPROM. If this times out or fails, do
568 * not continue or we could be in for a very long wait while every
571 status = hw->eeprom.ops.read(hw, 0, &checksum);
573 DEBUGOUT("EEPROM read failed\n");
577 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
578 return IXGBE_ERR_SWFW_SYNC;
580 status = hw->eeprom.ops.calc_checksum(hw);
584 checksum = (u16)(status & 0xffff);
586 /* Do not use hw->eeprom.ops.read because we do not want to take
587 * the synchronization semaphores twice here.
589 status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
594 /* Verify read checksum from EEPROM is the same as
595 * calculated checksum
597 if (read_checksum != checksum) {
598 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
599 "Invalid EEPROM checksum");
600 status = IXGBE_ERR_EEPROM_CHECKSUM;
603 /* If the user cares, return the calculated checksum */
605 *checksum_val = checksum;
608 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
614 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
615 * @hw: pointer to hardware structure
617 * After writing EEPROM to shadow RAM using EEWR register, software calculates
618 * checksum and updates the EEPROM and instructs the hardware to update
621 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
626 DEBUGFUNC("ixgbe_update_eeprom_checksum_X540");
628 /* Read the first word from the EEPROM. If this times out or fails, do
629 * not continue or we could be in for a very long wait while every
632 status = hw->eeprom.ops.read(hw, 0, &checksum);
634 DEBUGOUT("EEPROM read failed\n");
638 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
639 return IXGBE_ERR_SWFW_SYNC;
641 status = hw->eeprom.ops.calc_checksum(hw);
645 checksum = (u16)(status & 0xffff);
647 /* Do not use hw->eeprom.ops.write because we do not want to
648 * take the synchronization semaphores twice here.
650 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum);
654 status = ixgbe_update_flash_X540(hw);
657 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
663 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
664 * @hw: pointer to hardware structure
666 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
667 * EEPROM from shadow RAM to the flash device.
669 s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
674 DEBUGFUNC("ixgbe_update_flash_X540");
676 status = ixgbe_poll_flash_update_done_X540(hw);
677 if (status == IXGBE_ERR_EEPROM) {
678 DEBUGOUT("Flash update time out\n");
682 flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)) | IXGBE_EEC_FLUP;
683 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup);
685 status = ixgbe_poll_flash_update_done_X540(hw);
686 if (status == IXGBE_SUCCESS)
687 DEBUGOUT("Flash update complete\n");
689 DEBUGOUT("Flash update time out\n");
691 if (hw->mac.type == ixgbe_mac_X540 && hw->revision_id == 0) {
692 flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
694 if (flup & IXGBE_EEC_SEC1VAL) {
695 flup |= IXGBE_EEC_FLUP;
696 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup);
699 status = ixgbe_poll_flash_update_done_X540(hw);
700 if (status == IXGBE_SUCCESS)
701 DEBUGOUT("Flash update complete\n");
703 DEBUGOUT("Flash update time out\n");
710 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
711 * @hw: pointer to hardware structure
713 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
714 * flash update is done.
716 STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
720 s32 status = IXGBE_ERR_EEPROM;
722 DEBUGFUNC("ixgbe_poll_flash_update_done_X540");
724 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
725 reg = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
726 if (reg & IXGBE_EEC_FLUDONE) {
727 status = IXGBE_SUCCESS;
733 if (i == IXGBE_FLUDONE_ATTEMPTS)
734 ERROR_REPORT1(IXGBE_ERROR_POLLING,
735 "Flash update status polling timed out");
741 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
742 * @hw: pointer to hardware structure
743 * @mask: Mask to specify which semaphore to acquire
745 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
746 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
748 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
750 u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK;
751 u32 fwmask = swmask << 5;
752 u32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK;
758 DEBUGFUNC("ixgbe_acquire_swfw_sync_X540");
760 if (swmask & IXGBE_GSSR_EEP_SM)
761 hwmask |= IXGBE_GSSR_FLASH_SM;
763 /* SW only mask doesn't have FW bit pair */
764 if (mask & IXGBE_GSSR_SW_MNG_SM)
765 swmask |= IXGBE_GSSR_SW_MNG_SM;
767 swmask |= swi2c_mask;
768 fwmask |= swi2c_mask << 2;
769 for (i = 0; i < timeout; i++) {
770 /* SW NVM semaphore bit is used for access to all
771 * SW_FW_SYNC bits (not just NVM)
773 if (ixgbe_get_swfw_sync_semaphore(hw))
774 return IXGBE_ERR_SWFW_SYNC;
776 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
777 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
779 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw),
781 ixgbe_release_swfw_sync_semaphore(hw);
783 return IXGBE_SUCCESS;
785 /* Firmware currently using resource (fwmask), hardware
786 * currently using resource (hwmask), or other software
787 * thread currently using resource (swmask)
789 ixgbe_release_swfw_sync_semaphore(hw);
793 /* Failed to get SW only semaphore */
794 if (swmask == IXGBE_GSSR_SW_MNG_SM) {
795 ERROR_REPORT1(IXGBE_ERROR_POLLING,
796 "Failed to get SW only semaphore");
797 return IXGBE_ERR_SWFW_SYNC;
800 /* If the resource is not released by the FW/HW the SW can assume that
801 * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
802 * of the requested resource(s) while ignoring the corresponding FW/HW
803 * bits in the SW_FW_SYNC register.
805 if (ixgbe_get_swfw_sync_semaphore(hw))
806 return IXGBE_ERR_SWFW_SYNC;
807 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
808 if (swfw_sync & (fwmask | hwmask)) {
810 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync);
811 ixgbe_release_swfw_sync_semaphore(hw);
813 return IXGBE_SUCCESS;
815 /* If the resource is not released by other SW the SW can assume that
816 * the other SW malfunctions. In that case the SW should clear all SW
817 * flags that it does not own and then repeat the whole process once
820 if (swfw_sync & swmask) {
821 u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
822 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM;
825 rmask |= IXGBE_GSSR_I2C_MASK;
826 ixgbe_release_swfw_sync_X540(hw, rmask);
827 ixgbe_release_swfw_sync_semaphore(hw);
828 return IXGBE_ERR_SWFW_SYNC;
830 ixgbe_release_swfw_sync_semaphore(hw);
832 return IXGBE_ERR_SWFW_SYNC;
836 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
837 * @hw: pointer to hardware structure
838 * @mask: Mask to specify which semaphore to release
840 * Releases the SWFW semaphore through the SW_FW_SYNC register
841 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
843 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
845 u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM);
848 DEBUGFUNC("ixgbe_release_swfw_sync_X540");
850 if (mask & IXGBE_GSSR_I2C_MASK)
851 swmask |= mask & IXGBE_GSSR_I2C_MASK;
852 ixgbe_get_swfw_sync_semaphore(hw);
854 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
855 swfw_sync &= ~swmask;
856 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync);
858 ixgbe_release_swfw_sync_semaphore(hw);
863 * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore
864 * @hw: pointer to hardware structure
866 * Sets the hardware semaphores so SW/FW can gain control of shared resources
868 STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
870 s32 status = IXGBE_ERR_EEPROM;
875 DEBUGFUNC("ixgbe_get_swfw_sync_semaphore");
877 /* Get SMBI software semaphore between device drivers first */
878 for (i = 0; i < timeout; i++) {
880 * If the SMBI bit is 0 when we read it, then the bit will be
881 * set and we have the semaphore
883 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
884 if (!(swsm & IXGBE_SWSM_SMBI)) {
885 status = IXGBE_SUCCESS;
891 /* Now get the semaphore between SW/FW through the REGSMP bit */
892 if (status == IXGBE_SUCCESS) {
893 for (i = 0; i < timeout; i++) {
894 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
895 if (!(swsm & IXGBE_SWFW_REGSMP))
902 * Release semaphores and return error if SW NVM semaphore
903 * was not granted because we don't have access to the EEPROM
906 ERROR_REPORT1(IXGBE_ERROR_POLLING,
907 "REGSMP Software NVM semaphore not granted.\n");
908 ixgbe_release_swfw_sync_semaphore(hw);
909 status = IXGBE_ERR_EEPROM;
912 ERROR_REPORT1(IXGBE_ERROR_POLLING,
913 "Software semaphore SMBI between device drivers "
921 * ixgbe_release_swfw_sync_semaphore - Release hardware semaphore
922 * @hw: pointer to hardware structure
924 * This function clears hardware semaphore bits.
926 STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
930 DEBUGFUNC("ixgbe_release_swfw_sync_semaphore");
932 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
934 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
935 swsm &= ~IXGBE_SWFW_REGSMP;
936 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swsm);
938 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
939 swsm &= ~IXGBE_SWSM_SMBI;
940 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
942 IXGBE_WRITE_FLUSH(hw);
946 * ixgbe_blink_led_start_X540 - Blink LED based on index.
947 * @hw: pointer to hardware structure
948 * @index: led number to blink
950 * Devices that implement the version 2 interface:
953 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
957 ixgbe_link_speed speed;
960 DEBUGFUNC("ixgbe_blink_led_start_X540");
963 * Link should be up in order for the blink bit in the LED control
964 * register to work. Force link and speed in the MAC if link is down.
965 * This will be reversed when we stop the blinking.
967 hw->mac.ops.check_link(hw, &speed, &link_up, false);
968 if (link_up == false) {
969 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
970 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
971 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
973 /* Set the LED to LINK_UP + BLINK. */
974 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
975 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
976 ledctl_reg |= IXGBE_LED_BLINK(index);
977 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
978 IXGBE_WRITE_FLUSH(hw);
980 return IXGBE_SUCCESS;
984 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
985 * @hw: pointer to hardware structure
986 * @index: led number to stop blinking
988 * Devices that implement the version 2 interface:
991 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
996 DEBUGFUNC("ixgbe_blink_led_stop_X540");
998 /* Restore the LED to its default value. */
999 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1000 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
1001 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
1002 ledctl_reg &= ~IXGBE_LED_BLINK(index);
1003 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
1005 /* Unforce link and speed in the MAC. */
1006 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
1007 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
1008 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
1009 IXGBE_WRITE_FLUSH(hw);
1011 return IXGBE_SUCCESS;