1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
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16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x540.h"
35 #include "ixgbe_type.h"
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
40 #define IXGBE_X540_MAX_TX_QUEUES 128
41 #define IXGBE_X540_MAX_RX_QUEUES 128
42 #define IXGBE_X540_RAR_ENTRIES 128
43 #define IXGBE_X540_MC_TBL_SIZE 128
44 #define IXGBE_X540_VFT_TBL_SIZE 128
45 #define IXGBE_X540_RX_PB_SIZE 384
47 STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
48 STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
49 STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
52 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type
53 * @hw: pointer to hardware structure
55 * Initialize the function pointers and assign the MAC type for X540.
56 * Does not touch the hardware.
58 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
60 struct ixgbe_mac_info *mac = &hw->mac;
61 struct ixgbe_phy_info *phy = &hw->phy;
62 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
65 DEBUGFUNC("ixgbe_init_ops_X540");
67 ret_val = ixgbe_init_phy_ops_generic(hw);
68 ret_val = ixgbe_init_ops_generic(hw);
72 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
73 eeprom->ops.read = ixgbe_read_eerd_X540;
74 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_X540;
75 eeprom->ops.write = ixgbe_write_eewr_X540;
76 eeprom->ops.write_buffer = ixgbe_write_eewr_buffer_X540;
77 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X540;
78 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X540;
79 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X540;
82 phy->ops.init = ixgbe_init_phy_ops_generic;
83 phy->ops.reset = NULL;
84 phy->ops.set_phy_power = ixgbe_set_copper_phy_power;
87 mac->ops.reset_hw = ixgbe_reset_hw_X540;
88 mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2;
89 mac->ops.get_media_type = ixgbe_get_media_type_X540;
90 mac->ops.get_supported_physical_layer =
91 ixgbe_get_supported_physical_layer_X540;
92 mac->ops.read_analog_reg8 = NULL;
93 mac->ops.write_analog_reg8 = NULL;
94 mac->ops.start_hw = ixgbe_start_hw_X540;
95 mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic;
96 mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic;
97 mac->ops.get_device_caps = ixgbe_get_device_caps_generic;
98 mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic;
99 mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic;
100 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X540;
101 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X540;
102 mac->ops.init_swfw_sync = ixgbe_init_swfw_sync_X540;
103 mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic;
104 mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic;
106 /* RAR, Multicast, VLAN */
107 mac->ops.set_vmdq = ixgbe_set_vmdq_generic;
108 mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic;
109 mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic;
110 mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic;
111 mac->rar_highwater = 1;
112 mac->ops.set_vfta = ixgbe_set_vfta_generic;
113 mac->ops.set_vlvf = ixgbe_set_vlvf_generic;
114 mac->ops.clear_vfta = ixgbe_clear_vfta_generic;
115 mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic;
116 mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing;
117 mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing;
120 mac->ops.get_link_capabilities =
121 ixgbe_get_copper_link_capabilities_generic;
122 mac->ops.setup_link = ixgbe_setup_mac_link_X540;
123 mac->ops.setup_rxpba = ixgbe_set_rxpba_generic;
124 mac->ops.check_link = ixgbe_check_mac_link_generic;
127 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE;
128 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE;
129 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES;
130 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE;
131 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES;
132 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES;
133 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
137 * ARC supported; valid only if manageability features are
140 mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw))
141 & IXGBE_FWSM_MODE_MASK);
143 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
146 mac->ops.blink_led_start = ixgbe_blink_led_start_X540;
147 mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;
149 /* Manageability interface */
150 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic;
152 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
158 * ixgbe_get_link_capabilities_X540 - Determines link capabilities
159 * @hw: pointer to hardware structure
160 * @speed: pointer to link speed
161 * @autoneg: true when autoneg or autotry is enabled
163 * Determines the link capabilities by reading the AUTOC register.
165 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
166 ixgbe_link_speed *speed,
169 ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
171 return IXGBE_SUCCESS;
175 * ixgbe_get_media_type_X540 - Get media type
176 * @hw: pointer to hardware structure
178 * Returns the media type (fiber, copper, backplane)
180 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
182 UNREFERENCED_1PARAMETER(hw);
183 return ixgbe_media_type_copper;
187 * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities
188 * @hw: pointer to hardware structure
189 * @speed: new link speed
190 * @autoneg_wait_to_complete: true when waiting for completion is needed
192 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
193 ixgbe_link_speed speed,
194 bool autoneg_wait_to_complete)
196 DEBUGFUNC("ixgbe_setup_mac_link_X540");
197 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
201 * ixgbe_reset_hw_X540 - Perform hardware reset
202 * @hw: pointer to hardware structure
204 * Resets the hardware by resetting the transmit and receive units, masks
205 * and clears all interrupts, and perform a reset.
207 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
212 DEBUGFUNC("ixgbe_reset_hw_X540");
214 /* Call adapter stop to disable tx/rx and clear interrupts */
215 status = hw->mac.ops.stop_adapter(hw);
216 if (status != IXGBE_SUCCESS)
219 /* flush pending Tx transactions */
220 ixgbe_clear_tx_pending(hw);
223 ctrl = IXGBE_CTRL_RST;
224 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
225 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
226 IXGBE_WRITE_FLUSH(hw);
228 /* Poll for reset bit to self-clear indicating reset is complete */
229 for (i = 0; i < 10; i++) {
231 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
232 if (!(ctrl & IXGBE_CTRL_RST_MASK))
236 if (ctrl & IXGBE_CTRL_RST_MASK) {
237 status = IXGBE_ERR_RESET_FAILED;
238 ERROR_REPORT1(IXGBE_ERROR_POLLING,
239 "Reset polling failed to complete.\n");
244 * Double resets are required for recovery from certain error
245 * conditions. Between resets, it is necessary to stall to allow time
246 * for any pending HW events to complete.
248 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
249 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
253 /* Set the Rx packet buffer size. */
254 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
256 /* Store the permanent mac address */
257 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
260 * Store MAC address from RAR0, clear receive address registers, and
261 * clear the multicast table. Also reset num_rar_entries to 128,
262 * since we modify this value when programming the SAN MAC address.
264 hw->mac.num_rar_entries = 128;
265 hw->mac.ops.init_rx_addrs(hw);
267 /* Store the permanent SAN mac address */
268 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
270 /* Add the SAN MAC address to the RAR only if it's a valid address */
271 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
272 /* Save the SAN MAC RAR index */
273 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
274 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index,
275 hw->mac.san_addr, 0, IXGBE_RAH_AV);
277 /* clear VMDq pool/queue selection for this RAR */
278 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index,
279 IXGBE_CLEAR_VMDQ_ALL);
281 /* Reserve the last RAR for the SAN MAC address */
282 hw->mac.num_rar_entries--;
285 /* Store the alternative WWNN/WWPN prefix */
286 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
287 &hw->mac.wwpn_prefix);
294 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
295 * @hw: pointer to hardware structure
297 * Starts the hardware using the generic start_hw function
298 * and the generation start_hw function.
299 * Then performs revision-specific operations, if any.
301 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
303 s32 ret_val = IXGBE_SUCCESS;
305 DEBUGFUNC("ixgbe_start_hw_X540");
307 ret_val = ixgbe_start_hw_generic(hw);
308 if (ret_val != IXGBE_SUCCESS)
311 ret_val = ixgbe_start_hw_gen2(hw);
318 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
319 * @hw: pointer to hardware structure
321 * Determines physical layer capabilities of the current configuration.
323 u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
325 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
328 DEBUGFUNC("ixgbe_get_supported_physical_layer_X540");
330 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
331 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
332 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
333 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
334 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
335 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
336 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
337 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
339 return physical_layer;
343 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
344 * @hw: pointer to hardware structure
346 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
347 * ixgbe_hw struct in order to set up EEPROM access.
349 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
351 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
355 DEBUGFUNC("ixgbe_init_eeprom_params_X540");
357 if (eeprom->type == ixgbe_eeprom_uninitialized) {
358 eeprom->semaphore_delay = 10;
359 eeprom->type = ixgbe_flash;
361 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
362 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
363 IXGBE_EEC_SIZE_SHIFT);
364 eeprom->word_size = 1 << (eeprom_size +
365 IXGBE_EEPROM_WORD_SIZE_SHIFT);
367 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
368 eeprom->type, eeprom->word_size);
371 return IXGBE_SUCCESS;
375 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
376 * @hw: pointer to hardware structure
377 * @offset: offset of word in the EEPROM to read
378 * @data: word read from the EEPROM
380 * Reads a 16 bit word from the EEPROM using the EERD register.
382 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
384 s32 status = IXGBE_SUCCESS;
386 DEBUGFUNC("ixgbe_read_eerd_X540");
387 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
389 status = ixgbe_read_eerd_generic(hw, offset, data);
390 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
392 status = IXGBE_ERR_SWFW_SYNC;
399 * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD
400 * @hw: pointer to hardware structure
401 * @offset: offset of word in the EEPROM to read
402 * @words: number of words
403 * @data: word(s) read from the EEPROM
405 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
407 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
408 u16 offset, u16 words, u16 *data)
410 s32 status = IXGBE_SUCCESS;
412 DEBUGFUNC("ixgbe_read_eerd_buffer_X540");
413 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
415 status = ixgbe_read_eerd_buffer_generic(hw, offset,
417 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
419 status = IXGBE_ERR_SWFW_SYNC;
426 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
427 * @hw: pointer to hardware structure
428 * @offset: offset of word in the EEPROM to write
429 * @data: word write to the EEPROM
431 * Write a 16 bit word to the EEPROM using the EEWR register.
433 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
435 s32 status = IXGBE_SUCCESS;
437 DEBUGFUNC("ixgbe_write_eewr_X540");
438 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
440 status = ixgbe_write_eewr_generic(hw, offset, data);
441 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
443 status = IXGBE_ERR_SWFW_SYNC;
450 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
451 * @hw: pointer to hardware structure
452 * @offset: offset of word in the EEPROM to write
453 * @words: number of words
454 * @data: word(s) write to the EEPROM
456 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
458 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
459 u16 offset, u16 words, u16 *data)
461 s32 status = IXGBE_SUCCESS;
463 DEBUGFUNC("ixgbe_write_eewr_buffer_X540");
464 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
466 status = ixgbe_write_eewr_buffer_generic(hw, offset,
468 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
470 status = IXGBE_ERR_SWFW_SYNC;
477 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
479 * This function does not use synchronization for EERD and EEWR. It can
480 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
482 * @hw: pointer to hardware structure
484 * Returns a negative error code on error, or the 16-bit checksum
486 s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
493 u16 checksum_last_word = IXGBE_EEPROM_CHECKSUM;
494 u16 ptr_start = IXGBE_PCIE_ANALOG_PTR;
496 /* Do not use hw->eeprom.ops.read because we do not want to take
497 * the synchronization semaphores here. Instead use
498 * ixgbe_read_eerd_generic
501 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540");
503 /* Include 0x0-0x3F in the checksum */
504 for (i = 0; i <= checksum_last_word; i++) {
505 if (ixgbe_read_eerd_generic(hw, i, &word)) {
506 DEBUGOUT("EEPROM read failed\n");
507 return IXGBE_ERR_EEPROM;
509 if (i != IXGBE_EEPROM_CHECKSUM)
513 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the
514 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
516 for (i = ptr_start; i < IXGBE_FW_PTR; i++) {
517 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
520 if (ixgbe_read_eerd_generic(hw, i, &pointer)) {
521 DEBUGOUT("EEPROM read failed\n");
522 return IXGBE_ERR_EEPROM;
525 /* Skip pointer section if the pointer is invalid. */
526 if (pointer == 0xFFFF || pointer == 0 ||
527 pointer >= hw->eeprom.word_size)
530 if (ixgbe_read_eerd_generic(hw, pointer, &length)) {
531 DEBUGOUT("EEPROM read failed\n");
532 return IXGBE_ERR_EEPROM;
535 /* Skip pointer section if length is invalid. */
536 if (length == 0xFFFF || length == 0 ||
537 (pointer + length) >= hw->eeprom.word_size)
540 for (j = pointer + 1; j <= pointer + length; j++) {
541 if (ixgbe_read_eerd_generic(hw, j, &word)) {
542 DEBUGOUT("EEPROM read failed\n");
543 return IXGBE_ERR_EEPROM;
549 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
551 return (s32)checksum;
555 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
556 * @hw: pointer to hardware structure
557 * @checksum_val: calculated checksum
559 * Performs checksum calculation and validates the EEPROM checksum. If the
560 * caller does not need checksum_val, the value can be NULL.
562 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
567 u16 read_checksum = 0;
569 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540");
571 /* Read the first word from the EEPROM. If this times out or fails, do
572 * not continue or we could be in for a very long wait while every
575 status = hw->eeprom.ops.read(hw, 0, &checksum);
577 DEBUGOUT("EEPROM read failed\n");
581 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
582 return IXGBE_ERR_SWFW_SYNC;
584 status = hw->eeprom.ops.calc_checksum(hw);
588 checksum = (u16)(status & 0xffff);
590 /* Do not use hw->eeprom.ops.read because we do not want to take
591 * the synchronization semaphores twice here.
593 status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
598 /* Verify read checksum from EEPROM is the same as
599 * calculated checksum
601 if (read_checksum != checksum) {
602 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
603 "Invalid EEPROM checksum");
604 status = IXGBE_ERR_EEPROM_CHECKSUM;
607 /* If the user cares, return the calculated checksum */
609 *checksum_val = checksum;
612 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
618 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
619 * @hw: pointer to hardware structure
621 * After writing EEPROM to shadow RAM using EEWR register, software calculates
622 * checksum and updates the EEPROM and instructs the hardware to update
625 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
630 DEBUGFUNC("ixgbe_update_eeprom_checksum_X540");
632 /* Read the first word from the EEPROM. If this times out or fails, do
633 * not continue or we could be in for a very long wait while every
636 status = hw->eeprom.ops.read(hw, 0, &checksum);
638 DEBUGOUT("EEPROM read failed\n");
642 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
643 return IXGBE_ERR_SWFW_SYNC;
645 status = hw->eeprom.ops.calc_checksum(hw);
649 checksum = (u16)(status & 0xffff);
651 /* Do not use hw->eeprom.ops.write because we do not want to
652 * take the synchronization semaphores twice here.
654 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum);
658 status = ixgbe_update_flash_X540(hw);
661 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
667 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
668 * @hw: pointer to hardware structure
670 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
671 * EEPROM from shadow RAM to the flash device.
673 s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
678 DEBUGFUNC("ixgbe_update_flash_X540");
680 status = ixgbe_poll_flash_update_done_X540(hw);
681 if (status == IXGBE_ERR_EEPROM) {
682 DEBUGOUT("Flash update time out\n");
686 flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)) | IXGBE_EEC_FLUP;
687 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup);
689 status = ixgbe_poll_flash_update_done_X540(hw);
690 if (status == IXGBE_SUCCESS)
691 DEBUGOUT("Flash update complete\n");
693 DEBUGOUT("Flash update time out\n");
695 if (hw->mac.type == ixgbe_mac_X540 && hw->revision_id == 0) {
696 flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
698 if (flup & IXGBE_EEC_SEC1VAL) {
699 flup |= IXGBE_EEC_FLUP;
700 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup);
703 status = ixgbe_poll_flash_update_done_X540(hw);
704 if (status == IXGBE_SUCCESS)
705 DEBUGOUT("Flash update complete\n");
707 DEBUGOUT("Flash update time out\n");
714 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
715 * @hw: pointer to hardware structure
717 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
718 * flash update is done.
720 STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
724 s32 status = IXGBE_ERR_EEPROM;
726 DEBUGFUNC("ixgbe_poll_flash_update_done_X540");
728 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
729 reg = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
730 if (reg & IXGBE_EEC_FLUDONE) {
731 status = IXGBE_SUCCESS;
737 if (i == IXGBE_FLUDONE_ATTEMPTS)
738 ERROR_REPORT1(IXGBE_ERROR_POLLING,
739 "Flash update status polling timed out");
745 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
746 * @hw: pointer to hardware structure
747 * @mask: Mask to specify which semaphore to acquire
749 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
750 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
752 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
754 u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK;
755 u32 fwmask = swmask << 5;
756 u32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK;
762 DEBUGFUNC("ixgbe_acquire_swfw_sync_X540");
764 if (swmask & IXGBE_GSSR_EEP_SM)
765 hwmask |= IXGBE_GSSR_FLASH_SM;
767 /* SW only mask doesn't have FW bit pair */
768 if (mask & IXGBE_GSSR_SW_MNG_SM)
769 swmask |= IXGBE_GSSR_SW_MNG_SM;
771 swmask |= swi2c_mask;
772 fwmask |= swi2c_mask << 2;
773 for (i = 0; i < timeout; i++) {
774 /* SW NVM semaphore bit is used for access to all
775 * SW_FW_SYNC bits (not just NVM)
777 if (ixgbe_get_swfw_sync_semaphore(hw))
778 return IXGBE_ERR_SWFW_SYNC;
780 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
781 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
783 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw),
785 ixgbe_release_swfw_sync_semaphore(hw);
786 return IXGBE_SUCCESS;
788 /* Firmware currently using resource (fwmask), hardware
789 * currently using resource (hwmask), or other software
790 * thread currently using resource (swmask)
792 ixgbe_release_swfw_sync_semaphore(hw);
796 /* Failed to get SW only semaphore */
797 if (swmask == IXGBE_GSSR_SW_MNG_SM) {
798 ERROR_REPORT1(IXGBE_ERROR_POLLING,
799 "Failed to get SW only semaphore");
800 return IXGBE_ERR_SWFW_SYNC;
803 /* If the resource is not released by the FW/HW the SW can assume that
804 * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
805 * of the requested resource(s) while ignoring the corresponding FW/HW
806 * bits in the SW_FW_SYNC register.
808 if (ixgbe_get_swfw_sync_semaphore(hw))
809 return IXGBE_ERR_SWFW_SYNC;
810 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
811 if (swfw_sync & (fwmask | hwmask)) {
813 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync);
814 ixgbe_release_swfw_sync_semaphore(hw);
816 return IXGBE_SUCCESS;
818 /* If the resource is not released by other SW the SW can assume that
819 * the other SW malfunctions. In that case the SW should clear all SW
820 * flags that it does not own and then repeat the whole process once
823 if (swfw_sync & swmask) {
824 u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
825 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM;
828 rmask |= IXGBE_GSSR_I2C_MASK;
829 ixgbe_release_swfw_sync_X540(hw, rmask);
830 ixgbe_release_swfw_sync_semaphore(hw);
831 return IXGBE_ERR_SWFW_SYNC;
833 ixgbe_release_swfw_sync_semaphore(hw);
835 return IXGBE_ERR_SWFW_SYNC;
839 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
840 * @hw: pointer to hardware structure
841 * @mask: Mask to specify which semaphore to release
843 * Releases the SWFW semaphore through the SW_FW_SYNC register
844 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
846 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
848 u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM);
851 DEBUGFUNC("ixgbe_release_swfw_sync_X540");
853 if (mask & IXGBE_GSSR_I2C_MASK)
854 swmask |= mask & IXGBE_GSSR_I2C_MASK;
855 ixgbe_get_swfw_sync_semaphore(hw);
857 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
858 swfw_sync &= ~swmask;
859 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync);
861 ixgbe_release_swfw_sync_semaphore(hw);
866 * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore
867 * @hw: pointer to hardware structure
869 * Sets the hardware semaphores so SW/FW can gain control of shared resources
871 STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
873 s32 status = IXGBE_ERR_EEPROM;
878 DEBUGFUNC("ixgbe_get_swfw_sync_semaphore");
880 /* Get SMBI software semaphore between device drivers first */
881 for (i = 0; i < timeout; i++) {
883 * If the SMBI bit is 0 when we read it, then the bit will be
884 * set and we have the semaphore
886 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
887 if (!(swsm & IXGBE_SWSM_SMBI)) {
888 status = IXGBE_SUCCESS;
894 /* Now get the semaphore between SW/FW through the REGSMP bit */
895 if (status == IXGBE_SUCCESS) {
896 for (i = 0; i < timeout; i++) {
897 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
898 if (!(swsm & IXGBE_SWFW_REGSMP))
905 * Release semaphores and return error if SW NVM semaphore
906 * was not granted because we don't have access to the EEPROM
909 ERROR_REPORT1(IXGBE_ERROR_POLLING,
910 "REGSMP Software NVM semaphore not granted.\n");
911 ixgbe_release_swfw_sync_semaphore(hw);
912 status = IXGBE_ERR_EEPROM;
915 ERROR_REPORT1(IXGBE_ERROR_POLLING,
916 "Software semaphore SMBI between device drivers "
924 * ixgbe_release_swfw_sync_semaphore - Release hardware semaphore
925 * @hw: pointer to hardware structure
927 * This function clears hardware semaphore bits.
929 STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
933 DEBUGFUNC("ixgbe_release_swfw_sync_semaphore");
935 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
937 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
938 swsm &= ~IXGBE_SWFW_REGSMP;
939 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swsm);
941 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
942 swsm &= ~IXGBE_SWSM_SMBI;
943 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
945 IXGBE_WRITE_FLUSH(hw);
949 * ixgbe_init_swfw_sync_X540 - Release hardware semaphore
950 * @hw: pointer to hardware structure
952 * This function reset hardware semaphore bits for a semaphore that may
953 * have be left locked due to a catastrophic failure.
955 void ixgbe_init_swfw_sync_X540(struct ixgbe_hw *hw)
957 /* First try to grab the semaphore but we don't need to bother
958 * looking to see whether we got the lock or not since we do
959 * the same thing regardless of whether we got the lock or not.
960 * We got the lock - we release it.
961 * We timeout trying to get the lock - we force its release.
963 ixgbe_get_swfw_sync_semaphore(hw);
964 ixgbe_release_swfw_sync_semaphore(hw);
968 * ixgbe_blink_led_start_X540 - Blink LED based on index.
969 * @hw: pointer to hardware structure
970 * @index: led number to blink
972 * Devices that implement the version 2 interface:
975 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
979 ixgbe_link_speed speed;
982 DEBUGFUNC("ixgbe_blink_led_start_X540");
985 return IXGBE_ERR_PARAM;
988 * Link should be up in order for the blink bit in the LED control
989 * register to work. Force link and speed in the MAC if link is down.
990 * This will be reversed when we stop the blinking.
992 hw->mac.ops.check_link(hw, &speed, &link_up, false);
993 if (link_up == false) {
994 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
995 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
996 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
998 /* Set the LED to LINK_UP + BLINK. */
999 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1000 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
1001 ledctl_reg |= IXGBE_LED_BLINK(index);
1002 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
1003 IXGBE_WRITE_FLUSH(hw);
1005 return IXGBE_SUCCESS;
1009 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
1010 * @hw: pointer to hardware structure
1011 * @index: led number to stop blinking
1013 * Devices that implement the version 2 interface:
1016 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
1022 return IXGBE_ERR_PARAM;
1024 DEBUGFUNC("ixgbe_blink_led_stop_X540");
1026 /* Restore the LED to its default value. */
1027 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1028 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
1029 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
1030 ledctl_reg &= ~IXGBE_LED_BLINK(index);
1031 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
1033 /* Unforce link and speed in the MAC. */
1034 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
1035 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
1036 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
1037 IXGBE_WRITE_FLUSH(hw);
1039 return IXGBE_SUCCESS;