drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  44 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw);
  45
  46 /**
  47  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  48  *  @hw: pointer to hardware structure
  49  *
  50  *  Initialize the function pointers and assign the MAC type for X550.
  51  *  Does not touch the hardware.
  52  **/
  53 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  54 {
  55         struct ixgbe_mac_info *mac = &hw->mac;
  56         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  57         s32 ret_val;
  58
  59         DEBUGFUNC("ixgbe_init_ops_X550");
  60
  61         ret_val = ixgbe_init_ops_X540(hw);
  62         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  63         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  64         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  65         mac->ops.setup_eee = NULL;
  66         mac->ops.set_source_address_pruning =
  67                         ixgbe_set_source_address_pruning_X550;
  68         mac->ops.set_ethertype_anti_spoofing =
  69                         ixgbe_set_ethertype_anti_spoofing_X550;
  70
  71         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  72         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  73         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  74         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  75         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  76         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  77         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  78         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  79         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  80
  81         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  82         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  83         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  84         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  85         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  86         /* Manageability interface */
  87         mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_x550;
  88         switch (hw->device_id) {
  89         case IXGBE_DEV_ID_X550EM_X_10G_T:
  90         case IXGBE_DEV_ID_X550EM_A_10G_T:
  91                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  92                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  93                 break;
  94         default:
  95                 break;
  96         }
  97         return ret_val;
  98 }
  99
 100 /**
 101  * ixgbe_read_cs4227 - Read CS4227 register
 102  * @hw: pointer to hardware structure
 103  * @reg: register number to write
 104  * @value: pointer to receive value read
 105  *
 106  * Returns status code
 107  **/
 108 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
 109 {
 110         return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
 111 }
 112
 113 /**
 114  * ixgbe_write_cs4227 - Write CS4227 register
 115  * @hw: pointer to hardware structure
 116  * @reg: register number to write
 117  * @value: value to write to register
 118  *
 119  * Returns status code
 120  **/
 121 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 122 {
 123         return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
 124 }
 125
 126 /**
 127  * ixgbe_read_pe - Read register from port expander
 128  * @hw: pointer to hardware structure
 129  * @reg: register number to read
 130  * @value: pointer to receive read value
 131  *
 132  * Returns status code
 133  **/
 134 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 135 {
 136         s32 status;
 137
 138         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 139         if (status != IXGBE_SUCCESS)
 140                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 141                               "port expander access failed with %d\n", status);
 142         return status;
 143 }
 144
 145 /**
 146  * ixgbe_write_pe - Write register to port expander
 147  * @hw: pointer to hardware structure
 148  * @reg: register number to write
 149  * @value: value to write
 150  *
 151  * Returns status code
 152  **/
 153 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 154 {
 155         s32 status;
 156
 157         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 158         if (status != IXGBE_SUCCESS)
 159                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 160                               "port expander access failed with %d\n", status);
 161         return status;
 162 }
 163
 164 /**
 165  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 166  * @hw: pointer to hardware structure
 167  *
 168  * This function assumes that the caller has acquired the proper semaphore.
 169  * Returns error code
 170  **/
 171 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 172 {
 173         s32 status;
 174         u32 retry;
 175         u16 value;
 176         u8 reg;
 177
 178         /* Trigger hard reset. */
 179         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 180         if (status != IXGBE_SUCCESS)
 181                 return status;
 182         reg |= IXGBE_PE_BIT1;
 183         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 184         if (status != IXGBE_SUCCESS)
 185                 return status;
 186
 187         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 188         if (status != IXGBE_SUCCESS)
 189                 return status;
 190         reg &= ~IXGBE_PE_BIT1;
 191         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 192         if (status != IXGBE_SUCCESS)
 193                 return status;
 194
 195         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 196         if (status != IXGBE_SUCCESS)
 197                 return status;
 198         reg &= ~IXGBE_PE_BIT1;
 199         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 200         if (status != IXGBE_SUCCESS)
 201                 return status;
 202
 203         usec_delay(IXGBE_CS4227_RESET_HOLD);
 204
 205         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 206         if (status != IXGBE_SUCCESS)
 207                 return status;
 208         reg |= IXGBE_PE_BIT1;
 209         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 210         if (status != IXGBE_SUCCESS)
 211                 return status;
 212
 213         /* Wait for the reset to complete. */
 214         msec_delay(IXGBE_CS4227_RESET_DELAY);
 215         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 216                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 217                                            &value);
 218                 if (status == IXGBE_SUCCESS &&
 219                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 220                         break;
 221                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 222         }
 223         if (retry == IXGBE_CS4227_RETRIES) {
 224                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 225                         "CS4227 reset did not complete.");
 226                 return IXGBE_ERR_PHY;
 227         }
 228
 229         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 230         if (status != IXGBE_SUCCESS ||
 231             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 232                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 233                         "CS4227 EEPROM did not load successfully.");
 234                 return IXGBE_ERR_PHY;
 235         }
 236
 237         return IXGBE_SUCCESS;
 238 }
 239
 240 /**
 241  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 242  * @hw: pointer to hardware structure
 243  **/
 244 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 245 {
 246         s32 status = IXGBE_SUCCESS;
 247         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 248         u16 value = 0;
 249         u8 retry;
 250
 251         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 252                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 253                 if (status != IXGBE_SUCCESS) {
 254                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 255                                 "semaphore failed with %d", status);
 256                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 257                         continue;
 258                 }
 259
 260                 /* Get status of reset flow. */
 261                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 262
 263                 if (status == IXGBE_SUCCESS &&
 264                     value == IXGBE_CS4227_RESET_COMPLETE)
 265                         goto out;
 266
 267                 if (status != IXGBE_SUCCESS ||
 268                     value != IXGBE_CS4227_RESET_PENDING)
 269                         break;
 270
 271                 /* Reset is pending. Wait and check again. */
 272                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 273                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 274         }
 275
 276         /* If still pending, assume other instance failed. */
 277         if (retry == IXGBE_CS4227_RETRIES) {
 278                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 279                 if (status != IXGBE_SUCCESS) {
 280                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 281                                       "semaphore failed with %d", status);
 282                         return;
 283                 }
 284         }
 285
 286         /* Reset the CS4227. */
 287         status = ixgbe_reset_cs4227(hw);
 288         if (status != IXGBE_SUCCESS) {
 289                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 290                         "CS4227 reset failed: %d", status);
 291                 goto out;
 292         }
 293
 294         /* Reset takes so long, temporarily release semaphore in case the
 295          * other driver instance is waiting for the reset indication.
 296          */
 297         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 298                            IXGBE_CS4227_RESET_PENDING);
 299         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 300         msec_delay(10);
 301         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 302         if (status != IXGBE_SUCCESS) {
 303                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 304                         "semaphore failed with %d", status);
 305                 return;
 306         }
 307
 308         /* Record completion for next time. */
 309         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 310                 IXGBE_CS4227_RESET_COMPLETE);
 311
 312 out:
 313         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 314         msec_delay(hw->eeprom.semaphore_delay);
 315 }
 316
 317 /**
 318  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 319  * @hw: pointer to hardware structure
 320  **/
 321 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 322 {
 323         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 324
 325         if (hw->bus.lan_id) {
 326                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 327                 esdp |= IXGBE_ESDP_SDP1_DIR;
 328         }
 329         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 330         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 331         IXGBE_WRITE_FLUSH(hw);
 332 }
 333
 334 /**
 335  * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
 336  * @hw: pointer to hardware structure
 337  * @reg_addr: 32 bit address of PHY register to read
 338  * @dev_type: always unused
 339  * @phy_data: Pointer to read data from PHY register
 340  */
 341 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 342                                      u32 dev_type, u16 *phy_data)
 343 {
 344         u32 i, data, command;
 345         UNREFERENCED_1PARAMETER(dev_type);
 346
 347         /* Setup and write the read command */
 348         command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 349                   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 350                   IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
 351                   IXGBE_MSCA_MDI_COMMAND;
 352
 353         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 354
 355         /* Check every 10 usec to see if the access completed.
 356          * The MDI Command bit will clear when the operation is
 357          * complete
 358          */
 359         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 360                 usec_delay(10);
 361
 362                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 363                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 364                         break;
 365         }
 366
 367         if (command & IXGBE_MSCA_MDI_COMMAND) {
 368                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 369                               "PHY read command did not complete.\n");
 370                 return IXGBE_ERR_PHY;
 371         }
 372
 373         /* Read operation is complete.  Get the data from MSRWD */
 374         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 375         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 376         *phy_data = (u16)data;
 377
 378         return IXGBE_SUCCESS;
 379 }
 380
 381 /**
 382  * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
 383  * @hw: pointer to hardware structure
 384  * @reg_addr: 32 bit PHY register to write
 385  * @dev_type: always unused
 386  * @phy_data: Data to write to the PHY register
 387  */
 388 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 389                                       u32 dev_type, u16 phy_data)
 390 {
 391         u32 i, command;
 392         UNREFERENCED_1PARAMETER(dev_type);
 393
 394         /* Put the data in the MDI single read and write data register*/
 395         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 396
 397         /* Setup and write the write command */
 398         command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 399                   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 400                   IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
 401                   IXGBE_MSCA_MDI_COMMAND;
 402
 403         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 404
 405         /* Check every 10 usec to see if the access completed.
 406          * The MDI Command bit will clear when the operation is
 407          * complete
 408          */
 409         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 410                 usec_delay(10);
 411
 412                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 413                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 414                         break;
 415         }
 416
 417         if (command & IXGBE_MSCA_MDI_COMMAND) {
 418                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 419                               "PHY write cmd didn't complete\n");
 420                 return IXGBE_ERR_PHY;
 421         }
 422
 423         return IXGBE_SUCCESS;
 424 }
 425
 426 /**
 427  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 428  * @hw: pointer to hardware structure
 429  *
 430  * Returns error code
 431  */
 432 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 433 {
 434         hw->mac.ops.set_lan_id(hw);
 435
 436         ixgbe_read_mng_if_sel_x550em(hw);
 437
 438         switch (hw->device_id) {
 439         case IXGBE_DEV_ID_X550EM_A_SFP:
 440                 return ixgbe_identify_module_generic(hw);
 441         case IXGBE_DEV_ID_X550EM_X_SFP:
 442                 /* set up for CS4227 usage */
 443                 ixgbe_setup_mux_ctl(hw);
 444                 ixgbe_check_cs4227(hw);
 445                 /* Fallthrough */
 446
 447         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 448                 return ixgbe_identify_module_generic(hw);
 449                 break;
 450         case IXGBE_DEV_ID_X550EM_X_KX4:
 451                 hw->phy.type = ixgbe_phy_x550em_kx4;
 452                 break;
 453         case IXGBE_DEV_ID_X550EM_X_KR:
 454         case IXGBE_DEV_ID_X550EM_A_KR:
 455         case IXGBE_DEV_ID_X550EM_A_KR_L:
 456                 hw->phy.type = ixgbe_phy_x550em_kr;
 457                 break;
 458         case IXGBE_DEV_ID_X550EM_A_10G_T:
 459         case IXGBE_DEV_ID_X550EM_X_1G_T:
 460         case IXGBE_DEV_ID_X550EM_X_10G_T:
 461                 return ixgbe_identify_phy_generic(hw);
 462         case IXGBE_DEV_ID_X550EM_A_1G_T:
 463         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 464                 hw->phy.type = ixgbe_phy_fw;
 465                 hw->phy.ops.read_reg = NULL;
 466                 hw->phy.ops.write_reg = NULL;
 467                 if (hw->bus.lan_id)
 468                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 469                 else
 470                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 471                 break;
 472         default:
 473                 break;
 474         }
 475         return IXGBE_SUCCESS;
 476 }
 477
 478 /**
 479  * ixgbe_fw_phy_activity - Perform an activity on a PHY
 480  * @hw: pointer to hardware structure
 481  * @activity: activity to perform
 482  * @data: Pointer to 4 32-bit words of data
 483  */
 484 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,
 485                           u32 (*data)[FW_PHY_ACT_DATA_COUNT])
 486 {
 487         union {
 488                 struct ixgbe_hic_phy_activity_req cmd;
 489                 struct ixgbe_hic_phy_activity_resp rsp;
 490         } hic;
 491         u16 retries = FW_PHY_ACT_RETRIES;
 492         s32 rc;
 493         u16 i;
 494
 495         do {
 496                 memset(&hic, 0, sizeof(hic));
 497                 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD;
 498                 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN;
 499                 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 500                 hic.cmd.port_number = hw->bus.lan_id;
 501                 hic.cmd.activity_id = IXGBE_CPU_TO_LE16(activity);
 502                 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
 503                         hic.cmd.data[i] = IXGBE_CPU_TO_BE32((*data)[i]);
 504
 505                 rc = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
 506                                                   sizeof(hic.cmd),
 507                                                   IXGBE_HI_COMMAND_TIMEOUT,
 508                                                   true);
 509                 if (rc != IXGBE_SUCCESS)
 510                         return rc;
 511                 if (hic.rsp.hdr.cmd_or_resp.ret_status ==
 512                     FW_CEM_RESP_STATUS_SUCCESS) {
 513                         for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
 514                                 (*data)[i] = IXGBE_BE32_TO_CPU(hic.rsp.data[i]);
 515                         return IXGBE_SUCCESS;
 516                 }
 517                 usec_delay(20);
 518                 --retries;
 519         } while (retries > 0);
 520
 521         return IXGBE_ERR_HOST_INTERFACE_COMMAND;
 522 }
 523
 524 static const struct {
 525         u16 fw_speed;
 526         ixgbe_link_speed phy_speed;
 527 } ixgbe_fw_map[] = {
 528         { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL },
 529         { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL },
 530         { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL },
 531         { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL },
 532         { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL },
 533         { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL },
 534 };
 535
 536 /**
 537  * ixgbe_get_phy_id_fw - Get the phy ID via firmware command
 538  * @hw: pointer to hardware structure
 539  *
 540  * Returns error code
 541  */
 542 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw)
 543 {
 544         u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
 545         u16 phy_speeds;
 546         u16 phy_id_lo;
 547         s32 rc;
 548         u16 i;
 549
 550         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info);
 551         if (rc)
 552                 return rc;
 553
 554         hw->phy.speeds_supported = 0;
 555         phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK;
 556         for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
 557                 if (phy_speeds & ixgbe_fw_map[i].fw_speed)
 558                         hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed;
 559         }
 560         if (!hw->phy.autoneg_advertised)
 561                 hw->phy.autoneg_advertised = hw->phy.speeds_supported;
 562
 563         hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK;
 564         phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK;
 565         hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK;
 566         hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK;
 567         if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK)
 568                 return IXGBE_ERR_PHY_ADDR_INVALID;
 569         return IXGBE_SUCCESS;
 570 }
 571
 572 /**
 573  * ixgbe_identify_phy_fw - Get PHY type based on firmware command
 574  * @hw: pointer to hardware structure
 575  *
 576  * Returns error code
 577  */
 578 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw)
 579 {
 580         if (hw->bus.lan_id)
 581                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 582         else
 583                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 584
 585         hw->phy.type = ixgbe_phy_fw;
 586         hw->phy.ops.read_reg = NULL;
 587         hw->phy.ops.write_reg = NULL;
 588         return ixgbe_get_phy_id_fw(hw);
 589 }
 590
 591 /**
 592  * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY
 593  * @hw: pointer to hardware structure
 594  *
 595  * Returns error code
 596  */
 597 s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw)
 598 {
 599         u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
 600
 601         setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF;
 602         return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup);
 603 }
 604
 605 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 606                                      u32 device_type, u16 *phy_data)
 607 {
 608         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 609         return IXGBE_NOT_IMPLEMENTED;
 610 }
 611
 612 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 613                                       u32 device_type, u16 phy_data)
 614 {
 615         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 616         return IXGBE_NOT_IMPLEMENTED;
 617 }
 618
 619 /**
 620  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 621  * @hw: pointer to the hardware structure
 622  * @addr: I2C bus address to read from
 623  * @reg: I2C device register to read from
 624  * @val: pointer to location to receive read value
 625  *
 626  * Returns an error code on error.
 627  **/
 628 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 629                                            u16 reg, u16 *val)
 630 {
 631         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 632 }
 633
 634 /**
 635  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 636  * @hw: pointer to the hardware structure
 637  * @addr: I2C bus address to read from
 638  * @reg: I2C device register to read from
 639  * @val: pointer to location to receive read value
 640  *
 641  * Returns an error code on error.
 642  **/
 643 STATIC s32
 644 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 645                                          u16 reg, u16 *val)
 646 {
 647         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 648 }
 649
 650 /**
 651  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 652  * @hw: pointer to the hardware structure
 653  * @addr: I2C bus address to write to
 654  * @reg: I2C device register to write to
 655  * @val: value to write
 656  *
 657  * Returns an error code on error.
 658  **/
 659 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 660                                             u8 addr, u16 reg, u16 val)
 661 {
 662         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 663 }
 664
 665 /**
 666  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 667  * @hw: pointer to the hardware structure
 668  * @addr: I2C bus address to write to
 669  * @reg: I2C device register to write to
 670  * @val: value to write
 671  *
 672  * Returns an error code on error.
 673  **/
 674 STATIC s32
 675 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 676                                           u8 addr, u16 reg, u16 val)
 677 {
 678         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 679 }
 680
 681 /**
 682 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 683 *  @hw: pointer to hardware structure
 684 *
 685 *  Initialize the function pointers and for MAC type X550EM.
 686 *  Does not touch the hardware.
 687 **/
 688 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 689 {
 690         struct ixgbe_mac_info *mac = &hw->mac;
 691         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 692         struct ixgbe_phy_info *phy = &hw->phy;
 693         s32 ret_val;
 694
 695         DEBUGFUNC("ixgbe_init_ops_X550EM");
 696
 697         /* Similar to X550 so start there. */
 698         ret_val = ixgbe_init_ops_X550(hw);
 699
 700         /* Since this function eventually calls
 701          * ixgbe_init_ops_540 by design, we are setting
 702          * the pointers to NULL explicitly here to overwrite
 703          * the values being set in the x540 function.
 704          */
 705         /* Thermal sensor not supported in x550EM */
 706         mac->ops.get_thermal_sensor_data = NULL;
 707         mac->ops.init_thermal_sensor_thresh = NULL;
 708         mac->thermal_sensor_enabled = false;
 709
 710         /* FCOE not supported in x550EM */
 711         mac->ops.get_san_mac_addr = NULL;
 712         mac->ops.set_san_mac_addr = NULL;
 713         mac->ops.get_wwn_prefix = NULL;
 714         mac->ops.get_fcoe_boot_status = NULL;
 715
 716         /* IPsec not supported in x550EM */
 717         mac->ops.disable_sec_rx_path = NULL;
 718         mac->ops.enable_sec_rx_path = NULL;
 719
 720         /* AUTOC register is not present in x550EM. */
 721         mac->ops.prot_autoc_read = NULL;
 722         mac->ops.prot_autoc_write = NULL;
 723
 724         /* X550EM bus type is internal*/
 725         hw->bus.type = ixgbe_bus_type_internal;
 726         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 727
 728
 729         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 730         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 731         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 732         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 733         mac->ops.get_supported_physical_layer =
 734                                     ixgbe_get_supported_physical_layer_X550em;
 735
 736         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 737                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 738         else
 739                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 740
 741         /* PHY */
 742         phy->ops.init = ixgbe_init_phy_ops_X550em;
 743         switch (hw->device_id) {
 744         case IXGBE_DEV_ID_X550EM_A_1G_T:
 745         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 746                 mac->ops.setup_fc = NULL;
 747                 phy->ops.identify = ixgbe_identify_phy_fw;
 748                 phy->ops.set_phy_power = NULL;
 749                 phy->ops.get_firmware_version = NULL;
 750                 break;
 751         default:
 752                 phy->ops.identify = ixgbe_identify_phy_x550em;
 753         }
 754
 755         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 756                 phy->ops.set_phy_power = NULL;
 757
 758
 759         /* EEPROM */
 760         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 761         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 762         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 763         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 764         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 765         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 766         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 767         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 768
 769         return ret_val;
 770 }
 771
 772 /**
 773  * ixgbe_setup_fw_link - Setup firmware-controlled PHYs
 774  * @hw: pointer to hardware structure
 775  */
 776 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw)
 777 {
 778         u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
 779         s32 rc;
 780         u16 i;
 781
 782         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
 783                 return 0;
 784
 785         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
 786                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
 787                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
 788                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
 789         }
 790
 791         switch (hw->fc.requested_mode) {
 792         case ixgbe_fc_full:
 793                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX <<
 794                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 795                 break;
 796         case ixgbe_fc_rx_pause:
 797                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX <<
 798                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 799                 break;
 800         case ixgbe_fc_tx_pause:
 801                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX <<
 802                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 803                 break;
 804         default:
 805                 break;
 806         }
 807
 808         for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
 809                 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)
 810                         setup[0] |= ixgbe_fw_map[i].fw_speed;
 811         }
 812         setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN;
 813
 814         if (hw->phy.eee_speeds_advertised)
 815                 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE;
 816
 817         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup);
 818         if (rc)
 819                 return rc;
 820         if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN)
 821                 return IXGBE_ERR_OVERTEMP;
 822         return IXGBE_SUCCESS;
 823 }
 824
 825 /**
 826  * ixgbe_fc_autoneg_fw _ Set up flow control for FW-controlled PHYs
 827  * @hw: pointer to hardware structure
 828  *
 829  *  Called at init time to set up flow control.
 830  */
 831 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw)
 832 {
 833         if (hw->fc.requested_mode == ixgbe_fc_default)
 834                 hw->fc.requested_mode = ixgbe_fc_full;
 835
 836         return ixgbe_setup_fw_link(hw);
 837 }
 838
 839 /**
 840  * ixgbe_setup_eee_fw - Enable/disable EEE support
 841  * @hw: pointer to the HW structure
 842  * @enable_eee: boolean flag to enable EEE
 843  *
 844  * Enable/disable EEE based on enable_eee flag.
 845  * This function controls EEE for firmware-based PHY implementations.
 846  */
 847 static s32 ixgbe_setup_eee_fw(struct ixgbe_hw *hw, bool enable_eee)
 848 {
 849         if (!!hw->phy.eee_speeds_advertised == enable_eee)
 850                 return IXGBE_SUCCESS;
 851         if (enable_eee)
 852                 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
 853         else
 854                 hw->phy.eee_speeds_advertised = 0;
 855         return hw->phy.ops.setup_link(hw);
 856 }
 857
 858 /**
 859 *  ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
 860 *  @hw: pointer to hardware structure
 861 *
 862 *  Initialize the function pointers and for MAC type X550EM_a.
 863 *  Does not touch the hardware.
 864 **/
 865 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
 866 {
 867         struct ixgbe_mac_info *mac = &hw->mac;
 868         s32 ret_val;
 869
 870         DEBUGFUNC("ixgbe_init_ops_X550EM_a");
 871
 872         /* Start with generic X550EM init */
 873         ret_val = ixgbe_init_ops_X550EM(hw);
 874
 875         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
 876             hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) {
 877                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 878                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 879         } else {
 880                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
 881                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
 882         }
 883         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
 884         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
 885
 886         switch (mac->ops.get_media_type(hw)) {
 887         case ixgbe_media_type_fiber:
 888                 mac->ops.setup_fc = NULL;
 889                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
 890                 break;
 891         case ixgbe_media_type_backplane:
 892                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
 893                 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
 894                 break;
 895         default:
 896                 break;
 897         }
 898
 899         if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T) ||
 900                 (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)) {
 901                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
 902                 mac->ops.setup_fc = ixgbe_fc_autoneg_fw;
 903         }
 904
 905         switch (hw->device_id) {
 906         case IXGBE_DEV_ID_X550EM_A_KR:
 907         case IXGBE_DEV_ID_X550EM_A_KR_L:
 908                 mac->ops.setup_eee = ixgbe_setup_eee_fw;
 909                 break;
 910         default:
 911                 mac->ops.setup_eee = NULL;
 912         }
 913
 914         return ret_val;
 915 }
 916
 917 /**
 918 *  ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
 919 *  @hw: pointer to hardware structure
 920 *
 921 *  Initialize the function pointers and for MAC type X550EM_x.
 922 *  Does not touch the hardware.
 923 **/
 924 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
 925 {
 926         struct ixgbe_mac_info *mac = &hw->mac;
 927         struct ixgbe_link_info *link = &hw->link;
 928         s32 ret_val;
 929
 930         DEBUGFUNC("ixgbe_init_ops_X550EM_x");
 931
 932         /* Start with generic X550EM init */
 933         ret_val = ixgbe_init_ops_X550EM(hw);
 934
 935         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 936         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 937         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 938         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 939         link->ops.read_link = ixgbe_read_i2c_combined_generic;
 940         link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
 941         link->ops.write_link = ixgbe_write_i2c_combined_generic;
 942         link->ops.write_link_unlocked =
 943                                       ixgbe_write_i2c_combined_generic_unlocked;
 944         link->addr = IXGBE_CS4227;
 945
 946         return ret_val;
 947 }
 948
 949 /**
 950  *  ixgbe_dmac_config_X550
 951  *  @hw: pointer to hardware structure
 952  *
 953  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 954  *  When disabling dmac, dmac enable dmac bit is cleared.
 955  **/
 956 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 957 {
 958         u32 reg, high_pri_tc;
 959
 960         DEBUGFUNC("ixgbe_dmac_config_X550");
 961
 962         /* Disable DMA coalescing before configuring */
 963         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 964         reg &= ~IXGBE_DMACR_DMAC_EN;
 965         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 966
 967         /* Disable DMA Coalescing if the watchdog timer is 0 */
 968         if (!hw->mac.dmac_config.watchdog_timer)
 969                 goto out;
 970
 971         ixgbe_dmac_config_tcs_X550(hw);
 972
 973         /* Configure DMA Coalescing Control Register */
 974         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 975
 976         /* Set the watchdog timer in units of 40.96 usec */
 977         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 978         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 979
 980         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 981         /* If fcoe is enabled, set high priority traffic class */
 982         if (hw->mac.dmac_config.fcoe_en) {
 983                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 984                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 985                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 986         }
 987         reg |= IXGBE_DMACR_EN_MNG_IND;
 988
 989         /* Enable DMA coalescing after configuration */
 990         reg |= IXGBE_DMACR_DMAC_EN;
 991         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 992
 993 out:
 994         return IXGBE_SUCCESS;
 995 }
 996
 997 /**
 998  *  ixgbe_dmac_config_tcs_X550
 999  *  @hw: pointer to hardware structure
1000  *
1001  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
1002  *  be cleared before configuring.
1003  **/
1004 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
1005 {
1006         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
1007
1008         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
1009
1010         /* Configure DMA coalescing enabled */
1011         switch (hw->mac.dmac_config.link_speed) {
1012         case IXGBE_LINK_SPEED_10_FULL:
1013         case IXGBE_LINK_SPEED_100_FULL:
1014                 pb_headroom = IXGBE_DMACRXT_100M;
1015                 break;
1016         case IXGBE_LINK_SPEED_1GB_FULL:
1017                 pb_headroom = IXGBE_DMACRXT_1G;
1018                 break;
1019         default:
1020                 pb_headroom = IXGBE_DMACRXT_10G;
1021                 break;
1022         }
1023
1024         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
1025                              IXGBE_MHADD_MFS_SHIFT) / 1024);
1026
1027         /* Set the per Rx packet buffer receive threshold */
1028         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
1029                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
1030                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
1031
1032                 if (tc < hw->mac.dmac_config.num_tcs) {
1033                         /* Get Rx PB size */
1034                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
1035                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
1036                                 IXGBE_RXPBSIZE_SHIFT;
1037
1038                         /* Calculate receive buffer threshold in kilobytes */
1039                         if (rx_pb_size > pb_headroom)
1040                                 rx_pb_size = rx_pb_size - pb_headroom;
1041                         else
1042                                 rx_pb_size = 0;
1043
1044                         /* Minimum of MFS shall be set for DMCTH */
1045                         reg |= (rx_pb_size > maxframe_size_kb) ?
1046                                 rx_pb_size : maxframe_size_kb;
1047                 }
1048                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
1049         }
1050         return IXGBE_SUCCESS;
1051 }
1052
1053 /**
1054  *  ixgbe_dmac_update_tcs_X550
1055  *  @hw: pointer to hardware structure
1056  *
1057  *  Disables dmac, updates per TC settings, and then enables dmac.
1058  **/
1059 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
1060 {
1061         u32 reg;
1062
1063         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
1064
1065         /* Disable DMA coalescing before configuring */
1066         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
1067         reg &= ~IXGBE_DMACR_DMAC_EN;
1068         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
1069
1070         ixgbe_dmac_config_tcs_X550(hw);
1071
1072         /* Enable DMA coalescing after configuration */
1073         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
1074         reg |= IXGBE_DMACR_DMAC_EN;
1075         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
1076
1077         return IXGBE_SUCCESS;
1078 }
1079
1080 /**
1081  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
1082  *  @hw: pointer to hardware structure
1083  *
1084  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
1085  *  ixgbe_hw struct in order to set up EEPROM access.
1086  **/
1087 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
1088 {
1089         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1090         u32 eec;
1091         u16 eeprom_size;
1092
1093         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
1094
1095         if (eeprom->type == ixgbe_eeprom_uninitialized) {
1096                 eeprom->semaphore_delay = 10;
1097                 eeprom->type = ixgbe_flash;
1098
1099                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1100                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1101                                     IXGBE_EEC_SIZE_SHIFT);
1102                 eeprom->word_size = 1 << (eeprom_size +
1103                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
1104
1105                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
1106                           eeprom->type, eeprom->word_size);
1107         }
1108
1109         return IXGBE_SUCCESS;
1110 }
1111
1112 /**
1113  * ixgbe_enable_eee_x550 - Enable EEE support
1114  * @hw: pointer to hardware structure
1115  */
1116 STATIC s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
1117 {
1118         u32 link_reg;
1119         s32 status;
1120
1121         switch (hw->device_id) {
1122         case IXGBE_DEV_ID_X550EM_A_KR:
1123         case IXGBE_DEV_ID_X550EM_A_KR_L:
1124                 status = hw->mac.ops.read_iosf_sb_reg(hw,
1125                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1126                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
1127                 if (status != IXGBE_SUCCESS)
1128                         return status;
1129
1130                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
1131                             IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
1132
1133                 /* Don't advertise FEC capability when EEE enabled. */
1134                 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
1135
1136                 status = hw->mac.ops.write_iosf_sb_reg(hw,
1137                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1138                                         IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
1139                 if (status != IXGBE_SUCCESS)
1140                         return status;
1141                 break;
1142         default:
1143                 break;
1144         }
1145
1146         return IXGBE_SUCCESS;
1147 }
1148
1149 /**
1150  * ixgbe_disable_eee_x550 - Disable EEE support
1151  * @hw: pointer to hardware structure
1152  */
1153 STATIC s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
1154 {
1155         u32 link_reg;
1156         s32 status;
1157
1158         switch (hw->device_id) {
1159         case IXGBE_DEV_ID_X550EM_X_KR:
1160         case IXGBE_DEV_ID_X550EM_A_KR:
1161         case IXGBE_DEV_ID_X550EM_A_KR_L:
1162                 status = hw->mac.ops.read_iosf_sb_reg(hw,
1163                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1164                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
1165                 if (status != IXGBE_SUCCESS)
1166                         return status;
1167
1168                 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
1169                               IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
1170
1171                 /* Advertise FEC capability when EEE is disabled. */
1172                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
1173
1174                 status = hw->mac.ops.write_iosf_sb_reg(hw,
1175                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1176                                         IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
1177                 if (status != IXGBE_SUCCESS)
1178                         return status;
1179                 break;
1180         default:
1181                 break;
1182         }
1183
1184         return IXGBE_SUCCESS;
1185 }
1186
1187 /**
1188  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
1189  *  @hw: pointer to the HW structure
1190  *  @enable_eee: boolean flag to enable EEE
1191  *
1192  *  Enable/disable EEE based on enable_eee flag.
1193  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
1194  *  are modified.
1195  *
1196  **/
1197 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
1198 {
1199         s32 status;
1200         u32 eeer;
1201
1202         DEBUGFUNC("ixgbe_setup_eee_X550");
1203
1204         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
1205         /* Enable or disable EEE per flag */
1206         if (enable_eee) {
1207                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1208
1209                 status = ixgbe_enable_eee_x550(hw);
1210                 if (status)
1211                         return status;
1212         } else {
1213                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1214
1215                 status = ixgbe_disable_eee_x550(hw);
1216                 if (status)
1217                         return status;
1218         }
1219         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
1220
1221         return IXGBE_SUCCESS;
1222 }
1223
1224 /**
1225  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1226  * @hw: pointer to hardware structure
1227  * @enable: enable or disable source address pruning
1228  * @pool: Rx pool to set source address pruning for
1229  **/
1230 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1231                                            unsigned int pool)
1232 {
1233         u64 pfflp;
1234
1235         /* max rx pool is 63 */
1236         if (pool > 63)
1237                 return;
1238
1239         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1240         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1241
1242         if (enable)
1243                 pfflp |= (1ULL << pool);
1244         else
1245                 pfflp &= ~(1ULL << pool);
1246
1247         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1248         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1249 }
1250
1251 /**
1252  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1253  *  @hw: pointer to hardware structure
1254  *  @enable: enable or disable switch for Ethertype anti-spoofing
1255  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1256  *
1257  **/
1258 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1259                 bool enable, int vf)
1260 {
1261         int vf_target_reg = vf >> 3;
1262         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1263         u32 pfvfspoof;
1264
1265         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1266
1267         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1268         if (enable)
1269                 pfvfspoof |= (1 << vf_target_shift);
1270         else
1271                 pfvfspoof &= ~(1 << vf_target_shift);
1272
1273         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1274 }
1275
1276 /**
1277  * ixgbe_iosf_wait - Wait for IOSF command completion
1278  * @hw: pointer to hardware structure
1279  * @ctrl: pointer to location to receive final IOSF control value
1280  *
1281  * Returns failing status on timeout
1282  *
1283  * Note: ctrl can be NULL if the IOSF control register value is not needed
1284  **/
1285 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1286 {
1287         u32 i, command = 0;
1288
1289         /* Check every 10 usec to see if the address cycle completed.
1290          * The SB IOSF BUSY bit will clear when the operation is
1291          * complete
1292          */
1293         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1294                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1295                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1296                         break;
1297                 usec_delay(10);
1298         }
1299         if (ctrl)
1300                 *ctrl = command;
1301         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1302                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1303                 return IXGBE_ERR_PHY;
1304         }
1305
1306         return IXGBE_SUCCESS;
1307 }
1308
1309 /**
1310  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register
1311  *  of the IOSF device
1312  *  @hw: pointer to hardware structure
1313  *  @reg_addr: 32 bit PHY register to write
1314  *  @device_type: 3 bit device type
1315  *  @data: Data to write to the register
1316  **/
1317 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1318                             u32 device_type, u32 data)
1319 {
1320         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1321         u32 command, error;
1322         s32 ret;
1323
1324         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1325         if (ret != IXGBE_SUCCESS)
1326                 return ret;
1327
1328         ret = ixgbe_iosf_wait(hw, NULL);
1329         if (ret != IXGBE_SUCCESS)
1330                 goto out;
1331
1332         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1333                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1334
1335         /* Write IOSF control register */
1336         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1337
1338         /* Write IOSF data register */
1339         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1340
1341         ret = ixgbe_iosf_wait(hw, &command);
1342
1343         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1344                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1345                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1346                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1347                               "Failed to write, error %x\n", error);
1348                 ret = IXGBE_ERR_PHY;
1349         }
1350
1351 out:
1352         ixgbe_release_swfw_semaphore(hw, gssr);
1353         return ret;
1354 }
1355
1356 /**
1357  *  ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device
1358  *  @hw: pointer to hardware structure
1359  *  @reg_addr: 32 bit PHY register to write
1360  *  @device_type: 3 bit device type
1361  *  @data: Pointer to read data from the register
1362  **/
1363 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1364                            u32 device_type, u32 *data)
1365 {
1366         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1367         u32 command, error;
1368         s32 ret;
1369
1370         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1371         if (ret != IXGBE_SUCCESS)
1372                 return ret;
1373
1374         ret = ixgbe_iosf_wait(hw, NULL);
1375         if (ret != IXGBE_SUCCESS)
1376                 goto out;
1377
1378         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1379                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1380
1381         /* Write IOSF control register */
1382         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1383
1384         ret = ixgbe_iosf_wait(hw, &command);
1385
1386         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1387                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1388                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1389                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1390                                 "Failed to read, error %x\n", error);
1391                 ret = IXGBE_ERR_PHY;
1392         }
1393
1394         if (ret == IXGBE_SUCCESS)
1395                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1396
1397 out:
1398         ixgbe_release_swfw_semaphore(hw, gssr);
1399         return ret;
1400 }
1401
1402 /**
1403  * ixgbe_get_phy_token - Get the token for shared phy access
1404  * @hw: Pointer to hardware structure
1405  */
1406
1407 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1408 {
1409         struct ixgbe_hic_phy_token_req token_cmd;
1410         s32 status;
1411
1412         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1413         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1414         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1415         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1416         token_cmd.port_number = hw->bus.lan_id;
1417         token_cmd.command_type = FW_PHY_TOKEN_REQ;
1418         token_cmd.pad = 0;
1419         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1420                                               sizeof(token_cmd),
1421                                               IXGBE_HI_COMMAND_TIMEOUT,
1422                                               true);
1423         if (status)
1424                 return status;
1425         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1426                 return IXGBE_SUCCESS;
1427         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1428                 return IXGBE_ERR_FW_RESP_INVALID;
1429
1430         return IXGBE_ERR_TOKEN_RETRY;
1431 }
1432
1433 /**
1434  * ixgbe_put_phy_token - Put the token for shared phy access
1435  * @hw: Pointer to hardware structure
1436  */
1437
1438 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1439 {
1440         struct ixgbe_hic_phy_token_req token_cmd;
1441         s32 status;
1442
1443         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1444         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1445         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1446         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1447         token_cmd.port_number = hw->bus.lan_id;
1448         token_cmd.command_type = FW_PHY_TOKEN_REL;
1449         token_cmd.pad = 0;
1450         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1451                                               sizeof(token_cmd),
1452                                               IXGBE_HI_COMMAND_TIMEOUT,
1453                                               true);
1454         if (status)
1455                 return status;
1456         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1457                 return IXGBE_SUCCESS;
1458
1459         DEBUGOUT("Put PHY Token host interface command failed");
1460         return IXGBE_ERR_FW_RESP_INVALID;
1461 }
1462
1463 /**
1464  *  ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1465  *  of the IOSF device
1466  *  @hw: pointer to hardware structure
1467  *  @reg_addr: 32 bit PHY register to write
1468  *  @device_type: 3 bit device type
1469  *  @data: Data to write to the register
1470  **/
1471 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1472                                   u32 device_type, u32 data)
1473 {
1474         struct ixgbe_hic_internal_phy_req write_cmd;
1475         s32 status;
1476         UNREFERENCED_1PARAMETER(device_type);
1477
1478         memset(&write_cmd, 0, sizeof(write_cmd));
1479         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1480         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1481         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1482         write_cmd.port_number = hw->bus.lan_id;
1483         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1484         write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1485         write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1486
1487         status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1488                                               sizeof(write_cmd),
1489                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1490
1491         return status;
1492 }
1493
1494 /**
1495  *  ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device
1496  *  @hw: pointer to hardware structure
1497  *  @reg_addr: 32 bit PHY register to write
1498  *  @device_type: 3 bit device type
1499  *  @data: Pointer to read data from the register
1500  **/
1501 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1502                                  u32 device_type, u32 *data)
1503 {
1504         union {
1505                 struct ixgbe_hic_internal_phy_req cmd;
1506                 struct ixgbe_hic_internal_phy_resp rsp;
1507         } hic;
1508         s32 status;
1509         UNREFERENCED_1PARAMETER(device_type);
1510
1511         memset(&hic, 0, sizeof(hic));
1512         hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1513         hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1514         hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1515         hic.cmd.port_number = hw->bus.lan_id;
1516         hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1517         hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1518
1519         status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1520                                               sizeof(hic.cmd),
1521                                               IXGBE_HI_COMMAND_TIMEOUT, true);
1522
1523         /* Extract the register value from the response. */
1524         *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1525
1526         return status;
1527 }
1528
1529 /**
1530  *  ixgbe_disable_mdd_X550
1531  *  @hw: pointer to hardware structure
1532  *
1533  *  Disable malicious driver detection
1534  **/
1535 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1536 {
1537         u32 reg;
1538
1539         DEBUGFUNC("ixgbe_disable_mdd_X550");
1540
1541         /* Disable MDD for TX DMA and interrupt */
1542         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1543         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1544         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1545
1546         /* Disable MDD for RX and interrupt */
1547         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1548         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1549         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1550 }
1551
1552 /**
1553  *  ixgbe_enable_mdd_X550
1554  *  @hw: pointer to hardware structure
1555  *
1556  *  Enable malicious driver detection
1557  **/
1558 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1559 {
1560         u32 reg;
1561
1562         DEBUGFUNC("ixgbe_enable_mdd_X550");
1563
1564         /* Enable MDD for TX DMA and interrupt */
1565         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1566         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1567         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1568
1569         /* Enable MDD for RX and interrupt */
1570         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1571         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1572         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1573 }
1574
1575 /**
1576  *  ixgbe_restore_mdd_vf_X550
1577  *  @hw: pointer to hardware structure
1578  *  @vf: vf index
1579  *
1580  *  Restore VF that was disabled during malicious driver detection event
1581  **/
1582 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1583 {
1584         u32 idx, reg, num_qs, start_q, bitmask;
1585
1586         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1587
1588         /* Map VF to queues */
1589         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1590         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1591         case IXGBE_MRQC_VMDQRT8TCEN:
1592                 num_qs = 8;  /* 16 VFs / pools */
1593                 bitmask = 0x000000FF;
1594                 break;
1595         case IXGBE_MRQC_VMDQRSS32EN:
1596         case IXGBE_MRQC_VMDQRT4TCEN:
1597                 num_qs = 4;  /* 32 VFs / pools */
1598                 bitmask = 0x0000000F;
1599                 break;
1600         default:            /* 64 VFs / pools */
1601                 num_qs = 2;
1602                 bitmask = 0x00000003;
1603                 break;
1604         }
1605         start_q = vf * num_qs;
1606
1607         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1608         idx = start_q / 32;
1609         reg = 0;
1610         reg |= (bitmask << (start_q % 32));
1611         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1612         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1613 }
1614
1615 /**
1616  *  ixgbe_mdd_event_X550
1617  *  @hw: pointer to hardware structure
1618  *  @vf_bitmap: vf bitmap of malicious vfs
1619  *
1620  *  Handle malicious driver detection event.
1621  **/
1622 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1623 {
1624         u32 wqbr;
1625         u32 i, j, reg, q, shift, vf, idx;
1626
1627         DEBUGFUNC("ixgbe_mdd_event_X550");
1628
1629         /* figure out pool size for mapping to vf's */
1630         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1631         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1632         case IXGBE_MRQC_VMDQRT8TCEN:
1633                 shift = 3;  /* 16 VFs / pools */
1634                 break;
1635         case IXGBE_MRQC_VMDQRSS32EN:
1636         case IXGBE_MRQC_VMDQRT4TCEN:
1637                 shift = 2;  /* 32 VFs / pools */
1638                 break;
1639         default:
1640                 shift = 1;  /* 64 VFs / pools */
1641                 break;
1642         }
1643
1644         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1645         for (i = 0; i < 4; i++) {
1646                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1647                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1648
1649                 if (!wqbr)
1650                         continue;
1651
1652                 /* Get malicious queue */
1653                 for (j = 0; j < 32 && wqbr; j++) {
1654
1655                         if (!(wqbr & (1 << j)))
1656                                 continue;
1657
1658                         /* Get queue from bitmask */
1659                         q = j + (i * 32);
1660
1661                         /* Map queue to vf */
1662                         vf = (q >> shift);
1663
1664                         /* Set vf bit in vf_bitmap */
1665                         idx = vf / 32;
1666                         vf_bitmap[idx] |= (1 << (vf % 32));
1667                         wqbr &= ~(1 << j);
1668                 }
1669         }
1670 }
1671
1672 /**
1673  *  ixgbe_get_media_type_X550em - Get media type
1674  *  @hw: pointer to hardware structure
1675  *
1676  *  Returns the media type (fiber, copper, backplane)
1677  */
1678 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1679 {
1680         enum ixgbe_media_type media_type;
1681
1682         DEBUGFUNC("ixgbe_get_media_type_X550em");
1683
1684         /* Detect if there is a copper PHY attached. */
1685         switch (hw->device_id) {
1686         case IXGBE_DEV_ID_X550EM_X_KR:
1687         case IXGBE_DEV_ID_X550EM_X_KX4:
1688         case IXGBE_DEV_ID_X550EM_A_KR:
1689         case IXGBE_DEV_ID_X550EM_A_KR_L:
1690                 media_type = ixgbe_media_type_backplane;
1691                 break;
1692         case IXGBE_DEV_ID_X550EM_X_SFP:
1693         case IXGBE_DEV_ID_X550EM_A_SFP:
1694         case IXGBE_DEV_ID_X550EM_A_SFP_N:
1695         case IXGBE_DEV_ID_X550EM_A_QSFP:
1696         case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1697                 media_type = ixgbe_media_type_fiber;
1698                 break;
1699         case IXGBE_DEV_ID_X550EM_X_1G_T:
1700         case IXGBE_DEV_ID_X550EM_X_10G_T:
1701         case IXGBE_DEV_ID_X550EM_A_10G_T:
1702                 media_type = ixgbe_media_type_copper;
1703                 break;
1704         case IXGBE_DEV_ID_X550EM_A_SGMII:
1705         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1706                 media_type = ixgbe_media_type_backplane;
1707                 hw->phy.type = ixgbe_phy_sgmii;
1708                 break;
1709         case IXGBE_DEV_ID_X550EM_A_1G_T:
1710         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1711                 media_type = ixgbe_media_type_copper;
1712                 break;
1713         default:
1714                 media_type = ixgbe_media_type_unknown;
1715                 break;
1716         }
1717         return media_type;
1718 }
1719
1720 /**
1721  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1722  *  @hw: pointer to hardware structure
1723  *  @linear: true if SFP module is linear
1724  */
1725 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1726 {
1727         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1728
1729         switch (hw->phy.sfp_type) {
1730         case ixgbe_sfp_type_not_present:
1731                 return IXGBE_ERR_SFP_NOT_PRESENT;
1732         case ixgbe_sfp_type_da_cu_core0:
1733         case ixgbe_sfp_type_da_cu_core1:
1734                 *linear = true;
1735                 break;
1736         case ixgbe_sfp_type_srlr_core0:
1737         case ixgbe_sfp_type_srlr_core1:
1738         case ixgbe_sfp_type_da_act_lmt_core0:
1739         case ixgbe_sfp_type_da_act_lmt_core1:
1740         case ixgbe_sfp_type_1g_sx_core0:
1741         case ixgbe_sfp_type_1g_sx_core1:
1742         case ixgbe_sfp_type_1g_lx_core0:
1743         case ixgbe_sfp_type_1g_lx_core1:
1744                 *linear = false;
1745                 break;
1746         case ixgbe_sfp_type_unknown:
1747         case ixgbe_sfp_type_1g_cu_core0:
1748         case ixgbe_sfp_type_1g_cu_core1:
1749         default:
1750                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1751         }
1752
1753         return IXGBE_SUCCESS;
1754 }
1755
1756 /**
1757  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1758  *  @hw: pointer to hardware structure
1759  *
1760  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1761  **/
1762 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1763 {
1764         s32 status;
1765         bool linear;
1766
1767         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1768
1769         status = ixgbe_identify_module_generic(hw);
1770
1771         if (status != IXGBE_SUCCESS)
1772                 return status;
1773
1774         /* Check if SFP module is supported */
1775         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1776
1777         return status;
1778 }
1779
1780 /**
1781  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1782  *  @hw: pointer to hardware structure
1783  */
1784 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1785 {
1786         s32 status;
1787         bool linear;
1788
1789         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1790
1791         /* Check if SFP module is supported */
1792         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1793
1794         if (status != IXGBE_SUCCESS)
1795                 return status;
1796
1797         ixgbe_init_mac_link_ops_X550em(hw);
1798         hw->phy.ops.reset = NULL;
1799
1800         return IXGBE_SUCCESS;
1801 }
1802
1803 /**
1804 *  ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1805 *  internal PHY
1806 *  @hw: pointer to hardware structure
1807 **/
1808 STATIC s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1809 {
1810         s32 status;
1811         u32 link_ctrl;
1812
1813         /* Restart auto-negotiation. */
1814         status = hw->mac.ops.read_iosf_sb_reg(hw,
1815                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1816                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1817
1818         if (status) {
1819                 DEBUGOUT("Auto-negotiation did not complete\n");
1820                 return status;
1821         }
1822
1823         link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1824         status = hw->mac.ops.write_iosf_sb_reg(hw,
1825                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1826                                         IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1827
1828         if (hw->mac.type == ixgbe_mac_X550EM_a) {
1829                 u32 flx_mask_st20;
1830
1831                 /* Indicate to FW that AN restart has been asserted */
1832                 status = hw->mac.ops.read_iosf_sb_reg(hw,
1833                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1834                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1835
1836                 if (status) {
1837                         DEBUGOUT("Auto-negotiation did not complete\n");
1838                         return status;
1839                 }
1840
1841                 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1842                 status = hw->mac.ops.write_iosf_sb_reg(hw,
1843                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1844                                 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1845         }
1846
1847         return status;
1848 }
1849
1850 /**
1851  * ixgbe_setup_sgmii - Set up link for sgmii
1852  * @hw: pointer to hardware structure
1853  */
1854 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1855                              bool autoneg_wait)
1856 {
1857         struct ixgbe_mac_info *mac = &hw->mac;
1858         u32 lval, sval, flx_val;
1859         s32 rc;
1860
1861         rc = mac->ops.read_iosf_sb_reg(hw,
1862                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1863                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1864         if (rc)
1865                 return rc;
1866
1867         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1868         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1869         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1870         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1871         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1872         rc = mac->ops.write_iosf_sb_reg(hw,
1873                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1874                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1875         if (rc)
1876                 return rc;
1877
1878         rc = mac->ops.read_iosf_sb_reg(hw,
1879                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1880                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1881         if (rc)
1882                 return rc;
1883
1884         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1885         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1886         rc = mac->ops.write_iosf_sb_reg(hw,
1887                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1888                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1889         if (rc)
1890                 return rc;
1891
1892         rc = mac->ops.read_iosf_sb_reg(hw,
1893                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1894                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1895         if (rc)
1896                 return rc;
1897
1898         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1899         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1900         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1901         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1902         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1903
1904         rc = mac->ops.write_iosf_sb_reg(hw,
1905                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1906                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1907         if (rc)
1908                 return rc;
1909
1910         rc = ixgbe_restart_an_internal_phy_x550em(hw);
1911         if (rc)
1912                 return rc;
1913
1914         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1915 }
1916
1917 /**
1918  * ixgbe_setup_sgmii_fw - Set up link for sgmii with firmware-controlled PHYs
1919  * @hw: pointer to hardware structure
1920  */
1921 STATIC s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1922                                 bool autoneg_wait)
1923 {
1924         struct ixgbe_mac_info *mac = &hw->mac;
1925         u32 lval, sval, flx_val;
1926         s32 rc;
1927
1928         rc = mac->ops.read_iosf_sb_reg(hw,
1929                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1930                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1931         if (rc)
1932                 return rc;
1933
1934         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1935         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1936         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1937         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1938         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1939         rc = mac->ops.write_iosf_sb_reg(hw,
1940                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1941                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1942         if (rc)
1943                 return rc;
1944
1945         rc = mac->ops.read_iosf_sb_reg(hw,
1946                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1947                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1948         if (rc)
1949                 return rc;
1950
1951         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1952         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1953         rc = mac->ops.write_iosf_sb_reg(hw,
1954                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1955                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1956         if (rc)
1957                 return rc;
1958
1959         rc = mac->ops.write_iosf_sb_reg(hw,
1960                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1961                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1962         if (rc)
1963                 return rc;
1964
1965         rc = mac->ops.read_iosf_sb_reg(hw,
1966                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1967                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1968         if (rc)
1969                 return rc;
1970
1971         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1972         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
1973         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1974         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1975         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1976
1977         rc = mac->ops.write_iosf_sb_reg(hw,
1978                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1979                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1980         if (rc)
1981                 return rc;
1982
1983         rc = ixgbe_restart_an_internal_phy_x550em(hw);
1984
1985         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1986 }
1987
1988 /**
1989  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1990  *  @hw: pointer to hardware structure
1991  */
1992 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1993 {
1994         struct ixgbe_mac_info *mac = &hw->mac;
1995
1996         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1997
1998         switch (hw->mac.ops.get_media_type(hw)) {
1999         case ixgbe_media_type_fiber:
2000                 /* CS4227 does not support autoneg, so disable the laser control
2001                  * functions for SFP+ fiber
2002                  */
2003                 mac->ops.disable_tx_laser = NULL;
2004                 mac->ops.enable_tx_laser = NULL;
2005                 mac->ops.flap_tx_laser = NULL;
2006                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
2007                 mac->ops.set_rate_select_speed =
2008                                         ixgbe_set_soft_rate_select_speed;
2009
2010                 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
2011                     (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
2012                         mac->ops.setup_mac_link =
2013                                                 ixgbe_setup_mac_link_sfp_x550a;
2014                 else
2015                         mac->ops.setup_mac_link =
2016                                                 ixgbe_setup_mac_link_sfp_x550em;
2017                 break;
2018         case ixgbe_media_type_copper:
2019                 if (hw->mac.type == ixgbe_mac_X550EM_a) {
2020                         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2021                             hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
2022                                 mac->ops.setup_link = ixgbe_setup_sgmii_fw;
2023                                 mac->ops.check_link =
2024                                                    ixgbe_check_mac_link_generic;
2025                         } else {
2026                                 mac->ops.setup_link =
2027                                                   ixgbe_setup_mac_link_t_X550em;
2028                         }
2029                 } else {
2030                         mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
2031                         mac->ops.check_link = ixgbe_check_link_t_X550em;
2032                 }
2033                 break;
2034         case ixgbe_media_type_backplane:
2035                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
2036                     hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
2037                         mac->ops.setup_link = ixgbe_setup_sgmii;
2038                 break;
2039         default:
2040                 break;
2041         }
2042 }
2043
2044 /**
2045  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
2046  *  @hw: pointer to hardware structure
2047  *  @speed: pointer to link speed
2048  *  @autoneg: true when autoneg or autotry is enabled
2049  */
2050 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
2051                                        ixgbe_link_speed *speed,
2052                                        bool *autoneg)
2053 {
2054         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
2055
2056
2057         if (hw->phy.type == ixgbe_phy_fw) {
2058                 *autoneg = true;
2059                 *speed = hw->phy.speeds_supported;
2060                 return 0;
2061         }
2062
2063         /* SFP */
2064         if (hw->phy.media_type == ixgbe_media_type_fiber) {
2065
2066                 /* CS4227 SFP must not enable auto-negotiation */
2067                 *autoneg = false;
2068
2069                 /* Check if 1G SFP module. */
2070                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
2071                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
2072                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
2073                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
2074                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
2075                         return IXGBE_SUCCESS;
2076                 }
2077
2078                 /* Link capabilities are based on SFP */
2079                 if (hw->phy.multispeed_fiber)
2080                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
2081                                  IXGBE_LINK_SPEED_1GB_FULL;
2082                 else
2083                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
2084         } else {
2085                 switch (hw->phy.type) {
2086                 case ixgbe_phy_sgmii:
2087                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
2088                         break;
2089                 case ixgbe_phy_x550em_kr:
2090                         if (hw->mac.type == ixgbe_mac_X550EM_a) {
2091                                 /* check different backplane modes */
2092                                 if (hw->phy.nw_mng_if_sel &
2093                                            IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
2094                                         *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
2095                                         break;
2096                                 } else if (hw->device_id ==
2097                                                    IXGBE_DEV_ID_X550EM_A_KR_L) {
2098                                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
2099                                         break;
2100                                 }
2101                         }
2102                         /* fall through */
2103                 default:
2104                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
2105                                  IXGBE_LINK_SPEED_1GB_FULL;
2106                         break;
2107                 }
2108                 *autoneg = true;
2109         }
2110
2111         return IXGBE_SUCCESS;
2112 }
2113
2114 /**
2115  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
2116  * @hw: pointer to hardware structure
2117  * @lsc: pointer to boolean flag which indicates whether external Base T
2118  *       PHY interrupt is lsc
2119  *
2120  * Determime if external Base T PHY interrupt cause is high temperature
2121  * failure alarm or link status change.
2122  *
2123  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2124  * failure alarm, else return PHY access status.
2125  */
2126 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
2127 {
2128         u32 status;
2129         u16 reg;
2130
2131         *lsc = false;
2132
2133         /* Vendor alarm triggered */
2134         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2135                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2136                                       &reg);
2137
2138         if (status != IXGBE_SUCCESS ||
2139             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
2140                 return status;
2141
2142         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
2143         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
2144                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2145                                       &reg);
2146
2147         if (status != IXGBE_SUCCESS ||
2148             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2149             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
2150                 return status;
2151
2152         /* Global alarm triggered */
2153         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
2154                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2155                                       &reg);
2156
2157         if (status != IXGBE_SUCCESS)
2158                 return status;
2159
2160         /* If high temperature failure, then return over temp error and exit */
2161         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
2162                 /* power down the PHY in case the PHY FW didn't already */
2163                 ixgbe_set_copper_phy_power(hw, false);
2164                 return IXGBE_ERR_OVERTEMP;
2165         } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
2166                 /*  device fault alarm triggered */
2167                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
2168                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2169                                           &reg);
2170
2171                 if (status != IXGBE_SUCCESS)
2172                         return status;
2173
2174                 /* if device fault was due to high temp alarm handle and exit */
2175                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
2176                         /* power down the PHY in case the PHY FW didn't */
2177                         ixgbe_set_copper_phy_power(hw, false);
2178                         return IXGBE_ERR_OVERTEMP;
2179                 }
2180         }
2181
2182         /* Vendor alarm 2 triggered */
2183         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2184                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2185
2186         if (status != IXGBE_SUCCESS ||
2187             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
2188                 return status;
2189
2190         /* link connect/disconnect event occurred */
2191         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
2192                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2193
2194         if (status != IXGBE_SUCCESS)
2195                 return status;
2196
2197         /* Indicate LSC */
2198         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2199                 *lsc = true;
2200
2201         return IXGBE_SUCCESS;
2202 }
2203
2204 /**
2205  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2206  * @hw: pointer to hardware structure
2207  *
2208  * Enable link status change and temperature failure alarm for the external
2209  * Base T PHY
2210  *
2211  * Returns PHY access status
2212  */
2213 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2214 {
2215         u32 status;
2216         u16 reg;
2217         bool lsc;
2218
2219         /* Clear interrupt flags */
2220         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2221
2222         /* Enable link status change alarm */
2223
2224         /* Enable the LASI interrupts on X552 devices to receive notifications
2225          * of the link configurations of the external PHY and correspondingly
2226          * support the configuration of the internal iXFI link, since iXFI does
2227          * not support auto-negotiation. This is not required for X553 devices
2228          * having KR support, which performs auto-negotiations and which is used
2229          * as the internal link to the external PHY. Hence adding a check here
2230          * to avoid enabling LASI interrupts for X553 devices.
2231          */
2232         if (hw->mac.type != ixgbe_mac_X550EM_a) {
2233                 status = hw->phy.ops.read_reg(hw,
2234                                         IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2235                                         IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2236
2237                 if (status != IXGBE_SUCCESS)
2238                         return status;
2239
2240                 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2241
2242                 status = hw->phy.ops.write_reg(hw,
2243                                         IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2244                                         IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
2245
2246                 if (status != IXGBE_SUCCESS)
2247                         return status;
2248         }
2249
2250         /* Enable high temperature failure and global fault alarms */
2251         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2252                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2253                                       &reg);
2254
2255         if (status != IXGBE_SUCCESS)
2256                 return status;
2257
2258         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2259                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2260
2261         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2262                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2263                                        reg);
2264
2265         if (status != IXGBE_SUCCESS)
2266                 return status;
2267
2268         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2269         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2270                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2271                                       &reg);
2272
2273         if (status != IXGBE_SUCCESS)
2274                 return status;
2275
2276         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2277                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2278
2279         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2280                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2281                                        reg);
2282
2283         if (status != IXGBE_SUCCESS)
2284                 return status;
2285
2286         /* Enable chip-wide vendor alarm */
2287         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2288                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2289                                       &reg);
2290
2291         if (status != IXGBE_SUCCESS)
2292                 return status;
2293
2294         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2295
2296         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2297                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2298                                        reg);
2299
2300         return status;
2301 }
2302
2303 /**
2304  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2305  *  @hw: pointer to hardware structure
2306  *  @speed: link speed
2307  *
2308  *  Configures the integrated KR PHY.
2309  **/
2310 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2311                                        ixgbe_link_speed speed)
2312 {
2313         s32 status;
2314         u32 reg_val;
2315
2316         status = hw->mac.ops.read_iosf_sb_reg(hw,
2317                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2318                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2319         if (status)
2320                 return status;
2321
2322         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2323         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2324                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2325
2326         /* Advertise 10G support. */
2327         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2328                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2329
2330         /* Advertise 1G support. */
2331         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2332                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2333
2334         status = hw->mac.ops.write_iosf_sb_reg(hw,
2335                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2336                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2337
2338         if (hw->mac.type == ixgbe_mac_X550EM_a) {
2339                 /* Set lane mode  to KR auto negotiation */
2340                 status = hw->mac.ops.read_iosf_sb_reg(hw,
2341                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2342                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2343
2344                 if (status)
2345                         return status;
2346
2347                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2348                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2349                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2350                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2351                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2352
2353                 status = hw->mac.ops.write_iosf_sb_reg(hw,
2354                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2355                                     IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2356         }
2357
2358         return ixgbe_restart_an_internal_phy_x550em(hw);
2359 }
2360
2361 /**
2362  * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs
2363  * @hw: pointer to hardware structure
2364  */
2365 static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw)
2366 {
2367         u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
2368         s32 rc;
2369
2370         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2371                 return IXGBE_SUCCESS;
2372
2373         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store);
2374         if (rc)
2375                 return rc;
2376         memset(store, 0, sizeof(store));
2377
2378         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store);
2379         if (rc)
2380                 return rc;
2381
2382         return ixgbe_setup_fw_link(hw);
2383 }
2384
2385 /**
2386  * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp
2387  * @hw: pointer to hardware structure
2388  */
2389 static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw)
2390 {
2391         u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
2392         s32 rc;
2393
2394         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store);
2395         if (rc)
2396                 return rc;
2397
2398         if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) {
2399                 ixgbe_shutdown_fw_phy(hw);
2400                 return IXGBE_ERR_OVERTEMP;
2401         }
2402         return IXGBE_SUCCESS;
2403 }
2404
2405 /**
2406  *  ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2407  *  @hw: pointer to hardware structure
2408  *
2409  *  Read NW_MNG_IF_SEL register and save field values, and check for valid field
2410  *  values.
2411  **/
2412 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2413 {
2414         /* Save NW management interface connected on board. This is used
2415          * to determine internal PHY mode.
2416          */
2417         hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2418
2419         /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2420          * PHY address. This register field was has only been used for X552.
2421          */
2422         if (hw->mac.type == ixgbe_mac_X550EM_a &&
2423             hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2424                 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2425                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2426                                IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2427         }
2428
2429         return IXGBE_SUCCESS;
2430 }
2431
2432 /**
2433  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2434  *  @hw: pointer to hardware structure
2435  *
2436  *  Initialize any function pointers that were not able to be
2437  *  set during init_shared_code because the PHY/SFP type was
2438  *  not known.  Perform the SFP init if necessary.
2439  */
2440 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2441 {
2442         struct ixgbe_phy_info *phy = &hw->phy;
2443         s32 ret_val;
2444
2445         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2446
2447         hw->mac.ops.set_lan_id(hw);
2448         ixgbe_read_mng_if_sel_x550em(hw);
2449
2450         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2451                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2452                 ixgbe_setup_mux_ctl(hw);
2453                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2454         }
2455
2456         switch (hw->device_id) {
2457         case IXGBE_DEV_ID_X550EM_A_1G_T:
2458         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2459                 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2460                 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2461                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2462                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2463                 phy->ops.check_overtemp = ixgbe_check_overtemp_fw;
2464                 if (hw->bus.lan_id)
2465                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2466                 else
2467                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2468
2469                 break;
2470         case IXGBE_DEV_ID_X550EM_A_10G_T:
2471         case IXGBE_DEV_ID_X550EM_A_SFP:
2472                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2473                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2474                 if (hw->bus.lan_id)
2475                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2476                 else
2477                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2478                 break;
2479         case IXGBE_DEV_ID_X550EM_X_SFP:
2480                 /* set up for CS4227 usage */
2481                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2482                 break;
2483         default:
2484                 break;
2485         }
2486
2487         /* Identify the PHY or SFP module */
2488         ret_val = phy->ops.identify(hw);
2489         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED ||
2490             ret_val == IXGBE_ERR_PHY_ADDR_INVALID)
2491                 return ret_val;
2492
2493         /* Setup function pointers based on detected hardware */
2494         ixgbe_init_mac_link_ops_X550em(hw);
2495         if (phy->sfp_type != ixgbe_sfp_type_unknown)
2496                 phy->ops.reset = NULL;
2497
2498         /* Set functions pointers based on phy type */
2499         switch (hw->phy.type) {
2500         case ixgbe_phy_x550em_kx4:
2501                 phy->ops.setup_link = NULL;
2502                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2503                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2504                 break;
2505         case ixgbe_phy_x550em_kr:
2506                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2507                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2508                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2509                 break;
2510         case ixgbe_phy_x550em_ext_t:
2511                 /* If internal link mode is XFI, then setup iXFI internal link,
2512                  * else setup KR now.
2513                  */
2514                 phy->ops.setup_internal_link =
2515                                               ixgbe_setup_internal_phy_t_x550em;
2516
2517                 /* setup SW LPLU only for first revision of X550EM_x */
2518                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2519                     !(IXGBE_FUSES0_REV_MASK &
2520                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2521                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2522
2523                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2524                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2525                 break;
2526         case ixgbe_phy_sgmii:
2527                 phy->ops.setup_link = NULL;
2528                 break;
2529         case ixgbe_phy_fw:
2530                 phy->ops.setup_link = ixgbe_setup_fw_link;
2531                 phy->ops.reset = ixgbe_reset_phy_fw;
2532                 break;
2533         default:
2534                 break;
2535         }
2536         return ret_val;
2537 }
2538
2539 /**
2540  * ixgbe_set_mdio_speed - Set MDIO clock speed
2541  *  @hw: pointer to hardware structure
2542  */
2543 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2544 {
2545         u32 hlreg0;
2546
2547         switch (hw->device_id) {
2548         case IXGBE_DEV_ID_X550EM_X_10G_T:
2549         case IXGBE_DEV_ID_X550EM_A_SGMII:
2550         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2551         case IXGBE_DEV_ID_X550EM_A_10G_T:
2552         case IXGBE_DEV_ID_X550EM_A_SFP:
2553         case IXGBE_DEV_ID_X550EM_A_QSFP:
2554                 /* Config MDIO clock speed before the first MDIO PHY access */
2555                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2556                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2557                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2558                 break;
2559         case IXGBE_DEV_ID_X550EM_A_1G_T:
2560         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2561                 /* Select fast MDIO clock speed for these devices */
2562                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2563                 hlreg0 |= IXGBE_HLREG0_MDCSPD;
2564                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2565                 break;
2566         default:
2567                 break;
2568         }
2569 }
2570
2571 /**
2572  *  ixgbe_reset_hw_X550em - Perform hardware reset
2573  *  @hw: pointer to hardware structure
2574  *
2575  *  Resets the hardware by resetting the transmit and receive units, masks
2576  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2577  *  reset.
2578  */
2579 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2580 {
2581         ixgbe_link_speed link_speed;
2582         s32 status;
2583         u32 ctrl = 0;
2584         u32 i;
2585         bool link_up = false;
2586
2587         DEBUGFUNC("ixgbe_reset_hw_X550em");
2588
2589         /* Call adapter stop to disable Tx/Rx and clear interrupts */
2590         status = hw->mac.ops.stop_adapter(hw);
2591         if (status != IXGBE_SUCCESS)
2592                 return status;
2593
2594         /* flush pending Tx transactions */
2595         ixgbe_clear_tx_pending(hw);
2596
2597         ixgbe_set_mdio_speed(hw);
2598
2599         /* PHY ops must be identified and initialized prior to reset */
2600         status = hw->phy.ops.init(hw);
2601
2602         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2603                 return status;
2604
2605         /* start the external PHY */
2606         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2607                 status = ixgbe_init_ext_t_x550em(hw);
2608                 if (status)
2609                         return status;
2610         }
2611
2612         /* Setup SFP module if there is one present. */
2613         if (hw->phy.sfp_setup_needed) {
2614                 status = hw->mac.ops.setup_sfp(hw);
2615                 hw->phy.sfp_setup_needed = false;
2616         }
2617
2618         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2619                 return status;
2620
2621         /* Reset PHY */
2622         if (!hw->phy.reset_disable && hw->phy.ops.reset) {
2623                 if (hw->phy.ops.reset(hw) == IXGBE_ERR_OVERTEMP)
2624                         return IXGBE_ERR_OVERTEMP;
2625         }
2626
2627 mac_reset_top:
2628         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2629          * If link reset is used when link is up, it might reset the PHY when
2630          * mng is using it.  If link is down or the flag to force full link
2631          * reset is set, then perform link reset.
2632          */
2633         ctrl = IXGBE_CTRL_LNK_RST;
2634         if (!hw->force_full_reset) {
2635                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2636                 if (link_up)
2637                         ctrl = IXGBE_CTRL_RST;
2638         }
2639
2640         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2641         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2642         IXGBE_WRITE_FLUSH(hw);
2643
2644         /* Poll for reset bit to self-clear meaning reset is complete */
2645         for (i = 0; i < 10; i++) {
2646                 usec_delay(1);
2647                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2648                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2649                         break;
2650         }
2651
2652         if (ctrl & IXGBE_CTRL_RST_MASK) {
2653                 status = IXGBE_ERR_RESET_FAILED;
2654                 DEBUGOUT("Reset polling failed to complete.\n");
2655         }
2656
2657         msec_delay(50);
2658
2659         /* Double resets are required for recovery from certain error
2660          * conditions.  Between resets, it is necessary to stall to
2661          * allow time for any pending HW events to complete.
2662          */
2663         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2664                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2665                 goto mac_reset_top;
2666         }
2667
2668         /* Store the permanent mac address */
2669         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2670
2671         /* Store MAC address from RAR0, clear receive address registers, and
2672          * clear the multicast table.  Also reset num_rar_entries to 128,
2673          * since we modify this value when programming the SAN MAC address.
2674          */
2675         hw->mac.num_rar_entries = 128;
2676         hw->mac.ops.init_rx_addrs(hw);
2677
2678         ixgbe_set_mdio_speed(hw);
2679
2680         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2681                 ixgbe_setup_mux_ctl(hw);
2682
2683         return status;
2684 }
2685
2686 /**
2687  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2688  * @hw: pointer to hardware structure
2689  */
2690 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2691 {
2692         u32 status;
2693         u16 reg;
2694
2695         status = hw->phy.ops.read_reg(hw,
2696                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2697                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2698                                       &reg);
2699
2700         if (status != IXGBE_SUCCESS)
2701                 return status;
2702
2703         /* If PHY FW reset completed bit is set then this is the first
2704          * SW instance after a power on so the PHY FW must be un-stalled.
2705          */
2706         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2707                 status = hw->phy.ops.read_reg(hw,
2708                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2709                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2710                                         &reg);
2711
2712                 if (status != IXGBE_SUCCESS)
2713                         return status;
2714
2715                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2716
2717                 status = hw->phy.ops.write_reg(hw,
2718                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2719                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2720                                         reg);
2721
2722                 if (status != IXGBE_SUCCESS)
2723                         return status;
2724         }
2725
2726         return status;
2727 }
2728
2729 /**
2730  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
2731  *  @hw: pointer to hardware structure
2732  *
2733  *  Configures the integrated KR PHY for X550EM_x.
2734  **/
2735 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2736 {
2737         if (hw->mac.type != ixgbe_mac_X550EM_x)
2738                 return IXGBE_SUCCESS;
2739
2740         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2741 }
2742
2743 /**
2744  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2745  *  @hw: pointer to hardware structure
2746  *
2747  *  Configure the external PHY and the integrated KR PHY for SFP support.
2748  **/
2749 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2750                                     ixgbe_link_speed speed,
2751                                     bool autoneg_wait_to_complete)
2752 {
2753         s32 ret_val;
2754         u16 reg_slice, reg_val;
2755         bool setup_linear = false;
2756         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2757
2758         /* Check if SFP module is supported and linear */
2759         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2760
2761         /* If no SFP module present, then return success. Return success since
2762          * there is no reason to configure CS4227 and SFP not present error is
2763          * not excepted in the setup MAC link flow.
2764          */
2765         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2766                 return IXGBE_SUCCESS;
2767
2768         if (ret_val != IXGBE_SUCCESS)
2769                 return ret_val;
2770
2771         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2772                 /* Configure CS4227 LINE side to 10G SR. */
2773                 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
2774                             (hw->bus.lan_id << 12);
2775                 reg_val = IXGBE_CS4227_SPEED_10G;
2776                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2777                                                   reg_val);
2778
2779                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2780                             (hw->bus.lan_id << 12);
2781                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2782                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2783                                                   reg_val);
2784
2785                 /* Configure CS4227 for HOST connection rate then type. */
2786                 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
2787                             (hw->bus.lan_id << 12);
2788                 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
2789                 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
2790                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2791                                                   reg_val);
2792
2793                 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
2794                             (hw->bus.lan_id << 12);
2795                 if (setup_linear)
2796                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2797                 else
2798                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2799                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2800                                                   reg_val);
2801
2802                 /* Setup XFI internal link. */
2803                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2804         } else {
2805                 /* Configure internal PHY for KR/KX. */
2806                 ixgbe_setup_kr_speed_x550em(hw, speed);
2807
2808                 /* Configure CS4227 LINE side to proper mode. */
2809                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2810                             (hw->bus.lan_id << 12);
2811                 if (setup_linear)
2812                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2813                 else
2814                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2815                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2816                                                   reg_val);
2817         }
2818         return ret_val;
2819 }
2820
2821 /**
2822  *  ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
2823  *  @hw: pointer to hardware structure
2824  *  @speed: the link speed to force
2825  *
2826  *  Configures the integrated PHY for native SFI mode. Used to connect the
2827  *  internal PHY directly to an SFP cage, without autonegotiation.
2828  **/
2829 STATIC s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2830 {
2831         struct ixgbe_mac_info *mac = &hw->mac;
2832         s32 status;
2833         u32 reg_val;
2834
2835         /* Disable all AN and force speed to 10G Serial. */
2836         status = mac->ops.read_iosf_sb_reg(hw,
2837                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2838                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2839         if (status != IXGBE_SUCCESS)
2840                 return status;
2841
2842         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2843         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2844         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2845         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2846
2847         /* Select forced link speed for internal PHY. */
2848         switch (*speed) {
2849         case IXGBE_LINK_SPEED_10GB_FULL:
2850                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
2851                 break;
2852         case IXGBE_LINK_SPEED_1GB_FULL:
2853                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2854                 break;
2855         default:
2856                 /* Other link speeds are not supported by internal PHY. */
2857                 return IXGBE_ERR_LINK_SETUP;
2858         }
2859
2860         status = mac->ops.write_iosf_sb_reg(hw,
2861                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2862                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2863
2864         /* Toggle port SW reset by AN reset. */
2865         status = ixgbe_restart_an_internal_phy_x550em(hw);
2866
2867         return status;
2868 }
2869
2870 /**
2871  *  ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2872  *  @hw: pointer to hardware structure
2873  *
2874  *  Configure the the integrated PHY for SFP support.
2875  **/
2876 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2877                                     ixgbe_link_speed speed,
2878                                     bool autoneg_wait_to_complete)
2879 {
2880         s32 ret_val;
2881         u16 reg_phy_ext;
2882         bool setup_linear = false;
2883         u32 reg_slice, reg_phy_int, slice_offset;
2884
2885         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2886
2887         /* Check if SFP module is supported and linear */
2888         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2889
2890         /* If no SFP module present, then return success. Return success since
2891          * SFP not present error is not excepted in the setup MAC link flow.
2892          */
2893         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2894                 return IXGBE_SUCCESS;
2895
2896         if (ret_val != IXGBE_SUCCESS)
2897                 return ret_val;
2898
2899         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2900                 /* Configure internal PHY for native SFI based on module type */
2901                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2902                                    IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2903                                    IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_phy_int);
2904
2905                 if (ret_val != IXGBE_SUCCESS)
2906                         return ret_val;
2907
2908                 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
2909                 if (!setup_linear)
2910                         reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
2911
2912                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2913                                    IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2914                                    IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2915
2916                 if (ret_val != IXGBE_SUCCESS)
2917                         return ret_val;
2918
2919                 /* Setup SFI internal link. */
2920                 ret_val = ixgbe_setup_sfi_x550a(hw, &speed);
2921         } else {
2922                 /* Configure internal PHY for KR/KX. */
2923                 ixgbe_setup_kr_speed_x550em(hw, speed);
2924
2925                 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2926                         /* Find Address */
2927                         DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2928                         return IXGBE_ERR_PHY_ADDR_INVALID;
2929                 }
2930
2931                 /* Get external PHY SKU id */
2932                 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,
2933                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2934
2935                 if (ret_val != IXGBE_SUCCESS)
2936                         return ret_val;
2937
2938                 /* When configuring quad port CS4223, the MAC instance is part
2939                  * of the slice offset.
2940                  */
2941                 if (reg_phy_ext == IXGBE_CS4223_SKU_ID)
2942                         slice_offset = (hw->bus.lan_id +
2943                                         (hw->bus.instance_id << 1)) << 12;
2944                 else
2945                         slice_offset = hw->bus.lan_id << 12;
2946
2947                 /* Configure CS4227/CS4223 LINE side to proper mode. */
2948                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2949                 if (setup_linear)
2950                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2951                 else
2952                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2953                 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2954                                          IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2955         }
2956         return ret_val;
2957 }
2958
2959 /**
2960  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2961  *  @hw: pointer to hardware structure
2962  *
2963  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2964  **/
2965 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2966 {
2967         struct ixgbe_mac_info *mac = &hw->mac;
2968         s32 status;
2969         u32 reg_val;
2970
2971         /* Disable training protocol FSM. */
2972         status = mac->ops.read_iosf_sb_reg(hw,
2973                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2974                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2975         if (status != IXGBE_SUCCESS)
2976                 return status;
2977         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2978         status = mac->ops.write_iosf_sb_reg(hw,
2979                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2980                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2981         if (status != IXGBE_SUCCESS)
2982                 return status;
2983
2984         /* Disable Flex from training TXFFE. */
2985         status = mac->ops.read_iosf_sb_reg(hw,
2986                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2987                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2988         if (status != IXGBE_SUCCESS)
2989                 return status;
2990         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2991         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2992         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2993         status = mac->ops.write_iosf_sb_reg(hw,
2994                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2995                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2996         if (status != IXGBE_SUCCESS)
2997                 return status;
2998         status = mac->ops.read_iosf_sb_reg(hw,
2999                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
3000                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3001         if (status != IXGBE_SUCCESS)
3002                 return status;
3003         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
3004         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
3005         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
3006         status = mac->ops.write_iosf_sb_reg(hw,
3007                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
3008                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3009         if (status != IXGBE_SUCCESS)
3010                 return status;
3011
3012         /* Enable override for coefficients. */
3013         status = mac->ops.read_iosf_sb_reg(hw,
3014                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
3015                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3016         if (status != IXGBE_SUCCESS)
3017                 return status;
3018         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
3019         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
3020         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
3021         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
3022         status = mac->ops.write_iosf_sb_reg(hw,
3023                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
3024                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3025         return status;
3026 }
3027
3028 /**
3029  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
3030  *  @hw: pointer to hardware structure
3031  *  @speed: the link speed to force
3032  *
3033  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
3034  *  internal and external PHY at a specific speed, without autonegotiation.
3035  **/
3036 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
3037 {
3038         struct ixgbe_mac_info *mac = &hw->mac;
3039         s32 status;
3040         u32 reg_val;
3041
3042         /* iXFI is only supported with X552 */
3043         if (mac->type != ixgbe_mac_X550EM_x)
3044                 return IXGBE_ERR_LINK_SETUP;
3045
3046         /* Disable AN and force speed to 10G Serial. */
3047         status = mac->ops.read_iosf_sb_reg(hw,
3048                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3049                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3050         if (status != IXGBE_SUCCESS)
3051                 return status;
3052
3053         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3054         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3055
3056         /* Select forced link speed for internal PHY. */
3057         switch (*speed) {
3058         case IXGBE_LINK_SPEED_10GB_FULL:
3059                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3060                 break;
3061         case IXGBE_LINK_SPEED_1GB_FULL:
3062                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
3063                 break;
3064         default:
3065                 /* Other link speeds are not supported by internal KR PHY. */
3066                 return IXGBE_ERR_LINK_SETUP;
3067         }
3068
3069         status = mac->ops.write_iosf_sb_reg(hw,
3070                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3071                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3072         if (status != IXGBE_SUCCESS)
3073                 return status;
3074
3075         /* Additional configuration needed for x550em_x */
3076         if (hw->mac.type == ixgbe_mac_X550EM_x) {
3077                 status = ixgbe_setup_ixfi_x550em_x(hw);
3078                 if (status != IXGBE_SUCCESS)
3079                         return status;
3080         }
3081
3082         /* Toggle port SW reset by AN reset. */
3083         status = ixgbe_restart_an_internal_phy_x550em(hw);
3084
3085         return status;
3086 }
3087
3088 /**
3089  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
3090  * @hw: address of hardware structure
3091  * @link_up: address of boolean to indicate link status
3092  *
3093  * Returns error code if unable to get link status.
3094  */
3095 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
3096 {
3097         u32 ret;
3098         u16 autoneg_status;
3099
3100         *link_up = false;
3101
3102         /* read this twice back to back to indicate current status */
3103         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3104                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3105                                    &autoneg_status);
3106         if (ret != IXGBE_SUCCESS)
3107                 return ret;
3108
3109         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3110                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3111                                    &autoneg_status);
3112         if (ret != IXGBE_SUCCESS)
3113                 return ret;
3114
3115         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
3116
3117         return IXGBE_SUCCESS;
3118 }
3119
3120 /**
3121  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
3122  * @hw: point to hardware structure
3123  *
3124  * Configures the link between the integrated KR PHY and the external X557 PHY
3125  * The driver will call this function when it gets a link status change
3126  * interrupt from the X557 PHY. This function configures the link speed
3127  * between the PHYs to match the link speed of the BASE-T link.
3128  *
3129  * A return of a non-zero value indicates an error, and the base driver should
3130  * not report link up.
3131  */
3132 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
3133 {
3134         ixgbe_link_speed force_speed;
3135         bool link_up;
3136         u32 status;
3137         u16 speed;
3138
3139         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3140                 return IXGBE_ERR_CONFIG;
3141
3142         if (hw->mac.type == ixgbe_mac_X550EM_x &&
3143             !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3144                 /* If link is down, there is no setup necessary so return  */
3145                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3146                 if (status != IXGBE_SUCCESS)
3147                         return status;
3148
3149                 if (!link_up)
3150                         return IXGBE_SUCCESS;
3151
3152                 status = hw->phy.ops.read_reg(hw,
3153                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3154                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3155                                               &speed);
3156                 if (status != IXGBE_SUCCESS)
3157                         return status;
3158
3159                 /* If link is still down - no setup is required so return */
3160                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3161                 if (status != IXGBE_SUCCESS)
3162                         return status;
3163                 if (!link_up)
3164                         return IXGBE_SUCCESS;
3165
3166                 /* clear everything but the speed and duplex bits */
3167                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
3168
3169                 switch (speed) {
3170                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
3171                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3172                         break;
3173                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
3174                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3175                         break;
3176                 default:
3177                         /* Internal PHY does not support anything else */
3178                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
3179                 }
3180
3181                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
3182         } else {
3183                 speed = IXGBE_LINK_SPEED_10GB_FULL |
3184                         IXGBE_LINK_SPEED_1GB_FULL;
3185                 return ixgbe_setup_kr_speed_x550em(hw, speed);
3186         }
3187 }
3188
3189 /**
3190  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
3191  *  @hw: pointer to hardware structure
3192  *
3193  *  Configures the integrated KR PHY to use internal loopback mode.
3194  **/
3195 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
3196 {
3197         s32 status;
3198         u32 reg_val;
3199
3200         /* Disable AN and force speed to 10G Serial. */
3201         status = hw->mac.ops.read_iosf_sb_reg(hw,
3202                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3203                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3204         if (status != IXGBE_SUCCESS)
3205                 return status;
3206         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3207         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3208         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3209         status = hw->mac.ops.write_iosf_sb_reg(hw,
3210                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3211                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3212         if (status != IXGBE_SUCCESS)
3213                 return status;
3214
3215         /* Set near-end loopback clocks. */
3216         status = hw->mac.ops.read_iosf_sb_reg(hw,
3217                                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3218                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3219         if (status != IXGBE_SUCCESS)
3220                 return status;
3221         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3222         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3223         status = hw->mac.ops.write_iosf_sb_reg(hw,
3224                                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3225                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3226         if (status != IXGBE_SUCCESS)
3227                 return status;
3228
3229         /* Set loopback enable. */
3230         status = hw->mac.ops.read_iosf_sb_reg(hw,
3231                                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3232                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3233         if (status != IXGBE_SUCCESS)
3234                 return status;
3235         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3236         status = hw->mac.ops.write_iosf_sb_reg(hw,
3237                                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3238                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3239         if (status != IXGBE_SUCCESS)
3240                 return status;
3241
3242         /* Training bypass. */
3243         status = hw->mac.ops.read_iosf_sb_reg(hw,
3244                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3245                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3246         if (status != IXGBE_SUCCESS)
3247                 return status;
3248         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3249         status = hw->mac.ops.write_iosf_sb_reg(hw,
3250                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3251                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3252
3253         return status;
3254 }
3255
3256 /**
3257  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3258  *  assuming that the semaphore is already obtained.
3259  *  @hw: pointer to hardware structure
3260  *  @offset: offset of  word in the EEPROM to read
3261  *  @data: word read from the EEPROM
3262  *
3263  *  Reads a 16 bit word from the EEPROM using the hostif.
3264  **/
3265 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
3266 {
3267         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3268         struct ixgbe_hic_read_shadow_ram buffer;
3269         s32 status;
3270
3271         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3272         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3273         buffer.hdr.req.buf_lenh = 0;
3274         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3275         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3276
3277         /* convert offset from words to bytes */
3278         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3279         /* one word */
3280         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3281
3282         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3283         if (status)
3284                 return status;
3285
3286         status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3287                                     IXGBE_HI_COMMAND_TIMEOUT);
3288         if (!status) {
3289                 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3290                                                   FW_NVM_DATA_OFFSET);
3291         }
3292
3293         hw->mac.ops.release_swfw_sync(hw, mask);
3294         return status;
3295 }
3296
3297 /**
3298  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3299  *  @hw: pointer to hardware structure
3300  *  @offset: offset of  word in the EEPROM to read
3301  *  @words: number of words
3302  *  @data: word(s) read from the EEPROM
3303  *
3304  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
3305  **/
3306 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3307                                      u16 offset, u16 words, u16 *data)
3308 {
3309         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3310         struct ixgbe_hic_read_shadow_ram buffer;
3311         u32 current_word = 0;
3312         u16 words_to_read;
3313         s32 status;
3314         u32 i;
3315
3316         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3317
3318         /* Take semaphore for the entire operation. */
3319         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3320         if (status) {
3321                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3322                 return status;
3323         }
3324
3325         while (words) {
3326                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3327                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3328                 else
3329                         words_to_read = words;
3330
3331                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3332                 buffer.hdr.req.buf_lenh = 0;
3333                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3334                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3335
3336                 /* convert offset from words to bytes */
3337                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3338                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3339
3340                 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3341                                             IXGBE_HI_COMMAND_TIMEOUT);
3342
3343                 if (status) {
3344                         DEBUGOUT("Host interface command failed\n");
3345                         goto out;
3346                 }
3347
3348                 for (i = 0; i < words_to_read; i++) {
3349                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3350                                   2 * i;
3351                         u32 value = IXGBE_READ_REG(hw, reg);
3352
3353                         data[current_word] = (u16)(value & 0xffff);
3354                         current_word++;
3355                         i++;
3356                         if (i < words_to_read) {
3357                                 value >>= 16;
3358                                 data[current_word] = (u16)(value & 0xffff);
3359                                 current_word++;
3360                         }
3361                 }
3362                 words -= words_to_read;
3363         }
3364
3365 out:
3366         hw->mac.ops.release_swfw_sync(hw, mask);
3367         return status;
3368 }
3369
3370 /**
3371  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3372  *  @hw: pointer to hardware structure
3373  *  @offset: offset of  word in the EEPROM to write
3374  *  @data: word write to the EEPROM
3375  *
3376  *  Write a 16 bit word to the EEPROM using the hostif.
3377  **/
3378 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3379                                     u16 data)
3380 {
3381         s32 status;
3382         struct ixgbe_hic_write_shadow_ram buffer;
3383
3384         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3385
3386         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3387         buffer.hdr.req.buf_lenh = 0;
3388         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3389         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3390
3391          /* one word */
3392         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3393         buffer.data = data;
3394         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3395
3396         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3397                                               sizeof(buffer),
3398                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3399
3400         return status;
3401 }
3402
3403 /**
3404  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3405  *  @hw: pointer to hardware structure
3406  *  @offset: offset of  word in the EEPROM to write
3407  *  @data: word write to the EEPROM
3408  *
3409  *  Write a 16 bit word to the EEPROM using the hostif.
3410  **/
3411 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3412                                u16 data)
3413 {
3414         s32 status = IXGBE_SUCCESS;
3415
3416         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3417
3418         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3419             IXGBE_SUCCESS) {
3420                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3421                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3422         } else {
3423                 DEBUGOUT("write ee hostif failed to get semaphore");
3424                 status = IXGBE_ERR_SWFW_SYNC;
3425         }
3426
3427         return status;
3428 }
3429
3430 /**
3431  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3432  *  @hw: pointer to hardware structure
3433  *  @offset: offset of  word in the EEPROM to write
3434  *  @words: number of words
3435  *  @data: word(s) write to the EEPROM
3436  *
3437  *  Write a 16 bit word(s) to the EEPROM using the hostif.
3438  **/
3439 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3440                                       u16 offset, u16 words, u16 *data)
3441 {
3442         s32 status = IXGBE_SUCCESS;
3443         u32 i = 0;
3444
3445         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3446
3447         /* Take semaphore for the entire operation. */
3448         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3449         if (status != IXGBE_SUCCESS) {
3450                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3451                 goto out;
3452         }
3453
3454         for (i = 0; i < words; i++) {
3455                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3456                                                          data[i]);
3457
3458                 if (status != IXGBE_SUCCESS) {
3459                         DEBUGOUT("Eeprom buffered write failed\n");
3460                         break;
3461                 }
3462         }
3463
3464         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3465 out:
3466
3467         return status;
3468 }
3469
3470 /**
3471  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3472  * @hw: pointer to hardware structure
3473  * @ptr: pointer offset in eeprom
3474  * @size: size of section pointed by ptr, if 0 first word will be used as size
3475  * @csum: address of checksum to update
3476  *
3477  * Returns error status for any failure
3478  */
3479 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3480                                    u16 size, u16 *csum, u16 *buffer,
3481                                    u32 buffer_size)
3482 {
3483         u16 buf[256];
3484         s32 status;
3485         u16 length, bufsz, i, start;
3486         u16 *local_buffer;
3487
3488         bufsz = sizeof(buf) / sizeof(buf[0]);
3489
3490         /* Read a chunk at the pointer location */
3491         if (!buffer) {
3492                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3493                 if (status) {
3494                         DEBUGOUT("Failed to read EEPROM image\n");
3495                         return status;
3496                 }
3497                 local_buffer = buf;
3498         } else {
3499                 if (buffer_size < ptr)
3500                         return  IXGBE_ERR_PARAM;
3501                 local_buffer = &buffer[ptr];
3502         }
3503
3504         if (size) {
3505                 start = 0;
3506                 length = size;
3507         } else {
3508                 start = 1;
3509                 length = local_buffer[0];
3510
3511                 /* Skip pointer section if length is invalid. */
3512                 if (length == 0xFFFF || length == 0 ||
3513                     (ptr + length) >= hw->eeprom.word_size)
3514                         return IXGBE_SUCCESS;
3515         }
3516
3517         if (buffer && ((u32)start + (u32)length > buffer_size))
3518                 return IXGBE_ERR_PARAM;
3519
3520         for (i = start; length; i++, length--) {
3521                 if (i == bufsz && !buffer) {
3522                         ptr += bufsz;
3523                         i = 0;
3524                         if (length < bufsz)
3525                                 bufsz = length;
3526
3527                         /* Read a chunk at the pointer location */
3528                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3529                                                                   bufsz, buf);
3530                         if (status) {
3531                                 DEBUGOUT("Failed to read EEPROM image\n");
3532                                 return status;
3533                         }
3534                 }
3535                 *csum += local_buffer[i];
3536         }
3537         return IXGBE_SUCCESS;
3538 }
3539
3540 /**
3541  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3542  *  @hw: pointer to hardware structure
3543  *  @buffer: pointer to buffer containing calculated checksum
3544  *  @buffer_size: size of buffer
3545  *
3546  *  Returns a negative error code on error, or the 16-bit checksum
3547  **/
3548 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3549 {
3550         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3551         u16 *local_buffer;
3552         s32 status;
3553         u16 checksum = 0;
3554         u16 pointer, i, size;
3555
3556         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3557
3558         hw->eeprom.ops.init_params(hw);
3559
3560         if (!buffer) {
3561                 /* Read pointer area */
3562                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3563                                                      IXGBE_EEPROM_LAST_WORD + 1,
3564                                                      eeprom_ptrs);
3565                 if (status) {
3566                         DEBUGOUT("Failed to read EEPROM image\n");
3567                         return status;
3568                 }
3569                 local_buffer = eeprom_ptrs;
3570         } else {
3571                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3572                         return IXGBE_ERR_PARAM;
3573                 local_buffer = buffer;
3574         }
3575
3576         /*
3577          * For X550 hardware include 0x0-0x41 in the checksum, skip the
3578          * checksum word itself
3579          */
3580         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3581                 if (i != IXGBE_EEPROM_CHECKSUM)
3582                         checksum += local_buffer[i];
3583
3584         /*
3585          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
3586          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3587          */
3588         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3589                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3590                         continue;
3591
3592                 pointer = local_buffer[i];
3593
3594                 /* Skip pointer section if the pointer is invalid. */
3595                 if (pointer == 0xFFFF || pointer == 0 ||
3596                     pointer >= hw->eeprom.word_size)
3597                         continue;
3598
3599                 switch (i) {
3600                 case IXGBE_PCIE_GENERAL_PTR:
3601                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3602                         break;
3603                 case IXGBE_PCIE_CONFIG0_PTR:
3604                 case IXGBE_PCIE_CONFIG1_PTR:
3605                         size = IXGBE_PCIE_CONFIG_SIZE;
3606                         break;
3607                 default:
3608                         size = 0;
3609                         break;
3610                 }
3611
3612                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3613                                                 buffer, buffer_size);
3614                 if (status)
3615                         return status;
3616         }
3617
3618         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3619
3620         return (s32)checksum;
3621 }
3622
3623 /**
3624  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3625  *  @hw: pointer to hardware structure
3626  *
3627  *  Returns a negative error code on error, or the 16-bit checksum
3628  **/
3629 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3630 {
3631         return ixgbe_calc_checksum_X550(hw, NULL, 0);
3632 }
3633
3634 /**
3635  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3636  *  @hw: pointer to hardware structure
3637  *  @checksum_val: calculated checksum
3638  *
3639  *  Performs checksum calculation and validates the EEPROM checksum.  If the
3640  *  caller does not need checksum_val, the value can be NULL.
3641  **/
3642 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3643 {
3644         s32 status;
3645         u16 checksum;
3646         u16 read_checksum = 0;
3647
3648         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3649
3650         /* Read the first word from the EEPROM. If this times out or fails, do
3651          * not continue or we could be in for a very long wait while every
3652          * EEPROM read fails
3653          */
3654         status = hw->eeprom.ops.read(hw, 0, &checksum);
3655         if (status) {
3656                 DEBUGOUT("EEPROM read failed\n");
3657                 return status;
3658         }
3659
3660         status = hw->eeprom.ops.calc_checksum(hw);
3661         if (status < 0)
3662                 return status;
3663
3664         checksum = (u16)(status & 0xffff);
3665
3666         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3667                                            &read_checksum);
3668         if (status)
3669                 return status;
3670
3671         /* Verify read checksum from EEPROM is the same as
3672          * calculated checksum
3673          */
3674         if (read_checksum != checksum) {
3675                 status = IXGBE_ERR_EEPROM_CHECKSUM;
3676                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3677                              "Invalid EEPROM checksum");
3678         }
3679
3680         /* If the user cares, return the calculated checksum */
3681         if (checksum_val)
3682                 *checksum_val = checksum;
3683
3684         return status;
3685 }
3686
3687 /**
3688  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3689  * @hw: pointer to hardware structure
3690  *
3691  * After writing EEPROM to shadow RAM using EEWR register, software calculates
3692  * checksum and updates the EEPROM and instructs the hardware to update
3693  * the flash.
3694  **/
3695 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3696 {
3697         s32 status;
3698         u16 checksum = 0;
3699
3700         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3701
3702         /* Read the first word from the EEPROM. If this times out or fails, do
3703          * not continue or we could be in for a very long wait while every
3704          * EEPROM read fails
3705          */
3706         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3707         if (status) {
3708                 DEBUGOUT("EEPROM read failed\n");
3709                 return status;
3710         }
3711
3712         status = ixgbe_calc_eeprom_checksum_X550(hw);
3713         if (status < 0)
3714                 return status;
3715
3716         checksum = (u16)(status & 0xffff);
3717
3718         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3719                                             checksum);
3720         if (status)
3721                 return status;
3722
3723         status = ixgbe_update_flash_X550(hw);
3724
3725         return status;
3726 }
3727
3728 /**
3729  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3730  *  @hw: pointer to hardware structure
3731  *
3732  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3733  **/
3734 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3735 {
3736         s32 status = IXGBE_SUCCESS;
3737         union ixgbe_hic_hdr2 buffer;
3738
3739         DEBUGFUNC("ixgbe_update_flash_X550");
3740
3741         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3742         buffer.req.buf_lenh = 0;
3743         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3744         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3745
3746         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3747                                               sizeof(buffer),
3748                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3749
3750         return status;
3751 }
3752
3753 /**
3754  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3755  *  @hw: pointer to hardware structure
3756  *
3757  *  Determines physical layer capabilities of the current configuration.
3758  **/
3759 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3760 {
3761         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3762         u16 ext_ability = 0;
3763
3764         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3765
3766         hw->phy.ops.identify(hw);
3767
3768         switch (hw->phy.type) {
3769         case ixgbe_phy_x550em_kr:
3770                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3771                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3772                 break;
3773         case ixgbe_phy_x550em_kx4:
3774                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3775                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3776                 break;
3777         case ixgbe_phy_x550em_ext_t:
3778                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3779                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3780                                      &ext_ability);
3781                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3782                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3783                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3784                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3785                 break;
3786         case ixgbe_phy_fw:
3787                 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
3788         default:
3789                 break;
3790         }
3791
3792         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3793                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3794
3795         return physical_layer;
3796 }
3797
3798 /**
3799  * ixgbe_get_bus_info_x550em - Set PCI bus info
3800  * @hw: pointer to hardware structure
3801  *
3802  * Sets bus link width and speed to unknown because X550em is
3803  * not a PCI device.
3804  **/
3805 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3806 {
3807
3808         DEBUGFUNC("ixgbe_get_bus_info_x550em");
3809
3810         hw->bus.width = ixgbe_bus_width_unknown;
3811         hw->bus.speed = ixgbe_bus_speed_unknown;
3812
3813         hw->mac.ops.set_lan_id(hw);
3814
3815         return IXGBE_SUCCESS;
3816 }
3817
3818 /**
3819  * ixgbe_disable_rx_x550 - Disable RX unit
3820  *
3821  * Enables the Rx DMA unit for x550
3822  **/
3823 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3824 {
3825         u32 rxctrl, pfdtxgswc;
3826         s32 status;
3827         struct ixgbe_hic_disable_rxen fw_cmd;
3828
3829         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3830
3831         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3832         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3833                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3834                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3835                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3836                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3837                         hw->mac.set_lben = true;
3838                 } else {
3839                         hw->mac.set_lben = false;
3840                 }
3841
3842                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3843                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3844                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3845                 fw_cmd.port_number = (u8)hw->bus.lan_id;
3846
3847                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3848                                         sizeof(struct ixgbe_hic_disable_rxen),
3849                                         IXGBE_HI_COMMAND_TIMEOUT, true);
3850
3851                 /* If we fail - disable RX using register write */
3852                 if (status) {
3853                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3854                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3855                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3856                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3857                         }
3858                 }
3859         }
3860 }
3861
3862 /**
3863  * ixgbe_enter_lplu_x550em - Transition to low power states
3864  *  @hw: pointer to hardware structure
3865  *
3866  * Configures Low Power Link Up on transition to low power states
3867  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3868  * X557 PHY immediately prior to entering LPLU.
3869  **/
3870 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3871 {
3872         u16 an_10g_cntl_reg, autoneg_reg, speed;
3873         s32 status;
3874         ixgbe_link_speed lcd_speed;
3875         u32 save_autoneg;
3876         bool link_up;
3877
3878         /* SW LPLU not required on later HW revisions. */
3879         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3880             (IXGBE_FUSES0_REV_MASK &
3881              IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3882                 return IXGBE_SUCCESS;
3883
3884         /* If blocked by MNG FW, then don't restart AN */
3885         if (ixgbe_check_reset_blocked(hw))
3886                 return IXGBE_SUCCESS;
3887
3888         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3889         if (status != IXGBE_SUCCESS)
3890                 return status;
3891
3892         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3893
3894         if (status != IXGBE_SUCCESS)
3895                 return status;
3896
3897         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3898          * disabled, then force link down by entering low power mode.
3899          */
3900         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3901             !(hw->wol_enabled || ixgbe_mng_present(hw)))
3902                 return ixgbe_set_copper_phy_power(hw, FALSE);
3903
3904         /* Determine LCD */
3905         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3906
3907         if (status != IXGBE_SUCCESS)
3908                 return status;
3909
3910         /* If no valid LCD link speed, then force link down and exit. */
3911         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3912                 return ixgbe_set_copper_phy_power(hw, FALSE);
3913
3914         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3915                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3916                                       &speed);
3917
3918         if (status != IXGBE_SUCCESS)
3919                 return status;
3920
3921         /* If no link now, speed is invalid so take link down */
3922         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3923         if (status != IXGBE_SUCCESS)
3924                 return ixgbe_set_copper_phy_power(hw, false);
3925
3926         /* clear everything but the speed bits */
3927         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3928
3929         /* If current speed is already LCD, then exit. */
3930         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3931              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3932             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3933              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3934                 return status;
3935
3936         /* Clear AN completed indication */
3937         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3938                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3939                                       &autoneg_reg);
3940
3941         if (status != IXGBE_SUCCESS)
3942                 return status;
3943
3944         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3945                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3946                              &an_10g_cntl_reg);
3947
3948         if (status != IXGBE_SUCCESS)
3949                 return status;
3950
3951         status = hw->phy.ops.read_reg(hw,
3952                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3953                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3954                              &autoneg_reg);
3955
3956         if (status != IXGBE_SUCCESS)
3957                 return status;
3958
3959         save_autoneg = hw->phy.autoneg_advertised;
3960
3961         /* Setup link at least common link speed */
3962         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3963
3964         /* restore autoneg from before setting lplu speed */
3965         hw->phy.autoneg_advertised = save_autoneg;
3966
3967         return status;
3968 }
3969
3970 /**
3971  * ixgbe_get_lcd_x550em - Determine lowest common denominator
3972  *  @hw: pointer to hardware structure
3973  *  @lcd_speed: pointer to lowest common link speed
3974  *
3975  * Determine lowest common link speed with link partner.
3976  **/
3977 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3978 {
3979         u16 an_lp_status;
3980         s32 status;
3981         u16 word = hw->eeprom.ctrl_word_3;
3982
3983         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3984
3985         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3986                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3987                                       &an_lp_status);
3988
3989         if (status != IXGBE_SUCCESS)
3990                 return status;
3991
3992         /* If link partner advertised 1G, return 1G */
3993         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3994                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3995                 return status;
3996         }
3997
3998         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3999         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
4000             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
4001                 return status;
4002
4003         /* Link partner not capable of lower speeds, return 10G */
4004         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
4005         return status;
4006 }
4007
4008 /**
4009  *  ixgbe_setup_fc_X550em - Set up flow control
4010  *  @hw: pointer to hardware structure
4011  *
4012  *  Called at init time to set up flow control.
4013  **/
4014 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
4015 {
4016         s32 ret_val = IXGBE_SUCCESS;
4017         u32 pause, asm_dir, reg_val;
4018
4019         DEBUGFUNC("ixgbe_setup_fc_X550em");
4020
4021         /* Validate the requested mode */
4022         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4023                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4024                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4025                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4026                 goto out;
4027         }
4028
4029         /* 10gig parts do not have a word in the EEPROM to determine the
4030          * default flow control setting, so we explicitly set it to full.
4031          */
4032         if (hw->fc.requested_mode == ixgbe_fc_default)
4033                 hw->fc.requested_mode = ixgbe_fc_full;
4034
4035         /* Determine PAUSE and ASM_DIR bits. */
4036         switch (hw->fc.requested_mode) {
4037         case ixgbe_fc_none:
4038                 pause = 0;
4039                 asm_dir = 0;
4040                 break;
4041         case ixgbe_fc_tx_pause:
4042                 pause = 0;
4043                 asm_dir = 1;
4044                 break;
4045         case ixgbe_fc_rx_pause:
4046                 /* Rx Flow control is enabled and Tx Flow control is
4047                  * disabled by software override. Since there really
4048                  * isn't a way to advertise that we are capable of RX
4049                  * Pause ONLY, we will advertise that we support both
4050                  * symmetric and asymmetric Rx PAUSE, as such we fall
4051                  * through to the fc_full statement.  Later, we will
4052                  * disable the adapter's ability to send PAUSE frames.
4053                  */
4054         case ixgbe_fc_full:
4055                 pause = 1;
4056                 asm_dir = 1;
4057                 break;
4058         default:
4059                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4060                         "Flow control param set incorrectly\n");
4061                 ret_val = IXGBE_ERR_CONFIG;
4062                 goto out;
4063         }
4064
4065         switch (hw->device_id) {
4066         case IXGBE_DEV_ID_X550EM_X_KR:
4067         case IXGBE_DEV_ID_X550EM_A_KR:
4068         case IXGBE_DEV_ID_X550EM_A_KR_L:
4069                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
4070                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4071                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
4072                 if (ret_val != IXGBE_SUCCESS)
4073                         goto out;
4074                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4075                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4076                 if (pause)
4077                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4078                 if (asm_dir)
4079                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4080                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
4081                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4082                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
4083
4084                 /* This device does not fully support AN. */
4085                 hw->fc.disable_fc_autoneg = true;
4086                 break;
4087         default:
4088                 break;
4089         }
4090
4091 out:
4092         return ret_val;
4093 }
4094
4095 /**
4096  *  ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
4097  *  @hw: pointer to hardware structure
4098  *
4099  *  Enable flow control according to IEEE clause 37.
4100  **/
4101 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
4102 {
4103         u32 link_s1, lp_an_page_low, an_cntl_1;
4104         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4105         ixgbe_link_speed speed;
4106         bool link_up;
4107
4108         /* AN should have completed when the cable was plugged in.
4109          * Look for reasons to bail out.  Bail out if:
4110          * - FC autoneg is disabled, or if
4111          * - link is not up.
4112          */
4113         if (hw->fc.disable_fc_autoneg) {
4114                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4115                              "Flow control autoneg is disabled");
4116                 goto out;
4117         }
4118
4119         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4120         if (!link_up) {
4121                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4122                 goto out;
4123         }
4124
4125         /* Check at auto-negotiation has completed */
4126         status = hw->mac.ops.read_iosf_sb_reg(hw,
4127                                         IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4128                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4129
4130         if (status != IXGBE_SUCCESS ||
4131             (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4132                 DEBUGOUT("Auto-Negotiation did not complete\n");
4133                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4134                 goto out;
4135         }
4136
4137         /* Read the 10g AN autoc and LP ability registers and resolve
4138          * local flow control settings accordingly
4139          */
4140         status = hw->mac.ops.read_iosf_sb_reg(hw,
4141                                 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4142                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
4143
4144         if (status != IXGBE_SUCCESS) {
4145                 DEBUGOUT("Auto-Negotiation did not complete\n");
4146                 goto out;
4147         }
4148
4149         status = hw->mac.ops.read_iosf_sb_reg(hw,
4150                                 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
4151                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
4152
4153         if (status != IXGBE_SUCCESS) {
4154                 DEBUGOUT("Auto-Negotiation did not complete\n");
4155                 goto out;
4156         }
4157
4158         status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
4159                                     IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
4160                                     IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
4161                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
4162                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
4163
4164 out:
4165         if (status == IXGBE_SUCCESS) {
4166                 hw->fc.fc_was_autonegged = true;
4167         } else {
4168                 hw->fc.fc_was_autonegged = false;
4169                 hw->fc.current_mode = hw->fc.requested_mode;
4170         }
4171 }
4172
4173 /**
4174  *  ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
4175  *  @hw: pointer to hardware structure
4176  *
4177  **/
4178 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
4179 {
4180         hw->fc.fc_was_autonegged = false;
4181         hw->fc.current_mode = hw->fc.requested_mode;
4182 }
4183
4184 /**
4185  *  ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
4186  *  @hw: pointer to hardware structure
4187  *
4188  *  Enable flow control according to IEEE clause 37.
4189  **/
4190 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
4191 {
4192         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4193         u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
4194         ixgbe_link_speed speed;
4195         bool link_up;
4196         u32 fc;
4197
4198         /* AN should have completed when the cable was plugged in.
4199          * Look for reasons to bail out.  Bail out if:
4200          * - FC autoneg is disabled, or if
4201          * - link is not up.
4202          */
4203         if (hw->fc.disable_fc_autoneg) {
4204                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4205                              "Flow control autoneg is disabled");
4206                 goto out;
4207         }
4208
4209         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4210         if (!link_up) {
4211                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4212                 goto out;
4213         }
4214
4215         /* Check if auto-negotiation has completed */
4216         status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info);
4217         if (status != IXGBE_SUCCESS ||
4218             !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) {
4219                 DEBUGOUT("Auto-Negotiation did not complete\n");
4220                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4221                 goto out;
4222         }
4223
4224         /* Get the advertized flow control and modify it to indicate
4225          * pause and asymmetric pause instead of rx and tx
4226          */
4227         fc = info[0];
4228         if (fc & FW_PHY_ACT_GET_LINK_INFO_FC_RX)
4229                 fc ^= FW_PHY_ACT_GET_LINK_INFO_FC_TX;
4230
4231         /* Modify link partner's flow control to indicate pause and
4232          * asymmetric pause instead of rx and tx
4233          */
4234         if (fc & FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX)
4235                 fc ^= FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX;
4236
4237         /* Negotiate the flow control */
4238         status = ixgbe_negotiate_fc(hw, fc, fc,
4239                                     FW_PHY_ACT_GET_LINK_INFO_FC_RX,
4240                                     FW_PHY_ACT_GET_LINK_INFO_FC_TX,
4241                                     FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX,
4242                                     FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX);
4243
4244 out:
4245         if (status == IXGBE_SUCCESS) {
4246                 hw->fc.fc_was_autonegged = true;
4247         } else {
4248                 hw->fc.fc_was_autonegged = false;
4249                 hw->fc.current_mode = hw->fc.requested_mode;
4250         }
4251 }
4252
4253 /**
4254  *  ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4255  *  @hw: pointer to hardware structure
4256  *
4257  *  Called at init time to set up flow control.
4258  **/
4259 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4260 {
4261         s32 status = IXGBE_SUCCESS;
4262         u32 an_cntl = 0;
4263
4264         DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4265
4266         /* Validate the requested mode */
4267         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4268                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4269                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4270                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4271         }
4272
4273         if (hw->fc.requested_mode == ixgbe_fc_default)
4274                 hw->fc.requested_mode = ixgbe_fc_full;
4275
4276         /* Set up the 1G and 10G flow control advertisement registers so the
4277          * HW will be able to do FC autoneg once the cable is plugged in.  If
4278          * we link at 10G, the 1G advertisement is harmless and vice versa.
4279          */
4280         status = hw->mac.ops.read_iosf_sb_reg(hw,
4281                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4282                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4283
4284         if (status != IXGBE_SUCCESS) {
4285                 DEBUGOUT("Auto-Negotiation did not complete\n");
4286                 return status;
4287         }
4288
4289         /* The possible values of fc.requested_mode are:
4290          * 0: Flow control is completely disabled
4291          * 1: Rx flow control is enabled (we can receive pause frames,
4292          *    but not send pause frames).
4293          * 2: Tx flow control is enabled (we can send pause frames but
4294          *    we do not support receiving pause frames).
4295          * 3: Both Rx and Tx flow control (symmetric) are enabled.
4296          * other: Invalid.
4297          */
4298         switch (hw->fc.requested_mode) {
4299         case ixgbe_fc_none:
4300                 /* Flow control completely disabled by software override. */
4301                 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4302                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4303                 break;
4304         case ixgbe_fc_tx_pause:
4305                 /* Tx Flow control is enabled, and Rx Flow control is
4306                  * disabled by software override.
4307                  */
4308                 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4309                 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4310                 break;
4311         case ixgbe_fc_rx_pause:
4312                 /* Rx Flow control is enabled and Tx Flow control is
4313                  * disabled by software override. Since there really
4314                  * isn't a way to advertise that we are capable of RX
4315                  * Pause ONLY, we will advertise that we support both
4316                  * symmetric and asymmetric Rx PAUSE, as such we fall
4317                  * through to the fc_full statement.  Later, we will
4318                  * disable the adapter's ability to send PAUSE frames.
4319                  */
4320         case ixgbe_fc_full:
4321                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4322                 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4323                            IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4324                 break;
4325         default:
4326                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4327                               "Flow control param set incorrectly\n");
4328                 return IXGBE_ERR_CONFIG;
4329         }
4330
4331         status = hw->mac.ops.write_iosf_sb_reg(hw,
4332                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4333                                         IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4334
4335         /* Restart auto-negotiation. */
4336         status = ixgbe_restart_an_internal_phy_x550em(hw);
4337
4338         return status;
4339 }
4340
4341 /**
4342  * ixgbe_set_mux - Set mux for port 1 access with CS4227
4343  * @hw: pointer to hardware structure
4344  * @state: set mux if 1, clear if 0
4345  */
4346 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4347 {
4348         u32 esdp;
4349
4350         if (!hw->bus.lan_id)
4351                 return;
4352         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4353         if (state)
4354                 esdp |= IXGBE_ESDP_SDP1;
4355         else
4356                 esdp &= ~IXGBE_ESDP_SDP1;
4357         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4358         IXGBE_WRITE_FLUSH(hw);
4359 }
4360
4361 /**
4362  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4363  *  @hw: pointer to hardware structure
4364  *  @mask: Mask to specify which semaphore to acquire
4365  *
4366  *  Acquires the SWFW semaphore and sets the I2C MUX
4367  **/
4368 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4369 {
4370         s32 status;
4371
4372         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4373
4374         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4375         if (status)
4376                 return status;
4377
4378         if (mask & IXGBE_GSSR_I2C_MASK)
4379                 ixgbe_set_mux(hw, 1);
4380
4381         return IXGBE_SUCCESS;
4382 }
4383
4384 /**
4385  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4386  *  @hw: pointer to hardware structure
4387  *  @mask: Mask to specify which semaphore to release
4388  *
4389  *  Releases the SWFW semaphore and sets the I2C MUX
4390  **/
4391 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4392 {
4393         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4394
4395         if (mask & IXGBE_GSSR_I2C_MASK)
4396                 ixgbe_set_mux(hw, 0);
4397
4398         ixgbe_release_swfw_sync_X540(hw, mask);
4399 }
4400
4401 /**
4402  *  ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4403  *  @hw: pointer to hardware structure
4404  *  @mask: Mask to specify which semaphore to acquire
4405  *
4406  *  Acquires the SWFW semaphore and get the shared phy token as needed
4407  */
4408 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4409 {
4410         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4411         int retries = FW_PHY_TOKEN_RETRIES;
4412         s32 status = IXGBE_SUCCESS;
4413
4414         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4415
4416         while (--retries) {
4417                 status = IXGBE_SUCCESS;
4418                 if (hmask)
4419                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4420                 if (status)
4421                         return status;
4422                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4423                         return IXGBE_SUCCESS;
4424
4425                 status = ixgbe_get_phy_token(hw);
4426                 if (status == IXGBE_SUCCESS)
4427                         return IXGBE_SUCCESS;
4428
4429                 if (hmask)
4430                         ixgbe_release_swfw_sync_X540(hw, hmask);
4431                 if (status != IXGBE_ERR_TOKEN_RETRY)
4432                         return status;
4433         }
4434
4435         return status;
4436 }
4437
4438 /**
4439  *  ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4440  *  @hw: pointer to hardware structure
4441  *  @mask: Mask to specify which semaphore to release
4442  *
4443  *  Releases the SWFW semaphore and puts the shared phy token as needed
4444  */
4445 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4446 {
4447         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4448
4449         DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4450
4451         if (mask & IXGBE_GSSR_TOKEN_SM)
4452                 ixgbe_put_phy_token(hw);
4453
4454         if (hmask)
4455                 ixgbe_release_swfw_sync_X540(hw, hmask);
4456 }
4457
4458 /**
4459  *  ixgbe_read_phy_reg_x550a  - Reads specified PHY register
4460  *  @hw: pointer to hardware structure
4461  *  @reg_addr: 32 bit address of PHY register to read
4462  *  @phy_data: Pointer to read data from PHY register
4463  *
4464  *  Reads a value from a specified PHY register using the SWFW lock and PHY
4465  *  Token. The PHY Token is needed since the MDIO is shared between to MAC
4466  *  instances.
4467  **/
4468 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4469                                u32 device_type, u16 *phy_data)
4470 {
4471         s32 status;
4472         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4473
4474         DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4475
4476         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4477                 return IXGBE_ERR_SWFW_SYNC;
4478
4479         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4480
4481         hw->mac.ops.release_swfw_sync(hw, mask);
4482
4483         return status;
4484 }
4485
4486 /**
4487  *  ixgbe_write_phy_reg_x550a - Writes specified PHY register
4488  *  @hw: pointer to hardware structure
4489  *  @reg_addr: 32 bit PHY register to write
4490  *  @device_type: 5 bit device type
4491  *  @phy_data: Data to write to the PHY register
4492  *
4493  *  Writes a value to specified PHY register using the SWFW lock and PHY Token.
4494  *  The PHY Token is needed since the MDIO is shared between to MAC instances.
4495  **/
4496 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4497                                 u32 device_type, u16 phy_data)
4498 {
4499         s32 status;
4500         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4501
4502         DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4503
4504         if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4505                 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
4506                                                  phy_data);
4507                 hw->mac.ops.release_swfw_sync(hw, mask);
4508         } else {
4509                 status = IXGBE_ERR_SWFW_SYNC;
4510         }
4511
4512         return status;
4513 }
4514
4515 /**
4516  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4517  * @hw: pointer to hardware structure
4518  *
4519  * Handle external Base T PHY interrupt. If high temperature
4520  * failure alarm then return error, else if link status change
4521  * then setup internal/external PHY link
4522  *
4523  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4524  * failure alarm, else return PHY access status.
4525  */
4526 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4527 {
4528         bool lsc;
4529         u32 status;
4530
4531         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4532
4533         if (status != IXGBE_SUCCESS)
4534                 return status;
4535
4536         if (lsc)
4537                 return ixgbe_setup_internal_phy(hw);
4538
4539         return IXGBE_SUCCESS;
4540 }
4541
4542 /**
4543  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4544  * @hw: pointer to hardware structure
4545  * @speed: new link speed
4546  * @autoneg_wait_to_complete: true when waiting for completion is needed
4547  *
4548  * Setup internal/external PHY link speed based on link speed, then set
4549  * external PHY auto advertised link speed.
4550  *
4551  * Returns error status for any failure
4552  **/
4553 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4554                                   ixgbe_link_speed speed,
4555                                   bool autoneg_wait_to_complete)
4556 {
4557         s32 status;
4558         ixgbe_link_speed force_speed;
4559
4560         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4561
4562         /* Setup internal/external PHY link speed to iXFI (10G), unless
4563          * only 1G is auto advertised then setup KX link.
4564          */
4565         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4566                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4567         else
4568                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4569
4570         /* If X552 and internal link mode is XFI, then setup XFI internal link.
4571          */
4572         if (hw->mac.type == ixgbe_mac_X550EM_x &&
4573             !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4574                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4575
4576                 if (status != IXGBE_SUCCESS)
4577                         return status;
4578         }
4579
4580         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4581 }
4582
4583 /**
4584  * ixgbe_check_link_t_X550em - Determine link and speed status
4585  * @hw: pointer to hardware structure
4586  * @speed: pointer to link speed
4587  * @link_up: true when link is up
4588  * @link_up_wait_to_complete: bool used to wait for link up or not
4589  *
4590  * Check that both the MAC and X557 external PHY have link.
4591  **/
4592 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4593                               bool *link_up, bool link_up_wait_to_complete)
4594 {
4595         u32 status;
4596         u16 i, autoneg_status = 0;
4597
4598         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4599                 return IXGBE_ERR_CONFIG;
4600
4601         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4602                                               link_up_wait_to_complete);
4603
4604         /* If check link fails or MAC link is not up, then return */
4605         if (status != IXGBE_SUCCESS || !(*link_up))
4606                 return status;
4607
4608         /* MAC link is up, so check external PHY link.
4609          * X557 PHY. Link status is latching low, and can only be used to detect
4610          * link drop, and not the current status of the link without performing
4611          * back-to-back reads.
4612          */
4613         for (i = 0; i < 2; i++) {
4614                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4615                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4616                                               &autoneg_status);
4617
4618                 if (status != IXGBE_SUCCESS)
4619                         return status;
4620         }
4621
4622         /* If external PHY link is not up, then indicate link not up */
4623         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4624                 *link_up = false;
4625
4626         return IXGBE_SUCCESS;
4627 }
4628
4629 /**
4630  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4631  *  @hw: pointer to hardware structure
4632  **/
4633 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4634 {
4635         s32 status;
4636
4637         status = ixgbe_reset_phy_generic(hw);
4638
4639         if (status != IXGBE_SUCCESS)
4640                 return status;
4641
4642         /* Configure Link Status Alarm and Temperature Threshold interrupts */
4643         return ixgbe_enable_lasi_ext_t_x550em(hw);
4644 }
4645
4646 /**
4647  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4648  *  @hw: pointer to hardware structure
4649  *  @led_idx: led number to turn on
4650  **/
4651 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4652 {
4653         u16 phy_data;
4654
4655         DEBUGFUNC("ixgbe_led_on_t_X550em");
4656
4657         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4658                 return IXGBE_ERR_PARAM;
4659
4660         /* To turn on the LED, set mode to ON. */
4661         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4662                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4663         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4664         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4665                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4666
4667         return IXGBE_SUCCESS;
4668 }
4669
4670 /**
4671  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4672  *  @hw: pointer to hardware structure
4673  *  @led_idx: led number to turn off
4674  **/
4675 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4676 {
4677         u16 phy_data;
4678
4679         DEBUGFUNC("ixgbe_led_off_t_X550em");
4680
4681         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4682                 return IXGBE_ERR_PARAM;
4683
4684         /* To turn on the LED, set mode to ON. */
4685         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4686                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4687         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4688         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4689                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4690
4691         return IXGBE_SUCCESS;
4692 }
4693
4694 /**
4695  *  ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware
4696  *  @hw: pointer to the HW structure
4697  *  @maj: driver version major number
4698  *  @min: driver version minor number
4699  *  @build: driver version build number
4700  *  @sub: driver version sub build number
4701  *  @len: length of driver_ver string
4702  *  @driver_ver: driver string
4703  *
4704  *  Sends driver version number to firmware through the manageability
4705  *  block.  On success return IXGBE_SUCCESS
4706  *  else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4707  *  semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4708  **/
4709 s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,
4710                               u8 build, u8 sub, u16 len, const char *driver_ver)
4711 {
4712         struct ixgbe_hic_drv_info2 fw_cmd;
4713         s32 ret_val = IXGBE_SUCCESS;
4714         int i;
4715
4716         DEBUGFUNC("ixgbe_set_fw_drv_ver_x550");
4717
4718         if ((len == 0) || (driver_ver == NULL) ||
4719            (len > sizeof(fw_cmd.driver_string)))
4720                 return IXGBE_ERR_INVALID_ARGUMENT;
4721
4722         fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4723         fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len;
4724         fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4725         fw_cmd.port_num = (u8)hw->bus.func;
4726         fw_cmd.ver_maj = maj;
4727         fw_cmd.ver_min = min;
4728         fw_cmd.ver_build = build;
4729         fw_cmd.ver_sub = sub;
4730         fw_cmd.hdr.checksum = 0;
4731         memcpy(fw_cmd.driver_string, driver_ver, len);
4732         fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4733                                 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4734
4735         for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4736                 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4737                                                        sizeof(fw_cmd),
4738                                                        IXGBE_HI_COMMAND_TIMEOUT,
4739                                                        true);
4740                 if (ret_val != IXGBE_SUCCESS)
4741                         continue;
4742
4743                 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4744                     FW_CEM_RESP_STATUS_SUCCESS)
4745                         ret_val = IXGBE_SUCCESS;
4746                 else
4747                         ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4748
4749                 break;
4750         }
4751
4752         return ret_val;
4753 }