drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  44
  45 /**
  46  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  47  *  @hw: pointer to hardware structure
  48  *
  49  *  Initialize the function pointers and assign the MAC type for X550.
  50  *  Does not touch the hardware.
  51  **/
  52 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  53 {
  54         struct ixgbe_mac_info *mac = &hw->mac;
  55         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  56         s32 ret_val;
  57
  58         DEBUGFUNC("ixgbe_init_ops_X550");
  59
  60         ret_val = ixgbe_init_ops_X540(hw);
  61         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  62         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  63         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  64         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  65         mac->ops.set_source_address_pruning =
  66                         ixgbe_set_source_address_pruning_X550;
  67         mac->ops.set_ethertype_anti_spoofing =
  68                         ixgbe_set_ethertype_anti_spoofing_X550;
  69
  70         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  71         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  72         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  73         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  74         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  75         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  76         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  77         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  78         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  79
  80         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  81         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  82         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  83         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  84         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  85         switch (hw->device_id) {
  86         case IXGBE_DEV_ID_X550EM_X_10G_T:
  87         case IXGBE_DEV_ID_X550EM_A_10G_T:
  88                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  89                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  90                 break;
  91         default:
  92                 break;
  93         }
  94         return ret_val;
  95 }
  96
  97 /**
  98  * ixgbe_read_cs4227 - Read CS4227 register
  99  * @hw: pointer to hardware structure
 100  * @reg: register number to write
 101  * @value: pointer to receive value read
 102  *
 103  * Returns status code
 104  **/
 105 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
 106 {
 107         return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
 108 }
 109
 110 /**
 111  * ixgbe_write_cs4227 - Write CS4227 register
 112  * @hw: pointer to hardware structure
 113  * @reg: register number to write
 114  * @value: value to write to register
 115  *
 116  * Returns status code
 117  **/
 118 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 119 {
 120         return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
 121 }
 122
 123 /**
 124  * ixgbe_read_pe - Read register from port expander
 125  * @hw: pointer to hardware structure
 126  * @reg: register number to read
 127  * @value: pointer to receive read value
 128  *
 129  * Returns status code
 130  **/
 131 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 132 {
 133         s32 status;
 134
 135         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 136         if (status != IXGBE_SUCCESS)
 137                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 138                               "port expander access failed with %d\n", status);
 139         return status;
 140 }
 141
 142 /**
 143  * ixgbe_write_pe - Write register to port expander
 144  * @hw: pointer to hardware structure
 145  * @reg: register number to write
 146  * @value: value to write
 147  *
 148  * Returns status code
 149  **/
 150 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 151 {
 152         s32 status;
 153
 154         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 155         if (status != IXGBE_SUCCESS)
 156                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 157                               "port expander access failed with %d\n", status);
 158         return status;
 159 }
 160
 161 /**
 162  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 163  * @hw: pointer to hardware structure
 164  *
 165  * This function assumes that the caller has acquired the proper semaphore.
 166  * Returns error code
 167  **/
 168 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 169 {
 170         s32 status;
 171         u32 retry;
 172         u16 value;
 173         u8 reg;
 174
 175         /* Trigger hard reset. */
 176         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 177         if (status != IXGBE_SUCCESS)
 178                 return status;
 179         reg |= IXGBE_PE_BIT1;
 180         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 181         if (status != IXGBE_SUCCESS)
 182                 return status;
 183
 184         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 185         if (status != IXGBE_SUCCESS)
 186                 return status;
 187         reg &= ~IXGBE_PE_BIT1;
 188         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 189         if (status != IXGBE_SUCCESS)
 190                 return status;
 191
 192         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 193         if (status != IXGBE_SUCCESS)
 194                 return status;
 195         reg &= ~IXGBE_PE_BIT1;
 196         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 197         if (status != IXGBE_SUCCESS)
 198                 return status;
 199
 200         usec_delay(IXGBE_CS4227_RESET_HOLD);
 201
 202         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 203         if (status != IXGBE_SUCCESS)
 204                 return status;
 205         reg |= IXGBE_PE_BIT1;
 206         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 207         if (status != IXGBE_SUCCESS)
 208                 return status;
 209
 210         /* Wait for the reset to complete. */
 211         msec_delay(IXGBE_CS4227_RESET_DELAY);
 212         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 213                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 214                                            &value);
 215                 if (status == IXGBE_SUCCESS &&
 216                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 217                         break;
 218                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 219         }
 220         if (retry == IXGBE_CS4227_RETRIES) {
 221                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 222                         "CS4227 reset did not complete.");
 223                 return IXGBE_ERR_PHY;
 224         }
 225
 226         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 227         if (status != IXGBE_SUCCESS ||
 228             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 229                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 230                         "CS4227 EEPROM did not load successfully.");
 231                 return IXGBE_ERR_PHY;
 232         }
 233
 234         return IXGBE_SUCCESS;
 235 }
 236
 237 /**
 238  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 239  * @hw: pointer to hardware structure
 240  **/
 241 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 242 {
 243         s32 status = IXGBE_SUCCESS;
 244         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 245         u16 value = 0;
 246         u8 retry;
 247
 248         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 249                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 250                 if (status != IXGBE_SUCCESS) {
 251                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 252                                 "semaphore failed with %d", status);
 253                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 254                         continue;
 255                 }
 256
 257                 /* Get status of reset flow. */
 258                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 259
 260                 if (status == IXGBE_SUCCESS &&
 261                     value == IXGBE_CS4227_RESET_COMPLETE)
 262                         goto out;
 263
 264                 if (status != IXGBE_SUCCESS ||
 265                     value != IXGBE_CS4227_RESET_PENDING)
 266                         break;
 267
 268                 /* Reset is pending. Wait and check again. */
 269                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 270                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 271         }
 272
 273         /* If still pending, assume other instance failed. */
 274         if (retry == IXGBE_CS4227_RETRIES) {
 275                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 276                 if (status != IXGBE_SUCCESS) {
 277                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 278                                       "semaphore failed with %d", status);
 279                         return;
 280                 }
 281         }
 282
 283         /* Reset the CS4227. */
 284         status = ixgbe_reset_cs4227(hw);
 285         if (status != IXGBE_SUCCESS) {
 286                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 287                         "CS4227 reset failed: %d", status);
 288                 goto out;
 289         }
 290
 291         /* Reset takes so long, temporarily release semaphore in case the
 292          * other driver instance is waiting for the reset indication.
 293          */
 294         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 295                            IXGBE_CS4227_RESET_PENDING);
 296         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 297         msec_delay(10);
 298         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 299         if (status != IXGBE_SUCCESS) {
 300                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 301                         "semaphore failed with %d", status);
 302                 return;
 303         }
 304
 305         /* Record completion for next time. */
 306         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 307                 IXGBE_CS4227_RESET_COMPLETE);
 308
 309 out:
 310         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 311         msec_delay(hw->eeprom.semaphore_delay);
 312 }
 313
 314 /**
 315  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 316  * @hw: pointer to hardware structure
 317  **/
 318 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 319 {
 320         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 321
 322         if (hw->bus.lan_id) {
 323                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 324                 esdp |= IXGBE_ESDP_SDP1_DIR;
 325         }
 326         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 327         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 328         IXGBE_WRITE_FLUSH(hw);
 329 }
 330
 331 /**
 332  * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
 333  * @hw: pointer to hardware structure
 334  * @reg_addr: 32 bit address of PHY register to read
 335  * @dev_type: always unused
 336  * @phy_data: Pointer to read data from PHY register
 337  */
 338 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 339                                      u32 dev_type, u16 *phy_data)
 340 {
 341         u32 i, data, command;
 342         UNREFERENCED_1PARAMETER(dev_type);
 343
 344         /* Setup and write the read command */
 345         command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 346                   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 347                   IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
 348                   IXGBE_MSCA_MDI_COMMAND;
 349
 350         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 351
 352         /* Check every 10 usec to see if the access completed.
 353          * The MDI Command bit will clear when the operation is
 354          * complete
 355          */
 356         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 357                 usec_delay(10);
 358
 359                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 360                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 361                         break;
 362         }
 363
 364         if (command & IXGBE_MSCA_MDI_COMMAND) {
 365                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 366                               "PHY read command did not complete.\n");
 367                 return IXGBE_ERR_PHY;
 368         }
 369
 370         /* Read operation is complete.  Get the data from MSRWD */
 371         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 372         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 373         *phy_data = (u16)data;
 374
 375         return IXGBE_SUCCESS;
 376 }
 377
 378 /**
 379  * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
 380  * @hw: pointer to hardware structure
 381  * @reg_addr: 32 bit PHY register to write
 382  * @dev_type: always unused
 383  * @phy_data: Data to write to the PHY register
 384  */
 385 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 386                                       u32 dev_type, u16 phy_data)
 387 {
 388         u32 i, command;
 389         UNREFERENCED_1PARAMETER(dev_type);
 390
 391         /* Put the data in the MDI single read and write data register*/
 392         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 393
 394         /* Setup and write the write command */
 395         command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 396                   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 397                   IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
 398                   IXGBE_MSCA_MDI_COMMAND;
 399
 400         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 401
 402         /* Check every 10 usec to see if the access completed.
 403          * The MDI Command bit will clear when the operation is
 404          * complete
 405          */
 406         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 407                 usec_delay(10);
 408
 409                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 410                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 411                         break;
 412         }
 413
 414         if (command & IXGBE_MSCA_MDI_COMMAND) {
 415                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 416                               "PHY write cmd didn't complete\n");
 417                 return IXGBE_ERR_PHY;
 418         }
 419
 420         return IXGBE_SUCCESS;
 421 }
 422
 423 /**
 424  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 425  * @hw: pointer to hardware structure
 426  *
 427  * Returns error code
 428  */
 429 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 430 {
 431         switch (hw->device_id) {
 432         case IXGBE_DEV_ID_X550EM_A_SFP:
 433                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
 434                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
 435                 if (hw->bus.lan_id)
 436                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 437                 else
 438                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 439                 return ixgbe_identify_module_generic(hw);
 440         case IXGBE_DEV_ID_X550EM_X_SFP:
 441                 /* set up for CS4227 usage */
 442                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 443                 ixgbe_setup_mux_ctl(hw);
 444                 ixgbe_check_cs4227(hw);
 445                 /* Fallthrough */
 446
 447         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 448                 return ixgbe_identify_module_generic(hw);
 449                 break;
 450         case IXGBE_DEV_ID_X550EM_X_KX4:
 451                 hw->phy.type = ixgbe_phy_x550em_kx4;
 452                 break;
 453         case IXGBE_DEV_ID_X550EM_X_KR:
 454         case IXGBE_DEV_ID_X550EM_A_KR:
 455         case IXGBE_DEV_ID_X550EM_A_KR_L:
 456                 hw->phy.type = ixgbe_phy_x550em_kr;
 457                 break;
 458         case IXGBE_DEV_ID_X550EM_A_10G_T:
 459                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
 460                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
 461        /* Fallthrough to ixgbe_identify_phy_generic */
 462         case IXGBE_DEV_ID_X550EM_A_1G_T:
 463         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 464         case IXGBE_DEV_ID_X550EM_X_1G_T:
 465         case IXGBE_DEV_ID_X550EM_X_10G_T:
 466                 return ixgbe_identify_phy_generic(hw);
 467         default:
 468                 break;
 469         }
 470         return IXGBE_SUCCESS;
 471 }
 472
 473 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 474                                      u32 device_type, u16 *phy_data)
 475 {
 476         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 477         return IXGBE_NOT_IMPLEMENTED;
 478 }
 479
 480 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 481                                       u32 device_type, u16 phy_data)
 482 {
 483         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 484         return IXGBE_NOT_IMPLEMENTED;
 485 }
 486
 487 /**
 488  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 489  * @hw: pointer to the hardware structure
 490  * @addr: I2C bus address to read from
 491  * @reg: I2C device register to read from
 492  * @val: pointer to location to receive read value
 493  *
 494  * Returns an error code on error.
 495  **/
 496 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 497                                            u16 reg, u16 *val)
 498 {
 499         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 500 }
 501
 502 /**
 503  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 504  * @hw: pointer to the hardware structure
 505  * @addr: I2C bus address to read from
 506  * @reg: I2C device register to read from
 507  * @val: pointer to location to receive read value
 508  *
 509  * Returns an error code on error.
 510  **/
 511 STATIC s32
 512 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 513                                          u16 reg, u16 *val)
 514 {
 515         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 516 }
 517
 518 /**
 519  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 520  * @hw: pointer to the hardware structure
 521  * @addr: I2C bus address to write to
 522  * @reg: I2C device register to write to
 523  * @val: value to write
 524  *
 525  * Returns an error code on error.
 526  **/
 527 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 528                                             u8 addr, u16 reg, u16 val)
 529 {
 530         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 531 }
 532
 533 /**
 534  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 535  * @hw: pointer to the hardware structure
 536  * @addr: I2C bus address to write to
 537  * @reg: I2C device register to write to
 538  * @val: value to write
 539  *
 540  * Returns an error code on error.
 541  **/
 542 STATIC s32
 543 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 544                                           u8 addr, u16 reg, u16 val)
 545 {
 546         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 547 }
 548
 549 /**
 550 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 551 *  @hw: pointer to hardware structure
 552 *
 553 *  Initialize the function pointers and for MAC type X550EM.
 554 *  Does not touch the hardware.
 555 **/
 556 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 557 {
 558         struct ixgbe_mac_info *mac = &hw->mac;
 559         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 560         struct ixgbe_phy_info *phy = &hw->phy;
 561         s32 ret_val;
 562
 563         DEBUGFUNC("ixgbe_init_ops_X550EM");
 564
 565         /* Similar to X550 so start there. */
 566         ret_val = ixgbe_init_ops_X550(hw);
 567
 568         /* Since this function eventually calls
 569          * ixgbe_init_ops_540 by design, we are setting
 570          * the pointers to NULL explicitly here to overwrite
 571          * the values being set in the x540 function.
 572          */
 573         /* Thermal sensor not supported in x550EM */
 574         mac->ops.get_thermal_sensor_data = NULL;
 575         mac->ops.init_thermal_sensor_thresh = NULL;
 576         mac->thermal_sensor_enabled = false;
 577
 578         /* FCOE not supported in x550EM */
 579         mac->ops.get_san_mac_addr = NULL;
 580         mac->ops.set_san_mac_addr = NULL;
 581         mac->ops.get_wwn_prefix = NULL;
 582         mac->ops.get_fcoe_boot_status = NULL;
 583
 584         /* IPsec not supported in x550EM */
 585         mac->ops.disable_sec_rx_path = NULL;
 586         mac->ops.enable_sec_rx_path = NULL;
 587
 588         /* AUTOC register is not present in x550EM. */
 589         mac->ops.prot_autoc_read = NULL;
 590         mac->ops.prot_autoc_write = NULL;
 591
 592         /* X550EM bus type is internal*/
 593         hw->bus.type = ixgbe_bus_type_internal;
 594         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 595
 596
 597         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 598         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 599         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 600         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 601         mac->ops.get_supported_physical_layer =
 602                                     ixgbe_get_supported_physical_layer_X550em;
 603
 604         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 605                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 606         else
 607                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 608
 609         switch (hw->device_id) {
 610         case IXGBE_DEV_ID_X550EM_X_KR:
 611         case IXGBE_DEV_ID_X550EM_A_KR:
 612         case IXGBE_DEV_ID_X550EM_A_KR_L:
 613                 break;
 614         default:
 615                 mac->ops.setup_eee = NULL;
 616         }
 617
 618         /* PHY */
 619         phy->ops.init = ixgbe_init_phy_ops_X550em;
 620         phy->ops.identify = ixgbe_identify_phy_x550em;
 621         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 622                 phy->ops.set_phy_power = NULL;
 623
 624
 625         /* EEPROM */
 626         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 627         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 628         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 629         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 630         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 631         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 632         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 633         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 634
 635         return ret_val;
 636 }
 637
 638 /**
 639 *  ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
 640 *  @hw: pointer to hardware structure
 641 *
 642 *  Initialize the function pointers and for MAC type X550EM_a.
 643 *  Does not touch the hardware.
 644 **/
 645 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
 646 {
 647         struct ixgbe_mac_info *mac = &hw->mac;
 648         s32 ret_val;
 649
 650         DEBUGFUNC("ixgbe_init_ops_X550EM_a");
 651
 652         /* Start with generic X550EM init */
 653         ret_val = ixgbe_init_ops_X550EM(hw);
 654
 655         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 656         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 657         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
 658         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
 659
 660         switch (mac->ops.get_media_type(hw)) {
 661         case ixgbe_media_type_fiber:
 662                 mac->ops.setup_fc = ixgbe_setup_fc_fiber_x550em_a;
 663                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
 664                 break;
 665         case ixgbe_media_type_backplane:
 666                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
 667                 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
 668                 break;
 669         default:
 670                 break;
 671         }
 672
 673         return ret_val;
 674 }
 675
 676 /**
 677 *  ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
 678 *  @hw: pointer to hardware structure
 679 *
 680 *  Initialize the function pointers and for MAC type X550EM_x.
 681 *  Does not touch the hardware.
 682 **/
 683 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
 684 {
 685         struct ixgbe_mac_info *mac = &hw->mac;
 686         struct ixgbe_link_info *link = &hw->link;
 687         s32 ret_val;
 688
 689         DEBUGFUNC("ixgbe_init_ops_X550EM_x");
 690
 691         /* Start with generic X550EM init */
 692         ret_val = ixgbe_init_ops_X550EM(hw);
 693
 694         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 695         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 696         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 697         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 698         link->ops.read_link = ixgbe_read_i2c_combined_generic;
 699         link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
 700         link->ops.write_link = ixgbe_write_i2c_combined_generic;
 701         link->ops.write_link_unlocked =
 702                                       ixgbe_write_i2c_combined_generic_unlocked;
 703         link->addr = IXGBE_CS4227;
 704
 705         return ret_val;
 706 }
 707
 708 /**
 709  *  ixgbe_dmac_config_X550
 710  *  @hw: pointer to hardware structure
 711  *
 712  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 713  *  When disabling dmac, dmac enable dmac bit is cleared.
 714  **/
 715 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 716 {
 717         u32 reg, high_pri_tc;
 718
 719         DEBUGFUNC("ixgbe_dmac_config_X550");
 720
 721         /* Disable DMA coalescing before configuring */
 722         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 723         reg &= ~IXGBE_DMACR_DMAC_EN;
 724         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 725
 726         /* Disable DMA Coalescing if the watchdog timer is 0 */
 727         if (!hw->mac.dmac_config.watchdog_timer)
 728                 goto out;
 729
 730         ixgbe_dmac_config_tcs_X550(hw);
 731
 732         /* Configure DMA Coalescing Control Register */
 733         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 734
 735         /* Set the watchdog timer in units of 40.96 usec */
 736         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 737         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 738
 739         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 740         /* If fcoe is enabled, set high priority traffic class */
 741         if (hw->mac.dmac_config.fcoe_en) {
 742                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 743                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 744                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 745         }
 746         reg |= IXGBE_DMACR_EN_MNG_IND;
 747
 748         /* Enable DMA coalescing after configuration */
 749         reg |= IXGBE_DMACR_DMAC_EN;
 750         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 751
 752 out:
 753         return IXGBE_SUCCESS;
 754 }
 755
 756 /**
 757  *  ixgbe_dmac_config_tcs_X550
 758  *  @hw: pointer to hardware structure
 759  *
 760  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 761  *  be cleared before configuring.
 762  **/
 763 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 764 {
 765         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 766
 767         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 768
 769         /* Configure DMA coalescing enabled */
 770         switch (hw->mac.dmac_config.link_speed) {
 771         case IXGBE_LINK_SPEED_10_FULL:
 772         case IXGBE_LINK_SPEED_100_FULL:
 773                 pb_headroom = IXGBE_DMACRXT_100M;
 774                 break;
 775         case IXGBE_LINK_SPEED_1GB_FULL:
 776                 pb_headroom = IXGBE_DMACRXT_1G;
 777                 break;
 778         default:
 779                 pb_headroom = IXGBE_DMACRXT_10G;
 780                 break;
 781         }
 782
 783         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 784                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 785
 786         /* Set the per Rx packet buffer receive threshold */
 787         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 788                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 789                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 790
 791                 if (tc < hw->mac.dmac_config.num_tcs) {
 792                         /* Get Rx PB size */
 793                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 794                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 795                                 IXGBE_RXPBSIZE_SHIFT;
 796
 797                         /* Calculate receive buffer threshold in kilobytes */
 798                         if (rx_pb_size > pb_headroom)
 799                                 rx_pb_size = rx_pb_size - pb_headroom;
 800                         else
 801                                 rx_pb_size = 0;
 802
 803                         /* Minimum of MFS shall be set for DMCTH */
 804                         reg |= (rx_pb_size > maxframe_size_kb) ?
 805                                 rx_pb_size : maxframe_size_kb;
 806                 }
 807                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 808         }
 809         return IXGBE_SUCCESS;
 810 }
 811
 812 /**
 813  *  ixgbe_dmac_update_tcs_X550
 814  *  @hw: pointer to hardware structure
 815  *
 816  *  Disables dmac, updates per TC settings, and then enables dmac.
 817  **/
 818 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 819 {
 820         u32 reg;
 821
 822         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 823
 824         /* Disable DMA coalescing before configuring */
 825         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 826         reg &= ~IXGBE_DMACR_DMAC_EN;
 827         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 828
 829         ixgbe_dmac_config_tcs_X550(hw);
 830
 831         /* Enable DMA coalescing after configuration */
 832         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 833         reg |= IXGBE_DMACR_DMAC_EN;
 834         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 835
 836         return IXGBE_SUCCESS;
 837 }
 838
 839 /**
 840  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 841  *  @hw: pointer to hardware structure
 842  *
 843  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 844  *  ixgbe_hw struct in order to set up EEPROM access.
 845  **/
 846 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 847 {
 848         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 849         u32 eec;
 850         u16 eeprom_size;
 851
 852         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 853
 854         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 855                 eeprom->semaphore_delay = 10;
 856                 eeprom->type = ixgbe_flash;
 857
 858                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 859                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 860                                     IXGBE_EEC_SIZE_SHIFT);
 861                 eeprom->word_size = 1 << (eeprom_size +
 862                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 863
 864                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 865                           eeprom->type, eeprom->word_size);
 866         }
 867
 868         return IXGBE_SUCCESS;
 869 }
 870
 871 /**
 872  * ixgbe_enable_eee_x550 - Enable EEE support
 873  * @hw: pointer to hardware structure
 874  */
 875 STATIC s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
 876 {
 877         u16 autoneg_eee_reg;
 878         u32 link_reg;
 879         s32 status;
 880
 881         if (hw->mac.type == ixgbe_mac_X550) {
 882                 /* Advertise EEE capability */
 883                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 884                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 885                                      &autoneg_eee_reg);
 886
 887                 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 888                                     IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 889                                     IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 890
 891                 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 892                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 893                                       autoneg_eee_reg);
 894                 return IXGBE_SUCCESS;
 895         }
 896
 897         switch (hw->device_id) {
 898         case IXGBE_DEV_ID_X550EM_X_KR:
 899         case IXGBE_DEV_ID_X550EM_A_KR:
 900         case IXGBE_DEV_ID_X550EM_A_KR_L:
 901                 status = hw->mac.ops.read_iosf_sb_reg(hw,
 902                                      IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 903                                      IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 904                 if (status != IXGBE_SUCCESS)
 905                         return status;
 906
 907                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 908                         IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 909
 910                 /* Don't advertise FEC capability when EEE enabled. */
 911                 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 912
 913                 status = hw->mac.ops.write_iosf_sb_reg(hw,
 914                                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 915                                       IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 916                 if (status != IXGBE_SUCCESS)
 917                         return status;
 918                 break;
 919         default:
 920                 break;
 921         }
 922
 923         return IXGBE_SUCCESS;
 924 }
 925
 926 /**
 927  * ixgbe_disable_eee_x550 - Disable EEE support
 928  * @hw: pointer to hardware structure
 929  */
 930 STATIC s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
 931 {
 932         u16 autoneg_eee_reg;
 933         u32 link_reg;
 934         s32 status;
 935
 936         if (hw->mac.type == ixgbe_mac_X550) {
 937                 /* Disable advertised EEE capability */
 938                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 939                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 940                                      &autoneg_eee_reg);
 941
 942                 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 943                                      IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 944                                      IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 945
 946                 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 947                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 948                                       autoneg_eee_reg);
 949                 return IXGBE_SUCCESS;
 950         }
 951
 952         switch (hw->device_id) {
 953         case IXGBE_DEV_ID_X550EM_X_KR:
 954         case IXGBE_DEV_ID_X550EM_A_KR:
 955         case IXGBE_DEV_ID_X550EM_A_KR_L:
 956                 status = hw->mac.ops.read_iosf_sb_reg(hw,
 957                                      IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 958                                      IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 959                 if (status != IXGBE_SUCCESS)
 960                         return status;
 961
 962                 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 963                               IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 964
 965                 /* Advertise FEC capability when EEE is disabled. */
 966                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 967
 968                 status = hw->mac.ops.write_iosf_sb_reg(hw,
 969                                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 970                                       IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 971                 if (status != IXGBE_SUCCESS)
 972                         return status;
 973                 break;
 974         default:
 975                 break;
 976         }
 977
 978         return IXGBE_SUCCESS;
 979 }
 980
 981 /**
 982  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 983  *  @hw: pointer to the HW structure
 984  *  @enable_eee: boolean flag to enable EEE
 985  *
 986  *  Enable/disable EEE based on enable_eee flag.
 987  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 988  *  are modified.
 989  *
 990  **/
 991 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 992 {
 993         s32 status;
 994         u32 eeer;
 995
 996         DEBUGFUNC("ixgbe_setup_eee_X550");
 997
 998         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 999         /* Enable or disable EEE per flag */
1000         if (enable_eee) {
1001                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1002
1003                 /* Not supported on first revision of X550EM_x. */
1004                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
1005                     !(IXGBE_FUSES0_REV_MASK &
1006                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
1007                         return IXGBE_SUCCESS;
1008                 status = ixgbe_enable_eee_x550(hw);
1009                 if (status)
1010                         return status;
1011         } else {
1012                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1013
1014                 status = ixgbe_disable_eee_x550(hw);
1015                 if (status)
1016                         return status;
1017         }
1018         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
1019
1020         return IXGBE_SUCCESS;
1021 }
1022
1023 /**
1024  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1025  * @hw: pointer to hardware structure
1026  * @enable: enable or disable source address pruning
1027  * @pool: Rx pool to set source address pruning for
1028  **/
1029 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1030                                            unsigned int pool)
1031 {
1032         u64 pfflp;
1033
1034         /* max rx pool is 63 */
1035         if (pool > 63)
1036                 return;
1037
1038         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1039         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1040
1041         if (enable)
1042                 pfflp |= (1ULL << pool);
1043         else
1044                 pfflp &= ~(1ULL << pool);
1045
1046         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1047         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1048 }
1049
1050 /**
1051  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1052  *  @hw: pointer to hardware structure
1053  *  @enable: enable or disable switch for Ethertype anti-spoofing
1054  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1055  *
1056  **/
1057 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1058                 bool enable, int vf)
1059 {
1060         int vf_target_reg = vf >> 3;
1061         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1062         u32 pfvfspoof;
1063
1064         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1065
1066         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1067         if (enable)
1068                 pfvfspoof |= (1 << vf_target_shift);
1069         else
1070                 pfvfspoof &= ~(1 << vf_target_shift);
1071
1072         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1073 }
1074
1075 /**
1076  * ixgbe_iosf_wait - Wait for IOSF command completion
1077  * @hw: pointer to hardware structure
1078  * @ctrl: pointer to location to receive final IOSF control value
1079  *
1080  * Returns failing status on timeout
1081  *
1082  * Note: ctrl can be NULL if the IOSF control register value is not needed
1083  **/
1084 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1085 {
1086         u32 i, command = 0;
1087
1088         /* Check every 10 usec to see if the address cycle completed.
1089          * The SB IOSF BUSY bit will clear when the operation is
1090          * complete
1091          */
1092         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1093                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1094                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1095                         break;
1096                 usec_delay(10);
1097         }
1098         if (ctrl)
1099                 *ctrl = command;
1100         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1101                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1102                 return IXGBE_ERR_PHY;
1103         }
1104
1105         return IXGBE_SUCCESS;
1106 }
1107
1108 /**
1109  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
1110  *  device
1111  *  @hw: pointer to hardware structure
1112  *  @reg_addr: 32 bit PHY register to write
1113  *  @device_type: 3 bit device type
1114  *  @data: Data to write to the register
1115  **/
1116 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1117                             u32 device_type, u32 data)
1118 {
1119         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1120         u32 command, error;
1121         s32 ret;
1122
1123         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1124         if (ret != IXGBE_SUCCESS)
1125                 return ret;
1126
1127         ret = ixgbe_iosf_wait(hw, NULL);
1128         if (ret != IXGBE_SUCCESS)
1129                 goto out;
1130
1131         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1132                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1133
1134         /* Write IOSF control register */
1135         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1136
1137         /* Write IOSF data register */
1138         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1139
1140         ret = ixgbe_iosf_wait(hw, &command);
1141
1142         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1143                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1144                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1145                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1146                               "Failed to write, error %x\n", error);
1147                 ret = IXGBE_ERR_PHY;
1148         }
1149
1150 out:
1151         ixgbe_release_swfw_semaphore(hw, gssr);
1152         return ret;
1153 }
1154
1155 /**
1156  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
1157  *  device
1158  *  @hw: pointer to hardware structure
1159  *  @reg_addr: 32 bit PHY register to write
1160  *  @device_type: 3 bit device type
1161  *  @phy_data: Pointer to read data from the register
1162  **/
1163 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1164                            u32 device_type, u32 *data)
1165 {
1166         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1167         u32 command, error;
1168         s32 ret;
1169
1170         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1171         if (ret != IXGBE_SUCCESS)
1172                 return ret;
1173
1174         ret = ixgbe_iosf_wait(hw, NULL);
1175         if (ret != IXGBE_SUCCESS)
1176                 goto out;
1177
1178         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1179                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1180
1181         /* Write IOSF control register */
1182         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1183
1184         ret = ixgbe_iosf_wait(hw, &command);
1185
1186         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1187                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1188                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1189                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1190                                 "Failed to read, error %x\n", error);
1191                 ret = IXGBE_ERR_PHY;
1192         }
1193
1194         if (ret == IXGBE_SUCCESS)
1195                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1196
1197 out:
1198         ixgbe_release_swfw_semaphore(hw, gssr);
1199         return ret;
1200 }
1201
1202 /**
1203  * ixgbe_get_phy_token - Get the token for shared phy access
1204  * @hw: Pointer to hardware structure
1205  */
1206
1207 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1208 {
1209         struct ixgbe_hic_phy_token_req token_cmd;
1210         s32 status;
1211
1212         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1213         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1214         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1215         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1216         token_cmd.port_number = hw->bus.lan_id;
1217         token_cmd.command_type = FW_PHY_TOKEN_REQ;
1218         token_cmd.pad = 0;
1219         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1220                                               sizeof(token_cmd),
1221                                               IXGBE_HI_COMMAND_TIMEOUT,
1222                                               true);
1223         if (status)
1224                 return status;
1225         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1226                 return IXGBE_SUCCESS;
1227         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1228                 return IXGBE_ERR_FW_RESP_INVALID;
1229
1230         return IXGBE_ERR_TOKEN_RETRY;
1231 }
1232
1233 /**
1234  * ixgbe_put_phy_token - Put the token for shared phy access
1235  * @hw: Pointer to hardware structure
1236  */
1237
1238 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1239 {
1240         struct ixgbe_hic_phy_token_req token_cmd;
1241         s32 status;
1242
1243         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1244         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1245         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1246         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1247         token_cmd.port_number = hw->bus.lan_id;
1248         token_cmd.command_type = FW_PHY_TOKEN_REL;
1249         token_cmd.pad = 0;
1250         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1251                                               sizeof(token_cmd),
1252                                               IXGBE_HI_COMMAND_TIMEOUT,
1253                                               true);
1254         if (status)
1255                 return status;
1256         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1257                 return IXGBE_SUCCESS;
1258
1259         DEBUGOUT("Put PHY Token host interface command failed");
1260         return IXGBE_ERR_FW_RESP_INVALID;
1261 }
1262
1263 /**
1264  *  ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1265  *  of the IOSF device
1266  *  @hw: pointer to hardware structure
1267  *  @reg_addr: 32 bit PHY register to write
1268  *  @device_type: 3 bit device type
1269  *  @data: Data to write to the register
1270  **/
1271 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1272                                   u32 device_type, u32 data)
1273 {
1274         struct ixgbe_hic_internal_phy_req write_cmd;
1275         s32 status;
1276         UNREFERENCED_1PARAMETER(device_type);
1277
1278         memset(&write_cmd, 0, sizeof(write_cmd));
1279         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1280         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1281         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1282         write_cmd.port_number = hw->bus.lan_id;
1283         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1284         write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1285         write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1286
1287         status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1288                                               sizeof(write_cmd),
1289                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1290
1291         return status;
1292 }
1293
1294 /**
1295  *  ixgbe_read_iosf_sb_reg_x550a - Writes a value to specified register
1296  *  of the IOSF device.
1297  *  @hw: pointer to hardware structure
1298  *  @reg_addr: 32 bit PHY register to write
1299  *  @device_type: 3 bit device type
1300  *  @data: Pointer to read data from the register
1301  **/
1302 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1303                                  u32 device_type, u32 *data)
1304 {
1305         union {
1306                 struct ixgbe_hic_internal_phy_req cmd;
1307                 struct ixgbe_hic_internal_phy_resp rsp;
1308         } hic;
1309         s32 status;
1310         UNREFERENCED_1PARAMETER(device_type);
1311
1312         memset(&hic, 0, sizeof(hic));
1313         hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1314         hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1315         hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1316         hic.cmd.port_number = hw->bus.lan_id;
1317         hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1318         hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1319
1320         status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1321                                               sizeof(hic.cmd),
1322                                               IXGBE_HI_COMMAND_TIMEOUT, true);
1323
1324         /* Extract the register value from the response. */
1325         *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1326
1327         return status;
1328 }
1329
1330 /**
1331  *  ixgbe_disable_mdd_X550
1332  *  @hw: pointer to hardware structure
1333  *
1334  *  Disable malicious driver detection
1335  **/
1336 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1337 {
1338         u32 reg;
1339
1340         DEBUGFUNC("ixgbe_disable_mdd_X550");
1341
1342         /* Disable MDD for TX DMA and interrupt */
1343         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1344         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1345         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1346
1347         /* Disable MDD for RX and interrupt */
1348         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1349         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1350         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1351 }
1352
1353 /**
1354  *  ixgbe_enable_mdd_X550
1355  *  @hw: pointer to hardware structure
1356  *
1357  *  Enable malicious driver detection
1358  **/
1359 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1360 {
1361         u32 reg;
1362
1363         DEBUGFUNC("ixgbe_enable_mdd_X550");
1364
1365         /* Enable MDD for TX DMA and interrupt */
1366         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1367         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1368         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1369
1370         /* Enable MDD for RX and interrupt */
1371         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1372         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1373         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1374 }
1375
1376 /**
1377  *  ixgbe_restore_mdd_vf_X550
1378  *  @hw: pointer to hardware structure
1379  *  @vf: vf index
1380  *
1381  *  Restore VF that was disabled during malicious driver detection event
1382  **/
1383 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1384 {
1385         u32 idx, reg, num_qs, start_q, bitmask;
1386
1387         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1388
1389         /* Map VF to queues */
1390         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1391         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1392         case IXGBE_MRQC_VMDQRT8TCEN:
1393                 num_qs = 8;  /* 16 VFs / pools */
1394                 bitmask = 0x000000FF;
1395                 break;
1396         case IXGBE_MRQC_VMDQRSS32EN:
1397         case IXGBE_MRQC_VMDQRT4TCEN:
1398                 num_qs = 4;  /* 32 VFs / pools */
1399                 bitmask = 0x0000000F;
1400                 break;
1401         default:            /* 64 VFs / pools */
1402                 num_qs = 2;
1403                 bitmask = 0x00000003;
1404                 break;
1405         }
1406         start_q = vf * num_qs;
1407
1408         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1409         idx = start_q / 32;
1410         reg = 0;
1411         reg |= (bitmask << (start_q % 32));
1412         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1413         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1414 }
1415
1416 /**
1417  *  ixgbe_mdd_event_X550
1418  *  @hw: pointer to hardware structure
1419  *  @vf_bitmap: vf bitmap of malicious vfs
1420  *
1421  *  Handle malicious driver detection event.
1422  **/
1423 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1424 {
1425         u32 wqbr;
1426         u32 i, j, reg, q, shift, vf, idx;
1427
1428         DEBUGFUNC("ixgbe_mdd_event_X550");
1429
1430         /* figure out pool size for mapping to vf's */
1431         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1432         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1433         case IXGBE_MRQC_VMDQRT8TCEN:
1434                 shift = 3;  /* 16 VFs / pools */
1435                 break;
1436         case IXGBE_MRQC_VMDQRSS32EN:
1437         case IXGBE_MRQC_VMDQRT4TCEN:
1438                 shift = 2;  /* 32 VFs / pools */
1439                 break;
1440         default:
1441                 shift = 1;  /* 64 VFs / pools */
1442                 break;
1443         }
1444
1445         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1446         for (i = 0; i < 4; i++) {
1447                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1448                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1449
1450                 if (!wqbr)
1451                         continue;
1452
1453                 /* Get malicious queue */
1454                 for (j = 0; j < 32 && wqbr; j++) {
1455
1456                         if (!(wqbr & (1 << j)))
1457                                 continue;
1458
1459                         /* Get queue from bitmask */
1460                         q = j + (i * 32);
1461
1462                         /* Map queue to vf */
1463                         vf = (q >> shift);
1464
1465                         /* Set vf bit in vf_bitmap */
1466                         idx = vf / 32;
1467                         vf_bitmap[idx] |= (1 << (vf % 32));
1468                         wqbr &= ~(1 << j);
1469                 }
1470         }
1471 }
1472
1473 /**
1474  *  ixgbe_get_media_type_X550em - Get media type
1475  *  @hw: pointer to hardware structure
1476  *
1477  *  Returns the media type (fiber, copper, backplane)
1478  */
1479 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1480 {
1481         enum ixgbe_media_type media_type;
1482
1483         DEBUGFUNC("ixgbe_get_media_type_X550em");
1484
1485         /* Detect if there is a copper PHY attached. */
1486         switch (hw->device_id) {
1487         case IXGBE_DEV_ID_X550EM_X_KR:
1488         case IXGBE_DEV_ID_X550EM_X_KX4:
1489         case IXGBE_DEV_ID_X550EM_A_KR:
1490         case IXGBE_DEV_ID_X550EM_A_KR_L:
1491                 media_type = ixgbe_media_type_backplane;
1492                 break;
1493         case IXGBE_DEV_ID_X550EM_X_SFP:
1494         case IXGBE_DEV_ID_X550EM_A_SFP:
1495         case IXGBE_DEV_ID_X550EM_A_SFP_N:
1496         case IXGBE_DEV_ID_X550EM_A_QSFP:
1497         case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1498                 media_type = ixgbe_media_type_fiber;
1499                 break;
1500         case IXGBE_DEV_ID_X550EM_X_1G_T:
1501         case IXGBE_DEV_ID_X550EM_X_10G_T:
1502         case IXGBE_DEV_ID_X550EM_A_10G_T:
1503                 media_type = ixgbe_media_type_copper;
1504                 break;
1505         case IXGBE_DEV_ID_X550EM_A_SGMII:
1506         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1507                 media_type = ixgbe_media_type_backplane;
1508                 hw->phy.type = ixgbe_phy_sgmii;
1509                 break;
1510         case IXGBE_DEV_ID_X550EM_A_1G_T:
1511         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1512                 media_type = ixgbe_media_type_copper;
1513                 break;
1514         default:
1515                 media_type = ixgbe_media_type_unknown;
1516                 break;
1517         }
1518         return media_type;
1519 }
1520
1521 /**
1522  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1523  *  @hw: pointer to hardware structure
1524  *  @linear: true if SFP module is linear
1525  */
1526 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1527 {
1528         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1529
1530         switch (hw->phy.sfp_type) {
1531         case ixgbe_sfp_type_not_present:
1532                 return IXGBE_ERR_SFP_NOT_PRESENT;
1533         case ixgbe_sfp_type_da_cu_core0:
1534         case ixgbe_sfp_type_da_cu_core1:
1535                 *linear = true;
1536                 break;
1537         case ixgbe_sfp_type_srlr_core0:
1538         case ixgbe_sfp_type_srlr_core1:
1539         case ixgbe_sfp_type_da_act_lmt_core0:
1540         case ixgbe_sfp_type_da_act_lmt_core1:
1541         case ixgbe_sfp_type_1g_sx_core0:
1542         case ixgbe_sfp_type_1g_sx_core1:
1543         case ixgbe_sfp_type_1g_lx_core0:
1544         case ixgbe_sfp_type_1g_lx_core1:
1545                 *linear = false;
1546                 break;
1547         case ixgbe_sfp_type_unknown:
1548         case ixgbe_sfp_type_1g_cu_core0:
1549         case ixgbe_sfp_type_1g_cu_core1:
1550         default:
1551                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1552         }
1553
1554         return IXGBE_SUCCESS;
1555 }
1556
1557 /**
1558  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1559  *  @hw: pointer to hardware structure
1560  *
1561  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1562  **/
1563 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1564 {
1565         s32 status;
1566         bool linear;
1567
1568         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1569
1570         status = ixgbe_identify_module_generic(hw);
1571
1572         if (status != IXGBE_SUCCESS)
1573                 return status;
1574
1575         /* Check if SFP module is supported */
1576         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1577
1578         return status;
1579 }
1580
1581 /**
1582  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1583  *  @hw: pointer to hardware structure
1584  */
1585 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1586 {
1587         s32 status;
1588         bool linear;
1589
1590         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1591
1592         /* Check if SFP module is supported */
1593         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1594
1595         if (status != IXGBE_SUCCESS)
1596                 return status;
1597
1598         ixgbe_init_mac_link_ops_X550em(hw);
1599         hw->phy.ops.reset = NULL;
1600
1601         return IXGBE_SUCCESS;
1602 }
1603
1604 /**
1605  * ixgbe_setup_sgmii - Set up link for sgmii
1606  * @hw: pointer to hardware structure
1607  */
1608 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1609                              bool autoneg_wait)
1610 {
1611         struct ixgbe_mac_info *mac = &hw->mac;
1612         u32 lval, sval;
1613         s32 rc;
1614
1615         rc = mac->ops.read_iosf_sb_reg(hw,
1616                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1617                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1618         if (rc)
1619                 return rc;
1620
1621         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1622         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1623         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1624         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1625         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1626         rc = mac->ops.write_iosf_sb_reg(hw,
1627                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1628                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1629         if (rc)
1630                 return rc;
1631
1632         rc = mac->ops.read_iosf_sb_reg(hw,
1633                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1634                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1635         if (rc)
1636                 return rc;
1637
1638         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1639         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1640         rc = mac->ops.write_iosf_sb_reg(hw,
1641                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1642                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1643         if (rc)
1644                 return rc;
1645
1646         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1647         rc = mac->ops.write_iosf_sb_reg(hw,
1648                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1649                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1650         if (rc)
1651                 return rc;
1652
1653         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1654 }
1655
1656  /**
1657  * ixgbe_setup_sgmii_m88 - Set up link for sgmii with Marvell PHYs
1658  * @hw: pointer to hardware structure
1659  */
1660 STATIC s32 ixgbe_setup_sgmii_m88(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1661                                  bool autoneg_wait)
1662 {
1663         struct ixgbe_mac_info *mac = &hw->mac;
1664         u32 lval, sval;
1665         s32 rc;
1666
1667         rc = mac->ops.read_iosf_sb_reg(hw,
1668                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1669                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1670         if (rc)
1671                 return rc;
1672
1673         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1674         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1675         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1676         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1677         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1678         rc = mac->ops.write_iosf_sb_reg(hw,
1679                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1680                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1681         if (rc)
1682                 return rc;
1683
1684         rc = mac->ops.read_iosf_sb_reg(hw,
1685                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1686                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1687         if (rc)
1688                 return rc;
1689
1690         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1691         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1692         rc = mac->ops.write_iosf_sb_reg(hw,
1693                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1694                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1695         if (rc)
1696                 return rc;
1697
1698         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1699         rc = mac->ops.write_iosf_sb_reg(hw,
1700                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1701                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1702         if (rc)
1703                 return rc;
1704
1705         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1706 }
1707
1708 /**
1709  * ixgbe_check_link_m88 - Poll PHY for link
1710  * @hw: pointer to hardware structure
1711  * @speed: pointer to link speed
1712  * @link_up: true when link is up
1713  * @link_up_wait: bool indicating whether to wait for link
1714  *
1715  * Check that both the MAC and PHY have link.
1716  */
1717 static s32
1718 ixgbe_check_link_m88(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1719                      bool *link_up, bool link_up_wait)
1720 {
1721         u16 reg;
1722         s32 rc;
1723         u32 i;
1724
1725         rc = ixgbe_check_mac_link_generic(hw, speed, link_up, link_up_wait);
1726         if (rc || !*link_up)
1727                 return rc;
1728
1729         rc = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_PHY_SPEC_STATUS, 0, &reg);
1730
1731         /* MAC link is up, so check external PHY link */
1732         *link_up = !!(reg & IXGBE_M88E1500_PHY_SPEC_STATUS_LINK);
1733
1734         if (link_up_wait) {
1735                 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
1736                         if (!rc &&
1737                             (reg & IXGBE_M88E1500_PHY_SPEC_STATUS_LINK)) {
1738                                 *link_up = true;
1739                                 break;
1740                         }
1741                         *link_up = false;
1742                         msec_delay(100);
1743                         rc = hw->phy.ops.read_reg(hw,
1744                                                  IXGBE_M88E1500_PHY_SPEC_STATUS,
1745                                                  0, &reg);
1746                 }
1747         }
1748
1749 #define M88_SPEED(x) (IXGBE_M88E1500_PHY_SPEC_STATUS_RESOLVED  | \
1750                       IXGBE_M88E1500_PHY_SPEC_STATUS_DUPLEX     | \
1751                       ((IXGBE_M88E1500_PHY_SPEC_STATUS_SPEED_##x) <<\
1752                         IXGBE_M88E1500_PHY_SPEC_STATUS_SPEED_SHIFT))
1753
1754         reg &= M88_SPEED(MASK);
1755         switch (reg) {
1756         case M88_SPEED(10):
1757                 *speed = IXGBE_LINK_SPEED_10_FULL;
1758                 break;
1759         case M88_SPEED(100):
1760                 *speed = IXGBE_LINK_SPEED_100_FULL;
1761                 break;
1762         case M88_SPEED(1000):
1763                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1764                 break;
1765         default:
1766                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
1767                 break;
1768         }
1769 #undef M88_SPEED
1770
1771         return rc;
1772 }
1773
1774 /**
1775  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1776  *  @hw: pointer to hardware structure
1777  */
1778 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1779 {
1780         struct ixgbe_mac_info *mac = &hw->mac;
1781
1782         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1783
1784         switch (hw->mac.ops.get_media_type(hw)) {
1785         case ixgbe_media_type_fiber:
1786                 /* CS4227 does not support autoneg, so disable the laser control
1787                  * functions for SFP+ fiber
1788                  */
1789                 mac->ops.disable_tx_laser = NULL;
1790                 mac->ops.enable_tx_laser = NULL;
1791                 mac->ops.flap_tx_laser = NULL;
1792                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1793                 mac->ops.set_rate_select_speed =
1794                                         ixgbe_set_soft_rate_select_speed;
1795                 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1796                     (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1797                         mac->ops.setup_mac_link =
1798                                 ixgbe_setup_mac_link_sfp_x550a;
1799                 else
1800                         mac->ops.setup_mac_link =
1801                                 ixgbe_setup_mac_link_sfp_x550em;
1802                 break;
1803         case ixgbe_media_type_copper:
1804                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
1805                     hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
1806                         mac->ops.setup_link = ixgbe_setup_sgmii_m88;
1807                         mac->ops.check_link = ixgbe_check_link_m88;
1808                 } else {
1809                         mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1810                         mac->ops.check_link = ixgbe_check_link_t_X550em;
1811                 }
1812                 break;
1813         case ixgbe_media_type_backplane:
1814                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1815                     hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1816                         mac->ops.setup_link = ixgbe_setup_sgmii;
1817                 break;
1818         default:
1819                 break;
1820         }
1821 }
1822
1823 /**
1824  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1825  *  @hw: pointer to hardware structure
1826  *  @speed: pointer to link speed
1827  *  @autoneg: true when autoneg or autotry is enabled
1828  */
1829 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1830                                        ixgbe_link_speed *speed,
1831                                        bool *autoneg)
1832 {
1833         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1834
1835         /* SFP */
1836         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1837
1838                 /* CS4227 SFP must not enable auto-negotiation */
1839                 *autoneg = false;
1840
1841                 /* Check if 1G SFP module. */
1842                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1843                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1844                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1845                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1846                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1847                         return IXGBE_SUCCESS;
1848                 }
1849
1850                 /* Link capabilities are based on SFP */
1851                 if (hw->phy.multispeed_fiber)
1852                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1853                                  IXGBE_LINK_SPEED_1GB_FULL;
1854                 else
1855                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1856         } else {
1857                 switch (hw->phy.type) {
1858                 case ixgbe_phy_m88:
1859                         *speed = IXGBE_LINK_SPEED_1GB_FULL |
1860                                  IXGBE_LINK_SPEED_100_FULL |
1861                                  IXGBE_LINK_SPEED_10_FULL;
1862                         break;
1863                 case ixgbe_phy_sgmii:
1864                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1865                         break;
1866                 default:
1867                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1868                                  IXGBE_LINK_SPEED_1GB_FULL;
1869                         break;
1870                 }
1871                 *autoneg = true;
1872         }
1873
1874         return IXGBE_SUCCESS;
1875 }
1876
1877 /**
1878  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1879  * @hw: pointer to hardware structure
1880  * @lsc: pointer to boolean flag which indicates whether external Base T
1881  *       PHY interrupt is lsc
1882  *
1883  * Determime if external Base T PHY interrupt cause is high temperature
1884  * failure alarm or link status change.
1885  *
1886  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1887  * failure alarm, else return PHY access status.
1888  */
1889 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1890 {
1891         u32 status;
1892         u16 reg;
1893
1894         *lsc = false;
1895
1896         /* Vendor alarm triggered */
1897         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1898                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1899                                       &reg);
1900
1901         if (status != IXGBE_SUCCESS ||
1902             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1903                 return status;
1904
1905         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1906         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1907                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1908                                       &reg);
1909
1910         if (status != IXGBE_SUCCESS ||
1911             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1912             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1913                 return status;
1914
1915         /* Global alarm triggered */
1916         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1917                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1918                                       &reg);
1919
1920         if (status != IXGBE_SUCCESS)
1921                 return status;
1922
1923         /* If high temperature failure, then return over temp error and exit */
1924         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1925                 /* power down the PHY in case the PHY FW didn't already */
1926                 ixgbe_set_copper_phy_power(hw, false);
1927                 return IXGBE_ERR_OVERTEMP;
1928         } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1929                 /*  device fault alarm triggered */
1930                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1931                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1932                                           &reg);
1933
1934                 if (status != IXGBE_SUCCESS)
1935                         return status;
1936
1937                 /* if device fault was due to high temp alarm handle and exit */
1938                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1939                         /* power down the PHY in case the PHY FW didn't */
1940                         ixgbe_set_copper_phy_power(hw, false);
1941                         return IXGBE_ERR_OVERTEMP;
1942                 }
1943         }
1944
1945         /* Vendor alarm 2 triggered */
1946         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1947                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1948
1949         if (status != IXGBE_SUCCESS ||
1950             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1951                 return status;
1952
1953         /* link connect/disconnect event occurred */
1954         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1955                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1956
1957         if (status != IXGBE_SUCCESS)
1958                 return status;
1959
1960         /* Indicate LSC */
1961         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1962                 *lsc = true;
1963
1964         return IXGBE_SUCCESS;
1965 }
1966
1967 /**
1968  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1969  * @hw: pointer to hardware structure
1970  *
1971  * Enable link status change and temperature failure alarm for the external
1972  * Base T PHY
1973  *
1974  * Returns PHY access status
1975  */
1976 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1977 {
1978         u32 status;
1979         u16 reg;
1980         bool lsc;
1981
1982         /* Clear interrupt flags */
1983         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1984
1985         /* Enable link status change alarm */
1986         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1987                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1988
1989         if (status != IXGBE_SUCCESS)
1990                 return status;
1991
1992         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1993
1994         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1995                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1996
1997         if (status != IXGBE_SUCCESS)
1998                 return status;
1999
2000         /* Enable high temperature failure and global fault alarms */
2001         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2002                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2003                                       &reg);
2004
2005         if (status != IXGBE_SUCCESS)
2006                 return status;
2007
2008         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2009                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2010
2011         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2012                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2013                                        reg);
2014
2015         if (status != IXGBE_SUCCESS)
2016                 return status;
2017
2018         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2019         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2020                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2021                                       &reg);
2022
2023         if (status != IXGBE_SUCCESS)
2024                 return status;
2025
2026         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2027                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2028
2029         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2030                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2031                                        reg);
2032
2033         if (status != IXGBE_SUCCESS)
2034                 return status;
2035
2036         /* Enable chip-wide vendor alarm */
2037         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2038                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2039                                       &reg);
2040
2041         if (status != IXGBE_SUCCESS)
2042                 return status;
2043
2044         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2045
2046         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2047                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2048                                        reg);
2049
2050         return status;
2051 }
2052
2053 /**
2054  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2055  *  @hw: pointer to hardware structure
2056  *  @speed: link speed
2057  *
2058  *  Configures the integrated KR PHY.
2059  **/
2060 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2061                                        ixgbe_link_speed speed)
2062 {
2063         s32 status;
2064         u32 reg_val;
2065
2066         status = hw->mac.ops.read_iosf_sb_reg(hw,
2067                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2068                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2069         if (status)
2070                 return status;
2071
2072         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2073         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2074                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2075
2076         /* Advertise 10G support. */
2077         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2078                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2079
2080         /* Advertise 1G support. */
2081         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2082                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2083
2084         /* Restart auto-negotiation. */
2085         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2086         status = hw->mac.ops.write_iosf_sb_reg(hw,
2087                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2088                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2089
2090         return status;
2091 }
2092
2093 /**
2094  * ixgbe_setup_m88 - setup m88 PHY
2095  * @hw: pointer to hardware structure
2096  */
2097 STATIC s32 ixgbe_setup_m88(struct ixgbe_hw *hw)
2098 {
2099         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2100         u16 reg;
2101         s32 rc;
2102
2103         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2104                 return IXGBE_SUCCESS;
2105
2106         rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2107         if (rc)
2108                 return rc;
2109
2110         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2111         if (rc)
2112                 goto out;
2113         if (reg & IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN) {
2114                 reg &= ~IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN;
2115                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2116                                           reg);
2117         }
2118
2119         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, &reg);
2120         if (rc)
2121                 goto out;
2122         if (reg & IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN) {
2123                 reg &= ~IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN;
2124                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0,
2125                                           reg);
2126         }
2127
2128         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 2);
2129         if (rc)
2130                 goto out;
2131
2132         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2133                                       &reg);
2134         if (rc)
2135                 goto out;
2136         if (reg & IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN) {
2137                 reg &= ~IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN;
2138                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2139                                           reg);
2140                 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2141                                                0);
2142                 if (rc)
2143                         goto out;
2144                 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2145                                               &reg);
2146                 if (rc)
2147                         goto out;
2148                 reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2149                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2150                                           reg);
2151                 usec_delay(50);
2152         } else {
2153                 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2154                                                0);
2155                 if (rc)
2156                         goto out;
2157         }
2158
2159         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2160         if (rc)
2161                 goto out;
2162
2163         if (!(reg & IXGBE_M88E1500_COPPER_CTRL_AN_EN)) {
2164                 reg |= IXGBE_M88E1500_COPPER_CTRL_AN_EN;
2165                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2166                                           reg);
2167         }
2168
2169         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, &reg);
2170         if (rc)
2171                 goto out;
2172         reg &= ~IXGBE_M88E1500_1000T_CTRL_HALF_DUPLEX;
2173         reg &= ~IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2174         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
2175                 reg |= IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2176         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, reg);
2177
2178         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, &reg);
2179         if (rc)
2180                 goto out;
2181         reg &= ~IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
2182         reg &= ~IXGBE_M88E1500_COPPER_AN_PAUSE;
2183         reg &= ~IXGBE_M88E1500_COPPER_AN_T4;
2184         reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_FD;
2185         reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_HD;
2186         reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_FD;
2187         reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_HD;
2188         switch (hw->fc.current_mode) {
2189         case ixgbe_fc_full:
2190                 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
2191                 break;
2192         case ixgbe_fc_rx_pause:
2193                 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
2194                 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
2195                 break;
2196         case ixgbe_fc_tx_pause:
2197                 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
2198                 break;
2199         default:
2200                 break;
2201         }
2202
2203         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
2204                 reg |= IXGBE_M88E1500_COPPER_AN_100TX_FD;
2205         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL)
2206                 reg |= IXGBE_M88E1500_COPPER_AN_10TX_FD;
2207         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, reg);
2208
2209         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2210         if (rc)
2211                 goto out;
2212         reg |= IXGBE_M88E1500_COPPER_CTRL_RESTART_AN;
2213         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2214
2215
2216         hw->mac.ops.release_swfw_sync(hw, mask);
2217         return rc;
2218
2219 out:
2220         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2221         hw->mac.ops.release_swfw_sync(hw, mask);
2222         return rc;
2223 }
2224
2225 /**
2226  * ixgbe_reset_phy_m88e1500 - Reset m88e1500 PHY
2227  * @hw: pointer to hardware structure
2228  *
2229  * The PHY token must be held when calling this function.
2230  */
2231 static s32 ixgbe_reset_phy_m88e1500(struct ixgbe_hw *hw)
2232 {
2233         u16 reg;
2234         s32 rc;
2235
2236         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2237         if (rc)
2238                 return rc;
2239
2240         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2241         if (rc)
2242                 return rc;
2243
2244         reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2245         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2246
2247         usec_delay(10);
2248
2249         return rc;
2250 }
2251
2252 /**
2253  * ixgbe_reset_phy_m88e1543 - Reset m88e1543 PHY
2254  * @hw: pointer to hardware structure
2255  *
2256  * The PHY token must be held when calling this function.
2257  */
2258 static s32 ixgbe_reset_phy_m88e1543(struct ixgbe_hw *hw)
2259 {
2260         return hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2261 }
2262
2263 /**
2264  * ixgbe_reset_phy_m88 - Reset m88 PHY
2265  * @hw: pointer to hardware structure
2266  */
2267 STATIC s32 ixgbe_reset_phy_m88(struct ixgbe_hw *hw)
2268 {
2269         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2270         u16 reg;
2271         s32 rc;
2272
2273         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2274                 return IXGBE_SUCCESS;
2275
2276         rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2277         if (rc)
2278                 return rc;
2279
2280         switch (hw->phy.id) {
2281         case IXGBE_M88E1500_E_PHY_ID:
2282                 rc = ixgbe_reset_phy_m88e1500(hw);
2283                 break;
2284         case IXGBE_M88E1543_E_PHY_ID:
2285                 rc = ixgbe_reset_phy_m88e1543(hw);
2286                 break;
2287         default:
2288                 rc = IXGBE_ERR_PHY;
2289                 break;
2290         }
2291
2292         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2293         if (rc)
2294                 goto out;
2295
2296         reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2297               IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2298               IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2299         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2300         if (rc)
2301                 goto out;
2302
2303         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 18);
2304         if (rc)
2305                 goto out;
2306
2307         reg = IXGBE_M88E1500_GEN_CTRL_RESET |
2308               IXGBE_M88E1500_GEN_CTRL_MODE_SGMII_COPPER;
2309         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_GEN_CTRL, 0, reg);
2310         if (rc)
2311                 goto out;
2312
2313         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2314         if (rc)
2315                 goto out;
2316
2317         reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2318               IXGBE_M88E1500_FIBER_CTRL_AN_EN |
2319               IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2320               IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2321         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2322         if (rc)
2323                 goto out;
2324
2325         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2326         if (rc)
2327                 goto out;
2328
2329         reg = (IXGBE_M88E1500_MAC_CTRL_1_DWN_4X <<
2330                IXGBE_M88E1500_MAC_CTRL_1_DWN_SHIFT) |
2331               (IXGBE_M88E1500_MAC_CTRL_1_ED_TM <<
2332                IXGBE_M88E1500_MAC_CTRL_1_ED_SHIFT) |
2333               (IXGBE_M88E1500_MAC_CTRL_1_MDIX_AUTO <<
2334                IXGBE_M88E1500_MAC_CTRL_1_MDIX_SHIFT);
2335         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, reg);
2336         if (rc)
2337                 goto out;
2338
2339         reg = IXGBE_M88E1500_COPPER_CTRL_RESET |
2340               IXGBE_M88E1500_COPPER_CTRL_AN_EN |
2341               IXGBE_M88E1500_COPPER_CTRL_RESTART_AN |
2342               IXGBE_M88E1500_COPPER_CTRL_FULL_DUPLEX |
2343               IXGBE_M88E1500_COPPER_CTRL_SPEED_MSB;
2344         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2345         if (rc)
2346                 goto out;
2347
2348         hw->mac.ops.release_swfw_sync(hw, mask);
2349
2350         return ixgbe_setup_m88(hw);
2351
2352 out:
2353         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2354         hw->mac.ops.release_swfw_sync(hw, mask);
2355         return rc;
2356 }
2357
2358 /**
2359  *  ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2360  *  @hw: pointer to hardware structure
2361  *
2362  *  Read NW_MNG_IF_SEL register and save field values, and check for valid field
2363  *  values.
2364  **/
2365 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2366 {
2367         /* Save NW management interface connected on board. This is used
2368          * to determine internal PHY mode.
2369          */
2370         hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2371
2372         /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2373          * PHY address. This register field was has only been used for X552.
2374          */
2375         if (hw->mac.type == ixgbe_mac_X550EM_a &&
2376             hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2377                 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2378                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2379                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2380         }
2381
2382         return IXGBE_SUCCESS;
2383 }
2384
2385 /**
2386  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2387  *  @hw: pointer to hardware structure
2388  *
2389  *  Initialize any function pointers that were not able to be
2390  *  set during init_shared_code because the PHY/SFP type was
2391  *  not known.  Perform the SFP init if necessary.
2392  */
2393 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2394 {
2395         struct ixgbe_phy_info *phy = &hw->phy;
2396         s32 ret_val;
2397
2398         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2399
2400         hw->mac.ops.set_lan_id(hw);
2401
2402         ixgbe_read_mng_if_sel_x550em(hw);
2403
2404         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2405                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2406                 ixgbe_setup_mux_ctl(hw);
2407                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2408         }
2409
2410         switch (hw->device_id) {
2411         case IXGBE_DEV_ID_X550EM_A_1G_T:
2412         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2413                 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2414                 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2415                 break;
2416         default:
2417                 break;
2418         }
2419
2420         /* Identify the PHY or SFP module */
2421         ret_val = phy->ops.identify(hw);
2422         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
2423                 return ret_val;
2424
2425         /* Setup function pointers based on detected hardware */
2426         ixgbe_init_mac_link_ops_X550em(hw);
2427         if (phy->sfp_type != ixgbe_sfp_type_unknown)
2428                 phy->ops.reset = NULL;
2429
2430         /* Set functions pointers based on phy type */
2431         switch (hw->phy.type) {
2432         case ixgbe_phy_x550em_kx4:
2433                 phy->ops.setup_link = NULL;
2434                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2435                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2436                 break;
2437         case ixgbe_phy_x550em_kr:
2438                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2439                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2440                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2441                 break;
2442         case ixgbe_phy_x550em_ext_t:
2443                 /* If internal link mode is XFI, then setup iXFI internal link,
2444                  * else setup KR now.
2445                  */
2446                 phy->ops.setup_internal_link =
2447                                               ixgbe_setup_internal_phy_t_x550em;
2448
2449                 /* setup SW LPLU only for first revision of X550EM_x */
2450                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2451                     !(IXGBE_FUSES0_REV_MASK &
2452                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2453                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2454
2455                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2456                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2457                 break;
2458         case ixgbe_phy_sgmii:
2459                 phy->ops.setup_link = NULL;
2460                 break;
2461         case ixgbe_phy_m88:
2462                 phy->ops.setup_link = ixgbe_setup_m88;
2463                 phy->ops.reset = ixgbe_reset_phy_m88;
2464                 break;
2465         default:
2466                 break;
2467         }
2468         return ret_val;
2469 }
2470
2471 /**
2472  * ixgbe_set_mdio_speed - Set MDIO clock speed
2473  *  @hw: pointer to hardware structure
2474  */
2475 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2476 {
2477         u32 hlreg0;
2478
2479         switch (hw->device_id) {
2480         case IXGBE_DEV_ID_X550EM_X_10G_T:
2481         case IXGBE_DEV_ID_X550EM_A_SGMII:
2482         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2483         case IXGBE_DEV_ID_X550EM_A_1G_T:
2484         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2485         case IXGBE_DEV_ID_X550EM_A_10G_T:
2486         case IXGBE_DEV_ID_X550EM_A_SFP:
2487         case IXGBE_DEV_ID_X550EM_A_QSFP:
2488                 /* Config MDIO clock speed before the first MDIO PHY access */
2489                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2490                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2491                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2492                 break;
2493         default:
2494                 break;
2495         }
2496 }
2497
2498 /**
2499  *  ixgbe_reset_hw_X550em - Perform hardware reset
2500  *  @hw: pointer to hardware structure
2501  *
2502  *  Resets the hardware by resetting the transmit and receive units, masks
2503  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2504  *  reset.
2505  */
2506 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2507 {
2508         ixgbe_link_speed link_speed;
2509         s32 status;
2510         u32 ctrl = 0;
2511         u32 i;
2512         bool link_up = false;
2513
2514         DEBUGFUNC("ixgbe_reset_hw_X550em");
2515
2516         /* Call adapter stop to disable Tx/Rx and clear interrupts */
2517         status = hw->mac.ops.stop_adapter(hw);
2518         if (status != IXGBE_SUCCESS)
2519                 return status;
2520
2521         /* flush pending Tx transactions */
2522         ixgbe_clear_tx_pending(hw);
2523
2524         ixgbe_set_mdio_speed(hw);
2525
2526         /* PHY ops must be identified and initialized prior to reset */
2527         status = hw->phy.ops.init(hw);
2528
2529         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2530                 return status;
2531
2532         /* start the external PHY */
2533         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2534                 status = ixgbe_init_ext_t_x550em(hw);
2535                 if (status)
2536                         return status;
2537         }
2538
2539         /* Setup SFP module if there is one present. */
2540         if (hw->phy.sfp_setup_needed) {
2541                 status = hw->mac.ops.setup_sfp(hw);
2542                 hw->phy.sfp_setup_needed = false;
2543         }
2544
2545         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2546                 return status;
2547
2548         /* Reset PHY */
2549         if (!hw->phy.reset_disable && hw->phy.ops.reset)
2550                 hw->phy.ops.reset(hw);
2551
2552 mac_reset_top:
2553         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2554          * If link reset is used when link is up, it might reset the PHY when
2555          * mng is using it.  If link is down or the flag to force full link
2556          * reset is set, then perform link reset.
2557          */
2558         ctrl = IXGBE_CTRL_LNK_RST;
2559         if (!hw->force_full_reset) {
2560                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2561                 if (link_up)
2562                         ctrl = IXGBE_CTRL_RST;
2563         }
2564
2565         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2566         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2567         IXGBE_WRITE_FLUSH(hw);
2568
2569         /* Poll for reset bit to self-clear meaning reset is complete */
2570         for (i = 0; i < 10; i++) {
2571                 usec_delay(1);
2572                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2573                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2574                         break;
2575         }
2576
2577         if (ctrl & IXGBE_CTRL_RST_MASK) {
2578                 status = IXGBE_ERR_RESET_FAILED;
2579                 DEBUGOUT("Reset polling failed to complete.\n");
2580         }
2581
2582         msec_delay(50);
2583
2584         /* Double resets are required for recovery from certain error
2585          * conditions.  Between resets, it is necessary to stall to
2586          * allow time for any pending HW events to complete.
2587          */
2588         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2589                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2590                 goto mac_reset_top;
2591         }
2592
2593         /* Store the permanent mac address */
2594         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2595
2596         /* Store MAC address from RAR0, clear receive address registers, and
2597          * clear the multicast table.  Also reset num_rar_entries to 128,
2598          * since we modify this value when programming the SAN MAC address.
2599          */
2600         hw->mac.num_rar_entries = 128;
2601         hw->mac.ops.init_rx_addrs(hw);
2602
2603         ixgbe_set_mdio_speed(hw);
2604
2605         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2606                 ixgbe_setup_mux_ctl(hw);
2607
2608         return status;
2609 }
2610
2611 /**
2612  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2613  * @hw: pointer to hardware structure
2614  */
2615 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2616 {
2617         u32 status;
2618         u16 reg;
2619
2620         status = hw->phy.ops.read_reg(hw,
2621                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2622                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2623                                       &reg);
2624
2625         if (status != IXGBE_SUCCESS)
2626                 return status;
2627
2628         /* If PHY FW reset completed bit is set then this is the first
2629          * SW instance after a power on so the PHY FW must be un-stalled.
2630          */
2631         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2632                 status = hw->phy.ops.read_reg(hw,
2633                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2634                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2635                                         &reg);
2636
2637                 if (status != IXGBE_SUCCESS)
2638                         return status;
2639
2640                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2641
2642                 status = hw->phy.ops.write_reg(hw,
2643                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2644                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2645                                         reg);
2646
2647                 if (status != IXGBE_SUCCESS)
2648                         return status;
2649         }
2650
2651         return status;
2652 }
2653
2654 /**
2655  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
2656  *  @hw: pointer to hardware structure
2657  *
2658  *  Configures the integrated KR PHY for X550EM_x.
2659  **/
2660 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2661 {
2662         if (hw->mac.type != ixgbe_mac_X550EM_x)
2663                 return IXGBE_SUCCESS;
2664
2665         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2666 }
2667
2668 /**
2669  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2670  *  @hw: pointer to hardware structure
2671  *
2672  *  Configure the external PHY and the integrated KR PHY for SFP support.
2673  **/
2674 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2675                                     ixgbe_link_speed speed,
2676                                     bool autoneg_wait_to_complete)
2677 {
2678         s32 ret_val;
2679         u16 reg_slice, reg_val;
2680         bool setup_linear = false;
2681         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2682
2683         /* Check if SFP module is supported and linear */
2684         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2685
2686         /* If no SFP module present, then return success. Return success since
2687          * there is no reason to configure CS4227 and SFP not present error is
2688          * not excepted in the setup MAC link flow.
2689          */
2690         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2691                 return IXGBE_SUCCESS;
2692
2693         if (ret_val != IXGBE_SUCCESS)
2694                 return ret_val;
2695
2696         /* Configure internal PHY for KR/KX. */
2697         ixgbe_setup_kr_speed_x550em(hw, speed);
2698
2699         /* Configure CS4227 LINE side to proper mode. */
2700         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2701                     (hw->bus.lan_id << 12);
2702         if (setup_linear)
2703                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2704         else
2705                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2706         ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2707                                           reg_val);
2708         return ret_val;
2709 }
2710
2711 /**
2712  *  ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2713  *  @hw: pointer to hardware structure
2714  *
2715  *  Configure the the integrated PHY for SFP support.
2716  **/
2717 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2718                                    ixgbe_link_speed speed,
2719                                    bool autoneg_wait_to_complete)
2720 {
2721         s32 ret_val;
2722         u16 reg_phy_ext;
2723         bool setup_linear = false;
2724         u32 reg_slice, reg_phy_int, slice_offset;
2725
2726         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2727
2728         /* Check if SFP module is supported and linear */
2729         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2730
2731         /* If no SFP module present, then return success. Return success since
2732          * SFP not present error is not excepted in the setup MAC link flow.
2733          */
2734         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2735                 return IXGBE_SUCCESS;
2736
2737         if (ret_val != IXGBE_SUCCESS)
2738                 return ret_val;
2739
2740         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2741                 /* Configure internal PHY for native SFI */
2742                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2743                                IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2744                                IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_phy_int);
2745
2746                 if (ret_val != IXGBE_SUCCESS)
2747                         return ret_val;
2748
2749                 if (setup_linear) {
2750                         reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LIMITING;
2751                         reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LINEAR;
2752                 } else {
2753                         reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LIMITING;
2754                         reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LINEAR;
2755                 }
2756
2757                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2758                                 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2759                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2760
2761                 if (ret_val != IXGBE_SUCCESS)
2762                         return ret_val;
2763
2764                 /* Setup XFI/SFI internal link. */
2765                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2766         } else {
2767                 /* Configure internal PHY for KR/KX. */
2768                 ixgbe_setup_kr_speed_x550em(hw, speed);
2769
2770                 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2771                         /* Find Address */
2772                         DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2773                         return IXGBE_ERR_PHY_ADDR_INVALID;
2774                 }
2775
2776                 /* Get external PHY device id */
2777                 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_GLOBAL_ID_MSB,
2778                                        IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2779
2780                 if (ret_val != IXGBE_SUCCESS)
2781                         return ret_val;
2782
2783                 /* When configuring quad port CS4223, the MAC instance is part
2784                  * of the slice offset.
2785                  */
2786                 if (reg_phy_ext == IXGBE_CS4223_PHY_ID)
2787                         slice_offset = (hw->bus.lan_id +
2788                                         (hw->bus.instance_id << 1)) << 12;
2789                 else
2790                         slice_offset = hw->bus.lan_id << 12;
2791
2792                 /* Configure CS4227/CS4223 LINE side to proper mode. */
2793                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2794                 if (setup_linear)
2795                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2796                 else
2797                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2798                 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2799                                         IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2800         }
2801         return ret_val;
2802 }
2803
2804 /**
2805  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2806  *  @hw: pointer to hardware structure
2807  *
2808  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2809  **/
2810 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2811 {
2812         s32 status;
2813         u32 reg_val;
2814
2815         /* Disable training protocol FSM. */
2816         status = ixgbe_read_iosf_sb_reg_x550(hw,
2817                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2818                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2819         if (status != IXGBE_SUCCESS)
2820                 return status;
2821         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2822         status = ixgbe_write_iosf_sb_reg_x550(hw,
2823                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2824                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2825         if (status != IXGBE_SUCCESS)
2826                 return status;
2827
2828         /* Disable Flex from training TXFFE. */
2829         status = ixgbe_read_iosf_sb_reg_x550(hw,
2830                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2831                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2832         if (status != IXGBE_SUCCESS)
2833                 return status;
2834         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2835         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2836         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2837         status = ixgbe_write_iosf_sb_reg_x550(hw,
2838                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2839                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2840         if (status != IXGBE_SUCCESS)
2841                 return status;
2842         status = ixgbe_read_iosf_sb_reg_x550(hw,
2843                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2844                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2845         if (status != IXGBE_SUCCESS)
2846                 return status;
2847         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2848         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2849         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2850         status = ixgbe_write_iosf_sb_reg_x550(hw,
2851                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2852                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2853         if (status != IXGBE_SUCCESS)
2854                 return status;
2855
2856         /* Enable override for coefficients. */
2857         status = ixgbe_read_iosf_sb_reg_x550(hw,
2858                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2859                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2860         if (status != IXGBE_SUCCESS)
2861                 return status;
2862         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2863         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2864         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2865         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2866         status = ixgbe_write_iosf_sb_reg_x550(hw,
2867                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2868                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2869         return status;
2870 }
2871
2872 /**
2873  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2874  *  @hw: pointer to hardware structure
2875  *  @speed: the link speed to force
2876  *
2877  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
2878  *  internal and external PHY at a specific speed, without autonegotiation.
2879  **/
2880 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2881 {
2882         s32 status;
2883         u32 reg_val;
2884
2885         /* Disable AN and force speed to 10G Serial. */
2886         status = ixgbe_read_iosf_sb_reg_x550(hw,
2887                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2888                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2889         if (status != IXGBE_SUCCESS)
2890                 return status;
2891
2892         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2893         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2894
2895         /* Select forced link speed for internal PHY. */
2896         switch (*speed) {
2897         case IXGBE_LINK_SPEED_10GB_FULL:
2898                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2899                 break;
2900         case IXGBE_LINK_SPEED_1GB_FULL:
2901                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2902                 break;
2903         default:
2904                 /* Other link speeds are not supported by internal KR PHY. */
2905                 return IXGBE_ERR_LINK_SETUP;
2906         }
2907
2908         status = ixgbe_write_iosf_sb_reg_x550(hw,
2909                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2910                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2911         if (status != IXGBE_SUCCESS)
2912                 return status;
2913
2914         /* Additional configuration needed for x550em_x */
2915         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2916                 status = ixgbe_setup_ixfi_x550em_x(hw);
2917                 if (status != IXGBE_SUCCESS)
2918                         return status;
2919         }
2920
2921         /* Toggle port SW reset by AN reset. */
2922         status = ixgbe_read_iosf_sb_reg_x550(hw,
2923                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2924                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2925         if (status != IXGBE_SUCCESS)
2926                 return status;
2927         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2928         status = ixgbe_write_iosf_sb_reg_x550(hw,
2929                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2930                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2931
2932         return status;
2933 }
2934
2935 /**
2936  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2937  * @hw: address of hardware structure
2938  * @link_up: address of boolean to indicate link status
2939  *
2940  * Returns error code if unable to get link status.
2941  */
2942 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2943 {
2944         u32 ret;
2945         u16 autoneg_status;
2946
2947         *link_up = false;
2948
2949         /* read this twice back to back to indicate current status */
2950         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2951                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2952                                    &autoneg_status);
2953         if (ret != IXGBE_SUCCESS)
2954                 return ret;
2955
2956         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2957                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2958                                    &autoneg_status);
2959         if (ret != IXGBE_SUCCESS)
2960                 return ret;
2961
2962         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2963
2964         return IXGBE_SUCCESS;
2965 }
2966
2967 /**
2968  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2969  * @hw: point to hardware structure
2970  *
2971  * Configures the link between the integrated KR PHY and the external X557 PHY
2972  * The driver will call this function when it gets a link status change
2973  * interrupt from the X557 PHY. This function configures the link speed
2974  * between the PHYs to match the link speed of the BASE-T link.
2975  *
2976  * A return of a non-zero value indicates an error, and the base driver should
2977  * not report link up.
2978  */
2979 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2980 {
2981         ixgbe_link_speed force_speed;
2982         bool link_up;
2983         u32 status;
2984         u16 speed;
2985
2986         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2987                 return IXGBE_ERR_CONFIG;
2988
2989         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2990                 /* If link is down, there is no setup necessary so return  */
2991                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2992                 if (status != IXGBE_SUCCESS)
2993                         return status;
2994
2995                 if (!link_up)
2996                         return IXGBE_SUCCESS;
2997
2998                 status = hw->phy.ops.read_reg(hw,
2999                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3000                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3001                                               &speed);
3002                 if (status != IXGBE_SUCCESS)
3003                         return status;
3004
3005                 /* If link is still down - no setup is required so return */
3006                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3007                 if (status != IXGBE_SUCCESS)
3008                         return status;
3009                 if (!link_up)
3010                         return IXGBE_SUCCESS;
3011
3012                 /* clear everything but the speed and duplex bits */
3013                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
3014
3015                 switch (speed) {
3016                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
3017                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3018                         break;
3019                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
3020                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3021                         break;
3022                 default:
3023                         /* Internal PHY does not support anything else */
3024                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
3025                 }
3026
3027                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
3028         } else {
3029                 speed = IXGBE_LINK_SPEED_10GB_FULL |
3030                         IXGBE_LINK_SPEED_1GB_FULL;
3031                 return ixgbe_setup_kr_speed_x550em(hw, speed);
3032         }
3033 }
3034
3035 /**
3036  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
3037  *  @hw: pointer to hardware structure
3038  *
3039  *  Configures the integrated KR PHY to use internal loopback mode.
3040  **/
3041 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
3042 {
3043         s32 status;
3044         u32 reg_val;
3045
3046         /* Disable AN and force speed to 10G Serial. */
3047         status = hw->mac.ops.read_iosf_sb_reg(hw,
3048                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3049                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3050         if (status != IXGBE_SUCCESS)
3051                 return status;
3052         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3053         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3054         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3055         status = hw->mac.ops.write_iosf_sb_reg(hw,
3056                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3057                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3058         if (status != IXGBE_SUCCESS)
3059                 return status;
3060
3061         /* Set near-end loopback clocks. */
3062         status = hw->mac.ops.read_iosf_sb_reg(hw,
3063                       IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3064                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3065         if (status != IXGBE_SUCCESS)
3066                 return status;
3067         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3068         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3069         status = hw->mac.ops.write_iosf_sb_reg(hw,
3070                        IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3071                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3072         if (status != IXGBE_SUCCESS)
3073                 return status;
3074
3075         /* Set loopback enable. */
3076         status = hw->mac.ops.read_iosf_sb_reg(hw,
3077                       IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3078                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3079         if (status != IXGBE_SUCCESS)
3080                 return status;
3081         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3082         status = hw->mac.ops.write_iosf_sb_reg(hw,
3083                        IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3084                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3085         if (status != IXGBE_SUCCESS)
3086                 return status;
3087
3088         /* Training bypass. */
3089         status = hw->mac.ops.read_iosf_sb_reg(hw,
3090                       IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3091                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3092         if (status != IXGBE_SUCCESS)
3093                 return status;
3094         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3095         status = hw->mac.ops.write_iosf_sb_reg(hw,
3096                        IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3097                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3098
3099         return status;
3100 }
3101
3102 /**
3103  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3104  *  assuming that the semaphore is already obtained.
3105  *  @hw: pointer to hardware structure
3106  *  @offset: offset of  word in the EEPROM to read
3107  *  @data: word read from the EEPROM
3108  *
3109  *  Reads a 16 bit word from the EEPROM using the hostif.
3110  **/
3111 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3112                                    u16 *data)
3113 {
3114         s32 status;
3115         struct ixgbe_hic_read_shadow_ram buffer;
3116
3117         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
3118         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3119         buffer.hdr.req.buf_lenh = 0;
3120         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3121         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3122
3123         /* convert offset from words to bytes */
3124         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3125         /* one word */
3126         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3127
3128         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3129                                               sizeof(buffer),
3130                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3131
3132         if (status)
3133                 return status;
3134
3135         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3136                                           FW_NVM_DATA_OFFSET);
3137
3138         return 0;
3139 }
3140
3141 /**
3142  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3143  *  @hw: pointer to hardware structure
3144  *  @offset: offset of  word in the EEPROM to read
3145  *  @data: word read from the EEPROM
3146  *
3147  *  Reads a 16 bit word from the EEPROM using the hostif.
3148  **/
3149 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3150                               u16 *data)
3151 {
3152         s32 status = IXGBE_SUCCESS;
3153
3154         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3155
3156         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3157             IXGBE_SUCCESS) {
3158                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
3159                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3160         } else {
3161                 status = IXGBE_ERR_SWFW_SYNC;
3162         }
3163
3164         return status;
3165 }
3166
3167 /**
3168  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3169  *  @hw: pointer to hardware structure
3170  *  @offset: offset of  word in the EEPROM to read
3171  *  @words: number of words
3172  *  @data: word(s) read from the EEPROM
3173  *
3174  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
3175  **/
3176 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3177                                      u16 offset, u16 words, u16 *data)
3178 {
3179         struct ixgbe_hic_read_shadow_ram buffer;
3180         u32 current_word = 0;
3181         u16 words_to_read;
3182         s32 status;
3183         u32 i;
3184
3185         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3186
3187         /* Take semaphore for the entire operation. */
3188         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3189         if (status) {
3190                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3191                 return status;
3192         }
3193         while (words) {
3194                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3195                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3196                 else
3197                         words_to_read = words;
3198
3199                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3200                 buffer.hdr.req.buf_lenh = 0;
3201                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3202                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3203
3204                 /* convert offset from words to bytes */
3205                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3206                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3207
3208                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3209                                                       sizeof(buffer),
3210                                                       IXGBE_HI_COMMAND_TIMEOUT,
3211                                                       false);
3212
3213                 if (status) {
3214                         DEBUGOUT("Host interface command failed\n");
3215                         goto out;
3216                 }
3217
3218                 for (i = 0; i < words_to_read; i++) {
3219                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3220                                   2 * i;
3221                         u32 value = IXGBE_READ_REG(hw, reg);
3222
3223                         data[current_word] = (u16)(value & 0xffff);
3224                         current_word++;
3225                         i++;
3226                         if (i < words_to_read) {
3227                                 value >>= 16;
3228                                 data[current_word] = (u16)(value & 0xffff);
3229                                 current_word++;
3230                         }
3231                 }
3232                 words -= words_to_read;
3233         }
3234
3235 out:
3236         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3237         return status;
3238 }
3239
3240 /**
3241  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3242  *  @hw: pointer to hardware structure
3243  *  @offset: offset of  word in the EEPROM to write
3244  *  @data: word write to the EEPROM
3245  *
3246  *  Write a 16 bit word to the EEPROM using the hostif.
3247  **/
3248 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3249                                     u16 data)
3250 {
3251         s32 status;
3252         struct ixgbe_hic_write_shadow_ram buffer;
3253
3254         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3255
3256         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3257         buffer.hdr.req.buf_lenh = 0;
3258         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3259         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3260
3261          /* one word */
3262         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3263         buffer.data = data;
3264         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3265
3266         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3267                                               sizeof(buffer),
3268                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3269
3270         return status;
3271 }
3272
3273 /**
3274  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3275  *  @hw: pointer to hardware structure
3276  *  @offset: offset of  word in the EEPROM to write
3277  *  @data: word write to the EEPROM
3278  *
3279  *  Write a 16 bit word to the EEPROM using the hostif.
3280  **/
3281 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3282                                u16 data)
3283 {
3284         s32 status = IXGBE_SUCCESS;
3285
3286         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3287
3288         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3289             IXGBE_SUCCESS) {
3290                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3291                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3292         } else {
3293                 DEBUGOUT("write ee hostif failed to get semaphore");
3294                 status = IXGBE_ERR_SWFW_SYNC;
3295         }
3296
3297         return status;
3298 }
3299
3300 /**
3301  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3302  *  @hw: pointer to hardware structure
3303  *  @offset: offset of  word in the EEPROM to write
3304  *  @words: number of words
3305  *  @data: word(s) write to the EEPROM
3306  *
3307  *  Write a 16 bit word(s) to the EEPROM using the hostif.
3308  **/
3309 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3310                                       u16 offset, u16 words, u16 *data)
3311 {
3312         s32 status = IXGBE_SUCCESS;
3313         u32 i = 0;
3314
3315         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3316
3317         /* Take semaphore for the entire operation. */
3318         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3319         if (status != IXGBE_SUCCESS) {
3320                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3321                 goto out;
3322         }
3323
3324         for (i = 0; i < words; i++) {
3325                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3326                                                          data[i]);
3327
3328                 if (status != IXGBE_SUCCESS) {
3329                         DEBUGOUT("Eeprom buffered write failed\n");
3330                         break;
3331                 }
3332         }
3333
3334         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3335 out:
3336
3337         return status;
3338 }
3339
3340 /**
3341  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3342  * @hw: pointer to hardware structure
3343  * @ptr: pointer offset in eeprom
3344  * @size: size of section pointed by ptr, if 0 first word will be used as size
3345  * @csum: address of checksum to update
3346  *
3347  * Returns error status for any failure
3348  */
3349 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3350                                    u16 size, u16 *csum, u16 *buffer,
3351                                    u32 buffer_size)
3352 {
3353         u16 buf[256];
3354         s32 status;
3355         u16 length, bufsz, i, start;
3356         u16 *local_buffer;
3357
3358         bufsz = sizeof(buf) / sizeof(buf[0]);
3359
3360         /* Read a chunk at the pointer location */
3361         if (!buffer) {
3362                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3363                 if (status) {
3364                         DEBUGOUT("Failed to read EEPROM image\n");
3365                         return status;
3366                 }
3367                 local_buffer = buf;
3368         } else {
3369                 if (buffer_size < ptr)
3370                         return  IXGBE_ERR_PARAM;
3371                 local_buffer = &buffer[ptr];
3372         }
3373
3374         if (size) {
3375                 start = 0;
3376                 length = size;
3377         } else {
3378                 start = 1;
3379                 length = local_buffer[0];
3380
3381                 /* Skip pointer section if length is invalid. */
3382                 if (length == 0xFFFF || length == 0 ||
3383                     (ptr + length) >= hw->eeprom.word_size)
3384                         return IXGBE_SUCCESS;
3385         }
3386
3387         if (buffer && ((u32)start + (u32)length > buffer_size))
3388                 return IXGBE_ERR_PARAM;
3389
3390         for (i = start; length; i++, length--) {
3391                 if (i == bufsz && !buffer) {
3392                         ptr += bufsz;
3393                         i = 0;
3394                         if (length < bufsz)
3395                                 bufsz = length;
3396
3397                         /* Read a chunk at the pointer location */
3398                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3399                                                                   bufsz, buf);
3400                         if (status) {
3401                                 DEBUGOUT("Failed to read EEPROM image\n");
3402                                 return status;
3403                         }
3404                 }
3405                 *csum += local_buffer[i];
3406         }
3407         return IXGBE_SUCCESS;
3408 }
3409
3410 /**
3411  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3412  *  @hw: pointer to hardware structure
3413  *  @buffer: pointer to buffer containing calculated checksum
3414  *  @buffer_size: size of buffer
3415  *
3416  *  Returns a negative error code on error, or the 16-bit checksum
3417  **/
3418 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3419 {
3420         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3421         u16 *local_buffer;
3422         s32 status;
3423         u16 checksum = 0;
3424         u16 pointer, i, size;
3425
3426         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3427
3428         hw->eeprom.ops.init_params(hw);
3429
3430         if (!buffer) {
3431                 /* Read pointer area */
3432                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3433                                                      IXGBE_EEPROM_LAST_WORD + 1,
3434                                                      eeprom_ptrs);
3435                 if (status) {
3436                         DEBUGOUT("Failed to read EEPROM image\n");
3437                         return status;
3438                 }
3439                 local_buffer = eeprom_ptrs;
3440         } else {
3441                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3442                         return IXGBE_ERR_PARAM;
3443                 local_buffer = buffer;
3444         }
3445
3446         /*
3447          * For X550 hardware include 0x0-0x41 in the checksum, skip the
3448          * checksum word itself
3449          */
3450         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3451                 if (i != IXGBE_EEPROM_CHECKSUM)
3452                         checksum += local_buffer[i];
3453
3454         /*
3455          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
3456          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3457          */
3458         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3459                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3460                         continue;
3461
3462                 pointer = local_buffer[i];
3463
3464                 /* Skip pointer section if the pointer is invalid. */
3465                 if (pointer == 0xFFFF || pointer == 0 ||
3466                     pointer >= hw->eeprom.word_size)
3467                         continue;
3468
3469                 switch (i) {
3470                 case IXGBE_PCIE_GENERAL_PTR:
3471                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3472                         break;
3473                 case IXGBE_PCIE_CONFIG0_PTR:
3474                 case IXGBE_PCIE_CONFIG1_PTR:
3475                         size = IXGBE_PCIE_CONFIG_SIZE;
3476                         break;
3477                 default:
3478                         size = 0;
3479                         break;
3480                 }
3481
3482                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3483                                                 buffer, buffer_size);
3484                 if (status)
3485                         return status;
3486         }
3487
3488         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3489
3490         return (s32)checksum;
3491 }
3492
3493 /**
3494  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3495  *  @hw: pointer to hardware structure
3496  *
3497  *  Returns a negative error code on error, or the 16-bit checksum
3498  **/
3499 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3500 {
3501         return ixgbe_calc_checksum_X550(hw, NULL, 0);
3502 }
3503
3504 /**
3505  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3506  *  @hw: pointer to hardware structure
3507  *  @checksum_val: calculated checksum
3508  *
3509  *  Performs checksum calculation and validates the EEPROM checksum.  If the
3510  *  caller does not need checksum_val, the value can be NULL.
3511  **/
3512 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3513 {
3514         s32 status;
3515         u16 checksum;
3516         u16 read_checksum = 0;
3517
3518         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3519
3520         /* Read the first word from the EEPROM. If this times out or fails, do
3521          * not continue or we could be in for a very long wait while every
3522          * EEPROM read fails
3523          */
3524         status = hw->eeprom.ops.read(hw, 0, &checksum);
3525         if (status) {
3526                 DEBUGOUT("EEPROM read failed\n");
3527                 return status;
3528         }
3529
3530         status = hw->eeprom.ops.calc_checksum(hw);
3531         if (status < 0)
3532                 return status;
3533
3534         checksum = (u16)(status & 0xffff);
3535
3536         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3537                                            &read_checksum);
3538         if (status)
3539                 return status;
3540
3541         /* Verify read checksum from EEPROM is the same as
3542          * calculated checksum
3543          */
3544         if (read_checksum != checksum) {
3545                 status = IXGBE_ERR_EEPROM_CHECKSUM;
3546                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3547                              "Invalid EEPROM checksum");
3548         }
3549
3550         /* If the user cares, return the calculated checksum */
3551         if (checksum_val)
3552                 *checksum_val = checksum;
3553
3554         return status;
3555 }
3556
3557 /**
3558  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3559  * @hw: pointer to hardware structure
3560  *
3561  * After writing EEPROM to shadow RAM using EEWR register, software calculates
3562  * checksum and updates the EEPROM and instructs the hardware to update
3563  * the flash.
3564  **/
3565 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3566 {
3567         s32 status;
3568         u16 checksum = 0;
3569
3570         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3571
3572         /* Read the first word from the EEPROM. If this times out or fails, do
3573          * not continue or we could be in for a very long wait while every
3574          * EEPROM read fails
3575          */
3576         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3577         if (status) {
3578                 DEBUGOUT("EEPROM read failed\n");
3579                 return status;
3580         }
3581
3582         status = ixgbe_calc_eeprom_checksum_X550(hw);
3583         if (status < 0)
3584                 return status;
3585
3586         checksum = (u16)(status & 0xffff);
3587
3588         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3589                                             checksum);
3590         if (status)
3591                 return status;
3592
3593         status = ixgbe_update_flash_X550(hw);
3594
3595         return status;
3596 }
3597
3598 /**
3599  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3600  *  @hw: pointer to hardware structure
3601  *
3602  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3603  **/
3604 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3605 {
3606         s32 status = IXGBE_SUCCESS;
3607         union ixgbe_hic_hdr2 buffer;
3608
3609         DEBUGFUNC("ixgbe_update_flash_X550");
3610
3611         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3612         buffer.req.buf_lenh = 0;
3613         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3614         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3615
3616         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3617                                               sizeof(buffer),
3618                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3619
3620         return status;
3621 }
3622
3623 /**
3624  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3625  *  @hw: pointer to hardware structure
3626  *
3627  *  Determines physical layer capabilities of the current configuration.
3628  **/
3629 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3630 {
3631         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3632         u16 ext_ability = 0;
3633
3634         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3635
3636         hw->phy.ops.identify(hw);
3637
3638         switch (hw->phy.type) {
3639         case ixgbe_phy_x550em_kr:
3640                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3641                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3642                 break;
3643         case ixgbe_phy_x550em_kx4:
3644                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3645                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3646                 break;
3647         case ixgbe_phy_x550em_ext_t:
3648                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3649                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3650                                      &ext_ability);
3651                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3652                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3653                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3654                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3655                 break;
3656         default:
3657                 break;
3658         }
3659
3660         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3661                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3662
3663         return physical_layer;
3664 }
3665
3666 /**
3667  * ixgbe_get_bus_info_x550em - Set PCI bus info
3668  * @hw: pointer to hardware structure
3669  *
3670  * Sets bus link width and speed to unknown because X550em is
3671  * not a PCI device.
3672  **/
3673 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3674 {
3675
3676         DEBUGFUNC("ixgbe_get_bus_info_x550em");
3677
3678         hw->bus.width = ixgbe_bus_width_unknown;
3679         hw->bus.speed = ixgbe_bus_speed_unknown;
3680
3681         hw->mac.ops.set_lan_id(hw);
3682
3683         return IXGBE_SUCCESS;
3684 }
3685
3686 /**
3687  * ixgbe_disable_rx_x550 - Disable RX unit
3688  *
3689  * Enables the Rx DMA unit for x550
3690  **/
3691 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3692 {
3693         u32 rxctrl, pfdtxgswc;
3694         s32 status;
3695         struct ixgbe_hic_disable_rxen fw_cmd;
3696
3697         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3698
3699         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3700         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3701                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3702                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3703                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3704                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3705                         hw->mac.set_lben = true;
3706                 } else {
3707                         hw->mac.set_lben = false;
3708                 }
3709
3710                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3711                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3712                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3713                 fw_cmd.port_number = (u8)hw->bus.lan_id;
3714
3715                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3716                                         sizeof(struct ixgbe_hic_disable_rxen),
3717                                         IXGBE_HI_COMMAND_TIMEOUT, true);
3718
3719                 /* If we fail - disable RX using register write */
3720                 if (status) {
3721                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3722                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3723                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3724                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3725                         }
3726                 }
3727         }
3728 }
3729
3730 /**
3731  * ixgbe_enter_lplu_x550em - Transition to low power states
3732  *  @hw: pointer to hardware structure
3733  *
3734  * Configures Low Power Link Up on transition to low power states
3735  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3736  * X557 PHY immediately prior to entering LPLU.
3737  **/
3738 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3739 {
3740         u16 an_10g_cntl_reg, autoneg_reg, speed;
3741         s32 status;
3742         ixgbe_link_speed lcd_speed;
3743         u32 save_autoneg;
3744         bool link_up;
3745
3746         /* SW LPLU not required on later HW revisions. */
3747         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3748             (IXGBE_FUSES0_REV_MASK &
3749              IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3750                 return IXGBE_SUCCESS;
3751
3752         /* If blocked by MNG FW, then don't restart AN */
3753         if (ixgbe_check_reset_blocked(hw))
3754                 return IXGBE_SUCCESS;
3755
3756         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3757         if (status != IXGBE_SUCCESS)
3758                 return status;
3759
3760         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3761
3762         if (status != IXGBE_SUCCESS)
3763                 return status;
3764
3765         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3766          * disabled, then force link down by entering low power mode.
3767          */
3768         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3769             !(hw->wol_enabled || ixgbe_mng_present(hw)))
3770                 return ixgbe_set_copper_phy_power(hw, FALSE);
3771
3772         /* Determine LCD */
3773         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3774
3775         if (status != IXGBE_SUCCESS)
3776                 return status;
3777
3778         /* If no valid LCD link speed, then force link down and exit. */
3779         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3780                 return ixgbe_set_copper_phy_power(hw, FALSE);
3781
3782         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3783                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3784                                       &speed);
3785
3786         if (status != IXGBE_SUCCESS)
3787                 return status;
3788
3789         /* If no link now, speed is invalid so take link down */
3790         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3791         if (status != IXGBE_SUCCESS)
3792                 return ixgbe_set_copper_phy_power(hw, false);
3793
3794         /* clear everything but the speed bits */
3795         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3796
3797         /* If current speed is already LCD, then exit. */
3798         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3799              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3800             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3801              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3802                 return status;
3803
3804         /* Clear AN completed indication */
3805         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3806                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3807                                       &autoneg_reg);
3808
3809         if (status != IXGBE_SUCCESS)
3810                 return status;
3811
3812         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3813                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3814                              &an_10g_cntl_reg);
3815
3816         if (status != IXGBE_SUCCESS)
3817                 return status;
3818
3819         status = hw->phy.ops.read_reg(hw,
3820                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3821                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3822                              &autoneg_reg);
3823
3824         if (status != IXGBE_SUCCESS)
3825                 return status;
3826
3827         save_autoneg = hw->phy.autoneg_advertised;
3828
3829         /* Setup link at least common link speed */
3830         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3831
3832         /* restore autoneg from before setting lplu speed */
3833         hw->phy.autoneg_advertised = save_autoneg;
3834
3835         return status;
3836 }
3837
3838 /**
3839  * ixgbe_get_lcd_x550em - Determine lowest common denominator
3840  *  @hw: pointer to hardware structure
3841  *  @lcd_speed: pointer to lowest common link speed
3842  *
3843  * Determine lowest common link speed with link partner.
3844  **/
3845 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3846 {
3847         u16 an_lp_status;
3848         s32 status;
3849         u16 word = hw->eeprom.ctrl_word_3;
3850
3851         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3852
3853         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3854                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3855                                       &an_lp_status);
3856
3857         if (status != IXGBE_SUCCESS)
3858                 return status;
3859
3860         /* If link partner advertised 1G, return 1G */
3861         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3862                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3863                 return status;
3864         }
3865
3866         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3867         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3868             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3869                 return status;
3870
3871         /* Link partner not capable of lower speeds, return 10G */
3872         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3873         return status;
3874 }
3875
3876 /**
3877  *  ixgbe_setup_fc_X550em - Set up flow control
3878  *  @hw: pointer to hardware structure
3879  *
3880  *  Called at init time to set up flow control.
3881  **/
3882 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3883 {
3884         s32 ret_val = IXGBE_SUCCESS;
3885         u32 pause, asm_dir, reg_val;
3886
3887         DEBUGFUNC("ixgbe_setup_fc_X550em");
3888
3889         /* Validate the requested mode */
3890         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3891                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3892                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3893                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3894                 goto out;
3895         }
3896
3897         /* 10gig parts do not have a word in the EEPROM to determine the
3898          * default flow control setting, so we explicitly set it to full.
3899          */
3900         if (hw->fc.requested_mode == ixgbe_fc_default)
3901                 hw->fc.requested_mode = ixgbe_fc_full;
3902
3903         /* Determine PAUSE and ASM_DIR bits. */
3904         switch (hw->fc.requested_mode) {
3905         case ixgbe_fc_none:
3906                 pause = 0;
3907                 asm_dir = 0;
3908                 break;
3909         case ixgbe_fc_tx_pause:
3910                 pause = 0;
3911                 asm_dir = 1;
3912                 break;
3913         case ixgbe_fc_rx_pause:
3914                 /* Rx Flow control is enabled and Tx Flow control is
3915                  * disabled by software override. Since there really
3916                  * isn't a way to advertise that we are capable of RX
3917                  * Pause ONLY, we will advertise that we support both
3918                  * symmetric and asymmetric Rx PAUSE, as such we fall
3919                  * through to the fc_full statement.  Later, we will
3920                  * disable the adapter's ability to send PAUSE frames.
3921                  */
3922         case ixgbe_fc_full:
3923                 pause = 1;
3924                 asm_dir = 1;
3925                 break;
3926         default:
3927                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3928                         "Flow control param set incorrectly\n");
3929                 ret_val = IXGBE_ERR_CONFIG;
3930                 goto out;
3931         }
3932
3933         switch (hw->device_id) {
3934         case IXGBE_DEV_ID_X550EM_X_KR:
3935         case IXGBE_DEV_ID_X550EM_A_KR:
3936         case IXGBE_DEV_ID_X550EM_A_KR_L:
3937                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
3938                                       IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3939                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3940                 if (ret_val != IXGBE_SUCCESS)
3941                         goto out;
3942                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3943                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3944                 if (pause)
3945                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3946                 if (asm_dir)
3947                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3948                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
3949                                        IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3950                                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3951
3952                 /* This device does not fully support AN. */
3953                 hw->fc.disable_fc_autoneg = true;
3954                 break;
3955         default:
3956                 break;
3957         }
3958
3959 out:
3960         return ret_val;
3961 }
3962
3963 /**
3964  *  ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
3965  *  @hw: pointer to hardware structure
3966  *
3967  *  Enable flow control according to IEEE clause 37.
3968  **/
3969 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
3970 {
3971         u32 link_s1, lp_an_page_low, an_cntl_1;
3972         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
3973         ixgbe_link_speed speed;
3974         bool link_up;
3975
3976         /* AN should have completed when the cable was plugged in.
3977          * Look for reasons to bail out.  Bail out if:
3978          * - FC autoneg is disabled, or if
3979          * - link is not up.
3980          */
3981         if (hw->fc.disable_fc_autoneg) {
3982                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3983                               "Flow control autoneg is disabled");
3984                 goto out;
3985         }
3986
3987         hw->mac.ops.check_link(hw, &speed, &link_up, false);
3988         if (!link_up) {
3989                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3990                 goto out;
3991         }
3992
3993         /* Check at auto-negotiation has completed */
3994         status = hw->mac.ops.read_iosf_sb_reg(hw,
3995                                       IXGBE_KRM_LINK_S1(hw->bus.lan_id),
3996                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
3997
3998         if (status != IXGBE_SUCCESS ||
3999             (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4000                 DEBUGOUT("Auto-Negotiation did not complete\n");
4001                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4002                 goto out;
4003         }
4004
4005         /* Read the 10g AN autoc and LP ability registers and resolve
4006          * local flow control settings accordingly
4007          */
4008         status = hw->mac.ops.read_iosf_sb_reg(hw,
4009                                       IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4010                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
4011
4012         if (status != IXGBE_SUCCESS) {
4013                 DEBUGOUT("Auto-Negotiation did not complete\n");
4014                 goto out;
4015         }
4016
4017         status = hw->mac.ops.read_iosf_sb_reg(hw,
4018                               IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
4019                               IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
4020
4021         if (status != IXGBE_SUCCESS) {
4022                 DEBUGOUT("Auto-Negotiation did not complete\n");
4023                 goto out;
4024         }
4025
4026         status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
4027                                     IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
4028                                     IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
4029                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
4030                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
4031
4032 out:
4033         if (status == IXGBE_SUCCESS) {
4034                 hw->fc.fc_was_autonegged = true;
4035         } else {
4036                 hw->fc.fc_was_autonegged = false;
4037                 hw->fc.current_mode = hw->fc.requested_mode;
4038         }
4039 }
4040
4041 /**
4042  *  ixgbe_fc_autoneg_fiber_x550em_a - Enable flow control IEEE clause 37
4043  *  @hw: pointer to hardware structure
4044  *
4045  *  Enable flow control according to IEEE clause 37.
4046  **/
4047 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
4048 {
4049         u32 link_s1, pcs_an_lp, pcs_an;
4050         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4051         ixgbe_link_speed speed;
4052         bool link_up;
4053
4054         /* AN should have completed when the cable was plugged in.
4055          * Look for reasons to bail out.  Bail out if:
4056          * - FC autoneg is disabled, or if
4057          * - link is not up.
4058          */
4059         if (hw->fc.disable_fc_autoneg) {
4060                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4061                              "Flow control autoneg is disabled");
4062                 goto out;
4063         }
4064
4065         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4066         if (!link_up) {
4067                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4068                 goto out;
4069         }
4070
4071         /* Check if auto-negotiation has completed */
4072         status = hw->mac.ops.read_iosf_sb_reg(hw,
4073                                          IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4074                                          IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4075
4076         if (status != IXGBE_SUCCESS ||
4077             (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4078                 DEBUGOUT("Auto-Negotiation did not complete\n");
4079                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4080                 goto out;
4081         }
4082
4083         /* Determine advertised flow control */
4084         status = hw->mac.ops.read_iosf_sb_reg(hw,
4085                                           IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id),
4086                                           IXGBE_SB_IOSF_TARGET_KR_PHY, &pcs_an);
4087
4088         if (status != IXGBE_SUCCESS) {
4089                 DEBUGOUT("Auto-Negotiation did not complete\n");
4090                 goto out;
4091         }
4092
4093         /* Determine link parter flow control */
4094         status = hw->mac.ops.read_iosf_sb_reg(hw,
4095                                   IXGBE_KRM_PCS_KX_AN_LP(hw->bus.lan_id),
4096                                   IXGBE_SB_IOSF_TARGET_KR_PHY, &pcs_an_lp);
4097
4098         if (status != IXGBE_SUCCESS) {
4099                 DEBUGOUT("Auto-Negotiation did not complete\n");
4100                 goto out;
4101         }
4102
4103         status = ixgbe_negotiate_fc(hw, pcs_an, pcs_an_lp,
4104                                     IXGBE_KRM_PCS_KX_AN_SYM_PAUSE,
4105                                     IXGBE_KRM_PCS_KX_AN_ASM_PAUSE,
4106                                     IXGBE_KRM_PCS_KX_AN_LP_SYM_PAUSE,
4107                                     IXGBE_KRM_PCS_KX_AN_LP_ASM_PAUSE);
4108
4109 out:
4110         if (status == IXGBE_SUCCESS) {
4111                 hw->fc.fc_was_autonegged = true;
4112         } else {
4113                 hw->fc.fc_was_autonegged = false;
4114                 hw->fc.current_mode = hw->fc.requested_mode;
4115         }
4116 }
4117
4118 /**
4119  *  ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4120  *  @hw: pointer to hardware structure
4121  *
4122  *  Called at init time to set up flow control.
4123  **/
4124 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4125 {
4126         s32 status = IXGBE_SUCCESS;
4127         u32 an_cntl, link_ctrl = 0;
4128
4129         DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4130
4131         /* Validate the requested mode */
4132         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4133                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4134                       "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4135                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4136         }
4137
4138         if (hw->fc.requested_mode == ixgbe_fc_default)
4139                 hw->fc.requested_mode = ixgbe_fc_full;
4140
4141         /* Set up the 1G and 10G flow control advertisement registers so the
4142          * HW will be able to do FC autoneg once the cable is plugged in.  If
4143          * we link at 10G, the 1G advertisement is harmless and vice versa.
4144          */
4145         status = hw->mac.ops.read_iosf_sb_reg(hw,
4146                                       IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4147                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4148
4149         if (status != IXGBE_SUCCESS) {
4150                 DEBUGOUT("Auto-Negotiation did not complete\n");
4151                 return status;
4152         }
4153
4154         /* The possible values of fc.requested_mode are:
4155          * 0: Flow control is completely disabled
4156          * 1: Rx flow control is enabled (we can receive pause frames,
4157          *    but not send pause frames).
4158          * 2: Tx flow control is enabled (we can send pause frames but
4159          *    we do not support receiving pause frames).
4160          * 3: Both Rx and Tx flow control (symmetric) are enabled.
4161          * other: Invalid.
4162          */
4163         switch (hw->fc.requested_mode) {
4164         case ixgbe_fc_none:
4165                 /* Flow control completely disabled by software override. */
4166                 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4167                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4168                 break;
4169         case ixgbe_fc_tx_pause:
4170                 /* Tx Flow control is enabled, and Rx Flow control is
4171                  * disabled by software override.
4172                  */
4173                 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4174                 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4175                 break;
4176         case ixgbe_fc_rx_pause:
4177                 /* Rx Flow control is enabled and Tx Flow control is
4178                  * disabled by software override. Since there really
4179                  * isn't a way to advertise that we are capable of RX
4180                  * Pause ONLY, we will advertise that we support both
4181                  * symmetric and asymmetric Rx PAUSE, as such we fall
4182                  * through to the fc_full statement.  Later, we will
4183                  * disable the adapter's ability to send PAUSE frames.
4184                  */
4185         case ixgbe_fc_full:
4186                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4187                 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4188                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4189                 break;
4190         default:
4191                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4192                               "Flow control param set incorrectly\n");
4193                 return IXGBE_ERR_CONFIG;
4194         }
4195
4196         status = hw->mac.ops.write_iosf_sb_reg(hw,
4197                                        IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4198                                        IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4199
4200         /* Restart auto-negotiation. */
4201         status = hw->mac.ops.read_iosf_sb_reg(hw,
4202                                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4203                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
4204
4205         if (status != IXGBE_SUCCESS) {
4206                 DEBUGOUT("Auto-Negotiation did not complete\n");
4207                 return status;
4208         }
4209
4210         link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
4211         status = hw->mac.ops.write_iosf_sb_reg(hw,
4212                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4213                                        IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
4214
4215         return status;
4216 }
4217
4218 /**
4219  *  ixgbe_setup_fc_fiber_x550em_a - Set up flow control
4220  *  @hw: pointer to hardware structure
4221  *
4222  *  Called at init time to set up flow control.
4223  **/
4224 s32 ixgbe_setup_fc_fiber_x550em_a(struct ixgbe_hw *hw)
4225 {
4226         struct ixgbe_mac_info *mac = &hw->mac;
4227         s32 rc = IXGBE_SUCCESS;
4228         u32 an_cntl4, lctrl, pcs_an;
4229
4230         DEBUGFUNC("ixgbe_setup_fc_fiber_x550em_a");
4231
4232         /* Validate the requested mode */
4233         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4234                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4235                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4236                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4237         }
4238
4239         /* Enable clause 37 auto-negotiation in KRM_LINK_CTRL_1 */
4240         if (hw->fc.requested_mode == ixgbe_fc_default)
4241                 hw->fc.requested_mode = ixgbe_fc_full;
4242
4243         rc = mac->ops.read_iosf_sb_reg(hw,
4244                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4245                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lctrl);
4246         if (rc)
4247                 return rc;
4248
4249         lctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
4250         lctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
4251
4252         rc = mac->ops.write_iosf_sb_reg(hw,
4253                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4254                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lctrl);
4255         if (rc)
4256                 return rc;
4257
4258         /* Enable clause 37 over 73 in KRM_AN_CNTL_4 */
4259         rc = mac->ops.read_iosf_sb_reg(hw,
4260                                        IXGBE_KRM_AN_CNTL_4(hw->bus.lan_id),
4261                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl4);
4262         if (rc)
4263                 return rc;
4264
4265         an_cntl4 |= IXGBE_KRM_AN_CNTL_4_ECSR_AN37_OVER_73;
4266
4267         rc = mac->ops.write_iosf_sb_reg(hw,
4268                                         IXGBE_KRM_AN_CNTL_4(hw->bus.lan_id),
4269                                         IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl4);
4270         if (rc)
4271                 return rc;
4272
4273         rc = hw->mac.ops.read_iosf_sb_reg(hw,
4274                                           IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id),
4275                                           IXGBE_SB_IOSF_TARGET_KR_PHY, &pcs_an);
4276
4277         if (rc)
4278                 return rc;
4279
4280         /* The possible values of fc.requested_mode are:
4281          * 0: Flow control is completely disabled
4282          * 1: Rx flow control is enabled (we can receive pause frames,
4283          *    but not send pause frames).
4284          * 2: Tx flow control is enabled (we can send pause frames but
4285          *    we do not support receiving pause frames).
4286          * 3: Both Rx and Tx flow control (symmetric) are enabled.
4287          * other: Invalid.
4288          */
4289         switch (hw->fc.requested_mode) {
4290         case ixgbe_fc_none:
4291                 /* Flow control completely disabled by software override. */
4292                 pcs_an &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4293                             IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4294                 break;
4295         case ixgbe_fc_tx_pause:
4296                 /* Tx Flow control is enabled, and Rx Flow control is
4297                  * disabled by software override.
4298                  */
4299                 pcs_an |= IXGBE_KRM_PCS_KX_AN_ASM_PAUSE;
4300                 pcs_an &= ~IXGBE_KRM_PCS_KX_AN_SYM_PAUSE;
4301                 break;
4302         case ixgbe_fc_rx_pause:
4303                 /* Rx Flow control is enabled and Tx Flow control is
4304                  * disabled by software override. Since there really
4305                  * isn't a way to advertise that we are capable of RX
4306                  * Pause ONLY, we will advertise that we support both
4307                  * symmetric and asymmetric Rx PAUSE, as such we fall
4308                  * through to the fc_full statement.  Later, we will
4309                  * disable the adapter's ability to send PAUSE frames.
4310                  */
4311         case ixgbe_fc_full:
4312                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4313                 pcs_an |= IXGBE_KRM_PCS_KX_AN_SYM_PAUSE |
4314                            IXGBE_KRM_PCS_KX_AN_ASM_PAUSE;
4315                 break;
4316         default:
4317                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4318                               "Flow control param set incorrectly\n");
4319                 return IXGBE_ERR_CONFIG;
4320         }
4321
4322         rc = hw->mac.ops.write_iosf_sb_reg(hw,
4323                                            IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id),
4324                                            IXGBE_SB_IOSF_TARGET_KR_PHY, pcs_an);
4325
4326         /* Restart auto-negotiation. */
4327         rc = hw->mac.ops.read_iosf_sb_reg(hw,
4328                                           IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4329                                           IXGBE_SB_IOSF_TARGET_KR_PHY, &lctrl);
4330
4331         if (rc) {
4332                 DEBUGOUT("Auto-Negotiation did not complete\n");
4333                 return rc;
4334         }
4335
4336         lctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
4337         rc = hw->mac.ops.write_iosf_sb_reg(hw,
4338                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4339                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lctrl);
4340
4341         return rc;
4342 }
4343
4344 /**
4345  * ixgbe_set_mux - Set mux for port 1 access with CS4227
4346  * @hw: pointer to hardware structure
4347  * @state: set mux if 1, clear if 0
4348  */
4349 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4350 {
4351         u32 esdp;
4352
4353         if (!hw->bus.lan_id)
4354                 return;
4355         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4356         if (state)
4357                 esdp |= IXGBE_ESDP_SDP1;
4358         else
4359                 esdp &= ~IXGBE_ESDP_SDP1;
4360         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4361         IXGBE_WRITE_FLUSH(hw);
4362 }
4363
4364 /**
4365  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4366  *  @hw: pointer to hardware structure
4367  *  @mask: Mask to specify which semaphore to acquire
4368  *
4369  *  Acquires the SWFW semaphore and sets the I2C MUX
4370  **/
4371 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4372 {
4373         s32 status;
4374
4375         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4376
4377         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4378         if (status)
4379                 return status;
4380
4381         if (mask & IXGBE_GSSR_I2C_MASK)
4382                 ixgbe_set_mux(hw, 1);
4383
4384         return IXGBE_SUCCESS;
4385 }
4386
4387 /**
4388  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4389  *  @hw: pointer to hardware structure
4390  *  @mask: Mask to specify which semaphore to release
4391  *
4392  *  Releases the SWFW semaphore and sets the I2C MUX
4393  **/
4394 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4395 {
4396         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4397
4398         if (mask & IXGBE_GSSR_I2C_MASK)
4399                 ixgbe_set_mux(hw, 0);
4400
4401         ixgbe_release_swfw_sync_X540(hw, mask);
4402 }
4403
4404 /**
4405  *  ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4406  *  @hw: pointer to hardware structure
4407  *  @mask: Mask to specify which semaphore to acquire
4408  *
4409  *  Acquires the SWFW semaphore and get the shared phy token as needed
4410  */
4411 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4412 {
4413         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4414         int retries = FW_PHY_TOKEN_RETRIES;
4415         s32 status = IXGBE_SUCCESS;
4416
4417         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4418
4419         while (--retries) {
4420                 status = IXGBE_SUCCESS;
4421                 if (hmask)
4422                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4423                 if (status)
4424                         return status;
4425                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4426                         return IXGBE_SUCCESS;
4427
4428                 status = ixgbe_get_phy_token(hw);
4429                 if (status == IXGBE_SUCCESS)
4430                         return IXGBE_SUCCESS;
4431
4432                 if (hmask)
4433                         ixgbe_release_swfw_sync_X540(hw, hmask);
4434                 if (status != IXGBE_ERR_TOKEN_RETRY)
4435                         return status;
4436                 msec_delay(FW_PHY_TOKEN_DELAY);
4437         }
4438
4439         return status;
4440 }
4441
4442 /**
4443  *  ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4444  *  @hw: pointer to hardware structure
4445  *  @mask: Mask to specify which semaphore to release
4446  *
4447  *  Releases the SWFW semaphore and puts the shared phy token as needed
4448  */
4449 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4450 {
4451         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4452
4453         DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4454
4455         if (mask & IXGBE_GSSR_TOKEN_SM)
4456                 ixgbe_put_phy_token(hw);
4457
4458         if (hmask)
4459                 ixgbe_release_swfw_sync_X540(hw, hmask);
4460 }
4461
4462 /**
4463  *  ixgbe_read_phy_reg_x550a  - Reads specified PHY register
4464  *  @hw: pointer to hardware structure
4465  *  @reg_addr: 32 bit address of PHY register to read
4466  *  @phy_data: Pointer to read data from PHY register
4467  *
4468  *  Reads a value from a specified PHY register using the SWFW lock and PHY
4469  *  Token. The PHY Token is needed since the MDIO is shared between to MAC
4470  *  instances.
4471  **/
4472 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4473                              u32 device_type, u16 *phy_data)
4474 {
4475         s32 status;
4476         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4477
4478         DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4479
4480         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4481                 return IXGBE_ERR_SWFW_SYNC;
4482
4483         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4484
4485         hw->mac.ops.release_swfw_sync(hw, mask);
4486
4487         return status;
4488 }
4489
4490 /**
4491  *  ixgbe_write_phy_reg_x550a - Writes specified PHY register
4492  *  @hw: pointer to hardware structure
4493  *  @reg_addr: 32 bit PHY register to write
4494  *  @device_type: 5 bit device type
4495  *  @phy_data: Data to write to the PHY register
4496  *
4497  *  Writes a value to specified PHY register using the SWFW lock and PHY Token.
4498  *  The PHY Token is needed since the MDIO is shared between to MAC instances.
4499  **/
4500 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4501                               u32 device_type, u16 phy_data)
4502 {
4503         s32 status;
4504         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4505
4506         DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4507
4508         if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4509                 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
4510                                                  phy_data);
4511                 hw->mac.ops.release_swfw_sync(hw, mask);
4512         } else {
4513                 status = IXGBE_ERR_SWFW_SYNC;
4514         }
4515
4516         return status;
4517 }
4518
4519 /**
4520  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4521  * @hw: pointer to hardware structure
4522  *
4523  * Handle external Base T PHY interrupt. If high temperature
4524  * failure alarm then return error, else if link status change
4525  * then setup internal/external PHY link
4526  *
4527  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4528  * failure alarm, else return PHY access status.
4529  */
4530 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4531 {
4532         bool lsc;
4533         u32 status;
4534
4535         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4536
4537         if (status != IXGBE_SUCCESS)
4538                 return status;
4539
4540         if (lsc)
4541                 return ixgbe_setup_internal_phy(hw);
4542
4543         return IXGBE_SUCCESS;
4544 }
4545
4546 /**
4547  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4548  * @hw: pointer to hardware structure
4549  * @speed: new link speed
4550  * @autoneg_wait_to_complete: true when waiting for completion is needed
4551  *
4552  * Setup internal/external PHY link speed based on link speed, then set
4553  * external PHY auto advertised link speed.
4554  *
4555  * Returns error status for any failure
4556  **/
4557 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4558                                   ixgbe_link_speed speed,
4559                                   bool autoneg_wait_to_complete)
4560 {
4561         s32 status;
4562         ixgbe_link_speed force_speed;
4563
4564         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4565
4566         /* Setup internal/external PHY link speed to iXFI (10G), unless
4567          * only 1G is auto advertised then setup KX link.
4568          */
4569         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4570                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4571         else
4572                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4573
4574         /* If internal link mode is XFI, then setup XFI internal link. */
4575         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4576                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4577
4578                 if (status != IXGBE_SUCCESS)
4579                         return status;
4580         }
4581
4582         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4583 }
4584
4585 /**
4586  * ixgbe_check_link_t_X550em - Determine link and speed status
4587  * @hw: pointer to hardware structure
4588  * @speed: pointer to link speed
4589  * @link_up: true when link is up
4590  * @link_up_wait_to_complete: bool used to wait for link up or not
4591  *
4592  * Check that both the MAC and X557 external PHY have link.
4593  **/
4594 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4595                               bool *link_up, bool link_up_wait_to_complete)
4596 {
4597         u32 status;
4598         u16 autoneg_status;
4599
4600         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4601                 return IXGBE_ERR_CONFIG;
4602
4603         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4604                                               link_up_wait_to_complete);
4605
4606         /* If check link fails or MAC link is not up, then return */
4607         if (status != IXGBE_SUCCESS || !(*link_up))
4608                 return status;
4609
4610         /* MAC link is up, so check external PHY link.
4611          * Read this twice back to back to indicate current status.
4612          */
4613         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4614                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4615                                       &autoneg_status);
4616
4617         if (status != IXGBE_SUCCESS)
4618                 return status;
4619
4620         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4621                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4622                                       &autoneg_status);
4623
4624         if (status != IXGBE_SUCCESS)
4625                 return status;
4626
4627         /* If external PHY link is not up, then indicate link not up */
4628         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4629                 *link_up = false;
4630
4631         return IXGBE_SUCCESS;
4632 }
4633
4634 /**
4635  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4636  *  @hw: pointer to hardware structure
4637  **/
4638 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4639 {
4640         s32 status;
4641
4642         status = ixgbe_reset_phy_generic(hw);
4643
4644         if (status != IXGBE_SUCCESS)
4645                 return status;
4646
4647         /* Configure Link Status Alarm and Temperature Threshold interrupts */
4648         return ixgbe_enable_lasi_ext_t_x550em(hw);
4649 }
4650
4651 /**
4652  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4653  *  @hw: pointer to hardware structure
4654  *  @led_idx: led number to turn on
4655  **/
4656 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4657 {
4658         u16 phy_data;
4659
4660         DEBUGFUNC("ixgbe_led_on_t_X550em");
4661
4662         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4663                 return IXGBE_ERR_PARAM;
4664
4665         /* To turn on the LED, set mode to ON. */
4666         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4667                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4668         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4669         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4670                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4671
4672         return IXGBE_SUCCESS;
4673 }
4674
4675 /**
4676  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4677  *  @hw: pointer to hardware structure
4678  *  @led_idx: led number to turn off
4679  **/
4680 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4681 {
4682         u16 phy_data;
4683
4684         DEBUGFUNC("ixgbe_led_off_t_X550em");
4685
4686         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4687                 return IXGBE_ERR_PARAM;
4688
4689         /* To turn on the LED, set mode to ON. */
4690         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4691                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4692         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4693         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4694                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4695
4696         return IXGBE_SUCCESS;
4697 }
4698