drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  44 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw);
  45
  46 /**
  47  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  48  *  @hw: pointer to hardware structure
  49  *
  50  *  Initialize the function pointers and assign the MAC type for X550.
  51  *  Does not touch the hardware.
  52  **/
  53 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  54 {
  55         struct ixgbe_mac_info *mac = &hw->mac;
  56         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  57         s32 ret_val;
  58
  59         DEBUGFUNC("ixgbe_init_ops_X550");
  60
  61         ret_val = ixgbe_init_ops_X540(hw);
  62         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  63         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  64         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  65         mac->ops.setup_eee = NULL;
  66         mac->ops.set_source_address_pruning =
  67                         ixgbe_set_source_address_pruning_X550;
  68         mac->ops.set_ethertype_anti_spoofing =
  69                         ixgbe_set_ethertype_anti_spoofing_X550;
  70
  71         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  72         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  73         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  74         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  75         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  76         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  77         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  78         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  79         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  80
  81         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  82         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  83         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  84         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  85         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  86         /* Manageability interface */
  87         mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_x550;
  88         switch (hw->device_id) {
  89         case IXGBE_DEV_ID_X550EM_X_10G_T:
  90         case IXGBE_DEV_ID_X550EM_A_10G_T:
  91                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  92                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  93                 break;
  94         default:
  95                 break;
  96         }
  97         return ret_val;
  98 }
  99
 100 /**
 101  * ixgbe_read_cs4227 - Read CS4227 register
 102  * @hw: pointer to hardware structure
 103  * @reg: register number to write
 104  * @value: pointer to receive value read
 105  *
 106  * Returns status code
 107  **/
 108 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
 109 {
 110         return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
 111 }
 112
 113 /**
 114  * ixgbe_write_cs4227 - Write CS4227 register
 115  * @hw: pointer to hardware structure
 116  * @reg: register number to write
 117  * @value: value to write to register
 118  *
 119  * Returns status code
 120  **/
 121 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 122 {
 123         return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
 124 }
 125
 126 /**
 127  * ixgbe_read_pe - Read register from port expander
 128  * @hw: pointer to hardware structure
 129  * @reg: register number to read
 130  * @value: pointer to receive read value
 131  *
 132  * Returns status code
 133  **/
 134 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 135 {
 136         s32 status;
 137
 138         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 139         if (status != IXGBE_SUCCESS)
 140                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 141                               "port expander access failed with %d\n", status);
 142         return status;
 143 }
 144
 145 /**
 146  * ixgbe_write_pe - Write register to port expander
 147  * @hw: pointer to hardware structure
 148  * @reg: register number to write
 149  * @value: value to write
 150  *
 151  * Returns status code
 152  **/
 153 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 154 {
 155         s32 status;
 156
 157         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 158         if (status != IXGBE_SUCCESS)
 159                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 160                               "port expander access failed with %d\n", status);
 161         return status;
 162 }
 163
 164 /**
 165  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 166  * @hw: pointer to hardware structure
 167  *
 168  * This function assumes that the caller has acquired the proper semaphore.
 169  * Returns error code
 170  **/
 171 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 172 {
 173         s32 status;
 174         u32 retry;
 175         u16 value;
 176         u8 reg;
 177
 178         /* Trigger hard reset. */
 179         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 180         if (status != IXGBE_SUCCESS)
 181                 return status;
 182         reg |= IXGBE_PE_BIT1;
 183         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 184         if (status != IXGBE_SUCCESS)
 185                 return status;
 186
 187         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 188         if (status != IXGBE_SUCCESS)
 189                 return status;
 190         reg &= ~IXGBE_PE_BIT1;
 191         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 192         if (status != IXGBE_SUCCESS)
 193                 return status;
 194
 195         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 196         if (status != IXGBE_SUCCESS)
 197                 return status;
 198         reg &= ~IXGBE_PE_BIT1;
 199         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 200         if (status != IXGBE_SUCCESS)
 201                 return status;
 202
 203         usec_delay(IXGBE_CS4227_RESET_HOLD);
 204
 205         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 206         if (status != IXGBE_SUCCESS)
 207                 return status;
 208         reg |= IXGBE_PE_BIT1;
 209         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 210         if (status != IXGBE_SUCCESS)
 211                 return status;
 212
 213         /* Wait for the reset to complete. */
 214         msec_delay(IXGBE_CS4227_RESET_DELAY);
 215         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 216                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 217                                            &value);
 218                 if (status == IXGBE_SUCCESS &&
 219                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 220                         break;
 221                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 222         }
 223         if (retry == IXGBE_CS4227_RETRIES) {
 224                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 225                         "CS4227 reset did not complete.");
 226                 return IXGBE_ERR_PHY;
 227         }
 228
 229         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 230         if (status != IXGBE_SUCCESS ||
 231             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 232                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 233                         "CS4227 EEPROM did not load successfully.");
 234                 return IXGBE_ERR_PHY;
 235         }
 236
 237         return IXGBE_SUCCESS;
 238 }
 239
 240 /**
 241  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 242  * @hw: pointer to hardware structure
 243  **/
 244 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 245 {
 246         s32 status = IXGBE_SUCCESS;
 247         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 248         u16 value = 0;
 249         u8 retry;
 250
 251         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 252                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 253                 if (status != IXGBE_SUCCESS) {
 254                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 255                                 "semaphore failed with %d", status);
 256                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 257                         continue;
 258                 }
 259
 260                 /* Get status of reset flow. */
 261                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 262
 263                 if (status == IXGBE_SUCCESS &&
 264                     value == IXGBE_CS4227_RESET_COMPLETE)
 265                         goto out;
 266
 267                 if (status != IXGBE_SUCCESS ||
 268                     value != IXGBE_CS4227_RESET_PENDING)
 269                         break;
 270
 271                 /* Reset is pending. Wait and check again. */
 272                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 273                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 274         }
 275
 276         /* If still pending, assume other instance failed. */
 277         if (retry == IXGBE_CS4227_RETRIES) {
 278                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 279                 if (status != IXGBE_SUCCESS) {
 280                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 281                                       "semaphore failed with %d", status);
 282                         return;
 283                 }
 284         }
 285
 286         /* Reset the CS4227. */
 287         status = ixgbe_reset_cs4227(hw);
 288         if (status != IXGBE_SUCCESS) {
 289                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 290                         "CS4227 reset failed: %d", status);
 291                 goto out;
 292         }
 293
 294         /* Reset takes so long, temporarily release semaphore in case the
 295          * other driver instance is waiting for the reset indication.
 296          */
 297         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 298                            IXGBE_CS4227_RESET_PENDING);
 299         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 300         msec_delay(10);
 301         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 302         if (status != IXGBE_SUCCESS) {
 303                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 304                         "semaphore failed with %d", status);
 305                 return;
 306         }
 307
 308         /* Record completion for next time. */
 309         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 310                 IXGBE_CS4227_RESET_COMPLETE);
 311
 312 out:
 313         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 314         msec_delay(hw->eeprom.semaphore_delay);
 315 }
 316
 317 /**
 318  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 319  * @hw: pointer to hardware structure
 320  **/
 321 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 322 {
 323         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 324
 325         if (hw->bus.lan_id) {
 326                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 327                 esdp |= IXGBE_ESDP_SDP1_DIR;
 328         }
 329         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 330         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 331         IXGBE_WRITE_FLUSH(hw);
 332 }
 333
 334 /**
 335  * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
 336  * @hw: pointer to hardware structure
 337  * @reg_addr: 32 bit address of PHY register to read
 338  * @dev_type: always unused
 339  * @phy_data: Pointer to read data from PHY register
 340  */
 341 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 342                                      u32 dev_type, u16 *phy_data)
 343 {
 344         u32 i, data, command;
 345         UNREFERENCED_1PARAMETER(dev_type);
 346
 347         /* Setup and write the read command */
 348         command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 349                   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 350                   IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
 351                   IXGBE_MSCA_MDI_COMMAND;
 352
 353         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 354
 355         /* Check every 10 usec to see if the access completed.
 356          * The MDI Command bit will clear when the operation is
 357          * complete
 358          */
 359         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 360                 usec_delay(10);
 361
 362                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 363                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 364                         break;
 365         }
 366
 367         if (command & IXGBE_MSCA_MDI_COMMAND) {
 368                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 369                               "PHY read command did not complete.\n");
 370                 return IXGBE_ERR_PHY;
 371         }
 372
 373         /* Read operation is complete.  Get the data from MSRWD */
 374         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 375         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 376         *phy_data = (u16)data;
 377
 378         return IXGBE_SUCCESS;
 379 }
 380
 381 /**
 382  * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
 383  * @hw: pointer to hardware structure
 384  * @reg_addr: 32 bit PHY register to write
 385  * @dev_type: always unused
 386  * @phy_data: Data to write to the PHY register
 387  */
 388 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 389                                       u32 dev_type, u16 phy_data)
 390 {
 391         u32 i, command;
 392         UNREFERENCED_1PARAMETER(dev_type);
 393
 394         /* Put the data in the MDI single read and write data register*/
 395         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 396
 397         /* Setup and write the write command */
 398         command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 399                   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 400                   IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
 401                   IXGBE_MSCA_MDI_COMMAND;
 402
 403         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 404
 405         /* Check every 10 usec to see if the access completed.
 406          * The MDI Command bit will clear when the operation is
 407          * complete
 408          */
 409         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 410                 usec_delay(10);
 411
 412                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 413                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 414                         break;
 415         }
 416
 417         if (command & IXGBE_MSCA_MDI_COMMAND) {
 418                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 419                               "PHY write cmd didn't complete\n");
 420                 return IXGBE_ERR_PHY;
 421         }
 422
 423         return IXGBE_SUCCESS;
 424 }
 425
 426 /**
 427  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 428  * @hw: pointer to hardware structure
 429  *
 430  * Returns error code
 431  */
 432 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 433 {
 434         hw->mac.ops.set_lan_id(hw);
 435
 436         ixgbe_read_mng_if_sel_x550em(hw);
 437
 438         switch (hw->device_id) {
 439         case IXGBE_DEV_ID_X550EM_A_SFP:
 440                 return ixgbe_identify_module_generic(hw);
 441         case IXGBE_DEV_ID_X550EM_X_SFP:
 442                 /* set up for CS4227 usage */
 443                 ixgbe_setup_mux_ctl(hw);
 444                 ixgbe_check_cs4227(hw);
 445                 /* Fallthrough */
 446
 447         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 448                 return ixgbe_identify_module_generic(hw);
 449                 break;
 450         case IXGBE_DEV_ID_X550EM_X_KX4:
 451                 hw->phy.type = ixgbe_phy_x550em_kx4;
 452                 break;
 453         case IXGBE_DEV_ID_X550EM_X_KR:
 454         case IXGBE_DEV_ID_X550EM_A_KR:
 455         case IXGBE_DEV_ID_X550EM_A_KR_L:
 456                 hw->phy.type = ixgbe_phy_x550em_kr;
 457                 break;
 458         case IXGBE_DEV_ID_X550EM_A_10G_T:
 459         case IXGBE_DEV_ID_X550EM_A_1G_T:
 460         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 461         case IXGBE_DEV_ID_X550EM_X_1G_T:
 462         case IXGBE_DEV_ID_X550EM_X_10G_T:
 463                 return ixgbe_identify_phy_generic(hw);
 464         default:
 465                 break;
 466         }
 467         return IXGBE_SUCCESS;
 468 }
 469
 470 /**
 471  * ixgbe_fw_phy_activity - Perform an activity on a PHY
 472  * @hw: pointer to hardware structure
 473  * @activity: activity to perform
 474  * @data: Pointer to 4 32-bit words of data
 475  */
 476 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,
 477                           u32 (*data)[FW_PHY_ACT_DATA_COUNT])
 478 {
 479         union {
 480                 struct ixgbe_hic_phy_activity_req cmd;
 481                 struct ixgbe_hic_phy_activity_resp rsp;
 482         } hic;
 483         u16 retries = FW_PHY_ACT_RETRIES;
 484         s32 rc;
 485         u16 i;
 486
 487         do {
 488                 memset(&hic, 0, sizeof(hic));
 489                 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD;
 490                 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN;
 491                 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 492                 hic.cmd.port_number = hw->bus.lan_id;
 493                 hic.cmd.activity_id = IXGBE_CPU_TO_LE16(activity);
 494                 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
 495                         hic.cmd.data[i] = IXGBE_CPU_TO_BE32((*data)[i]);
 496
 497                 rc = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
 498                                                   sizeof(hic.cmd),
 499                                                   IXGBE_HI_COMMAND_TIMEOUT,
 500                                                   true);
 501                 if (rc != IXGBE_SUCCESS)
 502                         return rc;
 503                 if (hic.rsp.hdr.cmd_or_resp.ret_status ==
 504                     FW_CEM_RESP_STATUS_SUCCESS) {
 505                         for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
 506                                 (*data)[i] = IXGBE_BE32_TO_CPU(hic.rsp.data[i]);
 507                         return IXGBE_SUCCESS;
 508                 }
 509                 usec_delay(20);
 510                 --retries;
 511         } while (retries > 0);
 512
 513         return IXGBE_ERR_HOST_INTERFACE_COMMAND;
 514 }
 515
 516 static const struct {
 517         u16 fw_speed;
 518         ixgbe_link_speed phy_speed;
 519 } ixgbe_fw_map[] = {
 520         { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL },
 521         { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL },
 522         { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL },
 523         { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL },
 524         { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL },
 525         { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL },
 526 };
 527
 528 /**
 529  * ixgbe_get_phy_id_fw - Get the phy ID via firmware command
 530  * @hw: pointer to hardware structure
 531  *
 532  * Returns error code
 533  */
 534 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw)
 535 {
 536         u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
 537         u16 phy_speeds;
 538         u16 phy_id_lo;
 539         s32 rc;
 540         u16 i;
 541
 542         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info);
 543         if (rc)
 544                 return rc;
 545
 546         hw->phy.speeds_supported = 0;
 547         phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK;
 548         for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
 549                 if (phy_speeds & ixgbe_fw_map[i].fw_speed)
 550                         hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed;
 551         }
 552         if (!hw->phy.autoneg_advertised)
 553                 hw->phy.autoneg_advertised = hw->phy.speeds_supported;
 554
 555         hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK;
 556         phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK;
 557         hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK;
 558         hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK;
 559         if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK)
 560                 return IXGBE_ERR_PHY_ADDR_INVALID;
 561         return IXGBE_SUCCESS;
 562 }
 563
 564 /**
 565  * ixgbe_identify_phy_fw - Get PHY type based on firmware command
 566  * @hw: pointer to hardware structure
 567  *
 568  * Returns error code
 569  */
 570 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw)
 571 {
 572         if (hw->bus.lan_id)
 573                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 574         else
 575                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 576
 577         hw->phy.type = ixgbe_phy_m88;
 578         hw->phy.ops.read_reg = NULL;
 579         hw->phy.ops.write_reg = NULL;
 580         return ixgbe_get_phy_id_fw(hw);
 581 }
 582
 583 /**
 584  * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY
 585  * @hw: pointer to hardware structure
 586  *
 587  * Returns error code
 588  */
 589 s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw)
 590 {
 591         u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
 592
 593         setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF;
 594         return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup);
 595 }
 596
 597 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 598                                      u32 device_type, u16 *phy_data)
 599 {
 600         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 601         return IXGBE_NOT_IMPLEMENTED;
 602 }
 603
 604 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 605                                       u32 device_type, u16 phy_data)
 606 {
 607         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 608         return IXGBE_NOT_IMPLEMENTED;
 609 }
 610
 611 /**
 612  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 613  * @hw: pointer to the hardware structure
 614  * @addr: I2C bus address to read from
 615  * @reg: I2C device register to read from
 616  * @val: pointer to location to receive read value
 617  *
 618  * Returns an error code on error.
 619  **/
 620 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 621                                            u16 reg, u16 *val)
 622 {
 623         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 624 }
 625
 626 /**
 627  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 628  * @hw: pointer to the hardware structure
 629  * @addr: I2C bus address to read from
 630  * @reg: I2C device register to read from
 631  * @val: pointer to location to receive read value
 632  *
 633  * Returns an error code on error.
 634  **/
 635 STATIC s32
 636 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 637                                          u16 reg, u16 *val)
 638 {
 639         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 640 }
 641
 642 /**
 643  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 644  * @hw: pointer to the hardware structure
 645  * @addr: I2C bus address to write to
 646  * @reg: I2C device register to write to
 647  * @val: value to write
 648  *
 649  * Returns an error code on error.
 650  **/
 651 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 652                                             u8 addr, u16 reg, u16 val)
 653 {
 654         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 655 }
 656
 657 /**
 658  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 659  * @hw: pointer to the hardware structure
 660  * @addr: I2C bus address to write to
 661  * @reg: I2C device register to write to
 662  * @val: value to write
 663  *
 664  * Returns an error code on error.
 665  **/
 666 STATIC s32
 667 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 668                                           u8 addr, u16 reg, u16 val)
 669 {
 670         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 671 }
 672
 673 /**
 674 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 675 *  @hw: pointer to hardware structure
 676 *
 677 *  Initialize the function pointers and for MAC type X550EM.
 678 *  Does not touch the hardware.
 679 **/
 680 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 681 {
 682         struct ixgbe_mac_info *mac = &hw->mac;
 683         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 684         struct ixgbe_phy_info *phy = &hw->phy;
 685         s32 ret_val;
 686
 687         DEBUGFUNC("ixgbe_init_ops_X550EM");
 688
 689         /* Similar to X550 so start there. */
 690         ret_val = ixgbe_init_ops_X550(hw);
 691
 692         /* Since this function eventually calls
 693          * ixgbe_init_ops_540 by design, we are setting
 694          * the pointers to NULL explicitly here to overwrite
 695          * the values being set in the x540 function.
 696          */
 697         /* Thermal sensor not supported in x550EM */
 698         mac->ops.get_thermal_sensor_data = NULL;
 699         mac->ops.init_thermal_sensor_thresh = NULL;
 700         mac->thermal_sensor_enabled = false;
 701
 702         /* FCOE not supported in x550EM */
 703         mac->ops.get_san_mac_addr = NULL;
 704         mac->ops.set_san_mac_addr = NULL;
 705         mac->ops.get_wwn_prefix = NULL;
 706         mac->ops.get_fcoe_boot_status = NULL;
 707
 708         /* IPsec not supported in x550EM */
 709         mac->ops.disable_sec_rx_path = NULL;
 710         mac->ops.enable_sec_rx_path = NULL;
 711
 712         /* AUTOC register is not present in x550EM. */
 713         mac->ops.prot_autoc_read = NULL;
 714         mac->ops.prot_autoc_write = NULL;
 715
 716         /* X550EM bus type is internal*/
 717         hw->bus.type = ixgbe_bus_type_internal;
 718         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 719
 720
 721         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 722         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 723         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 724         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 725         mac->ops.get_supported_physical_layer =
 726                                     ixgbe_get_supported_physical_layer_X550em;
 727
 728         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 729                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 730         else
 731                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 732
 733         /* PHY */
 734         phy->ops.init = ixgbe_init_phy_ops_X550em;
 735         switch (hw->device_id) {
 736         case IXGBE_DEV_ID_X550EM_A_1G_T:
 737         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 738                 mac->ops.setup_fc = NULL;
 739                 phy->ops.identify = ixgbe_identify_phy_fw;
 740                 phy->ops.set_phy_power = NULL;
 741                 phy->ops.get_firmware_version = NULL;
 742                 break;
 743         default:
 744                 phy->ops.identify = ixgbe_identify_phy_x550em;
 745         }
 746
 747         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 748                 phy->ops.set_phy_power = NULL;
 749
 750
 751         /* EEPROM */
 752         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 753         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 754         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 755         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 756         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 757         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 758         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 759         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 760
 761         return ret_val;
 762 }
 763
 764 /**
 765  * ixgbe_setup_fw_link - Setup firmware-controlled PHYs
 766  * @hw: pointer to hardware structure
 767  */
 768 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw)
 769 {
 770         u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
 771         s32 rc;
 772         u16 i;
 773
 774         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
 775                 return 0;
 776
 777         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
 778                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
 779                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
 780                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
 781         }
 782
 783         switch (hw->fc.requested_mode) {
 784         case ixgbe_fc_full:
 785                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX <<
 786                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 787                 break;
 788         case ixgbe_fc_rx_pause:
 789                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX <<
 790                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 791                 break;
 792         case ixgbe_fc_tx_pause:
 793                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX <<
 794                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 795                 break;
 796         default:
 797                 break;
 798         }
 799
 800         for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
 801                 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)
 802                         setup[0] |= ixgbe_fw_map[i].fw_speed;
 803         }
 804         setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN;
 805
 806         if (hw->phy.eee_speeds_advertised)
 807                 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE;
 808
 809         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup);
 810         if (rc)
 811                 return rc;
 812         if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN)
 813                 return IXGBE_ERR_OVERTEMP;
 814         return IXGBE_SUCCESS;
 815 }
 816
 817 /**
 818  * ixgbe_fc_autoneg_fw _ Set up flow control for FW-controlled PHYs
 819  * @hw: pointer to hardware structure
 820  *
 821  *  Called at init time to set up flow control.
 822  */
 823 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw)
 824 {
 825         if (hw->fc.requested_mode == ixgbe_fc_default)
 826                 hw->fc.requested_mode = ixgbe_fc_full;
 827
 828         return ixgbe_setup_fw_link(hw);
 829 }
 830
 831 /**
 832  * ixgbe_setup_eee_fw - Enable/disable EEE support
 833  * @hw: pointer to the HW structure
 834  * @enable_eee: boolean flag to enable EEE
 835  *
 836  * Enable/disable EEE based on enable_eee flag.
 837  * This function controls EEE for firmware-based PHY implementations.
 838  */
 839 static s32 ixgbe_setup_eee_fw(struct ixgbe_hw *hw, bool enable_eee)
 840 {
 841         if (!!hw->phy.eee_speeds_advertised == enable_eee)
 842                 return IXGBE_SUCCESS;
 843         if (enable_eee)
 844                 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
 845         else
 846                 hw->phy.eee_speeds_advertised = 0;
 847         return hw->phy.ops.setup_link(hw);
 848 }
 849
 850 /**
 851 *  ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
 852 *  @hw: pointer to hardware structure
 853 *
 854 *  Initialize the function pointers and for MAC type X550EM_a.
 855 *  Does not touch the hardware.
 856 **/
 857 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
 858 {
 859         struct ixgbe_mac_info *mac = &hw->mac;
 860         s32 ret_val;
 861
 862         DEBUGFUNC("ixgbe_init_ops_X550EM_a");
 863
 864         /* Start with generic X550EM init */
 865         ret_val = ixgbe_init_ops_X550EM(hw);
 866
 867         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
 868             hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) {
 869                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 870                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 871         } else {
 872                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
 873                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
 874         }
 875         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
 876         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
 877
 878         switch (mac->ops.get_media_type(hw)) {
 879         case ixgbe_media_type_fiber:
 880                 mac->ops.setup_fc = NULL;
 881                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
 882                 break;
 883         case ixgbe_media_type_backplane:
 884                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
 885                 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
 886                 break;
 887         default:
 888                 break;
 889         }
 890
 891         if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T) ||
 892                 (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)) {
 893                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
 894                 mac->ops.setup_fc = ixgbe_fc_autoneg_fw;
 895         }
 896
 897         switch (hw->device_id) {
 898         case IXGBE_DEV_ID_X550EM_A_KR:
 899         case IXGBE_DEV_ID_X550EM_A_KR_L:
 900                 mac->ops.setup_eee = ixgbe_setup_eee_fw;
 901                 break;
 902         default:
 903                 mac->ops.setup_eee = NULL;
 904         }
 905
 906         return ret_val;
 907 }
 908
 909 /**
 910 *  ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
 911 *  @hw: pointer to hardware structure
 912 *
 913 *  Initialize the function pointers and for MAC type X550EM_x.
 914 *  Does not touch the hardware.
 915 **/
 916 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
 917 {
 918         struct ixgbe_mac_info *mac = &hw->mac;
 919         struct ixgbe_link_info *link = &hw->link;
 920         s32 ret_val;
 921
 922         DEBUGFUNC("ixgbe_init_ops_X550EM_x");
 923
 924         /* Start with generic X550EM init */
 925         ret_val = ixgbe_init_ops_X550EM(hw);
 926
 927         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 928         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 929         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 930         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 931         link->ops.read_link = ixgbe_read_i2c_combined_generic;
 932         link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
 933         link->ops.write_link = ixgbe_write_i2c_combined_generic;
 934         link->ops.write_link_unlocked =
 935                                       ixgbe_write_i2c_combined_generic_unlocked;
 936         link->addr = IXGBE_CS4227;
 937
 938         return ret_val;
 939 }
 940
 941 /**
 942  *  ixgbe_dmac_config_X550
 943  *  @hw: pointer to hardware structure
 944  *
 945  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 946  *  When disabling dmac, dmac enable dmac bit is cleared.
 947  **/
 948 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 949 {
 950         u32 reg, high_pri_tc;
 951
 952         DEBUGFUNC("ixgbe_dmac_config_X550");
 953
 954         /* Disable DMA coalescing before configuring */
 955         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 956         reg &= ~IXGBE_DMACR_DMAC_EN;
 957         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 958
 959         /* Disable DMA Coalescing if the watchdog timer is 0 */
 960         if (!hw->mac.dmac_config.watchdog_timer)
 961                 goto out;
 962
 963         ixgbe_dmac_config_tcs_X550(hw);
 964
 965         /* Configure DMA Coalescing Control Register */
 966         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 967
 968         /* Set the watchdog timer in units of 40.96 usec */
 969         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 970         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 971
 972         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 973         /* If fcoe is enabled, set high priority traffic class */
 974         if (hw->mac.dmac_config.fcoe_en) {
 975                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 976                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 977                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 978         }
 979         reg |= IXGBE_DMACR_EN_MNG_IND;
 980
 981         /* Enable DMA coalescing after configuration */
 982         reg |= IXGBE_DMACR_DMAC_EN;
 983         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 984
 985 out:
 986         return IXGBE_SUCCESS;
 987 }
 988
 989 /**
 990  *  ixgbe_dmac_config_tcs_X550
 991  *  @hw: pointer to hardware structure
 992  *
 993  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 994  *  be cleared before configuring.
 995  **/
 996 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 997 {
 998         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 999
1000         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
1001
1002         /* Configure DMA coalescing enabled */
1003         switch (hw->mac.dmac_config.link_speed) {
1004         case IXGBE_LINK_SPEED_10_FULL:
1005         case IXGBE_LINK_SPEED_100_FULL:
1006                 pb_headroom = IXGBE_DMACRXT_100M;
1007                 break;
1008         case IXGBE_LINK_SPEED_1GB_FULL:
1009                 pb_headroom = IXGBE_DMACRXT_1G;
1010                 break;
1011         default:
1012                 pb_headroom = IXGBE_DMACRXT_10G;
1013                 break;
1014         }
1015
1016         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
1017                              IXGBE_MHADD_MFS_SHIFT) / 1024);
1018
1019         /* Set the per Rx packet buffer receive threshold */
1020         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
1021                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
1022                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
1023
1024                 if (tc < hw->mac.dmac_config.num_tcs) {
1025                         /* Get Rx PB size */
1026                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
1027                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
1028                                 IXGBE_RXPBSIZE_SHIFT;
1029
1030                         /* Calculate receive buffer threshold in kilobytes */
1031                         if (rx_pb_size > pb_headroom)
1032                                 rx_pb_size = rx_pb_size - pb_headroom;
1033                         else
1034                                 rx_pb_size = 0;
1035
1036                         /* Minimum of MFS shall be set for DMCTH */
1037                         reg |= (rx_pb_size > maxframe_size_kb) ?
1038                                 rx_pb_size : maxframe_size_kb;
1039                 }
1040                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
1041         }
1042         return IXGBE_SUCCESS;
1043 }
1044
1045 /**
1046  *  ixgbe_dmac_update_tcs_X550
1047  *  @hw: pointer to hardware structure
1048  *
1049  *  Disables dmac, updates per TC settings, and then enables dmac.
1050  **/
1051 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
1052 {
1053         u32 reg;
1054
1055         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
1056
1057         /* Disable DMA coalescing before configuring */
1058         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
1059         reg &= ~IXGBE_DMACR_DMAC_EN;
1060         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
1061
1062         ixgbe_dmac_config_tcs_X550(hw);
1063
1064         /* Enable DMA coalescing after configuration */
1065         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
1066         reg |= IXGBE_DMACR_DMAC_EN;
1067         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
1068
1069         return IXGBE_SUCCESS;
1070 }
1071
1072 /**
1073  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
1074  *  @hw: pointer to hardware structure
1075  *
1076  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
1077  *  ixgbe_hw struct in order to set up EEPROM access.
1078  **/
1079 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
1080 {
1081         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1082         u32 eec;
1083         u16 eeprom_size;
1084
1085         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
1086
1087         if (eeprom->type == ixgbe_eeprom_uninitialized) {
1088                 eeprom->semaphore_delay = 10;
1089                 eeprom->type = ixgbe_flash;
1090
1091                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1092                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1093                                     IXGBE_EEC_SIZE_SHIFT);
1094                 eeprom->word_size = 1 << (eeprom_size +
1095                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
1096
1097                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
1098                           eeprom->type, eeprom->word_size);
1099         }
1100
1101         return IXGBE_SUCCESS;
1102 }
1103
1104 /**
1105  * ixgbe_enable_eee_x550 - Enable EEE support
1106  * @hw: pointer to hardware structure
1107  */
1108 STATIC s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
1109 {
1110         u32 link_reg;
1111         s32 status;
1112
1113         switch (hw->device_id) {
1114         case IXGBE_DEV_ID_X550EM_A_KR:
1115         case IXGBE_DEV_ID_X550EM_A_KR_L:
1116                 status = hw->mac.ops.read_iosf_sb_reg(hw,
1117                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1118                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
1119                 if (status != IXGBE_SUCCESS)
1120                         return status;
1121
1122                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
1123                             IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
1124
1125                 /* Don't advertise FEC capability when EEE enabled. */
1126                 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
1127
1128                 status = hw->mac.ops.write_iosf_sb_reg(hw,
1129                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1130                                         IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
1131                 if (status != IXGBE_SUCCESS)
1132                         return status;
1133                 break;
1134         default:
1135                 break;
1136         }
1137
1138         return IXGBE_SUCCESS;
1139 }
1140
1141 /**
1142  * ixgbe_disable_eee_x550 - Disable EEE support
1143  * @hw: pointer to hardware structure
1144  */
1145 STATIC s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
1146 {
1147         u32 link_reg;
1148         s32 status;
1149
1150         switch (hw->device_id) {
1151         case IXGBE_DEV_ID_X550EM_X_KR:
1152         case IXGBE_DEV_ID_X550EM_A_KR:
1153         case IXGBE_DEV_ID_X550EM_A_KR_L:
1154                 status = hw->mac.ops.read_iosf_sb_reg(hw,
1155                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1156                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
1157                 if (status != IXGBE_SUCCESS)
1158                         return status;
1159
1160                 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
1161                               IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
1162
1163                 /* Advertise FEC capability when EEE is disabled. */
1164                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
1165
1166                 status = hw->mac.ops.write_iosf_sb_reg(hw,
1167                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1168                                         IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
1169                 if (status != IXGBE_SUCCESS)
1170                         return status;
1171                 break;
1172         default:
1173                 break;
1174         }
1175
1176         return IXGBE_SUCCESS;
1177 }
1178
1179 /**
1180  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
1181  *  @hw: pointer to the HW structure
1182  *  @enable_eee: boolean flag to enable EEE
1183  *
1184  *  Enable/disable EEE based on enable_eee flag.
1185  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
1186  *  are modified.
1187  *
1188  **/
1189 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
1190 {
1191         s32 status;
1192         u32 eeer;
1193
1194         DEBUGFUNC("ixgbe_setup_eee_X550");
1195
1196         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
1197         /* Enable or disable EEE per flag */
1198         if (enable_eee) {
1199                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1200
1201                 status = ixgbe_enable_eee_x550(hw);
1202                 if (status)
1203                         return status;
1204         } else {
1205                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1206
1207                 status = ixgbe_disable_eee_x550(hw);
1208                 if (status)
1209                         return status;
1210         }
1211         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
1212
1213         return IXGBE_SUCCESS;
1214 }
1215
1216 /**
1217  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1218  * @hw: pointer to hardware structure
1219  * @enable: enable or disable source address pruning
1220  * @pool: Rx pool to set source address pruning for
1221  **/
1222 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1223                                            unsigned int pool)
1224 {
1225         u64 pfflp;
1226
1227         /* max rx pool is 63 */
1228         if (pool > 63)
1229                 return;
1230
1231         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1232         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1233
1234         if (enable)
1235                 pfflp |= (1ULL << pool);
1236         else
1237                 pfflp &= ~(1ULL << pool);
1238
1239         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1240         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1241 }
1242
1243 /**
1244  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1245  *  @hw: pointer to hardware structure
1246  *  @enable: enable or disable switch for Ethertype anti-spoofing
1247  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1248  *
1249  **/
1250 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1251                 bool enable, int vf)
1252 {
1253         int vf_target_reg = vf >> 3;
1254         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1255         u32 pfvfspoof;
1256
1257         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1258
1259         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1260         if (enable)
1261                 pfvfspoof |= (1 << vf_target_shift);
1262         else
1263                 pfvfspoof &= ~(1 << vf_target_shift);
1264
1265         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1266 }
1267
1268 /**
1269  * ixgbe_iosf_wait - Wait for IOSF command completion
1270  * @hw: pointer to hardware structure
1271  * @ctrl: pointer to location to receive final IOSF control value
1272  *
1273  * Returns failing status on timeout
1274  *
1275  * Note: ctrl can be NULL if the IOSF control register value is not needed
1276  **/
1277 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1278 {
1279         u32 i, command = 0;
1280
1281         /* Check every 10 usec to see if the address cycle completed.
1282          * The SB IOSF BUSY bit will clear when the operation is
1283          * complete
1284          */
1285         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1286                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1287                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1288                         break;
1289                 usec_delay(10);
1290         }
1291         if (ctrl)
1292                 *ctrl = command;
1293         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1294                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1295                 return IXGBE_ERR_PHY;
1296         }
1297
1298         return IXGBE_SUCCESS;
1299 }
1300
1301 /**
1302  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register
1303  *  of the IOSF device
1304  *  @hw: pointer to hardware structure
1305  *  @reg_addr: 32 bit PHY register to write
1306  *  @device_type: 3 bit device type
1307  *  @data: Data to write to the register
1308  **/
1309 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1310                             u32 device_type, u32 data)
1311 {
1312         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1313         u32 command, error;
1314         s32 ret;
1315
1316         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1317         if (ret != IXGBE_SUCCESS)
1318                 return ret;
1319
1320         ret = ixgbe_iosf_wait(hw, NULL);
1321         if (ret != IXGBE_SUCCESS)
1322                 goto out;
1323
1324         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1325                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1326
1327         /* Write IOSF control register */
1328         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1329
1330         /* Write IOSF data register */
1331         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1332
1333         ret = ixgbe_iosf_wait(hw, &command);
1334
1335         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1336                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1337                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1338                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1339                               "Failed to write, error %x\n", error);
1340                 ret = IXGBE_ERR_PHY;
1341         }
1342
1343 out:
1344         ixgbe_release_swfw_semaphore(hw, gssr);
1345         return ret;
1346 }
1347
1348 /**
1349  *  ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device
1350  *  @hw: pointer to hardware structure
1351  *  @reg_addr: 32 bit PHY register to write
1352  *  @device_type: 3 bit device type
1353  *  @data: Pointer to read data from the register
1354  **/
1355 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1356                            u32 device_type, u32 *data)
1357 {
1358         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1359         u32 command, error;
1360         s32 ret;
1361
1362         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1363         if (ret != IXGBE_SUCCESS)
1364                 return ret;
1365
1366         ret = ixgbe_iosf_wait(hw, NULL);
1367         if (ret != IXGBE_SUCCESS)
1368                 goto out;
1369
1370         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1371                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1372
1373         /* Write IOSF control register */
1374         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1375
1376         ret = ixgbe_iosf_wait(hw, &command);
1377
1378         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1379                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1380                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1381                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1382                                 "Failed to read, error %x\n", error);
1383                 ret = IXGBE_ERR_PHY;
1384         }
1385
1386         if (ret == IXGBE_SUCCESS)
1387                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1388
1389 out:
1390         ixgbe_release_swfw_semaphore(hw, gssr);
1391         return ret;
1392 }
1393
1394 /**
1395  * ixgbe_get_phy_token - Get the token for shared phy access
1396  * @hw: Pointer to hardware structure
1397  */
1398
1399 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1400 {
1401         struct ixgbe_hic_phy_token_req token_cmd;
1402         s32 status;
1403
1404         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1405         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1406         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1407         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1408         token_cmd.port_number = hw->bus.lan_id;
1409         token_cmd.command_type = FW_PHY_TOKEN_REQ;
1410         token_cmd.pad = 0;
1411         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1412                                               sizeof(token_cmd),
1413                                               IXGBE_HI_COMMAND_TIMEOUT,
1414                                               true);
1415         if (status)
1416                 return status;
1417         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1418                 return IXGBE_SUCCESS;
1419         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1420                 return IXGBE_ERR_FW_RESP_INVALID;
1421
1422         return IXGBE_ERR_TOKEN_RETRY;
1423 }
1424
1425 /**
1426  * ixgbe_put_phy_token - Put the token for shared phy access
1427  * @hw: Pointer to hardware structure
1428  */
1429
1430 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1431 {
1432         struct ixgbe_hic_phy_token_req token_cmd;
1433         s32 status;
1434
1435         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1436         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1437         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1438         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1439         token_cmd.port_number = hw->bus.lan_id;
1440         token_cmd.command_type = FW_PHY_TOKEN_REL;
1441         token_cmd.pad = 0;
1442         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1443                                               sizeof(token_cmd),
1444                                               IXGBE_HI_COMMAND_TIMEOUT,
1445                                               true);
1446         if (status)
1447                 return status;
1448         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1449                 return IXGBE_SUCCESS;
1450
1451         DEBUGOUT("Put PHY Token host interface command failed");
1452         return IXGBE_ERR_FW_RESP_INVALID;
1453 }
1454
1455 /**
1456  *  ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1457  *  of the IOSF device
1458  *  @hw: pointer to hardware structure
1459  *  @reg_addr: 32 bit PHY register to write
1460  *  @device_type: 3 bit device type
1461  *  @data: Data to write to the register
1462  **/
1463 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1464                                   u32 device_type, u32 data)
1465 {
1466         struct ixgbe_hic_internal_phy_req write_cmd;
1467         s32 status;
1468         UNREFERENCED_1PARAMETER(device_type);
1469
1470         memset(&write_cmd, 0, sizeof(write_cmd));
1471         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1472         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1473         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1474         write_cmd.port_number = hw->bus.lan_id;
1475         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1476         write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1477         write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1478
1479         status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1480                                               sizeof(write_cmd),
1481                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1482
1483         return status;
1484 }
1485
1486 /**
1487  *  ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device
1488  *  @hw: pointer to hardware structure
1489  *  @reg_addr: 32 bit PHY register to write
1490  *  @device_type: 3 bit device type
1491  *  @data: Pointer to read data from the register
1492  **/
1493 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1494                                  u32 device_type, u32 *data)
1495 {
1496         union {
1497                 struct ixgbe_hic_internal_phy_req cmd;
1498                 struct ixgbe_hic_internal_phy_resp rsp;
1499         } hic;
1500         s32 status;
1501         UNREFERENCED_1PARAMETER(device_type);
1502
1503         memset(&hic, 0, sizeof(hic));
1504         hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1505         hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1506         hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1507         hic.cmd.port_number = hw->bus.lan_id;
1508         hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1509         hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1510
1511         status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1512                                               sizeof(hic.cmd),
1513                                               IXGBE_HI_COMMAND_TIMEOUT, true);
1514
1515         /* Extract the register value from the response. */
1516         *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1517
1518         return status;
1519 }
1520
1521 /**
1522  *  ixgbe_disable_mdd_X550
1523  *  @hw: pointer to hardware structure
1524  *
1525  *  Disable malicious driver detection
1526  **/
1527 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1528 {
1529         u32 reg;
1530
1531         DEBUGFUNC("ixgbe_disable_mdd_X550");
1532
1533         /* Disable MDD for TX DMA and interrupt */
1534         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1535         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1536         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1537
1538         /* Disable MDD for RX and interrupt */
1539         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1540         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1541         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1542 }
1543
1544 /**
1545  *  ixgbe_enable_mdd_X550
1546  *  @hw: pointer to hardware structure
1547  *
1548  *  Enable malicious driver detection
1549  **/
1550 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1551 {
1552         u32 reg;
1553
1554         DEBUGFUNC("ixgbe_enable_mdd_X550");
1555
1556         /* Enable MDD for TX DMA and interrupt */
1557         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1558         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1559         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1560
1561         /* Enable MDD for RX and interrupt */
1562         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1563         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1564         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1565 }
1566
1567 /**
1568  *  ixgbe_restore_mdd_vf_X550
1569  *  @hw: pointer to hardware structure
1570  *  @vf: vf index
1571  *
1572  *  Restore VF that was disabled during malicious driver detection event
1573  **/
1574 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1575 {
1576         u32 idx, reg, num_qs, start_q, bitmask;
1577
1578         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1579
1580         /* Map VF to queues */
1581         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1582         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1583         case IXGBE_MRQC_VMDQRT8TCEN:
1584                 num_qs = 8;  /* 16 VFs / pools */
1585                 bitmask = 0x000000FF;
1586                 break;
1587         case IXGBE_MRQC_VMDQRSS32EN:
1588         case IXGBE_MRQC_VMDQRT4TCEN:
1589                 num_qs = 4;  /* 32 VFs / pools */
1590                 bitmask = 0x0000000F;
1591                 break;
1592         default:            /* 64 VFs / pools */
1593                 num_qs = 2;
1594                 bitmask = 0x00000003;
1595                 break;
1596         }
1597         start_q = vf * num_qs;
1598
1599         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1600         idx = start_q / 32;
1601         reg = 0;
1602         reg |= (bitmask << (start_q % 32));
1603         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1604         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1605 }
1606
1607 /**
1608  *  ixgbe_mdd_event_X550
1609  *  @hw: pointer to hardware structure
1610  *  @vf_bitmap: vf bitmap of malicious vfs
1611  *
1612  *  Handle malicious driver detection event.
1613  **/
1614 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1615 {
1616         u32 wqbr;
1617         u32 i, j, reg, q, shift, vf, idx;
1618
1619         DEBUGFUNC("ixgbe_mdd_event_X550");
1620
1621         /* figure out pool size for mapping to vf's */
1622         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1623         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1624         case IXGBE_MRQC_VMDQRT8TCEN:
1625                 shift = 3;  /* 16 VFs / pools */
1626                 break;
1627         case IXGBE_MRQC_VMDQRSS32EN:
1628         case IXGBE_MRQC_VMDQRT4TCEN:
1629                 shift = 2;  /* 32 VFs / pools */
1630                 break;
1631         default:
1632                 shift = 1;  /* 64 VFs / pools */
1633                 break;
1634         }
1635
1636         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1637         for (i = 0; i < 4; i++) {
1638                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1639                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1640
1641                 if (!wqbr)
1642                         continue;
1643
1644                 /* Get malicious queue */
1645                 for (j = 0; j < 32 && wqbr; j++) {
1646
1647                         if (!(wqbr & (1 << j)))
1648                                 continue;
1649
1650                         /* Get queue from bitmask */
1651                         q = j + (i * 32);
1652
1653                         /* Map queue to vf */
1654                         vf = (q >> shift);
1655
1656                         /* Set vf bit in vf_bitmap */
1657                         idx = vf / 32;
1658                         vf_bitmap[idx] |= (1 << (vf % 32));
1659                         wqbr &= ~(1 << j);
1660                 }
1661         }
1662 }
1663
1664 /**
1665  *  ixgbe_get_media_type_X550em - Get media type
1666  *  @hw: pointer to hardware structure
1667  *
1668  *  Returns the media type (fiber, copper, backplane)
1669  */
1670 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1671 {
1672         enum ixgbe_media_type media_type;
1673
1674         DEBUGFUNC("ixgbe_get_media_type_X550em");
1675
1676         /* Detect if there is a copper PHY attached. */
1677         switch (hw->device_id) {
1678         case IXGBE_DEV_ID_X550EM_X_KR:
1679         case IXGBE_DEV_ID_X550EM_X_KX4:
1680         case IXGBE_DEV_ID_X550EM_A_KR:
1681         case IXGBE_DEV_ID_X550EM_A_KR_L:
1682                 media_type = ixgbe_media_type_backplane;
1683                 break;
1684         case IXGBE_DEV_ID_X550EM_X_SFP:
1685         case IXGBE_DEV_ID_X550EM_A_SFP:
1686         case IXGBE_DEV_ID_X550EM_A_SFP_N:
1687         case IXGBE_DEV_ID_X550EM_A_QSFP:
1688         case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1689                 media_type = ixgbe_media_type_fiber;
1690                 break;
1691         case IXGBE_DEV_ID_X550EM_X_1G_T:
1692         case IXGBE_DEV_ID_X550EM_X_10G_T:
1693         case IXGBE_DEV_ID_X550EM_A_10G_T:
1694                 media_type = ixgbe_media_type_copper;
1695                 break;
1696         case IXGBE_DEV_ID_X550EM_A_SGMII:
1697         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1698                 media_type = ixgbe_media_type_backplane;
1699                 hw->phy.type = ixgbe_phy_sgmii;
1700                 break;
1701         case IXGBE_DEV_ID_X550EM_A_1G_T:
1702         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1703                 media_type = ixgbe_media_type_copper;
1704                 break;
1705         default:
1706                 media_type = ixgbe_media_type_unknown;
1707                 break;
1708         }
1709         return media_type;
1710 }
1711
1712 /**
1713  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1714  *  @hw: pointer to hardware structure
1715  *  @linear: true if SFP module is linear
1716  */
1717 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1718 {
1719         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1720
1721         switch (hw->phy.sfp_type) {
1722         case ixgbe_sfp_type_not_present:
1723                 return IXGBE_ERR_SFP_NOT_PRESENT;
1724         case ixgbe_sfp_type_da_cu_core0:
1725         case ixgbe_sfp_type_da_cu_core1:
1726                 *linear = true;
1727                 break;
1728         case ixgbe_sfp_type_srlr_core0:
1729         case ixgbe_sfp_type_srlr_core1:
1730         case ixgbe_sfp_type_da_act_lmt_core0:
1731         case ixgbe_sfp_type_da_act_lmt_core1:
1732         case ixgbe_sfp_type_1g_sx_core0:
1733         case ixgbe_sfp_type_1g_sx_core1:
1734         case ixgbe_sfp_type_1g_lx_core0:
1735         case ixgbe_sfp_type_1g_lx_core1:
1736                 *linear = false;
1737                 break;
1738         case ixgbe_sfp_type_unknown:
1739         case ixgbe_sfp_type_1g_cu_core0:
1740         case ixgbe_sfp_type_1g_cu_core1:
1741         default:
1742                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1743         }
1744
1745         return IXGBE_SUCCESS;
1746 }
1747
1748 /**
1749  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1750  *  @hw: pointer to hardware structure
1751  *
1752  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1753  **/
1754 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1755 {
1756         s32 status;
1757         bool linear;
1758
1759         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1760
1761         status = ixgbe_identify_module_generic(hw);
1762
1763         if (status != IXGBE_SUCCESS)
1764                 return status;
1765
1766         /* Check if SFP module is supported */
1767         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1768
1769         return status;
1770 }
1771
1772 /**
1773  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1774  *  @hw: pointer to hardware structure
1775  */
1776 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1777 {
1778         s32 status;
1779         bool linear;
1780
1781         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1782
1783         /* Check if SFP module is supported */
1784         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1785
1786         if (status != IXGBE_SUCCESS)
1787                 return status;
1788
1789         ixgbe_init_mac_link_ops_X550em(hw);
1790         hw->phy.ops.reset = NULL;
1791
1792         return IXGBE_SUCCESS;
1793 }
1794
1795 /**
1796 *  ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1797 *  internal PHY
1798 *  @hw: pointer to hardware structure
1799 **/
1800 STATIC s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1801 {
1802         s32 status;
1803         u32 link_ctrl;
1804
1805         /* Restart auto-negotiation. */
1806         status = hw->mac.ops.read_iosf_sb_reg(hw,
1807                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1808                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1809
1810         if (status) {
1811                 DEBUGOUT("Auto-negotiation did not complete\n");
1812                 return status;
1813         }
1814
1815         link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1816         status = hw->mac.ops.write_iosf_sb_reg(hw,
1817                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1818                                         IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1819
1820         if (hw->mac.type == ixgbe_mac_X550EM_a) {
1821                 u32 flx_mask_st20;
1822
1823                 /* Indicate to FW that AN restart has been asserted */
1824                 status = hw->mac.ops.read_iosf_sb_reg(hw,
1825                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1826                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1827
1828                 if (status) {
1829                         DEBUGOUT("Auto-negotiation did not complete\n");
1830                         return status;
1831                 }
1832
1833                 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1834                 status = hw->mac.ops.write_iosf_sb_reg(hw,
1835                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1836                                 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1837         }
1838
1839         return status;
1840 }
1841
1842 /**
1843  * ixgbe_setup_sgmii - Set up link for sgmii
1844  * @hw: pointer to hardware structure
1845  */
1846 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1847                              bool autoneg_wait)
1848 {
1849         struct ixgbe_mac_info *mac = &hw->mac;
1850         u32 lval, sval, flx_val;
1851         s32 rc;
1852
1853         rc = mac->ops.read_iosf_sb_reg(hw,
1854                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1855                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1856         if (rc)
1857                 return rc;
1858
1859         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1860         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1861         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1862         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1863         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1864         rc = mac->ops.write_iosf_sb_reg(hw,
1865                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1866                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1867         if (rc)
1868                 return rc;
1869
1870         rc = mac->ops.read_iosf_sb_reg(hw,
1871                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1872                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1873         if (rc)
1874                 return rc;
1875
1876         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1877         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1878         rc = mac->ops.write_iosf_sb_reg(hw,
1879                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1880                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1881         if (rc)
1882                 return rc;
1883
1884         rc = mac->ops.read_iosf_sb_reg(hw,
1885                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1886                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1887         if (rc)
1888                 return rc;
1889
1890         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1891         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1892         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1893         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1894         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1895
1896         rc = mac->ops.write_iosf_sb_reg(hw,
1897                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1898                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1899         if (rc)
1900                 return rc;
1901
1902         rc = ixgbe_restart_an_internal_phy_x550em(hw);
1903         if (rc)
1904                 return rc;
1905
1906         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1907 }
1908
1909 /**
1910  * ixgbe_setup_sgmii_m88 - Set up link for sgmii with Marvell PHYs
1911  * @hw: pointer to hardware structure
1912  */
1913 STATIC s32 ixgbe_setup_sgmii_m88(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1914                                  bool autoneg_wait)
1915 {
1916         struct ixgbe_mac_info *mac = &hw->mac;
1917         u32 lval, sval, flx_val;
1918         s32 rc;
1919
1920         rc = mac->ops.read_iosf_sb_reg(hw,
1921                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1922                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1923         if (rc)
1924                 return rc;
1925
1926         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1927         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1928         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1929         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1930         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1931         rc = mac->ops.write_iosf_sb_reg(hw,
1932                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1933                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1934         if (rc)
1935                 return rc;
1936
1937         rc = mac->ops.read_iosf_sb_reg(hw,
1938                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1939                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1940         if (rc)
1941                 return rc;
1942
1943         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1944         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1945         rc = mac->ops.write_iosf_sb_reg(hw,
1946                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1947                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1948         if (rc)
1949                 return rc;
1950
1951         rc = mac->ops.write_iosf_sb_reg(hw,
1952                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1953                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1954         if (rc)
1955                 return rc;
1956
1957         rc = mac->ops.read_iosf_sb_reg(hw,
1958                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1959                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1960         if (rc)
1961                 return rc;
1962
1963         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1964         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
1965         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1966         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1967         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1968
1969         rc = mac->ops.write_iosf_sb_reg(hw,
1970                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1971                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1972         if (rc)
1973                 return rc;
1974
1975         rc = ixgbe_restart_an_internal_phy_x550em(hw);
1976
1977         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1978 }
1979
1980 /**
1981  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1982  *  @hw: pointer to hardware structure
1983  */
1984 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1985 {
1986         struct ixgbe_mac_info *mac = &hw->mac;
1987
1988         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1989
1990         switch (hw->mac.ops.get_media_type(hw)) {
1991         case ixgbe_media_type_fiber:
1992                 /* CS4227 does not support autoneg, so disable the laser control
1993                  * functions for SFP+ fiber
1994                  */
1995                 mac->ops.disable_tx_laser = NULL;
1996                 mac->ops.enable_tx_laser = NULL;
1997                 mac->ops.flap_tx_laser = NULL;
1998                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1999                 mac->ops.set_rate_select_speed =
2000                                         ixgbe_set_soft_rate_select_speed;
2001
2002                 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
2003                     (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
2004                         mac->ops.setup_mac_link =
2005                                                 ixgbe_setup_mac_link_sfp_x550a;
2006                 else
2007                         mac->ops.setup_mac_link =
2008                                                 ixgbe_setup_mac_link_sfp_x550em;
2009                 break;
2010         case ixgbe_media_type_copper:
2011                 if (hw->mac.type == ixgbe_mac_X550EM_a) {
2012                         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2013                             hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
2014                                 mac->ops.setup_link = ixgbe_setup_sgmii_m88;
2015                         } else {
2016                                 mac->ops.setup_link =
2017                                                   ixgbe_setup_mac_link_t_X550em;
2018                         }
2019                 } else {
2020                         mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
2021                         mac->ops.check_link = ixgbe_check_link_t_X550em;
2022                 }
2023                 break;
2024         case ixgbe_media_type_backplane:
2025                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
2026                     hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
2027                         mac->ops.setup_link = ixgbe_setup_sgmii;
2028                 break;
2029         default:
2030                 break;
2031         }
2032 }
2033
2034 /**
2035  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
2036  *  @hw: pointer to hardware structure
2037  *  @speed: pointer to link speed
2038  *  @autoneg: true when autoneg or autotry is enabled
2039  */
2040 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
2041                                        ixgbe_link_speed *speed,
2042                                        bool *autoneg)
2043 {
2044         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
2045
2046
2047         /* SFP */
2048         if (hw->phy.media_type == ixgbe_media_type_fiber) {
2049
2050                 /* CS4227 SFP must not enable auto-negotiation */
2051                 *autoneg = false;
2052
2053                 /* Check if 1G SFP module. */
2054                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
2055                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
2056                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
2057                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
2058                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
2059                         return IXGBE_SUCCESS;
2060                 }
2061
2062                 /* Link capabilities are based on SFP */
2063                 if (hw->phy.multispeed_fiber)
2064                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
2065                                  IXGBE_LINK_SPEED_1GB_FULL;
2066                 else
2067                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
2068         } else {
2069                 switch (hw->phy.type) {
2070                 case ixgbe_phy_m88:
2071                         *speed = IXGBE_LINK_SPEED_1GB_FULL |
2072                                  IXGBE_LINK_SPEED_100_FULL |
2073                                  IXGBE_LINK_SPEED_10_FULL;
2074                         break;
2075                 case ixgbe_phy_sgmii:
2076                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
2077                         break;
2078                 case ixgbe_phy_x550em_kr:
2079                         if (hw->mac.type == ixgbe_mac_X550EM_a) {
2080                                 /* check different backplane modes */
2081                                 if (hw->phy.nw_mng_if_sel &
2082                                            IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
2083                                         *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
2084                                         break;
2085                                 } else if (hw->device_id ==
2086                                                    IXGBE_DEV_ID_X550EM_A_KR_L) {
2087                                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
2088                                         break;
2089                                 }
2090                         }
2091                         /* fall through */
2092                 default:
2093                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
2094                                  IXGBE_LINK_SPEED_1GB_FULL;
2095                         break;
2096                 }
2097                 *autoneg = true;
2098         }
2099
2100         return IXGBE_SUCCESS;
2101 }
2102
2103 /**
2104  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
2105  * @hw: pointer to hardware structure
2106  * @lsc: pointer to boolean flag which indicates whether external Base T
2107  *       PHY interrupt is lsc
2108  *
2109  * Determime if external Base T PHY interrupt cause is high temperature
2110  * failure alarm or link status change.
2111  *
2112  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2113  * failure alarm, else return PHY access status.
2114  */
2115 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
2116 {
2117         u32 status;
2118         u16 reg;
2119
2120         *lsc = false;
2121
2122         /* Vendor alarm triggered */
2123         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2124                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2125                                       &reg);
2126
2127         if (status != IXGBE_SUCCESS ||
2128             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
2129                 return status;
2130
2131         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
2132         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
2133                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2134                                       &reg);
2135
2136         if (status != IXGBE_SUCCESS ||
2137             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2138             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
2139                 return status;
2140
2141         /* Global alarm triggered */
2142         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
2143                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2144                                       &reg);
2145
2146         if (status != IXGBE_SUCCESS)
2147                 return status;
2148
2149         /* If high temperature failure, then return over temp error and exit */
2150         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
2151                 /* power down the PHY in case the PHY FW didn't already */
2152                 ixgbe_set_copper_phy_power(hw, false);
2153                 return IXGBE_ERR_OVERTEMP;
2154         } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
2155                 /*  device fault alarm triggered */
2156                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
2157                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2158                                           &reg);
2159
2160                 if (status != IXGBE_SUCCESS)
2161                         return status;
2162
2163                 /* if device fault was due to high temp alarm handle and exit */
2164                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
2165                         /* power down the PHY in case the PHY FW didn't */
2166                         ixgbe_set_copper_phy_power(hw, false);
2167                         return IXGBE_ERR_OVERTEMP;
2168                 }
2169         }
2170
2171         /* Vendor alarm 2 triggered */
2172         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2173                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2174
2175         if (status != IXGBE_SUCCESS ||
2176             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
2177                 return status;
2178
2179         /* link connect/disconnect event occurred */
2180         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
2181                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2182
2183         if (status != IXGBE_SUCCESS)
2184                 return status;
2185
2186         /* Indicate LSC */
2187         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2188                 *lsc = true;
2189
2190         return IXGBE_SUCCESS;
2191 }
2192
2193 /**
2194  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2195  * @hw: pointer to hardware structure
2196  *
2197  * Enable link status change and temperature failure alarm for the external
2198  * Base T PHY
2199  *
2200  * Returns PHY access status
2201  */
2202 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2203 {
2204         u32 status;
2205         u16 reg;
2206         bool lsc;
2207
2208         /* Clear interrupt flags */
2209         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2210
2211         /* Enable link status change alarm */
2212
2213         /* Enable the LASI interrupts on X552 devices to receive notifications
2214          * of the link configurations of the external PHY and correspondingly
2215          * support the configuration of the internal iXFI link, since iXFI does
2216          * not support auto-negotiation. This is not required for X553 devices
2217          * having KR support, which performs auto-negotiations and which is used
2218          * as the internal link to the external PHY. Hence adding a check here
2219          * to avoid enabling LASI interrupts for X553 devices.
2220          */
2221         if (hw->mac.type != ixgbe_mac_X550EM_a) {
2222                 status = hw->phy.ops.read_reg(hw,
2223                                         IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2224                                         IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2225
2226                 if (status != IXGBE_SUCCESS)
2227                         return status;
2228
2229                 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2230
2231                 status = hw->phy.ops.write_reg(hw,
2232                                         IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2233                                         IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
2234
2235                 if (status != IXGBE_SUCCESS)
2236                         return status;
2237         }
2238
2239         /* Enable high temperature failure and global fault alarms */
2240         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2241                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2242                                       &reg);
2243
2244         if (status != IXGBE_SUCCESS)
2245                 return status;
2246
2247         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2248                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2249
2250         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2251                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2252                                        reg);
2253
2254         if (status != IXGBE_SUCCESS)
2255                 return status;
2256
2257         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2258         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2259                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2260                                       &reg);
2261
2262         if (status != IXGBE_SUCCESS)
2263                 return status;
2264
2265         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2266                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2267
2268         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2269                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2270                                        reg);
2271
2272         if (status != IXGBE_SUCCESS)
2273                 return status;
2274
2275         /* Enable chip-wide vendor alarm */
2276         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2277                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2278                                       &reg);
2279
2280         if (status != IXGBE_SUCCESS)
2281                 return status;
2282
2283         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2284
2285         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2286                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2287                                        reg);
2288
2289         return status;
2290 }
2291
2292 /**
2293  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2294  *  @hw: pointer to hardware structure
2295  *  @speed: link speed
2296  *
2297  *  Configures the integrated KR PHY.
2298  **/
2299 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2300                                        ixgbe_link_speed speed)
2301 {
2302         s32 status;
2303         u32 reg_val;
2304
2305         status = hw->mac.ops.read_iosf_sb_reg(hw,
2306                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2307                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2308         if (status)
2309                 return status;
2310
2311         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2312         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2313                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2314
2315         /* Advertise 10G support. */
2316         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2317                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2318
2319         /* Advertise 1G support. */
2320         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2321                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2322
2323         status = hw->mac.ops.write_iosf_sb_reg(hw,
2324                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2325                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2326
2327         if (hw->mac.type == ixgbe_mac_X550EM_a) {
2328                 /* Set lane mode  to KR auto negotiation */
2329                 status = hw->mac.ops.read_iosf_sb_reg(hw,
2330                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2331                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2332
2333                 if (status)
2334                         return status;
2335
2336                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2337                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2338                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2339                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2340                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2341
2342                 status = hw->mac.ops.write_iosf_sb_reg(hw,
2343                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2344                                     IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2345         }
2346
2347         return ixgbe_restart_an_internal_phy_x550em(hw);
2348 }
2349
2350 /**
2351  * ixgbe_setup_m88 - setup m88 PHY
2352  * @hw: pointer to hardware structure
2353  */
2354 STATIC s32 ixgbe_setup_m88(struct ixgbe_hw *hw)
2355 {
2356         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2357         u16 reg;
2358         s32 rc;
2359
2360         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2361                 return IXGBE_SUCCESS;
2362
2363         rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2364         if (rc)
2365                 return rc;
2366
2367         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2368         if (rc)
2369                 goto out;
2370         if (reg & IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN) {
2371                 reg &= ~IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN;
2372                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2373                                           reg);
2374         }
2375
2376         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, &reg);
2377         if (rc)
2378                 goto out;
2379         if (reg & IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN) {
2380                 reg &= ~IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN;
2381                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0,
2382                                           reg);
2383         }
2384
2385         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 2);
2386         if (rc)
2387                 goto out;
2388
2389         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2390                                       &reg);
2391         if (rc)
2392                 goto out;
2393         if (reg & IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN) {
2394                 reg &= ~IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN;
2395                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2396                                           reg);
2397                 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2398                                                0);
2399                 if (rc)
2400                         goto out;
2401                 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2402                                               &reg);
2403                 if (rc)
2404                         goto out;
2405                 reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2406                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2407                                           reg);
2408                 usec_delay(50);
2409         } else {
2410                 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2411                                                0);
2412                 if (rc)
2413                         goto out;
2414         }
2415
2416         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2417         if (rc)
2418                 goto out;
2419
2420         if (!(reg & IXGBE_M88E1500_COPPER_CTRL_AN_EN)) {
2421                 reg |= IXGBE_M88E1500_COPPER_CTRL_AN_EN;
2422                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2423                                           reg);
2424         }
2425
2426         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, &reg);
2427         if (rc)
2428                 goto out;
2429         reg &= ~IXGBE_M88E1500_1000T_CTRL_HALF_DUPLEX;
2430         reg &= ~IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2431         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
2432                 reg |= IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2433         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, reg);
2434
2435         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, &reg);
2436         if (rc)
2437                 goto out;
2438         reg &= ~IXGBE_M88E1500_COPPER_AN_T4;
2439         reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_FD;
2440         reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_HD;
2441         reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_FD;
2442         reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_HD;
2443
2444         /* Flow control auto negotiation configuration was moved from here to
2445          * the function ixgbe_setup_fc_sgmii_x550em_a()
2446          */
2447
2448         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
2449                 reg |= IXGBE_M88E1500_COPPER_AN_100TX_FD;
2450         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL)
2451                 reg |= IXGBE_M88E1500_COPPER_AN_10TX_FD;
2452         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, reg);
2453
2454         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2455         if (rc)
2456                 goto out;
2457         reg |= IXGBE_M88E1500_COPPER_CTRL_RESTART_AN;
2458         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2459
2460
2461         hw->mac.ops.release_swfw_sync(hw, mask);
2462         return rc;
2463
2464 out:
2465         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2466         hw->mac.ops.release_swfw_sync(hw, mask);
2467         return rc;
2468 }
2469
2470 /**
2471  * ixgbe_reset_phy_m88e1500 - Reset m88e1500 PHY
2472  * @hw: pointer to hardware structure
2473  *
2474  * The PHY token must be held when calling this function.
2475  */
2476 static s32 ixgbe_reset_phy_m88e1500(struct ixgbe_hw *hw)
2477 {
2478         u16 reg;
2479         s32 rc;
2480
2481         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2482         if (rc)
2483                 return rc;
2484
2485         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2486         if (rc)
2487                 return rc;
2488
2489         reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2490         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2491
2492         usec_delay(10);
2493
2494         return rc;
2495 }
2496
2497 /**
2498  * ixgbe_reset_phy_m88e1543 - Reset m88e1543 PHY
2499  * @hw: pointer to hardware structure
2500  *
2501  * The PHY token must be held when calling this function.
2502  */
2503 static s32 ixgbe_reset_phy_m88e1543(struct ixgbe_hw *hw)
2504 {
2505         return hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2506 }
2507
2508 /**
2509  * ixgbe_reset_phy_m88 - Reset m88 PHY
2510  * @hw: pointer to hardware structure
2511  */
2512 STATIC s32 ixgbe_reset_phy_m88(struct ixgbe_hw *hw)
2513 {
2514         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2515         u16 reg;
2516         s32 rc;
2517
2518         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2519                 return IXGBE_SUCCESS;
2520
2521         rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2522         if (rc)
2523                 return rc;
2524
2525         switch (hw->phy.id) {
2526         case IXGBE_M88E1500_E_PHY_ID:
2527                 rc = ixgbe_reset_phy_m88e1500(hw);
2528                 break;
2529         case IXGBE_M88E1543_E_PHY_ID:
2530                 rc = ixgbe_reset_phy_m88e1543(hw);
2531                 break;
2532         default:
2533                 rc = IXGBE_ERR_PHY;
2534                 break;
2535         }
2536
2537         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2538         if (rc)
2539                 goto out;
2540
2541         reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2542               IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2543               IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2544         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2545         if (rc)
2546                 goto out;
2547
2548         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 18);
2549         if (rc)
2550                 goto out;
2551
2552         reg = IXGBE_M88E1500_GEN_CTRL_RESET |
2553               IXGBE_M88E1500_GEN_CTRL_MODE_SGMII_COPPER;
2554         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_GEN_CTRL, 0, reg);
2555         if (rc)
2556                 goto out;
2557
2558         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2559         if (rc)
2560                 goto out;
2561
2562         reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2563               IXGBE_M88E1500_FIBER_CTRL_AN_EN |
2564               IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2565               IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2566         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2567         if (rc)
2568                 goto out;
2569
2570         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2571         if (rc)
2572                 goto out;
2573
2574         reg = (IXGBE_M88E1500_MAC_CTRL_1_DWN_4X <<
2575                IXGBE_M88E1500_MAC_CTRL_1_DWN_SHIFT) |
2576               (IXGBE_M88E1500_MAC_CTRL_1_ED_TM <<
2577                IXGBE_M88E1500_MAC_CTRL_1_ED_SHIFT) |
2578               (IXGBE_M88E1500_MAC_CTRL_1_MDIX_AUTO <<
2579                IXGBE_M88E1500_MAC_CTRL_1_MDIX_SHIFT);
2580         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, reg);
2581         if (rc)
2582                 goto out;
2583
2584         reg = IXGBE_M88E1500_COPPER_CTRL_RESET |
2585               IXGBE_M88E1500_COPPER_CTRL_AN_EN |
2586               IXGBE_M88E1500_COPPER_CTRL_RESTART_AN |
2587               IXGBE_M88E1500_COPPER_CTRL_FULL_DUPLEX |
2588               IXGBE_M88E1500_COPPER_CTRL_SPEED_MSB;
2589         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2590         if (rc)
2591                 goto out;
2592
2593         hw->mac.ops.release_swfw_sync(hw, mask);
2594
2595         /* In case of first reset set advertised speeds to default value */
2596         if (!hw->phy.autoneg_advertised)
2597                 hw->phy.autoneg_advertised = IXGBE_LINK_SPEED_1GB_FULL |
2598                                              IXGBE_LINK_SPEED_100_FULL |
2599                                              IXGBE_LINK_SPEED_10_FULL;
2600
2601         return ixgbe_setup_m88(hw);
2602
2603 out:
2604         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2605         hw->mac.ops.release_swfw_sync(hw, mask);
2606         return rc;
2607 }
2608
2609 /**
2610  *  ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2611  *  @hw: pointer to hardware structure
2612  *
2613  *  Read NW_MNG_IF_SEL register and save field values, and check for valid field
2614  *  values.
2615  **/
2616 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2617 {
2618         /* Save NW management interface connected on board. This is used
2619          * to determine internal PHY mode.
2620          */
2621         hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2622
2623         /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2624          * PHY address. This register field was has only been used for X552.
2625          */
2626         if (hw->mac.type == ixgbe_mac_X550EM_a &&
2627             hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2628                 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2629                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2630                                IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2631         }
2632
2633         return IXGBE_SUCCESS;
2634 }
2635
2636 /**
2637  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2638  *  @hw: pointer to hardware structure
2639  *
2640  *  Initialize any function pointers that were not able to be
2641  *  set during init_shared_code because the PHY/SFP type was
2642  *  not known.  Perform the SFP init if necessary.
2643  */
2644 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2645 {
2646         struct ixgbe_phy_info *phy = &hw->phy;
2647         s32 ret_val;
2648
2649         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2650
2651         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2652                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2653                 ixgbe_setup_mux_ctl(hw);
2654                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2655         }
2656
2657         switch (hw->device_id) {
2658         case IXGBE_DEV_ID_X550EM_A_1G_T:
2659         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2660                 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2661                 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2662                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2663                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2664                 if (hw->bus.lan_id)
2665                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2666                 else
2667                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2668
2669                 break;
2670         case IXGBE_DEV_ID_X550EM_A_10G_T:
2671         case IXGBE_DEV_ID_X550EM_A_SFP:
2672                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2673                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2674                 if (hw->bus.lan_id)
2675                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2676                 else
2677                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2678                 break;
2679         case IXGBE_DEV_ID_X550EM_X_SFP:
2680                 /* set up for CS4227 usage */
2681                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2682                 break;
2683         default:
2684                 break;
2685         }
2686
2687         /* Identify the PHY or SFP module */
2688         ret_val = phy->ops.identify(hw);
2689         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
2690                 return ret_val;
2691
2692         /* Setup function pointers based on detected hardware */
2693         ixgbe_init_mac_link_ops_X550em(hw);
2694         if (phy->sfp_type != ixgbe_sfp_type_unknown)
2695                 phy->ops.reset = NULL;
2696
2697         /* Set functions pointers based on phy type */
2698         switch (hw->phy.type) {
2699         case ixgbe_phy_x550em_kx4:
2700                 phy->ops.setup_link = NULL;
2701                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2702                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2703                 break;
2704         case ixgbe_phy_x550em_kr:
2705                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2706                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2707                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2708                 break;
2709         case ixgbe_phy_x550em_ext_t:
2710                 /* If internal link mode is XFI, then setup iXFI internal link,
2711                  * else setup KR now.
2712                  */
2713                 phy->ops.setup_internal_link =
2714                                               ixgbe_setup_internal_phy_t_x550em;
2715
2716                 /* setup SW LPLU only for first revision of X550EM_x */
2717                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2718                     !(IXGBE_FUSES0_REV_MASK &
2719                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2720                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2721
2722                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2723                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2724                 break;
2725         case ixgbe_phy_sgmii:
2726                 phy->ops.setup_link = NULL;
2727                 break;
2728         case ixgbe_phy_m88:
2729                 phy->ops.setup_link = ixgbe_setup_m88;
2730                 phy->ops.reset = ixgbe_reset_phy_m88;
2731                 break;
2732         default:
2733                 break;
2734         }
2735         return ret_val;
2736 }
2737
2738 /**
2739  * ixgbe_set_mdio_speed - Set MDIO clock speed
2740  *  @hw: pointer to hardware structure
2741  */
2742 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2743 {
2744         u32 hlreg0;
2745
2746         switch (hw->device_id) {
2747         case IXGBE_DEV_ID_X550EM_X_10G_T:
2748         case IXGBE_DEV_ID_X550EM_A_SGMII:
2749         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2750         case IXGBE_DEV_ID_X550EM_A_10G_T:
2751         case IXGBE_DEV_ID_X550EM_A_SFP:
2752         case IXGBE_DEV_ID_X550EM_A_QSFP:
2753                 /* Config MDIO clock speed before the first MDIO PHY access */
2754                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2755                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2756                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2757                 break;
2758         case IXGBE_DEV_ID_X550EM_A_1G_T:
2759         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2760                 /* Select fast MDIO clock speed for these devices */
2761                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2762                 hlreg0 |= IXGBE_HLREG0_MDCSPD;
2763                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2764                 break;
2765         default:
2766                 break;
2767         }
2768 }
2769
2770 /**
2771  *  ixgbe_reset_hw_X550em - Perform hardware reset
2772  *  @hw: pointer to hardware structure
2773  *
2774  *  Resets the hardware by resetting the transmit and receive units, masks
2775  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2776  *  reset.
2777  */
2778 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2779 {
2780         ixgbe_link_speed link_speed;
2781         s32 status;
2782         u32 ctrl = 0;
2783         u32 i;
2784         bool link_up = false;
2785
2786         DEBUGFUNC("ixgbe_reset_hw_X550em");
2787
2788         /* Call adapter stop to disable Tx/Rx and clear interrupts */
2789         status = hw->mac.ops.stop_adapter(hw);
2790         if (status != IXGBE_SUCCESS)
2791                 return status;
2792
2793         /* flush pending Tx transactions */
2794         ixgbe_clear_tx_pending(hw);
2795
2796         ixgbe_set_mdio_speed(hw);
2797
2798         /* PHY ops must be identified and initialized prior to reset */
2799         status = hw->phy.ops.init(hw);
2800
2801         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2802                 return status;
2803
2804         /* start the external PHY */
2805         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2806                 status = ixgbe_init_ext_t_x550em(hw);
2807                 if (status)
2808                         return status;
2809         }
2810
2811         /* Setup SFP module if there is one present. */
2812         if (hw->phy.sfp_setup_needed) {
2813                 status = hw->mac.ops.setup_sfp(hw);
2814                 hw->phy.sfp_setup_needed = false;
2815         }
2816
2817         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2818                 return status;
2819
2820         /* Reset PHY */
2821         if (!hw->phy.reset_disable && hw->phy.ops.reset)
2822                 hw->phy.ops.reset(hw);
2823
2824 mac_reset_top:
2825         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2826          * If link reset is used when link is up, it might reset the PHY when
2827          * mng is using it.  If link is down or the flag to force full link
2828          * reset is set, then perform link reset.
2829          */
2830         ctrl = IXGBE_CTRL_LNK_RST;
2831         if (!hw->force_full_reset) {
2832                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2833                 if (link_up)
2834                         ctrl = IXGBE_CTRL_RST;
2835         }
2836
2837         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2838         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2839         IXGBE_WRITE_FLUSH(hw);
2840
2841         /* Poll for reset bit to self-clear meaning reset is complete */
2842         for (i = 0; i < 10; i++) {
2843                 usec_delay(1);
2844                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2845                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2846                         break;
2847         }
2848
2849         if (ctrl & IXGBE_CTRL_RST_MASK) {
2850                 status = IXGBE_ERR_RESET_FAILED;
2851                 DEBUGOUT("Reset polling failed to complete.\n");
2852         }
2853
2854         msec_delay(50);
2855
2856         /* Double resets are required for recovery from certain error
2857          * conditions.  Between resets, it is necessary to stall to
2858          * allow time for any pending HW events to complete.
2859          */
2860         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2861                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2862                 goto mac_reset_top;
2863         }
2864
2865         /* Store the permanent mac address */
2866         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2867
2868         /* Store MAC address from RAR0, clear receive address registers, and
2869          * clear the multicast table.  Also reset num_rar_entries to 128,
2870          * since we modify this value when programming the SAN MAC address.
2871          */
2872         hw->mac.num_rar_entries = 128;
2873         hw->mac.ops.init_rx_addrs(hw);
2874
2875         ixgbe_set_mdio_speed(hw);
2876
2877         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2878                 ixgbe_setup_mux_ctl(hw);
2879
2880         return status;
2881 }
2882
2883 /**
2884  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2885  * @hw: pointer to hardware structure
2886  */
2887 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2888 {
2889         u32 status;
2890         u16 reg;
2891
2892         status = hw->phy.ops.read_reg(hw,
2893                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2894                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2895                                       &reg);
2896
2897         if (status != IXGBE_SUCCESS)
2898                 return status;
2899
2900         /* If PHY FW reset completed bit is set then this is the first
2901          * SW instance after a power on so the PHY FW must be un-stalled.
2902          */
2903         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2904                 status = hw->phy.ops.read_reg(hw,
2905                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2906                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2907                                         &reg);
2908
2909                 if (status != IXGBE_SUCCESS)
2910                         return status;
2911
2912                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2913
2914                 status = hw->phy.ops.write_reg(hw,
2915                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2916                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2917                                         reg);
2918
2919                 if (status != IXGBE_SUCCESS)
2920                         return status;
2921         }
2922
2923         return status;
2924 }
2925
2926 /**
2927  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
2928  *  @hw: pointer to hardware structure
2929  *
2930  *  Configures the integrated KR PHY for X550EM_x.
2931  **/
2932 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2933 {
2934         if (hw->mac.type != ixgbe_mac_X550EM_x)
2935                 return IXGBE_SUCCESS;
2936
2937         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2938 }
2939
2940 /**
2941  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2942  *  @hw: pointer to hardware structure
2943  *
2944  *  Configure the external PHY and the integrated KR PHY for SFP support.
2945  **/
2946 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2947                                     ixgbe_link_speed speed,
2948                                     bool autoneg_wait_to_complete)
2949 {
2950         s32 ret_val;
2951         u16 reg_slice, reg_val;
2952         bool setup_linear = false;
2953         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2954
2955         /* Check if SFP module is supported and linear */
2956         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2957
2958         /* If no SFP module present, then return success. Return success since
2959          * there is no reason to configure CS4227 and SFP not present error is
2960          * not excepted in the setup MAC link flow.
2961          */
2962         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2963                 return IXGBE_SUCCESS;
2964
2965         if (ret_val != IXGBE_SUCCESS)
2966                 return ret_val;
2967
2968         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2969                 /* Configure CS4227 LINE side to 10G SR. */
2970                 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
2971                             (hw->bus.lan_id << 12);
2972                 reg_val = IXGBE_CS4227_SPEED_10G;
2973                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2974                                                   reg_val);
2975
2976                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2977                             (hw->bus.lan_id << 12);
2978                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2979                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2980                                                   reg_val);
2981
2982                 /* Configure CS4227 for HOST connection rate then type. */
2983                 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
2984                             (hw->bus.lan_id << 12);
2985                 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
2986                 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
2987                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2988                                                   reg_val);
2989
2990                 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
2991                             (hw->bus.lan_id << 12);
2992                 if (setup_linear)
2993                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2994                 else
2995                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2996                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2997                                                   reg_val);
2998
2999                 /* Setup XFI internal link. */
3000                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
3001         } else {
3002                 /* Configure internal PHY for KR/KX. */
3003                 ixgbe_setup_kr_speed_x550em(hw, speed);
3004
3005                 /* Configure CS4227 LINE side to proper mode. */
3006                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
3007                             (hw->bus.lan_id << 12);
3008                 if (setup_linear)
3009                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
3010                 else
3011                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
3012                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
3013                                                   reg_val);
3014         }
3015         return ret_val;
3016 }
3017
3018 /**
3019  *  ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
3020  *  @hw: pointer to hardware structure
3021  *  @speed: the link speed to force
3022  *
3023  *  Configures the integrated PHY for native SFI mode. Used to connect the
3024  *  internal PHY directly to an SFP cage, without autonegotiation.
3025  **/
3026 STATIC s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
3027 {
3028         struct ixgbe_mac_info *mac = &hw->mac;
3029         s32 status;
3030         u32 reg_val;
3031
3032         /* Disable all AN and force speed to 10G Serial. */
3033         status = mac->ops.read_iosf_sb_reg(hw,
3034                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
3035                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3036         if (status != IXGBE_SUCCESS)
3037                 return status;
3038
3039         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
3040         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
3041         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
3042         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
3043
3044         /* Select forced link speed for internal PHY. */
3045         switch (*speed) {
3046         case IXGBE_LINK_SPEED_10GB_FULL:
3047                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
3048                 break;
3049         case IXGBE_LINK_SPEED_1GB_FULL:
3050                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
3051                 break;
3052         default:
3053                 /* Other link speeds are not supported by internal PHY. */
3054                 return IXGBE_ERR_LINK_SETUP;
3055         }
3056
3057         status = mac->ops.write_iosf_sb_reg(hw,
3058                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
3059                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3060
3061         /* Toggle port SW reset by AN reset. */
3062         status = ixgbe_restart_an_internal_phy_x550em(hw);
3063
3064         return status;
3065 }
3066
3067 /**
3068  *  ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
3069  *  @hw: pointer to hardware structure
3070  *
3071  *  Configure the the integrated PHY for SFP support.
3072  **/
3073 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
3074                                     ixgbe_link_speed speed,
3075                                     bool autoneg_wait_to_complete)
3076 {
3077         s32 ret_val;
3078         u16 reg_phy_ext;
3079         bool setup_linear = false;
3080         u32 reg_slice, reg_phy_int, slice_offset;
3081
3082         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
3083
3084         /* Check if SFP module is supported and linear */
3085         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
3086
3087         /* If no SFP module present, then return success. Return success since
3088          * SFP not present error is not excepted in the setup MAC link flow.
3089          */
3090         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
3091                 return IXGBE_SUCCESS;
3092
3093         if (ret_val != IXGBE_SUCCESS)
3094                 return ret_val;
3095
3096         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
3097                 /* Configure internal PHY for native SFI based on module type */
3098                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
3099                                    IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
3100                                    IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_phy_int);
3101
3102                 if (ret_val != IXGBE_SUCCESS)
3103                         return ret_val;
3104
3105                 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
3106                 if (!setup_linear)
3107                         reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
3108
3109                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
3110                                    IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
3111                                    IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
3112
3113                 if (ret_val != IXGBE_SUCCESS)
3114                         return ret_val;
3115
3116                 /* Setup SFI internal link. */
3117                 ret_val = ixgbe_setup_sfi_x550a(hw, &speed);
3118         } else {
3119                 /* Configure internal PHY for KR/KX. */
3120                 ixgbe_setup_kr_speed_x550em(hw, speed);
3121
3122                 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
3123                         /* Find Address */
3124                         DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
3125                         return IXGBE_ERR_PHY_ADDR_INVALID;
3126                 }
3127
3128                 /* Get external PHY SKU id */
3129                 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,
3130                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
3131
3132                 if (ret_val != IXGBE_SUCCESS)
3133                         return ret_val;
3134
3135                 /* When configuring quad port CS4223, the MAC instance is part
3136                  * of the slice offset.
3137                  */
3138                 if (reg_phy_ext == IXGBE_CS4223_SKU_ID)
3139                         slice_offset = (hw->bus.lan_id +
3140                                         (hw->bus.instance_id << 1)) << 12;
3141                 else
3142                         slice_offset = hw->bus.lan_id << 12;
3143
3144                 /* Configure CS4227/CS4223 LINE side to proper mode. */
3145                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
3146                 if (setup_linear)
3147                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
3148                 else
3149                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
3150                 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
3151                                          IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
3152         }
3153         return ret_val;
3154 }
3155
3156 /**
3157  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
3158  *  @hw: pointer to hardware structure
3159  *
3160  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
3161  **/
3162 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
3163 {
3164         struct ixgbe_mac_info *mac = &hw->mac;
3165         s32 status;
3166         u32 reg_val;
3167
3168         /* Disable training protocol FSM. */
3169         status = mac->ops.read_iosf_sb_reg(hw,
3170                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3171                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3172         if (status != IXGBE_SUCCESS)
3173                 return status;
3174         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
3175         status = mac->ops.write_iosf_sb_reg(hw,
3176                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3177                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3178         if (status != IXGBE_SUCCESS)
3179                 return status;
3180
3181         /* Disable Flex from training TXFFE. */
3182         status = mac->ops.read_iosf_sb_reg(hw,
3183                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
3184                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3185         if (status != IXGBE_SUCCESS)
3186                 return status;
3187         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
3188         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
3189         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
3190         status = mac->ops.write_iosf_sb_reg(hw,
3191                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
3192                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3193         if (status != IXGBE_SUCCESS)
3194                 return status;
3195         status = mac->ops.read_iosf_sb_reg(hw,
3196                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
3197                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3198         if (status != IXGBE_SUCCESS)
3199                 return status;
3200         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
3201         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
3202         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
3203         status = mac->ops.write_iosf_sb_reg(hw,
3204                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
3205                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3206         if (status != IXGBE_SUCCESS)
3207                 return status;
3208
3209         /* Enable override for coefficients. */
3210         status = mac->ops.read_iosf_sb_reg(hw,
3211                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
3212                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3213         if (status != IXGBE_SUCCESS)
3214                 return status;
3215         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
3216         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
3217         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
3218         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
3219         status = mac->ops.write_iosf_sb_reg(hw,
3220                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
3221                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3222         return status;
3223 }
3224
3225 /**
3226  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
3227  *  @hw: pointer to hardware structure
3228  *  @speed: the link speed to force
3229  *
3230  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
3231  *  internal and external PHY at a specific speed, without autonegotiation.
3232  **/
3233 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
3234 {
3235         struct ixgbe_mac_info *mac = &hw->mac;
3236         s32 status;
3237         u32 reg_val;
3238
3239         /* iXFI is only supported with X552 */
3240         if (mac->type != ixgbe_mac_X550EM_x)
3241                 return IXGBE_ERR_LINK_SETUP;
3242
3243         /* Disable AN and force speed to 10G Serial. */
3244         status = mac->ops.read_iosf_sb_reg(hw,
3245                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3246                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3247         if (status != IXGBE_SUCCESS)
3248                 return status;
3249
3250         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3251         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3252
3253         /* Select forced link speed for internal PHY. */
3254         switch (*speed) {
3255         case IXGBE_LINK_SPEED_10GB_FULL:
3256                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3257                 break;
3258         case IXGBE_LINK_SPEED_1GB_FULL:
3259                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
3260                 break;
3261         default:
3262                 /* Other link speeds are not supported by internal KR PHY. */
3263                 return IXGBE_ERR_LINK_SETUP;
3264         }
3265
3266         status = mac->ops.write_iosf_sb_reg(hw,
3267                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3268                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3269         if (status != IXGBE_SUCCESS)
3270                 return status;
3271
3272         /* Additional configuration needed for x550em_x */
3273         if (hw->mac.type == ixgbe_mac_X550EM_x) {
3274                 status = ixgbe_setup_ixfi_x550em_x(hw);
3275                 if (status != IXGBE_SUCCESS)
3276                         return status;
3277         }
3278
3279         /* Toggle port SW reset by AN reset. */
3280         status = ixgbe_restart_an_internal_phy_x550em(hw);
3281
3282         return status;
3283 }
3284
3285 /**
3286  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
3287  * @hw: address of hardware structure
3288  * @link_up: address of boolean to indicate link status
3289  *
3290  * Returns error code if unable to get link status.
3291  */
3292 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
3293 {
3294         u32 ret;
3295         u16 autoneg_status;
3296
3297         *link_up = false;
3298
3299         /* read this twice back to back to indicate current status */
3300         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3301                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3302                                    &autoneg_status);
3303         if (ret != IXGBE_SUCCESS)
3304                 return ret;
3305
3306         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3307                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3308                                    &autoneg_status);
3309         if (ret != IXGBE_SUCCESS)
3310                 return ret;
3311
3312         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
3313
3314         return IXGBE_SUCCESS;
3315 }
3316
3317 /**
3318  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
3319  * @hw: point to hardware structure
3320  *
3321  * Configures the link between the integrated KR PHY and the external X557 PHY
3322  * The driver will call this function when it gets a link status change
3323  * interrupt from the X557 PHY. This function configures the link speed
3324  * between the PHYs to match the link speed of the BASE-T link.
3325  *
3326  * A return of a non-zero value indicates an error, and the base driver should
3327  * not report link up.
3328  */
3329 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
3330 {
3331         ixgbe_link_speed force_speed;
3332         bool link_up;
3333         u32 status;
3334         u16 speed;
3335
3336         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3337                 return IXGBE_ERR_CONFIG;
3338
3339         if (hw->mac.type == ixgbe_mac_X550EM_x &&
3340             !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3341                 /* If link is down, there is no setup necessary so return  */
3342                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3343                 if (status != IXGBE_SUCCESS)
3344                         return status;
3345
3346                 if (!link_up)
3347                         return IXGBE_SUCCESS;
3348
3349                 status = hw->phy.ops.read_reg(hw,
3350                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3351                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3352                                               &speed);
3353                 if (status != IXGBE_SUCCESS)
3354                         return status;
3355
3356                 /* If link is still down - no setup is required so return */
3357                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3358                 if (status != IXGBE_SUCCESS)
3359                         return status;
3360                 if (!link_up)
3361                         return IXGBE_SUCCESS;
3362
3363                 /* clear everything but the speed and duplex bits */
3364                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
3365
3366                 switch (speed) {
3367                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
3368                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3369                         break;
3370                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
3371                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3372                         break;
3373                 default:
3374                         /* Internal PHY does not support anything else */
3375                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
3376                 }
3377
3378                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
3379         } else {
3380                 speed = IXGBE_LINK_SPEED_10GB_FULL |
3381                         IXGBE_LINK_SPEED_1GB_FULL;
3382                 return ixgbe_setup_kr_speed_x550em(hw, speed);
3383         }
3384 }
3385
3386 /**
3387  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
3388  *  @hw: pointer to hardware structure
3389  *
3390  *  Configures the integrated KR PHY to use internal loopback mode.
3391  **/
3392 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
3393 {
3394         s32 status;
3395         u32 reg_val;
3396
3397         /* Disable AN and force speed to 10G Serial. */
3398         status = hw->mac.ops.read_iosf_sb_reg(hw,
3399                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3400                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3401         if (status != IXGBE_SUCCESS)
3402                 return status;
3403         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3404         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3405         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3406         status = hw->mac.ops.write_iosf_sb_reg(hw,
3407                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3408                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3409         if (status != IXGBE_SUCCESS)
3410                 return status;
3411
3412         /* Set near-end loopback clocks. */
3413         status = hw->mac.ops.read_iosf_sb_reg(hw,
3414                                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3415                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3416         if (status != IXGBE_SUCCESS)
3417                 return status;
3418         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3419         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3420         status = hw->mac.ops.write_iosf_sb_reg(hw,
3421                                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3422                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3423         if (status != IXGBE_SUCCESS)
3424                 return status;
3425
3426         /* Set loopback enable. */
3427         status = hw->mac.ops.read_iosf_sb_reg(hw,
3428                                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3429                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3430         if (status != IXGBE_SUCCESS)
3431                 return status;
3432         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3433         status = hw->mac.ops.write_iosf_sb_reg(hw,
3434                                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3435                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3436         if (status != IXGBE_SUCCESS)
3437                 return status;
3438
3439         /* Training bypass. */
3440         status = hw->mac.ops.read_iosf_sb_reg(hw,
3441                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3442                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3443         if (status != IXGBE_SUCCESS)
3444                 return status;
3445         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3446         status = hw->mac.ops.write_iosf_sb_reg(hw,
3447                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3448                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3449
3450         return status;
3451 }
3452
3453 /**
3454  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3455  *  assuming that the semaphore is already obtained.
3456  *  @hw: pointer to hardware structure
3457  *  @offset: offset of  word in the EEPROM to read
3458  *  @data: word read from the EEPROM
3459  *
3460  *  Reads a 16 bit word from the EEPROM using the hostif.
3461  **/
3462 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
3463 {
3464         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3465         struct ixgbe_hic_read_shadow_ram buffer;
3466         s32 status;
3467
3468         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3469         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3470         buffer.hdr.req.buf_lenh = 0;
3471         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3472         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3473
3474         /* convert offset from words to bytes */
3475         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3476         /* one word */
3477         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3478
3479         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3480         if (status)
3481                 return status;
3482
3483         status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3484                                     IXGBE_HI_COMMAND_TIMEOUT);
3485         if (!status) {
3486                 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3487                                                   FW_NVM_DATA_OFFSET);
3488         }
3489
3490         hw->mac.ops.release_swfw_sync(hw, mask);
3491         return status;
3492 }
3493
3494 /**
3495  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3496  *  @hw: pointer to hardware structure
3497  *  @offset: offset of  word in the EEPROM to read
3498  *  @words: number of words
3499  *  @data: word(s) read from the EEPROM
3500  *
3501  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
3502  **/
3503 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3504                                      u16 offset, u16 words, u16 *data)
3505 {
3506         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3507         struct ixgbe_hic_read_shadow_ram buffer;
3508         u32 current_word = 0;
3509         u16 words_to_read;
3510         s32 status;
3511         u32 i;
3512
3513         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3514
3515         /* Take semaphore for the entire operation. */
3516         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3517         if (status) {
3518                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3519                 return status;
3520         }
3521
3522         while (words) {
3523                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3524                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3525                 else
3526                         words_to_read = words;
3527
3528                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3529                 buffer.hdr.req.buf_lenh = 0;
3530                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3531                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3532
3533                 /* convert offset from words to bytes */
3534                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3535                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3536
3537                 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3538                                             IXGBE_HI_COMMAND_TIMEOUT);
3539
3540                 if (status) {
3541                         DEBUGOUT("Host interface command failed\n");
3542                         goto out;
3543                 }
3544
3545                 for (i = 0; i < words_to_read; i++) {
3546                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3547                                   2 * i;
3548                         u32 value = IXGBE_READ_REG(hw, reg);
3549
3550                         data[current_word] = (u16)(value & 0xffff);
3551                         current_word++;
3552                         i++;
3553                         if (i < words_to_read) {
3554                                 value >>= 16;
3555                                 data[current_word] = (u16)(value & 0xffff);
3556                                 current_word++;
3557                         }
3558                 }
3559                 words -= words_to_read;
3560         }
3561
3562 out:
3563         hw->mac.ops.release_swfw_sync(hw, mask);
3564         return status;
3565 }
3566
3567 /**
3568  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3569  *  @hw: pointer to hardware structure
3570  *  @offset: offset of  word in the EEPROM to write
3571  *  @data: word write to the EEPROM
3572  *
3573  *  Write a 16 bit word to the EEPROM using the hostif.
3574  **/
3575 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3576                                     u16 data)
3577 {
3578         s32 status;
3579         struct ixgbe_hic_write_shadow_ram buffer;
3580
3581         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3582
3583         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3584         buffer.hdr.req.buf_lenh = 0;
3585         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3586         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3587
3588          /* one word */
3589         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3590         buffer.data = data;
3591         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3592
3593         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3594                                               sizeof(buffer),
3595                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3596
3597         return status;
3598 }
3599
3600 /**
3601  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3602  *  @hw: pointer to hardware structure
3603  *  @offset: offset of  word in the EEPROM to write
3604  *  @data: word write to the EEPROM
3605  *
3606  *  Write a 16 bit word to the EEPROM using the hostif.
3607  **/
3608 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3609                                u16 data)
3610 {
3611         s32 status = IXGBE_SUCCESS;
3612
3613         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3614
3615         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3616             IXGBE_SUCCESS) {
3617                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3618                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3619         } else {
3620                 DEBUGOUT("write ee hostif failed to get semaphore");
3621                 status = IXGBE_ERR_SWFW_SYNC;
3622         }
3623
3624         return status;
3625 }
3626
3627 /**
3628  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3629  *  @hw: pointer to hardware structure
3630  *  @offset: offset of  word in the EEPROM to write
3631  *  @words: number of words
3632  *  @data: word(s) write to the EEPROM
3633  *
3634  *  Write a 16 bit word(s) to the EEPROM using the hostif.
3635  **/
3636 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3637                                       u16 offset, u16 words, u16 *data)
3638 {
3639         s32 status = IXGBE_SUCCESS;
3640         u32 i = 0;
3641
3642         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3643
3644         /* Take semaphore for the entire operation. */
3645         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3646         if (status != IXGBE_SUCCESS) {
3647                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3648                 goto out;
3649         }
3650
3651         for (i = 0; i < words; i++) {
3652                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3653                                                          data[i]);
3654
3655                 if (status != IXGBE_SUCCESS) {
3656                         DEBUGOUT("Eeprom buffered write failed\n");
3657                         break;
3658                 }
3659         }
3660
3661         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3662 out:
3663
3664         return status;
3665 }
3666
3667 /**
3668  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3669  * @hw: pointer to hardware structure
3670  * @ptr: pointer offset in eeprom
3671  * @size: size of section pointed by ptr, if 0 first word will be used as size
3672  * @csum: address of checksum to update
3673  *
3674  * Returns error status for any failure
3675  */
3676 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3677                                    u16 size, u16 *csum, u16 *buffer,
3678                                    u32 buffer_size)
3679 {
3680         u16 buf[256];
3681         s32 status;
3682         u16 length, bufsz, i, start;
3683         u16 *local_buffer;
3684
3685         bufsz = sizeof(buf) / sizeof(buf[0]);
3686
3687         /* Read a chunk at the pointer location */
3688         if (!buffer) {
3689                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3690                 if (status) {
3691                         DEBUGOUT("Failed to read EEPROM image\n");
3692                         return status;
3693                 }
3694                 local_buffer = buf;
3695         } else {
3696                 if (buffer_size < ptr)
3697                         return  IXGBE_ERR_PARAM;
3698                 local_buffer = &buffer[ptr];
3699         }
3700
3701         if (size) {
3702                 start = 0;
3703                 length = size;
3704         } else {
3705                 start = 1;
3706                 length = local_buffer[0];
3707
3708                 /* Skip pointer section if length is invalid. */
3709                 if (length == 0xFFFF || length == 0 ||
3710                     (ptr + length) >= hw->eeprom.word_size)
3711                         return IXGBE_SUCCESS;
3712         }
3713
3714         if (buffer && ((u32)start + (u32)length > buffer_size))
3715                 return IXGBE_ERR_PARAM;
3716
3717         for (i = start; length; i++, length--) {
3718                 if (i == bufsz && !buffer) {
3719                         ptr += bufsz;
3720                         i = 0;
3721                         if (length < bufsz)
3722                                 bufsz = length;
3723
3724                         /* Read a chunk at the pointer location */
3725                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3726                                                                   bufsz, buf);
3727                         if (status) {
3728                                 DEBUGOUT("Failed to read EEPROM image\n");
3729                                 return status;
3730                         }
3731                 }
3732                 *csum += local_buffer[i];
3733         }
3734         return IXGBE_SUCCESS;
3735 }
3736
3737 /**
3738  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3739  *  @hw: pointer to hardware structure
3740  *  @buffer: pointer to buffer containing calculated checksum
3741  *  @buffer_size: size of buffer
3742  *
3743  *  Returns a negative error code on error, or the 16-bit checksum
3744  **/
3745 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3746 {
3747         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3748         u16 *local_buffer;
3749         s32 status;
3750         u16 checksum = 0;
3751         u16 pointer, i, size;
3752
3753         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3754
3755         hw->eeprom.ops.init_params(hw);
3756
3757         if (!buffer) {
3758                 /* Read pointer area */
3759                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3760                                                      IXGBE_EEPROM_LAST_WORD + 1,
3761                                                      eeprom_ptrs);
3762                 if (status) {
3763                         DEBUGOUT("Failed to read EEPROM image\n");
3764                         return status;
3765                 }
3766                 local_buffer = eeprom_ptrs;
3767         } else {
3768                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3769                         return IXGBE_ERR_PARAM;
3770                 local_buffer = buffer;
3771         }
3772
3773         /*
3774          * For X550 hardware include 0x0-0x41 in the checksum, skip the
3775          * checksum word itself
3776          */
3777         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3778                 if (i != IXGBE_EEPROM_CHECKSUM)
3779                         checksum += local_buffer[i];
3780
3781         /*
3782          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
3783          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3784          */
3785         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3786                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3787                         continue;
3788
3789                 pointer = local_buffer[i];
3790
3791                 /* Skip pointer section if the pointer is invalid. */
3792                 if (pointer == 0xFFFF || pointer == 0 ||
3793                     pointer >= hw->eeprom.word_size)
3794                         continue;
3795
3796                 switch (i) {
3797                 case IXGBE_PCIE_GENERAL_PTR:
3798                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3799                         break;
3800                 case IXGBE_PCIE_CONFIG0_PTR:
3801                 case IXGBE_PCIE_CONFIG1_PTR:
3802                         size = IXGBE_PCIE_CONFIG_SIZE;
3803                         break;
3804                 default:
3805                         size = 0;
3806                         break;
3807                 }
3808
3809                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3810                                                 buffer, buffer_size);
3811                 if (status)
3812                         return status;
3813         }
3814
3815         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3816
3817         return (s32)checksum;
3818 }
3819
3820 /**
3821  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3822  *  @hw: pointer to hardware structure
3823  *
3824  *  Returns a negative error code on error, or the 16-bit checksum
3825  **/
3826 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3827 {
3828         return ixgbe_calc_checksum_X550(hw, NULL, 0);
3829 }
3830
3831 /**
3832  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3833  *  @hw: pointer to hardware structure
3834  *  @checksum_val: calculated checksum
3835  *
3836  *  Performs checksum calculation and validates the EEPROM checksum.  If the
3837  *  caller does not need checksum_val, the value can be NULL.
3838  **/
3839 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3840 {
3841         s32 status;
3842         u16 checksum;
3843         u16 read_checksum = 0;
3844
3845         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3846
3847         /* Read the first word from the EEPROM. If this times out or fails, do
3848          * not continue or we could be in for a very long wait while every
3849          * EEPROM read fails
3850          */
3851         status = hw->eeprom.ops.read(hw, 0, &checksum);
3852         if (status) {
3853                 DEBUGOUT("EEPROM read failed\n");
3854                 return status;
3855         }
3856
3857         status = hw->eeprom.ops.calc_checksum(hw);
3858         if (status < 0)
3859                 return status;
3860
3861         checksum = (u16)(status & 0xffff);
3862
3863         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3864                                            &read_checksum);
3865         if (status)
3866                 return status;
3867
3868         /* Verify read checksum from EEPROM is the same as
3869          * calculated checksum
3870          */
3871         if (read_checksum != checksum) {
3872                 status = IXGBE_ERR_EEPROM_CHECKSUM;
3873                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3874                              "Invalid EEPROM checksum");
3875         }
3876
3877         /* If the user cares, return the calculated checksum */
3878         if (checksum_val)
3879                 *checksum_val = checksum;
3880
3881         return status;
3882 }
3883
3884 /**
3885  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3886  * @hw: pointer to hardware structure
3887  *
3888  * After writing EEPROM to shadow RAM using EEWR register, software calculates
3889  * checksum and updates the EEPROM and instructs the hardware to update
3890  * the flash.
3891  **/
3892 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3893 {
3894         s32 status;
3895         u16 checksum = 0;
3896
3897         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3898
3899         /* Read the first word from the EEPROM. If this times out or fails, do
3900          * not continue or we could be in for a very long wait while every
3901          * EEPROM read fails
3902          */
3903         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3904         if (status) {
3905                 DEBUGOUT("EEPROM read failed\n");
3906                 return status;
3907         }
3908
3909         status = ixgbe_calc_eeprom_checksum_X550(hw);
3910         if (status < 0)
3911                 return status;
3912
3913         checksum = (u16)(status & 0xffff);
3914
3915         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3916                                             checksum);
3917         if (status)
3918                 return status;
3919
3920         status = ixgbe_update_flash_X550(hw);
3921
3922         return status;
3923 }
3924
3925 /**
3926  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3927  *  @hw: pointer to hardware structure
3928  *
3929  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3930  **/
3931 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3932 {
3933         s32 status = IXGBE_SUCCESS;
3934         union ixgbe_hic_hdr2 buffer;
3935
3936         DEBUGFUNC("ixgbe_update_flash_X550");
3937
3938         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3939         buffer.req.buf_lenh = 0;
3940         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3941         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3942
3943         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3944                                               sizeof(buffer),
3945                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3946
3947         return status;
3948 }
3949
3950 /**
3951  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3952  *  @hw: pointer to hardware structure
3953  *
3954  *  Determines physical layer capabilities of the current configuration.
3955  **/
3956 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3957 {
3958         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3959         u16 ext_ability = 0;
3960
3961         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3962
3963         hw->phy.ops.identify(hw);
3964
3965         switch (hw->phy.type) {
3966         case ixgbe_phy_x550em_kr:
3967                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3968                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3969                 break;
3970         case ixgbe_phy_x550em_kx4:
3971                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3972                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3973                 break;
3974         case ixgbe_phy_x550em_ext_t:
3975                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3976                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3977                                      &ext_ability);
3978                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3979                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3980                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3981                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3982                 break;
3983         case ixgbe_phy_m88:
3984                 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
3985         default:
3986                 break;
3987         }
3988
3989         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3990                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3991
3992         return physical_layer;
3993 }
3994
3995 /**
3996  * ixgbe_get_bus_info_x550em - Set PCI bus info
3997  * @hw: pointer to hardware structure
3998  *
3999  * Sets bus link width and speed to unknown because X550em is
4000  * not a PCI device.
4001  **/
4002 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
4003 {
4004
4005         DEBUGFUNC("ixgbe_get_bus_info_x550em");
4006
4007         hw->bus.width = ixgbe_bus_width_unknown;
4008         hw->bus.speed = ixgbe_bus_speed_unknown;
4009
4010         hw->mac.ops.set_lan_id(hw);
4011
4012         return IXGBE_SUCCESS;
4013 }
4014
4015 /**
4016  * ixgbe_disable_rx_x550 - Disable RX unit
4017  *
4018  * Enables the Rx DMA unit for x550
4019  **/
4020 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
4021 {
4022         u32 rxctrl, pfdtxgswc;
4023         s32 status;
4024         struct ixgbe_hic_disable_rxen fw_cmd;
4025
4026         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
4027
4028         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4029         if (rxctrl & IXGBE_RXCTRL_RXEN) {
4030                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4031                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
4032                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4033                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4034                         hw->mac.set_lben = true;
4035                 } else {
4036                         hw->mac.set_lben = false;
4037                 }
4038
4039                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
4040                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
4041                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
4042                 fw_cmd.port_number = (u8)hw->bus.lan_id;
4043
4044                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4045                                         sizeof(struct ixgbe_hic_disable_rxen),
4046                                         IXGBE_HI_COMMAND_TIMEOUT, true);
4047
4048                 /* If we fail - disable RX using register write */
4049                 if (status) {
4050                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4051                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
4052                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
4053                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
4054                         }
4055                 }
4056         }
4057 }
4058
4059 /**
4060  * ixgbe_enter_lplu_x550em - Transition to low power states
4061  *  @hw: pointer to hardware structure
4062  *
4063  * Configures Low Power Link Up on transition to low power states
4064  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
4065  * X557 PHY immediately prior to entering LPLU.
4066  **/
4067 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
4068 {
4069         u16 an_10g_cntl_reg, autoneg_reg, speed;
4070         s32 status;
4071         ixgbe_link_speed lcd_speed;
4072         u32 save_autoneg;
4073         bool link_up;
4074
4075         /* SW LPLU not required on later HW revisions. */
4076         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
4077             (IXGBE_FUSES0_REV_MASK &
4078              IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
4079                 return IXGBE_SUCCESS;
4080
4081         /* If blocked by MNG FW, then don't restart AN */
4082         if (ixgbe_check_reset_blocked(hw))
4083                 return IXGBE_SUCCESS;
4084
4085         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
4086         if (status != IXGBE_SUCCESS)
4087                 return status;
4088
4089         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
4090
4091         if (status != IXGBE_SUCCESS)
4092                 return status;
4093
4094         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
4095          * disabled, then force link down by entering low power mode.
4096          */
4097         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
4098             !(hw->wol_enabled || ixgbe_mng_present(hw)))
4099                 return ixgbe_set_copper_phy_power(hw, FALSE);
4100
4101         /* Determine LCD */
4102         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
4103
4104         if (status != IXGBE_SUCCESS)
4105                 return status;
4106
4107         /* If no valid LCD link speed, then force link down and exit. */
4108         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
4109                 return ixgbe_set_copper_phy_power(hw, FALSE);
4110
4111         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
4112                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4113                                       &speed);
4114
4115         if (status != IXGBE_SUCCESS)
4116                 return status;
4117
4118         /* If no link now, speed is invalid so take link down */
4119         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
4120         if (status != IXGBE_SUCCESS)
4121                 return ixgbe_set_copper_phy_power(hw, false);
4122
4123         /* clear everything but the speed bits */
4124         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
4125
4126         /* If current speed is already LCD, then exit. */
4127         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
4128              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
4129             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
4130              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
4131                 return status;
4132
4133         /* Clear AN completed indication */
4134         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
4135                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4136                                       &autoneg_reg);
4137
4138         if (status != IXGBE_SUCCESS)
4139                 return status;
4140
4141         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
4142                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4143                              &an_10g_cntl_reg);
4144
4145         if (status != IXGBE_SUCCESS)
4146                 return status;
4147
4148         status = hw->phy.ops.read_reg(hw,
4149                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
4150                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4151                              &autoneg_reg);
4152
4153         if (status != IXGBE_SUCCESS)
4154                 return status;
4155
4156         save_autoneg = hw->phy.autoneg_advertised;
4157
4158         /* Setup link at least common link speed */
4159         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
4160
4161         /* restore autoneg from before setting lplu speed */
4162         hw->phy.autoneg_advertised = save_autoneg;
4163
4164         return status;
4165 }
4166
4167 /**
4168  * ixgbe_get_lcd_x550em - Determine lowest common denominator
4169  *  @hw: pointer to hardware structure
4170  *  @lcd_speed: pointer to lowest common link speed
4171  *
4172  * Determine lowest common link speed with link partner.
4173  **/
4174 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
4175 {
4176         u16 an_lp_status;
4177         s32 status;
4178         u16 word = hw->eeprom.ctrl_word_3;
4179
4180         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
4181
4182         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
4183                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4184                                       &an_lp_status);
4185
4186         if (status != IXGBE_SUCCESS)
4187                 return status;
4188
4189         /* If link partner advertised 1G, return 1G */
4190         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
4191                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
4192                 return status;
4193         }
4194
4195         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
4196         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
4197             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
4198                 return status;
4199
4200         /* Link partner not capable of lower speeds, return 10G */
4201         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
4202         return status;
4203 }
4204
4205 /**
4206  *  ixgbe_setup_fc_X550em - Set up flow control
4207  *  @hw: pointer to hardware structure
4208  *
4209  *  Called at init time to set up flow control.
4210  **/
4211 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
4212 {
4213         s32 ret_val = IXGBE_SUCCESS;
4214         u32 pause, asm_dir, reg_val;
4215
4216         DEBUGFUNC("ixgbe_setup_fc_X550em");
4217
4218         /* Validate the requested mode */
4219         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4220                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4221                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4222                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4223                 goto out;
4224         }
4225
4226         /* 10gig parts do not have a word in the EEPROM to determine the
4227          * default flow control setting, so we explicitly set it to full.
4228          */
4229         if (hw->fc.requested_mode == ixgbe_fc_default)
4230                 hw->fc.requested_mode = ixgbe_fc_full;
4231
4232         /* Determine PAUSE and ASM_DIR bits. */
4233         switch (hw->fc.requested_mode) {
4234         case ixgbe_fc_none:
4235                 pause = 0;
4236                 asm_dir = 0;
4237                 break;
4238         case ixgbe_fc_tx_pause:
4239                 pause = 0;
4240                 asm_dir = 1;
4241                 break;
4242         case ixgbe_fc_rx_pause:
4243                 /* Rx Flow control is enabled and Tx Flow control is
4244                  * disabled by software override. Since there really
4245                  * isn't a way to advertise that we are capable of RX
4246                  * Pause ONLY, we will advertise that we support both
4247                  * symmetric and asymmetric Rx PAUSE, as such we fall
4248                  * through to the fc_full statement.  Later, we will
4249                  * disable the adapter's ability to send PAUSE frames.
4250                  */
4251         case ixgbe_fc_full:
4252                 pause = 1;
4253                 asm_dir = 1;
4254                 break;
4255         default:
4256                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4257                         "Flow control param set incorrectly\n");
4258                 ret_val = IXGBE_ERR_CONFIG;
4259                 goto out;
4260         }
4261
4262         switch (hw->device_id) {
4263         case IXGBE_DEV_ID_X550EM_X_KR:
4264         case IXGBE_DEV_ID_X550EM_A_KR:
4265         case IXGBE_DEV_ID_X550EM_A_KR_L:
4266                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
4267                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4268                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
4269                 if (ret_val != IXGBE_SUCCESS)
4270                         goto out;
4271                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4272                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4273                 if (pause)
4274                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4275                 if (asm_dir)
4276                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4277                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
4278                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4279                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
4280
4281                 /* This device does not fully support AN. */
4282                 hw->fc.disable_fc_autoneg = true;
4283                 break;
4284         default:
4285                 break;
4286         }
4287
4288 out:
4289         return ret_val;
4290 }
4291
4292 /**
4293  *  ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
4294  *  @hw: pointer to hardware structure
4295  *
4296  *  Enable flow control according to IEEE clause 37.
4297  **/
4298 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
4299 {
4300         u32 link_s1, lp_an_page_low, an_cntl_1;
4301         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4302         ixgbe_link_speed speed;
4303         bool link_up;
4304
4305         /* AN should have completed when the cable was plugged in.
4306          * Look for reasons to bail out.  Bail out if:
4307          * - FC autoneg is disabled, or if
4308          * - link is not up.
4309          */
4310         if (hw->fc.disable_fc_autoneg) {
4311                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4312                              "Flow control autoneg is disabled");
4313                 goto out;
4314         }
4315
4316         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4317         if (!link_up) {
4318                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4319                 goto out;
4320         }
4321
4322         /* Check at auto-negotiation has completed */
4323         status = hw->mac.ops.read_iosf_sb_reg(hw,
4324                                         IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4325                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4326
4327         if (status != IXGBE_SUCCESS ||
4328             (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4329                 DEBUGOUT("Auto-Negotiation did not complete\n");
4330                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4331                 goto out;
4332         }
4333
4334         /* Read the 10g AN autoc and LP ability registers and resolve
4335          * local flow control settings accordingly
4336          */
4337         status = hw->mac.ops.read_iosf_sb_reg(hw,
4338                                 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4339                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
4340
4341         if (status != IXGBE_SUCCESS) {
4342                 DEBUGOUT("Auto-Negotiation did not complete\n");
4343                 goto out;
4344         }
4345
4346         status = hw->mac.ops.read_iosf_sb_reg(hw,
4347                                 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
4348                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
4349
4350         if (status != IXGBE_SUCCESS) {
4351                 DEBUGOUT("Auto-Negotiation did not complete\n");
4352                 goto out;
4353         }
4354
4355         status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
4356                                     IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
4357                                     IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
4358                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
4359                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
4360
4361 out:
4362         if (status == IXGBE_SUCCESS) {
4363                 hw->fc.fc_was_autonegged = true;
4364         } else {
4365                 hw->fc.fc_was_autonegged = false;
4366                 hw->fc.current_mode = hw->fc.requested_mode;
4367         }
4368 }
4369
4370 /**
4371  *  ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
4372  *  @hw: pointer to hardware structure
4373  *
4374  **/
4375 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
4376 {
4377         hw->fc.fc_was_autonegged = false;
4378         hw->fc.current_mode = hw->fc.requested_mode;
4379 }
4380
4381 /**
4382  *  ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
4383  *  @hw: pointer to hardware structure
4384  *
4385  *  Enable flow control according to IEEE clause 37.
4386  **/
4387 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
4388 {
4389         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4390         u16 reg, pcs_an_lp, pcs_an;
4391         ixgbe_link_speed speed;
4392         bool link_up;
4393
4394         /* AN should have completed when the cable was plugged in.
4395          * Look for reasons to bail out.  Bail out if:
4396          * - FC autoneg is disabled, or if
4397          * - link is not up.
4398          */
4399         if (hw->fc.disable_fc_autoneg) {
4400                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4401                              "Flow control autoneg is disabled");
4402                 goto out;
4403         }
4404
4405         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4406         if (!link_up) {
4407                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4408                 goto out;
4409         }
4410
4411         /* Check if auto-negotiation has completed */
4412         status = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_STATUS,
4413                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg);
4414         if (status != IXGBE_SUCCESS ||
4415             (reg & IXGBE_M88E1500_COPPER_STATUS_AN_DONE) == 0) {
4416                 DEBUGOUT("Auto-Negotiation did not complete\n");
4417                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4418                 goto out;
4419         }
4420
4421         /* Get the advertized flow control */
4422         status = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_AN,
4423                                         IXGBE_MDIO_ZERO_DEV_TYPE, &pcs_an);
4424         if (status != IXGBE_SUCCESS)
4425                 goto out;
4426
4427         /* Get link partner's flow control */
4428         status = hw->phy.ops.read_reg(hw,
4429                         IXGBE_M88E1500_COPPER_AN_LP_ABILITY,
4430                                         IXGBE_MDIO_ZERO_DEV_TYPE, &pcs_an_lp);
4431         if (status != IXGBE_SUCCESS)
4432                 goto out;
4433
4434         /* Negotiate the flow control */
4435         status = ixgbe_negotiate_fc(hw, (u32)pcs_an, (u32)pcs_an_lp,
4436                                     IXGBE_M88E1500_COPPER_AN_PAUSE,
4437                                     IXGBE_M88E1500_COPPER_AN_AS_PAUSE,
4438                                     IXGBE_M88E1500_COPPER_AN_LP_PAUSE,
4439                                     IXGBE_M88E1500_COPPER_AN_LP_AS_PAUSE);
4440
4441 out:
4442         if (status == IXGBE_SUCCESS) {
4443                 hw->fc.fc_was_autonegged = true;
4444         } else {
4445                 hw->fc.fc_was_autonegged = false;
4446                 hw->fc.current_mode = hw->fc.requested_mode;
4447         }
4448 }
4449
4450 /**
4451  *  ixgbe_setup_fc_sgmii_x550em_a - Set up flow control
4452  *  @hw: pointer to hardware structure
4453  *
4454  *  Called at init time to set up flow control.
4455  **/
4456 s32 ixgbe_setup_fc_sgmii_x550em_a(struct ixgbe_hw *hw)
4457 {
4458         u16 reg;
4459         s32 rc;
4460
4461         /* Validate the requested mode */
4462         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4463                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4464                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4465                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4466         }
4467
4468         if (hw->fc.requested_mode == ixgbe_fc_default)
4469                 hw->fc.requested_mode = ixgbe_fc_full;
4470
4471         /* Read contents of the Auto-Negotiation register, page 0 reg 4 */
4472         rc = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_AN,
4473                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg);
4474         if (rc)
4475                 goto out;
4476
4477         /* Disable all the settings related to Flow control Auto-negotiation */
4478         reg &= ~IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4479         reg &= ~IXGBE_M88E1500_COPPER_AN_PAUSE;
4480
4481         /* Configure the Asymmetric and symmetric pause according to the user
4482          * requested mode.
4483          */
4484         switch (hw->fc.requested_mode) {
4485         case ixgbe_fc_full:
4486                 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
4487                 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4488                 break;
4489         case ixgbe_fc_rx_pause:
4490                 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
4491                 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4492                 break;
4493         case ixgbe_fc_tx_pause:
4494                 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4495                 break;
4496         default:
4497                 break;
4498         }
4499
4500         /* Write back to the Auto-Negotiation register with newly configured
4501          * fields
4502          */
4503         hw->phy.ops.write_reg(hw, IXGBE_M88E1500_COPPER_AN,
4504                                         IXGBE_MDIO_ZERO_DEV_TYPE, reg);
4505
4506         /* In this section of the code we restart Auto-negotiation */
4507
4508         /* Read the CONTROL register, Page 0 reg 0 */
4509         rc = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_CTRL,
4510                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg);
4511         if (rc)
4512                 goto out;
4513
4514         /* Set the bit to restart Auto-Neg. The bit to enable Auto-neg is ON
4515          * by default
4516          */
4517         reg |= IXGBE_M88E1500_COPPER_CTRL_RESTART_AN;
4518
4519         /* write the new values to the register to restart Auto-Negotiation */
4520         hw->phy.ops.write_reg(hw, IXGBE_M88E1500_COPPER_CTRL,
4521                                         IXGBE_MDIO_ZERO_DEV_TYPE, reg);
4522
4523 out:
4524         return rc;
4525 }
4526
4527 /**
4528  *  ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4529  *  @hw: pointer to hardware structure
4530  *
4531  *  Called at init time to set up flow control.
4532  **/
4533 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4534 {
4535         s32 status = IXGBE_SUCCESS;
4536         u32 an_cntl = 0;
4537
4538         DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4539
4540         /* Validate the requested mode */
4541         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4542                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4543                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4544                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4545         }
4546
4547         if (hw->fc.requested_mode == ixgbe_fc_default)
4548                 hw->fc.requested_mode = ixgbe_fc_full;
4549
4550         /* Set up the 1G and 10G flow control advertisement registers so the
4551          * HW will be able to do FC autoneg once the cable is plugged in.  If
4552          * we link at 10G, the 1G advertisement is harmless and vice versa.
4553          */
4554         status = hw->mac.ops.read_iosf_sb_reg(hw,
4555                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4556                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4557
4558         if (status != IXGBE_SUCCESS) {
4559                 DEBUGOUT("Auto-Negotiation did not complete\n");
4560                 return status;
4561         }
4562
4563         /* The possible values of fc.requested_mode are:
4564          * 0: Flow control is completely disabled
4565          * 1: Rx flow control is enabled (we can receive pause frames,
4566          *    but not send pause frames).
4567          * 2: Tx flow control is enabled (we can send pause frames but
4568          *    we do not support receiving pause frames).
4569          * 3: Both Rx and Tx flow control (symmetric) are enabled.
4570          * other: Invalid.
4571          */
4572         switch (hw->fc.requested_mode) {
4573         case ixgbe_fc_none:
4574                 /* Flow control completely disabled by software override. */
4575                 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4576                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4577                 break;
4578         case ixgbe_fc_tx_pause:
4579                 /* Tx Flow control is enabled, and Rx Flow control is
4580                  * disabled by software override.
4581                  */
4582                 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4583                 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4584                 break;
4585         case ixgbe_fc_rx_pause:
4586                 /* Rx Flow control is enabled and Tx Flow control is
4587                  * disabled by software override. Since there really
4588                  * isn't a way to advertise that we are capable of RX
4589                  * Pause ONLY, we will advertise that we support both
4590                  * symmetric and asymmetric Rx PAUSE, as such we fall
4591                  * through to the fc_full statement.  Later, we will
4592                  * disable the adapter's ability to send PAUSE frames.
4593                  */
4594         case ixgbe_fc_full:
4595                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4596                 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4597                            IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4598                 break;
4599         default:
4600                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4601                               "Flow control param set incorrectly\n");
4602                 return IXGBE_ERR_CONFIG;
4603         }
4604
4605         status = hw->mac.ops.write_iosf_sb_reg(hw,
4606                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4607                                         IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4608
4609         /* Restart auto-negotiation. */
4610         status = ixgbe_restart_an_internal_phy_x550em(hw);
4611
4612         return status;
4613 }
4614
4615 /**
4616  * ixgbe_set_mux - Set mux for port 1 access with CS4227
4617  * @hw: pointer to hardware structure
4618  * @state: set mux if 1, clear if 0
4619  */
4620 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4621 {
4622         u32 esdp;
4623
4624         if (!hw->bus.lan_id)
4625                 return;
4626         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4627         if (state)
4628                 esdp |= IXGBE_ESDP_SDP1;
4629         else
4630                 esdp &= ~IXGBE_ESDP_SDP1;
4631         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4632         IXGBE_WRITE_FLUSH(hw);
4633 }
4634
4635 /**
4636  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4637  *  @hw: pointer to hardware structure
4638  *  @mask: Mask to specify which semaphore to acquire
4639  *
4640  *  Acquires the SWFW semaphore and sets the I2C MUX
4641  **/
4642 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4643 {
4644         s32 status;
4645
4646         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4647
4648         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4649         if (status)
4650                 return status;
4651
4652         if (mask & IXGBE_GSSR_I2C_MASK)
4653                 ixgbe_set_mux(hw, 1);
4654
4655         return IXGBE_SUCCESS;
4656 }
4657
4658 /**
4659  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4660  *  @hw: pointer to hardware structure
4661  *  @mask: Mask to specify which semaphore to release
4662  *
4663  *  Releases the SWFW semaphore and sets the I2C MUX
4664  **/
4665 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4666 {
4667         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4668
4669         if (mask & IXGBE_GSSR_I2C_MASK)
4670                 ixgbe_set_mux(hw, 0);
4671
4672         ixgbe_release_swfw_sync_X540(hw, mask);
4673 }
4674
4675 /**
4676  *  ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4677  *  @hw: pointer to hardware structure
4678  *  @mask: Mask to specify which semaphore to acquire
4679  *
4680  *  Acquires the SWFW semaphore and get the shared phy token as needed
4681  */
4682 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4683 {
4684         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4685         int retries = FW_PHY_TOKEN_RETRIES;
4686         s32 status = IXGBE_SUCCESS;
4687
4688         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4689
4690         while (--retries) {
4691                 status = IXGBE_SUCCESS;
4692                 if (hmask)
4693                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4694                 if (status)
4695                         return status;
4696                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4697                         return IXGBE_SUCCESS;
4698
4699                 status = ixgbe_get_phy_token(hw);
4700                 if (status == IXGBE_SUCCESS)
4701                         return IXGBE_SUCCESS;
4702
4703                 if (hmask)
4704                         ixgbe_release_swfw_sync_X540(hw, hmask);
4705                 if (status != IXGBE_ERR_TOKEN_RETRY)
4706                         return status;
4707         }
4708
4709         return status;
4710 }
4711
4712 /**
4713  *  ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4714  *  @hw: pointer to hardware structure
4715  *  @mask: Mask to specify which semaphore to release
4716  *
4717  *  Releases the SWFW semaphore and puts the shared phy token as needed
4718  */
4719 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4720 {
4721         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4722
4723         DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4724
4725         if (mask & IXGBE_GSSR_TOKEN_SM)
4726                 ixgbe_put_phy_token(hw);
4727
4728         if (hmask)
4729                 ixgbe_release_swfw_sync_X540(hw, hmask);
4730 }
4731
4732 /**
4733  *  ixgbe_read_phy_reg_x550a  - Reads specified PHY register
4734  *  @hw: pointer to hardware structure
4735  *  @reg_addr: 32 bit address of PHY register to read
4736  *  @phy_data: Pointer to read data from PHY register
4737  *
4738  *  Reads a value from a specified PHY register using the SWFW lock and PHY
4739  *  Token. The PHY Token is needed since the MDIO is shared between to MAC
4740  *  instances.
4741  **/
4742 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4743                                u32 device_type, u16 *phy_data)
4744 {
4745         s32 status;
4746         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4747
4748         DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4749
4750         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4751                 return IXGBE_ERR_SWFW_SYNC;
4752
4753         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4754
4755         hw->mac.ops.release_swfw_sync(hw, mask);
4756
4757         return status;
4758 }
4759
4760 /**
4761  *  ixgbe_write_phy_reg_x550a - Writes specified PHY register
4762  *  @hw: pointer to hardware structure
4763  *  @reg_addr: 32 bit PHY register to write
4764  *  @device_type: 5 bit device type
4765  *  @phy_data: Data to write to the PHY register
4766  *
4767  *  Writes a value to specified PHY register using the SWFW lock and PHY Token.
4768  *  The PHY Token is needed since the MDIO is shared between to MAC instances.
4769  **/
4770 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4771                                 u32 device_type, u16 phy_data)
4772 {
4773         s32 status;
4774         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4775
4776         DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4777
4778         if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4779                 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
4780                                                  phy_data);
4781                 hw->mac.ops.release_swfw_sync(hw, mask);
4782         } else {
4783                 status = IXGBE_ERR_SWFW_SYNC;
4784         }
4785
4786         return status;
4787 }
4788
4789 /**
4790  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4791  * @hw: pointer to hardware structure
4792  *
4793  * Handle external Base T PHY interrupt. If high temperature
4794  * failure alarm then return error, else if link status change
4795  * then setup internal/external PHY link
4796  *
4797  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4798  * failure alarm, else return PHY access status.
4799  */
4800 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4801 {
4802         bool lsc;
4803         u32 status;
4804
4805         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4806
4807         if (status != IXGBE_SUCCESS)
4808                 return status;
4809
4810         if (lsc)
4811                 return ixgbe_setup_internal_phy(hw);
4812
4813         return IXGBE_SUCCESS;
4814 }
4815
4816 /**
4817  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4818  * @hw: pointer to hardware structure
4819  * @speed: new link speed
4820  * @autoneg_wait_to_complete: true when waiting for completion is needed
4821  *
4822  * Setup internal/external PHY link speed based on link speed, then set
4823  * external PHY auto advertised link speed.
4824  *
4825  * Returns error status for any failure
4826  **/
4827 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4828                                   ixgbe_link_speed speed,
4829                                   bool autoneg_wait_to_complete)
4830 {
4831         s32 status;
4832         ixgbe_link_speed force_speed;
4833
4834         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4835
4836         /* Setup internal/external PHY link speed to iXFI (10G), unless
4837          * only 1G is auto advertised then setup KX link.
4838          */
4839         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4840                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4841         else
4842                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4843
4844         /* If X552 and internal link mode is XFI, then setup XFI internal link.
4845          */
4846         if (hw->mac.type == ixgbe_mac_X550EM_x &&
4847             !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4848                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4849
4850                 if (status != IXGBE_SUCCESS)
4851                         return status;
4852         }
4853
4854         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4855 }
4856
4857 /**
4858  * ixgbe_check_link_t_X550em - Determine link and speed status
4859  * @hw: pointer to hardware structure
4860  * @speed: pointer to link speed
4861  * @link_up: true when link is up
4862  * @link_up_wait_to_complete: bool used to wait for link up or not
4863  *
4864  * Check that both the MAC and X557 external PHY have link.
4865  **/
4866 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4867                               bool *link_up, bool link_up_wait_to_complete)
4868 {
4869         u32 status;
4870         u16 i, autoneg_status = 0;
4871
4872         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4873                 return IXGBE_ERR_CONFIG;
4874
4875         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4876                                               link_up_wait_to_complete);
4877
4878         /* If check link fails or MAC link is not up, then return */
4879         if (status != IXGBE_SUCCESS || !(*link_up))
4880                 return status;
4881
4882         /* MAC link is up, so check external PHY link.
4883          * X557 PHY. Link status is latching low, and can only be used to detect
4884          * link drop, and not the current status of the link without performing
4885          * back-to-back reads.
4886          */
4887         for (i = 0; i < 2; i++) {
4888                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4889                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4890                                               &autoneg_status);
4891
4892                 if (status != IXGBE_SUCCESS)
4893                         return status;
4894         }
4895
4896         /* If external PHY link is not up, then indicate link not up */
4897         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4898                 *link_up = false;
4899
4900         return IXGBE_SUCCESS;
4901 }
4902
4903 /**
4904  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4905  *  @hw: pointer to hardware structure
4906  **/
4907 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4908 {
4909         s32 status;
4910
4911         status = ixgbe_reset_phy_generic(hw);
4912
4913         if (status != IXGBE_SUCCESS)
4914                 return status;
4915
4916         /* Configure Link Status Alarm and Temperature Threshold interrupts */
4917         return ixgbe_enable_lasi_ext_t_x550em(hw);
4918 }
4919
4920 /**
4921  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4922  *  @hw: pointer to hardware structure
4923  *  @led_idx: led number to turn on
4924  **/
4925 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4926 {
4927         u16 phy_data;
4928
4929         DEBUGFUNC("ixgbe_led_on_t_X550em");
4930
4931         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4932                 return IXGBE_ERR_PARAM;
4933
4934         /* To turn on the LED, set mode to ON. */
4935         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4936                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4937         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4938         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4939                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4940
4941         return IXGBE_SUCCESS;
4942 }
4943
4944 /**
4945  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4946  *  @hw: pointer to hardware structure
4947  *  @led_idx: led number to turn off
4948  **/
4949 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4950 {
4951         u16 phy_data;
4952
4953         DEBUGFUNC("ixgbe_led_off_t_X550em");
4954
4955         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4956                 return IXGBE_ERR_PARAM;
4957
4958         /* To turn on the LED, set mode to ON. */
4959         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4960                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4961         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4962         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4963                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4964
4965         return IXGBE_SUCCESS;
4966 }
4967
4968 /**
4969  *  ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware
4970  *  @hw: pointer to the HW structure
4971  *  @maj: driver version major number
4972  *  @min: driver version minor number
4973  *  @build: driver version build number
4974  *  @sub: driver version sub build number
4975  *  @len: length of driver_ver string
4976  *  @driver_ver: driver string
4977  *
4978  *  Sends driver version number to firmware through the manageability
4979  *  block.  On success return IXGBE_SUCCESS
4980  *  else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4981  *  semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4982  **/
4983 s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,
4984                               u8 build, u8 sub, u16 len, const char *driver_ver)
4985 {
4986         struct ixgbe_hic_drv_info2 fw_cmd;
4987         s32 ret_val = IXGBE_SUCCESS;
4988         int i;
4989
4990         DEBUGFUNC("ixgbe_set_fw_drv_ver_x550");
4991
4992         if ((len == 0) || (driver_ver == NULL) ||
4993            (len > sizeof(fw_cmd.driver_string)))
4994                 return IXGBE_ERR_INVALID_ARGUMENT;
4995
4996         fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4997         fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len;
4998         fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4999         fw_cmd.port_num = (u8)hw->bus.func;
5000         fw_cmd.ver_maj = maj;
5001         fw_cmd.ver_min = min;
5002         fw_cmd.ver_build = build;
5003         fw_cmd.ver_sub = sub;
5004         fw_cmd.hdr.checksum = 0;
5005         memcpy(fw_cmd.driver_string, driver_ver, len);
5006         fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
5007                                 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
5008
5009         for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
5010                 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
5011                                                        sizeof(fw_cmd),
5012                                                        IXGBE_HI_COMMAND_TIMEOUT,
5013                                                        true);
5014                 if (ret_val != IXGBE_SUCCESS)
5015                         continue;
5016
5017                 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
5018                     FW_CEM_RESP_STATUS_SUCCESS)
5019                         ret_val = IXGBE_SUCCESS;
5020                 else
5021                         ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
5022
5023                 break;
5024         }
5025
5026         return ret_val;
5027 }