1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
42 static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
43 static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
46 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
47 * @hw: pointer to hardware structure
49 * Initialize the function pointers and assign the MAC type for X550.
50 * Does not touch the hardware.
52 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
54 struct ixgbe_mac_info *mac = &hw->mac;
55 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
58 DEBUGFUNC("ixgbe_init_ops_X550");
60 ret_val = ixgbe_init_ops_X540(hw);
61 mac->ops.dmac_config = ixgbe_dmac_config_X550;
62 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
63 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
64 mac->ops.setup_eee = ixgbe_setup_eee_X550;
65 mac->ops.set_source_address_pruning =
66 ixgbe_set_source_address_pruning_X550;
67 mac->ops.set_ethertype_anti_spoofing =
68 ixgbe_set_ethertype_anti_spoofing_X550;
70 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
71 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
72 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
73 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
74 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
75 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
76 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
77 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
78 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
80 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
81 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
82 mac->ops.mdd_event = ixgbe_mdd_event_X550;
83 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
84 mac->ops.disable_rx = ixgbe_disable_rx_x550;
85 switch (hw->device_id) {
86 case IXGBE_DEV_ID_X550EM_X_10G_T:
87 case IXGBE_DEV_ID_X550EM_A_10G_T:
88 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
89 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
98 * ixgbe_read_cs4227 - Read CS4227 register
99 * @hw: pointer to hardware structure
100 * @reg: register number to write
101 * @value: pointer to receive value read
103 * Returns status code
105 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
107 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
111 * ixgbe_write_cs4227 - Write CS4227 register
112 * @hw: pointer to hardware structure
113 * @reg: register number to write
114 * @value: value to write to register
116 * Returns status code
118 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
120 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
124 * ixgbe_read_pe - Read register from port expander
125 * @hw: pointer to hardware structure
126 * @reg: register number to read
127 * @value: pointer to receive read value
129 * Returns status code
131 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
135 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
136 if (status != IXGBE_SUCCESS)
137 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
138 "port expander access failed with %d\n", status);
143 * ixgbe_write_pe - Write register to port expander
144 * @hw: pointer to hardware structure
145 * @reg: register number to write
146 * @value: value to write
148 * Returns status code
150 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
154 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
155 if (status != IXGBE_SUCCESS)
156 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
157 "port expander access failed with %d\n", status);
162 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
163 * @hw: pointer to hardware structure
165 * This function assumes that the caller has acquired the proper semaphore.
168 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
175 /* Trigger hard reset. */
176 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
177 if (status != IXGBE_SUCCESS)
179 reg |= IXGBE_PE_BIT1;
180 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
181 if (status != IXGBE_SUCCESS)
184 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
185 if (status != IXGBE_SUCCESS)
187 reg &= ~IXGBE_PE_BIT1;
188 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
189 if (status != IXGBE_SUCCESS)
192 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
193 if (status != IXGBE_SUCCESS)
195 reg &= ~IXGBE_PE_BIT1;
196 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
197 if (status != IXGBE_SUCCESS)
200 usec_delay(IXGBE_CS4227_RESET_HOLD);
202 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
203 if (status != IXGBE_SUCCESS)
205 reg |= IXGBE_PE_BIT1;
206 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
207 if (status != IXGBE_SUCCESS)
210 /* Wait for the reset to complete. */
211 msec_delay(IXGBE_CS4227_RESET_DELAY);
212 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
213 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
215 if (status == IXGBE_SUCCESS &&
216 value == IXGBE_CS4227_EEPROM_LOAD_OK)
218 msec_delay(IXGBE_CS4227_CHECK_DELAY);
220 if (retry == IXGBE_CS4227_RETRIES) {
221 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
222 "CS4227 reset did not complete.");
223 return IXGBE_ERR_PHY;
226 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
227 if (status != IXGBE_SUCCESS ||
228 !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
229 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
230 "CS4227 EEPROM did not load successfully.");
231 return IXGBE_ERR_PHY;
234 return IXGBE_SUCCESS;
238 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
239 * @hw: pointer to hardware structure
241 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
243 s32 status = IXGBE_SUCCESS;
244 u32 swfw_mask = hw->phy.phy_semaphore_mask;
248 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
249 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
250 if (status != IXGBE_SUCCESS) {
251 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
252 "semaphore failed with %d", status);
253 msec_delay(IXGBE_CS4227_CHECK_DELAY);
257 /* Get status of reset flow. */
258 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
260 if (status == IXGBE_SUCCESS &&
261 value == IXGBE_CS4227_RESET_COMPLETE)
264 if (status != IXGBE_SUCCESS ||
265 value != IXGBE_CS4227_RESET_PENDING)
268 /* Reset is pending. Wait and check again. */
269 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
270 msec_delay(IXGBE_CS4227_CHECK_DELAY);
273 /* If still pending, assume other instance failed. */
274 if (retry == IXGBE_CS4227_RETRIES) {
275 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
276 if (status != IXGBE_SUCCESS) {
277 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
278 "semaphore failed with %d", status);
283 /* Reset the CS4227. */
284 status = ixgbe_reset_cs4227(hw);
285 if (status != IXGBE_SUCCESS) {
286 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
287 "CS4227 reset failed: %d", status);
291 /* Reset takes so long, temporarily release semaphore in case the
292 * other driver instance is waiting for the reset indication.
294 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
295 IXGBE_CS4227_RESET_PENDING);
296 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
298 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
299 if (status != IXGBE_SUCCESS) {
300 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
301 "semaphore failed with %d", status);
305 /* Record completion for next time. */
306 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
307 IXGBE_CS4227_RESET_COMPLETE);
310 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
311 msec_delay(hw->eeprom.semaphore_delay);
315 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
316 * @hw: pointer to hardware structure
318 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
320 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
322 if (hw->bus.lan_id) {
323 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
324 esdp |= IXGBE_ESDP_SDP1_DIR;
326 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
327 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
328 IXGBE_WRITE_FLUSH(hw);
332 * ixgbe_identify_phy_1g - Get 1g PHY type based on device id
333 * @hw: pointer to hardware structure
337 static s32 ixgbe_identify_phy_1g(struct ixgbe_hw *hw)
341 u32 val = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
343 hw->phy.addr = (val >> 3) & 0x1F;
344 val = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
345 hw->phy.addr, &phy_id_high);
346 if (val || phy_id_high == 0xFFFF) {
347 hw->phy.type = ixgbe_phy_sgmii;
351 val = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
352 hw->phy.addr, &phy_id_low);
356 hw->phy.id = (u32)phy_id_high << 16;
357 hw->phy.id |= phy_id_low & IXGBE_PHY_REVISION_MASK;
358 hw->phy.revision = (u32)phy_id_low & ~IXGBE_PHY_REVISION_MASK;
359 hw->phy.type = ixgbe_phy_m88;
365 * ixgbe_identify_phy_x550em - Get PHY type based on device id
366 * @hw: pointer to hardware structure
370 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
372 switch (hw->device_id) {
373 case IXGBE_DEV_ID_X550EM_A_SFP:
374 hw->phy.phy_semaphore_mask = IXGBE_GSSR_TOKEN_SM;
376 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
378 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
379 return ixgbe_identify_module_generic(hw);
380 case IXGBE_DEV_ID_X550EM_X_SFP:
381 /* set up for CS4227 usage */
382 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
383 ixgbe_setup_mux_ctl(hw);
384 ixgbe_check_cs4227(hw);
387 case IXGBE_DEV_ID_X550EM_A_SFP_N:
388 return ixgbe_identify_module_generic(hw);
390 case IXGBE_DEV_ID_X550EM_X_KX4:
391 hw->phy.type = ixgbe_phy_x550em_kx4;
393 case IXGBE_DEV_ID_X550EM_X_KR:
394 case IXGBE_DEV_ID_X550EM_A_KR:
395 case IXGBE_DEV_ID_X550EM_A_KR_L:
396 hw->phy.type = ixgbe_phy_x550em_kr;
398 case IXGBE_DEV_ID_X550EM_X_1G_T:
399 case IXGBE_DEV_ID_X550EM_X_10G_T:
400 case IXGBE_DEV_ID_X550EM_A_10G_T:
401 return ixgbe_identify_phy_generic(hw);
402 case IXGBE_DEV_ID_X550EM_A_1G_T:
403 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
404 return ixgbe_identify_phy_1g(hw);
408 return IXGBE_SUCCESS;
411 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
412 u32 device_type, u16 *phy_data)
414 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
415 return IXGBE_NOT_IMPLEMENTED;
418 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
419 u32 device_type, u16 phy_data)
421 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
422 return IXGBE_NOT_IMPLEMENTED;
426 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
427 * @hw: pointer to the hardware structure
428 * @addr: I2C bus address to read from
429 * @reg: I2C device register to read from
430 * @val: pointer to location to receive read value
432 * Returns an error code on error.
434 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
437 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
441 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
442 * @hw: pointer to the hardware structure
443 * @addr: I2C bus address to read from
444 * @reg: I2C device register to read from
445 * @val: pointer to location to receive read value
447 * Returns an error code on error.
450 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
453 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
457 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
458 * @hw: pointer to the hardware structure
459 * @addr: I2C bus address to write to
460 * @reg: I2C device register to write to
461 * @val: value to write
463 * Returns an error code on error.
465 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
466 u8 addr, u16 reg, u16 val)
468 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
472 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
473 * @hw: pointer to the hardware structure
474 * @addr: I2C bus address to write to
475 * @reg: I2C device register to write to
476 * @val: value to write
478 * Returns an error code on error.
481 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
482 u8 addr, u16 reg, u16 val)
484 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
488 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
489 * @hw: pointer to hardware structure
491 * Initialize the function pointers and for MAC type X550EM.
492 * Does not touch the hardware.
494 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
496 struct ixgbe_mac_info *mac = &hw->mac;
497 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
498 struct ixgbe_phy_info *phy = &hw->phy;
499 struct ixgbe_link_info *link = &hw->link;
502 DEBUGFUNC("ixgbe_init_ops_X550EM");
504 /* Similar to X550 so start there. */
505 ret_val = ixgbe_init_ops_X550(hw);
507 /* Since this function eventually calls
508 * ixgbe_init_ops_540 by design, we are setting
509 * the pointers to NULL explicitly here to overwrite
510 * the values being set in the x540 function.
512 /* Thermal sensor not supported in x550EM */
513 mac->ops.get_thermal_sensor_data = NULL;
514 mac->ops.init_thermal_sensor_thresh = NULL;
515 mac->thermal_sensor_enabled = false;
517 /* FCOE not supported in x550EM */
518 mac->ops.get_san_mac_addr = NULL;
519 mac->ops.set_san_mac_addr = NULL;
520 mac->ops.get_wwn_prefix = NULL;
521 mac->ops.get_fcoe_boot_status = NULL;
523 /* IPsec not supported in x550EM */
524 mac->ops.disable_sec_rx_path = NULL;
525 mac->ops.enable_sec_rx_path = NULL;
527 /* AUTOC register is not present in x550EM. */
528 mac->ops.prot_autoc_read = NULL;
529 mac->ops.prot_autoc_write = NULL;
531 /* X550EM bus type is internal*/
532 hw->bus.type = ixgbe_bus_type_internal;
533 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
535 if (hw->mac.type == ixgbe_mac_X550EM_x) {
536 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
537 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
538 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
539 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
540 link->ops.read_link = ixgbe_read_i2c_combined_generic;
541 link->ops.read_link_unlocked =
542 ixgbe_read_i2c_combined_generic_unlocked;
543 link->ops.write_link = ixgbe_write_i2c_combined_generic;
544 link->ops.write_link_unlocked =
545 ixgbe_write_i2c_combined_generic_unlocked;
546 link->addr = IXGBE_CS4227;
548 if (hw->mac.type == ixgbe_mac_X550EM_a) {
549 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
550 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
551 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
552 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
555 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
556 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
557 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
558 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
559 mac->ops.get_supported_physical_layer =
560 ixgbe_get_supported_physical_layer_X550em;
562 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
563 mac->ops.setup_fc = ixgbe_setup_fc_generic;
565 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
567 switch (hw->device_id) {
568 case IXGBE_DEV_ID_X550EM_X_KR:
569 case IXGBE_DEV_ID_X550EM_A_KR:
570 case IXGBE_DEV_ID_X550EM_A_KR_L:
573 mac->ops.setup_eee = NULL;
577 phy->ops.init = ixgbe_init_phy_ops_X550em;
578 phy->ops.identify = ixgbe_identify_phy_x550em;
579 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
580 phy->ops.set_phy_power = NULL;
584 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
585 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
586 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
587 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
588 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
589 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
590 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
591 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
597 * ixgbe_dmac_config_X550
598 * @hw: pointer to hardware structure
600 * Configure DMA coalescing. If enabling dmac, dmac is activated.
601 * When disabling dmac, dmac enable dmac bit is cleared.
603 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
605 u32 reg, high_pri_tc;
607 DEBUGFUNC("ixgbe_dmac_config_X550");
609 /* Disable DMA coalescing before configuring */
610 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
611 reg &= ~IXGBE_DMACR_DMAC_EN;
612 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
614 /* Disable DMA Coalescing if the watchdog timer is 0 */
615 if (!hw->mac.dmac_config.watchdog_timer)
618 ixgbe_dmac_config_tcs_X550(hw);
620 /* Configure DMA Coalescing Control Register */
621 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
623 /* Set the watchdog timer in units of 40.96 usec */
624 reg &= ~IXGBE_DMACR_DMACWT_MASK;
625 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
627 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
628 /* If fcoe is enabled, set high priority traffic class */
629 if (hw->mac.dmac_config.fcoe_en) {
630 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
631 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
632 IXGBE_DMACR_HIGH_PRI_TC_MASK);
634 reg |= IXGBE_DMACR_EN_MNG_IND;
636 /* Enable DMA coalescing after configuration */
637 reg |= IXGBE_DMACR_DMAC_EN;
638 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
641 return IXGBE_SUCCESS;
645 * ixgbe_dmac_config_tcs_X550
646 * @hw: pointer to hardware structure
648 * Configure DMA coalescing threshold per TC. The dmac enable bit must
649 * be cleared before configuring.
651 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
653 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
655 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
657 /* Configure DMA coalescing enabled */
658 switch (hw->mac.dmac_config.link_speed) {
659 case IXGBE_LINK_SPEED_100_FULL:
660 pb_headroom = IXGBE_DMACRXT_100M;
662 case IXGBE_LINK_SPEED_1GB_FULL:
663 pb_headroom = IXGBE_DMACRXT_1G;
666 pb_headroom = IXGBE_DMACRXT_10G;
670 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
671 IXGBE_MHADD_MFS_SHIFT) / 1024);
673 /* Set the per Rx packet buffer receive threshold */
674 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
675 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
676 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
678 if (tc < hw->mac.dmac_config.num_tcs) {
680 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
681 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
682 IXGBE_RXPBSIZE_SHIFT;
684 /* Calculate receive buffer threshold in kilobytes */
685 if (rx_pb_size > pb_headroom)
686 rx_pb_size = rx_pb_size - pb_headroom;
690 /* Minimum of MFS shall be set for DMCTH */
691 reg |= (rx_pb_size > maxframe_size_kb) ?
692 rx_pb_size : maxframe_size_kb;
694 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
696 return IXGBE_SUCCESS;
700 * ixgbe_dmac_update_tcs_X550
701 * @hw: pointer to hardware structure
703 * Disables dmac, updates per TC settings, and then enables dmac.
705 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
709 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
711 /* Disable DMA coalescing before configuring */
712 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
713 reg &= ~IXGBE_DMACR_DMAC_EN;
714 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
716 ixgbe_dmac_config_tcs_X550(hw);
718 /* Enable DMA coalescing after configuration */
719 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
720 reg |= IXGBE_DMACR_DMAC_EN;
721 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
723 return IXGBE_SUCCESS;
727 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
728 * @hw: pointer to hardware structure
730 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
731 * ixgbe_hw struct in order to set up EEPROM access.
733 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
735 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
739 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
741 if (eeprom->type == ixgbe_eeprom_uninitialized) {
742 eeprom->semaphore_delay = 10;
743 eeprom->type = ixgbe_flash;
745 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
746 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
747 IXGBE_EEC_SIZE_SHIFT);
748 eeprom->word_size = 1 << (eeprom_size +
749 IXGBE_EEPROM_WORD_SIZE_SHIFT);
751 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
752 eeprom->type, eeprom->word_size);
755 return IXGBE_SUCCESS;
759 * ixgbe_enable_eee_x550 - Enable EEE support
760 * @hw: pointer to hardware structure
762 static s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
768 if (hw->mac.type == ixgbe_mac_X550) {
769 /* Advertise EEE capability */
770 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
771 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
774 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
775 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
776 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
778 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
779 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
781 return IXGBE_SUCCESS;
784 switch (hw->device_id) {
785 case IXGBE_DEV_ID_X550EM_X_KR:
786 case IXGBE_DEV_ID_X550EM_A_KR:
787 case IXGBE_DEV_ID_X550EM_A_KR_L:
788 status = ixgbe_read_iosf_sb_reg_x550(hw,
789 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
790 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
791 if (status != IXGBE_SUCCESS)
794 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
795 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
797 /* Don't advertise FEC capability when EEE enabled. */
798 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
800 status = ixgbe_write_iosf_sb_reg_x550(hw,
801 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
802 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
803 if (status != IXGBE_SUCCESS)
810 return IXGBE_SUCCESS;
814 * ixgbe_disable_eee_x550 - Disable EEE support
815 * @hw: pointer to hardware structure
817 static s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
823 if (hw->mac.type == ixgbe_mac_X550) {
824 /* Disable advertised EEE capability */
825 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
826 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
829 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
830 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
831 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
833 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
834 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
836 return IXGBE_SUCCESS;
839 switch (hw->device_id) {
840 case IXGBE_DEV_ID_X550EM_X_KR:
841 case IXGBE_DEV_ID_X550EM_A_KR:
842 case IXGBE_DEV_ID_X550EM_A_KR_L:
843 status = ixgbe_read_iosf_sb_reg_x550(hw,
844 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
845 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
846 if (status != IXGBE_SUCCESS)
849 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
850 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
852 /* Advertise FEC capability when EEE is disabled. */
853 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
855 status = ixgbe_write_iosf_sb_reg_x550(hw,
856 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
857 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
858 if (status != IXGBE_SUCCESS)
865 return IXGBE_SUCCESS;
869 * ixgbe_setup_eee_X550 - Enable/disable EEE support
870 * @hw: pointer to the HW structure
871 * @enable_eee: boolean flag to enable EEE
873 * Enable/disable EEE based on enable_eee flag.
874 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
878 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
883 DEBUGFUNC("ixgbe_setup_eee_X550");
885 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
886 /* Enable or disable EEE per flag */
888 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
890 /* Not supported on first revision of X550EM_x. */
891 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
892 !(IXGBE_FUSES0_REV_MASK &
893 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
894 return IXGBE_SUCCESS;
895 status = ixgbe_enable_eee_x550(hw);
899 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
901 status = ixgbe_disable_eee_x550(hw);
905 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
907 return IXGBE_SUCCESS;
911 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
912 * @hw: pointer to hardware structure
913 * @enable: enable or disable source address pruning
914 * @pool: Rx pool to set source address pruning for
916 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
921 /* max rx pool is 63 */
925 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
926 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
929 pfflp |= (1ULL << pool);
931 pfflp &= ~(1ULL << pool);
933 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
934 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
938 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
939 * @hw: pointer to hardware structure
940 * @enable: enable or disable switch for Ethertype anti-spoofing
941 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
944 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
947 int vf_target_reg = vf >> 3;
948 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
951 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
953 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
955 pfvfspoof |= (1 << vf_target_shift);
957 pfvfspoof &= ~(1 << vf_target_shift);
959 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
963 * ixgbe_iosf_wait - Wait for IOSF command completion
964 * @hw: pointer to hardware structure
965 * @ctrl: pointer to location to receive final IOSF control value
967 * Returns failing status on timeout
969 * Note: ctrl can be NULL if the IOSF control register value is not needed
971 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
975 /* Check every 10 usec to see if the address cycle completed.
976 * The SB IOSF BUSY bit will clear when the operation is
979 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
980 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
981 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
987 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
988 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
989 return IXGBE_ERR_PHY;
992 return IXGBE_SUCCESS;
996 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
998 * @hw: pointer to hardware structure
999 * @reg_addr: 32 bit PHY register to write
1000 * @device_type: 3 bit device type
1001 * @data: Data to write to the register
1003 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1004 u32 device_type, u32 data)
1006 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1010 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1011 if (ret != IXGBE_SUCCESS)
1014 ret = ixgbe_iosf_wait(hw, NULL);
1015 if (ret != IXGBE_SUCCESS)
1018 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1019 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1021 /* Write IOSF control register */
1022 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1024 /* Write IOSF data register */
1025 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1027 ret = ixgbe_iosf_wait(hw, &command);
1029 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1030 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1031 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1032 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1033 "Failed to write, error %x\n", error);
1034 ret = IXGBE_ERR_PHY;
1038 ixgbe_release_swfw_semaphore(hw, gssr);
1043 * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
1045 * @hw: pointer to hardware structure
1046 * @reg_addr: 32 bit PHY register to write
1047 * @device_type: 3 bit device type
1048 * @phy_data: Pointer to read data from the register
1050 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1051 u32 device_type, u32 *data)
1053 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1057 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1058 if (ret != IXGBE_SUCCESS)
1061 ret = ixgbe_iosf_wait(hw, NULL);
1062 if (ret != IXGBE_SUCCESS)
1065 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1066 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1068 /* Write IOSF control register */
1069 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1071 ret = ixgbe_iosf_wait(hw, &command);
1073 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1074 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1075 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1076 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1077 "Failed to read, error %x\n", error);
1078 ret = IXGBE_ERR_PHY;
1081 if (ret == IXGBE_SUCCESS)
1082 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1085 ixgbe_release_swfw_semaphore(hw, gssr);
1090 * ixgbe_get_phy_token - Get the token for shared phy access
1091 * @hw: Pointer to hardware structure
1094 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1096 struct ixgbe_hic_phy_token_req token_cmd;
1099 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1100 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1101 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1102 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1103 token_cmd.port_number = hw->bus.lan_id;
1104 token_cmd.command_type = FW_PHY_TOKEN_REQ;
1106 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1108 IXGBE_HI_COMMAND_TIMEOUT,
1112 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1113 return IXGBE_SUCCESS;
1114 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1115 return IXGBE_ERR_FW_RESP_INVALID;
1117 return IXGBE_ERR_TOKEN_RETRY;
1121 * ixgbe_put_phy_token - Put the token for shared phy access
1122 * @hw: Pointer to hardware structure
1125 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1127 struct ixgbe_hic_phy_token_req token_cmd;
1130 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1131 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1132 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1133 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1134 token_cmd.port_number = hw->bus.lan_id;
1135 token_cmd.command_type = FW_PHY_TOKEN_REL;
1137 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1139 IXGBE_HI_COMMAND_TIMEOUT,
1143 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1144 return IXGBE_SUCCESS;
1145 return IXGBE_ERR_FW_RESP_INVALID;
1149 * ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1150 * of the IOSF device
1151 * @hw: pointer to hardware structure
1152 * @reg_addr: 32 bit PHY register to write
1153 * @device_type: 3 bit device type
1154 * @data: Data to write to the register
1156 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1157 u32 device_type, u32 data)
1159 struct ixgbe_hic_internal_phy_req write_cmd;
1161 UNREFERENCED_1PARAMETER(device_type);
1163 memset(&write_cmd, 0, sizeof(write_cmd));
1164 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1165 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1166 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1167 write_cmd.port_number = hw->bus.lan_id;
1168 write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1169 write_cmd.address = (u16)reg_addr;
1170 write_cmd.write_data = data;
1172 status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1174 IXGBE_HI_COMMAND_TIMEOUT, false);
1180 * ixgbe_read_iosf_sb_reg_x550a - Writes a value to specified register
1181 * of the IOSF device.
1182 * @hw: pointer to hardware structure
1183 * @reg_addr: 32 bit PHY register to write
1184 * @device_type: 3 bit device type
1185 * @data: Pointer to read data from the register
1187 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1188 u32 device_type, u32 *data)
1190 struct ixgbe_hic_internal_phy_req read_cmd;
1192 UNREFERENCED_1PARAMETER(device_type);
1194 memset(&read_cmd, 0, sizeof(read_cmd));
1195 read_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1196 read_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1197 read_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1198 read_cmd.port_number = hw->bus.lan_id;
1199 read_cmd.command_type = FW_INT_PHY_REQ_READ;
1200 read_cmd.address = (u16)reg_addr;
1202 status = ixgbe_host_interface_command(hw, (u32 *)&read_cmd,
1204 IXGBE_HI_COMMAND_TIMEOUT, true);
1206 /* Extract the register value from the response. */
1207 *data = ((struct ixgbe_hic_internal_phy_resp *)&read_cmd)->read_data;
1213 * ixgbe_disable_mdd_X550
1214 * @hw: pointer to hardware structure
1216 * Disable malicious driver detection
1218 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1222 DEBUGFUNC("ixgbe_disable_mdd_X550");
1224 /* Disable MDD for TX DMA and interrupt */
1225 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1226 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1227 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1229 /* Disable MDD for RX and interrupt */
1230 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1231 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1232 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1236 * ixgbe_enable_mdd_X550
1237 * @hw: pointer to hardware structure
1239 * Enable malicious driver detection
1241 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1245 DEBUGFUNC("ixgbe_enable_mdd_X550");
1247 /* Enable MDD for TX DMA and interrupt */
1248 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1249 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1250 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1252 /* Enable MDD for RX and interrupt */
1253 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1254 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1255 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1259 * ixgbe_restore_mdd_vf_X550
1260 * @hw: pointer to hardware structure
1263 * Restore VF that was disabled during malicious driver detection event
1265 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1267 u32 idx, reg, num_qs, start_q, bitmask;
1269 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1271 /* Map VF to queues */
1272 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1273 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1274 case IXGBE_MRQC_VMDQRT8TCEN:
1275 num_qs = 8; /* 16 VFs / pools */
1276 bitmask = 0x000000FF;
1278 case IXGBE_MRQC_VMDQRSS32EN:
1279 case IXGBE_MRQC_VMDQRT4TCEN:
1280 num_qs = 4; /* 32 VFs / pools */
1281 bitmask = 0x0000000F;
1283 default: /* 64 VFs / pools */
1285 bitmask = 0x00000003;
1288 start_q = vf * num_qs;
1290 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1293 reg |= (bitmask << (start_q % 32));
1294 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1295 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1299 * ixgbe_mdd_event_X550
1300 * @hw: pointer to hardware structure
1301 * @vf_bitmap: vf bitmap of malicious vfs
1303 * Handle malicious driver detection event.
1305 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1308 u32 i, j, reg, q, shift, vf, idx;
1310 DEBUGFUNC("ixgbe_mdd_event_X550");
1312 /* figure out pool size for mapping to vf's */
1313 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1314 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1315 case IXGBE_MRQC_VMDQRT8TCEN:
1316 shift = 3; /* 16 VFs / pools */
1318 case IXGBE_MRQC_VMDQRSS32EN:
1319 case IXGBE_MRQC_VMDQRT4TCEN:
1320 shift = 2; /* 32 VFs / pools */
1323 shift = 1; /* 64 VFs / pools */
1327 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1328 for (i = 0; i < 4; i++) {
1329 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1330 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1335 /* Get malicious queue */
1336 for (j = 0; j < 32 && wqbr; j++) {
1338 if (!(wqbr & (1 << j)))
1341 /* Get queue from bitmask */
1344 /* Map queue to vf */
1347 /* Set vf bit in vf_bitmap */
1349 vf_bitmap[idx] |= (1 << (vf % 32));
1356 * ixgbe_get_media_type_X550em - Get media type
1357 * @hw: pointer to hardware structure
1359 * Returns the media type (fiber, copper, backplane)
1361 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1363 enum ixgbe_media_type media_type;
1365 DEBUGFUNC("ixgbe_get_media_type_X550em");
1367 /* Detect if there is a copper PHY attached. */
1368 switch (hw->device_id) {
1369 case IXGBE_DEV_ID_X550EM_X_KR:
1370 case IXGBE_DEV_ID_X550EM_X_KX4:
1371 case IXGBE_DEV_ID_X550EM_A_KR:
1372 case IXGBE_DEV_ID_X550EM_A_KR_L:
1373 media_type = ixgbe_media_type_backplane;
1375 case IXGBE_DEV_ID_X550EM_X_SFP:
1376 case IXGBE_DEV_ID_X550EM_A_SFP:
1377 case IXGBE_DEV_ID_X550EM_A_SFP_N:
1378 case IXGBE_DEV_ID_X550EM_A_QSFP:
1379 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1380 media_type = ixgbe_media_type_fiber;
1382 case IXGBE_DEV_ID_X550EM_X_1G_T:
1383 case IXGBE_DEV_ID_X550EM_X_10G_T:
1384 case IXGBE_DEV_ID_X550EM_A_10G_T:
1385 media_type = ixgbe_media_type_copper;
1387 case IXGBE_DEV_ID_X550EM_A_1G_T:
1388 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1389 media_type = ixgbe_media_type_sgmii;
1390 hw->phy.type = ixgbe_phy_sgmii;
1393 media_type = ixgbe_media_type_unknown;
1400 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1401 * @hw: pointer to hardware structure
1402 * @linear: true if SFP module is linear
1404 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1406 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1408 switch (hw->phy.sfp_type) {
1409 case ixgbe_sfp_type_not_present:
1410 return IXGBE_ERR_SFP_NOT_PRESENT;
1411 case ixgbe_sfp_type_da_cu_core0:
1412 case ixgbe_sfp_type_da_cu_core1:
1415 case ixgbe_sfp_type_srlr_core0:
1416 case ixgbe_sfp_type_srlr_core1:
1417 case ixgbe_sfp_type_da_act_lmt_core0:
1418 case ixgbe_sfp_type_da_act_lmt_core1:
1419 case ixgbe_sfp_type_1g_sx_core0:
1420 case ixgbe_sfp_type_1g_sx_core1:
1421 case ixgbe_sfp_type_1g_lx_core0:
1422 case ixgbe_sfp_type_1g_lx_core1:
1425 case ixgbe_sfp_type_unknown:
1426 case ixgbe_sfp_type_1g_cu_core0:
1427 case ixgbe_sfp_type_1g_cu_core1:
1429 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1432 return IXGBE_SUCCESS;
1436 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1437 * @hw: pointer to hardware structure
1439 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1441 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1446 DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1448 status = ixgbe_identify_module_generic(hw);
1450 if (status != IXGBE_SUCCESS)
1453 /* Check if SFP module is supported */
1454 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1460 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1461 * @hw: pointer to hardware structure
1463 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1468 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1470 /* Check if SFP module is supported */
1471 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1473 if (status != IXGBE_SUCCESS)
1476 ixgbe_init_mac_link_ops_X550em(hw);
1477 hw->phy.ops.reset = NULL;
1479 return IXGBE_SUCCESS;
1483 * ixgbe_setup_sgmii - Set up link for sgmii
1484 * @hw: pointer to hardware structure
1486 static s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1487 bool autoneg_wait_to_complete)
1489 struct ixgbe_mac_info *mac = &hw->mac;
1492 UNREFERENCED_2PARAMETER(speed, autoneg_wait_to_complete);
1494 rc = mac->ops.read_iosf_sb_reg(hw,
1495 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1496 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1500 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1501 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1502 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1503 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1504 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1505 rc = mac->ops.write_iosf_sb_reg(hw,
1506 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1507 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1511 rc = mac->ops.read_iosf_sb_reg(hw,
1512 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1513 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1517 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1518 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1519 rc = mac->ops.write_iosf_sb_reg(hw,
1520 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1521 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1525 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1526 rc = mac->ops.write_iosf_sb_reg(hw,
1527 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1528 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1534 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1535 * @hw: pointer to hardware structure
1537 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1539 struct ixgbe_mac_info *mac = &hw->mac;
1541 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1543 switch (hw->mac.ops.get_media_type(hw)) {
1544 case ixgbe_media_type_fiber:
1545 /* CS4227 does not support autoneg, so disable the laser control
1546 * functions for SFP+ fiber
1548 mac->ops.disable_tx_laser = NULL;
1549 mac->ops.enable_tx_laser = NULL;
1550 mac->ops.flap_tx_laser = NULL;
1551 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1552 mac->ops.set_rate_select_speed =
1553 ixgbe_set_soft_rate_select_speed;
1554 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N)
1555 mac->ops.setup_mac_link =
1556 ixgbe_setup_mac_link_sfp_x550a;
1558 mac->ops.setup_mac_link =
1559 ixgbe_setup_mac_link_sfp_x550em;
1561 case ixgbe_media_type_copper:
1562 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1563 mac->ops.check_link = ixgbe_check_link_t_X550em;
1565 case ixgbe_media_type_backplane:
1567 case ixgbe_media_type_sgmii:
1568 mac->ops.setup_link = ixgbe_setup_sgmii;
1576 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1577 * @hw: pointer to hardware structure
1578 * @speed: pointer to link speed
1579 * @autoneg: true when autoneg or autotry is enabled
1581 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1582 ixgbe_link_speed *speed,
1585 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1588 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1590 /* CS4227 SFP must not enable auto-negotiation */
1593 /* Check if 1G SFP module. */
1594 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1595 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1596 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1597 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1598 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1599 return IXGBE_SUCCESS;
1602 /* Link capabilities are based on SFP */
1603 if (hw->phy.multispeed_fiber)
1604 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1605 IXGBE_LINK_SPEED_1GB_FULL;
1607 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1609 switch (hw->phy.type) {
1611 *speed = IXGBE_LINK_SPEED_100_FULL |
1612 IXGBE_LINK_SPEED_1GB_FULL;
1614 case ixgbe_phy_sgmii:
1615 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1618 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1619 IXGBE_LINK_SPEED_1GB_FULL;
1625 return IXGBE_SUCCESS;
1629 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1630 * @hw: pointer to hardware structure
1631 * @lsc: pointer to boolean flag which indicates whether external Base T
1632 * PHY interrupt is lsc
1634 * Determime if external Base T PHY interrupt cause is high temperature
1635 * failure alarm or link status change.
1637 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1638 * failure alarm, else return PHY access status.
1640 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1647 /* Vendor alarm triggered */
1648 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1649 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1652 if (status != IXGBE_SUCCESS ||
1653 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1656 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1657 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1658 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1661 if (status != IXGBE_SUCCESS ||
1662 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1663 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1666 /* Global alarm triggered */
1667 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1668 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1671 if (status != IXGBE_SUCCESS)
1674 /* If high temperature failure, then return over temp error and exit */
1675 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1676 /* power down the PHY in case the PHY FW didn't already */
1677 ixgbe_set_copper_phy_power(hw, false);
1678 return IXGBE_ERR_OVERTEMP;
1679 } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1680 /* device fault alarm triggered */
1681 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1682 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1685 if (status != IXGBE_SUCCESS)
1688 /* if device fault was due to high temp alarm handle and exit */
1689 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1690 /* power down the PHY in case the PHY FW didn't */
1691 ixgbe_set_copper_phy_power(hw, false);
1692 return IXGBE_ERR_OVERTEMP;
1696 /* Vendor alarm 2 triggered */
1697 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1698 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1700 if (status != IXGBE_SUCCESS ||
1701 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1704 /* link connect/disconnect event occurred */
1705 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1706 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1708 if (status != IXGBE_SUCCESS)
1712 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1715 return IXGBE_SUCCESS;
1719 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1720 * @hw: pointer to hardware structure
1722 * Enable link status change and temperature failure alarm for the external
1725 * Returns PHY access status
1727 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1733 /* Clear interrupt flags */
1734 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1736 /* Enable link status change alarm */
1737 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1738 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1740 if (status != IXGBE_SUCCESS)
1743 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1745 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1746 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1748 if (status != IXGBE_SUCCESS)
1751 /* Enable high temperature failure and global fault alarms */
1752 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1753 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1756 if (status != IXGBE_SUCCESS)
1759 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
1760 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
1762 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1763 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1766 if (status != IXGBE_SUCCESS)
1769 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1770 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1771 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1774 if (status != IXGBE_SUCCESS)
1777 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1778 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1780 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1781 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1784 if (status != IXGBE_SUCCESS)
1787 /* Enable chip-wide vendor alarm */
1788 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1789 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1792 if (status != IXGBE_SUCCESS)
1795 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1797 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1798 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1805 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1806 * @hw: pointer to hardware structure
1807 * @speed: link speed
1809 * Configures the integrated KR PHY.
1811 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1812 ixgbe_link_speed speed)
1817 status = ixgbe_read_iosf_sb_reg_x550(hw,
1818 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1819 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1823 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1824 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1825 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1827 /* Advertise 10G support. */
1828 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1829 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1831 /* Advertise 1G support. */
1832 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1833 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1835 /* Restart auto-negotiation. */
1836 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1837 status = ixgbe_write_iosf_sb_reg_x550(hw,
1838 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1839 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1845 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1846 * @hw: pointer to hardware structure
1848 * Initialize any function pointers that were not able to be
1849 * set during init_shared_code because the PHY/SFP type was
1850 * not known. Perform the SFP init if necessary.
1852 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1854 struct ixgbe_phy_info *phy = &hw->phy;
1857 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1859 hw->mac.ops.set_lan_id(hw);
1861 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1862 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1863 ixgbe_setup_mux_ctl(hw);
1865 /* Save NW management interface connected on board. This is used
1866 * to determine internal PHY mode.
1868 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1869 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
1872 /* Identify the PHY or SFP module */
1873 ret_val = phy->ops.identify(hw);
1874 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1877 /* Setup function pointers based on detected hardware */
1878 ixgbe_init_mac_link_ops_X550em(hw);
1879 if (phy->sfp_type != ixgbe_sfp_type_unknown)
1880 phy->ops.reset = NULL;
1882 /* Set functions pointers based on phy type */
1883 switch (hw->phy.type) {
1884 case ixgbe_phy_x550em_kx4:
1885 phy->ops.setup_link = NULL;
1886 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1887 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1889 case ixgbe_phy_x550em_kr:
1890 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1891 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1892 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1894 case ixgbe_phy_x550em_ext_t:
1895 /* Save NW management interface connected on board. This is used
1896 * to determine internal PHY mode
1898 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1900 /* If internal link mode is XFI, then setup iXFI internal link,
1901 * else setup KR now.
1903 phy->ops.setup_internal_link =
1904 ixgbe_setup_internal_phy_t_x550em;
1906 /* setup SW LPLU only for first revision of X550EM_x */
1907 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
1908 !(IXGBE_FUSES0_REV_MASK &
1909 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
1910 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1912 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1913 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1915 case ixgbe_phy_sgmii:
1916 phy->ops.setup_link = NULL;
1927 * ixgbe_set_mdio_speed - Set MDIO clock speed
1928 * @hw: pointer to hardware structure
1930 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
1934 switch (hw->device_id) {
1935 case IXGBE_DEV_ID_X550EM_X_10G_T:
1936 case IXGBE_DEV_ID_X550EM_A_1G_T:
1937 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1938 case IXGBE_DEV_ID_X550EM_A_10G_T:
1939 case IXGBE_DEV_ID_X550EM_A_SFP:
1940 case IXGBE_DEV_ID_X550EM_A_QSFP:
1941 /* Config MDIO clock speed before the first MDIO PHY access */
1942 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1943 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
1944 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1952 * ixgbe_reset_hw_X550em - Perform hardware reset
1953 * @hw: pointer to hardware structure
1955 * Resets the hardware by resetting the transmit and receive units, masks
1956 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1959 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1961 ixgbe_link_speed link_speed;
1965 bool link_up = false;
1967 DEBUGFUNC("ixgbe_reset_hw_X550em");
1969 /* Call adapter stop to disable Tx/Rx and clear interrupts */
1970 status = hw->mac.ops.stop_adapter(hw);
1971 if (status != IXGBE_SUCCESS)
1974 /* flush pending Tx transactions */
1975 ixgbe_clear_tx_pending(hw);
1977 ixgbe_set_mdio_speed(hw);
1979 /* PHY ops must be identified and initialized prior to reset */
1980 status = hw->phy.ops.init(hw);
1982 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1985 /* start the external PHY */
1986 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1987 status = ixgbe_init_ext_t_x550em(hw);
1992 /* Setup SFP module if there is one present. */
1993 if (hw->phy.sfp_setup_needed) {
1994 status = hw->mac.ops.setup_sfp(hw);
1995 hw->phy.sfp_setup_needed = false;
1998 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2002 if (!hw->phy.reset_disable && hw->phy.ops.reset)
2003 hw->phy.ops.reset(hw);
2006 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
2007 * If link reset is used when link is up, it might reset the PHY when
2008 * mng is using it. If link is down or the flag to force full link
2009 * reset is set, then perform link reset.
2011 ctrl = IXGBE_CTRL_LNK_RST;
2012 if (!hw->force_full_reset) {
2013 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2015 ctrl = IXGBE_CTRL_RST;
2018 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2019 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2020 IXGBE_WRITE_FLUSH(hw);
2022 /* Poll for reset bit to self-clear meaning reset is complete */
2023 for (i = 0; i < 10; i++) {
2025 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2026 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2030 if (ctrl & IXGBE_CTRL_RST_MASK) {
2031 status = IXGBE_ERR_RESET_FAILED;
2032 DEBUGOUT("Reset polling failed to complete.\n");
2037 /* Double resets are required for recovery from certain error
2038 * conditions. Between resets, it is necessary to stall to
2039 * allow time for any pending HW events to complete.
2041 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2042 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2046 /* Store the permanent mac address */
2047 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2049 /* Store MAC address from RAR0, clear receive address registers, and
2050 * clear the multicast table. Also reset num_rar_entries to 128,
2051 * since we modify this value when programming the SAN MAC address.
2053 hw->mac.num_rar_entries = 128;
2054 hw->mac.ops.init_rx_addrs(hw);
2056 ixgbe_set_mdio_speed(hw);
2058 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2059 ixgbe_setup_mux_ctl(hw);
2065 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2066 * @hw: pointer to hardware structure
2068 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2073 status = hw->phy.ops.read_reg(hw,
2074 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2075 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2078 if (status != IXGBE_SUCCESS)
2081 /* If PHY FW reset completed bit is set then this is the first
2082 * SW instance after a power on so the PHY FW must be un-stalled.
2084 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2085 status = hw->phy.ops.read_reg(hw,
2086 IXGBE_MDIO_GLOBAL_RES_PR_10,
2087 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2090 if (status != IXGBE_SUCCESS)
2093 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2095 status = hw->phy.ops.write_reg(hw,
2096 IXGBE_MDIO_GLOBAL_RES_PR_10,
2097 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2100 if (status != IXGBE_SUCCESS)
2108 * ixgbe_setup_kr_x550em - Configure the KR PHY.
2109 * @hw: pointer to hardware structure
2111 * Configures the integrated KR PHY for X550EM_x.
2113 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2115 if (hw->mac.type != ixgbe_mac_X550EM_x)
2116 return IXGBE_SUCCESS;
2118 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2122 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2123 * @hw: pointer to hardware structure
2125 * Configure the external PHY and the integrated KR PHY for SFP support.
2127 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2128 ixgbe_link_speed speed,
2129 bool autoneg_wait_to_complete)
2132 u16 reg_slice, reg_val;
2133 bool setup_linear = false;
2134 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2136 /* Check if SFP module is supported and linear */
2137 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2139 /* If no SFP module present, then return success. Return success since
2140 * there is no reason to configure CS4227 and SFP not present error is
2141 * not excepted in the setup MAC link flow.
2143 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2144 return IXGBE_SUCCESS;
2146 if (ret_val != IXGBE_SUCCESS)
2149 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2150 /* Configure CS4227 LINE side to 10G SR. */
2151 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
2152 (hw->bus.lan_id << 12);
2153 reg_val = IXGBE_CS4227_SPEED_10G;
2154 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2157 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2158 (hw->bus.lan_id << 12);
2159 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2160 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2163 /* Configure CS4227 for HOST connection rate then type. */
2164 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
2165 (hw->bus.lan_id << 12);
2166 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
2167 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
2168 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2171 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
2172 (hw->bus.lan_id << 12);
2174 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2176 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2177 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2180 /* Setup XFI internal link. */
2181 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2183 /* Configure internal PHY for KR/KX. */
2184 ixgbe_setup_kr_speed_x550em(hw, speed);
2186 /* Configure CS4227 LINE side to proper mode. */
2187 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2188 (hw->bus.lan_id << 12);
2190 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2192 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2193 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2200 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2201 * @hw: pointer to hardware structure
2203 * Configure the the integrated PHY for SFP support.
2205 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2206 ixgbe_link_speed speed,
2207 bool autoneg_wait_to_complete)
2211 bool setup_linear = false;
2213 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2215 /* Check if SFP module is supported and linear */
2216 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2218 /* If no SFP module present, then return success. Return success since
2219 * SFP not present error is not excepted in the setup MAC link flow.
2221 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2222 return IXGBE_SUCCESS;
2224 if (ret_val != IXGBE_SUCCESS)
2227 /* Configure internal PHY for native SFI */
2228 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2229 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2230 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2232 if (ret_val != IXGBE_SUCCESS)
2236 reg_val &= ~IXGBE_KRM_AN_CNTL_8_LIMITING;
2237 reg_val |= IXGBE_KRM_AN_CNTL_8_LINEAR;
2239 reg_val |= IXGBE_KRM_AN_CNTL_8_LIMITING;
2240 reg_val &= ~IXGBE_KRM_AN_CNTL_8_LINEAR;
2243 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2244 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2245 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2247 if (ret_val != IXGBE_SUCCESS)
2250 /* Setup XFI/SFI internal link. */
2251 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2257 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2258 * @hw: pointer to hardware structure
2260 * iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2262 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2267 /* Disable training protocol FSM. */
2268 status = ixgbe_read_iosf_sb_reg_x550(hw,
2269 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2270 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2271 if (status != IXGBE_SUCCESS)
2273 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2274 status = ixgbe_write_iosf_sb_reg_x550(hw,
2275 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2276 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2277 if (status != IXGBE_SUCCESS)
2280 /* Disable Flex from training TXFFE. */
2281 status = ixgbe_read_iosf_sb_reg_x550(hw,
2282 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2283 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2284 if (status != IXGBE_SUCCESS)
2286 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2287 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2288 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2289 status = ixgbe_write_iosf_sb_reg_x550(hw,
2290 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2291 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2292 if (status != IXGBE_SUCCESS)
2294 status = ixgbe_read_iosf_sb_reg_x550(hw,
2295 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2296 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2297 if (status != IXGBE_SUCCESS)
2299 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2300 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2301 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2302 status = ixgbe_write_iosf_sb_reg_x550(hw,
2303 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2304 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2305 if (status != IXGBE_SUCCESS)
2308 /* Enable override for coefficients. */
2309 status = ixgbe_read_iosf_sb_reg_x550(hw,
2310 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2311 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2312 if (status != IXGBE_SUCCESS)
2314 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2315 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2316 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2317 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2318 status = ixgbe_write_iosf_sb_reg_x550(hw,
2319 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2320 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2325 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2326 * @hw: pointer to hardware structure
2327 * @speed: the link speed to force
2329 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
2330 * internal and external PHY at a specific speed, without autonegotiation.
2332 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2337 /* Disable AN and force speed to 10G Serial. */
2338 status = ixgbe_read_iosf_sb_reg_x550(hw,
2339 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2340 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2341 if (status != IXGBE_SUCCESS)
2344 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2345 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2347 /* Select forced link speed for internal PHY. */
2349 case IXGBE_LINK_SPEED_10GB_FULL:
2350 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2352 case IXGBE_LINK_SPEED_1GB_FULL:
2353 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2356 /* Other link speeds are not supported by internal KR PHY. */
2357 return IXGBE_ERR_LINK_SETUP;
2360 status = ixgbe_write_iosf_sb_reg_x550(hw,
2361 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2362 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2363 if (status != IXGBE_SUCCESS)
2366 /* Additional configuration needed for x550em_x */
2367 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2368 status = ixgbe_setup_ixfi_x550em_x(hw);
2369 if (status != IXGBE_SUCCESS)
2373 /* Toggle port SW reset by AN reset. */
2374 status = ixgbe_read_iosf_sb_reg_x550(hw,
2375 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2376 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2377 if (status != IXGBE_SUCCESS)
2379 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2380 status = ixgbe_write_iosf_sb_reg_x550(hw,
2381 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2382 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2388 * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2389 * @hw: address of hardware structure
2390 * @link_up: address of boolean to indicate link status
2392 * Returns error code if unable to get link status.
2394 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2401 /* read this twice back to back to indicate current status */
2402 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2403 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2405 if (ret != IXGBE_SUCCESS)
2408 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2409 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2411 if (ret != IXGBE_SUCCESS)
2414 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2416 return IXGBE_SUCCESS;
2420 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2421 * @hw: point to hardware structure
2423 * Configures the link between the integrated KR PHY and the external X557 PHY
2424 * The driver will call this function when it gets a link status change
2425 * interrupt from the X557 PHY. This function configures the link speed
2426 * between the PHYs to match the link speed of the BASE-T link.
2428 * A return of a non-zero value indicates an error, and the base driver should
2429 * not report link up.
2431 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2433 ixgbe_link_speed force_speed;
2438 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2439 return IXGBE_ERR_CONFIG;
2441 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2442 /* If link is down, there is no setup necessary so return */
2443 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2444 if (status != IXGBE_SUCCESS)
2448 return IXGBE_SUCCESS;
2450 status = hw->phy.ops.read_reg(hw,
2451 IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2452 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2454 if (status != IXGBE_SUCCESS)
2457 /* If link is still down - no setup is required so return */
2458 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2459 if (status != IXGBE_SUCCESS)
2462 return IXGBE_SUCCESS;
2464 /* clear everything but the speed and duplex bits */
2465 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2468 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2469 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2471 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2472 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2475 /* Internal PHY does not support anything else */
2476 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2479 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2481 speed = IXGBE_LINK_SPEED_10GB_FULL |
2482 IXGBE_LINK_SPEED_1GB_FULL;
2483 return ixgbe_setup_kr_speed_x550em(hw, speed);
2488 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
2489 * @hw: pointer to hardware structure
2491 * Configures the integrated KR PHY to use internal loopback mode.
2493 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
2498 /* Disable AN and force speed to 10G Serial. */
2499 status = ixgbe_read_iosf_sb_reg_x550(hw,
2500 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2501 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2502 if (status != IXGBE_SUCCESS)
2504 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2505 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2506 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2507 status = ixgbe_write_iosf_sb_reg_x550(hw,
2508 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2509 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2510 if (status != IXGBE_SUCCESS)
2513 /* Set near-end loopback clocks. */
2514 status = ixgbe_read_iosf_sb_reg_x550(hw,
2515 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2516 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2517 if (status != IXGBE_SUCCESS)
2519 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2520 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2521 status = ixgbe_write_iosf_sb_reg_x550(hw,
2522 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2523 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2524 if (status != IXGBE_SUCCESS)
2527 /* Set loopback enable. */
2528 status = ixgbe_read_iosf_sb_reg_x550(hw,
2529 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2530 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2531 if (status != IXGBE_SUCCESS)
2533 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2534 status = ixgbe_write_iosf_sb_reg_x550(hw,
2535 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2536 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2537 if (status != IXGBE_SUCCESS)
2540 /* Training bypass. */
2541 status = ixgbe_read_iosf_sb_reg_x550(hw,
2542 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2543 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2544 if (status != IXGBE_SUCCESS)
2546 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2547 status = ixgbe_write_iosf_sb_reg_x550(hw,
2548 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2549 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2555 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2556 * assuming that the semaphore is already obtained.
2557 * @hw: pointer to hardware structure
2558 * @offset: offset of word in the EEPROM to read
2559 * @data: word read from the EEPROM
2561 * Reads a 16 bit word from the EEPROM using the hostif.
2563 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2567 struct ixgbe_hic_read_shadow_ram buffer;
2569 DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2570 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2571 buffer.hdr.req.buf_lenh = 0;
2572 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2573 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2575 /* convert offset from words to bytes */
2576 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2578 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2580 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2582 IXGBE_HI_COMMAND_TIMEOUT, false);
2587 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2588 FW_NVM_DATA_OFFSET);
2594 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2595 * @hw: pointer to hardware structure
2596 * @offset: offset of word in the EEPROM to read
2597 * @data: word read from the EEPROM
2599 * Reads a 16 bit word from the EEPROM using the hostif.
2601 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2604 s32 status = IXGBE_SUCCESS;
2606 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2608 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2610 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2611 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2613 status = IXGBE_ERR_SWFW_SYNC;
2620 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2621 * @hw: pointer to hardware structure
2622 * @offset: offset of word in the EEPROM to read
2623 * @words: number of words
2624 * @data: word(s) read from the EEPROM
2626 * Reads a 16 bit word(s) from the EEPROM using the hostif.
2628 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2629 u16 offset, u16 words, u16 *data)
2631 struct ixgbe_hic_read_shadow_ram buffer;
2632 u32 current_word = 0;
2637 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2639 /* Take semaphore for the entire operation. */
2640 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2642 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2646 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2647 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2649 words_to_read = words;
2651 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2652 buffer.hdr.req.buf_lenh = 0;
2653 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2654 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2656 /* convert offset from words to bytes */
2657 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2658 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2660 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2662 IXGBE_HI_COMMAND_TIMEOUT,
2666 DEBUGOUT("Host interface command failed\n");
2670 for (i = 0; i < words_to_read; i++) {
2671 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
2673 u32 value = IXGBE_READ_REG(hw, reg);
2675 data[current_word] = (u16)(value & 0xffff);
2678 if (i < words_to_read) {
2680 data[current_word] = (u16)(value & 0xffff);
2684 words -= words_to_read;
2688 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2693 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2694 * @hw: pointer to hardware structure
2695 * @offset: offset of word in the EEPROM to write
2696 * @data: word write to the EEPROM
2698 * Write a 16 bit word to the EEPROM using the hostif.
2700 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2704 struct ixgbe_hic_write_shadow_ram buffer;
2706 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
2708 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
2709 buffer.hdr.req.buf_lenh = 0;
2710 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
2711 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2714 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2716 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2718 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2720 IXGBE_HI_COMMAND_TIMEOUT, false);
2726 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2727 * @hw: pointer to hardware structure
2728 * @offset: offset of word in the EEPROM to write
2729 * @data: word write to the EEPROM
2731 * Write a 16 bit word to the EEPROM using the hostif.
2733 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2736 s32 status = IXGBE_SUCCESS;
2738 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2740 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2742 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2743 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2745 DEBUGOUT("write ee hostif failed to get semaphore");
2746 status = IXGBE_ERR_SWFW_SYNC;
2753 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2754 * @hw: pointer to hardware structure
2755 * @offset: offset of word in the EEPROM to write
2756 * @words: number of words
2757 * @data: word(s) write to the EEPROM
2759 * Write a 16 bit word(s) to the EEPROM using the hostif.
2761 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2762 u16 offset, u16 words, u16 *data)
2764 s32 status = IXGBE_SUCCESS;
2767 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2769 /* Take semaphore for the entire operation. */
2770 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2771 if (status != IXGBE_SUCCESS) {
2772 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2776 for (i = 0; i < words; i++) {
2777 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2780 if (status != IXGBE_SUCCESS) {
2781 DEBUGOUT("Eeprom buffered write failed\n");
2786 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2793 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2794 * @hw: pointer to hardware structure
2795 * @ptr: pointer offset in eeprom
2796 * @size: size of section pointed by ptr, if 0 first word will be used as size
2797 * @csum: address of checksum to update
2799 * Returns error status for any failure
2801 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2802 u16 size, u16 *csum, u16 *buffer,
2807 u16 length, bufsz, i, start;
2810 bufsz = sizeof(buf) / sizeof(buf[0]);
2812 /* Read a chunk at the pointer location */
2814 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2816 DEBUGOUT("Failed to read EEPROM image\n");
2821 if (buffer_size < ptr)
2822 return IXGBE_ERR_PARAM;
2823 local_buffer = &buffer[ptr];
2831 length = local_buffer[0];
2833 /* Skip pointer section if length is invalid. */
2834 if (length == 0xFFFF || length == 0 ||
2835 (ptr + length) >= hw->eeprom.word_size)
2836 return IXGBE_SUCCESS;
2839 if (buffer && ((u32)start + (u32)length > buffer_size))
2840 return IXGBE_ERR_PARAM;
2842 for (i = start; length; i++, length--) {
2843 if (i == bufsz && !buffer) {
2849 /* Read a chunk at the pointer location */
2850 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2853 DEBUGOUT("Failed to read EEPROM image\n");
2857 *csum += local_buffer[i];
2859 return IXGBE_SUCCESS;
2863 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2864 * @hw: pointer to hardware structure
2865 * @buffer: pointer to buffer containing calculated checksum
2866 * @buffer_size: size of buffer
2868 * Returns a negative error code on error, or the 16-bit checksum
2870 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2872 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2876 u16 pointer, i, size;
2878 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2880 hw->eeprom.ops.init_params(hw);
2883 /* Read pointer area */
2884 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2885 IXGBE_EEPROM_LAST_WORD + 1,
2888 DEBUGOUT("Failed to read EEPROM image\n");
2891 local_buffer = eeprom_ptrs;
2893 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2894 return IXGBE_ERR_PARAM;
2895 local_buffer = buffer;
2899 * For X550 hardware include 0x0-0x41 in the checksum, skip the
2900 * checksum word itself
2902 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2903 if (i != IXGBE_EEPROM_CHECKSUM)
2904 checksum += local_buffer[i];
2907 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
2908 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2910 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2911 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2914 pointer = local_buffer[i];
2916 /* Skip pointer section if the pointer is invalid. */
2917 if (pointer == 0xFFFF || pointer == 0 ||
2918 pointer >= hw->eeprom.word_size)
2922 case IXGBE_PCIE_GENERAL_PTR:
2923 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2925 case IXGBE_PCIE_CONFIG0_PTR:
2926 case IXGBE_PCIE_CONFIG1_PTR:
2927 size = IXGBE_PCIE_CONFIG_SIZE;
2934 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2935 buffer, buffer_size);
2940 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2942 return (s32)checksum;
2946 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2947 * @hw: pointer to hardware structure
2949 * Returns a negative error code on error, or the 16-bit checksum
2951 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2953 return ixgbe_calc_checksum_X550(hw, NULL, 0);
2957 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2958 * @hw: pointer to hardware structure
2959 * @checksum_val: calculated checksum
2961 * Performs checksum calculation and validates the EEPROM checksum. If the
2962 * caller does not need checksum_val, the value can be NULL.
2964 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2968 u16 read_checksum = 0;
2970 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2972 /* Read the first word from the EEPROM. If this times out or fails, do
2973 * not continue or we could be in for a very long wait while every
2976 status = hw->eeprom.ops.read(hw, 0, &checksum);
2978 DEBUGOUT("EEPROM read failed\n");
2982 status = hw->eeprom.ops.calc_checksum(hw);
2986 checksum = (u16)(status & 0xffff);
2988 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2993 /* Verify read checksum from EEPROM is the same as
2994 * calculated checksum
2996 if (read_checksum != checksum) {
2997 status = IXGBE_ERR_EEPROM_CHECKSUM;
2998 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2999 "Invalid EEPROM checksum");
3002 /* If the user cares, return the calculated checksum */
3004 *checksum_val = checksum;
3010 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3011 * @hw: pointer to hardware structure
3013 * After writing EEPROM to shadow RAM using EEWR register, software calculates
3014 * checksum and updates the EEPROM and instructs the hardware to update
3017 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3022 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3024 /* Read the first word from the EEPROM. If this times out or fails, do
3025 * not continue or we could be in for a very long wait while every
3028 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3030 DEBUGOUT("EEPROM read failed\n");
3034 status = ixgbe_calc_eeprom_checksum_X550(hw);
3038 checksum = (u16)(status & 0xffff);
3040 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3045 status = ixgbe_update_flash_X550(hw);
3051 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3052 * @hw: pointer to hardware structure
3054 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3056 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3058 s32 status = IXGBE_SUCCESS;
3059 union ixgbe_hic_hdr2 buffer;
3061 DEBUGFUNC("ixgbe_update_flash_X550");
3063 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3064 buffer.req.buf_lenh = 0;
3065 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3066 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3068 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3070 IXGBE_HI_COMMAND_TIMEOUT, false);
3076 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3077 * @hw: pointer to hardware structure
3079 * Determines physical layer capabilities of the current configuration.
3081 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3083 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3084 u16 ext_ability = 0;
3086 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3088 hw->phy.ops.identify(hw);
3090 switch (hw->phy.type) {
3091 case ixgbe_phy_x550em_kr:
3092 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3093 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3095 case ixgbe_phy_x550em_kx4:
3096 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3097 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3099 case ixgbe_phy_x550em_ext_t:
3100 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3101 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3103 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3104 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3105 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3106 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3112 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3113 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3115 return physical_layer;
3119 * ixgbe_get_bus_info_x550em - Set PCI bus info
3120 * @hw: pointer to hardware structure
3122 * Sets bus link width and speed to unknown because X550em is
3125 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3128 DEBUGFUNC("ixgbe_get_bus_info_x550em");
3130 hw->bus.width = ixgbe_bus_width_unknown;
3131 hw->bus.speed = ixgbe_bus_speed_unknown;
3133 hw->mac.ops.set_lan_id(hw);
3135 return IXGBE_SUCCESS;
3139 * ixgbe_disable_rx_x550 - Disable RX unit
3141 * Enables the Rx DMA unit for x550
3143 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3145 u32 rxctrl, pfdtxgswc;
3147 struct ixgbe_hic_disable_rxen fw_cmd;
3149 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3151 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3152 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3153 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3154 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3155 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3156 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3157 hw->mac.set_lben = true;
3159 hw->mac.set_lben = false;
3162 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3163 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3164 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3165 fw_cmd.port_number = (u8)hw->bus.lan_id;
3167 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3168 sizeof(struct ixgbe_hic_disable_rxen),
3169 IXGBE_HI_COMMAND_TIMEOUT, true);
3171 /* If we fail - disable RX using register write */
3173 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3174 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3175 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3176 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3183 * ixgbe_enter_lplu_x550em - Transition to low power states
3184 * @hw: pointer to hardware structure
3186 * Configures Low Power Link Up on transition to low power states
3187 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3188 * X557 PHY immediately prior to entering LPLU.
3190 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3192 u16 an_10g_cntl_reg, autoneg_reg, speed;
3194 ixgbe_link_speed lcd_speed;
3198 /* SW LPLU not required on later HW revisions. */
3199 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3200 (IXGBE_FUSES0_REV_MASK &
3201 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3202 return IXGBE_SUCCESS;
3204 /* If blocked by MNG FW, then don't restart AN */
3205 if (ixgbe_check_reset_blocked(hw))
3206 return IXGBE_SUCCESS;
3208 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3209 if (status != IXGBE_SUCCESS)
3212 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3214 if (status != IXGBE_SUCCESS)
3217 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3218 * disabled, then force link down by entering low power mode.
3220 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3221 !(hw->wol_enabled || ixgbe_mng_present(hw)))
3222 return ixgbe_set_copper_phy_power(hw, FALSE);
3225 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3227 if (status != IXGBE_SUCCESS)
3230 /* If no valid LCD link speed, then force link down and exit. */
3231 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3232 return ixgbe_set_copper_phy_power(hw, FALSE);
3234 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3235 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3238 if (status != IXGBE_SUCCESS)
3241 /* If no link now, speed is invalid so take link down */
3242 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3243 if (status != IXGBE_SUCCESS)
3244 return ixgbe_set_copper_phy_power(hw, false);
3246 /* clear everything but the speed bits */
3247 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3249 /* If current speed is already LCD, then exit. */
3250 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3251 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3252 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3253 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3256 /* Clear AN completed indication */
3257 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3258 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3261 if (status != IXGBE_SUCCESS)
3264 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3265 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3268 if (status != IXGBE_SUCCESS)
3271 status = hw->phy.ops.read_reg(hw,
3272 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3273 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3276 if (status != IXGBE_SUCCESS)
3279 save_autoneg = hw->phy.autoneg_advertised;
3281 /* Setup link at least common link speed */
3282 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3284 /* restore autoneg from before setting lplu speed */
3285 hw->phy.autoneg_advertised = save_autoneg;
3291 * ixgbe_get_lcd_x550em - Determine lowest common denominator
3292 * @hw: pointer to hardware structure
3293 * @lcd_speed: pointer to lowest common link speed
3295 * Determine lowest common link speed with link partner.
3297 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3301 u16 word = hw->eeprom.ctrl_word_3;
3303 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3305 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3306 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3309 if (status != IXGBE_SUCCESS)
3312 /* If link partner advertised 1G, return 1G */
3313 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3314 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3318 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3319 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3320 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3323 /* Link partner not capable of lower speeds, return 10G */
3324 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3329 * ixgbe_setup_fc_X550em - Set up flow control
3330 * @hw: pointer to hardware structure
3332 * Called at init time to set up flow control.
3334 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3336 s32 ret_val = IXGBE_SUCCESS;
3337 u32 pause, asm_dir, reg_val;
3339 DEBUGFUNC("ixgbe_setup_fc_X550em");
3341 /* Validate the requested mode */
3342 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3343 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3344 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3345 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3349 /* 10gig parts do not have a word in the EEPROM to determine the
3350 * default flow control setting, so we explicitly set it to full.
3352 if (hw->fc.requested_mode == ixgbe_fc_default)
3353 hw->fc.requested_mode = ixgbe_fc_full;
3355 /* Determine PAUSE and ASM_DIR bits. */
3356 switch (hw->fc.requested_mode) {
3361 case ixgbe_fc_tx_pause:
3365 case ixgbe_fc_rx_pause:
3366 /* Rx Flow control is enabled and Tx Flow control is
3367 * disabled by software override. Since there really
3368 * isn't a way to advertise that we are capable of RX
3369 * Pause ONLY, we will advertise that we support both
3370 * symmetric and asymmetric Rx PAUSE, as such we fall
3371 * through to the fc_full statement. Later, we will
3372 * disable the adapter's ability to send PAUSE frames.
3379 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3380 "Flow control param set incorrectly\n");
3381 ret_val = IXGBE_ERR_CONFIG;
3385 switch (hw->device_id) {
3386 case IXGBE_DEV_ID_X550EM_X_KR:
3387 case IXGBE_DEV_ID_X550EM_A_KR:
3388 case IXGBE_DEV_ID_X550EM_A_KR_L:
3389 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
3390 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3391 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3392 if (ret_val != IXGBE_SUCCESS)
3394 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3395 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3397 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3399 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3400 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
3401 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3402 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3404 /* This device does not fully support AN. */
3405 hw->fc.disable_fc_autoneg = true;
3416 * ixgbe_set_mux - Set mux for port 1 access with CS4227
3417 * @hw: pointer to hardware structure
3418 * @state: set mux if 1, clear if 0
3420 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
3424 if (!hw->bus.lan_id)
3426 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3428 esdp |= IXGBE_ESDP_SDP1;
3430 esdp &= ~IXGBE_ESDP_SDP1;
3431 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
3432 IXGBE_WRITE_FLUSH(hw);
3436 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
3437 * @hw: pointer to hardware structure
3438 * @mask: Mask to specify which semaphore to acquire
3440 * Acquires the SWFW semaphore and sets the I2C MUX
3442 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3446 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
3448 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
3452 if (mask & IXGBE_GSSR_I2C_MASK)
3453 ixgbe_set_mux(hw, 1);
3455 return IXGBE_SUCCESS;
3459 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
3460 * @hw: pointer to hardware structure
3461 * @mask: Mask to specify which semaphore to release
3463 * Releases the SWFW semaphore and sets the I2C MUX
3465 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3467 DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
3469 if (mask & IXGBE_GSSR_I2C_MASK)
3470 ixgbe_set_mux(hw, 0);
3472 ixgbe_release_swfw_sync_X540(hw, mask);
3476 * ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
3477 * @hw: pointer to hardware structure
3478 * @mask: Mask to specify which semaphore to acquire
3480 * Acquires the SWFW semaphore and get the shared phy token as needed
3482 static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
3484 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3485 int retries = FW_PHY_TOKEN_RETRIES;
3486 s32 status = IXGBE_SUCCESS;
3488 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
3492 status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
3495 if (!(mask & IXGBE_GSSR_TOKEN_SM))
3497 status = ixgbe_get_phy_token(hw);
3498 if (status != IXGBE_ERR_TOKEN_RETRY)
3501 ixgbe_release_swfw_sync_X540(hw, hmask);
3502 msec_delay(FW_PHY_TOKEN_DELAY);
3509 * ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
3510 * @hw: pointer to hardware structure
3511 * @mask: Mask to specify which semaphore to release
3513 * Releases the SWFW semaphore and puts the shared phy token as needed
3515 static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
3517 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3519 DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
3521 if (mask & IXGBE_GSSR_TOKEN_SM)
3522 ixgbe_put_phy_token(hw);
3525 ixgbe_release_swfw_sync_X540(hw, hmask);
3529 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
3530 * @hw: pointer to hardware structure
3532 * Handle external Base T PHY interrupt. If high temperature
3533 * failure alarm then return error, else if link status change
3534 * then setup internal/external PHY link
3536 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
3537 * failure alarm, else return PHY access status.
3539 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
3544 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
3546 if (status != IXGBE_SUCCESS)
3550 return ixgbe_setup_internal_phy(hw);
3552 return IXGBE_SUCCESS;
3556 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
3557 * @hw: pointer to hardware structure
3558 * @speed: new link speed
3559 * @autoneg_wait_to_complete: true when waiting for completion is needed
3561 * Setup internal/external PHY link speed based on link speed, then set
3562 * external PHY auto advertised link speed.
3564 * Returns error status for any failure
3566 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
3567 ixgbe_link_speed speed,
3568 bool autoneg_wait_to_complete)
3571 ixgbe_link_speed force_speed;
3573 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
3575 /* Setup internal/external PHY link speed to iXFI (10G), unless
3576 * only 1G is auto advertised then setup KX link.
3578 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
3579 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3581 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3583 /* If internal link mode is XFI, then setup XFI internal link. */
3584 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3585 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
3587 if (status != IXGBE_SUCCESS)
3591 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
3595 * ixgbe_check_link_t_X550em - Determine link and speed status
3596 * @hw: pointer to hardware structure
3597 * @speed: pointer to link speed
3598 * @link_up: true when link is up
3599 * @link_up_wait_to_complete: bool used to wait for link up or not
3601 * Check that both the MAC and X557 external PHY have link.
3603 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3604 bool *link_up, bool link_up_wait_to_complete)
3609 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3610 return IXGBE_ERR_CONFIG;
3612 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
3613 link_up_wait_to_complete);
3615 /* If check link fails or MAC link is not up, then return */
3616 if (status != IXGBE_SUCCESS || !(*link_up))
3619 /* MAC link is up, so check external PHY link.
3620 * Read this twice back to back to indicate current status.
3622 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3623 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3626 if (status != IXGBE_SUCCESS)
3629 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3630 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3633 if (status != IXGBE_SUCCESS)
3636 /* If external PHY link is not up, then indicate link not up */
3637 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
3640 return IXGBE_SUCCESS;
3644 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
3645 * @hw: pointer to hardware structure
3647 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
3651 status = ixgbe_reset_phy_generic(hw);
3653 if (status != IXGBE_SUCCESS)
3656 /* Configure Link Status Alarm and Temperature Threshold interrupts */
3657 return ixgbe_enable_lasi_ext_t_x550em(hw);
3661 * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
3662 * @hw: pointer to hardware structure
3663 * @led_idx: led number to turn on
3665 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3669 DEBUGFUNC("ixgbe_led_on_t_X550em");
3671 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3672 return IXGBE_ERR_PARAM;
3674 /* To turn on the LED, set mode to ON. */
3675 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3676 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3677 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
3678 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3679 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3681 return IXGBE_SUCCESS;
3685 * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
3686 * @hw: pointer to hardware structure
3687 * @led_idx: led number to turn off
3689 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3693 DEBUGFUNC("ixgbe_led_off_t_X550em");
3695 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3696 return IXGBE_ERR_PARAM;
3698 /* To turn on the LED, set mode to ON. */
3699 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3700 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3701 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
3702 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3703 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3705 return IXGBE_SUCCESS;