1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
43 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
44 * @hw: pointer to hardware structure
46 * Initialize the function pointers and assign the MAC type for X550.
47 * Does not touch the hardware.
49 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
51 struct ixgbe_mac_info *mac = &hw->mac;
52 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
55 DEBUGFUNC("ixgbe_init_ops_X550");
57 ret_val = ixgbe_init_ops_X540(hw);
58 mac->ops.dmac_config = ixgbe_dmac_config_X550;
59 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
60 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
61 mac->ops.setup_eee = ixgbe_setup_eee_X550;
62 mac->ops.set_source_address_pruning =
63 ixgbe_set_source_address_pruning_X550;
64 mac->ops.set_ethertype_anti_spoofing =
65 ixgbe_set_ethertype_anti_spoofing_X550;
67 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
68 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
69 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
70 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
71 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
72 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
73 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
74 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
75 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
77 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
78 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
79 mac->ops.mdd_event = ixgbe_mdd_event_X550;
80 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
81 mac->ops.disable_rx = ixgbe_disable_rx_x550;
86 * ixgbe_read_cs4227 - Read CS4227 register
87 * @hw: pointer to hardware structure
88 * @reg: register number to write
89 * @value: pointer to receive value read
93 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
95 return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
99 * ixgbe_write_cs4227 - Write CS4227 register
100 * @hw: pointer to hardware structure
101 * @reg: register number to write
102 * @value: value to write to register
104 * Returns status code
106 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
108 return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
112 * ixgbe_get_cs4227_status - Return CS4227 status
113 * @hw: pointer to hardware structure
115 * Returns error if CS4227 not successfully initialized
117 STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
123 for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) {
124 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB,
126 if (status != IXGBE_SUCCESS)
128 if (value == IXGBE_CS4227_GLOBAL_ID_VALUE)
130 msec_delay(IXGBE_CS4227_CHECK_DELAY);
132 if (value != IXGBE_CS4227_GLOBAL_ID_VALUE)
133 return IXGBE_ERR_PHY;
135 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
136 IXGBE_CS4227_SCRATCH_VALUE);
137 if (status != IXGBE_SUCCESS)
139 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
140 if (status != IXGBE_SUCCESS)
142 if (value != IXGBE_CS4227_SCRATCH_VALUE)
143 return IXGBE_ERR_PHY;
144 return IXGBE_SUCCESS;
148 * ixgbe_read_pe - Read register from port expander
149 * @hw: pointer to hardware structure
150 * @reg: register number to read
151 * @value: pointer to receive read value
153 * Returns status code
155 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
159 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
160 if (status != IXGBE_SUCCESS)
161 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
162 "port expander access failed with %d\n", status);
167 * ixgbe_write_pe - Write register to port expander
168 * @hw: pointer to hardware structure
169 * @reg: register number to write
170 * @value: value to write
172 * Returns status code
174 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
178 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
179 if (status != IXGBE_SUCCESS)
180 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
181 "port expander access failed with %d\n", status);
186 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
187 * @hw: pointer to hardware structure
191 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
196 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
197 if (status != IXGBE_SUCCESS)
199 reg |= IXGBE_PE_BIT1;
200 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
201 if (status != IXGBE_SUCCESS)
204 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
205 if (status != IXGBE_SUCCESS)
207 reg &= ~IXGBE_PE_BIT1;
208 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
209 if (status != IXGBE_SUCCESS)
212 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
213 if (status != IXGBE_SUCCESS)
215 reg &= ~IXGBE_PE_BIT1;
216 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
217 if (status != IXGBE_SUCCESS)
220 usec_delay(IXGBE_CS4227_RESET_HOLD);
222 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
223 if (status != IXGBE_SUCCESS)
225 reg |= IXGBE_PE_BIT1;
226 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
227 if (status != IXGBE_SUCCESS)
230 msec_delay(IXGBE_CS4227_RESET_DELAY);
232 return IXGBE_SUCCESS;
236 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
237 * @hw: pointer to hardware structure
239 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
241 u32 swfw_mask = hw->phy.phy_semaphore_mask;
245 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
246 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
247 if (status != IXGBE_SUCCESS) {
248 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
249 "semaphore failed with %d\n", status);
252 status = ixgbe_get_cs4227_status(hw);
253 if (status == IXGBE_SUCCESS) {
254 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
255 msec_delay(hw->eeprom.semaphore_delay);
258 ixgbe_reset_cs4227(hw);
259 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
260 msec_delay(hw->eeprom.semaphore_delay);
262 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
263 "Unable to initialize CS4227, err=%d\n", status);
267 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
268 * @hw: pointer to hardware structure
270 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
272 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
274 if (hw->bus.lan_id) {
275 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
276 esdp |= IXGBE_ESDP_SDP1_DIR;
278 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
279 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
280 IXGBE_WRITE_FLUSH(hw);
284 * ixgbe_identify_phy_x550em - Get PHY type based on device id
285 * @hw: pointer to hardware structure
289 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
291 switch (hw->device_id) {
292 case IXGBE_DEV_ID_X550EM_X_SFP:
293 /* set up for CS4227 usage */
294 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
295 ixgbe_setup_mux_ctl(hw);
296 ixgbe_check_cs4227(hw);
298 return ixgbe_identify_module_generic(hw);
300 case IXGBE_DEV_ID_X550EM_X_KX4:
301 hw->phy.type = ixgbe_phy_x550em_kx4;
303 case IXGBE_DEV_ID_X550EM_X_KR:
304 hw->phy.type = ixgbe_phy_x550em_kr;
306 case IXGBE_DEV_ID_X550EM_X_1G_T:
307 case IXGBE_DEV_ID_X550EM_X_10G_T:
308 return ixgbe_identify_phy_generic(hw);
312 return IXGBE_SUCCESS;
315 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
316 u32 device_type, u16 *phy_data)
318 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
319 return IXGBE_NOT_IMPLEMENTED;
322 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
323 u32 device_type, u16 phy_data)
325 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
326 return IXGBE_NOT_IMPLEMENTED;
330 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
331 * @hw: pointer to hardware structure
333 * Initialize the function pointers and for MAC type X550EM.
334 * Does not touch the hardware.
336 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
338 struct ixgbe_mac_info *mac = &hw->mac;
339 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
340 struct ixgbe_phy_info *phy = &hw->phy;
343 DEBUGFUNC("ixgbe_init_ops_X550EM");
345 /* Similar to X550 so start there. */
346 ret_val = ixgbe_init_ops_X550(hw);
348 /* Since this function eventually calls
349 * ixgbe_init_ops_540 by design, we are setting
350 * the pointers to NULL explicitly here to overwrite
351 * the values being set in the x540 function.
353 /* Thermal sensor not supported in x550EM */
354 mac->ops.get_thermal_sensor_data = NULL;
355 mac->ops.init_thermal_sensor_thresh = NULL;
356 mac->thermal_sensor_enabled = false;
358 /* FCOE not supported in x550EM */
359 mac->ops.get_san_mac_addr = NULL;
360 mac->ops.set_san_mac_addr = NULL;
361 mac->ops.get_wwn_prefix = NULL;
362 mac->ops.get_fcoe_boot_status = NULL;
364 /* IPsec not supported in x550EM */
365 mac->ops.disable_sec_rx_path = NULL;
366 mac->ops.enable_sec_rx_path = NULL;
368 /* X550EM bus type is internal*/
369 hw->bus.type = ixgbe_bus_type_internal;
370 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
372 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
373 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
374 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
375 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
376 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
377 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
378 mac->ops.get_supported_physical_layer =
379 ixgbe_get_supported_physical_layer_X550em;
382 phy->ops.init = ixgbe_init_phy_ops_X550em;
383 phy->ops.identify = ixgbe_identify_phy_x550em;
384 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
385 phy->ops.set_phy_power = NULL;
389 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
390 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
391 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
392 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
393 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
394 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
395 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
396 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
402 * ixgbe_dmac_config_X550
403 * @hw: pointer to hardware structure
405 * Configure DMA coalescing. If enabling dmac, dmac is activated.
406 * When disabling dmac, dmac enable dmac bit is cleared.
408 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
410 u32 reg, high_pri_tc;
412 DEBUGFUNC("ixgbe_dmac_config_X550");
414 /* Disable DMA coalescing before configuring */
415 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
416 reg &= ~IXGBE_DMACR_DMAC_EN;
417 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
419 /* Disable DMA Coalescing if the watchdog timer is 0 */
420 if (!hw->mac.dmac_config.watchdog_timer)
423 ixgbe_dmac_config_tcs_X550(hw);
425 /* Configure DMA Coalescing Control Register */
426 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
428 /* Set the watchdog timer in units of 40.96 usec */
429 reg &= ~IXGBE_DMACR_DMACWT_MASK;
430 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
432 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
433 /* If fcoe is enabled, set high priority traffic class */
434 if (hw->mac.dmac_config.fcoe_en) {
435 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
436 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
437 IXGBE_DMACR_HIGH_PRI_TC_MASK);
439 reg |= IXGBE_DMACR_EN_MNG_IND;
441 /* Enable DMA coalescing after configuration */
442 reg |= IXGBE_DMACR_DMAC_EN;
443 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
446 return IXGBE_SUCCESS;
450 * ixgbe_dmac_config_tcs_X550
451 * @hw: pointer to hardware structure
453 * Configure DMA coalescing threshold per TC. The dmac enable bit must
454 * be cleared before configuring.
456 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
458 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
460 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
462 /* Configure DMA coalescing enabled */
463 switch (hw->mac.dmac_config.link_speed) {
464 case IXGBE_LINK_SPEED_100_FULL:
465 pb_headroom = IXGBE_DMACRXT_100M;
467 case IXGBE_LINK_SPEED_1GB_FULL:
468 pb_headroom = IXGBE_DMACRXT_1G;
471 pb_headroom = IXGBE_DMACRXT_10G;
475 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
476 IXGBE_MHADD_MFS_SHIFT) / 1024);
478 /* Set the per Rx packet buffer receive threshold */
479 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
480 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
481 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
483 if (tc < hw->mac.dmac_config.num_tcs) {
485 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
486 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
487 IXGBE_RXPBSIZE_SHIFT;
489 /* Calculate receive buffer threshold in kilobytes */
490 if (rx_pb_size > pb_headroom)
491 rx_pb_size = rx_pb_size - pb_headroom;
495 /* Minimum of MFS shall be set for DMCTH */
496 reg |= (rx_pb_size > maxframe_size_kb) ?
497 rx_pb_size : maxframe_size_kb;
499 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
501 return IXGBE_SUCCESS;
505 * ixgbe_dmac_update_tcs_X550
506 * @hw: pointer to hardware structure
508 * Disables dmac, updates per TC settings, and then enables dmac.
510 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
514 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
516 /* Disable DMA coalescing before configuring */
517 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
518 reg &= ~IXGBE_DMACR_DMAC_EN;
519 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
521 ixgbe_dmac_config_tcs_X550(hw);
523 /* Enable DMA coalescing after configuration */
524 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
525 reg |= IXGBE_DMACR_DMAC_EN;
526 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
528 return IXGBE_SUCCESS;
532 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
533 * @hw: pointer to hardware structure
535 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
536 * ixgbe_hw struct in order to set up EEPROM access.
538 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
540 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
544 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
546 if (eeprom->type == ixgbe_eeprom_uninitialized) {
547 eeprom->semaphore_delay = 10;
548 eeprom->type = ixgbe_flash;
550 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
551 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
552 IXGBE_EEC_SIZE_SHIFT);
553 eeprom->word_size = 1 << (eeprom_size +
554 IXGBE_EEPROM_WORD_SIZE_SHIFT);
556 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
557 eeprom->type, eeprom->word_size);
560 return IXGBE_SUCCESS;
564 * ixgbe_setup_eee_X550 - Enable/disable EEE support
565 * @hw: pointer to the HW structure
566 * @enable_eee: boolean flag to enable EEE
568 * Enable/disable EEE based on enable_eee flag.
569 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
573 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
580 DEBUGFUNC("ixgbe_setup_eee_X550");
582 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
583 /* Enable or disable EEE per flag */
585 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
587 if (hw->device_id == IXGBE_DEV_ID_X550T) {
588 /* Advertise EEE capability */
589 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
590 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
592 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
593 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
594 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
596 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
597 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
598 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
599 status = ixgbe_read_iosf_sb_reg_x550(hw,
600 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
601 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
602 if (status != IXGBE_SUCCESS)
605 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
606 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
608 status = ixgbe_write_iosf_sb_reg_x550(hw,
609 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
610 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
611 if (status != IXGBE_SUCCESS)
615 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
617 if (hw->device_id == IXGBE_DEV_ID_X550T) {
618 /* Disable advertised EEE capability */
619 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
620 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
622 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
623 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
624 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
626 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
627 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
628 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
629 status = ixgbe_read_iosf_sb_reg_x550(hw,
630 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
631 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
632 if (status != IXGBE_SUCCESS)
635 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
636 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
638 status = ixgbe_write_iosf_sb_reg_x550(hw,
639 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
640 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
641 if (status != IXGBE_SUCCESS)
645 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
647 return IXGBE_SUCCESS;
651 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
652 * @hw: pointer to hardware structure
653 * @enable: enable or disable source address pruning
654 * @pool: Rx pool to set source address pruning for
656 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
661 /* max rx pool is 63 */
665 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
666 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
669 pfflp |= (1ULL << pool);
671 pfflp &= ~(1ULL << pool);
673 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
674 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
678 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
679 * @hw: pointer to hardware structure
680 * @enable: enable or disable switch for Ethertype anti-spoofing
681 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
684 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
687 int vf_target_reg = vf >> 3;
688 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
691 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
693 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
695 pfvfspoof |= (1 << vf_target_shift);
697 pfvfspoof &= ~(1 << vf_target_shift);
699 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
703 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
705 * @hw: pointer to hardware structure
706 * @reg_addr: 32 bit PHY register to write
707 * @device_type: 3 bit device type
708 * @data: Data to write to the register
710 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
711 u32 device_type, u32 data)
713 u32 i, command, error;
715 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
716 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
718 /* Write IOSF control register */
719 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
721 /* Write IOSF data register */
722 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
724 * Check every 10 usec to see if the address cycle completed.
725 * The SB IOSF BUSY bit will clear when the operation is
728 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
731 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
732 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
736 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
737 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
738 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
739 ERROR_REPORT2(IXGBE_ERROR_POLLING,
740 "Failed to write, error %x\n", error);
741 return IXGBE_ERR_PHY;
744 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
745 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Write timed out\n");
746 return IXGBE_ERR_PHY;
749 return IXGBE_SUCCESS;
753 * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
755 * @hw: pointer to hardware structure
756 * @reg_addr: 32 bit PHY register to write
757 * @device_type: 3 bit device type
758 * @phy_data: Pointer to read data from the register
760 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
761 u32 device_type, u32 *data)
763 u32 i, command, error;
765 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
766 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
768 /* Write IOSF control register */
769 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
772 * Check every 10 usec to see if the address cycle completed.
773 * The SB IOSF BUSY bit will clear when the operation is
776 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
779 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
780 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
784 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
785 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
786 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
787 ERROR_REPORT2(IXGBE_ERROR_POLLING,
788 "Failed to read, error %x\n", error);
789 return IXGBE_ERR_PHY;
792 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
793 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Read timed out\n");
794 return IXGBE_ERR_PHY;
797 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
799 return IXGBE_SUCCESS;
803 * ixgbe_disable_mdd_X550
804 * @hw: pointer to hardware structure
806 * Disable malicious driver detection
808 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
812 DEBUGFUNC("ixgbe_disable_mdd_X550");
814 /* Disable MDD for TX DMA and interrupt */
815 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
816 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
817 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
819 /* Disable MDD for RX and interrupt */
820 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
821 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
822 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
826 * ixgbe_enable_mdd_X550
827 * @hw: pointer to hardware structure
829 * Enable malicious driver detection
831 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
835 DEBUGFUNC("ixgbe_enable_mdd_X550");
837 /* Enable MDD for TX DMA and interrupt */
838 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
839 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
840 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
842 /* Enable MDD for RX and interrupt */
843 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
844 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
845 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
849 * ixgbe_restore_mdd_vf_X550
850 * @hw: pointer to hardware structure
853 * Restore VF that was disabled during malicious driver detection event
855 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
857 u32 idx, reg, num_qs, start_q, bitmask;
859 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
861 /* Map VF to queues */
862 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
863 switch (reg & IXGBE_MRQC_MRQE_MASK) {
864 case IXGBE_MRQC_VMDQRT8TCEN:
865 num_qs = 8; /* 16 VFs / pools */
866 bitmask = 0x000000FF;
868 case IXGBE_MRQC_VMDQRSS32EN:
869 case IXGBE_MRQC_VMDQRT4TCEN:
870 num_qs = 4; /* 32 VFs / pools */
871 bitmask = 0x0000000F;
873 default: /* 64 VFs / pools */
875 bitmask = 0x00000003;
878 start_q = vf * num_qs;
880 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
883 reg |= (bitmask << (start_q % 32));
884 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
885 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
889 * ixgbe_mdd_event_X550
890 * @hw: pointer to hardware structure
891 * @vf_bitmap: vf bitmap of malicious vfs
893 * Handle malicious driver detection event.
895 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
898 u32 i, j, reg, q, shift, vf, idx;
900 DEBUGFUNC("ixgbe_mdd_event_X550");
902 /* figure out pool size for mapping to vf's */
903 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
904 switch (reg & IXGBE_MRQC_MRQE_MASK) {
905 case IXGBE_MRQC_VMDQRT8TCEN:
906 shift = 3; /* 16 VFs / pools */
908 case IXGBE_MRQC_VMDQRSS32EN:
909 case IXGBE_MRQC_VMDQRT4TCEN:
910 shift = 2; /* 32 VFs / pools */
913 shift = 1; /* 64 VFs / pools */
917 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
918 for (i = 0; i < 4; i++) {
919 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
920 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
925 /* Get malicious queue */
926 for (j = 0; j < 32 && wqbr; j++) {
928 if (!(wqbr & (1 << j)))
931 /* Get queue from bitmask */
934 /* Map queue to vf */
937 /* Set vf bit in vf_bitmap */
939 vf_bitmap[idx] |= (1 << (vf % 32));
946 * ixgbe_get_media_type_X550em - Get media type
947 * @hw: pointer to hardware structure
949 * Returns the media type (fiber, copper, backplane)
951 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
953 enum ixgbe_media_type media_type;
955 DEBUGFUNC("ixgbe_get_media_type_X550em");
957 /* Detect if there is a copper PHY attached. */
958 switch (hw->device_id) {
959 case IXGBE_DEV_ID_X550EM_X_KR:
960 case IXGBE_DEV_ID_X550EM_X_KX4:
961 media_type = ixgbe_media_type_backplane;
963 case IXGBE_DEV_ID_X550EM_X_SFP:
964 media_type = ixgbe_media_type_fiber;
966 case IXGBE_DEV_ID_X550EM_X_1G_T:
967 case IXGBE_DEV_ID_X550EM_X_10G_T:
968 media_type = ixgbe_media_type_copper;
971 media_type = ixgbe_media_type_unknown;
978 * ixgbe_setup_sfp_modules_X550em - Setup SFP module
979 * @hw: pointer to hardware structure
981 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
984 u16 reg_slice, edc_mode;
987 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
989 switch (hw->phy.sfp_type) {
990 case ixgbe_sfp_type_unknown:
991 return IXGBE_SUCCESS;
992 case ixgbe_sfp_type_not_present:
993 return IXGBE_ERR_SFP_NOT_PRESENT;
994 case ixgbe_sfp_type_da_cu_core0:
995 case ixgbe_sfp_type_da_cu_core1:
998 case ixgbe_sfp_type_srlr_core0:
999 case ixgbe_sfp_type_srlr_core1:
1000 case ixgbe_sfp_type_da_act_lmt_core0:
1001 case ixgbe_sfp_type_da_act_lmt_core1:
1002 case ixgbe_sfp_type_1g_sx_core0:
1003 case ixgbe_sfp_type_1g_sx_core1:
1004 case ixgbe_sfp_type_1g_lx_core0:
1005 case ixgbe_sfp_type_1g_lx_core1:
1006 setup_linear = false;
1009 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1012 ixgbe_init_mac_link_ops_X550em(hw);
1013 hw->phy.ops.reset = NULL;
1015 /* The CS4227 slice address is the base address + the port-pair reg
1016 * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0.
1018 reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->bus.lan_id << 12);
1021 edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1023 edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1025 /* Configure CS4227 for connection type. */
1026 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1029 if (ret_val != IXGBE_SUCCESS)
1030 ret_val = ixgbe_write_i2c_combined(hw, 0x80, reg_slice,
1037 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1038 * @hw: pointer to hardware structure
1040 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1042 struct ixgbe_mac_info *mac = &hw->mac;
1044 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1046 /* CS4227 does not support autoneg, so disable the laser control
1047 * functions for SFP+ fiber
1049 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1050 mac->ops.disable_tx_laser = NULL;
1051 mac->ops.enable_tx_laser = NULL;
1052 mac->ops.flap_tx_laser = NULL;
1053 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1054 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1055 mac->ops.set_rate_select_speed =
1056 ixgbe_set_soft_rate_select_speed;
1061 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1062 * @hw: pointer to hardware structure
1063 * @speed: pointer to link speed
1064 * @autoneg: true when autoneg or autotry is enabled
1066 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1067 ixgbe_link_speed *speed,
1070 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1073 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1075 /* CS4227 SFP must not enable auto-negotiation */
1078 /* Check if 1G SFP module. */
1079 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1080 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1081 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1082 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1083 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1084 return IXGBE_SUCCESS;
1087 /* Link capabilities are based on SFP */
1088 if (hw->phy.multispeed_fiber)
1089 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1090 IXGBE_LINK_SPEED_1GB_FULL;
1092 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1094 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1095 IXGBE_LINK_SPEED_1GB_FULL;
1099 return IXGBE_SUCCESS;
1103 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1104 * @hw: pointer to hardware structure
1106 * Initialize any function pointers that were not able to be
1107 * set during init_shared_code because the PHY/SFP type was
1108 * not known. Perform the SFP init if necessary.
1110 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1112 struct ixgbe_phy_info *phy = &hw->phy;
1115 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1117 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1118 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1119 ixgbe_setup_mux_ctl(hw);
1122 /* Identify the PHY or SFP module */
1123 ret_val = phy->ops.identify(hw);
1124 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1127 /* Setup function pointers based on detected SFP module and speeds */
1128 ixgbe_init_mac_link_ops_X550em(hw);
1129 if (phy->sfp_type != ixgbe_sfp_type_unknown)
1130 phy->ops.reset = NULL;
1132 /* Set functions pointers based on phy type */
1133 switch (hw->phy.type) {
1134 case ixgbe_phy_x550em_kx4:
1135 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
1136 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1137 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1139 case ixgbe_phy_x550em_kr:
1140 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1141 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1142 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1144 case ixgbe_phy_x550em_ext_t:
1145 phy->ops.setup_internal_link = ixgbe_setup_internal_phy_x550em;
1154 * ixgbe_reset_hw_X550em - Perform hardware reset
1155 * @hw: pointer to hardware structure
1157 * Resets the hardware by resetting the transmit and receive units, masks
1158 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1161 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1163 struct ixgbe_hic_hdr fw_cmd;
1164 ixgbe_link_speed link_speed;
1168 bool link_up = false;
1170 DEBUGFUNC("ixgbe_reset_hw_X550em");
1172 fw_cmd.cmd = FW_PHY_MGMT_REQ_CMD;
1174 fw_cmd.cmd_or_resp.cmd_resv = 0;
1175 fw_cmd.checksum = FW_DEFAULT_CHECKSUM;
1176 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
1178 IXGBE_HI_PHY_MGMT_REQ_TIMEOUT,
1181 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
1182 "PHY mgmt command failed with %d\n", status);
1183 else if (fw_cmd.cmd_or_resp.ret_status != FW_CEM_RESP_STATUS_SUCCESS)
1184 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
1185 "PHY mgmt command returned %d\n",
1186 fw_cmd.cmd_or_resp.ret_status);
1188 /* Call adapter stop to disable Tx/Rx and clear interrupts */
1189 status = hw->mac.ops.stop_adapter(hw);
1190 if (status != IXGBE_SUCCESS)
1193 /* flush pending Tx transactions */
1194 ixgbe_clear_tx_pending(hw);
1196 /* PHY ops must be identified and initialized prior to reset */
1198 /* Identify PHY and related function pointers */
1199 status = hw->phy.ops.init(hw);
1201 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1204 /* start the external PHY */
1205 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1206 status = ixgbe_init_ext_t_x550em(hw);
1211 /* Setup SFP module if there is one present. */
1212 if (hw->phy.sfp_setup_needed) {
1213 status = hw->mac.ops.setup_sfp(hw);
1214 hw->phy.sfp_setup_needed = false;
1217 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1221 if (!hw->phy.reset_disable && hw->phy.ops.reset)
1222 hw->phy.ops.reset(hw);
1225 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
1226 * If link reset is used when link is up, it might reset the PHY when
1227 * mng is using it. If link is down or the flag to force full link
1228 * reset is set, then perform link reset.
1230 ctrl = IXGBE_CTRL_LNK_RST;
1231 if (!hw->force_full_reset) {
1232 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1234 ctrl = IXGBE_CTRL_RST;
1237 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1238 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1239 IXGBE_WRITE_FLUSH(hw);
1241 /* Poll for reset bit to self-clear meaning reset is complete */
1242 for (i = 0; i < 10; i++) {
1244 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1245 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1249 if (ctrl & IXGBE_CTRL_RST_MASK) {
1250 status = IXGBE_ERR_RESET_FAILED;
1251 DEBUGOUT("Reset polling failed to complete.\n");
1256 /* Double resets are required for recovery from certain error
1257 * conditions. Between resets, it is necessary to stall to
1258 * allow time for any pending HW events to complete.
1260 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1261 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1265 /* Store the permanent mac address */
1266 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1268 /* Store MAC address from RAR0, clear receive address registers, and
1269 * clear the multicast table. Also reset num_rar_entries to 128,
1270 * since we modify this value when programming the SAN MAC address.
1272 hw->mac.num_rar_entries = 128;
1273 hw->mac.ops.init_rx_addrs(hw);
1276 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1277 ixgbe_setup_mux_ctl(hw);
1283 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1284 * @hw: pointer to hardware structure
1286 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1292 /* TODO: The number of attempts and delay between attempts is undefined */
1294 /* decrement retries counter and exit if we hit 0 */
1296 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
1297 "External PHY not yet finished resetting.");
1298 return IXGBE_ERR_PHY;
1304 status = hw->phy.ops.read_reg(hw,
1305 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1306 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1309 if (status != IXGBE_SUCCESS)
1312 /* Verify PHY FW reset has completed */
1313 } while ((reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) != 1);
1315 /* Set port to low power mode */
1316 status = hw->phy.ops.read_reg(hw,
1317 IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
1318 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1321 if (status != IXGBE_SUCCESS)
1324 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
1326 status = hw->phy.ops.write_reg(hw,
1327 IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
1328 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1331 if (status != IXGBE_SUCCESS)
1334 /* Enable the transmitter */
1335 status = hw->phy.ops.read_reg(hw,
1336 IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR,
1337 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1340 if (status != IXGBE_SUCCESS)
1343 reg &= ~IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE;
1345 status = hw->phy.ops.write_reg(hw,
1346 IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR,
1347 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1350 if (status != IXGBE_SUCCESS)
1353 /* Un-stall the PHY FW */
1354 status = hw->phy.ops.read_reg(hw,
1355 IXGBE_MDIO_GLOBAL_RES_PR_10,
1356 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1359 if (status != IXGBE_SUCCESS)
1362 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1364 status = hw->phy.ops.write_reg(hw,
1365 IXGBE_MDIO_GLOBAL_RES_PR_10,
1366 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1373 * ixgbe_setup_kr_x550em - Configure the KR PHY.
1374 * @hw: pointer to hardware structure
1376 * Configures the integrated KR PHY.
1378 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1383 status = ixgbe_read_iosf_sb_reg_x550(hw,
1384 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1385 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1389 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1390 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ |
1391 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC);
1392 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1393 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1395 /* Advertise 10G support. */
1396 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1397 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1399 /* Advertise 1G support. */
1400 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1401 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1403 /* Restart auto-negotiation. */
1404 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1405 status = ixgbe_write_iosf_sb_reg_x550(hw,
1406 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1407 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1413 * ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1414 * @hw: pointer to hardware structure
1416 * Configures the integrated KX4 PHY.
1418 s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1423 status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1424 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, ®_val);
1428 reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1429 IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1431 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1433 /* Advertise 10G support. */
1434 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1435 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1437 /* Advertise 1G support. */
1438 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1439 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1441 /* Restart auto-negotiation. */
1442 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1443 status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1444 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, reg_val);
1450 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1451 * @hw: pointer to hardware structure
1452 * @speed: the link speed to force
1454 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
1455 * internal and external PHY at a specific speed, without autonegotiation.
1457 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1462 /* Disable AN and force speed to 10G Serial. */
1463 status = ixgbe_read_iosf_sb_reg_x550(hw,
1464 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1465 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1466 if (status != IXGBE_SUCCESS)
1469 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1470 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1472 /* Select forced link speed for internal PHY. */
1474 case IXGBE_LINK_SPEED_10GB_FULL:
1475 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1477 case IXGBE_LINK_SPEED_1GB_FULL:
1478 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1481 /* Other link speeds are not supported by internal KR PHY. */
1482 return IXGBE_ERR_LINK_SETUP;
1485 status = ixgbe_write_iosf_sb_reg_x550(hw,
1486 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1487 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1488 if (status != IXGBE_SUCCESS)
1491 /* Disable training protocol FSM. */
1492 status = ixgbe_read_iosf_sb_reg_x550(hw,
1493 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1494 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1495 if (status != IXGBE_SUCCESS)
1497 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1498 status = ixgbe_write_iosf_sb_reg_x550(hw,
1499 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1500 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1501 if (status != IXGBE_SUCCESS)
1504 /* Disable Flex from training TXFFE. */
1505 status = ixgbe_read_iosf_sb_reg_x550(hw,
1506 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1507 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1508 if (status != IXGBE_SUCCESS)
1510 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1511 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1512 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1513 status = ixgbe_write_iosf_sb_reg_x550(hw,
1514 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1515 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1516 if (status != IXGBE_SUCCESS)
1518 status = ixgbe_read_iosf_sb_reg_x550(hw,
1519 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1520 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1521 if (status != IXGBE_SUCCESS)
1523 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1524 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1525 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1526 status = ixgbe_write_iosf_sb_reg_x550(hw,
1527 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1528 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1529 if (status != IXGBE_SUCCESS)
1532 /* Enable override for coefficients. */
1533 status = ixgbe_read_iosf_sb_reg_x550(hw,
1534 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1535 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1536 if (status != IXGBE_SUCCESS)
1538 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1539 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1540 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1541 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1542 status = ixgbe_write_iosf_sb_reg_x550(hw,
1543 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1544 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1545 if (status != IXGBE_SUCCESS)
1548 /* Toggle port SW reset by AN reset. */
1549 status = ixgbe_read_iosf_sb_reg_x550(hw,
1550 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1551 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1552 if (status != IXGBE_SUCCESS)
1554 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1555 status = ixgbe_write_iosf_sb_reg_x550(hw,
1556 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1557 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1563 * ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
1564 * @hw: pointer to hardware structure
1566 * Configures the integrated KR PHY for SFP support.
1568 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1569 ixgbe_link_speed speed,
1570 bool autoneg_wait_to_complete)
1572 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1574 return ixgbe_setup_ixfi_x550em(hw, &speed);
1578 * ixgbe_setup_internal_phy_x550em - Configure integrated KR PHY
1579 * @hw: point to hardware structure
1581 * Configures the integrated KR PHY to talk to the external PHY. The base
1582 * driver will call this function when it gets notification via interrupt from
1583 * the external PHY. This function forces the internal PHY into iXFI mode at
1584 * the correct speed.
1586 * A return of a non-zero value indicates an error, and the base driver should
1587 * not report link up.
1589 s32 ixgbe_setup_internal_phy_x550em(struct ixgbe_hw *hw)
1592 u16 lasi, autoneg_status, speed;
1593 ixgbe_link_speed force_speed;
1595 /* Verify that the external link status has changed */
1596 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_XENPAK_LASI_STATUS,
1597 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1599 if (status != IXGBE_SUCCESS)
1602 /* If there was no change in link status, we can just exit */
1603 if (!(lasi & IXGBE_XENPAK_LASI_LINK_STATUS_ALARM))
1604 return IXGBE_SUCCESS;
1606 /* we read this twice back to back to indicate current status */
1607 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1608 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1610 if (status != IXGBE_SUCCESS)
1613 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1614 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1616 if (status != IXGBE_SUCCESS)
1619 /* If link is not up return an error indicating treat link as down */
1620 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1621 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1623 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1624 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1627 /* clear everything but the speed and duplex bits */
1628 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1631 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1632 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1634 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1635 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1638 /* Internal PHY does not support anything else */
1639 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1642 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1646 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1647 * @hw: pointer to hardware structure
1649 * Configures the integrated KR PHY to use internal loopback mode.
1651 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1656 /* Disable AN and force speed to 10G Serial. */
1657 status = ixgbe_read_iosf_sb_reg_x550(hw,
1658 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1659 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1660 if (status != IXGBE_SUCCESS)
1662 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1663 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1664 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1665 status = ixgbe_write_iosf_sb_reg_x550(hw,
1666 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1667 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1668 if (status != IXGBE_SUCCESS)
1671 /* Set near-end loopback clocks. */
1672 status = ixgbe_read_iosf_sb_reg_x550(hw,
1673 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1674 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1675 if (status != IXGBE_SUCCESS)
1677 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1678 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1679 status = ixgbe_write_iosf_sb_reg_x550(hw,
1680 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1681 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1682 if (status != IXGBE_SUCCESS)
1685 /* Set loopback enable. */
1686 status = ixgbe_read_iosf_sb_reg_x550(hw,
1687 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1688 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1689 if (status != IXGBE_SUCCESS)
1691 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1692 status = ixgbe_write_iosf_sb_reg_x550(hw,
1693 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1694 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1695 if (status != IXGBE_SUCCESS)
1698 /* Training bypass. */
1699 status = ixgbe_read_iosf_sb_reg_x550(hw,
1700 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1701 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1702 if (status != IXGBE_SUCCESS)
1704 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
1705 status = ixgbe_write_iosf_sb_reg_x550(hw,
1706 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1707 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1713 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1714 * assuming that the semaphore is already obtained.
1715 * @hw: pointer to hardware structure
1716 * @offset: offset of word in the EEPROM to read
1717 * @data: word read from the EEPROM
1719 * Reads a 16 bit word from the EEPROM using the hostif.
1721 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1725 struct ixgbe_hic_read_shadow_ram buffer;
1727 DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
1728 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1729 buffer.hdr.req.buf_lenh = 0;
1730 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1731 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1733 /* convert offset from words to bytes */
1734 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1736 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1738 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1740 IXGBE_HI_COMMAND_TIMEOUT, false);
1745 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1746 FW_NVM_DATA_OFFSET);
1752 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1753 * @hw: pointer to hardware structure
1754 * @offset: offset of word in the EEPROM to read
1755 * @data: word read from the EEPROM
1757 * Reads a 16 bit word from the EEPROM using the hostif.
1759 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1762 s32 status = IXGBE_SUCCESS;
1764 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
1766 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1768 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
1769 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1771 status = IXGBE_ERR_SWFW_SYNC;
1778 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
1779 * @hw: pointer to hardware structure
1780 * @offset: offset of word in the EEPROM to read
1781 * @words: number of words
1782 * @data: word(s) read from the EEPROM
1784 * Reads a 16 bit word(s) from the EEPROM using the hostif.
1786 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1787 u16 offset, u16 words, u16 *data)
1789 struct ixgbe_hic_read_shadow_ram buffer;
1790 u32 current_word = 0;
1795 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
1797 /* Take semaphore for the entire operation. */
1798 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1800 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
1804 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
1805 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
1807 words_to_read = words;
1809 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1810 buffer.hdr.req.buf_lenh = 0;
1811 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1812 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1814 /* convert offset from words to bytes */
1815 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
1816 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
1818 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1820 IXGBE_HI_COMMAND_TIMEOUT,
1824 DEBUGOUT("Host interface command failed\n");
1828 for (i = 0; i < words_to_read; i++) {
1829 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
1831 u32 value = IXGBE_READ_REG(hw, reg);
1833 data[current_word] = (u16)(value & 0xffff);
1836 if (i < words_to_read) {
1838 data[current_word] = (u16)(value & 0xffff);
1842 words -= words_to_read;
1846 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1851 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1852 * @hw: pointer to hardware structure
1853 * @offset: offset of word in the EEPROM to write
1854 * @data: word write to the EEPROM
1856 * Write a 16 bit word to the EEPROM using the hostif.
1858 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1862 struct ixgbe_hic_write_shadow_ram buffer;
1864 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
1866 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
1867 buffer.hdr.req.buf_lenh = 0;
1868 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
1869 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1872 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1874 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1876 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1878 IXGBE_HI_COMMAND_TIMEOUT, false);
1884 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1885 * @hw: pointer to hardware structure
1886 * @offset: offset of word in the EEPROM to write
1887 * @data: word write to the EEPROM
1889 * Write a 16 bit word to the EEPROM using the hostif.
1891 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1894 s32 status = IXGBE_SUCCESS;
1896 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
1898 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1900 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
1901 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1903 DEBUGOUT("write ee hostif failed to get semaphore");
1904 status = IXGBE_ERR_SWFW_SYNC;
1911 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1912 * @hw: pointer to hardware structure
1913 * @offset: offset of word in the EEPROM to write
1914 * @words: number of words
1915 * @data: word(s) write to the EEPROM
1917 * Write a 16 bit word(s) to the EEPROM using the hostif.
1919 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1920 u16 offset, u16 words, u16 *data)
1922 s32 status = IXGBE_SUCCESS;
1925 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
1927 /* Take semaphore for the entire operation. */
1928 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1929 if (status != IXGBE_SUCCESS) {
1930 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
1934 for (i = 0; i < words; i++) {
1935 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1938 if (status != IXGBE_SUCCESS) {
1939 DEBUGOUT("Eeprom buffered write failed\n");
1944 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1951 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
1952 * @hw: pointer to hardware structure
1953 * @ptr: pointer offset in eeprom
1954 * @size: size of section pointed by ptr, if 0 first word will be used as size
1955 * @csum: address of checksum to update
1957 * Returns error status for any failure
1959 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
1960 u16 size, u16 *csum, u16 *buffer,
1965 u16 length, bufsz, i, start;
1968 bufsz = sizeof(buf) / sizeof(buf[0]);
1970 /* Read a chunk at the pointer location */
1972 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
1974 DEBUGOUT("Failed to read EEPROM image\n");
1979 if (buffer_size < ptr)
1980 return IXGBE_ERR_PARAM;
1981 local_buffer = &buffer[ptr];
1989 length = local_buffer[0];
1991 /* Skip pointer section if length is invalid. */
1992 if (length == 0xFFFF || length == 0 ||
1993 (ptr + length) >= hw->eeprom.word_size)
1994 return IXGBE_SUCCESS;
1997 if (buffer && ((u32)start + (u32)length > buffer_size))
1998 return IXGBE_ERR_PARAM;
2000 for (i = start; length; i++, length--) {
2001 if (i == bufsz && !buffer) {
2007 /* Read a chunk at the pointer location */
2008 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2011 DEBUGOUT("Failed to read EEPROM image\n");
2015 *csum += local_buffer[i];
2017 return IXGBE_SUCCESS;
2021 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2022 * @hw: pointer to hardware structure
2023 * @buffer: pointer to buffer containing calculated checksum
2024 * @buffer_size: size of buffer
2026 * Returns a negative error code on error, or the 16-bit checksum
2028 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2030 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2034 u16 pointer, i, size;
2036 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2038 hw->eeprom.ops.init_params(hw);
2041 /* Read pointer area */
2042 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2043 IXGBE_EEPROM_LAST_WORD + 1,
2046 DEBUGOUT("Failed to read EEPROM image\n");
2049 local_buffer = eeprom_ptrs;
2051 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2052 return IXGBE_ERR_PARAM;
2053 local_buffer = buffer;
2057 * For X550 hardware include 0x0-0x41 in the checksum, skip the
2058 * checksum word itself
2060 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2061 if (i != IXGBE_EEPROM_CHECKSUM)
2062 checksum += local_buffer[i];
2065 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
2066 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2068 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2069 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2072 pointer = local_buffer[i];
2074 /* Skip pointer section if the pointer is invalid. */
2075 if (pointer == 0xFFFF || pointer == 0 ||
2076 pointer >= hw->eeprom.word_size)
2080 case IXGBE_PCIE_GENERAL_PTR:
2081 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2083 case IXGBE_PCIE_CONFIG0_PTR:
2084 case IXGBE_PCIE_CONFIG1_PTR:
2085 size = IXGBE_PCIE_CONFIG_SIZE;
2092 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2093 buffer, buffer_size);
2098 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2100 return (s32)checksum;
2104 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2105 * @hw: pointer to hardware structure
2107 * Returns a negative error code on error, or the 16-bit checksum
2109 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2111 return ixgbe_calc_checksum_X550(hw, NULL, 0);
2115 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2116 * @hw: pointer to hardware structure
2117 * @checksum_val: calculated checksum
2119 * Performs checksum calculation and validates the EEPROM checksum. If the
2120 * caller does not need checksum_val, the value can be NULL.
2122 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2126 u16 read_checksum = 0;
2128 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2130 /* Read the first word from the EEPROM. If this times out or fails, do
2131 * not continue or we could be in for a very long wait while every
2134 status = hw->eeprom.ops.read(hw, 0, &checksum);
2136 DEBUGOUT("EEPROM read failed\n");
2140 status = hw->eeprom.ops.calc_checksum(hw);
2144 checksum = (u16)(status & 0xffff);
2146 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2151 /* Verify read checksum from EEPROM is the same as
2152 * calculated checksum
2154 if (read_checksum != checksum) {
2155 status = IXGBE_ERR_EEPROM_CHECKSUM;
2156 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2157 "Invalid EEPROM checksum");
2160 /* If the user cares, return the calculated checksum */
2162 *checksum_val = checksum;
2168 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2169 * @hw: pointer to hardware structure
2171 * After writing EEPROM to shadow RAM using EEWR register, software calculates
2172 * checksum and updates the EEPROM and instructs the hardware to update
2175 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2180 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2182 /* Read the first word from the EEPROM. If this times out or fails, do
2183 * not continue or we could be in for a very long wait while every
2186 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2188 DEBUGOUT("EEPROM read failed\n");
2192 status = ixgbe_calc_eeprom_checksum_X550(hw);
2196 checksum = (u16)(status & 0xffff);
2198 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2203 status = ixgbe_update_flash_X550(hw);
2209 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2210 * @hw: pointer to hardware structure
2212 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2214 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2216 s32 status = IXGBE_SUCCESS;
2217 union ixgbe_hic_hdr2 buffer;
2219 DEBUGFUNC("ixgbe_update_flash_X550");
2221 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2222 buffer.req.buf_lenh = 0;
2223 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2224 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2226 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2228 IXGBE_HI_COMMAND_TIMEOUT, false);
2234 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2235 * @hw: pointer to hardware structure
2237 * Determines physical layer capabilities of the current configuration.
2239 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2241 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2242 u16 ext_ability = 0;
2244 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2246 hw->phy.ops.identify(hw);
2248 switch (hw->phy.type) {
2249 case ixgbe_phy_x550em_kr:
2250 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2251 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2253 case ixgbe_phy_x550em_kx4:
2254 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2255 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2257 case ixgbe_phy_x550em_ext_t:
2258 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2259 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2261 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2262 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2263 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2264 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2270 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2271 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2273 return physical_layer;
2277 * ixgbe_get_bus_info_x550em - Set PCI bus info
2278 * @hw: pointer to hardware structure
2280 * Sets bus link width and speed to unknown because X550em is
2283 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2286 DEBUGFUNC("ixgbe_get_bus_info_x550em");
2288 hw->bus.width = ixgbe_bus_width_unknown;
2289 hw->bus.speed = ixgbe_bus_speed_unknown;
2291 return IXGBE_SUCCESS;
2295 * ixgbe_disable_rx_x550 - Disable RX unit
2297 * Enables the Rx DMA unit for x550
2299 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2301 u32 rxctrl, pfdtxgswc;
2303 struct ixgbe_hic_disable_rxen fw_cmd;
2305 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2307 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2308 if (rxctrl & IXGBE_RXCTRL_RXEN) {
2309 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2310 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2311 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2312 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2313 hw->mac.set_lben = true;
2315 hw->mac.set_lben = false;
2318 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2319 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2320 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2321 fw_cmd.port_number = (u8)hw->bus.lan_id;
2323 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2324 sizeof(struct ixgbe_hic_disable_rxen),
2325 IXGBE_HI_COMMAND_TIMEOUT, true);
2327 /* If we fail - disable RX using register write */
2329 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2330 if (rxctrl & IXGBE_RXCTRL_RXEN) {
2331 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2332 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);