1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
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16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
44 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw);
47 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
48 * @hw: pointer to hardware structure
50 * Initialize the function pointers and assign the MAC type for X550.
51 * Does not touch the hardware.
53 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
55 struct ixgbe_mac_info *mac = &hw->mac;
56 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
59 DEBUGFUNC("ixgbe_init_ops_X550");
61 ret_val = ixgbe_init_ops_X540(hw);
62 mac->ops.dmac_config = ixgbe_dmac_config_X550;
63 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
64 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
65 mac->ops.setup_eee = ixgbe_setup_eee_X550;
66 mac->ops.set_source_address_pruning =
67 ixgbe_set_source_address_pruning_X550;
68 mac->ops.set_ethertype_anti_spoofing =
69 ixgbe_set_ethertype_anti_spoofing_X550;
71 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
72 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
73 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
74 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
75 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
76 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
77 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
78 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
79 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
81 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
82 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
83 mac->ops.mdd_event = ixgbe_mdd_event_X550;
84 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
85 mac->ops.disable_rx = ixgbe_disable_rx_x550;
86 /* Manageability interface */
87 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_x550;
88 switch (hw->device_id) {
89 case IXGBE_DEV_ID_X550EM_X_10G_T:
90 case IXGBE_DEV_ID_X550EM_A_10G_T:
91 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
92 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
101 * ixgbe_read_cs4227 - Read CS4227 register
102 * @hw: pointer to hardware structure
103 * @reg: register number to write
104 * @value: pointer to receive value read
106 * Returns status code
108 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
110 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
114 * ixgbe_write_cs4227 - Write CS4227 register
115 * @hw: pointer to hardware structure
116 * @reg: register number to write
117 * @value: value to write to register
119 * Returns status code
121 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
123 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
127 * ixgbe_read_pe - Read register from port expander
128 * @hw: pointer to hardware structure
129 * @reg: register number to read
130 * @value: pointer to receive read value
132 * Returns status code
134 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
138 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
139 if (status != IXGBE_SUCCESS)
140 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
141 "port expander access failed with %d\n", status);
146 * ixgbe_write_pe - Write register to port expander
147 * @hw: pointer to hardware structure
148 * @reg: register number to write
149 * @value: value to write
151 * Returns status code
153 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
157 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
158 if (status != IXGBE_SUCCESS)
159 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
160 "port expander access failed with %d\n", status);
165 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
166 * @hw: pointer to hardware structure
168 * This function assumes that the caller has acquired the proper semaphore.
171 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
178 /* Trigger hard reset. */
179 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
180 if (status != IXGBE_SUCCESS)
182 reg |= IXGBE_PE_BIT1;
183 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
184 if (status != IXGBE_SUCCESS)
187 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
188 if (status != IXGBE_SUCCESS)
190 reg &= ~IXGBE_PE_BIT1;
191 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
192 if (status != IXGBE_SUCCESS)
195 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
196 if (status != IXGBE_SUCCESS)
198 reg &= ~IXGBE_PE_BIT1;
199 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
200 if (status != IXGBE_SUCCESS)
203 usec_delay(IXGBE_CS4227_RESET_HOLD);
205 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
206 if (status != IXGBE_SUCCESS)
208 reg |= IXGBE_PE_BIT1;
209 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
210 if (status != IXGBE_SUCCESS)
213 /* Wait for the reset to complete. */
214 msec_delay(IXGBE_CS4227_RESET_DELAY);
215 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
216 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
218 if (status == IXGBE_SUCCESS &&
219 value == IXGBE_CS4227_EEPROM_LOAD_OK)
221 msec_delay(IXGBE_CS4227_CHECK_DELAY);
223 if (retry == IXGBE_CS4227_RETRIES) {
224 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
225 "CS4227 reset did not complete.");
226 return IXGBE_ERR_PHY;
229 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
230 if (status != IXGBE_SUCCESS ||
231 !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
232 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
233 "CS4227 EEPROM did not load successfully.");
234 return IXGBE_ERR_PHY;
237 return IXGBE_SUCCESS;
241 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
242 * @hw: pointer to hardware structure
244 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
246 s32 status = IXGBE_SUCCESS;
247 u32 swfw_mask = hw->phy.phy_semaphore_mask;
251 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
252 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
253 if (status != IXGBE_SUCCESS) {
254 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
255 "semaphore failed with %d", status);
256 msec_delay(IXGBE_CS4227_CHECK_DELAY);
260 /* Get status of reset flow. */
261 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
263 if (status == IXGBE_SUCCESS &&
264 value == IXGBE_CS4227_RESET_COMPLETE)
267 if (status != IXGBE_SUCCESS ||
268 value != IXGBE_CS4227_RESET_PENDING)
271 /* Reset is pending. Wait and check again. */
272 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
273 msec_delay(IXGBE_CS4227_CHECK_DELAY);
276 /* If still pending, assume other instance failed. */
277 if (retry == IXGBE_CS4227_RETRIES) {
278 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
279 if (status != IXGBE_SUCCESS) {
280 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
281 "semaphore failed with %d", status);
286 /* Reset the CS4227. */
287 status = ixgbe_reset_cs4227(hw);
288 if (status != IXGBE_SUCCESS) {
289 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
290 "CS4227 reset failed: %d", status);
294 /* Reset takes so long, temporarily release semaphore in case the
295 * other driver instance is waiting for the reset indication.
297 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
298 IXGBE_CS4227_RESET_PENDING);
299 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
301 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
302 if (status != IXGBE_SUCCESS) {
303 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
304 "semaphore failed with %d", status);
308 /* Record completion for next time. */
309 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
310 IXGBE_CS4227_RESET_COMPLETE);
313 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
314 msec_delay(hw->eeprom.semaphore_delay);
318 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
319 * @hw: pointer to hardware structure
321 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
323 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
325 if (hw->bus.lan_id) {
326 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
327 esdp |= IXGBE_ESDP_SDP1_DIR;
329 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
330 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
331 IXGBE_WRITE_FLUSH(hw);
335 * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
336 * @hw: pointer to hardware structure
337 * @reg_addr: 32 bit address of PHY register to read
338 * @dev_type: always unused
339 * @phy_data: Pointer to read data from PHY register
341 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
342 u32 dev_type, u16 *phy_data)
344 u32 i, data, command;
345 UNREFERENCED_1PARAMETER(dev_type);
347 /* Setup and write the read command */
348 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
349 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
350 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
351 IXGBE_MSCA_MDI_COMMAND;
353 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
355 /* Check every 10 usec to see if the access completed.
356 * The MDI Command bit will clear when the operation is
359 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
362 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
363 if (!(command & IXGBE_MSCA_MDI_COMMAND))
367 if (command & IXGBE_MSCA_MDI_COMMAND) {
368 ERROR_REPORT1(IXGBE_ERROR_POLLING,
369 "PHY read command did not complete.\n");
370 return IXGBE_ERR_PHY;
373 /* Read operation is complete. Get the data from MSRWD */
374 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
375 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
376 *phy_data = (u16)data;
378 return IXGBE_SUCCESS;
382 * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
383 * @hw: pointer to hardware structure
384 * @reg_addr: 32 bit PHY register to write
385 * @dev_type: always unused
386 * @phy_data: Data to write to the PHY register
388 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
389 u32 dev_type, u16 phy_data)
392 UNREFERENCED_1PARAMETER(dev_type);
394 /* Put the data in the MDI single read and write data register*/
395 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
397 /* Setup and write the write command */
398 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
399 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
400 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
401 IXGBE_MSCA_MDI_COMMAND;
403 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
405 /* Check every 10 usec to see if the access completed.
406 * The MDI Command bit will clear when the operation is
409 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
412 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
413 if (!(command & IXGBE_MSCA_MDI_COMMAND))
417 if (command & IXGBE_MSCA_MDI_COMMAND) {
418 ERROR_REPORT1(IXGBE_ERROR_POLLING,
419 "PHY write cmd didn't complete\n");
420 return IXGBE_ERR_PHY;
423 return IXGBE_SUCCESS;
427 * ixgbe_identify_phy_x550em - Get PHY type based on device id
428 * @hw: pointer to hardware structure
432 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
434 hw->mac.ops.set_lan_id(hw);
436 ixgbe_read_mng_if_sel_x550em(hw);
438 switch (hw->device_id) {
439 case IXGBE_DEV_ID_X550EM_A_SFP:
440 return ixgbe_identify_module_generic(hw);
441 case IXGBE_DEV_ID_X550EM_X_SFP:
442 /* set up for CS4227 usage */
443 ixgbe_setup_mux_ctl(hw);
444 ixgbe_check_cs4227(hw);
447 case IXGBE_DEV_ID_X550EM_A_SFP_N:
448 return ixgbe_identify_module_generic(hw);
450 case IXGBE_DEV_ID_X550EM_X_KX4:
451 hw->phy.type = ixgbe_phy_x550em_kx4;
453 case IXGBE_DEV_ID_X550EM_X_KR:
454 case IXGBE_DEV_ID_X550EM_A_KR:
455 case IXGBE_DEV_ID_X550EM_A_KR_L:
456 hw->phy.type = ixgbe_phy_x550em_kr;
458 case IXGBE_DEV_ID_X550EM_A_10G_T:
459 case IXGBE_DEV_ID_X550EM_A_1G_T:
460 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
461 case IXGBE_DEV_ID_X550EM_X_1G_T:
462 case IXGBE_DEV_ID_X550EM_X_10G_T:
463 return ixgbe_identify_phy_generic(hw);
467 return IXGBE_SUCCESS;
470 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
471 u32 device_type, u16 *phy_data)
473 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
474 return IXGBE_NOT_IMPLEMENTED;
477 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
478 u32 device_type, u16 phy_data)
480 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
481 return IXGBE_NOT_IMPLEMENTED;
485 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
486 * @hw: pointer to the hardware structure
487 * @addr: I2C bus address to read from
488 * @reg: I2C device register to read from
489 * @val: pointer to location to receive read value
491 * Returns an error code on error.
493 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
496 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
500 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
501 * @hw: pointer to the hardware structure
502 * @addr: I2C bus address to read from
503 * @reg: I2C device register to read from
504 * @val: pointer to location to receive read value
506 * Returns an error code on error.
509 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
512 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
516 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
517 * @hw: pointer to the hardware structure
518 * @addr: I2C bus address to write to
519 * @reg: I2C device register to write to
520 * @val: value to write
522 * Returns an error code on error.
524 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
525 u8 addr, u16 reg, u16 val)
527 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
531 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
532 * @hw: pointer to the hardware structure
533 * @addr: I2C bus address to write to
534 * @reg: I2C device register to write to
535 * @val: value to write
537 * Returns an error code on error.
540 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
541 u8 addr, u16 reg, u16 val)
543 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
547 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
548 * @hw: pointer to hardware structure
550 * Initialize the function pointers and for MAC type X550EM.
551 * Does not touch the hardware.
553 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
555 struct ixgbe_mac_info *mac = &hw->mac;
556 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
557 struct ixgbe_phy_info *phy = &hw->phy;
560 DEBUGFUNC("ixgbe_init_ops_X550EM");
562 /* Similar to X550 so start there. */
563 ret_val = ixgbe_init_ops_X550(hw);
565 /* Since this function eventually calls
566 * ixgbe_init_ops_540 by design, we are setting
567 * the pointers to NULL explicitly here to overwrite
568 * the values being set in the x540 function.
570 /* Thermal sensor not supported in x550EM */
571 mac->ops.get_thermal_sensor_data = NULL;
572 mac->ops.init_thermal_sensor_thresh = NULL;
573 mac->thermal_sensor_enabled = false;
575 /* FCOE not supported in x550EM */
576 mac->ops.get_san_mac_addr = NULL;
577 mac->ops.set_san_mac_addr = NULL;
578 mac->ops.get_wwn_prefix = NULL;
579 mac->ops.get_fcoe_boot_status = NULL;
581 /* IPsec not supported in x550EM */
582 mac->ops.disable_sec_rx_path = NULL;
583 mac->ops.enable_sec_rx_path = NULL;
585 /* AUTOC register is not present in x550EM. */
586 mac->ops.prot_autoc_read = NULL;
587 mac->ops.prot_autoc_write = NULL;
589 /* X550EM bus type is internal*/
590 hw->bus.type = ixgbe_bus_type_internal;
591 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
594 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
595 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
596 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
597 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
598 mac->ops.get_supported_physical_layer =
599 ixgbe_get_supported_physical_layer_X550em;
601 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
602 mac->ops.setup_fc = ixgbe_setup_fc_generic;
604 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
606 switch (hw->device_id) {
607 case IXGBE_DEV_ID_X550EM_X_KR:
608 case IXGBE_DEV_ID_X550EM_A_KR:
609 case IXGBE_DEV_ID_X550EM_A_KR_L:
612 mac->ops.setup_eee = NULL;
616 phy->ops.init = ixgbe_init_phy_ops_X550em;
617 phy->ops.identify = ixgbe_identify_phy_x550em;
618 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
619 phy->ops.set_phy_power = NULL;
623 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
624 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
625 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
626 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
627 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
628 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
629 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
630 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
636 * ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
637 * @hw: pointer to hardware structure
639 * Initialize the function pointers and for MAC type X550EM_a.
640 * Does not touch the hardware.
642 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
644 struct ixgbe_mac_info *mac = &hw->mac;
647 DEBUGFUNC("ixgbe_init_ops_X550EM_a");
649 /* Start with generic X550EM init */
650 ret_val = ixgbe_init_ops_X550EM(hw);
652 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
653 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) {
654 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
655 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
657 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
658 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
660 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
661 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
663 switch (mac->ops.get_media_type(hw)) {
664 case ixgbe_media_type_fiber:
665 mac->ops.setup_fc = NULL;
666 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
668 case ixgbe_media_type_backplane:
669 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
670 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
676 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T) ||
677 (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)) {
678 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
679 mac->ops.setup_fc = ixgbe_setup_fc_sgmii_x550em_a;
686 * ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
687 * @hw: pointer to hardware structure
689 * Initialize the function pointers and for MAC type X550EM_x.
690 * Does not touch the hardware.
692 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
694 struct ixgbe_mac_info *mac = &hw->mac;
695 struct ixgbe_link_info *link = &hw->link;
698 DEBUGFUNC("ixgbe_init_ops_X550EM_x");
700 /* Start with generic X550EM init */
701 ret_val = ixgbe_init_ops_X550EM(hw);
703 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
704 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
705 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
706 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
707 link->ops.read_link = ixgbe_read_i2c_combined_generic;
708 link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
709 link->ops.write_link = ixgbe_write_i2c_combined_generic;
710 link->ops.write_link_unlocked =
711 ixgbe_write_i2c_combined_generic_unlocked;
712 link->addr = IXGBE_CS4227;
718 * ixgbe_dmac_config_X550
719 * @hw: pointer to hardware structure
721 * Configure DMA coalescing. If enabling dmac, dmac is activated.
722 * When disabling dmac, dmac enable dmac bit is cleared.
724 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
726 u32 reg, high_pri_tc;
728 DEBUGFUNC("ixgbe_dmac_config_X550");
730 /* Disable DMA coalescing before configuring */
731 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
732 reg &= ~IXGBE_DMACR_DMAC_EN;
733 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
735 /* Disable DMA Coalescing if the watchdog timer is 0 */
736 if (!hw->mac.dmac_config.watchdog_timer)
739 ixgbe_dmac_config_tcs_X550(hw);
741 /* Configure DMA Coalescing Control Register */
742 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
744 /* Set the watchdog timer in units of 40.96 usec */
745 reg &= ~IXGBE_DMACR_DMACWT_MASK;
746 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
748 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
749 /* If fcoe is enabled, set high priority traffic class */
750 if (hw->mac.dmac_config.fcoe_en) {
751 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
752 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
753 IXGBE_DMACR_HIGH_PRI_TC_MASK);
755 reg |= IXGBE_DMACR_EN_MNG_IND;
757 /* Enable DMA coalescing after configuration */
758 reg |= IXGBE_DMACR_DMAC_EN;
759 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
762 return IXGBE_SUCCESS;
766 * ixgbe_dmac_config_tcs_X550
767 * @hw: pointer to hardware structure
769 * Configure DMA coalescing threshold per TC. The dmac enable bit must
770 * be cleared before configuring.
772 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
774 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
776 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
778 /* Configure DMA coalescing enabled */
779 switch (hw->mac.dmac_config.link_speed) {
780 case IXGBE_LINK_SPEED_10_FULL:
781 case IXGBE_LINK_SPEED_100_FULL:
782 pb_headroom = IXGBE_DMACRXT_100M;
784 case IXGBE_LINK_SPEED_1GB_FULL:
785 pb_headroom = IXGBE_DMACRXT_1G;
788 pb_headroom = IXGBE_DMACRXT_10G;
792 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
793 IXGBE_MHADD_MFS_SHIFT) / 1024);
795 /* Set the per Rx packet buffer receive threshold */
796 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
797 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
798 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
800 if (tc < hw->mac.dmac_config.num_tcs) {
802 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
803 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
804 IXGBE_RXPBSIZE_SHIFT;
806 /* Calculate receive buffer threshold in kilobytes */
807 if (rx_pb_size > pb_headroom)
808 rx_pb_size = rx_pb_size - pb_headroom;
812 /* Minimum of MFS shall be set for DMCTH */
813 reg |= (rx_pb_size > maxframe_size_kb) ?
814 rx_pb_size : maxframe_size_kb;
816 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
818 return IXGBE_SUCCESS;
822 * ixgbe_dmac_update_tcs_X550
823 * @hw: pointer to hardware structure
825 * Disables dmac, updates per TC settings, and then enables dmac.
827 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
831 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
833 /* Disable DMA coalescing before configuring */
834 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
835 reg &= ~IXGBE_DMACR_DMAC_EN;
836 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
838 ixgbe_dmac_config_tcs_X550(hw);
840 /* Enable DMA coalescing after configuration */
841 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
842 reg |= IXGBE_DMACR_DMAC_EN;
843 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
845 return IXGBE_SUCCESS;
849 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
850 * @hw: pointer to hardware structure
852 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
853 * ixgbe_hw struct in order to set up EEPROM access.
855 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
857 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
861 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
863 if (eeprom->type == ixgbe_eeprom_uninitialized) {
864 eeprom->semaphore_delay = 10;
865 eeprom->type = ixgbe_flash;
867 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
868 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
869 IXGBE_EEC_SIZE_SHIFT);
870 eeprom->word_size = 1 << (eeprom_size +
871 IXGBE_EEPROM_WORD_SIZE_SHIFT);
873 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
874 eeprom->type, eeprom->word_size);
877 return IXGBE_SUCCESS;
881 * ixgbe_enable_eee_x550 - Enable EEE support
882 * @hw: pointer to hardware structure
884 STATIC s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
890 if (hw->mac.type == ixgbe_mac_X550) {
891 /* Advertise EEE capability */
892 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
893 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
896 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
897 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
898 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
900 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
901 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
903 return IXGBE_SUCCESS;
906 switch (hw->device_id) {
907 case IXGBE_DEV_ID_X550EM_X_KR:
908 case IXGBE_DEV_ID_X550EM_A_KR:
909 case IXGBE_DEV_ID_X550EM_A_KR_L:
910 status = hw->mac.ops.read_iosf_sb_reg(hw,
911 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
912 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
913 if (status != IXGBE_SUCCESS)
916 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
917 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
919 /* Don't advertise FEC capability when EEE enabled. */
920 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
922 status = hw->mac.ops.write_iosf_sb_reg(hw,
923 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
924 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
925 if (status != IXGBE_SUCCESS)
932 return IXGBE_SUCCESS;
936 * ixgbe_disable_eee_x550 - Disable EEE support
937 * @hw: pointer to hardware structure
939 STATIC s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
945 if (hw->mac.type == ixgbe_mac_X550) {
946 /* Disable advertised EEE capability */
947 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
948 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
951 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
952 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
953 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
955 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
956 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
958 return IXGBE_SUCCESS;
961 switch (hw->device_id) {
962 case IXGBE_DEV_ID_X550EM_X_KR:
963 case IXGBE_DEV_ID_X550EM_A_KR:
964 case IXGBE_DEV_ID_X550EM_A_KR_L:
965 status = hw->mac.ops.read_iosf_sb_reg(hw,
966 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
967 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
968 if (status != IXGBE_SUCCESS)
971 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
972 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
974 /* Advertise FEC capability when EEE is disabled. */
975 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
977 status = hw->mac.ops.write_iosf_sb_reg(hw,
978 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
979 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
980 if (status != IXGBE_SUCCESS)
987 return IXGBE_SUCCESS;
991 * ixgbe_setup_eee_X550 - Enable/disable EEE support
992 * @hw: pointer to the HW structure
993 * @enable_eee: boolean flag to enable EEE
995 * Enable/disable EEE based on enable_eee flag.
996 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
1000 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
1005 DEBUGFUNC("ixgbe_setup_eee_X550");
1007 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
1008 /* Enable or disable EEE per flag */
1010 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1012 /* Not supported on first revision of X550EM_x. */
1013 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
1014 !(IXGBE_FUSES0_REV_MASK &
1015 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
1016 return IXGBE_SUCCESS;
1018 status = ixgbe_enable_eee_x550(hw);
1022 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1024 status = ixgbe_disable_eee_x550(hw);
1028 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
1030 return IXGBE_SUCCESS;
1034 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1035 * @hw: pointer to hardware structure
1036 * @enable: enable or disable source address pruning
1037 * @pool: Rx pool to set source address pruning for
1039 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1044 /* max rx pool is 63 */
1048 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1049 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1052 pfflp |= (1ULL << pool);
1054 pfflp &= ~(1ULL << pool);
1056 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1057 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1061 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1062 * @hw: pointer to hardware structure
1063 * @enable: enable or disable switch for Ethertype anti-spoofing
1064 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1067 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1068 bool enable, int vf)
1070 int vf_target_reg = vf >> 3;
1071 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1074 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1076 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1078 pfvfspoof |= (1 << vf_target_shift);
1080 pfvfspoof &= ~(1 << vf_target_shift);
1082 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1086 * ixgbe_iosf_wait - Wait for IOSF command completion
1087 * @hw: pointer to hardware structure
1088 * @ctrl: pointer to location to receive final IOSF control value
1090 * Returns failing status on timeout
1092 * Note: ctrl can be NULL if the IOSF control register value is not needed
1094 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1098 /* Check every 10 usec to see if the address cycle completed.
1099 * The SB IOSF BUSY bit will clear when the operation is
1102 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1103 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1104 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1110 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1111 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1112 return IXGBE_ERR_PHY;
1115 return IXGBE_SUCCESS;
1119 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register
1120 * of the IOSF device
1121 * @hw: pointer to hardware structure
1122 * @reg_addr: 32 bit PHY register to write
1123 * @device_type: 3 bit device type
1124 * @data: Data to write to the register
1126 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1127 u32 device_type, u32 data)
1129 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1133 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1134 if (ret != IXGBE_SUCCESS)
1137 ret = ixgbe_iosf_wait(hw, NULL);
1138 if (ret != IXGBE_SUCCESS)
1141 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1142 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1144 /* Write IOSF control register */
1145 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1147 /* Write IOSF data register */
1148 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1150 ret = ixgbe_iosf_wait(hw, &command);
1152 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1153 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1154 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1155 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1156 "Failed to write, error %x\n", error);
1157 ret = IXGBE_ERR_PHY;
1161 ixgbe_release_swfw_semaphore(hw, gssr);
1166 * ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device
1167 * @hw: pointer to hardware structure
1168 * @reg_addr: 32 bit PHY register to write
1169 * @device_type: 3 bit device type
1170 * @data: Pointer to read data from the register
1172 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1173 u32 device_type, u32 *data)
1175 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1179 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1180 if (ret != IXGBE_SUCCESS)
1183 ret = ixgbe_iosf_wait(hw, NULL);
1184 if (ret != IXGBE_SUCCESS)
1187 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1188 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1190 /* Write IOSF control register */
1191 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1193 ret = ixgbe_iosf_wait(hw, &command);
1195 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1196 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1197 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1198 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1199 "Failed to read, error %x\n", error);
1200 ret = IXGBE_ERR_PHY;
1203 if (ret == IXGBE_SUCCESS)
1204 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1207 ixgbe_release_swfw_semaphore(hw, gssr);
1212 * ixgbe_get_phy_token - Get the token for shared phy access
1213 * @hw: Pointer to hardware structure
1216 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1218 struct ixgbe_hic_phy_token_req token_cmd;
1221 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1222 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1223 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1224 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1225 token_cmd.port_number = hw->bus.lan_id;
1226 token_cmd.command_type = FW_PHY_TOKEN_REQ;
1228 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1230 IXGBE_HI_COMMAND_TIMEOUT,
1234 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1235 return IXGBE_SUCCESS;
1236 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1237 return IXGBE_ERR_FW_RESP_INVALID;
1239 return IXGBE_ERR_TOKEN_RETRY;
1243 * ixgbe_put_phy_token - Put the token for shared phy access
1244 * @hw: Pointer to hardware structure
1247 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1249 struct ixgbe_hic_phy_token_req token_cmd;
1252 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1253 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1254 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1255 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1256 token_cmd.port_number = hw->bus.lan_id;
1257 token_cmd.command_type = FW_PHY_TOKEN_REL;
1259 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1261 IXGBE_HI_COMMAND_TIMEOUT,
1265 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1266 return IXGBE_SUCCESS;
1268 DEBUGOUT("Put PHY Token host interface command failed");
1269 return IXGBE_ERR_FW_RESP_INVALID;
1273 * ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1274 * of the IOSF device
1275 * @hw: pointer to hardware structure
1276 * @reg_addr: 32 bit PHY register to write
1277 * @device_type: 3 bit device type
1278 * @data: Data to write to the register
1280 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1281 u32 device_type, u32 data)
1283 struct ixgbe_hic_internal_phy_req write_cmd;
1285 UNREFERENCED_1PARAMETER(device_type);
1287 memset(&write_cmd, 0, sizeof(write_cmd));
1288 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1289 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1290 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1291 write_cmd.port_number = hw->bus.lan_id;
1292 write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1293 write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1294 write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1296 status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1298 IXGBE_HI_COMMAND_TIMEOUT, false);
1304 * ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device
1305 * @hw: pointer to hardware structure
1306 * @reg_addr: 32 bit PHY register to write
1307 * @device_type: 3 bit device type
1308 * @data: Pointer to read data from the register
1310 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1311 u32 device_type, u32 *data)
1314 struct ixgbe_hic_internal_phy_req cmd;
1315 struct ixgbe_hic_internal_phy_resp rsp;
1318 UNREFERENCED_1PARAMETER(device_type);
1320 memset(&hic, 0, sizeof(hic));
1321 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1322 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1323 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1324 hic.cmd.port_number = hw->bus.lan_id;
1325 hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1326 hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1328 status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1330 IXGBE_HI_COMMAND_TIMEOUT, true);
1332 /* Extract the register value from the response. */
1333 *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1339 * ixgbe_disable_mdd_X550
1340 * @hw: pointer to hardware structure
1342 * Disable malicious driver detection
1344 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1348 DEBUGFUNC("ixgbe_disable_mdd_X550");
1350 /* Disable MDD for TX DMA and interrupt */
1351 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1352 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1353 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1355 /* Disable MDD for RX and interrupt */
1356 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1357 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1358 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1362 * ixgbe_enable_mdd_X550
1363 * @hw: pointer to hardware structure
1365 * Enable malicious driver detection
1367 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1371 DEBUGFUNC("ixgbe_enable_mdd_X550");
1373 /* Enable MDD for TX DMA and interrupt */
1374 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1375 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1376 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1378 /* Enable MDD for RX and interrupt */
1379 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1380 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1381 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1385 * ixgbe_restore_mdd_vf_X550
1386 * @hw: pointer to hardware structure
1389 * Restore VF that was disabled during malicious driver detection event
1391 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1393 u32 idx, reg, num_qs, start_q, bitmask;
1395 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1397 /* Map VF to queues */
1398 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1399 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1400 case IXGBE_MRQC_VMDQRT8TCEN:
1401 num_qs = 8; /* 16 VFs / pools */
1402 bitmask = 0x000000FF;
1404 case IXGBE_MRQC_VMDQRSS32EN:
1405 case IXGBE_MRQC_VMDQRT4TCEN:
1406 num_qs = 4; /* 32 VFs / pools */
1407 bitmask = 0x0000000F;
1409 default: /* 64 VFs / pools */
1411 bitmask = 0x00000003;
1414 start_q = vf * num_qs;
1416 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1419 reg |= (bitmask << (start_q % 32));
1420 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1421 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1425 * ixgbe_mdd_event_X550
1426 * @hw: pointer to hardware structure
1427 * @vf_bitmap: vf bitmap of malicious vfs
1429 * Handle malicious driver detection event.
1431 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1434 u32 i, j, reg, q, shift, vf, idx;
1436 DEBUGFUNC("ixgbe_mdd_event_X550");
1438 /* figure out pool size for mapping to vf's */
1439 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1440 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1441 case IXGBE_MRQC_VMDQRT8TCEN:
1442 shift = 3; /* 16 VFs / pools */
1444 case IXGBE_MRQC_VMDQRSS32EN:
1445 case IXGBE_MRQC_VMDQRT4TCEN:
1446 shift = 2; /* 32 VFs / pools */
1449 shift = 1; /* 64 VFs / pools */
1453 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1454 for (i = 0; i < 4; i++) {
1455 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1456 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1461 /* Get malicious queue */
1462 for (j = 0; j < 32 && wqbr; j++) {
1464 if (!(wqbr & (1 << j)))
1467 /* Get queue from bitmask */
1470 /* Map queue to vf */
1473 /* Set vf bit in vf_bitmap */
1475 vf_bitmap[idx] |= (1 << (vf % 32));
1482 * ixgbe_get_media_type_X550em - Get media type
1483 * @hw: pointer to hardware structure
1485 * Returns the media type (fiber, copper, backplane)
1487 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1489 enum ixgbe_media_type media_type;
1491 DEBUGFUNC("ixgbe_get_media_type_X550em");
1493 /* Detect if there is a copper PHY attached. */
1494 switch (hw->device_id) {
1495 case IXGBE_DEV_ID_X550EM_X_KR:
1496 case IXGBE_DEV_ID_X550EM_X_KX4:
1497 case IXGBE_DEV_ID_X550EM_A_KR:
1498 case IXGBE_DEV_ID_X550EM_A_KR_L:
1499 media_type = ixgbe_media_type_backplane;
1501 case IXGBE_DEV_ID_X550EM_X_SFP:
1502 case IXGBE_DEV_ID_X550EM_A_SFP:
1503 case IXGBE_DEV_ID_X550EM_A_SFP_N:
1504 case IXGBE_DEV_ID_X550EM_A_QSFP:
1505 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1506 media_type = ixgbe_media_type_fiber;
1508 case IXGBE_DEV_ID_X550EM_X_1G_T:
1509 case IXGBE_DEV_ID_X550EM_X_10G_T:
1510 case IXGBE_DEV_ID_X550EM_A_10G_T:
1511 media_type = ixgbe_media_type_copper;
1513 case IXGBE_DEV_ID_X550EM_A_SGMII:
1514 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1515 media_type = ixgbe_media_type_backplane;
1516 hw->phy.type = ixgbe_phy_sgmii;
1518 case IXGBE_DEV_ID_X550EM_A_1G_T:
1519 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1520 media_type = ixgbe_media_type_copper;
1523 media_type = ixgbe_media_type_unknown;
1530 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1531 * @hw: pointer to hardware structure
1532 * @linear: true if SFP module is linear
1534 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1536 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1538 switch (hw->phy.sfp_type) {
1539 case ixgbe_sfp_type_not_present:
1540 return IXGBE_ERR_SFP_NOT_PRESENT;
1541 case ixgbe_sfp_type_da_cu_core0:
1542 case ixgbe_sfp_type_da_cu_core1:
1545 case ixgbe_sfp_type_srlr_core0:
1546 case ixgbe_sfp_type_srlr_core1:
1547 case ixgbe_sfp_type_da_act_lmt_core0:
1548 case ixgbe_sfp_type_da_act_lmt_core1:
1549 case ixgbe_sfp_type_1g_sx_core0:
1550 case ixgbe_sfp_type_1g_sx_core1:
1551 case ixgbe_sfp_type_1g_lx_core0:
1552 case ixgbe_sfp_type_1g_lx_core1:
1555 case ixgbe_sfp_type_unknown:
1556 case ixgbe_sfp_type_1g_cu_core0:
1557 case ixgbe_sfp_type_1g_cu_core1:
1559 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1562 return IXGBE_SUCCESS;
1566 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1567 * @hw: pointer to hardware structure
1569 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1571 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1576 DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1578 status = ixgbe_identify_module_generic(hw);
1580 if (status != IXGBE_SUCCESS)
1583 /* Check if SFP module is supported */
1584 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1590 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1591 * @hw: pointer to hardware structure
1593 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1598 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1600 /* Check if SFP module is supported */
1601 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1603 if (status != IXGBE_SUCCESS)
1606 ixgbe_init_mac_link_ops_X550em(hw);
1607 hw->phy.ops.reset = NULL;
1609 return IXGBE_SUCCESS;
1613 * ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1615 * @hw: pointer to hardware structure
1617 STATIC s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1622 /* Restart auto-negotiation. */
1623 status = hw->mac.ops.read_iosf_sb_reg(hw,
1624 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1625 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1628 DEBUGOUT("Auto-negotiation did not complete\n");
1632 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1633 status = hw->mac.ops.write_iosf_sb_reg(hw,
1634 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1635 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1637 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1640 /* Indicate to FW that AN restart has been asserted */
1641 status = hw->mac.ops.read_iosf_sb_reg(hw,
1642 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1643 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1646 DEBUGOUT("Auto-negotiation did not complete\n");
1650 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1651 status = hw->mac.ops.write_iosf_sb_reg(hw,
1652 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1653 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1660 * ixgbe_setup_sgmii - Set up link for sgmii
1661 * @hw: pointer to hardware structure
1663 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1666 struct ixgbe_mac_info *mac = &hw->mac;
1667 u32 lval, sval, flx_val;
1670 rc = mac->ops.read_iosf_sb_reg(hw,
1671 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1672 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1676 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1677 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1678 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1679 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1680 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1681 rc = mac->ops.write_iosf_sb_reg(hw,
1682 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1683 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1687 rc = mac->ops.read_iosf_sb_reg(hw,
1688 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1689 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1693 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1694 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1695 rc = mac->ops.write_iosf_sb_reg(hw,
1696 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1697 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1701 rc = mac->ops.read_iosf_sb_reg(hw,
1702 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1703 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1707 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1708 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1709 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1710 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1711 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1713 rc = mac->ops.write_iosf_sb_reg(hw,
1714 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1715 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1719 rc = ixgbe_restart_an_internal_phy_x550em(hw);
1723 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1727 * ixgbe_setup_sgmii_m88 - Set up link for sgmii with Marvell PHYs
1728 * @hw: pointer to hardware structure
1730 STATIC s32 ixgbe_setup_sgmii_m88(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1733 struct ixgbe_mac_info *mac = &hw->mac;
1734 u32 lval, sval, flx_val;
1737 rc = mac->ops.read_iosf_sb_reg(hw,
1738 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1739 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1743 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1744 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1745 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1746 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1747 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1748 rc = mac->ops.write_iosf_sb_reg(hw,
1749 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1750 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1754 rc = mac->ops.read_iosf_sb_reg(hw,
1755 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1756 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1760 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1761 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1762 rc = mac->ops.write_iosf_sb_reg(hw,
1763 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1764 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1768 rc = mac->ops.write_iosf_sb_reg(hw,
1769 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1770 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1774 rc = mac->ops.read_iosf_sb_reg(hw,
1775 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1776 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1780 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1781 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1782 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1783 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1784 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1786 rc = mac->ops.write_iosf_sb_reg(hw,
1787 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1788 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1792 rc = ixgbe_restart_an_internal_phy_x550em(hw);
1794 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1798 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1799 * @hw: pointer to hardware structure
1801 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1803 struct ixgbe_mac_info *mac = &hw->mac;
1805 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1807 switch (hw->mac.ops.get_media_type(hw)) {
1808 case ixgbe_media_type_fiber:
1809 /* CS4227 does not support autoneg, so disable the laser control
1810 * functions for SFP+ fiber
1812 mac->ops.disable_tx_laser = NULL;
1813 mac->ops.enable_tx_laser = NULL;
1814 mac->ops.flap_tx_laser = NULL;
1815 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1816 mac->ops.set_rate_select_speed =
1817 ixgbe_set_soft_rate_select_speed;
1819 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1820 (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1821 mac->ops.setup_mac_link =
1822 ixgbe_setup_mac_link_sfp_x550a;
1824 mac->ops.setup_mac_link =
1825 ixgbe_setup_mac_link_sfp_x550em;
1827 case ixgbe_media_type_copper:
1828 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1829 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
1830 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
1831 mac->ops.setup_link = ixgbe_setup_sgmii_m88;
1833 mac->ops.setup_link =
1834 ixgbe_setup_mac_link_t_X550em;
1837 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1838 mac->ops.check_link = ixgbe_check_link_t_X550em;
1841 case ixgbe_media_type_backplane:
1842 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1843 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1844 mac->ops.setup_link = ixgbe_setup_sgmii;
1852 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1853 * @hw: pointer to hardware structure
1854 * @speed: pointer to link speed
1855 * @autoneg: true when autoneg or autotry is enabled
1857 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1858 ixgbe_link_speed *speed,
1861 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1865 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1867 /* CS4227 SFP must not enable auto-negotiation */
1870 /* Check if 1G SFP module. */
1871 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1872 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1873 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1874 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1875 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1876 return IXGBE_SUCCESS;
1879 /* Link capabilities are based on SFP */
1880 if (hw->phy.multispeed_fiber)
1881 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1882 IXGBE_LINK_SPEED_1GB_FULL;
1884 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1886 switch (hw->phy.type) {
1888 *speed = IXGBE_LINK_SPEED_1GB_FULL |
1889 IXGBE_LINK_SPEED_100_FULL |
1890 IXGBE_LINK_SPEED_10_FULL;
1892 case ixgbe_phy_sgmii:
1893 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1895 case ixgbe_phy_x550em_kr:
1896 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1897 /* check different backplane modes */
1898 if (hw->phy.nw_mng_if_sel &
1899 IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
1900 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
1902 } else if (hw->device_id ==
1903 IXGBE_DEV_ID_X550EM_A_KR_L) {
1904 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1910 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1911 IXGBE_LINK_SPEED_1GB_FULL;
1917 return IXGBE_SUCCESS;
1921 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1922 * @hw: pointer to hardware structure
1923 * @lsc: pointer to boolean flag which indicates whether external Base T
1924 * PHY interrupt is lsc
1926 * Determime if external Base T PHY interrupt cause is high temperature
1927 * failure alarm or link status change.
1929 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1930 * failure alarm, else return PHY access status.
1932 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1939 /* Vendor alarm triggered */
1940 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1941 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1944 if (status != IXGBE_SUCCESS ||
1945 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1948 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1949 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1950 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1953 if (status != IXGBE_SUCCESS ||
1954 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1955 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1958 /* Global alarm triggered */
1959 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1960 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1963 if (status != IXGBE_SUCCESS)
1966 /* If high temperature failure, then return over temp error and exit */
1967 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1968 /* power down the PHY in case the PHY FW didn't already */
1969 ixgbe_set_copper_phy_power(hw, false);
1970 return IXGBE_ERR_OVERTEMP;
1971 } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1972 /* device fault alarm triggered */
1973 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1974 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1977 if (status != IXGBE_SUCCESS)
1980 /* if device fault was due to high temp alarm handle and exit */
1981 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1982 /* power down the PHY in case the PHY FW didn't */
1983 ixgbe_set_copper_phy_power(hw, false);
1984 return IXGBE_ERR_OVERTEMP;
1988 /* Vendor alarm 2 triggered */
1989 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1990 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1992 if (status != IXGBE_SUCCESS ||
1993 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1996 /* link connect/disconnect event occurred */
1997 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1998 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
2000 if (status != IXGBE_SUCCESS)
2004 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2007 return IXGBE_SUCCESS;
2011 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2012 * @hw: pointer to hardware structure
2014 * Enable link status change and temperature failure alarm for the external
2017 * Returns PHY access status
2019 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2025 /* Clear interrupt flags */
2026 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2028 /* Enable link status change alarm */
2029 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2030 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
2032 if (status != IXGBE_SUCCESS)
2035 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2037 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2038 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
2040 if (status != IXGBE_SUCCESS)
2043 /* Enable high temperature failure and global fault alarms */
2044 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2045 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2048 if (status != IXGBE_SUCCESS)
2051 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2052 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2054 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2055 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2058 if (status != IXGBE_SUCCESS)
2061 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2062 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2063 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2066 if (status != IXGBE_SUCCESS)
2069 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2070 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2072 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2073 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2076 if (status != IXGBE_SUCCESS)
2079 /* Enable chip-wide vendor alarm */
2080 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2081 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2084 if (status != IXGBE_SUCCESS)
2087 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2089 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2090 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2097 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2098 * @hw: pointer to hardware structure
2099 * @speed: link speed
2101 * Configures the integrated KR PHY.
2103 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2104 ixgbe_link_speed speed)
2109 status = hw->mac.ops.read_iosf_sb_reg(hw,
2110 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2111 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2115 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2116 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2117 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2119 /* Advertise 10G support. */
2120 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2121 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2123 /* Advertise 1G support. */
2124 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2125 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2127 status = hw->mac.ops.write_iosf_sb_reg(hw,
2128 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2129 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2131 if (hw->mac.type == ixgbe_mac_X550EM_a) {
2132 /* Set lane mode to KR auto negotiation */
2133 status = hw->mac.ops.read_iosf_sb_reg(hw,
2134 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2135 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2140 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2141 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2142 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2143 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2144 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2146 status = hw->mac.ops.write_iosf_sb_reg(hw,
2147 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2148 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2151 return ixgbe_restart_an_internal_phy_x550em(hw);
2155 * ixgbe_setup_m88 - setup m88 PHY
2156 * @hw: pointer to hardware structure
2158 STATIC s32 ixgbe_setup_m88(struct ixgbe_hw *hw)
2160 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2164 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2165 return IXGBE_SUCCESS;
2167 rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2171 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2174 if (reg & IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN) {
2175 reg &= ~IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN;
2176 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2180 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, ®);
2183 if (reg & IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN) {
2184 reg &= ~IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN;
2185 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0,
2189 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 2);
2193 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2197 if (reg & IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN) {
2198 reg &= ~IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN;
2199 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2201 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2205 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2209 reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2210 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2214 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2220 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2224 if (!(reg & IXGBE_M88E1500_COPPER_CTRL_AN_EN)) {
2225 reg |= IXGBE_M88E1500_COPPER_CTRL_AN_EN;
2226 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2230 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, ®);
2233 reg &= ~IXGBE_M88E1500_1000T_CTRL_HALF_DUPLEX;
2234 reg &= ~IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2235 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
2236 reg |= IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2237 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, reg);
2239 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, ®);
2242 reg &= ~IXGBE_M88E1500_COPPER_AN_T4;
2243 reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_FD;
2244 reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_HD;
2245 reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_FD;
2246 reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_HD;
2248 /* Flow control auto negotiation configuration was moved from here to
2249 * the function ixgbe_setup_fc_sgmii_x550em_a()
2252 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
2253 reg |= IXGBE_M88E1500_COPPER_AN_100TX_FD;
2254 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL)
2255 reg |= IXGBE_M88E1500_COPPER_AN_10TX_FD;
2256 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, reg);
2258 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2261 reg |= IXGBE_M88E1500_COPPER_CTRL_RESTART_AN;
2262 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2265 hw->mac.ops.release_swfw_sync(hw, mask);
2269 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2270 hw->mac.ops.release_swfw_sync(hw, mask);
2275 * ixgbe_reset_phy_m88e1500 - Reset m88e1500 PHY
2276 * @hw: pointer to hardware structure
2278 * The PHY token must be held when calling this function.
2280 static s32 ixgbe_reset_phy_m88e1500(struct ixgbe_hw *hw)
2285 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2289 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2293 reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2294 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2302 * ixgbe_reset_phy_m88e1543 - Reset m88e1543 PHY
2303 * @hw: pointer to hardware structure
2305 * The PHY token must be held when calling this function.
2307 static s32 ixgbe_reset_phy_m88e1543(struct ixgbe_hw *hw)
2309 return hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2313 * ixgbe_reset_phy_m88 - Reset m88 PHY
2314 * @hw: pointer to hardware structure
2316 STATIC s32 ixgbe_reset_phy_m88(struct ixgbe_hw *hw)
2318 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2322 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2323 return IXGBE_SUCCESS;
2325 rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2329 switch (hw->phy.id) {
2330 case IXGBE_M88E1500_E_PHY_ID:
2331 rc = ixgbe_reset_phy_m88e1500(hw);
2333 case IXGBE_M88E1543_E_PHY_ID:
2334 rc = ixgbe_reset_phy_m88e1543(hw);
2341 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2345 reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2346 IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2347 IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2348 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2352 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 18);
2356 reg = IXGBE_M88E1500_GEN_CTRL_RESET |
2357 IXGBE_M88E1500_GEN_CTRL_MODE_SGMII_COPPER;
2358 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_GEN_CTRL, 0, reg);
2362 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2366 reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2367 IXGBE_M88E1500_FIBER_CTRL_AN_EN |
2368 IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2369 IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2370 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2374 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2378 reg = (IXGBE_M88E1500_MAC_CTRL_1_DWN_4X <<
2379 IXGBE_M88E1500_MAC_CTRL_1_DWN_SHIFT) |
2380 (IXGBE_M88E1500_MAC_CTRL_1_ED_TM <<
2381 IXGBE_M88E1500_MAC_CTRL_1_ED_SHIFT) |
2382 (IXGBE_M88E1500_MAC_CTRL_1_MDIX_AUTO <<
2383 IXGBE_M88E1500_MAC_CTRL_1_MDIX_SHIFT);
2384 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, reg);
2388 reg = IXGBE_M88E1500_COPPER_CTRL_RESET |
2389 IXGBE_M88E1500_COPPER_CTRL_AN_EN |
2390 IXGBE_M88E1500_COPPER_CTRL_RESTART_AN |
2391 IXGBE_M88E1500_COPPER_CTRL_FULL_DUPLEX |
2392 IXGBE_M88E1500_COPPER_CTRL_SPEED_MSB;
2393 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2397 hw->mac.ops.release_swfw_sync(hw, mask);
2399 /* In case of first reset set advertised speeds to default value */
2400 if (!hw->phy.autoneg_advertised)
2401 hw->phy.autoneg_advertised = IXGBE_LINK_SPEED_1GB_FULL |
2402 IXGBE_LINK_SPEED_100_FULL |
2403 IXGBE_LINK_SPEED_10_FULL;
2405 return ixgbe_setup_m88(hw);
2408 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2409 hw->mac.ops.release_swfw_sync(hw, mask);
2414 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2415 * @hw: pointer to hardware structure
2417 * Read NW_MNG_IF_SEL register and save field values, and check for valid field
2420 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2422 /* Save NW management interface connected on board. This is used
2423 * to determine internal PHY mode.
2425 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2427 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2428 * PHY address. This register field was has only been used for X552.
2430 if (hw->mac.type == ixgbe_mac_X550EM_a &&
2431 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2432 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2433 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2434 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2437 return IXGBE_SUCCESS;
2441 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2442 * @hw: pointer to hardware structure
2444 * Initialize any function pointers that were not able to be
2445 * set during init_shared_code because the PHY/SFP type was
2446 * not known. Perform the SFP init if necessary.
2448 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2450 struct ixgbe_phy_info *phy = &hw->phy;
2453 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2455 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2456 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2457 ixgbe_setup_mux_ctl(hw);
2458 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2461 switch (hw->device_id) {
2462 case IXGBE_DEV_ID_X550EM_A_1G_T:
2463 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2464 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2465 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2466 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2467 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2469 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2471 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2474 case IXGBE_DEV_ID_X550EM_A_10G_T:
2475 case IXGBE_DEV_ID_X550EM_A_SFP:
2476 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2477 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2479 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2481 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2483 case IXGBE_DEV_ID_X550EM_X_SFP:
2484 /* set up for CS4227 usage */
2485 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2491 /* Identify the PHY or SFP module */
2492 ret_val = phy->ops.identify(hw);
2493 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
2496 /* Setup function pointers based on detected hardware */
2497 ixgbe_init_mac_link_ops_X550em(hw);
2498 if (phy->sfp_type != ixgbe_sfp_type_unknown)
2499 phy->ops.reset = NULL;
2501 /* Set functions pointers based on phy type */
2502 switch (hw->phy.type) {
2503 case ixgbe_phy_x550em_kx4:
2504 phy->ops.setup_link = NULL;
2505 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2506 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2508 case ixgbe_phy_x550em_kr:
2509 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2510 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2511 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2513 case ixgbe_phy_x550em_ext_t:
2514 /* If internal link mode is XFI, then setup iXFI internal link,
2515 * else setup KR now.
2517 phy->ops.setup_internal_link =
2518 ixgbe_setup_internal_phy_t_x550em;
2520 /* setup SW LPLU only for first revision of X550EM_x */
2521 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2522 !(IXGBE_FUSES0_REV_MASK &
2523 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2524 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2526 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2527 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2529 case ixgbe_phy_sgmii:
2530 phy->ops.setup_link = NULL;
2533 phy->ops.setup_link = ixgbe_setup_m88;
2534 phy->ops.reset = ixgbe_reset_phy_m88;
2543 * ixgbe_set_mdio_speed - Set MDIO clock speed
2544 * @hw: pointer to hardware structure
2546 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2550 switch (hw->device_id) {
2551 case IXGBE_DEV_ID_X550EM_X_10G_T:
2552 case IXGBE_DEV_ID_X550EM_A_SGMII:
2553 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2554 case IXGBE_DEV_ID_X550EM_A_10G_T:
2555 case IXGBE_DEV_ID_X550EM_A_SFP:
2556 case IXGBE_DEV_ID_X550EM_A_QSFP:
2557 /* Config MDIO clock speed before the first MDIO PHY access */
2558 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2559 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2560 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2562 case IXGBE_DEV_ID_X550EM_A_1G_T:
2563 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2564 /* Select fast MDIO clock speed for these devices */
2565 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2566 hlreg0 |= IXGBE_HLREG0_MDCSPD;
2567 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2575 * ixgbe_reset_hw_X550em - Perform hardware reset
2576 * @hw: pointer to hardware structure
2578 * Resets the hardware by resetting the transmit and receive units, masks
2579 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2582 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2584 ixgbe_link_speed link_speed;
2588 bool link_up = false;
2590 DEBUGFUNC("ixgbe_reset_hw_X550em");
2592 /* Call adapter stop to disable Tx/Rx and clear interrupts */
2593 status = hw->mac.ops.stop_adapter(hw);
2594 if (status != IXGBE_SUCCESS)
2597 /* flush pending Tx transactions */
2598 ixgbe_clear_tx_pending(hw);
2600 ixgbe_set_mdio_speed(hw);
2602 /* PHY ops must be identified and initialized prior to reset */
2603 status = hw->phy.ops.init(hw);
2605 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2608 /* start the external PHY */
2609 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2610 status = ixgbe_init_ext_t_x550em(hw);
2615 /* Setup SFP module if there is one present. */
2616 if (hw->phy.sfp_setup_needed) {
2617 status = hw->mac.ops.setup_sfp(hw);
2618 hw->phy.sfp_setup_needed = false;
2621 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2625 if (!hw->phy.reset_disable && hw->phy.ops.reset)
2626 hw->phy.ops.reset(hw);
2629 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
2630 * If link reset is used when link is up, it might reset the PHY when
2631 * mng is using it. If link is down or the flag to force full link
2632 * reset is set, then perform link reset.
2634 ctrl = IXGBE_CTRL_LNK_RST;
2635 if (!hw->force_full_reset) {
2636 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2638 ctrl = IXGBE_CTRL_RST;
2641 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2642 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2643 IXGBE_WRITE_FLUSH(hw);
2645 /* Poll for reset bit to self-clear meaning reset is complete */
2646 for (i = 0; i < 10; i++) {
2648 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2649 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2653 if (ctrl & IXGBE_CTRL_RST_MASK) {
2654 status = IXGBE_ERR_RESET_FAILED;
2655 DEBUGOUT("Reset polling failed to complete.\n");
2660 /* Double resets are required for recovery from certain error
2661 * conditions. Between resets, it is necessary to stall to
2662 * allow time for any pending HW events to complete.
2664 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2665 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2669 /* Store the permanent mac address */
2670 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2672 /* Store MAC address from RAR0, clear receive address registers, and
2673 * clear the multicast table. Also reset num_rar_entries to 128,
2674 * since we modify this value when programming the SAN MAC address.
2676 hw->mac.num_rar_entries = 128;
2677 hw->mac.ops.init_rx_addrs(hw);
2679 ixgbe_set_mdio_speed(hw);
2681 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2682 ixgbe_setup_mux_ctl(hw);
2688 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2689 * @hw: pointer to hardware structure
2691 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2696 status = hw->phy.ops.read_reg(hw,
2697 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2698 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2701 if (status != IXGBE_SUCCESS)
2704 /* If PHY FW reset completed bit is set then this is the first
2705 * SW instance after a power on so the PHY FW must be un-stalled.
2707 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2708 status = hw->phy.ops.read_reg(hw,
2709 IXGBE_MDIO_GLOBAL_RES_PR_10,
2710 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2713 if (status != IXGBE_SUCCESS)
2716 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2718 status = hw->phy.ops.write_reg(hw,
2719 IXGBE_MDIO_GLOBAL_RES_PR_10,
2720 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2723 if (status != IXGBE_SUCCESS)
2731 * ixgbe_setup_kr_x550em - Configure the KR PHY.
2732 * @hw: pointer to hardware structure
2734 * Configures the integrated KR PHY for X550EM_x.
2736 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2738 if (hw->mac.type != ixgbe_mac_X550EM_x)
2739 return IXGBE_SUCCESS;
2741 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2745 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2746 * @hw: pointer to hardware structure
2748 * Configure the external PHY and the integrated KR PHY for SFP support.
2750 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2751 ixgbe_link_speed speed,
2752 bool autoneg_wait_to_complete)
2755 u16 reg_slice, reg_val;
2756 bool setup_linear = false;
2757 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2759 /* Check if SFP module is supported and linear */
2760 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2762 /* If no SFP module present, then return success. Return success since
2763 * there is no reason to configure CS4227 and SFP not present error is
2764 * not excepted in the setup MAC link flow.
2766 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2767 return IXGBE_SUCCESS;
2769 if (ret_val != IXGBE_SUCCESS)
2772 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2773 /* Configure CS4227 LINE side to 10G SR. */
2774 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
2775 (hw->bus.lan_id << 12);
2776 reg_val = IXGBE_CS4227_SPEED_10G;
2777 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2780 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2781 (hw->bus.lan_id << 12);
2782 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2783 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2786 /* Configure CS4227 for HOST connection rate then type. */
2787 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
2788 (hw->bus.lan_id << 12);
2789 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
2790 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
2791 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2794 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
2795 (hw->bus.lan_id << 12);
2797 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2799 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2800 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2803 /* Setup XFI internal link. */
2804 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2806 /* Configure internal PHY for KR/KX. */
2807 ixgbe_setup_kr_speed_x550em(hw, speed);
2809 /* Configure CS4227 LINE side to proper mode. */
2810 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2811 (hw->bus.lan_id << 12);
2813 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2815 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2816 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2823 * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
2824 * @hw: pointer to hardware structure
2825 * @speed: the link speed to force
2827 * Configures the integrated PHY for native SFI mode. Used to connect the
2828 * internal PHY directly to an SFP cage, without autonegotiation.
2830 STATIC s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2832 struct ixgbe_mac_info *mac = &hw->mac;
2836 /* Disable all AN and force speed to 10G Serial. */
2837 status = mac->ops.read_iosf_sb_reg(hw,
2838 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2839 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2840 if (status != IXGBE_SUCCESS)
2843 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2844 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2845 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2846 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2848 /* Select forced link speed for internal PHY. */
2850 case IXGBE_LINK_SPEED_10GB_FULL:
2851 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
2853 case IXGBE_LINK_SPEED_1GB_FULL:
2854 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2857 /* Other link speeds are not supported by internal PHY. */
2858 return IXGBE_ERR_LINK_SETUP;
2861 status = mac->ops.write_iosf_sb_reg(hw,
2862 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2863 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2865 /* Toggle port SW reset by AN reset. */
2866 status = ixgbe_restart_an_internal_phy_x550em(hw);
2872 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2873 * @hw: pointer to hardware structure
2875 * Configure the the integrated PHY for SFP support.
2877 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2878 ixgbe_link_speed speed,
2879 bool autoneg_wait_to_complete)
2883 bool setup_linear = false;
2884 u32 reg_slice, reg_phy_int, slice_offset;
2886 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2888 /* Check if SFP module is supported and linear */
2889 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2891 /* If no SFP module present, then return success. Return success since
2892 * SFP not present error is not excepted in the setup MAC link flow.
2894 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2895 return IXGBE_SUCCESS;
2897 if (ret_val != IXGBE_SUCCESS)
2900 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2901 /* Configure internal PHY for native SFI based on module type */
2902 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2903 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2904 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int);
2906 if (ret_val != IXGBE_SUCCESS)
2909 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
2911 reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
2913 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2914 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2915 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2917 if (ret_val != IXGBE_SUCCESS)
2920 /* Setup SFI internal link. */
2921 ret_val = ixgbe_setup_sfi_x550a(hw, &speed);
2923 /* Configure internal PHY for KR/KX. */
2924 ixgbe_setup_kr_speed_x550em(hw, speed);
2926 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2928 DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2929 return IXGBE_ERR_PHY_ADDR_INVALID;
2932 /* Get external PHY SKU id */
2933 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,
2934 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
2936 if (ret_val != IXGBE_SUCCESS)
2939 /* When configuring quad port CS4223, the MAC instance is part
2940 * of the slice offset.
2942 if (reg_phy_ext == IXGBE_CS4223_SKU_ID)
2943 slice_offset = (hw->bus.lan_id +
2944 (hw->bus.instance_id << 1)) << 12;
2946 slice_offset = hw->bus.lan_id << 12;
2948 /* Configure CS4227/CS4223 LINE side to proper mode. */
2949 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2951 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2953 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2954 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2955 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2961 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2962 * @hw: pointer to hardware structure
2964 * iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2966 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2968 struct ixgbe_mac_info *mac = &hw->mac;
2972 /* Disable training protocol FSM. */
2973 status = mac->ops.read_iosf_sb_reg(hw,
2974 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2975 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2976 if (status != IXGBE_SUCCESS)
2978 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2979 status = mac->ops.write_iosf_sb_reg(hw,
2980 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2981 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2982 if (status != IXGBE_SUCCESS)
2985 /* Disable Flex from training TXFFE. */
2986 status = mac->ops.read_iosf_sb_reg(hw,
2987 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2988 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2989 if (status != IXGBE_SUCCESS)
2991 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2992 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2993 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2994 status = mac->ops.write_iosf_sb_reg(hw,
2995 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2996 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2997 if (status != IXGBE_SUCCESS)
2999 status = mac->ops.read_iosf_sb_reg(hw,
3000 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
3001 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3002 if (status != IXGBE_SUCCESS)
3004 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
3005 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
3006 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
3007 status = mac->ops.write_iosf_sb_reg(hw,
3008 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
3009 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3010 if (status != IXGBE_SUCCESS)
3013 /* Enable override for coefficients. */
3014 status = mac->ops.read_iosf_sb_reg(hw,
3015 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
3016 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3017 if (status != IXGBE_SUCCESS)
3019 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
3020 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
3021 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
3022 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
3023 status = mac->ops.write_iosf_sb_reg(hw,
3024 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
3025 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3030 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
3031 * @hw: pointer to hardware structure
3032 * @speed: the link speed to force
3034 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
3035 * internal and external PHY at a specific speed, without autonegotiation.
3037 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
3039 struct ixgbe_mac_info *mac = &hw->mac;
3043 /* Disable AN and force speed to 10G Serial. */
3044 status = mac->ops.read_iosf_sb_reg(hw,
3045 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3046 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3047 if (status != IXGBE_SUCCESS)
3050 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3051 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3053 /* Select forced link speed for internal PHY. */
3055 case IXGBE_LINK_SPEED_10GB_FULL:
3056 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3058 case IXGBE_LINK_SPEED_1GB_FULL:
3059 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
3062 /* Other link speeds are not supported by internal KR PHY. */
3063 return IXGBE_ERR_LINK_SETUP;
3066 status = mac->ops.write_iosf_sb_reg(hw,
3067 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3068 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3069 if (status != IXGBE_SUCCESS)
3072 /* Additional configuration needed for x550em_x */
3073 if (hw->mac.type == ixgbe_mac_X550EM_x) {
3074 status = ixgbe_setup_ixfi_x550em_x(hw);
3075 if (status != IXGBE_SUCCESS)
3079 /* Toggle port SW reset by AN reset. */
3080 status = ixgbe_restart_an_internal_phy_x550em(hw);
3086 * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
3087 * @hw: address of hardware structure
3088 * @link_up: address of boolean to indicate link status
3090 * Returns error code if unable to get link status.
3092 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
3099 /* read this twice back to back to indicate current status */
3100 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3101 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3103 if (ret != IXGBE_SUCCESS)
3106 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3107 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3109 if (ret != IXGBE_SUCCESS)
3112 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
3114 return IXGBE_SUCCESS;
3118 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
3119 * @hw: point to hardware structure
3121 * Configures the link between the integrated KR PHY and the external X557 PHY
3122 * The driver will call this function when it gets a link status change
3123 * interrupt from the X557 PHY. This function configures the link speed
3124 * between the PHYs to match the link speed of the BASE-T link.
3126 * A return of a non-zero value indicates an error, and the base driver should
3127 * not report link up.
3129 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
3131 ixgbe_link_speed force_speed;
3136 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3137 return IXGBE_ERR_CONFIG;
3139 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3140 /* If link is down, there is no setup necessary so return */
3141 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3142 if (status != IXGBE_SUCCESS)
3146 return IXGBE_SUCCESS;
3148 status = hw->phy.ops.read_reg(hw,
3149 IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3150 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3152 if (status != IXGBE_SUCCESS)
3155 /* If link is still down - no setup is required so return */
3156 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3157 if (status != IXGBE_SUCCESS)
3160 return IXGBE_SUCCESS;
3162 /* clear everything but the speed and duplex bits */
3163 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
3166 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
3167 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3169 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
3170 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3173 /* Internal PHY does not support anything else */
3174 return IXGBE_ERR_INVALID_LINK_SETTINGS;
3177 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
3179 speed = IXGBE_LINK_SPEED_10GB_FULL |
3180 IXGBE_LINK_SPEED_1GB_FULL;
3181 return ixgbe_setup_kr_speed_x550em(hw, speed);
3186 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
3187 * @hw: pointer to hardware structure
3189 * Configures the integrated KR PHY to use internal loopback mode.
3191 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
3196 /* Disable AN and force speed to 10G Serial. */
3197 status = hw->mac.ops.read_iosf_sb_reg(hw,
3198 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3199 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3200 if (status != IXGBE_SUCCESS)
3202 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3203 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3204 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3205 status = hw->mac.ops.write_iosf_sb_reg(hw,
3206 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3207 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3208 if (status != IXGBE_SUCCESS)
3211 /* Set near-end loopback clocks. */
3212 status = hw->mac.ops.read_iosf_sb_reg(hw,
3213 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3214 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3215 if (status != IXGBE_SUCCESS)
3217 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3218 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3219 status = hw->mac.ops.write_iosf_sb_reg(hw,
3220 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3221 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3222 if (status != IXGBE_SUCCESS)
3225 /* Set loopback enable. */
3226 status = hw->mac.ops.read_iosf_sb_reg(hw,
3227 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3228 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3229 if (status != IXGBE_SUCCESS)
3231 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3232 status = hw->mac.ops.write_iosf_sb_reg(hw,
3233 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3234 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3235 if (status != IXGBE_SUCCESS)
3238 /* Training bypass. */
3239 status = hw->mac.ops.read_iosf_sb_reg(hw,
3240 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3241 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3242 if (status != IXGBE_SUCCESS)
3244 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3245 status = hw->mac.ops.write_iosf_sb_reg(hw,
3246 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3247 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3253 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3254 * assuming that the semaphore is already obtained.
3255 * @hw: pointer to hardware structure
3256 * @offset: offset of word in the EEPROM to read
3257 * @data: word read from the EEPROM
3259 * Reads a 16 bit word from the EEPROM using the hostif.
3261 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
3263 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3264 struct ixgbe_hic_read_shadow_ram buffer;
3267 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3268 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3269 buffer.hdr.req.buf_lenh = 0;
3270 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3271 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3273 /* convert offset from words to bytes */
3274 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3276 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3278 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3282 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3283 IXGBE_HI_COMMAND_TIMEOUT);
3285 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3286 FW_NVM_DATA_OFFSET);
3289 hw->mac.ops.release_swfw_sync(hw, mask);
3294 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3295 * @hw: pointer to hardware structure
3296 * @offset: offset of word in the EEPROM to read
3297 * @words: number of words
3298 * @data: word(s) read from the EEPROM
3300 * Reads a 16 bit word(s) from the EEPROM using the hostif.
3302 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3303 u16 offset, u16 words, u16 *data)
3305 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3306 struct ixgbe_hic_read_shadow_ram buffer;
3307 u32 current_word = 0;
3312 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3314 /* Take semaphore for the entire operation. */
3315 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3317 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3322 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3323 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3325 words_to_read = words;
3327 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3328 buffer.hdr.req.buf_lenh = 0;
3329 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3330 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3332 /* convert offset from words to bytes */
3333 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3334 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3336 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3337 IXGBE_HI_COMMAND_TIMEOUT);
3340 DEBUGOUT("Host interface command failed\n");
3344 for (i = 0; i < words_to_read; i++) {
3345 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3347 u32 value = IXGBE_READ_REG(hw, reg);
3349 data[current_word] = (u16)(value & 0xffff);
3352 if (i < words_to_read) {
3354 data[current_word] = (u16)(value & 0xffff);
3358 words -= words_to_read;
3362 hw->mac.ops.release_swfw_sync(hw, mask);
3367 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3368 * @hw: pointer to hardware structure
3369 * @offset: offset of word in the EEPROM to write
3370 * @data: word write to the EEPROM
3372 * Write a 16 bit word to the EEPROM using the hostif.
3374 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3378 struct ixgbe_hic_write_shadow_ram buffer;
3380 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3382 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3383 buffer.hdr.req.buf_lenh = 0;
3384 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3385 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3388 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3390 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3392 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3394 IXGBE_HI_COMMAND_TIMEOUT, false);
3400 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3401 * @hw: pointer to hardware structure
3402 * @offset: offset of word in the EEPROM to write
3403 * @data: word write to the EEPROM
3405 * Write a 16 bit word to the EEPROM using the hostif.
3407 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3410 s32 status = IXGBE_SUCCESS;
3412 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3414 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3416 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3417 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3419 DEBUGOUT("write ee hostif failed to get semaphore");
3420 status = IXGBE_ERR_SWFW_SYNC;
3427 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3428 * @hw: pointer to hardware structure
3429 * @offset: offset of word in the EEPROM to write
3430 * @words: number of words
3431 * @data: word(s) write to the EEPROM
3433 * Write a 16 bit word(s) to the EEPROM using the hostif.
3435 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3436 u16 offset, u16 words, u16 *data)
3438 s32 status = IXGBE_SUCCESS;
3441 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3443 /* Take semaphore for the entire operation. */
3444 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3445 if (status != IXGBE_SUCCESS) {
3446 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3450 for (i = 0; i < words; i++) {
3451 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3454 if (status != IXGBE_SUCCESS) {
3455 DEBUGOUT("Eeprom buffered write failed\n");
3460 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3467 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3468 * @hw: pointer to hardware structure
3469 * @ptr: pointer offset in eeprom
3470 * @size: size of section pointed by ptr, if 0 first word will be used as size
3471 * @csum: address of checksum to update
3473 * Returns error status for any failure
3475 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3476 u16 size, u16 *csum, u16 *buffer,
3481 u16 length, bufsz, i, start;
3484 bufsz = sizeof(buf) / sizeof(buf[0]);
3486 /* Read a chunk at the pointer location */
3488 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3490 DEBUGOUT("Failed to read EEPROM image\n");
3495 if (buffer_size < ptr)
3496 return IXGBE_ERR_PARAM;
3497 local_buffer = &buffer[ptr];
3505 length = local_buffer[0];
3507 /* Skip pointer section if length is invalid. */
3508 if (length == 0xFFFF || length == 0 ||
3509 (ptr + length) >= hw->eeprom.word_size)
3510 return IXGBE_SUCCESS;
3513 if (buffer && ((u32)start + (u32)length > buffer_size))
3514 return IXGBE_ERR_PARAM;
3516 for (i = start; length; i++, length--) {
3517 if (i == bufsz && !buffer) {
3523 /* Read a chunk at the pointer location */
3524 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3527 DEBUGOUT("Failed to read EEPROM image\n");
3531 *csum += local_buffer[i];
3533 return IXGBE_SUCCESS;
3537 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3538 * @hw: pointer to hardware structure
3539 * @buffer: pointer to buffer containing calculated checksum
3540 * @buffer_size: size of buffer
3542 * Returns a negative error code on error, or the 16-bit checksum
3544 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3546 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3550 u16 pointer, i, size;
3552 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3554 hw->eeprom.ops.init_params(hw);
3557 /* Read pointer area */
3558 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3559 IXGBE_EEPROM_LAST_WORD + 1,
3562 DEBUGOUT("Failed to read EEPROM image\n");
3565 local_buffer = eeprom_ptrs;
3567 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3568 return IXGBE_ERR_PARAM;
3569 local_buffer = buffer;
3573 * For X550 hardware include 0x0-0x41 in the checksum, skip the
3574 * checksum word itself
3576 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3577 if (i != IXGBE_EEPROM_CHECKSUM)
3578 checksum += local_buffer[i];
3581 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
3582 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3584 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3585 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3588 pointer = local_buffer[i];
3590 /* Skip pointer section if the pointer is invalid. */
3591 if (pointer == 0xFFFF || pointer == 0 ||
3592 pointer >= hw->eeprom.word_size)
3596 case IXGBE_PCIE_GENERAL_PTR:
3597 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3599 case IXGBE_PCIE_CONFIG0_PTR:
3600 case IXGBE_PCIE_CONFIG1_PTR:
3601 size = IXGBE_PCIE_CONFIG_SIZE;
3608 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3609 buffer, buffer_size);
3614 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3616 return (s32)checksum;
3620 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3621 * @hw: pointer to hardware structure
3623 * Returns a negative error code on error, or the 16-bit checksum
3625 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3627 return ixgbe_calc_checksum_X550(hw, NULL, 0);
3631 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3632 * @hw: pointer to hardware structure
3633 * @checksum_val: calculated checksum
3635 * Performs checksum calculation and validates the EEPROM checksum. If the
3636 * caller does not need checksum_val, the value can be NULL.
3638 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3642 u16 read_checksum = 0;
3644 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3646 /* Read the first word from the EEPROM. If this times out or fails, do
3647 * not continue or we could be in for a very long wait while every
3650 status = hw->eeprom.ops.read(hw, 0, &checksum);
3652 DEBUGOUT("EEPROM read failed\n");
3656 status = hw->eeprom.ops.calc_checksum(hw);
3660 checksum = (u16)(status & 0xffff);
3662 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3667 /* Verify read checksum from EEPROM is the same as
3668 * calculated checksum
3670 if (read_checksum != checksum) {
3671 status = IXGBE_ERR_EEPROM_CHECKSUM;
3672 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3673 "Invalid EEPROM checksum");
3676 /* If the user cares, return the calculated checksum */
3678 *checksum_val = checksum;
3684 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3685 * @hw: pointer to hardware structure
3687 * After writing EEPROM to shadow RAM using EEWR register, software calculates
3688 * checksum and updates the EEPROM and instructs the hardware to update
3691 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3696 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3698 /* Read the first word from the EEPROM. If this times out or fails, do
3699 * not continue or we could be in for a very long wait while every
3702 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3704 DEBUGOUT("EEPROM read failed\n");
3708 status = ixgbe_calc_eeprom_checksum_X550(hw);
3712 checksum = (u16)(status & 0xffff);
3714 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3719 status = ixgbe_update_flash_X550(hw);
3725 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3726 * @hw: pointer to hardware structure
3728 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3730 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3732 s32 status = IXGBE_SUCCESS;
3733 union ixgbe_hic_hdr2 buffer;
3735 DEBUGFUNC("ixgbe_update_flash_X550");
3737 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3738 buffer.req.buf_lenh = 0;
3739 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3740 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3742 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3744 IXGBE_HI_COMMAND_TIMEOUT, false);
3750 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3751 * @hw: pointer to hardware structure
3753 * Determines physical layer capabilities of the current configuration.
3755 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3757 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3758 u16 ext_ability = 0;
3760 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3762 hw->phy.ops.identify(hw);
3764 switch (hw->phy.type) {
3765 case ixgbe_phy_x550em_kr:
3766 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3767 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3769 case ixgbe_phy_x550em_kx4:
3770 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3771 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3773 case ixgbe_phy_x550em_ext_t:
3774 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3775 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3777 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3778 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3779 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3780 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3786 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3787 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3789 return physical_layer;
3793 * ixgbe_get_bus_info_x550em - Set PCI bus info
3794 * @hw: pointer to hardware structure
3796 * Sets bus link width and speed to unknown because X550em is
3799 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3802 DEBUGFUNC("ixgbe_get_bus_info_x550em");
3804 hw->bus.width = ixgbe_bus_width_unknown;
3805 hw->bus.speed = ixgbe_bus_speed_unknown;
3807 hw->mac.ops.set_lan_id(hw);
3809 return IXGBE_SUCCESS;
3813 * ixgbe_disable_rx_x550 - Disable RX unit
3815 * Enables the Rx DMA unit for x550
3817 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3819 u32 rxctrl, pfdtxgswc;
3821 struct ixgbe_hic_disable_rxen fw_cmd;
3823 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3825 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3826 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3827 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3828 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3829 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3830 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3831 hw->mac.set_lben = true;
3833 hw->mac.set_lben = false;
3836 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3837 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3838 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3839 fw_cmd.port_number = (u8)hw->bus.lan_id;
3841 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3842 sizeof(struct ixgbe_hic_disable_rxen),
3843 IXGBE_HI_COMMAND_TIMEOUT, true);
3845 /* If we fail - disable RX using register write */
3847 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3848 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3849 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3850 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3857 * ixgbe_enter_lplu_x550em - Transition to low power states
3858 * @hw: pointer to hardware structure
3860 * Configures Low Power Link Up on transition to low power states
3861 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3862 * X557 PHY immediately prior to entering LPLU.
3864 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3866 u16 an_10g_cntl_reg, autoneg_reg, speed;
3868 ixgbe_link_speed lcd_speed;
3872 /* SW LPLU not required on later HW revisions. */
3873 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3874 (IXGBE_FUSES0_REV_MASK &
3875 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3876 return IXGBE_SUCCESS;
3878 /* If blocked by MNG FW, then don't restart AN */
3879 if (ixgbe_check_reset_blocked(hw))
3880 return IXGBE_SUCCESS;
3882 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3883 if (status != IXGBE_SUCCESS)
3886 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3888 if (status != IXGBE_SUCCESS)
3891 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3892 * disabled, then force link down by entering low power mode.
3894 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3895 !(hw->wol_enabled || ixgbe_mng_present(hw)))
3896 return ixgbe_set_copper_phy_power(hw, FALSE);
3899 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3901 if (status != IXGBE_SUCCESS)
3904 /* If no valid LCD link speed, then force link down and exit. */
3905 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3906 return ixgbe_set_copper_phy_power(hw, FALSE);
3908 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3909 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3912 if (status != IXGBE_SUCCESS)
3915 /* If no link now, speed is invalid so take link down */
3916 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3917 if (status != IXGBE_SUCCESS)
3918 return ixgbe_set_copper_phy_power(hw, false);
3920 /* clear everything but the speed bits */
3921 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3923 /* If current speed is already LCD, then exit. */
3924 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3925 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3926 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3927 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3930 /* Clear AN completed indication */
3931 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3932 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3935 if (status != IXGBE_SUCCESS)
3938 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3939 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3942 if (status != IXGBE_SUCCESS)
3945 status = hw->phy.ops.read_reg(hw,
3946 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3947 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3950 if (status != IXGBE_SUCCESS)
3953 save_autoneg = hw->phy.autoneg_advertised;
3955 /* Setup link at least common link speed */
3956 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3958 /* restore autoneg from before setting lplu speed */
3959 hw->phy.autoneg_advertised = save_autoneg;
3965 * ixgbe_get_lcd_x550em - Determine lowest common denominator
3966 * @hw: pointer to hardware structure
3967 * @lcd_speed: pointer to lowest common link speed
3969 * Determine lowest common link speed with link partner.
3971 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3975 u16 word = hw->eeprom.ctrl_word_3;
3977 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3979 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3980 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3983 if (status != IXGBE_SUCCESS)
3986 /* If link partner advertised 1G, return 1G */
3987 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3988 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3992 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3993 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3994 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3997 /* Link partner not capable of lower speeds, return 10G */
3998 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
4003 * ixgbe_setup_fc_X550em - Set up flow control
4004 * @hw: pointer to hardware structure
4006 * Called at init time to set up flow control.
4008 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
4010 s32 ret_val = IXGBE_SUCCESS;
4011 u32 pause, asm_dir, reg_val;
4013 DEBUGFUNC("ixgbe_setup_fc_X550em");
4015 /* Validate the requested mode */
4016 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4017 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4018 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4019 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4023 /* 10gig parts do not have a word in the EEPROM to determine the
4024 * default flow control setting, so we explicitly set it to full.
4026 if (hw->fc.requested_mode == ixgbe_fc_default)
4027 hw->fc.requested_mode = ixgbe_fc_full;
4029 /* Determine PAUSE and ASM_DIR bits. */
4030 switch (hw->fc.requested_mode) {
4035 case ixgbe_fc_tx_pause:
4039 case ixgbe_fc_rx_pause:
4040 /* Rx Flow control is enabled and Tx Flow control is
4041 * disabled by software override. Since there really
4042 * isn't a way to advertise that we are capable of RX
4043 * Pause ONLY, we will advertise that we support both
4044 * symmetric and asymmetric Rx PAUSE, as such we fall
4045 * through to the fc_full statement. Later, we will
4046 * disable the adapter's ability to send PAUSE frames.
4053 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4054 "Flow control param set incorrectly\n");
4055 ret_val = IXGBE_ERR_CONFIG;
4059 switch (hw->device_id) {
4060 case IXGBE_DEV_ID_X550EM_X_KR:
4061 case IXGBE_DEV_ID_X550EM_A_KR:
4062 case IXGBE_DEV_ID_X550EM_A_KR_L:
4063 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
4064 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4065 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
4066 if (ret_val != IXGBE_SUCCESS)
4068 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4069 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4071 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4073 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4074 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
4075 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4076 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
4078 /* This device does not fully support AN. */
4079 hw->fc.disable_fc_autoneg = true;
4090 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
4091 * @hw: pointer to hardware structure
4093 * Enable flow control according to IEEE clause 37.
4095 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
4097 u32 link_s1, lp_an_page_low, an_cntl_1;
4098 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4099 ixgbe_link_speed speed;
4102 /* AN should have completed when the cable was plugged in.
4103 * Look for reasons to bail out. Bail out if:
4104 * - FC autoneg is disabled, or if
4107 if (hw->fc.disable_fc_autoneg) {
4108 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4109 "Flow control autoneg is disabled");
4113 hw->mac.ops.check_link(hw, &speed, &link_up, false);
4115 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4119 /* Check at auto-negotiation has completed */
4120 status = hw->mac.ops.read_iosf_sb_reg(hw,
4121 IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4122 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4124 if (status != IXGBE_SUCCESS ||
4125 (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4126 DEBUGOUT("Auto-Negotiation did not complete\n");
4127 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4131 /* Read the 10g AN autoc and LP ability registers and resolve
4132 * local flow control settings accordingly
4134 status = hw->mac.ops.read_iosf_sb_reg(hw,
4135 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4136 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
4138 if (status != IXGBE_SUCCESS) {
4139 DEBUGOUT("Auto-Negotiation did not complete\n");
4143 status = hw->mac.ops.read_iosf_sb_reg(hw,
4144 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
4145 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
4147 if (status != IXGBE_SUCCESS) {
4148 DEBUGOUT("Auto-Negotiation did not complete\n");
4152 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
4153 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
4154 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
4155 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
4156 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
4159 if (status == IXGBE_SUCCESS) {
4160 hw->fc.fc_was_autonegged = true;
4162 hw->fc.fc_was_autonegged = false;
4163 hw->fc.current_mode = hw->fc.requested_mode;
4168 * ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
4169 * @hw: pointer to hardware structure
4172 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
4174 hw->fc.fc_was_autonegged = false;
4175 hw->fc.current_mode = hw->fc.requested_mode;
4179 * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
4180 * @hw: pointer to hardware structure
4182 * Enable flow control according to IEEE clause 37.
4184 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
4186 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4187 u16 reg, pcs_an_lp, pcs_an;
4188 ixgbe_link_speed speed;
4191 /* AN should have completed when the cable was plugged in.
4192 * Look for reasons to bail out. Bail out if:
4193 * - FC autoneg is disabled, or if
4196 if (hw->fc.disable_fc_autoneg) {
4197 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4198 "Flow control autoneg is disabled");
4202 hw->mac.ops.check_link(hw, &speed, &link_up, false);
4204 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4208 /* Check if auto-negotiation has completed */
4209 status = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_STATUS,
4210 IXGBE_MDIO_ZERO_DEV_TYPE, ®);
4211 if (status != IXGBE_SUCCESS ||
4212 (reg & IXGBE_M88E1500_COPPER_STATUS_AN_DONE) == 0) {
4213 DEBUGOUT("Auto-Negotiation did not complete\n");
4214 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4218 /* Get the advertized flow control */
4219 status = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_AN,
4220 IXGBE_MDIO_ZERO_DEV_TYPE, &pcs_an);
4221 if (status != IXGBE_SUCCESS)
4224 /* Get link partner's flow control */
4225 status = hw->phy.ops.read_reg(hw,
4226 IXGBE_M88E1500_COPPER_AN_LP_ABILITY,
4227 IXGBE_MDIO_ZERO_DEV_TYPE, &pcs_an_lp);
4228 if (status != IXGBE_SUCCESS)
4231 /* Negotiate the flow control */
4232 status = ixgbe_negotiate_fc(hw, (u32)pcs_an, (u32)pcs_an_lp,
4233 IXGBE_M88E1500_COPPER_AN_PAUSE,
4234 IXGBE_M88E1500_COPPER_AN_AS_PAUSE,
4235 IXGBE_M88E1500_COPPER_AN_LP_PAUSE,
4236 IXGBE_M88E1500_COPPER_AN_LP_AS_PAUSE);
4239 if (status == IXGBE_SUCCESS) {
4240 hw->fc.fc_was_autonegged = true;
4242 hw->fc.fc_was_autonegged = false;
4243 hw->fc.current_mode = hw->fc.requested_mode;
4248 * ixgbe_setup_fc_sgmii_x550em_a - Set up flow control
4249 * @hw: pointer to hardware structure
4251 * Called at init time to set up flow control.
4253 s32 ixgbe_setup_fc_sgmii_x550em_a(struct ixgbe_hw *hw)
4258 /* Validate the requested mode */
4259 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4260 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4261 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4262 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4265 if (hw->fc.requested_mode == ixgbe_fc_default)
4266 hw->fc.requested_mode = ixgbe_fc_full;
4268 /* Read contents of the Auto-Negotiation register, page 0 reg 4 */
4269 rc = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_AN,
4270 IXGBE_MDIO_ZERO_DEV_TYPE, ®);
4274 /* Disable all the settings related to Flow control Auto-negotiation */
4275 reg &= ~IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4276 reg &= ~IXGBE_M88E1500_COPPER_AN_PAUSE;
4278 /* Configure the Asymmetric and symmetric pause according to the user
4281 switch (hw->fc.requested_mode) {
4283 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
4284 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4286 case ixgbe_fc_rx_pause:
4287 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
4288 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4290 case ixgbe_fc_tx_pause:
4291 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4297 /* Write back to the Auto-Negotiation register with newly configured
4300 hw->phy.ops.write_reg(hw, IXGBE_M88E1500_COPPER_AN,
4301 IXGBE_MDIO_ZERO_DEV_TYPE, reg);
4303 /* In this section of the code we restart Auto-negotiation */
4305 /* Read the CONTROL register, Page 0 reg 0 */
4306 rc = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_CTRL,
4307 IXGBE_MDIO_ZERO_DEV_TYPE, ®);
4311 /* Set the bit to restart Auto-Neg. The bit to enable Auto-neg is ON
4314 reg |= IXGBE_M88E1500_COPPER_CTRL_RESTART_AN;
4316 /* write the new values to the register to restart Auto-Negotiation */
4317 hw->phy.ops.write_reg(hw, IXGBE_M88E1500_COPPER_CTRL,
4318 IXGBE_MDIO_ZERO_DEV_TYPE, reg);
4325 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4326 * @hw: pointer to hardware structure
4328 * Called at init time to set up flow control.
4330 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4332 s32 status = IXGBE_SUCCESS;
4335 DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4337 /* Validate the requested mode */
4338 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4339 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4340 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4341 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4344 if (hw->fc.requested_mode == ixgbe_fc_default)
4345 hw->fc.requested_mode = ixgbe_fc_full;
4347 /* Set up the 1G and 10G flow control advertisement registers so the
4348 * HW will be able to do FC autoneg once the cable is plugged in. If
4349 * we link at 10G, the 1G advertisement is harmless and vice versa.
4351 status = hw->mac.ops.read_iosf_sb_reg(hw,
4352 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4353 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4355 if (status != IXGBE_SUCCESS) {
4356 DEBUGOUT("Auto-Negotiation did not complete\n");
4360 /* The possible values of fc.requested_mode are:
4361 * 0: Flow control is completely disabled
4362 * 1: Rx flow control is enabled (we can receive pause frames,
4363 * but not send pause frames).
4364 * 2: Tx flow control is enabled (we can send pause frames but
4365 * we do not support receiving pause frames).
4366 * 3: Both Rx and Tx flow control (symmetric) are enabled.
4369 switch (hw->fc.requested_mode) {
4371 /* Flow control completely disabled by software override. */
4372 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4373 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4375 case ixgbe_fc_tx_pause:
4376 /* Tx Flow control is enabled, and Rx Flow control is
4377 * disabled by software override.
4379 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4380 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4382 case ixgbe_fc_rx_pause:
4383 /* Rx Flow control is enabled and Tx Flow control is
4384 * disabled by software override. Since there really
4385 * isn't a way to advertise that we are capable of RX
4386 * Pause ONLY, we will advertise that we support both
4387 * symmetric and asymmetric Rx PAUSE, as such we fall
4388 * through to the fc_full statement. Later, we will
4389 * disable the adapter's ability to send PAUSE frames.
4392 /* Flow control (both Rx and Tx) is enabled by SW override. */
4393 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4394 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4397 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4398 "Flow control param set incorrectly\n");
4399 return IXGBE_ERR_CONFIG;
4402 status = hw->mac.ops.write_iosf_sb_reg(hw,
4403 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4404 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4406 /* Restart auto-negotiation. */
4407 status = ixgbe_restart_an_internal_phy_x550em(hw);
4413 * ixgbe_set_mux - Set mux for port 1 access with CS4227
4414 * @hw: pointer to hardware structure
4415 * @state: set mux if 1, clear if 0
4417 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4421 if (!hw->bus.lan_id)
4423 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4425 esdp |= IXGBE_ESDP_SDP1;
4427 esdp &= ~IXGBE_ESDP_SDP1;
4428 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4429 IXGBE_WRITE_FLUSH(hw);
4433 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4434 * @hw: pointer to hardware structure
4435 * @mask: Mask to specify which semaphore to acquire
4437 * Acquires the SWFW semaphore and sets the I2C MUX
4439 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4443 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4445 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4449 if (mask & IXGBE_GSSR_I2C_MASK)
4450 ixgbe_set_mux(hw, 1);
4452 return IXGBE_SUCCESS;
4456 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4457 * @hw: pointer to hardware structure
4458 * @mask: Mask to specify which semaphore to release
4460 * Releases the SWFW semaphore and sets the I2C MUX
4462 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4464 DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4466 if (mask & IXGBE_GSSR_I2C_MASK)
4467 ixgbe_set_mux(hw, 0);
4469 ixgbe_release_swfw_sync_X540(hw, mask);
4473 * ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4474 * @hw: pointer to hardware structure
4475 * @mask: Mask to specify which semaphore to acquire
4477 * Acquires the SWFW semaphore and get the shared phy token as needed
4479 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4481 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4482 int retries = FW_PHY_TOKEN_RETRIES;
4483 s32 status = IXGBE_SUCCESS;
4485 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4488 status = IXGBE_SUCCESS;
4490 status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4493 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4494 return IXGBE_SUCCESS;
4496 status = ixgbe_get_phy_token(hw);
4497 if (status == IXGBE_SUCCESS)
4498 return IXGBE_SUCCESS;
4501 ixgbe_release_swfw_sync_X540(hw, hmask);
4502 if (status != IXGBE_ERR_TOKEN_RETRY)
4510 * ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4511 * @hw: pointer to hardware structure
4512 * @mask: Mask to specify which semaphore to release
4514 * Releases the SWFW semaphore and puts the shared phy token as needed
4516 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4518 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4520 DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4522 if (mask & IXGBE_GSSR_TOKEN_SM)
4523 ixgbe_put_phy_token(hw);
4526 ixgbe_release_swfw_sync_X540(hw, hmask);
4530 * ixgbe_read_phy_reg_x550a - Reads specified PHY register
4531 * @hw: pointer to hardware structure
4532 * @reg_addr: 32 bit address of PHY register to read
4533 * @phy_data: Pointer to read data from PHY register
4535 * Reads a value from a specified PHY register using the SWFW lock and PHY
4536 * Token. The PHY Token is needed since the MDIO is shared between to MAC
4539 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4540 u32 device_type, u16 *phy_data)
4543 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4545 DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4547 if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4548 return IXGBE_ERR_SWFW_SYNC;
4550 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4552 hw->mac.ops.release_swfw_sync(hw, mask);
4558 * ixgbe_write_phy_reg_x550a - Writes specified PHY register
4559 * @hw: pointer to hardware structure
4560 * @reg_addr: 32 bit PHY register to write
4561 * @device_type: 5 bit device type
4562 * @phy_data: Data to write to the PHY register
4564 * Writes a value to specified PHY register using the SWFW lock and PHY Token.
4565 * The PHY Token is needed since the MDIO is shared between to MAC instances.
4567 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4568 u32 device_type, u16 phy_data)
4571 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4573 DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4575 if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4576 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
4578 hw->mac.ops.release_swfw_sync(hw, mask);
4580 status = IXGBE_ERR_SWFW_SYNC;
4587 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4588 * @hw: pointer to hardware structure
4590 * Handle external Base T PHY interrupt. If high temperature
4591 * failure alarm then return error, else if link status change
4592 * then setup internal/external PHY link
4594 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4595 * failure alarm, else return PHY access status.
4597 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4602 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4604 if (status != IXGBE_SUCCESS)
4608 return ixgbe_setup_internal_phy(hw);
4610 return IXGBE_SUCCESS;
4614 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4615 * @hw: pointer to hardware structure
4616 * @speed: new link speed
4617 * @autoneg_wait_to_complete: true when waiting for completion is needed
4619 * Setup internal/external PHY link speed based on link speed, then set
4620 * external PHY auto advertised link speed.
4622 * Returns error status for any failure
4624 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4625 ixgbe_link_speed speed,
4626 bool autoneg_wait_to_complete)
4629 ixgbe_link_speed force_speed;
4631 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4633 /* Setup internal/external PHY link speed to iXFI (10G), unless
4634 * only 1G is auto advertised then setup KX link.
4636 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4637 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4639 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4641 /* If internal link mode is XFI, then setup XFI internal link. */
4642 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4643 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4645 if (status != IXGBE_SUCCESS)
4649 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4653 * ixgbe_check_link_t_X550em - Determine link and speed status
4654 * @hw: pointer to hardware structure
4655 * @speed: pointer to link speed
4656 * @link_up: true when link is up
4657 * @link_up_wait_to_complete: bool used to wait for link up or not
4659 * Check that both the MAC and X557 external PHY have link.
4661 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4662 bool *link_up, bool link_up_wait_to_complete)
4665 u16 i, autoneg_status = 0;
4667 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4668 return IXGBE_ERR_CONFIG;
4670 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4671 link_up_wait_to_complete);
4673 /* If check link fails or MAC link is not up, then return */
4674 if (status != IXGBE_SUCCESS || !(*link_up))
4677 /* MAC link is up, so check external PHY link.
4678 * X557 PHY. Link status is latching low, and can only be used to detect
4679 * link drop, and not the current status of the link without performing
4680 * back-to-back reads.
4682 for (i = 0; i < 2; i++) {
4683 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4684 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4687 if (status != IXGBE_SUCCESS)
4691 /* If external PHY link is not up, then indicate link not up */
4692 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4695 return IXGBE_SUCCESS;
4699 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4700 * @hw: pointer to hardware structure
4702 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4706 status = ixgbe_reset_phy_generic(hw);
4708 if (status != IXGBE_SUCCESS)
4711 /* Configure Link Status Alarm and Temperature Threshold interrupts */
4712 return ixgbe_enable_lasi_ext_t_x550em(hw);
4716 * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4717 * @hw: pointer to hardware structure
4718 * @led_idx: led number to turn on
4720 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4724 DEBUGFUNC("ixgbe_led_on_t_X550em");
4726 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4727 return IXGBE_ERR_PARAM;
4729 /* To turn on the LED, set mode to ON. */
4730 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4731 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4732 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4733 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4734 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4736 return IXGBE_SUCCESS;
4740 * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4741 * @hw: pointer to hardware structure
4742 * @led_idx: led number to turn off
4744 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4748 DEBUGFUNC("ixgbe_led_off_t_X550em");
4750 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4751 return IXGBE_ERR_PARAM;
4753 /* To turn on the LED, set mode to ON. */
4754 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4755 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4756 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4757 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4758 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4760 return IXGBE_SUCCESS;
4764 * ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware
4765 * @hw: pointer to the HW structure
4766 * @maj: driver version major number
4767 * @min: driver version minor number
4768 * @build: driver version build number
4769 * @sub: driver version sub build number
4770 * @len: length of driver_ver string
4771 * @driver_ver: driver string
4773 * Sends driver version number to firmware through the manageability
4774 * block. On success return IXGBE_SUCCESS
4775 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4776 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4778 s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,
4779 u8 build, u8 sub, u16 len, const char *driver_ver)
4781 struct ixgbe_hic_drv_info2 fw_cmd;
4782 s32 ret_val = IXGBE_SUCCESS;
4785 DEBUGFUNC("ixgbe_set_fw_drv_ver_x550");
4787 if ((len == 0) || (driver_ver == NULL) ||
4788 (len > sizeof(fw_cmd.driver_string)))
4789 return IXGBE_ERR_INVALID_ARGUMENT;
4791 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4792 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len;
4793 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4794 fw_cmd.port_num = (u8)hw->bus.func;
4795 fw_cmd.ver_maj = maj;
4796 fw_cmd.ver_min = min;
4797 fw_cmd.ver_build = build;
4798 fw_cmd.ver_sub = sub;
4799 fw_cmd.hdr.checksum = 0;
4800 memcpy(fw_cmd.driver_string, driver_ver, len);
4801 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4802 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4804 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4805 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4807 IXGBE_HI_COMMAND_TIMEOUT,
4809 if (ret_val != IXGBE_SUCCESS)
4812 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4813 FW_CEM_RESP_STATUS_SUCCESS)
4814 ret_val = IXGBE_SUCCESS;
4816 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;