drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  44 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw);
  45
  46 /**
  47  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  48  *  @hw: pointer to hardware structure
  49  *
  50  *  Initialize the function pointers and assign the MAC type for X550.
  51  *  Does not touch the hardware.
  52  **/
  53 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  54 {
  55         struct ixgbe_mac_info *mac = &hw->mac;
  56         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  57         s32 ret_val;
  58
  59         DEBUGFUNC("ixgbe_init_ops_X550");
  60
  61         ret_val = ixgbe_init_ops_X540(hw);
  62         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  63         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  64         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  65         mac->ops.setup_eee = NULL;
  66         mac->ops.set_source_address_pruning =
  67                         ixgbe_set_source_address_pruning_X550;
  68         mac->ops.set_ethertype_anti_spoofing =
  69                         ixgbe_set_ethertype_anti_spoofing_X550;
  70
  71         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  72         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  73         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  74         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  75         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  76         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  77         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  78         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  79         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  80
  81         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  82         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  83         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  84         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  85         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  86         /* Manageability interface */
  87         mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_x550;
  88         switch (hw->device_id) {
  89         case IXGBE_DEV_ID_X550EM_X_10G_T:
  90         case IXGBE_DEV_ID_X550EM_A_10G_T:
  91                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  92                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  93                 break;
  94         default:
  95                 break;
  96         }
  97         return ret_val;
  98 }
  99
 100 /**
 101  * ixgbe_read_cs4227 - Read CS4227 register
 102  * @hw: pointer to hardware structure
 103  * @reg: register number to write
 104  * @value: pointer to receive value read
 105  *
 106  * Returns status code
 107  **/
 108 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
 109 {
 110         return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
 111 }
 112
 113 /**
 114  * ixgbe_write_cs4227 - Write CS4227 register
 115  * @hw: pointer to hardware structure
 116  * @reg: register number to write
 117  * @value: value to write to register
 118  *
 119  * Returns status code
 120  **/
 121 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 122 {
 123         return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
 124 }
 125
 126 /**
 127  * ixgbe_read_pe - Read register from port expander
 128  * @hw: pointer to hardware structure
 129  * @reg: register number to read
 130  * @value: pointer to receive read value
 131  *
 132  * Returns status code
 133  **/
 134 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 135 {
 136         s32 status;
 137
 138         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 139         if (status != IXGBE_SUCCESS)
 140                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 141                               "port expander access failed with %d\n", status);
 142         return status;
 143 }
 144
 145 /**
 146  * ixgbe_write_pe - Write register to port expander
 147  * @hw: pointer to hardware structure
 148  * @reg: register number to write
 149  * @value: value to write
 150  *
 151  * Returns status code
 152  **/
 153 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 154 {
 155         s32 status;
 156
 157         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 158         if (status != IXGBE_SUCCESS)
 159                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 160                               "port expander access failed with %d\n", status);
 161         return status;
 162 }
 163
 164 /**
 165  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 166  * @hw: pointer to hardware structure
 167  *
 168  * This function assumes that the caller has acquired the proper semaphore.
 169  * Returns error code
 170  **/
 171 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 172 {
 173         s32 status;
 174         u32 retry;
 175         u16 value;
 176         u8 reg;
 177
 178         /* Trigger hard reset. */
 179         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 180         if (status != IXGBE_SUCCESS)
 181                 return status;
 182         reg |= IXGBE_PE_BIT1;
 183         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 184         if (status != IXGBE_SUCCESS)
 185                 return status;
 186
 187         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 188         if (status != IXGBE_SUCCESS)
 189                 return status;
 190         reg &= ~IXGBE_PE_BIT1;
 191         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 192         if (status != IXGBE_SUCCESS)
 193                 return status;
 194
 195         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 196         if (status != IXGBE_SUCCESS)
 197                 return status;
 198         reg &= ~IXGBE_PE_BIT1;
 199         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 200         if (status != IXGBE_SUCCESS)
 201                 return status;
 202
 203         usec_delay(IXGBE_CS4227_RESET_HOLD);
 204
 205         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 206         if (status != IXGBE_SUCCESS)
 207                 return status;
 208         reg |= IXGBE_PE_BIT1;
 209         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 210         if (status != IXGBE_SUCCESS)
 211                 return status;
 212
 213         /* Wait for the reset to complete. */
 214         msec_delay(IXGBE_CS4227_RESET_DELAY);
 215         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 216                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 217                                            &value);
 218                 if (status == IXGBE_SUCCESS &&
 219                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 220                         break;
 221                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 222         }
 223         if (retry == IXGBE_CS4227_RETRIES) {
 224                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 225                         "CS4227 reset did not complete.");
 226                 return IXGBE_ERR_PHY;
 227         }
 228
 229         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 230         if (status != IXGBE_SUCCESS ||
 231             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 232                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 233                         "CS4227 EEPROM did not load successfully.");
 234                 return IXGBE_ERR_PHY;
 235         }
 236
 237         return IXGBE_SUCCESS;
 238 }
 239
 240 /**
 241  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 242  * @hw: pointer to hardware structure
 243  **/
 244 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 245 {
 246         s32 status = IXGBE_SUCCESS;
 247         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 248         u16 value = 0;
 249         u8 retry;
 250
 251         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 252                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 253                 if (status != IXGBE_SUCCESS) {
 254                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 255                                 "semaphore failed with %d", status);
 256                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 257                         continue;
 258                 }
 259
 260                 /* Get status of reset flow. */
 261                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 262
 263                 if (status == IXGBE_SUCCESS &&
 264                     value == IXGBE_CS4227_RESET_COMPLETE)
 265                         goto out;
 266
 267                 if (status != IXGBE_SUCCESS ||
 268                     value != IXGBE_CS4227_RESET_PENDING)
 269                         break;
 270
 271                 /* Reset is pending. Wait and check again. */
 272                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 273                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 274         }
 275
 276         /* If still pending, assume other instance failed. */
 277         if (retry == IXGBE_CS4227_RETRIES) {
 278                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 279                 if (status != IXGBE_SUCCESS) {
 280                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 281                                       "semaphore failed with %d", status);
 282                         return;
 283                 }
 284         }
 285
 286         /* Reset the CS4227. */
 287         status = ixgbe_reset_cs4227(hw);
 288         if (status != IXGBE_SUCCESS) {
 289                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 290                         "CS4227 reset failed: %d", status);
 291                 goto out;
 292         }
 293
 294         /* Reset takes so long, temporarily release semaphore in case the
 295          * other driver instance is waiting for the reset indication.
 296          */
 297         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 298                            IXGBE_CS4227_RESET_PENDING);
 299         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 300         msec_delay(10);
 301         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 302         if (status != IXGBE_SUCCESS) {
 303                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 304                         "semaphore failed with %d", status);
 305                 return;
 306         }
 307
 308         /* Record completion for next time. */
 309         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 310                 IXGBE_CS4227_RESET_COMPLETE);
 311
 312 out:
 313         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 314         msec_delay(hw->eeprom.semaphore_delay);
 315 }
 316
 317 /**
 318  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 319  * @hw: pointer to hardware structure
 320  **/
 321 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 322 {
 323         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 324
 325         if (hw->bus.lan_id) {
 326                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 327                 esdp |= IXGBE_ESDP_SDP1_DIR;
 328         }
 329         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 330         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 331         IXGBE_WRITE_FLUSH(hw);
 332 }
 333
 334 /**
 335  * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
 336  * @hw: pointer to hardware structure
 337  * @reg_addr: 32 bit address of PHY register to read
 338  * @dev_type: always unused
 339  * @phy_data: Pointer to read data from PHY register
 340  */
 341 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 342                                      u32 dev_type, u16 *phy_data)
 343 {
 344         u32 i, data, command;
 345         UNREFERENCED_1PARAMETER(dev_type);
 346
 347         /* Setup and write the read command */
 348         command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 349                   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 350                   IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
 351                   IXGBE_MSCA_MDI_COMMAND;
 352
 353         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 354
 355         /* Check every 10 usec to see if the access completed.
 356          * The MDI Command bit will clear when the operation is
 357          * complete
 358          */
 359         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 360                 usec_delay(10);
 361
 362                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 363                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 364                         break;
 365         }
 366
 367         if (command & IXGBE_MSCA_MDI_COMMAND) {
 368                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 369                               "PHY read command did not complete.\n");
 370                 return IXGBE_ERR_PHY;
 371         }
 372
 373         /* Read operation is complete.  Get the data from MSRWD */
 374         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 375         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 376         *phy_data = (u16)data;
 377
 378         return IXGBE_SUCCESS;
 379 }
 380
 381 /**
 382  * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
 383  * @hw: pointer to hardware structure
 384  * @reg_addr: 32 bit PHY register to write
 385  * @dev_type: always unused
 386  * @phy_data: Data to write to the PHY register
 387  */
 388 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 389                                       u32 dev_type, u16 phy_data)
 390 {
 391         u32 i, command;
 392         UNREFERENCED_1PARAMETER(dev_type);
 393
 394         /* Put the data in the MDI single read and write data register*/
 395         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 396
 397         /* Setup and write the write command */
 398         command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 399                   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 400                   IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
 401                   IXGBE_MSCA_MDI_COMMAND;
 402
 403         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 404
 405         /* Check every 10 usec to see if the access completed.
 406          * The MDI Command bit will clear when the operation is
 407          * complete
 408          */
 409         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 410                 usec_delay(10);
 411
 412                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 413                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 414                         break;
 415         }
 416
 417         if (command & IXGBE_MSCA_MDI_COMMAND) {
 418                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 419                               "PHY write cmd didn't complete\n");
 420                 return IXGBE_ERR_PHY;
 421         }
 422
 423         return IXGBE_SUCCESS;
 424 }
 425
 426 /**
 427  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 428  * @hw: pointer to hardware structure
 429  *
 430  * Returns error code
 431  */
 432 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 433 {
 434         hw->mac.ops.set_lan_id(hw);
 435
 436         ixgbe_read_mng_if_sel_x550em(hw);
 437
 438         switch (hw->device_id) {
 439         case IXGBE_DEV_ID_X550EM_A_SFP:
 440                 return ixgbe_identify_module_generic(hw);
 441         case IXGBE_DEV_ID_X550EM_X_SFP:
 442                 /* set up for CS4227 usage */
 443                 ixgbe_setup_mux_ctl(hw);
 444                 ixgbe_check_cs4227(hw);
 445                 /* Fallthrough */
 446
 447         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 448                 return ixgbe_identify_module_generic(hw);
 449                 break;
 450         case IXGBE_DEV_ID_X550EM_X_KX4:
 451                 hw->phy.type = ixgbe_phy_x550em_kx4;
 452                 break;
 453         case IXGBE_DEV_ID_X550EM_X_KR:
 454         case IXGBE_DEV_ID_X550EM_A_KR:
 455         case IXGBE_DEV_ID_X550EM_A_KR_L:
 456                 hw->phy.type = ixgbe_phy_x550em_kr;
 457                 break;
 458         case IXGBE_DEV_ID_X550EM_A_10G_T:
 459         case IXGBE_DEV_ID_X550EM_X_1G_T:
 460         case IXGBE_DEV_ID_X550EM_X_10G_T:
 461                 return ixgbe_identify_phy_generic(hw);
 462         case IXGBE_DEV_ID_X550EM_A_1G_T:
 463         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 464                 hw->phy.type = ixgbe_phy_fw;
 465                 hw->phy.ops.read_reg = NULL;
 466                 hw->phy.ops.write_reg = NULL;
 467                 if (hw->bus.lan_id)
 468                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 469                 else
 470                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 471                 break;
 472         default:
 473                 break;
 474         }
 475         return IXGBE_SUCCESS;
 476 }
 477
 478 /**
 479  * ixgbe_fw_phy_activity - Perform an activity on a PHY
 480  * @hw: pointer to hardware structure
 481  * @activity: activity to perform
 482  * @data: Pointer to 4 32-bit words of data
 483  */
 484 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,
 485                           u32 (*data)[FW_PHY_ACT_DATA_COUNT])
 486 {
 487         union {
 488                 struct ixgbe_hic_phy_activity_req cmd;
 489                 struct ixgbe_hic_phy_activity_resp rsp;
 490         } hic;
 491         u16 retries = FW_PHY_ACT_RETRIES;
 492         s32 rc;
 493         u16 i;
 494
 495         do {
 496                 memset(&hic, 0, sizeof(hic));
 497                 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD;
 498                 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN;
 499                 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 500                 hic.cmd.port_number = hw->bus.lan_id;
 501                 hic.cmd.activity_id = IXGBE_CPU_TO_LE16(activity);
 502                 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
 503                         hic.cmd.data[i] = IXGBE_CPU_TO_BE32((*data)[i]);
 504
 505                 rc = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
 506                                                   sizeof(hic.cmd),
 507                                                   IXGBE_HI_COMMAND_TIMEOUT,
 508                                                   true);
 509                 if (rc != IXGBE_SUCCESS)
 510                         return rc;
 511                 if (hic.rsp.hdr.cmd_or_resp.ret_status ==
 512                     FW_CEM_RESP_STATUS_SUCCESS) {
 513                         for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
 514                                 (*data)[i] = IXGBE_BE32_TO_CPU(hic.rsp.data[i]);
 515                         return IXGBE_SUCCESS;
 516                 }
 517                 usec_delay(20);
 518                 --retries;
 519         } while (retries > 0);
 520
 521         return IXGBE_ERR_HOST_INTERFACE_COMMAND;
 522 }
 523
 524 static const struct {
 525         u16 fw_speed;
 526         ixgbe_link_speed phy_speed;
 527 } ixgbe_fw_map[] = {
 528         { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL },
 529         { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL },
 530         { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL },
 531         { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL },
 532         { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL },
 533         { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL },
 534 };
 535
 536 /**
 537  * ixgbe_get_phy_id_fw - Get the phy ID via firmware command
 538  * @hw: pointer to hardware structure
 539  *
 540  * Returns error code
 541  */
 542 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw)
 543 {
 544         u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
 545         u16 phy_speeds;
 546         u16 phy_id_lo;
 547         s32 rc;
 548         u16 i;
 549
 550         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info);
 551         if (rc)
 552                 return rc;
 553
 554         hw->phy.speeds_supported = 0;
 555         phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK;
 556         for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
 557                 if (phy_speeds & ixgbe_fw_map[i].fw_speed)
 558                         hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed;
 559         }
 560         if (!hw->phy.autoneg_advertised)
 561                 hw->phy.autoneg_advertised = hw->phy.speeds_supported;
 562
 563         hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK;
 564         phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK;
 565         hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK;
 566         hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK;
 567         if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK)
 568                 return IXGBE_ERR_PHY_ADDR_INVALID;
 569         return IXGBE_SUCCESS;
 570 }
 571
 572 /**
 573  * ixgbe_identify_phy_fw - Get PHY type based on firmware command
 574  * @hw: pointer to hardware structure
 575  *
 576  * Returns error code
 577  */
 578 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw)
 579 {
 580         if (hw->bus.lan_id)
 581                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 582         else
 583                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 584
 585         hw->phy.type = ixgbe_phy_fw;
 586         hw->phy.ops.read_reg = NULL;
 587         hw->phy.ops.write_reg = NULL;
 588         return ixgbe_get_phy_id_fw(hw);
 589 }
 590
 591 /**
 592  * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY
 593  * @hw: pointer to hardware structure
 594  *
 595  * Returns error code
 596  */
 597 s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw)
 598 {
 599         u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
 600
 601         setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF;
 602         return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup);
 603 }
 604
 605 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 606                                      u32 device_type, u16 *phy_data)
 607 {
 608         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 609         return IXGBE_NOT_IMPLEMENTED;
 610 }
 611
 612 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 613                                       u32 device_type, u16 phy_data)
 614 {
 615         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 616         return IXGBE_NOT_IMPLEMENTED;
 617 }
 618
 619 /**
 620  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 621  * @hw: pointer to the hardware structure
 622  * @addr: I2C bus address to read from
 623  * @reg: I2C device register to read from
 624  * @val: pointer to location to receive read value
 625  *
 626  * Returns an error code on error.
 627  **/
 628 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 629                                            u16 reg, u16 *val)
 630 {
 631         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 632 }
 633
 634 /**
 635  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 636  * @hw: pointer to the hardware structure
 637  * @addr: I2C bus address to read from
 638  * @reg: I2C device register to read from
 639  * @val: pointer to location to receive read value
 640  *
 641  * Returns an error code on error.
 642  **/
 643 STATIC s32
 644 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 645                                          u16 reg, u16 *val)
 646 {
 647         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 648 }
 649
 650 /**
 651  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 652  * @hw: pointer to the hardware structure
 653  * @addr: I2C bus address to write to
 654  * @reg: I2C device register to write to
 655  * @val: value to write
 656  *
 657  * Returns an error code on error.
 658  **/
 659 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 660                                             u8 addr, u16 reg, u16 val)
 661 {
 662         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 663 }
 664
 665 /**
 666  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 667  * @hw: pointer to the hardware structure
 668  * @addr: I2C bus address to write to
 669  * @reg: I2C device register to write to
 670  * @val: value to write
 671  *
 672  * Returns an error code on error.
 673  **/
 674 STATIC s32
 675 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 676                                           u8 addr, u16 reg, u16 val)
 677 {
 678         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 679 }
 680
 681 /**
 682 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 683 *  @hw: pointer to hardware structure
 684 *
 685 *  Initialize the function pointers and for MAC type X550EM.
 686 *  Does not touch the hardware.
 687 **/
 688 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 689 {
 690         struct ixgbe_mac_info *mac = &hw->mac;
 691         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 692         struct ixgbe_phy_info *phy = &hw->phy;
 693         s32 ret_val;
 694
 695         DEBUGFUNC("ixgbe_init_ops_X550EM");
 696
 697         /* Similar to X550 so start there. */
 698         ret_val = ixgbe_init_ops_X550(hw);
 699
 700         /* Since this function eventually calls
 701          * ixgbe_init_ops_540 by design, we are setting
 702          * the pointers to NULL explicitly here to overwrite
 703          * the values being set in the x540 function.
 704          */
 705         /* Thermal sensor not supported in x550EM */
 706         mac->ops.get_thermal_sensor_data = NULL;
 707         mac->ops.init_thermal_sensor_thresh = NULL;
 708         mac->thermal_sensor_enabled = false;
 709
 710         /* FCOE not supported in x550EM */
 711         mac->ops.get_san_mac_addr = NULL;
 712         mac->ops.set_san_mac_addr = NULL;
 713         mac->ops.get_wwn_prefix = NULL;
 714         mac->ops.get_fcoe_boot_status = NULL;
 715
 716         /* IPsec not supported in x550EM */
 717         mac->ops.disable_sec_rx_path = NULL;
 718         mac->ops.enable_sec_rx_path = NULL;
 719
 720         /* AUTOC register is not present in x550EM. */
 721         mac->ops.prot_autoc_read = NULL;
 722         mac->ops.prot_autoc_write = NULL;
 723
 724         /* X550EM bus type is internal*/
 725         hw->bus.type = ixgbe_bus_type_internal;
 726         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 727
 728
 729         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 730         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 731         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 732         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 733         mac->ops.get_supported_physical_layer =
 734                                     ixgbe_get_supported_physical_layer_X550em;
 735
 736         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 737                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 738         else
 739                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 740
 741         /* PHY */
 742         phy->ops.init = ixgbe_init_phy_ops_X550em;
 743         switch (hw->device_id) {
 744         case IXGBE_DEV_ID_X550EM_A_1G_T:
 745         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 746                 mac->ops.setup_fc = NULL;
 747                 phy->ops.identify = ixgbe_identify_phy_fw;
 748                 phy->ops.set_phy_power = NULL;
 749                 phy->ops.get_firmware_version = NULL;
 750                 break;
 751         default:
 752                 phy->ops.identify = ixgbe_identify_phy_x550em;
 753         }
 754
 755         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 756                 phy->ops.set_phy_power = NULL;
 757
 758
 759         /* EEPROM */
 760         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 761         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 762         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 763         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 764         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 765         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 766         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 767         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 768
 769         return ret_val;
 770 }
 771
 772 /**
 773  * ixgbe_setup_fw_link - Setup firmware-controlled PHYs
 774  * @hw: pointer to hardware structure
 775  */
 776 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw)
 777 {
 778         u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
 779         s32 rc;
 780         u16 i;
 781
 782         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
 783                 return 0;
 784
 785         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
 786                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
 787                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
 788                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
 789         }
 790
 791         switch (hw->fc.requested_mode) {
 792         case ixgbe_fc_full:
 793                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX <<
 794                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 795                 break;
 796         case ixgbe_fc_rx_pause:
 797                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX <<
 798                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 799                 break;
 800         case ixgbe_fc_tx_pause:
 801                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX <<
 802                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 803                 break;
 804         default:
 805                 break;
 806         }
 807
 808         for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
 809                 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)
 810                         setup[0] |= ixgbe_fw_map[i].fw_speed;
 811         }
 812         setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN;
 813
 814         if (hw->phy.eee_speeds_advertised)
 815                 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE;
 816
 817         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup);
 818         if (rc)
 819                 return rc;
 820         if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN)
 821                 return IXGBE_ERR_OVERTEMP;
 822         return IXGBE_SUCCESS;
 823 }
 824
 825 /**
 826  * ixgbe_fc_autoneg_fw _ Set up flow control for FW-controlled PHYs
 827  * @hw: pointer to hardware structure
 828  *
 829  *  Called at init time to set up flow control.
 830  */
 831 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw)
 832 {
 833         if (hw->fc.requested_mode == ixgbe_fc_default)
 834                 hw->fc.requested_mode = ixgbe_fc_full;
 835
 836         return ixgbe_setup_fw_link(hw);
 837 }
 838
 839 /**
 840  * ixgbe_setup_eee_fw - Enable/disable EEE support
 841  * @hw: pointer to the HW structure
 842  * @enable_eee: boolean flag to enable EEE
 843  *
 844  * Enable/disable EEE based on enable_eee flag.
 845  * This function controls EEE for firmware-based PHY implementations.
 846  */
 847 static s32 ixgbe_setup_eee_fw(struct ixgbe_hw *hw, bool enable_eee)
 848 {
 849         if (!!hw->phy.eee_speeds_advertised == enable_eee)
 850                 return IXGBE_SUCCESS;
 851         if (enable_eee)
 852                 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
 853         else
 854                 hw->phy.eee_speeds_advertised = 0;
 855         return hw->phy.ops.setup_link(hw);
 856 }
 857
 858 /**
 859 *  ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
 860 *  @hw: pointer to hardware structure
 861 *
 862 *  Initialize the function pointers and for MAC type X550EM_a.
 863 *  Does not touch the hardware.
 864 **/
 865 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
 866 {
 867         struct ixgbe_mac_info *mac = &hw->mac;
 868         s32 ret_val;
 869
 870         DEBUGFUNC("ixgbe_init_ops_X550EM_a");
 871
 872         /* Start with generic X550EM init */
 873         ret_val = ixgbe_init_ops_X550EM(hw);
 874
 875         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
 876             hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) {
 877                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 878                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 879         } else {
 880                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
 881                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
 882         }
 883         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
 884         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
 885
 886         switch (mac->ops.get_media_type(hw)) {
 887         case ixgbe_media_type_fiber:
 888                 mac->ops.setup_fc = NULL;
 889                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
 890                 break;
 891         case ixgbe_media_type_backplane:
 892                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
 893                 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
 894                 break;
 895         default:
 896                 break;
 897         }
 898
 899         switch (hw->device_id) {
 900         case IXGBE_DEV_ID_X550EM_A_1G_T:
 901         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 902                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
 903                 mac->ops.setup_fc = ixgbe_fc_autoneg_fw;
 904                 mac->ops.setup_eee = ixgbe_setup_eee_fw;
 905                 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL |
 906                                                IXGBE_LINK_SPEED_1GB_FULL;
 907                 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
 908                 break;
 909         default:
 910                 break;
 911         }
 912
 913         return ret_val;
 914 }
 915
 916 /**
 917 *  ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
 918 *  @hw: pointer to hardware structure
 919 *
 920 *  Initialize the function pointers and for MAC type X550EM_x.
 921 *  Does not touch the hardware.
 922 **/
 923 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
 924 {
 925         struct ixgbe_mac_info *mac = &hw->mac;
 926         struct ixgbe_link_info *link = &hw->link;
 927         s32 ret_val;
 928
 929         DEBUGFUNC("ixgbe_init_ops_X550EM_x");
 930
 931         /* Start with generic X550EM init */
 932         ret_val = ixgbe_init_ops_X550EM(hw);
 933
 934         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 935         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 936         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 937         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 938         link->ops.read_link = ixgbe_read_i2c_combined_generic;
 939         link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
 940         link->ops.write_link = ixgbe_write_i2c_combined_generic;
 941         link->ops.write_link_unlocked =
 942                                       ixgbe_write_i2c_combined_generic_unlocked;
 943         link->addr = IXGBE_CS4227;
 944
 945         return ret_val;
 946 }
 947
 948 /**
 949  *  ixgbe_dmac_config_X550
 950  *  @hw: pointer to hardware structure
 951  *
 952  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 953  *  When disabling dmac, dmac enable dmac bit is cleared.
 954  **/
 955 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 956 {
 957         u32 reg, high_pri_tc;
 958
 959         DEBUGFUNC("ixgbe_dmac_config_X550");
 960
 961         /* Disable DMA coalescing before configuring */
 962         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 963         reg &= ~IXGBE_DMACR_DMAC_EN;
 964         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 965
 966         /* Disable DMA Coalescing if the watchdog timer is 0 */
 967         if (!hw->mac.dmac_config.watchdog_timer)
 968                 goto out;
 969
 970         ixgbe_dmac_config_tcs_X550(hw);
 971
 972         /* Configure DMA Coalescing Control Register */
 973         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 974
 975         /* Set the watchdog timer in units of 40.96 usec */
 976         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 977         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 978
 979         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 980         /* If fcoe is enabled, set high priority traffic class */
 981         if (hw->mac.dmac_config.fcoe_en) {
 982                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 983                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 984                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 985         }
 986         reg |= IXGBE_DMACR_EN_MNG_IND;
 987
 988         /* Enable DMA coalescing after configuration */
 989         reg |= IXGBE_DMACR_DMAC_EN;
 990         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 991
 992 out:
 993         return IXGBE_SUCCESS;
 994 }
 995
 996 /**
 997  *  ixgbe_dmac_config_tcs_X550
 998  *  @hw: pointer to hardware structure
 999  *
1000  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
1001  *  be cleared before configuring.
1002  **/
1003 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
1004 {
1005         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
1006
1007         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
1008
1009         /* Configure DMA coalescing enabled */
1010         switch (hw->mac.dmac_config.link_speed) {
1011         case IXGBE_LINK_SPEED_10_FULL:
1012         case IXGBE_LINK_SPEED_100_FULL:
1013                 pb_headroom = IXGBE_DMACRXT_100M;
1014                 break;
1015         case IXGBE_LINK_SPEED_1GB_FULL:
1016                 pb_headroom = IXGBE_DMACRXT_1G;
1017                 break;
1018         default:
1019                 pb_headroom = IXGBE_DMACRXT_10G;
1020                 break;
1021         }
1022
1023         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
1024                              IXGBE_MHADD_MFS_SHIFT) / 1024);
1025
1026         /* Set the per Rx packet buffer receive threshold */
1027         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
1028                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
1029                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
1030
1031                 if (tc < hw->mac.dmac_config.num_tcs) {
1032                         /* Get Rx PB size */
1033                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
1034                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
1035                                 IXGBE_RXPBSIZE_SHIFT;
1036
1037                         /* Calculate receive buffer threshold in kilobytes */
1038                         if (rx_pb_size > pb_headroom)
1039                                 rx_pb_size = rx_pb_size - pb_headroom;
1040                         else
1041                                 rx_pb_size = 0;
1042
1043                         /* Minimum of MFS shall be set for DMCTH */
1044                         reg |= (rx_pb_size > maxframe_size_kb) ?
1045                                 rx_pb_size : maxframe_size_kb;
1046                 }
1047                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
1048         }
1049         return IXGBE_SUCCESS;
1050 }
1051
1052 /**
1053  *  ixgbe_dmac_update_tcs_X550
1054  *  @hw: pointer to hardware structure
1055  *
1056  *  Disables dmac, updates per TC settings, and then enables dmac.
1057  **/
1058 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
1059 {
1060         u32 reg;
1061
1062         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
1063
1064         /* Disable DMA coalescing before configuring */
1065         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
1066         reg &= ~IXGBE_DMACR_DMAC_EN;
1067         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
1068
1069         ixgbe_dmac_config_tcs_X550(hw);
1070
1071         /* Enable DMA coalescing after configuration */
1072         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
1073         reg |= IXGBE_DMACR_DMAC_EN;
1074         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
1075
1076         return IXGBE_SUCCESS;
1077 }
1078
1079 /**
1080  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
1081  *  @hw: pointer to hardware structure
1082  *
1083  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
1084  *  ixgbe_hw struct in order to set up EEPROM access.
1085  **/
1086 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
1087 {
1088         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1089         u32 eec;
1090         u16 eeprom_size;
1091
1092         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
1093
1094         if (eeprom->type == ixgbe_eeprom_uninitialized) {
1095                 eeprom->semaphore_delay = 10;
1096                 eeprom->type = ixgbe_flash;
1097
1098                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1099                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1100                                     IXGBE_EEC_SIZE_SHIFT);
1101                 eeprom->word_size = 1 << (eeprom_size +
1102                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
1103
1104                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
1105                           eeprom->type, eeprom->word_size);
1106         }
1107
1108         return IXGBE_SUCCESS;
1109 }
1110
1111 /**
1112  * ixgbe_enable_eee_x550 - Enable EEE support
1113  * @hw: pointer to hardware structure
1114  */
1115 STATIC s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
1116 {
1117         u32 link_reg;
1118         s32 status;
1119
1120         switch (hw->device_id) {
1121         case IXGBE_DEV_ID_X550EM_A_KR:
1122         case IXGBE_DEV_ID_X550EM_A_KR_L:
1123                 status = hw->mac.ops.read_iosf_sb_reg(hw,
1124                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1125                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
1126                 if (status != IXGBE_SUCCESS)
1127                         return status;
1128
1129                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
1130                             IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
1131
1132                 /* Don't advertise FEC capability when EEE enabled. */
1133                 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
1134
1135                 status = hw->mac.ops.write_iosf_sb_reg(hw,
1136                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1137                                         IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
1138                 if (status != IXGBE_SUCCESS)
1139                         return status;
1140                 break;
1141         default:
1142                 break;
1143         }
1144
1145         return IXGBE_SUCCESS;
1146 }
1147
1148 /**
1149  * ixgbe_disable_eee_x550 - Disable EEE support
1150  * @hw: pointer to hardware structure
1151  */
1152 STATIC s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
1153 {
1154         u32 link_reg;
1155         s32 status;
1156
1157         switch (hw->device_id) {
1158         case IXGBE_DEV_ID_X550EM_X_KR:
1159         case IXGBE_DEV_ID_X550EM_A_KR:
1160         case IXGBE_DEV_ID_X550EM_A_KR_L:
1161                 status = hw->mac.ops.read_iosf_sb_reg(hw,
1162                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1163                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
1164                 if (status != IXGBE_SUCCESS)
1165                         return status;
1166
1167                 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
1168                               IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
1169
1170                 /* Advertise FEC capability when EEE is disabled. */
1171                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
1172
1173                 status = hw->mac.ops.write_iosf_sb_reg(hw,
1174                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1175                                         IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
1176                 if (status != IXGBE_SUCCESS)
1177                         return status;
1178                 break;
1179         default:
1180                 break;
1181         }
1182
1183         return IXGBE_SUCCESS;
1184 }
1185
1186 /**
1187  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
1188  *  @hw: pointer to the HW structure
1189  *  @enable_eee: boolean flag to enable EEE
1190  *
1191  *  Enable/disable EEE based on enable_eee flag.
1192  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
1193  *  are modified.
1194  *
1195  **/
1196 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
1197 {
1198         s32 status;
1199         u32 eeer;
1200
1201         DEBUGFUNC("ixgbe_setup_eee_X550");
1202
1203         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
1204         /* Enable or disable EEE per flag */
1205         if (enable_eee) {
1206                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1207
1208                 status = ixgbe_enable_eee_x550(hw);
1209                 if (status)
1210                         return status;
1211         } else {
1212                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1213
1214                 status = ixgbe_disable_eee_x550(hw);
1215                 if (status)
1216                         return status;
1217         }
1218         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
1219
1220         return IXGBE_SUCCESS;
1221 }
1222
1223 /**
1224  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1225  * @hw: pointer to hardware structure
1226  * @enable: enable or disable source address pruning
1227  * @pool: Rx pool to set source address pruning for
1228  **/
1229 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1230                                            unsigned int pool)
1231 {
1232         u64 pfflp;
1233
1234         /* max rx pool is 63 */
1235         if (pool > 63)
1236                 return;
1237
1238         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1239         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1240
1241         if (enable)
1242                 pfflp |= (1ULL << pool);
1243         else
1244                 pfflp &= ~(1ULL << pool);
1245
1246         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1247         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1248 }
1249
1250 /**
1251  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1252  *  @hw: pointer to hardware structure
1253  *  @enable: enable or disable switch for Ethertype anti-spoofing
1254  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1255  *
1256  **/
1257 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1258                 bool enable, int vf)
1259 {
1260         int vf_target_reg = vf >> 3;
1261         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1262         u32 pfvfspoof;
1263
1264         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1265
1266         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1267         if (enable)
1268                 pfvfspoof |= (1 << vf_target_shift);
1269         else
1270                 pfvfspoof &= ~(1 << vf_target_shift);
1271
1272         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1273 }
1274
1275 /**
1276  * ixgbe_iosf_wait - Wait for IOSF command completion
1277  * @hw: pointer to hardware structure
1278  * @ctrl: pointer to location to receive final IOSF control value
1279  *
1280  * Returns failing status on timeout
1281  *
1282  * Note: ctrl can be NULL if the IOSF control register value is not needed
1283  **/
1284 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1285 {
1286         u32 i, command = 0;
1287
1288         /* Check every 10 usec to see if the address cycle completed.
1289          * The SB IOSF BUSY bit will clear when the operation is
1290          * complete
1291          */
1292         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1293                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1294                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1295                         break;
1296                 usec_delay(10);
1297         }
1298         if (ctrl)
1299                 *ctrl = command;
1300         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1301                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1302                 return IXGBE_ERR_PHY;
1303         }
1304
1305         return IXGBE_SUCCESS;
1306 }
1307
1308 /**
1309  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register
1310  *  of the IOSF device
1311  *  @hw: pointer to hardware structure
1312  *  @reg_addr: 32 bit PHY register to write
1313  *  @device_type: 3 bit device type
1314  *  @data: Data to write to the register
1315  **/
1316 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1317                             u32 device_type, u32 data)
1318 {
1319         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1320         u32 command, error;
1321         s32 ret;
1322
1323         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1324         if (ret != IXGBE_SUCCESS)
1325                 return ret;
1326
1327         ret = ixgbe_iosf_wait(hw, NULL);
1328         if (ret != IXGBE_SUCCESS)
1329                 goto out;
1330
1331         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1332                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1333
1334         /* Write IOSF control register */
1335         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1336
1337         /* Write IOSF data register */
1338         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1339
1340         ret = ixgbe_iosf_wait(hw, &command);
1341
1342         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1343                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1344                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1345                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1346                               "Failed to write, error %x\n", error);
1347                 ret = IXGBE_ERR_PHY;
1348         }
1349
1350 out:
1351         ixgbe_release_swfw_semaphore(hw, gssr);
1352         return ret;
1353 }
1354
1355 /**
1356  *  ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device
1357  *  @hw: pointer to hardware structure
1358  *  @reg_addr: 32 bit PHY register to write
1359  *  @device_type: 3 bit device type
1360  *  @data: Pointer to read data from the register
1361  **/
1362 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1363                            u32 device_type, u32 *data)
1364 {
1365         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1366         u32 command, error;
1367         s32 ret;
1368
1369         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1370         if (ret != IXGBE_SUCCESS)
1371                 return ret;
1372
1373         ret = ixgbe_iosf_wait(hw, NULL);
1374         if (ret != IXGBE_SUCCESS)
1375                 goto out;
1376
1377         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1378                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1379
1380         /* Write IOSF control register */
1381         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1382
1383         ret = ixgbe_iosf_wait(hw, &command);
1384
1385         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1386                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1387                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1388                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1389                                 "Failed to read, error %x\n", error);
1390                 ret = IXGBE_ERR_PHY;
1391         }
1392
1393         if (ret == IXGBE_SUCCESS)
1394                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1395
1396 out:
1397         ixgbe_release_swfw_semaphore(hw, gssr);
1398         return ret;
1399 }
1400
1401 /**
1402  * ixgbe_get_phy_token - Get the token for shared phy access
1403  * @hw: Pointer to hardware structure
1404  */
1405
1406 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1407 {
1408         struct ixgbe_hic_phy_token_req token_cmd;
1409         s32 status;
1410
1411         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1412         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1413         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1414         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1415         token_cmd.port_number = hw->bus.lan_id;
1416         token_cmd.command_type = FW_PHY_TOKEN_REQ;
1417         token_cmd.pad = 0;
1418         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1419                                               sizeof(token_cmd),
1420                                               IXGBE_HI_COMMAND_TIMEOUT,
1421                                               true);
1422         if (status)
1423                 return status;
1424         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1425                 return IXGBE_SUCCESS;
1426         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1427                 return IXGBE_ERR_FW_RESP_INVALID;
1428
1429         return IXGBE_ERR_TOKEN_RETRY;
1430 }
1431
1432 /**
1433  * ixgbe_put_phy_token - Put the token for shared phy access
1434  * @hw: Pointer to hardware structure
1435  */
1436
1437 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1438 {
1439         struct ixgbe_hic_phy_token_req token_cmd;
1440         s32 status;
1441
1442         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1443         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1444         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1445         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1446         token_cmd.port_number = hw->bus.lan_id;
1447         token_cmd.command_type = FW_PHY_TOKEN_REL;
1448         token_cmd.pad = 0;
1449         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1450                                               sizeof(token_cmd),
1451                                               IXGBE_HI_COMMAND_TIMEOUT,
1452                                               true);
1453         if (status)
1454                 return status;
1455         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1456                 return IXGBE_SUCCESS;
1457
1458         DEBUGOUT("Put PHY Token host interface command failed");
1459         return IXGBE_ERR_FW_RESP_INVALID;
1460 }
1461
1462 /**
1463  *  ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1464  *  of the IOSF device
1465  *  @hw: pointer to hardware structure
1466  *  @reg_addr: 32 bit PHY register to write
1467  *  @device_type: 3 bit device type
1468  *  @data: Data to write to the register
1469  **/
1470 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1471                                   u32 device_type, u32 data)
1472 {
1473         struct ixgbe_hic_internal_phy_req write_cmd;
1474         s32 status;
1475         UNREFERENCED_1PARAMETER(device_type);
1476
1477         memset(&write_cmd, 0, sizeof(write_cmd));
1478         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1479         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1480         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1481         write_cmd.port_number = hw->bus.lan_id;
1482         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1483         write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1484         write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1485
1486         status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1487                                               sizeof(write_cmd),
1488                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1489
1490         return status;
1491 }
1492
1493 /**
1494  *  ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device
1495  *  @hw: pointer to hardware structure
1496  *  @reg_addr: 32 bit PHY register to write
1497  *  @device_type: 3 bit device type
1498  *  @data: Pointer to read data from the register
1499  **/
1500 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1501                                  u32 device_type, u32 *data)
1502 {
1503         union {
1504                 struct ixgbe_hic_internal_phy_req cmd;
1505                 struct ixgbe_hic_internal_phy_resp rsp;
1506         } hic;
1507         s32 status;
1508         UNREFERENCED_1PARAMETER(device_type);
1509
1510         memset(&hic, 0, sizeof(hic));
1511         hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1512         hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1513         hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1514         hic.cmd.port_number = hw->bus.lan_id;
1515         hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1516         hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1517
1518         status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1519                                               sizeof(hic.cmd),
1520                                               IXGBE_HI_COMMAND_TIMEOUT, true);
1521
1522         /* Extract the register value from the response. */
1523         *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1524
1525         return status;
1526 }
1527
1528 /**
1529  *  ixgbe_disable_mdd_X550
1530  *  @hw: pointer to hardware structure
1531  *
1532  *  Disable malicious driver detection
1533  **/
1534 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1535 {
1536         u32 reg;
1537
1538         DEBUGFUNC("ixgbe_disable_mdd_X550");
1539
1540         /* Disable MDD for TX DMA and interrupt */
1541         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1542         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1543         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1544
1545         /* Disable MDD for RX and interrupt */
1546         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1547         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1548         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1549 }
1550
1551 /**
1552  *  ixgbe_enable_mdd_X550
1553  *  @hw: pointer to hardware structure
1554  *
1555  *  Enable malicious driver detection
1556  **/
1557 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1558 {
1559         u32 reg;
1560
1561         DEBUGFUNC("ixgbe_enable_mdd_X550");
1562
1563         /* Enable MDD for TX DMA and interrupt */
1564         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1565         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1566         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1567
1568         /* Enable MDD for RX and interrupt */
1569         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1570         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1571         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1572 }
1573
1574 /**
1575  *  ixgbe_restore_mdd_vf_X550
1576  *  @hw: pointer to hardware structure
1577  *  @vf: vf index
1578  *
1579  *  Restore VF that was disabled during malicious driver detection event
1580  **/
1581 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1582 {
1583         u32 idx, reg, num_qs, start_q, bitmask;
1584
1585         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1586
1587         /* Map VF to queues */
1588         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1589         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1590         case IXGBE_MRQC_VMDQRT8TCEN:
1591                 num_qs = 8;  /* 16 VFs / pools */
1592                 bitmask = 0x000000FF;
1593                 break;
1594         case IXGBE_MRQC_VMDQRSS32EN:
1595         case IXGBE_MRQC_VMDQRT4TCEN:
1596                 num_qs = 4;  /* 32 VFs / pools */
1597                 bitmask = 0x0000000F;
1598                 break;
1599         default:            /* 64 VFs / pools */
1600                 num_qs = 2;
1601                 bitmask = 0x00000003;
1602                 break;
1603         }
1604         start_q = vf * num_qs;
1605
1606         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1607         idx = start_q / 32;
1608         reg = 0;
1609         reg |= (bitmask << (start_q % 32));
1610         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1611         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1612 }
1613
1614 /**
1615  *  ixgbe_mdd_event_X550
1616  *  @hw: pointer to hardware structure
1617  *  @vf_bitmap: vf bitmap of malicious vfs
1618  *
1619  *  Handle malicious driver detection event.
1620  **/
1621 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1622 {
1623         u32 wqbr;
1624         u32 i, j, reg, q, shift, vf, idx;
1625
1626         DEBUGFUNC("ixgbe_mdd_event_X550");
1627
1628         /* figure out pool size for mapping to vf's */
1629         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1630         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1631         case IXGBE_MRQC_VMDQRT8TCEN:
1632                 shift = 3;  /* 16 VFs / pools */
1633                 break;
1634         case IXGBE_MRQC_VMDQRSS32EN:
1635         case IXGBE_MRQC_VMDQRT4TCEN:
1636                 shift = 2;  /* 32 VFs / pools */
1637                 break;
1638         default:
1639                 shift = 1;  /* 64 VFs / pools */
1640                 break;
1641         }
1642
1643         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1644         for (i = 0; i < 4; i++) {
1645                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1646                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1647
1648                 if (!wqbr)
1649                         continue;
1650
1651                 /* Get malicious queue */
1652                 for (j = 0; j < 32 && wqbr; j++) {
1653
1654                         if (!(wqbr & (1 << j)))
1655                                 continue;
1656
1657                         /* Get queue from bitmask */
1658                         q = j + (i * 32);
1659
1660                         /* Map queue to vf */
1661                         vf = (q >> shift);
1662
1663                         /* Set vf bit in vf_bitmap */
1664                         idx = vf / 32;
1665                         vf_bitmap[idx] |= (1 << (vf % 32));
1666                         wqbr &= ~(1 << j);
1667                 }
1668         }
1669 }
1670
1671 /**
1672  *  ixgbe_get_media_type_X550em - Get media type
1673  *  @hw: pointer to hardware structure
1674  *
1675  *  Returns the media type (fiber, copper, backplane)
1676  */
1677 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1678 {
1679         enum ixgbe_media_type media_type;
1680
1681         DEBUGFUNC("ixgbe_get_media_type_X550em");
1682
1683         /* Detect if there is a copper PHY attached. */
1684         switch (hw->device_id) {
1685         case IXGBE_DEV_ID_X550EM_X_KR:
1686         case IXGBE_DEV_ID_X550EM_X_KX4:
1687         case IXGBE_DEV_ID_X550EM_A_KR:
1688         case IXGBE_DEV_ID_X550EM_A_KR_L:
1689                 media_type = ixgbe_media_type_backplane;
1690                 break;
1691         case IXGBE_DEV_ID_X550EM_X_SFP:
1692         case IXGBE_DEV_ID_X550EM_A_SFP:
1693         case IXGBE_DEV_ID_X550EM_A_SFP_N:
1694         case IXGBE_DEV_ID_X550EM_A_QSFP:
1695         case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1696                 media_type = ixgbe_media_type_fiber;
1697                 break;
1698         case IXGBE_DEV_ID_X550EM_X_1G_T:
1699         case IXGBE_DEV_ID_X550EM_X_10G_T:
1700         case IXGBE_DEV_ID_X550EM_A_10G_T:
1701                 media_type = ixgbe_media_type_copper;
1702                 break;
1703         case IXGBE_DEV_ID_X550EM_A_SGMII:
1704         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1705                 media_type = ixgbe_media_type_backplane;
1706                 hw->phy.type = ixgbe_phy_sgmii;
1707                 break;
1708         case IXGBE_DEV_ID_X550EM_A_1G_T:
1709         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1710                 media_type = ixgbe_media_type_copper;
1711                 break;
1712         default:
1713                 media_type = ixgbe_media_type_unknown;
1714                 break;
1715         }
1716         return media_type;
1717 }
1718
1719 /**
1720  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1721  *  @hw: pointer to hardware structure
1722  *  @linear: true if SFP module is linear
1723  */
1724 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1725 {
1726         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1727
1728         switch (hw->phy.sfp_type) {
1729         case ixgbe_sfp_type_not_present:
1730                 return IXGBE_ERR_SFP_NOT_PRESENT;
1731         case ixgbe_sfp_type_da_cu_core0:
1732         case ixgbe_sfp_type_da_cu_core1:
1733                 *linear = true;
1734                 break;
1735         case ixgbe_sfp_type_srlr_core0:
1736         case ixgbe_sfp_type_srlr_core1:
1737         case ixgbe_sfp_type_da_act_lmt_core0:
1738         case ixgbe_sfp_type_da_act_lmt_core1:
1739         case ixgbe_sfp_type_1g_sx_core0:
1740         case ixgbe_sfp_type_1g_sx_core1:
1741         case ixgbe_sfp_type_1g_lx_core0:
1742         case ixgbe_sfp_type_1g_lx_core1:
1743                 *linear = false;
1744                 break;
1745         case ixgbe_sfp_type_unknown:
1746         case ixgbe_sfp_type_1g_cu_core0:
1747         case ixgbe_sfp_type_1g_cu_core1:
1748         default:
1749                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1750         }
1751
1752         return IXGBE_SUCCESS;
1753 }
1754
1755 /**
1756  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1757  *  @hw: pointer to hardware structure
1758  *
1759  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1760  **/
1761 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1762 {
1763         s32 status;
1764         bool linear;
1765
1766         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1767
1768         status = ixgbe_identify_module_generic(hw);
1769
1770         if (status != IXGBE_SUCCESS)
1771                 return status;
1772
1773         /* Check if SFP module is supported */
1774         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1775
1776         return status;
1777 }
1778
1779 /**
1780  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1781  *  @hw: pointer to hardware structure
1782  */
1783 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1784 {
1785         s32 status;
1786         bool linear;
1787
1788         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1789
1790         /* Check if SFP module is supported */
1791         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1792
1793         if (status != IXGBE_SUCCESS)
1794                 return status;
1795
1796         ixgbe_init_mac_link_ops_X550em(hw);
1797         hw->phy.ops.reset = NULL;
1798
1799         return IXGBE_SUCCESS;
1800 }
1801
1802 /**
1803 *  ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1804 *  internal PHY
1805 *  @hw: pointer to hardware structure
1806 **/
1807 STATIC s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1808 {
1809         s32 status;
1810         u32 link_ctrl;
1811
1812         /* Restart auto-negotiation. */
1813         status = hw->mac.ops.read_iosf_sb_reg(hw,
1814                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1815                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1816
1817         if (status) {
1818                 DEBUGOUT("Auto-negotiation did not complete\n");
1819                 return status;
1820         }
1821
1822         link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1823         status = hw->mac.ops.write_iosf_sb_reg(hw,
1824                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1825                                         IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1826
1827         if (hw->mac.type == ixgbe_mac_X550EM_a) {
1828                 u32 flx_mask_st20;
1829
1830                 /* Indicate to FW that AN restart has been asserted */
1831                 status = hw->mac.ops.read_iosf_sb_reg(hw,
1832                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1833                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1834
1835                 if (status) {
1836                         DEBUGOUT("Auto-negotiation did not complete\n");
1837                         return status;
1838                 }
1839
1840                 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1841                 status = hw->mac.ops.write_iosf_sb_reg(hw,
1842                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1843                                 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1844         }
1845
1846         return status;
1847 }
1848
1849 /**
1850  * ixgbe_setup_sgmii - Set up link for sgmii
1851  * @hw: pointer to hardware structure
1852  */
1853 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1854                              bool autoneg_wait)
1855 {
1856         struct ixgbe_mac_info *mac = &hw->mac;
1857         u32 lval, sval, flx_val;
1858         s32 rc;
1859
1860         rc = mac->ops.read_iosf_sb_reg(hw,
1861                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1862                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1863         if (rc)
1864                 return rc;
1865
1866         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1867         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1868         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1869         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1870         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1871         rc = mac->ops.write_iosf_sb_reg(hw,
1872                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1873                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1874         if (rc)
1875                 return rc;
1876
1877         rc = mac->ops.read_iosf_sb_reg(hw,
1878                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1879                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1880         if (rc)
1881                 return rc;
1882
1883         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1884         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1885         rc = mac->ops.write_iosf_sb_reg(hw,
1886                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1887                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1888         if (rc)
1889                 return rc;
1890
1891         rc = mac->ops.read_iosf_sb_reg(hw,
1892                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1893                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1894         if (rc)
1895                 return rc;
1896
1897         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1898         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1899         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1900         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1901         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1902
1903         rc = mac->ops.write_iosf_sb_reg(hw,
1904                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1905                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1906         if (rc)
1907                 return rc;
1908
1909         rc = ixgbe_restart_an_internal_phy_x550em(hw);
1910         if (rc)
1911                 return rc;
1912
1913         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1914 }
1915
1916 /**
1917  * ixgbe_setup_sgmii_fw - Set up link for sgmii with firmware-controlled PHYs
1918  * @hw: pointer to hardware structure
1919  */
1920 STATIC s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1921                                 bool autoneg_wait)
1922 {
1923         struct ixgbe_mac_info *mac = &hw->mac;
1924         u32 lval, sval, flx_val;
1925         s32 rc;
1926
1927         rc = mac->ops.read_iosf_sb_reg(hw,
1928                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1929                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1930         if (rc)
1931                 return rc;
1932
1933         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1934         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1935         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1936         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1937         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1938         rc = mac->ops.write_iosf_sb_reg(hw,
1939                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1940                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1941         if (rc)
1942                 return rc;
1943
1944         rc = mac->ops.read_iosf_sb_reg(hw,
1945                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1946                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1947         if (rc)
1948                 return rc;
1949
1950         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1951         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1952         rc = mac->ops.write_iosf_sb_reg(hw,
1953                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1954                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1955         if (rc)
1956                 return rc;
1957
1958         rc = mac->ops.write_iosf_sb_reg(hw,
1959                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1960                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1961         if (rc)
1962                 return rc;
1963
1964         rc = mac->ops.read_iosf_sb_reg(hw,
1965                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1966                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1967         if (rc)
1968                 return rc;
1969
1970         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1971         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
1972         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1973         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1974         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1975
1976         rc = mac->ops.write_iosf_sb_reg(hw,
1977                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1978                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1979         if (rc)
1980                 return rc;
1981
1982         rc = ixgbe_restart_an_internal_phy_x550em(hw);
1983
1984         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1985 }
1986
1987 /**
1988  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1989  *  @hw: pointer to hardware structure
1990  */
1991 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1992 {
1993         struct ixgbe_mac_info *mac = &hw->mac;
1994
1995         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1996
1997         switch (hw->mac.ops.get_media_type(hw)) {
1998         case ixgbe_media_type_fiber:
1999                 /* CS4227 does not support autoneg, so disable the laser control
2000                  * functions for SFP+ fiber
2001                  */
2002                 mac->ops.disable_tx_laser = NULL;
2003                 mac->ops.enable_tx_laser = NULL;
2004                 mac->ops.flap_tx_laser = NULL;
2005                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
2006                 mac->ops.set_rate_select_speed =
2007                                         ixgbe_set_soft_rate_select_speed;
2008
2009                 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
2010                     (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
2011                         mac->ops.setup_mac_link =
2012                                                 ixgbe_setup_mac_link_sfp_x550a;
2013                 else
2014                         mac->ops.setup_mac_link =
2015                                                 ixgbe_setup_mac_link_sfp_x550em;
2016                 break;
2017         case ixgbe_media_type_copper:
2018                 if (hw->mac.type == ixgbe_mac_X550EM_a) {
2019                         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2020                             hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
2021                                 mac->ops.setup_link = ixgbe_setup_sgmii_fw;
2022                                 mac->ops.check_link =
2023                                                    ixgbe_check_mac_link_generic;
2024                         } else {
2025                                 mac->ops.setup_link =
2026                                                   ixgbe_setup_mac_link_t_X550em;
2027                         }
2028                 } else {
2029                         mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
2030                         mac->ops.check_link = ixgbe_check_link_t_X550em;
2031                 }
2032                 break;
2033         case ixgbe_media_type_backplane:
2034                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
2035                     hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
2036                         mac->ops.setup_link = ixgbe_setup_sgmii;
2037                 break;
2038         default:
2039                 break;
2040         }
2041 }
2042
2043 /**
2044  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
2045  *  @hw: pointer to hardware structure
2046  *  @speed: pointer to link speed
2047  *  @autoneg: true when autoneg or autotry is enabled
2048  */
2049 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
2050                                        ixgbe_link_speed *speed,
2051                                        bool *autoneg)
2052 {
2053         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
2054
2055
2056         if (hw->phy.type == ixgbe_phy_fw) {
2057                 *autoneg = true;
2058                 *speed = hw->phy.speeds_supported;
2059                 return 0;
2060         }
2061
2062         /* SFP */
2063         if (hw->phy.media_type == ixgbe_media_type_fiber) {
2064
2065                 /* CS4227 SFP must not enable auto-negotiation */
2066                 *autoneg = false;
2067
2068                 /* Check if 1G SFP module. */
2069                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
2070                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
2071                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
2072                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
2073                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
2074                         return IXGBE_SUCCESS;
2075                 }
2076
2077                 /* Link capabilities are based on SFP */
2078                 if (hw->phy.multispeed_fiber)
2079                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
2080                                  IXGBE_LINK_SPEED_1GB_FULL;
2081                 else
2082                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
2083         } else {
2084                 switch (hw->phy.type) {
2085                 case ixgbe_phy_sgmii:
2086                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
2087                         break;
2088                 case ixgbe_phy_x550em_kr:
2089                         if (hw->mac.type == ixgbe_mac_X550EM_a) {
2090                                 /* check different backplane modes */
2091                                 if (hw->phy.nw_mng_if_sel &
2092                                            IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
2093                                         *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
2094                                         break;
2095                                 } else if (hw->device_id ==
2096                                                    IXGBE_DEV_ID_X550EM_A_KR_L) {
2097                                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
2098                                         break;
2099                                 }
2100                         }
2101                         /* fall through */
2102                 default:
2103                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
2104                                  IXGBE_LINK_SPEED_1GB_FULL;
2105                         break;
2106                 }
2107                 *autoneg = true;
2108         }
2109
2110         return IXGBE_SUCCESS;
2111 }
2112
2113 /**
2114  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
2115  * @hw: pointer to hardware structure
2116  * @lsc: pointer to boolean flag which indicates whether external Base T
2117  *       PHY interrupt is lsc
2118  *
2119  * Determime if external Base T PHY interrupt cause is high temperature
2120  * failure alarm or link status change.
2121  *
2122  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2123  * failure alarm, else return PHY access status.
2124  */
2125 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
2126 {
2127         u32 status;
2128         u16 reg;
2129
2130         *lsc = false;
2131
2132         /* Vendor alarm triggered */
2133         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2134                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2135                                       &reg);
2136
2137         if (status != IXGBE_SUCCESS ||
2138             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
2139                 return status;
2140
2141         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
2142         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
2143                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2144                                       &reg);
2145
2146         if (status != IXGBE_SUCCESS ||
2147             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2148             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
2149                 return status;
2150
2151         /* Global alarm triggered */
2152         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
2153                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2154                                       &reg);
2155
2156         if (status != IXGBE_SUCCESS)
2157                 return status;
2158
2159         /* If high temperature failure, then return over temp error and exit */
2160         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
2161                 /* power down the PHY in case the PHY FW didn't already */
2162                 ixgbe_set_copper_phy_power(hw, false);
2163                 return IXGBE_ERR_OVERTEMP;
2164         } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
2165                 /*  device fault alarm triggered */
2166                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
2167                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2168                                           &reg);
2169
2170                 if (status != IXGBE_SUCCESS)
2171                         return status;
2172
2173                 /* if device fault was due to high temp alarm handle and exit */
2174                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
2175                         /* power down the PHY in case the PHY FW didn't */
2176                         ixgbe_set_copper_phy_power(hw, false);
2177                         return IXGBE_ERR_OVERTEMP;
2178                 }
2179         }
2180
2181         /* Vendor alarm 2 triggered */
2182         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2183                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2184
2185         if (status != IXGBE_SUCCESS ||
2186             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
2187                 return status;
2188
2189         /* link connect/disconnect event occurred */
2190         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
2191                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2192
2193         if (status != IXGBE_SUCCESS)
2194                 return status;
2195
2196         /* Indicate LSC */
2197         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2198                 *lsc = true;
2199
2200         return IXGBE_SUCCESS;
2201 }
2202
2203 /**
2204  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2205  * @hw: pointer to hardware structure
2206  *
2207  * Enable link status change and temperature failure alarm for the external
2208  * Base T PHY
2209  *
2210  * Returns PHY access status
2211  */
2212 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2213 {
2214         u32 status;
2215         u16 reg;
2216         bool lsc;
2217
2218         /* Clear interrupt flags */
2219         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2220
2221         /* Enable link status change alarm */
2222
2223         /* Enable the LASI interrupts on X552 devices to receive notifications
2224          * of the link configurations of the external PHY and correspondingly
2225          * support the configuration of the internal iXFI link, since iXFI does
2226          * not support auto-negotiation. This is not required for X553 devices
2227          * having KR support, which performs auto-negotiations and which is used
2228          * as the internal link to the external PHY. Hence adding a check here
2229          * to avoid enabling LASI interrupts for X553 devices.
2230          */
2231         if (hw->mac.type != ixgbe_mac_X550EM_a) {
2232                 status = hw->phy.ops.read_reg(hw,
2233                                         IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2234                                         IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2235
2236                 if (status != IXGBE_SUCCESS)
2237                         return status;
2238
2239                 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2240
2241                 status = hw->phy.ops.write_reg(hw,
2242                                         IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2243                                         IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
2244
2245                 if (status != IXGBE_SUCCESS)
2246                         return status;
2247         }
2248
2249         /* Enable high temperature failure and global fault alarms */
2250         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2251                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2252                                       &reg);
2253
2254         if (status != IXGBE_SUCCESS)
2255                 return status;
2256
2257         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2258                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2259
2260         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2261                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2262                                        reg);
2263
2264         if (status != IXGBE_SUCCESS)
2265                 return status;
2266
2267         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2268         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2269                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2270                                       &reg);
2271
2272         if (status != IXGBE_SUCCESS)
2273                 return status;
2274
2275         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2276                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2277
2278         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2279                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2280                                        reg);
2281
2282         if (status != IXGBE_SUCCESS)
2283                 return status;
2284
2285         /* Enable chip-wide vendor alarm */
2286         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2287                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2288                                       &reg);
2289
2290         if (status != IXGBE_SUCCESS)
2291                 return status;
2292
2293         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2294
2295         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2296                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2297                                        reg);
2298
2299         return status;
2300 }
2301
2302 /**
2303  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2304  *  @hw: pointer to hardware structure
2305  *  @speed: link speed
2306  *
2307  *  Configures the integrated KR PHY.
2308  **/
2309 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2310                                        ixgbe_link_speed speed)
2311 {
2312         s32 status;
2313         u32 reg_val;
2314
2315         status = hw->mac.ops.read_iosf_sb_reg(hw,
2316                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2317                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2318         if (status)
2319                 return status;
2320
2321         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2322         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2323                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2324
2325         /* Advertise 10G support. */
2326         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2327                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2328
2329         /* Advertise 1G support. */
2330         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2331                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2332
2333         status = hw->mac.ops.write_iosf_sb_reg(hw,
2334                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2335                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2336
2337         if (hw->mac.type == ixgbe_mac_X550EM_a) {
2338                 /* Set lane mode  to KR auto negotiation */
2339                 status = hw->mac.ops.read_iosf_sb_reg(hw,
2340                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2341                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2342
2343                 if (status)
2344                         return status;
2345
2346                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2347                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2348                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2349                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2350                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2351
2352                 status = hw->mac.ops.write_iosf_sb_reg(hw,
2353                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2354                                     IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2355         }
2356
2357         return ixgbe_restart_an_internal_phy_x550em(hw);
2358 }
2359
2360 /**
2361  * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs
2362  * @hw: pointer to hardware structure
2363  */
2364 static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw)
2365 {
2366         u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
2367         s32 rc;
2368
2369         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2370                 return IXGBE_SUCCESS;
2371
2372         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store);
2373         if (rc)
2374                 return rc;
2375         memset(store, 0, sizeof(store));
2376
2377         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store);
2378         if (rc)
2379                 return rc;
2380
2381         return ixgbe_setup_fw_link(hw);
2382 }
2383
2384 /**
2385  * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp
2386  * @hw: pointer to hardware structure
2387  */
2388 static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw)
2389 {
2390         u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
2391         s32 rc;
2392
2393         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store);
2394         if (rc)
2395                 return rc;
2396
2397         if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) {
2398                 ixgbe_shutdown_fw_phy(hw);
2399                 return IXGBE_ERR_OVERTEMP;
2400         }
2401         return IXGBE_SUCCESS;
2402 }
2403
2404 /**
2405  *  ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2406  *  @hw: pointer to hardware structure
2407  *
2408  *  Read NW_MNG_IF_SEL register and save field values, and check for valid field
2409  *  values.
2410  **/
2411 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2412 {
2413         /* Save NW management interface connected on board. This is used
2414          * to determine internal PHY mode.
2415          */
2416         hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2417
2418         /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2419          * PHY address. This register field was has only been used for X552.
2420          */
2421         if (hw->mac.type == ixgbe_mac_X550EM_a &&
2422             hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2423                 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2424                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2425                                IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2426         }
2427
2428         return IXGBE_SUCCESS;
2429 }
2430
2431 /**
2432  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2433  *  @hw: pointer to hardware structure
2434  *
2435  *  Initialize any function pointers that were not able to be
2436  *  set during init_shared_code because the PHY/SFP type was
2437  *  not known.  Perform the SFP init if necessary.
2438  */
2439 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2440 {
2441         struct ixgbe_phy_info *phy = &hw->phy;
2442         s32 ret_val;
2443
2444         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2445
2446         hw->mac.ops.set_lan_id(hw);
2447         ixgbe_read_mng_if_sel_x550em(hw);
2448
2449         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2450                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2451                 ixgbe_setup_mux_ctl(hw);
2452                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2453         }
2454
2455         switch (hw->device_id) {
2456         case IXGBE_DEV_ID_X550EM_A_1G_T:
2457         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2458                 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2459                 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2460                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2461                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2462                 phy->ops.check_overtemp = ixgbe_check_overtemp_fw;
2463                 if (hw->bus.lan_id)
2464                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2465                 else
2466                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2467
2468                 break;
2469         case IXGBE_DEV_ID_X550EM_A_10G_T:
2470         case IXGBE_DEV_ID_X550EM_A_SFP:
2471                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2472                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2473                 if (hw->bus.lan_id)
2474                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2475                 else
2476                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2477                 break;
2478         case IXGBE_DEV_ID_X550EM_X_SFP:
2479                 /* set up for CS4227 usage */
2480                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2481                 break;
2482         default:
2483                 break;
2484         }
2485
2486         /* Identify the PHY or SFP module */
2487         ret_val = phy->ops.identify(hw);
2488         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED ||
2489             ret_val == IXGBE_ERR_PHY_ADDR_INVALID)
2490                 return ret_val;
2491
2492         /* Setup function pointers based on detected hardware */
2493         ixgbe_init_mac_link_ops_X550em(hw);
2494         if (phy->sfp_type != ixgbe_sfp_type_unknown)
2495                 phy->ops.reset = NULL;
2496
2497         /* Set functions pointers based on phy type */
2498         switch (hw->phy.type) {
2499         case ixgbe_phy_x550em_kx4:
2500                 phy->ops.setup_link = NULL;
2501                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2502                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2503                 break;
2504         case ixgbe_phy_x550em_kr:
2505                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2506                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2507                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2508                 break;
2509         case ixgbe_phy_x550em_ext_t:
2510                 /* If internal link mode is XFI, then setup iXFI internal link,
2511                  * else setup KR now.
2512                  */
2513                 phy->ops.setup_internal_link =
2514                                               ixgbe_setup_internal_phy_t_x550em;
2515
2516                 /* setup SW LPLU only for first revision of X550EM_x */
2517                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2518                     !(IXGBE_FUSES0_REV_MASK &
2519                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2520                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2521
2522                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2523                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2524                 break;
2525         case ixgbe_phy_sgmii:
2526                 phy->ops.setup_link = NULL;
2527                 break;
2528         case ixgbe_phy_fw:
2529                 phy->ops.setup_link = ixgbe_setup_fw_link;
2530                 phy->ops.reset = ixgbe_reset_phy_fw;
2531                 break;
2532         default:
2533                 break;
2534         }
2535         return ret_val;
2536 }
2537
2538 /**
2539  * ixgbe_set_mdio_speed - Set MDIO clock speed
2540  *  @hw: pointer to hardware structure
2541  */
2542 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2543 {
2544         u32 hlreg0;
2545
2546         switch (hw->device_id) {
2547         case IXGBE_DEV_ID_X550EM_X_10G_T:
2548         case IXGBE_DEV_ID_X550EM_A_SGMII:
2549         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2550         case IXGBE_DEV_ID_X550EM_A_10G_T:
2551         case IXGBE_DEV_ID_X550EM_A_SFP:
2552         case IXGBE_DEV_ID_X550EM_A_QSFP:
2553                 /* Config MDIO clock speed before the first MDIO PHY access */
2554                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2555                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2556                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2557                 break;
2558         case IXGBE_DEV_ID_X550EM_A_1G_T:
2559         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2560                 /* Select fast MDIO clock speed for these devices */
2561                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2562                 hlreg0 |= IXGBE_HLREG0_MDCSPD;
2563                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2564                 break;
2565         default:
2566                 break;
2567         }
2568 }
2569
2570 /**
2571  *  ixgbe_reset_hw_X550em - Perform hardware reset
2572  *  @hw: pointer to hardware structure
2573  *
2574  *  Resets the hardware by resetting the transmit and receive units, masks
2575  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2576  *  reset.
2577  */
2578 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2579 {
2580         ixgbe_link_speed link_speed;
2581         s32 status;
2582         u32 ctrl = 0;
2583         u32 i;
2584         bool link_up = false;
2585
2586         DEBUGFUNC("ixgbe_reset_hw_X550em");
2587
2588         /* Call adapter stop to disable Tx/Rx and clear interrupts */
2589         status = hw->mac.ops.stop_adapter(hw);
2590         if (status != IXGBE_SUCCESS)
2591                 return status;
2592
2593         /* flush pending Tx transactions */
2594         ixgbe_clear_tx_pending(hw);
2595
2596         ixgbe_set_mdio_speed(hw);
2597
2598         /* PHY ops must be identified and initialized prior to reset */
2599         status = hw->phy.ops.init(hw);
2600
2601         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2602                 return status;
2603
2604         /* start the external PHY */
2605         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2606                 status = ixgbe_init_ext_t_x550em(hw);
2607                 if (status)
2608                         return status;
2609         }
2610
2611         /* Setup SFP module if there is one present. */
2612         if (hw->phy.sfp_setup_needed) {
2613                 status = hw->mac.ops.setup_sfp(hw);
2614                 hw->phy.sfp_setup_needed = false;
2615         }
2616
2617         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2618                 return status;
2619
2620         /* Reset PHY */
2621         if (!hw->phy.reset_disable && hw->phy.ops.reset) {
2622                 if (hw->phy.ops.reset(hw) == IXGBE_ERR_OVERTEMP)
2623                         return IXGBE_ERR_OVERTEMP;
2624         }
2625
2626 mac_reset_top:
2627         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2628          * If link reset is used when link is up, it might reset the PHY when
2629          * mng is using it.  If link is down or the flag to force full link
2630          * reset is set, then perform link reset.
2631          */
2632         ctrl = IXGBE_CTRL_LNK_RST;
2633         if (!hw->force_full_reset) {
2634                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2635                 if (link_up)
2636                         ctrl = IXGBE_CTRL_RST;
2637         }
2638
2639         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2640         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2641         IXGBE_WRITE_FLUSH(hw);
2642
2643         /* Poll for reset bit to self-clear meaning reset is complete */
2644         for (i = 0; i < 10; i++) {
2645                 usec_delay(1);
2646                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2647                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2648                         break;
2649         }
2650
2651         if (ctrl & IXGBE_CTRL_RST_MASK) {
2652                 status = IXGBE_ERR_RESET_FAILED;
2653                 DEBUGOUT("Reset polling failed to complete.\n");
2654         }
2655
2656         msec_delay(50);
2657
2658         /* Double resets are required for recovery from certain error
2659          * conditions.  Between resets, it is necessary to stall to
2660          * allow time for any pending HW events to complete.
2661          */
2662         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2663                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2664                 goto mac_reset_top;
2665         }
2666
2667         /* Store the permanent mac address */
2668         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2669
2670         /* Store MAC address from RAR0, clear receive address registers, and
2671          * clear the multicast table.  Also reset num_rar_entries to 128,
2672          * since we modify this value when programming the SAN MAC address.
2673          */
2674         hw->mac.num_rar_entries = 128;
2675         hw->mac.ops.init_rx_addrs(hw);
2676
2677         ixgbe_set_mdio_speed(hw);
2678
2679         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2680                 ixgbe_setup_mux_ctl(hw);
2681
2682         return status;
2683 }
2684
2685 /**
2686  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2687  * @hw: pointer to hardware structure
2688  */
2689 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2690 {
2691         u32 status;
2692         u16 reg;
2693
2694         status = hw->phy.ops.read_reg(hw,
2695                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2696                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2697                                       &reg);
2698
2699         if (status != IXGBE_SUCCESS)
2700                 return status;
2701
2702         /* If PHY FW reset completed bit is set then this is the first
2703          * SW instance after a power on so the PHY FW must be un-stalled.
2704          */
2705         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2706                 status = hw->phy.ops.read_reg(hw,
2707                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2708                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2709                                         &reg);
2710
2711                 if (status != IXGBE_SUCCESS)
2712                         return status;
2713
2714                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2715
2716                 status = hw->phy.ops.write_reg(hw,
2717                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2718                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2719                                         reg);
2720
2721                 if (status != IXGBE_SUCCESS)
2722                         return status;
2723         }
2724
2725         return status;
2726 }
2727
2728 /**
2729  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
2730  *  @hw: pointer to hardware structure
2731  *
2732  *  Configures the integrated KR PHY for X550EM_x.
2733  **/
2734 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2735 {
2736         if (hw->mac.type != ixgbe_mac_X550EM_x)
2737                 return IXGBE_SUCCESS;
2738
2739         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2740 }
2741
2742 /**
2743  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2744  *  @hw: pointer to hardware structure
2745  *
2746  *  Configure the external PHY and the integrated KR PHY for SFP support.
2747  **/
2748 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2749                                     ixgbe_link_speed speed,
2750                                     bool autoneg_wait_to_complete)
2751 {
2752         s32 ret_val;
2753         u16 reg_slice, reg_val;
2754         bool setup_linear = false;
2755         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2756
2757         /* Check if SFP module is supported and linear */
2758         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2759
2760         /* If no SFP module present, then return success. Return success since
2761          * there is no reason to configure CS4227 and SFP not present error is
2762          * not excepted in the setup MAC link flow.
2763          */
2764         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2765                 return IXGBE_SUCCESS;
2766
2767         if (ret_val != IXGBE_SUCCESS)
2768                 return ret_val;
2769
2770         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2771                 /* Configure CS4227 LINE side to 10G SR. */
2772                 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
2773                             (hw->bus.lan_id << 12);
2774                 reg_val = IXGBE_CS4227_SPEED_10G;
2775                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2776                                                   reg_val);
2777
2778                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2779                             (hw->bus.lan_id << 12);
2780                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2781                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2782                                                   reg_val);
2783
2784                 /* Configure CS4227 for HOST connection rate then type. */
2785                 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
2786                             (hw->bus.lan_id << 12);
2787                 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
2788                 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
2789                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2790                                                   reg_val);
2791
2792                 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
2793                             (hw->bus.lan_id << 12);
2794                 if (setup_linear)
2795                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2796                 else
2797                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2798                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2799                                                   reg_val);
2800
2801                 /* Setup XFI internal link. */
2802                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2803         } else {
2804                 /* Configure internal PHY for KR/KX. */
2805                 ixgbe_setup_kr_speed_x550em(hw, speed);
2806
2807                 /* Configure CS4227 LINE side to proper mode. */
2808                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2809                             (hw->bus.lan_id << 12);
2810                 if (setup_linear)
2811                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2812                 else
2813                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2814                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2815                                                   reg_val);
2816         }
2817         return ret_val;
2818 }
2819
2820 /**
2821  *  ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
2822  *  @hw: pointer to hardware structure
2823  *  @speed: the link speed to force
2824  *
2825  *  Configures the integrated PHY for native SFI mode. Used to connect the
2826  *  internal PHY directly to an SFP cage, without autonegotiation.
2827  **/
2828 STATIC s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2829 {
2830         struct ixgbe_mac_info *mac = &hw->mac;
2831         s32 status;
2832         u32 reg_val;
2833
2834         /* Disable all AN and force speed to 10G Serial. */
2835         status = mac->ops.read_iosf_sb_reg(hw,
2836                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2837                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2838         if (status != IXGBE_SUCCESS)
2839                 return status;
2840
2841         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2842         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2843         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2844         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2845
2846         /* Select forced link speed for internal PHY. */
2847         switch (*speed) {
2848         case IXGBE_LINK_SPEED_10GB_FULL:
2849                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
2850                 break;
2851         case IXGBE_LINK_SPEED_1GB_FULL:
2852                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2853                 break;
2854         default:
2855                 /* Other link speeds are not supported by internal PHY. */
2856                 return IXGBE_ERR_LINK_SETUP;
2857         }
2858
2859         status = mac->ops.write_iosf_sb_reg(hw,
2860                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2861                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2862
2863         /* Toggle port SW reset by AN reset. */
2864         status = ixgbe_restart_an_internal_phy_x550em(hw);
2865
2866         return status;
2867 }
2868
2869 /**
2870  *  ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2871  *  @hw: pointer to hardware structure
2872  *
2873  *  Configure the the integrated PHY for SFP support.
2874  **/
2875 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2876                                     ixgbe_link_speed speed,
2877                                     bool autoneg_wait_to_complete)
2878 {
2879         s32 ret_val;
2880         u16 reg_phy_ext;
2881         bool setup_linear = false;
2882         u32 reg_slice, reg_phy_int, slice_offset;
2883
2884         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2885
2886         /* Check if SFP module is supported and linear */
2887         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2888
2889         /* If no SFP module present, then return success. Return success since
2890          * SFP not present error is not excepted in the setup MAC link flow.
2891          */
2892         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2893                 return IXGBE_SUCCESS;
2894
2895         if (ret_val != IXGBE_SUCCESS)
2896                 return ret_val;
2897
2898         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2899                 /* Configure internal PHY for native SFI based on module type */
2900                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2901                                    IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2902                                    IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_phy_int);
2903
2904                 if (ret_val != IXGBE_SUCCESS)
2905                         return ret_val;
2906
2907                 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
2908                 if (!setup_linear)
2909                         reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
2910
2911                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2912                                    IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2913                                    IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2914
2915                 if (ret_val != IXGBE_SUCCESS)
2916                         return ret_val;
2917
2918                 /* Setup SFI internal link. */
2919                 ret_val = ixgbe_setup_sfi_x550a(hw, &speed);
2920         } else {
2921                 /* Configure internal PHY for KR/KX. */
2922                 ixgbe_setup_kr_speed_x550em(hw, speed);
2923
2924                 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2925                         /* Find Address */
2926                         DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2927                         return IXGBE_ERR_PHY_ADDR_INVALID;
2928                 }
2929
2930                 /* Get external PHY SKU id */
2931                 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,
2932                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2933
2934                 if (ret_val != IXGBE_SUCCESS)
2935                         return ret_val;
2936
2937                 /* When configuring quad port CS4223, the MAC instance is part
2938                  * of the slice offset.
2939                  */
2940                 if (reg_phy_ext == IXGBE_CS4223_SKU_ID)
2941                         slice_offset = (hw->bus.lan_id +
2942                                         (hw->bus.instance_id << 1)) << 12;
2943                 else
2944                         slice_offset = hw->bus.lan_id << 12;
2945
2946                 /* Configure CS4227/CS4223 LINE side to proper mode. */
2947                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2948                 if (setup_linear)
2949                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2950                 else
2951                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2952                 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2953                                          IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2954         }
2955         return ret_val;
2956 }
2957
2958 /**
2959  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2960  *  @hw: pointer to hardware structure
2961  *
2962  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2963  **/
2964 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2965 {
2966         struct ixgbe_mac_info *mac = &hw->mac;
2967         s32 status;
2968         u32 reg_val;
2969
2970         /* Disable training protocol FSM. */
2971         status = mac->ops.read_iosf_sb_reg(hw,
2972                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2973                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2974         if (status != IXGBE_SUCCESS)
2975                 return status;
2976         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2977         status = mac->ops.write_iosf_sb_reg(hw,
2978                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2979                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2980         if (status != IXGBE_SUCCESS)
2981                 return status;
2982
2983         /* Disable Flex from training TXFFE. */
2984         status = mac->ops.read_iosf_sb_reg(hw,
2985                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2986                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2987         if (status != IXGBE_SUCCESS)
2988                 return status;
2989         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2990         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2991         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2992         status = mac->ops.write_iosf_sb_reg(hw,
2993                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2994                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2995         if (status != IXGBE_SUCCESS)
2996                 return status;
2997         status = mac->ops.read_iosf_sb_reg(hw,
2998                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2999                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3000         if (status != IXGBE_SUCCESS)
3001                 return status;
3002         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
3003         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
3004         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
3005         status = mac->ops.write_iosf_sb_reg(hw,
3006                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
3007                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3008         if (status != IXGBE_SUCCESS)
3009                 return status;
3010
3011         /* Enable override for coefficients. */
3012         status = mac->ops.read_iosf_sb_reg(hw,
3013                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
3014                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3015         if (status != IXGBE_SUCCESS)
3016                 return status;
3017         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
3018         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
3019         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
3020         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
3021         status = mac->ops.write_iosf_sb_reg(hw,
3022                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
3023                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3024         return status;
3025 }
3026
3027 /**
3028  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
3029  *  @hw: pointer to hardware structure
3030  *  @speed: the link speed to force
3031  *
3032  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
3033  *  internal and external PHY at a specific speed, without autonegotiation.
3034  **/
3035 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
3036 {
3037         struct ixgbe_mac_info *mac = &hw->mac;
3038         s32 status;
3039         u32 reg_val;
3040
3041         /* iXFI is only supported with X552 */
3042         if (mac->type != ixgbe_mac_X550EM_x)
3043                 return IXGBE_ERR_LINK_SETUP;
3044
3045         /* Disable AN and force speed to 10G Serial. */
3046         status = mac->ops.read_iosf_sb_reg(hw,
3047                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3048                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3049         if (status != IXGBE_SUCCESS)
3050                 return status;
3051
3052         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3053         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3054
3055         /* Select forced link speed for internal PHY. */
3056         switch (*speed) {
3057         case IXGBE_LINK_SPEED_10GB_FULL:
3058                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3059                 break;
3060         case IXGBE_LINK_SPEED_1GB_FULL:
3061                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
3062                 break;
3063         default:
3064                 /* Other link speeds are not supported by internal KR PHY. */
3065                 return IXGBE_ERR_LINK_SETUP;
3066         }
3067
3068         status = mac->ops.write_iosf_sb_reg(hw,
3069                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3070                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3071         if (status != IXGBE_SUCCESS)
3072                 return status;
3073
3074         /* Additional configuration needed for x550em_x */
3075         if (hw->mac.type == ixgbe_mac_X550EM_x) {
3076                 status = ixgbe_setup_ixfi_x550em_x(hw);
3077                 if (status != IXGBE_SUCCESS)
3078                         return status;
3079         }
3080
3081         /* Toggle port SW reset by AN reset. */
3082         status = ixgbe_restart_an_internal_phy_x550em(hw);
3083
3084         return status;
3085 }
3086
3087 /**
3088  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
3089  * @hw: address of hardware structure
3090  * @link_up: address of boolean to indicate link status
3091  *
3092  * Returns error code if unable to get link status.
3093  */
3094 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
3095 {
3096         u32 ret;
3097         u16 autoneg_status;
3098
3099         *link_up = false;
3100
3101         /* read this twice back to back to indicate current status */
3102         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3103                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3104                                    &autoneg_status);
3105         if (ret != IXGBE_SUCCESS)
3106                 return ret;
3107
3108         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3109                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3110                                    &autoneg_status);
3111         if (ret != IXGBE_SUCCESS)
3112                 return ret;
3113
3114         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
3115
3116         return IXGBE_SUCCESS;
3117 }
3118
3119 /**
3120  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
3121  * @hw: point to hardware structure
3122  *
3123  * Configures the link between the integrated KR PHY and the external X557 PHY
3124  * The driver will call this function when it gets a link status change
3125  * interrupt from the X557 PHY. This function configures the link speed
3126  * between the PHYs to match the link speed of the BASE-T link.
3127  *
3128  * A return of a non-zero value indicates an error, and the base driver should
3129  * not report link up.
3130  */
3131 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
3132 {
3133         ixgbe_link_speed force_speed;
3134         bool link_up;
3135         u32 status;
3136         u16 speed;
3137
3138         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3139                 return IXGBE_ERR_CONFIG;
3140
3141         if (hw->mac.type == ixgbe_mac_X550EM_x &&
3142             !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3143                 /* If link is down, there is no setup necessary so return  */
3144                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3145                 if (status != IXGBE_SUCCESS)
3146                         return status;
3147
3148                 if (!link_up)
3149                         return IXGBE_SUCCESS;
3150
3151                 status = hw->phy.ops.read_reg(hw,
3152                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3153                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3154                                               &speed);
3155                 if (status != IXGBE_SUCCESS)
3156                         return status;
3157
3158                 /* If link is still down - no setup is required so return */
3159                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3160                 if (status != IXGBE_SUCCESS)
3161                         return status;
3162                 if (!link_up)
3163                         return IXGBE_SUCCESS;
3164
3165                 /* clear everything but the speed and duplex bits */
3166                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
3167
3168                 switch (speed) {
3169                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
3170                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3171                         break;
3172                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
3173                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3174                         break;
3175                 default:
3176                         /* Internal PHY does not support anything else */
3177                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
3178                 }
3179
3180                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
3181         } else {
3182                 speed = IXGBE_LINK_SPEED_10GB_FULL |
3183                         IXGBE_LINK_SPEED_1GB_FULL;
3184                 return ixgbe_setup_kr_speed_x550em(hw, speed);
3185         }
3186 }
3187
3188 /**
3189  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
3190  *  @hw: pointer to hardware structure
3191  *
3192  *  Configures the integrated KR PHY to use internal loopback mode.
3193  **/
3194 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
3195 {
3196         s32 status;
3197         u32 reg_val;
3198
3199         /* Disable AN and force speed to 10G Serial. */
3200         status = hw->mac.ops.read_iosf_sb_reg(hw,
3201                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3202                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3203         if (status != IXGBE_SUCCESS)
3204                 return status;
3205         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3206         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3207         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3208         status = hw->mac.ops.write_iosf_sb_reg(hw,
3209                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3210                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3211         if (status != IXGBE_SUCCESS)
3212                 return status;
3213
3214         /* Set near-end loopback clocks. */
3215         status = hw->mac.ops.read_iosf_sb_reg(hw,
3216                                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3217                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3218         if (status != IXGBE_SUCCESS)
3219                 return status;
3220         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3221         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3222         status = hw->mac.ops.write_iosf_sb_reg(hw,
3223                                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3224                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3225         if (status != IXGBE_SUCCESS)
3226                 return status;
3227
3228         /* Set loopback enable. */
3229         status = hw->mac.ops.read_iosf_sb_reg(hw,
3230                                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3231                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3232         if (status != IXGBE_SUCCESS)
3233                 return status;
3234         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3235         status = hw->mac.ops.write_iosf_sb_reg(hw,
3236                                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3237                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3238         if (status != IXGBE_SUCCESS)
3239                 return status;
3240
3241         /* Training bypass. */
3242         status = hw->mac.ops.read_iosf_sb_reg(hw,
3243                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3244                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3245         if (status != IXGBE_SUCCESS)
3246                 return status;
3247         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3248         status = hw->mac.ops.write_iosf_sb_reg(hw,
3249                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3250                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3251
3252         return status;
3253 }
3254
3255 /**
3256  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3257  *  assuming that the semaphore is already obtained.
3258  *  @hw: pointer to hardware structure
3259  *  @offset: offset of  word in the EEPROM to read
3260  *  @data: word read from the EEPROM
3261  *
3262  *  Reads a 16 bit word from the EEPROM using the hostif.
3263  **/
3264 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
3265 {
3266         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3267         struct ixgbe_hic_read_shadow_ram buffer;
3268         s32 status;
3269
3270         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3271         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3272         buffer.hdr.req.buf_lenh = 0;
3273         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3274         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3275
3276         /* convert offset from words to bytes */
3277         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3278         /* one word */
3279         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3280
3281         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3282         if (status)
3283                 return status;
3284
3285         status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3286                                     IXGBE_HI_COMMAND_TIMEOUT);
3287         if (!status) {
3288                 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3289                                                   FW_NVM_DATA_OFFSET);
3290         }
3291
3292         hw->mac.ops.release_swfw_sync(hw, mask);
3293         return status;
3294 }
3295
3296 /**
3297  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3298  *  @hw: pointer to hardware structure
3299  *  @offset: offset of  word in the EEPROM to read
3300  *  @words: number of words
3301  *  @data: word(s) read from the EEPROM
3302  *
3303  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
3304  **/
3305 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3306                                      u16 offset, u16 words, u16 *data)
3307 {
3308         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3309         struct ixgbe_hic_read_shadow_ram buffer;
3310         u32 current_word = 0;
3311         u16 words_to_read;
3312         s32 status;
3313         u32 i;
3314
3315         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3316
3317         /* Take semaphore for the entire operation. */
3318         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3319         if (status) {
3320                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3321                 return status;
3322         }
3323
3324         while (words) {
3325                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3326                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3327                 else
3328                         words_to_read = words;
3329
3330                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3331                 buffer.hdr.req.buf_lenh = 0;
3332                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3333                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3334
3335                 /* convert offset from words to bytes */
3336                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3337                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3338
3339                 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3340                                             IXGBE_HI_COMMAND_TIMEOUT);
3341
3342                 if (status) {
3343                         DEBUGOUT("Host interface command failed\n");
3344                         goto out;
3345                 }
3346
3347                 for (i = 0; i < words_to_read; i++) {
3348                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3349                                   2 * i;
3350                         u32 value = IXGBE_READ_REG(hw, reg);
3351
3352                         data[current_word] = (u16)(value & 0xffff);
3353                         current_word++;
3354                         i++;
3355                         if (i < words_to_read) {
3356                                 value >>= 16;
3357                                 data[current_word] = (u16)(value & 0xffff);
3358                                 current_word++;
3359                         }
3360                 }
3361                 words -= words_to_read;
3362         }
3363
3364 out:
3365         hw->mac.ops.release_swfw_sync(hw, mask);
3366         return status;
3367 }
3368
3369 /**
3370  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3371  *  @hw: pointer to hardware structure
3372  *  @offset: offset of  word in the EEPROM to write
3373  *  @data: word write to the EEPROM
3374  *
3375  *  Write a 16 bit word to the EEPROM using the hostif.
3376  **/
3377 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3378                                     u16 data)
3379 {
3380         s32 status;
3381         struct ixgbe_hic_write_shadow_ram buffer;
3382
3383         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3384
3385         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3386         buffer.hdr.req.buf_lenh = 0;
3387         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3388         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3389
3390          /* one word */
3391         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3392         buffer.data = data;
3393         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3394
3395         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3396                                               sizeof(buffer),
3397                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3398
3399         return status;
3400 }
3401
3402 /**
3403  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3404  *  @hw: pointer to hardware structure
3405  *  @offset: offset of  word in the EEPROM to write
3406  *  @data: word write to the EEPROM
3407  *
3408  *  Write a 16 bit word to the EEPROM using the hostif.
3409  **/
3410 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3411                                u16 data)
3412 {
3413         s32 status = IXGBE_SUCCESS;
3414
3415         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3416
3417         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3418             IXGBE_SUCCESS) {
3419                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3420                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3421         } else {
3422                 DEBUGOUT("write ee hostif failed to get semaphore");
3423                 status = IXGBE_ERR_SWFW_SYNC;
3424         }
3425
3426         return status;
3427 }
3428
3429 /**
3430  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3431  *  @hw: pointer to hardware structure
3432  *  @offset: offset of  word in the EEPROM to write
3433  *  @words: number of words
3434  *  @data: word(s) write to the EEPROM
3435  *
3436  *  Write a 16 bit word(s) to the EEPROM using the hostif.
3437  **/
3438 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3439                                       u16 offset, u16 words, u16 *data)
3440 {
3441         s32 status = IXGBE_SUCCESS;
3442         u32 i = 0;
3443
3444         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3445
3446         /* Take semaphore for the entire operation. */
3447         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3448         if (status != IXGBE_SUCCESS) {
3449                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3450                 goto out;
3451         }
3452
3453         for (i = 0; i < words; i++) {
3454                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3455                                                          data[i]);
3456
3457                 if (status != IXGBE_SUCCESS) {
3458                         DEBUGOUT("Eeprom buffered write failed\n");
3459                         break;
3460                 }
3461         }
3462
3463         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3464 out:
3465
3466         return status;
3467 }
3468
3469 /**
3470  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3471  * @hw: pointer to hardware structure
3472  * @ptr: pointer offset in eeprom
3473  * @size: size of section pointed by ptr, if 0 first word will be used as size
3474  * @csum: address of checksum to update
3475  *
3476  * Returns error status for any failure
3477  */
3478 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3479                                    u16 size, u16 *csum, u16 *buffer,
3480                                    u32 buffer_size)
3481 {
3482         u16 buf[256];
3483         s32 status;
3484         u16 length, bufsz, i, start;
3485         u16 *local_buffer;
3486
3487         bufsz = sizeof(buf) / sizeof(buf[0]);
3488
3489         /* Read a chunk at the pointer location */
3490         if (!buffer) {
3491                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3492                 if (status) {
3493                         DEBUGOUT("Failed to read EEPROM image\n");
3494                         return status;
3495                 }
3496                 local_buffer = buf;
3497         } else {
3498                 if (buffer_size < ptr)
3499                         return  IXGBE_ERR_PARAM;
3500                 local_buffer = &buffer[ptr];
3501         }
3502
3503         if (size) {
3504                 start = 0;
3505                 length = size;
3506         } else {
3507                 start = 1;
3508                 length = local_buffer[0];
3509
3510                 /* Skip pointer section if length is invalid. */
3511                 if (length == 0xFFFF || length == 0 ||
3512                     (ptr + length) >= hw->eeprom.word_size)
3513                         return IXGBE_SUCCESS;
3514         }
3515
3516         if (buffer && ((u32)start + (u32)length > buffer_size))
3517                 return IXGBE_ERR_PARAM;
3518
3519         for (i = start; length; i++, length--) {
3520                 if (i == bufsz && !buffer) {
3521                         ptr += bufsz;
3522                         i = 0;
3523                         if (length < bufsz)
3524                                 bufsz = length;
3525
3526                         /* Read a chunk at the pointer location */
3527                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3528                                                                   bufsz, buf);
3529                         if (status) {
3530                                 DEBUGOUT("Failed to read EEPROM image\n");
3531                                 return status;
3532                         }
3533                 }
3534                 *csum += local_buffer[i];
3535         }
3536         return IXGBE_SUCCESS;
3537 }
3538
3539 /**
3540  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3541  *  @hw: pointer to hardware structure
3542  *  @buffer: pointer to buffer containing calculated checksum
3543  *  @buffer_size: size of buffer
3544  *
3545  *  Returns a negative error code on error, or the 16-bit checksum
3546  **/
3547 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3548 {
3549         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3550         u16 *local_buffer;
3551         s32 status;
3552         u16 checksum = 0;
3553         u16 pointer, i, size;
3554
3555         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3556
3557         hw->eeprom.ops.init_params(hw);
3558
3559         if (!buffer) {
3560                 /* Read pointer area */
3561                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3562                                                      IXGBE_EEPROM_LAST_WORD + 1,
3563                                                      eeprom_ptrs);
3564                 if (status) {
3565                         DEBUGOUT("Failed to read EEPROM image\n");
3566                         return status;
3567                 }
3568                 local_buffer = eeprom_ptrs;
3569         } else {
3570                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3571                         return IXGBE_ERR_PARAM;
3572                 local_buffer = buffer;
3573         }
3574
3575         /*
3576          * For X550 hardware include 0x0-0x41 in the checksum, skip the
3577          * checksum word itself
3578          */
3579         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3580                 if (i != IXGBE_EEPROM_CHECKSUM)
3581                         checksum += local_buffer[i];
3582
3583         /*
3584          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
3585          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3586          */
3587         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3588                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3589                         continue;
3590
3591                 pointer = local_buffer[i];
3592
3593                 /* Skip pointer section if the pointer is invalid. */
3594                 if (pointer == 0xFFFF || pointer == 0 ||
3595                     pointer >= hw->eeprom.word_size)
3596                         continue;
3597
3598                 switch (i) {
3599                 case IXGBE_PCIE_GENERAL_PTR:
3600                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3601                         break;
3602                 case IXGBE_PCIE_CONFIG0_PTR:
3603                 case IXGBE_PCIE_CONFIG1_PTR:
3604                         size = IXGBE_PCIE_CONFIG_SIZE;
3605                         break;
3606                 default:
3607                         size = 0;
3608                         break;
3609                 }
3610
3611                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3612                                                 buffer, buffer_size);
3613                 if (status)
3614                         return status;
3615         }
3616
3617         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3618
3619         return (s32)checksum;
3620 }
3621
3622 /**
3623  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3624  *  @hw: pointer to hardware structure
3625  *
3626  *  Returns a negative error code on error, or the 16-bit checksum
3627  **/
3628 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3629 {
3630         return ixgbe_calc_checksum_X550(hw, NULL, 0);
3631 }
3632
3633 /**
3634  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3635  *  @hw: pointer to hardware structure
3636  *  @checksum_val: calculated checksum
3637  *
3638  *  Performs checksum calculation and validates the EEPROM checksum.  If the
3639  *  caller does not need checksum_val, the value can be NULL.
3640  **/
3641 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3642 {
3643         s32 status;
3644         u16 checksum;
3645         u16 read_checksum = 0;
3646
3647         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3648
3649         /* Read the first word from the EEPROM. If this times out or fails, do
3650          * not continue or we could be in for a very long wait while every
3651          * EEPROM read fails
3652          */
3653         status = hw->eeprom.ops.read(hw, 0, &checksum);
3654         if (status) {
3655                 DEBUGOUT("EEPROM read failed\n");
3656                 return status;
3657         }
3658
3659         status = hw->eeprom.ops.calc_checksum(hw);
3660         if (status < 0)
3661                 return status;
3662
3663         checksum = (u16)(status & 0xffff);
3664
3665         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3666                                            &read_checksum);
3667         if (status)
3668                 return status;
3669
3670         /* Verify read checksum from EEPROM is the same as
3671          * calculated checksum
3672          */
3673         if (read_checksum != checksum) {
3674                 status = IXGBE_ERR_EEPROM_CHECKSUM;
3675                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3676                              "Invalid EEPROM checksum");
3677         }
3678
3679         /* If the user cares, return the calculated checksum */
3680         if (checksum_val)
3681                 *checksum_val = checksum;
3682
3683         return status;
3684 }
3685
3686 /**
3687  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3688  * @hw: pointer to hardware structure
3689  *
3690  * After writing EEPROM to shadow RAM using EEWR register, software calculates
3691  * checksum and updates the EEPROM and instructs the hardware to update
3692  * the flash.
3693  **/
3694 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3695 {
3696         s32 status;
3697         u16 checksum = 0;
3698
3699         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3700
3701         /* Read the first word from the EEPROM. If this times out or fails, do
3702          * not continue or we could be in for a very long wait while every
3703          * EEPROM read fails
3704          */
3705         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3706         if (status) {
3707                 DEBUGOUT("EEPROM read failed\n");
3708                 return status;
3709         }
3710
3711         status = ixgbe_calc_eeprom_checksum_X550(hw);
3712         if (status < 0)
3713                 return status;
3714
3715         checksum = (u16)(status & 0xffff);
3716
3717         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3718                                             checksum);
3719         if (status)
3720                 return status;
3721
3722         status = ixgbe_update_flash_X550(hw);
3723
3724         return status;
3725 }
3726
3727 /**
3728  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3729  *  @hw: pointer to hardware structure
3730  *
3731  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3732  **/
3733 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3734 {
3735         s32 status = IXGBE_SUCCESS;
3736         union ixgbe_hic_hdr2 buffer;
3737
3738         DEBUGFUNC("ixgbe_update_flash_X550");
3739
3740         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3741         buffer.req.buf_lenh = 0;
3742         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3743         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3744
3745         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3746                                               sizeof(buffer),
3747                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3748
3749         return status;
3750 }
3751
3752 /**
3753  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3754  *  @hw: pointer to hardware structure
3755  *
3756  *  Determines physical layer capabilities of the current configuration.
3757  **/
3758 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3759 {
3760         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3761         u16 ext_ability = 0;
3762
3763         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3764
3765         hw->phy.ops.identify(hw);
3766
3767         switch (hw->phy.type) {
3768         case ixgbe_phy_x550em_kr:
3769                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3770                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3771                 break;
3772         case ixgbe_phy_x550em_kx4:
3773                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3774                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3775                 break;
3776         case ixgbe_phy_x550em_ext_t:
3777                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3778                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3779                                      &ext_ability);
3780                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3781                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3782                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3783                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3784                 break;
3785         case ixgbe_phy_fw:
3786                 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_1GB_FULL)
3787                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3788                 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_100_FULL)
3789                         physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
3790                 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_10_FULL)
3791                         physical_layer |= IXGBE_PHYSICAL_LAYER_10BASE_T;
3792                 break;
3793         default:
3794                 break;
3795         }
3796
3797         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3798                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3799
3800         return physical_layer;
3801 }
3802
3803 /**
3804  * ixgbe_get_bus_info_x550em - Set PCI bus info
3805  * @hw: pointer to hardware structure
3806  *
3807  * Sets bus link width and speed to unknown because X550em is
3808  * not a PCI device.
3809  **/
3810 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3811 {
3812
3813         DEBUGFUNC("ixgbe_get_bus_info_x550em");
3814
3815         hw->bus.width = ixgbe_bus_width_unknown;
3816         hw->bus.speed = ixgbe_bus_speed_unknown;
3817
3818         hw->mac.ops.set_lan_id(hw);
3819
3820         return IXGBE_SUCCESS;
3821 }
3822
3823 /**
3824  * ixgbe_disable_rx_x550 - Disable RX unit
3825  *
3826  * Enables the Rx DMA unit for x550
3827  **/
3828 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3829 {
3830         u32 rxctrl, pfdtxgswc;
3831         s32 status;
3832         struct ixgbe_hic_disable_rxen fw_cmd;
3833
3834         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3835
3836         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3837         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3838                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3839                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3840                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3841                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3842                         hw->mac.set_lben = true;
3843                 } else {
3844                         hw->mac.set_lben = false;
3845                 }
3846
3847                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3848                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3849                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3850                 fw_cmd.port_number = (u8)hw->bus.lan_id;
3851
3852                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3853                                         sizeof(struct ixgbe_hic_disable_rxen),
3854                                         IXGBE_HI_COMMAND_TIMEOUT, true);
3855
3856                 /* If we fail - disable RX using register write */
3857                 if (status) {
3858                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3859                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3860                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3861                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3862                         }
3863                 }
3864         }
3865 }
3866
3867 /**
3868  * ixgbe_enter_lplu_x550em - Transition to low power states
3869  *  @hw: pointer to hardware structure
3870  *
3871  * Configures Low Power Link Up on transition to low power states
3872  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3873  * X557 PHY immediately prior to entering LPLU.
3874  **/
3875 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3876 {
3877         u16 an_10g_cntl_reg, autoneg_reg, speed;
3878         s32 status;
3879         ixgbe_link_speed lcd_speed;
3880         u32 save_autoneg;
3881         bool link_up;
3882
3883         /* SW LPLU not required on later HW revisions. */
3884         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3885             (IXGBE_FUSES0_REV_MASK &
3886              IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3887                 return IXGBE_SUCCESS;
3888
3889         /* If blocked by MNG FW, then don't restart AN */
3890         if (ixgbe_check_reset_blocked(hw))
3891                 return IXGBE_SUCCESS;
3892
3893         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3894         if (status != IXGBE_SUCCESS)
3895                 return status;
3896
3897         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3898
3899         if (status != IXGBE_SUCCESS)
3900                 return status;
3901
3902         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3903          * disabled, then force link down by entering low power mode.
3904          */
3905         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3906             !(hw->wol_enabled || ixgbe_mng_present(hw)))
3907                 return ixgbe_set_copper_phy_power(hw, FALSE);
3908
3909         /* Determine LCD */
3910         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3911
3912         if (status != IXGBE_SUCCESS)
3913                 return status;
3914
3915         /* If no valid LCD link speed, then force link down and exit. */
3916         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3917                 return ixgbe_set_copper_phy_power(hw, FALSE);
3918
3919         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3920                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3921                                       &speed);
3922
3923         if (status != IXGBE_SUCCESS)
3924                 return status;
3925
3926         /* If no link now, speed is invalid so take link down */
3927         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3928         if (status != IXGBE_SUCCESS)
3929                 return ixgbe_set_copper_phy_power(hw, false);
3930
3931         /* clear everything but the speed bits */
3932         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3933
3934         /* If current speed is already LCD, then exit. */
3935         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3936              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3937             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3938              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3939                 return status;
3940
3941         /* Clear AN completed indication */
3942         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3943                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3944                                       &autoneg_reg);
3945
3946         if (status != IXGBE_SUCCESS)
3947                 return status;
3948
3949         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3950                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3951                              &an_10g_cntl_reg);
3952
3953         if (status != IXGBE_SUCCESS)
3954                 return status;
3955
3956         status = hw->phy.ops.read_reg(hw,
3957                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3958                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3959                              &autoneg_reg);
3960
3961         if (status != IXGBE_SUCCESS)
3962                 return status;
3963
3964         save_autoneg = hw->phy.autoneg_advertised;
3965
3966         /* Setup link at least common link speed */
3967         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3968
3969         /* restore autoneg from before setting lplu speed */
3970         hw->phy.autoneg_advertised = save_autoneg;
3971
3972         return status;
3973 }
3974
3975 /**
3976  * ixgbe_get_lcd_x550em - Determine lowest common denominator
3977  *  @hw: pointer to hardware structure
3978  *  @lcd_speed: pointer to lowest common link speed
3979  *
3980  * Determine lowest common link speed with link partner.
3981  **/
3982 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3983 {
3984         u16 an_lp_status;
3985         s32 status;
3986         u16 word = hw->eeprom.ctrl_word_3;
3987
3988         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3989
3990         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3991                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3992                                       &an_lp_status);
3993
3994         if (status != IXGBE_SUCCESS)
3995                 return status;
3996
3997         /* If link partner advertised 1G, return 1G */
3998         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3999                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
4000                 return status;
4001         }
4002
4003         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
4004         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
4005             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
4006                 return status;
4007
4008         /* Link partner not capable of lower speeds, return 10G */
4009         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
4010         return status;
4011 }
4012
4013 /**
4014  *  ixgbe_setup_fc_X550em - Set up flow control
4015  *  @hw: pointer to hardware structure
4016  *
4017  *  Called at init time to set up flow control.
4018  **/
4019 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
4020 {
4021         s32 ret_val = IXGBE_SUCCESS;
4022         u32 pause, asm_dir, reg_val;
4023
4024         DEBUGFUNC("ixgbe_setup_fc_X550em");
4025
4026         /* Validate the requested mode */
4027         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4028                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4029                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4030                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4031                 goto out;
4032         }
4033
4034         /* 10gig parts do not have a word in the EEPROM to determine the
4035          * default flow control setting, so we explicitly set it to full.
4036          */
4037         if (hw->fc.requested_mode == ixgbe_fc_default)
4038                 hw->fc.requested_mode = ixgbe_fc_full;
4039
4040         /* Determine PAUSE and ASM_DIR bits. */
4041         switch (hw->fc.requested_mode) {
4042         case ixgbe_fc_none:
4043                 pause = 0;
4044                 asm_dir = 0;
4045                 break;
4046         case ixgbe_fc_tx_pause:
4047                 pause = 0;
4048                 asm_dir = 1;
4049                 break;
4050         case ixgbe_fc_rx_pause:
4051                 /* Rx Flow control is enabled and Tx Flow control is
4052                  * disabled by software override. Since there really
4053                  * isn't a way to advertise that we are capable of RX
4054                  * Pause ONLY, we will advertise that we support both
4055                  * symmetric and asymmetric Rx PAUSE, as such we fall
4056                  * through to the fc_full statement.  Later, we will
4057                  * disable the adapter's ability to send PAUSE frames.
4058                  */
4059         case ixgbe_fc_full:
4060                 pause = 1;
4061                 asm_dir = 1;
4062                 break;
4063         default:
4064                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4065                         "Flow control param set incorrectly\n");
4066                 ret_val = IXGBE_ERR_CONFIG;
4067                 goto out;
4068         }
4069
4070         switch (hw->device_id) {
4071         case IXGBE_DEV_ID_X550EM_X_KR:
4072         case IXGBE_DEV_ID_X550EM_A_KR:
4073         case IXGBE_DEV_ID_X550EM_A_KR_L:
4074                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
4075                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4076                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
4077                 if (ret_val != IXGBE_SUCCESS)
4078                         goto out;
4079                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4080                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4081                 if (pause)
4082                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4083                 if (asm_dir)
4084                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4085                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
4086                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4087                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
4088
4089                 /* This device does not fully support AN. */
4090                 hw->fc.disable_fc_autoneg = true;
4091                 break;
4092         default:
4093                 break;
4094         }
4095
4096 out:
4097         return ret_val;
4098 }
4099
4100 /**
4101  *  ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
4102  *  @hw: pointer to hardware structure
4103  *
4104  *  Enable flow control according to IEEE clause 37.
4105  **/
4106 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
4107 {
4108         u32 link_s1, lp_an_page_low, an_cntl_1;
4109         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4110         ixgbe_link_speed speed;
4111         bool link_up;
4112
4113         /* AN should have completed when the cable was plugged in.
4114          * Look for reasons to bail out.  Bail out if:
4115          * - FC autoneg is disabled, or if
4116          * - link is not up.
4117          */
4118         if (hw->fc.disable_fc_autoneg) {
4119                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4120                              "Flow control autoneg is disabled");
4121                 goto out;
4122         }
4123
4124         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4125         if (!link_up) {
4126                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4127                 goto out;
4128         }
4129
4130         /* Check at auto-negotiation has completed */
4131         status = hw->mac.ops.read_iosf_sb_reg(hw,
4132                                         IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4133                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4134
4135         if (status != IXGBE_SUCCESS ||
4136             (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4137                 DEBUGOUT("Auto-Negotiation did not complete\n");
4138                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4139                 goto out;
4140         }
4141
4142         /* Read the 10g AN autoc and LP ability registers and resolve
4143          * local flow control settings accordingly
4144          */
4145         status = hw->mac.ops.read_iosf_sb_reg(hw,
4146                                 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4147                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
4148
4149         if (status != IXGBE_SUCCESS) {
4150                 DEBUGOUT("Auto-Negotiation did not complete\n");
4151                 goto out;
4152         }
4153
4154         status = hw->mac.ops.read_iosf_sb_reg(hw,
4155                                 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
4156                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
4157
4158         if (status != IXGBE_SUCCESS) {
4159                 DEBUGOUT("Auto-Negotiation did not complete\n");
4160                 goto out;
4161         }
4162
4163         status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
4164                                     IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
4165                                     IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
4166                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
4167                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
4168
4169 out:
4170         if (status == IXGBE_SUCCESS) {
4171                 hw->fc.fc_was_autonegged = true;
4172         } else {
4173                 hw->fc.fc_was_autonegged = false;
4174                 hw->fc.current_mode = hw->fc.requested_mode;
4175         }
4176 }
4177
4178 /**
4179  *  ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
4180  *  @hw: pointer to hardware structure
4181  *
4182  **/
4183 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
4184 {
4185         hw->fc.fc_was_autonegged = false;
4186         hw->fc.current_mode = hw->fc.requested_mode;
4187 }
4188
4189 /**
4190  *  ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
4191  *  @hw: pointer to hardware structure
4192  *
4193  *  Enable flow control according to IEEE clause 37.
4194  **/
4195 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
4196 {
4197         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4198         u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
4199         ixgbe_link_speed speed;
4200         bool link_up;
4201
4202         /* AN should have completed when the cable was plugged in.
4203          * Look for reasons to bail out.  Bail out if:
4204          * - FC autoneg is disabled, or if
4205          * - link is not up.
4206          */
4207         if (hw->fc.disable_fc_autoneg) {
4208                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4209                              "Flow control autoneg is disabled");
4210                 goto out;
4211         }
4212
4213         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4214         if (!link_up) {
4215                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4216                 goto out;
4217         }
4218
4219         /* Check if auto-negotiation has completed */
4220         status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info);
4221         if (status != IXGBE_SUCCESS ||
4222             !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) {
4223                 DEBUGOUT("Auto-Negotiation did not complete\n");
4224                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4225                 goto out;
4226         }
4227
4228         /* Negotiate the flow control */
4229         status = ixgbe_negotiate_fc(hw, info[0], info[0],
4230                                     FW_PHY_ACT_GET_LINK_INFO_FC_RX,
4231                                     FW_PHY_ACT_GET_LINK_INFO_FC_TX,
4232                                     FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX,
4233                                     FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX);
4234
4235 out:
4236         if (status == IXGBE_SUCCESS) {
4237                 hw->fc.fc_was_autonegged = true;
4238         } else {
4239                 hw->fc.fc_was_autonegged = false;
4240                 hw->fc.current_mode = hw->fc.requested_mode;
4241         }
4242 }
4243
4244 /**
4245  *  ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4246  *  @hw: pointer to hardware structure
4247  *
4248  *  Called at init time to set up flow control.
4249  **/
4250 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4251 {
4252         s32 status = IXGBE_SUCCESS;
4253         u32 an_cntl = 0;
4254
4255         DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4256
4257         /* Validate the requested mode */
4258         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4259                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4260                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4261                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4262         }
4263
4264         if (hw->fc.requested_mode == ixgbe_fc_default)
4265                 hw->fc.requested_mode = ixgbe_fc_full;
4266
4267         /* Set up the 1G and 10G flow control advertisement registers so the
4268          * HW will be able to do FC autoneg once the cable is plugged in.  If
4269          * we link at 10G, the 1G advertisement is harmless and vice versa.
4270          */
4271         status = hw->mac.ops.read_iosf_sb_reg(hw,
4272                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4273                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4274
4275         if (status != IXGBE_SUCCESS) {
4276                 DEBUGOUT("Auto-Negotiation did not complete\n");
4277                 return status;
4278         }
4279
4280         /* The possible values of fc.requested_mode are:
4281          * 0: Flow control is completely disabled
4282          * 1: Rx flow control is enabled (we can receive pause frames,
4283          *    but not send pause frames).
4284          * 2: Tx flow control is enabled (we can send pause frames but
4285          *    we do not support receiving pause frames).
4286          * 3: Both Rx and Tx flow control (symmetric) are enabled.
4287          * other: Invalid.
4288          */
4289         switch (hw->fc.requested_mode) {
4290         case ixgbe_fc_none:
4291                 /* Flow control completely disabled by software override. */
4292                 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4293                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4294                 break;
4295         case ixgbe_fc_tx_pause:
4296                 /* Tx Flow control is enabled, and Rx Flow control is
4297                  * disabled by software override.
4298                  */
4299                 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4300                 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4301                 break;
4302         case ixgbe_fc_rx_pause:
4303                 /* Rx Flow control is enabled and Tx Flow control is
4304                  * disabled by software override. Since there really
4305                  * isn't a way to advertise that we are capable of RX
4306                  * Pause ONLY, we will advertise that we support both
4307                  * symmetric and asymmetric Rx PAUSE, as such we fall
4308                  * through to the fc_full statement.  Later, we will
4309                  * disable the adapter's ability to send PAUSE frames.
4310                  */
4311         case ixgbe_fc_full:
4312                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4313                 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4314                            IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4315                 break;
4316         default:
4317                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4318                               "Flow control param set incorrectly\n");
4319                 return IXGBE_ERR_CONFIG;
4320         }
4321
4322         status = hw->mac.ops.write_iosf_sb_reg(hw,
4323                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4324                                         IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4325
4326         /* Restart auto-negotiation. */
4327         status = ixgbe_restart_an_internal_phy_x550em(hw);
4328
4329         return status;
4330 }
4331
4332 /**
4333  * ixgbe_set_mux - Set mux for port 1 access with CS4227
4334  * @hw: pointer to hardware structure
4335  * @state: set mux if 1, clear if 0
4336  */
4337 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4338 {
4339         u32 esdp;
4340
4341         if (!hw->bus.lan_id)
4342                 return;
4343         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4344         if (state)
4345                 esdp |= IXGBE_ESDP_SDP1;
4346         else
4347                 esdp &= ~IXGBE_ESDP_SDP1;
4348         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4349         IXGBE_WRITE_FLUSH(hw);
4350 }
4351
4352 /**
4353  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4354  *  @hw: pointer to hardware structure
4355  *  @mask: Mask to specify which semaphore to acquire
4356  *
4357  *  Acquires the SWFW semaphore and sets the I2C MUX
4358  **/
4359 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4360 {
4361         s32 status;
4362
4363         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4364
4365         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4366         if (status)
4367                 return status;
4368
4369         if (mask & IXGBE_GSSR_I2C_MASK)
4370                 ixgbe_set_mux(hw, 1);
4371
4372         return IXGBE_SUCCESS;
4373 }
4374
4375 /**
4376  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4377  *  @hw: pointer to hardware structure
4378  *  @mask: Mask to specify which semaphore to release
4379  *
4380  *  Releases the SWFW semaphore and sets the I2C MUX
4381  **/
4382 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4383 {
4384         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4385
4386         if (mask & IXGBE_GSSR_I2C_MASK)
4387                 ixgbe_set_mux(hw, 0);
4388
4389         ixgbe_release_swfw_sync_X540(hw, mask);
4390 }
4391
4392 /**
4393  *  ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4394  *  @hw: pointer to hardware structure
4395  *  @mask: Mask to specify which semaphore to acquire
4396  *
4397  *  Acquires the SWFW semaphore and get the shared phy token as needed
4398  */
4399 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4400 {
4401         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4402         int retries = FW_PHY_TOKEN_RETRIES;
4403         s32 status = IXGBE_SUCCESS;
4404
4405         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4406
4407         while (--retries) {
4408                 status = IXGBE_SUCCESS;
4409                 if (hmask)
4410                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4411                 if (status)
4412                         return status;
4413                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4414                         return IXGBE_SUCCESS;
4415
4416                 status = ixgbe_get_phy_token(hw);
4417                 if (status == IXGBE_SUCCESS)
4418                         return IXGBE_SUCCESS;
4419
4420                 if (hmask)
4421                         ixgbe_release_swfw_sync_X540(hw, hmask);
4422                 if (status != IXGBE_ERR_TOKEN_RETRY)
4423                         return status;
4424         }
4425
4426         return status;
4427 }
4428
4429 /**
4430  *  ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4431  *  @hw: pointer to hardware structure
4432  *  @mask: Mask to specify which semaphore to release
4433  *
4434  *  Releases the SWFW semaphore and puts the shared phy token as needed
4435  */
4436 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4437 {
4438         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4439
4440         DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4441
4442         if (mask & IXGBE_GSSR_TOKEN_SM)
4443                 ixgbe_put_phy_token(hw);
4444
4445         if (hmask)
4446                 ixgbe_release_swfw_sync_X540(hw, hmask);
4447 }
4448
4449 /**
4450  *  ixgbe_read_phy_reg_x550a  - Reads specified PHY register
4451  *  @hw: pointer to hardware structure
4452  *  @reg_addr: 32 bit address of PHY register to read
4453  *  @phy_data: Pointer to read data from PHY register
4454  *
4455  *  Reads a value from a specified PHY register using the SWFW lock and PHY
4456  *  Token. The PHY Token is needed since the MDIO is shared between to MAC
4457  *  instances.
4458  **/
4459 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4460                                u32 device_type, u16 *phy_data)
4461 {
4462         s32 status;
4463         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4464
4465         DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4466
4467         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4468                 return IXGBE_ERR_SWFW_SYNC;
4469
4470         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4471
4472         hw->mac.ops.release_swfw_sync(hw, mask);
4473
4474         return status;
4475 }
4476
4477 /**
4478  *  ixgbe_write_phy_reg_x550a - Writes specified PHY register
4479  *  @hw: pointer to hardware structure
4480  *  @reg_addr: 32 bit PHY register to write
4481  *  @device_type: 5 bit device type
4482  *  @phy_data: Data to write to the PHY register
4483  *
4484  *  Writes a value to specified PHY register using the SWFW lock and PHY Token.
4485  *  The PHY Token is needed since the MDIO is shared between to MAC instances.
4486  **/
4487 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4488                                 u32 device_type, u16 phy_data)
4489 {
4490         s32 status;
4491         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4492
4493         DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4494
4495         if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4496                 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
4497                                                  phy_data);
4498                 hw->mac.ops.release_swfw_sync(hw, mask);
4499         } else {
4500                 status = IXGBE_ERR_SWFW_SYNC;
4501         }
4502
4503         return status;
4504 }
4505
4506 /**
4507  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4508  * @hw: pointer to hardware structure
4509  *
4510  * Handle external Base T PHY interrupt. If high temperature
4511  * failure alarm then return error, else if link status change
4512  * then setup internal/external PHY link
4513  *
4514  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4515  * failure alarm, else return PHY access status.
4516  */
4517 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4518 {
4519         bool lsc;
4520         u32 status;
4521
4522         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4523
4524         if (status != IXGBE_SUCCESS)
4525                 return status;
4526
4527         if (lsc)
4528                 return ixgbe_setup_internal_phy(hw);
4529
4530         return IXGBE_SUCCESS;
4531 }
4532
4533 /**
4534  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4535  * @hw: pointer to hardware structure
4536  * @speed: new link speed
4537  * @autoneg_wait_to_complete: true when waiting for completion is needed
4538  *
4539  * Setup internal/external PHY link speed based on link speed, then set
4540  * external PHY auto advertised link speed.
4541  *
4542  * Returns error status for any failure
4543  **/
4544 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4545                                   ixgbe_link_speed speed,
4546                                   bool autoneg_wait_to_complete)
4547 {
4548         s32 status;
4549         ixgbe_link_speed force_speed;
4550
4551         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4552
4553         /* Setup internal/external PHY link speed to iXFI (10G), unless
4554          * only 1G is auto advertised then setup KX link.
4555          */
4556         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4557                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4558         else
4559                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4560
4561         /* If X552 and internal link mode is XFI, then setup XFI internal link.
4562          */
4563         if (hw->mac.type == ixgbe_mac_X550EM_x &&
4564             !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4565                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4566
4567                 if (status != IXGBE_SUCCESS)
4568                         return status;
4569         }
4570
4571         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4572 }
4573
4574 /**
4575  * ixgbe_check_link_t_X550em - Determine link and speed status
4576  * @hw: pointer to hardware structure
4577  * @speed: pointer to link speed
4578  * @link_up: true when link is up
4579  * @link_up_wait_to_complete: bool used to wait for link up or not
4580  *
4581  * Check that both the MAC and X557 external PHY have link.
4582  **/
4583 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4584                               bool *link_up, bool link_up_wait_to_complete)
4585 {
4586         u32 status;
4587         u16 i, autoneg_status = 0;
4588
4589         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4590                 return IXGBE_ERR_CONFIG;
4591
4592         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4593                                               link_up_wait_to_complete);
4594
4595         /* If check link fails or MAC link is not up, then return */
4596         if (status != IXGBE_SUCCESS || !(*link_up))
4597                 return status;
4598
4599         /* MAC link is up, so check external PHY link.
4600          * X557 PHY. Link status is latching low, and can only be used to detect
4601          * link drop, and not the current status of the link without performing
4602          * back-to-back reads.
4603          */
4604         for (i = 0; i < 2; i++) {
4605                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4606                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4607                                               &autoneg_status);
4608
4609                 if (status != IXGBE_SUCCESS)
4610                         return status;
4611         }
4612
4613         /* If external PHY link is not up, then indicate link not up */
4614         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4615                 *link_up = false;
4616
4617         return IXGBE_SUCCESS;
4618 }
4619
4620 /**
4621  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4622  *  @hw: pointer to hardware structure
4623  **/
4624 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4625 {
4626         s32 status;
4627
4628         status = ixgbe_reset_phy_generic(hw);
4629
4630         if (status != IXGBE_SUCCESS)
4631                 return status;
4632
4633         /* Configure Link Status Alarm and Temperature Threshold interrupts */
4634         return ixgbe_enable_lasi_ext_t_x550em(hw);
4635 }
4636
4637 /**
4638  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4639  *  @hw: pointer to hardware structure
4640  *  @led_idx: led number to turn on
4641  **/
4642 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4643 {
4644         u16 phy_data;
4645
4646         DEBUGFUNC("ixgbe_led_on_t_X550em");
4647
4648         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4649                 return IXGBE_ERR_PARAM;
4650
4651         /* To turn on the LED, set mode to ON. */
4652         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4653                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4654         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4655         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4656                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4657
4658         return IXGBE_SUCCESS;
4659 }
4660
4661 /**
4662  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4663  *  @hw: pointer to hardware structure
4664  *  @led_idx: led number to turn off
4665  **/
4666 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4667 {
4668         u16 phy_data;
4669
4670         DEBUGFUNC("ixgbe_led_off_t_X550em");
4671
4672         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4673                 return IXGBE_ERR_PARAM;
4674
4675         /* To turn on the LED, set mode to ON. */
4676         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4677                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4678         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4679         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4680                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4681
4682         return IXGBE_SUCCESS;
4683 }
4684
4685 /**
4686  *  ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware
4687  *  @hw: pointer to the HW structure
4688  *  @maj: driver version major number
4689  *  @min: driver version minor number
4690  *  @build: driver version build number
4691  *  @sub: driver version sub build number
4692  *  @len: length of driver_ver string
4693  *  @driver_ver: driver string
4694  *
4695  *  Sends driver version number to firmware through the manageability
4696  *  block.  On success return IXGBE_SUCCESS
4697  *  else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4698  *  semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4699  **/
4700 s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,
4701                               u8 build, u8 sub, u16 len, const char *driver_ver)
4702 {
4703         struct ixgbe_hic_drv_info2 fw_cmd;
4704         s32 ret_val = IXGBE_SUCCESS;
4705         int i;
4706
4707         DEBUGFUNC("ixgbe_set_fw_drv_ver_x550");
4708
4709         if ((len == 0) || (driver_ver == NULL) ||
4710            (len > sizeof(fw_cmd.driver_string)))
4711                 return IXGBE_ERR_INVALID_ARGUMENT;
4712
4713         fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4714         fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len;
4715         fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4716         fw_cmd.port_num = (u8)hw->bus.func;
4717         fw_cmd.ver_maj = maj;
4718         fw_cmd.ver_min = min;
4719         fw_cmd.ver_build = build;
4720         fw_cmd.ver_sub = sub;
4721         fw_cmd.hdr.checksum = 0;
4722         memcpy(fw_cmd.driver_string, driver_ver, len);
4723         fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4724                                 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4725
4726         for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4727                 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4728                                                        sizeof(fw_cmd),
4729                                                        IXGBE_HI_COMMAND_TIMEOUT,
4730                                                        true);
4731                 if (ret_val != IXGBE_SUCCESS)
4732                         continue;
4733
4734                 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4735                     FW_CEM_RESP_STATUS_SUCCESS)
4736                         ret_val = IXGBE_SUCCESS;
4737                 else
4738                         ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4739
4740                 break;
4741         }
4742
4743         return ret_val;
4744 }