1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
46 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
47 * @hw: pointer to hardware structure
49 * Initialize the function pointers and assign the MAC type for X550.
50 * Does not touch the hardware.
52 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
54 struct ixgbe_mac_info *mac = &hw->mac;
55 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
58 DEBUGFUNC("ixgbe_init_ops_X550");
60 ret_val = ixgbe_init_ops_X540(hw);
61 mac->ops.dmac_config = ixgbe_dmac_config_X550;
62 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
63 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
64 mac->ops.setup_eee = ixgbe_setup_eee_X550;
65 mac->ops.set_source_address_pruning =
66 ixgbe_set_source_address_pruning_X550;
67 mac->ops.set_ethertype_anti_spoofing =
68 ixgbe_set_ethertype_anti_spoofing_X550;
70 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
71 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
72 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
73 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
74 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
75 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
76 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
77 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
78 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
80 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
81 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
82 mac->ops.mdd_event = ixgbe_mdd_event_X550;
83 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
84 mac->ops.disable_rx = ixgbe_disable_rx_x550;
85 switch (hw->device_id) {
86 case IXGBE_DEV_ID_X550EM_X_10G_T:
87 case IXGBE_DEV_ID_X550EM_A_10G_T:
88 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
89 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
98 * ixgbe_read_cs4227 - Read CS4227 register
99 * @hw: pointer to hardware structure
100 * @reg: register number to write
101 * @value: pointer to receive value read
103 * Returns status code
105 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
107 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
111 * ixgbe_write_cs4227 - Write CS4227 register
112 * @hw: pointer to hardware structure
113 * @reg: register number to write
114 * @value: value to write to register
116 * Returns status code
118 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
120 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
124 * ixgbe_read_pe - Read register from port expander
125 * @hw: pointer to hardware structure
126 * @reg: register number to read
127 * @value: pointer to receive read value
129 * Returns status code
131 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
135 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
136 if (status != IXGBE_SUCCESS)
137 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
138 "port expander access failed with %d\n", status);
143 * ixgbe_write_pe - Write register to port expander
144 * @hw: pointer to hardware structure
145 * @reg: register number to write
146 * @value: value to write
148 * Returns status code
150 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
154 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
155 if (status != IXGBE_SUCCESS)
156 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
157 "port expander access failed with %d\n", status);
162 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
163 * @hw: pointer to hardware structure
165 * This function assumes that the caller has acquired the proper semaphore.
168 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
175 /* Trigger hard reset. */
176 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
177 if (status != IXGBE_SUCCESS)
179 reg |= IXGBE_PE_BIT1;
180 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
181 if (status != IXGBE_SUCCESS)
184 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
185 if (status != IXGBE_SUCCESS)
187 reg &= ~IXGBE_PE_BIT1;
188 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
189 if (status != IXGBE_SUCCESS)
192 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
193 if (status != IXGBE_SUCCESS)
195 reg &= ~IXGBE_PE_BIT1;
196 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
197 if (status != IXGBE_SUCCESS)
200 usec_delay(IXGBE_CS4227_RESET_HOLD);
202 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
203 if (status != IXGBE_SUCCESS)
205 reg |= IXGBE_PE_BIT1;
206 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
207 if (status != IXGBE_SUCCESS)
210 /* Wait for the reset to complete. */
211 msec_delay(IXGBE_CS4227_RESET_DELAY);
212 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
213 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
215 if (status == IXGBE_SUCCESS &&
216 value == IXGBE_CS4227_EEPROM_LOAD_OK)
218 msec_delay(IXGBE_CS4227_CHECK_DELAY);
220 if (retry == IXGBE_CS4227_RETRIES) {
221 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
222 "CS4227 reset did not complete.");
223 return IXGBE_ERR_PHY;
226 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
227 if (status != IXGBE_SUCCESS ||
228 !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
229 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
230 "CS4227 EEPROM did not load successfully.");
231 return IXGBE_ERR_PHY;
234 return IXGBE_SUCCESS;
238 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
239 * @hw: pointer to hardware structure
241 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
243 s32 status = IXGBE_SUCCESS;
244 u32 swfw_mask = hw->phy.phy_semaphore_mask;
248 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
249 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
250 if (status != IXGBE_SUCCESS) {
251 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
252 "semaphore failed with %d", status);
253 msec_delay(IXGBE_CS4227_CHECK_DELAY);
257 /* Get status of reset flow. */
258 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
260 if (status == IXGBE_SUCCESS &&
261 value == IXGBE_CS4227_RESET_COMPLETE)
264 if (status != IXGBE_SUCCESS ||
265 value != IXGBE_CS4227_RESET_PENDING)
268 /* Reset is pending. Wait and check again. */
269 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
270 msec_delay(IXGBE_CS4227_CHECK_DELAY);
273 /* If still pending, assume other instance failed. */
274 if (retry == IXGBE_CS4227_RETRIES) {
275 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
276 if (status != IXGBE_SUCCESS) {
277 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
278 "semaphore failed with %d", status);
283 /* Reset the CS4227. */
284 status = ixgbe_reset_cs4227(hw);
285 if (status != IXGBE_SUCCESS) {
286 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
287 "CS4227 reset failed: %d", status);
291 /* Reset takes so long, temporarily release semaphore in case the
292 * other driver instance is waiting for the reset indication.
294 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
295 IXGBE_CS4227_RESET_PENDING);
296 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
298 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
299 if (status != IXGBE_SUCCESS) {
300 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
301 "semaphore failed with %d", status);
305 /* Record completion for next time. */
306 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
307 IXGBE_CS4227_RESET_COMPLETE);
310 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
311 msec_delay(hw->eeprom.semaphore_delay);
315 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
316 * @hw: pointer to hardware structure
318 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
320 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
322 if (hw->bus.lan_id) {
323 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
324 esdp |= IXGBE_ESDP_SDP1_DIR;
326 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
327 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
328 IXGBE_WRITE_FLUSH(hw);
332 * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
333 * @hw: pointer to hardware structure
334 * @reg_addr: 32 bit address of PHY register to read
335 * @dev_type: always unused
336 * @phy_data: Pointer to read data from PHY register
338 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
339 u32 dev_type, u16 *phy_data)
341 u32 i, data, command;
342 UNREFERENCED_1PARAMETER(dev_type);
344 /* Setup and write the read command */
345 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
346 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
347 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
348 IXGBE_MSCA_MDI_COMMAND;
350 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
352 /* Check every 10 usec to see if the access completed.
353 * The MDI Command bit will clear when the operation is
356 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
359 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
360 if (!(command & IXGBE_MSCA_MDI_COMMAND))
364 if (command & IXGBE_MSCA_MDI_COMMAND) {
365 ERROR_REPORT1(IXGBE_ERROR_POLLING,
366 "PHY read command did not complete.\n");
367 return IXGBE_ERR_PHY;
370 /* Read operation is complete. Get the data from MSRWD */
371 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
372 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
373 *phy_data = (u16)data;
375 return IXGBE_SUCCESS;
379 * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
380 * @hw: pointer to hardware structure
381 * @reg_addr: 32 bit PHY register to write
382 * @dev_type: always unused
383 * @phy_data: Data to write to the PHY register
385 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
386 u32 dev_type, u16 phy_data)
389 UNREFERENCED_1PARAMETER(dev_type);
391 /* Put the data in the MDI single read and write data register*/
392 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
394 /* Setup and write the write command */
395 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
396 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
397 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
398 IXGBE_MSCA_MDI_COMMAND;
400 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
402 /* Check every 10 usec to see if the access completed.
403 * The MDI Command bit will clear when the operation is
406 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
409 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
410 if (!(command & IXGBE_MSCA_MDI_COMMAND))
414 if (command & IXGBE_MSCA_MDI_COMMAND) {
415 ERROR_REPORT1(IXGBE_ERROR_POLLING,
416 "PHY write cmd didn't complete\n");
417 return IXGBE_ERR_PHY;
420 return IXGBE_SUCCESS;
424 * ixgbe_identify_phy_x550em - Get PHY type based on device id
425 * @hw: pointer to hardware structure
429 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
431 switch (hw->device_id) {
432 case IXGBE_DEV_ID_X550EM_A_SFP:
433 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
434 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
436 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
438 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
439 return ixgbe_identify_module_generic(hw);
440 case IXGBE_DEV_ID_X550EM_X_SFP:
441 /* set up for CS4227 usage */
442 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
443 ixgbe_setup_mux_ctl(hw);
444 ixgbe_check_cs4227(hw);
447 case IXGBE_DEV_ID_X550EM_A_SFP_N:
448 return ixgbe_identify_module_generic(hw);
450 case IXGBE_DEV_ID_X550EM_X_KX4:
451 hw->phy.type = ixgbe_phy_x550em_kx4;
453 case IXGBE_DEV_ID_X550EM_X_KR:
454 case IXGBE_DEV_ID_X550EM_A_KR:
455 case IXGBE_DEV_ID_X550EM_A_KR_L:
456 hw->phy.type = ixgbe_phy_x550em_kr;
458 case IXGBE_DEV_ID_X550EM_A_10G_T:
459 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
460 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
461 /* Fallthrough to ixgbe_identify_phy_generic */
462 case IXGBE_DEV_ID_X550EM_A_1G_T:
463 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
464 case IXGBE_DEV_ID_X550EM_X_1G_T:
465 case IXGBE_DEV_ID_X550EM_X_10G_T:
466 return ixgbe_identify_phy_generic(hw);
470 return IXGBE_SUCCESS;
473 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
474 u32 device_type, u16 *phy_data)
476 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
477 return IXGBE_NOT_IMPLEMENTED;
480 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
481 u32 device_type, u16 phy_data)
483 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
484 return IXGBE_NOT_IMPLEMENTED;
488 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
489 * @hw: pointer to the hardware structure
490 * @addr: I2C bus address to read from
491 * @reg: I2C device register to read from
492 * @val: pointer to location to receive read value
494 * Returns an error code on error.
496 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
499 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
503 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
504 * @hw: pointer to the hardware structure
505 * @addr: I2C bus address to read from
506 * @reg: I2C device register to read from
507 * @val: pointer to location to receive read value
509 * Returns an error code on error.
512 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
515 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
519 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
520 * @hw: pointer to the hardware structure
521 * @addr: I2C bus address to write to
522 * @reg: I2C device register to write to
523 * @val: value to write
525 * Returns an error code on error.
527 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
528 u8 addr, u16 reg, u16 val)
530 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
534 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
535 * @hw: pointer to the hardware structure
536 * @addr: I2C bus address to write to
537 * @reg: I2C device register to write to
538 * @val: value to write
540 * Returns an error code on error.
543 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
544 u8 addr, u16 reg, u16 val)
546 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
550 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
551 * @hw: pointer to hardware structure
553 * Initialize the function pointers and for MAC type X550EM.
554 * Does not touch the hardware.
556 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
558 struct ixgbe_mac_info *mac = &hw->mac;
559 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
560 struct ixgbe_phy_info *phy = &hw->phy;
563 DEBUGFUNC("ixgbe_init_ops_X550EM");
565 /* Similar to X550 so start there. */
566 ret_val = ixgbe_init_ops_X550(hw);
568 /* Since this function eventually calls
569 * ixgbe_init_ops_540 by design, we are setting
570 * the pointers to NULL explicitly here to overwrite
571 * the values being set in the x540 function.
573 /* Thermal sensor not supported in x550EM */
574 mac->ops.get_thermal_sensor_data = NULL;
575 mac->ops.init_thermal_sensor_thresh = NULL;
576 mac->thermal_sensor_enabled = false;
578 /* FCOE not supported in x550EM */
579 mac->ops.get_san_mac_addr = NULL;
580 mac->ops.set_san_mac_addr = NULL;
581 mac->ops.get_wwn_prefix = NULL;
582 mac->ops.get_fcoe_boot_status = NULL;
584 /* IPsec not supported in x550EM */
585 mac->ops.disable_sec_rx_path = NULL;
586 mac->ops.enable_sec_rx_path = NULL;
588 /* AUTOC register is not present in x550EM. */
589 mac->ops.prot_autoc_read = NULL;
590 mac->ops.prot_autoc_write = NULL;
592 /* X550EM bus type is internal*/
593 hw->bus.type = ixgbe_bus_type_internal;
594 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
597 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
598 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
599 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
600 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
601 mac->ops.get_supported_physical_layer =
602 ixgbe_get_supported_physical_layer_X550em;
604 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
605 mac->ops.setup_fc = ixgbe_setup_fc_generic;
607 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
609 switch (hw->device_id) {
610 case IXGBE_DEV_ID_X550EM_X_KR:
611 case IXGBE_DEV_ID_X550EM_A_KR:
612 case IXGBE_DEV_ID_X550EM_A_KR_L:
615 mac->ops.setup_eee = NULL;
619 phy->ops.init = ixgbe_init_phy_ops_X550em;
620 phy->ops.identify = ixgbe_identify_phy_x550em;
621 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
622 phy->ops.set_phy_power = NULL;
626 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
627 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
628 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
629 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
630 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
631 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
632 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
633 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
639 * ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
640 * @hw: pointer to hardware structure
642 * Initialize the function pointers and for MAC type X550EM_a.
643 * Does not touch the hardware.
645 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
647 struct ixgbe_mac_info *mac = &hw->mac;
650 DEBUGFUNC("ixgbe_init_ops_X550EM_a");
652 /* Start with generic X550EM init */
653 ret_val = ixgbe_init_ops_X550EM(hw);
655 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
656 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
657 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
658 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
660 switch (mac->ops.get_media_type(hw)) {
661 case ixgbe_media_type_fiber:
662 mac->ops.setup_fc = ixgbe_setup_fc_fiber_x550em_a;
663 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
665 case ixgbe_media_type_backplane:
666 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
667 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
677 * ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
678 * @hw: pointer to hardware structure
680 * Initialize the function pointers and for MAC type X550EM_x.
681 * Does not touch the hardware.
683 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
685 struct ixgbe_mac_info *mac = &hw->mac;
686 struct ixgbe_link_info *link = &hw->link;
689 DEBUGFUNC("ixgbe_init_ops_X550EM_x");
691 /* Start with generic X550EM init */
692 ret_val = ixgbe_init_ops_X550EM(hw);
694 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
695 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
696 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
697 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
698 link->ops.read_link = ixgbe_read_i2c_combined_generic;
699 link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
700 link->ops.write_link = ixgbe_write_i2c_combined_generic;
701 link->ops.write_link_unlocked =
702 ixgbe_write_i2c_combined_generic_unlocked;
703 link->addr = IXGBE_CS4227;
709 * ixgbe_dmac_config_X550
710 * @hw: pointer to hardware structure
712 * Configure DMA coalescing. If enabling dmac, dmac is activated.
713 * When disabling dmac, dmac enable dmac bit is cleared.
715 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
717 u32 reg, high_pri_tc;
719 DEBUGFUNC("ixgbe_dmac_config_X550");
721 /* Disable DMA coalescing before configuring */
722 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
723 reg &= ~IXGBE_DMACR_DMAC_EN;
724 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
726 /* Disable DMA Coalescing if the watchdog timer is 0 */
727 if (!hw->mac.dmac_config.watchdog_timer)
730 ixgbe_dmac_config_tcs_X550(hw);
732 /* Configure DMA Coalescing Control Register */
733 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
735 /* Set the watchdog timer in units of 40.96 usec */
736 reg &= ~IXGBE_DMACR_DMACWT_MASK;
737 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
739 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
740 /* If fcoe is enabled, set high priority traffic class */
741 if (hw->mac.dmac_config.fcoe_en) {
742 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
743 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
744 IXGBE_DMACR_HIGH_PRI_TC_MASK);
746 reg |= IXGBE_DMACR_EN_MNG_IND;
748 /* Enable DMA coalescing after configuration */
749 reg |= IXGBE_DMACR_DMAC_EN;
750 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
753 return IXGBE_SUCCESS;
757 * ixgbe_dmac_config_tcs_X550
758 * @hw: pointer to hardware structure
760 * Configure DMA coalescing threshold per TC. The dmac enable bit must
761 * be cleared before configuring.
763 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
765 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
767 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
769 /* Configure DMA coalescing enabled */
770 switch (hw->mac.dmac_config.link_speed) {
771 case IXGBE_LINK_SPEED_100_FULL:
772 pb_headroom = IXGBE_DMACRXT_100M;
774 case IXGBE_LINK_SPEED_1GB_FULL:
775 pb_headroom = IXGBE_DMACRXT_1G;
778 pb_headroom = IXGBE_DMACRXT_10G;
782 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
783 IXGBE_MHADD_MFS_SHIFT) / 1024);
785 /* Set the per Rx packet buffer receive threshold */
786 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
787 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
788 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
790 if (tc < hw->mac.dmac_config.num_tcs) {
792 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
793 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
794 IXGBE_RXPBSIZE_SHIFT;
796 /* Calculate receive buffer threshold in kilobytes */
797 if (rx_pb_size > pb_headroom)
798 rx_pb_size = rx_pb_size - pb_headroom;
802 /* Minimum of MFS shall be set for DMCTH */
803 reg |= (rx_pb_size > maxframe_size_kb) ?
804 rx_pb_size : maxframe_size_kb;
806 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
808 return IXGBE_SUCCESS;
812 * ixgbe_dmac_update_tcs_X550
813 * @hw: pointer to hardware structure
815 * Disables dmac, updates per TC settings, and then enables dmac.
817 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
821 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
823 /* Disable DMA coalescing before configuring */
824 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
825 reg &= ~IXGBE_DMACR_DMAC_EN;
826 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
828 ixgbe_dmac_config_tcs_X550(hw);
830 /* Enable DMA coalescing after configuration */
831 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
832 reg |= IXGBE_DMACR_DMAC_EN;
833 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
835 return IXGBE_SUCCESS;
839 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
840 * @hw: pointer to hardware structure
842 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
843 * ixgbe_hw struct in order to set up EEPROM access.
845 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
847 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
851 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
853 if (eeprom->type == ixgbe_eeprom_uninitialized) {
854 eeprom->semaphore_delay = 10;
855 eeprom->type = ixgbe_flash;
857 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
858 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
859 IXGBE_EEC_SIZE_SHIFT);
860 eeprom->word_size = 1 << (eeprom_size +
861 IXGBE_EEPROM_WORD_SIZE_SHIFT);
863 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
864 eeprom->type, eeprom->word_size);
867 return IXGBE_SUCCESS;
871 * ixgbe_enable_eee_x550 - Enable EEE support
872 * @hw: pointer to hardware structure
874 STATIC s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
880 if (hw->mac.type == ixgbe_mac_X550) {
881 /* Advertise EEE capability */
882 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
883 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
886 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
887 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
888 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
890 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
891 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
893 return IXGBE_SUCCESS;
896 switch (hw->device_id) {
897 case IXGBE_DEV_ID_X550EM_X_KR:
898 case IXGBE_DEV_ID_X550EM_A_KR:
899 case IXGBE_DEV_ID_X550EM_A_KR_L:
900 status = hw->mac.ops.read_iosf_sb_reg(hw,
901 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
902 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
903 if (status != IXGBE_SUCCESS)
906 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
907 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
909 /* Don't advertise FEC capability when EEE enabled. */
910 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
912 status = hw->mac.ops.write_iosf_sb_reg(hw,
913 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
914 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
915 if (status != IXGBE_SUCCESS)
922 return IXGBE_SUCCESS;
926 * ixgbe_disable_eee_x550 - Disable EEE support
927 * @hw: pointer to hardware structure
929 STATIC s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
935 if (hw->mac.type == ixgbe_mac_X550) {
936 /* Disable advertised EEE capability */
937 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
938 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
941 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
942 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
943 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
945 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
946 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
948 return IXGBE_SUCCESS;
951 switch (hw->device_id) {
952 case IXGBE_DEV_ID_X550EM_X_KR:
953 case IXGBE_DEV_ID_X550EM_A_KR:
954 case IXGBE_DEV_ID_X550EM_A_KR_L:
955 status = hw->mac.ops.read_iosf_sb_reg(hw,
956 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
957 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
958 if (status != IXGBE_SUCCESS)
961 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
962 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
964 /* Advertise FEC capability when EEE is disabled. */
965 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
967 status = hw->mac.ops.write_iosf_sb_reg(hw,
968 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
969 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
970 if (status != IXGBE_SUCCESS)
977 return IXGBE_SUCCESS;
981 * ixgbe_setup_eee_X550 - Enable/disable EEE support
982 * @hw: pointer to the HW structure
983 * @enable_eee: boolean flag to enable EEE
985 * Enable/disable EEE based on enable_eee flag.
986 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
990 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
995 DEBUGFUNC("ixgbe_setup_eee_X550");
997 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
998 /* Enable or disable EEE per flag */
1000 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1002 /* Not supported on first revision of X550EM_x. */
1003 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
1004 !(IXGBE_FUSES0_REV_MASK &
1005 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
1006 return IXGBE_SUCCESS;
1007 status = ixgbe_enable_eee_x550(hw);
1011 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1013 status = ixgbe_disable_eee_x550(hw);
1017 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
1019 return IXGBE_SUCCESS;
1023 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1024 * @hw: pointer to hardware structure
1025 * @enable: enable or disable source address pruning
1026 * @pool: Rx pool to set source address pruning for
1028 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1033 /* max rx pool is 63 */
1037 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1038 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1041 pfflp |= (1ULL << pool);
1043 pfflp &= ~(1ULL << pool);
1045 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1046 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1050 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1051 * @hw: pointer to hardware structure
1052 * @enable: enable or disable switch for Ethertype anti-spoofing
1053 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1056 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1057 bool enable, int vf)
1059 int vf_target_reg = vf >> 3;
1060 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1063 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1065 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1067 pfvfspoof |= (1 << vf_target_shift);
1069 pfvfspoof &= ~(1 << vf_target_shift);
1071 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1075 * ixgbe_iosf_wait - Wait for IOSF command completion
1076 * @hw: pointer to hardware structure
1077 * @ctrl: pointer to location to receive final IOSF control value
1079 * Returns failing status on timeout
1081 * Note: ctrl can be NULL if the IOSF control register value is not needed
1083 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1087 /* Check every 10 usec to see if the address cycle completed.
1088 * The SB IOSF BUSY bit will clear when the operation is
1091 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1092 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1093 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1099 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1100 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1101 return IXGBE_ERR_PHY;
1104 return IXGBE_SUCCESS;
1108 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
1110 * @hw: pointer to hardware structure
1111 * @reg_addr: 32 bit PHY register to write
1112 * @device_type: 3 bit device type
1113 * @data: Data to write to the register
1115 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1116 u32 device_type, u32 data)
1118 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1122 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1123 if (ret != IXGBE_SUCCESS)
1126 ret = ixgbe_iosf_wait(hw, NULL);
1127 if (ret != IXGBE_SUCCESS)
1130 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1131 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1133 /* Write IOSF control register */
1134 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1136 /* Write IOSF data register */
1137 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1139 ret = ixgbe_iosf_wait(hw, &command);
1141 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1142 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1143 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1144 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1145 "Failed to write, error %x\n", error);
1146 ret = IXGBE_ERR_PHY;
1150 ixgbe_release_swfw_semaphore(hw, gssr);
1155 * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
1157 * @hw: pointer to hardware structure
1158 * @reg_addr: 32 bit PHY register to write
1159 * @device_type: 3 bit device type
1160 * @phy_data: Pointer to read data from the register
1162 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1163 u32 device_type, u32 *data)
1165 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1169 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1170 if (ret != IXGBE_SUCCESS)
1173 ret = ixgbe_iosf_wait(hw, NULL);
1174 if (ret != IXGBE_SUCCESS)
1177 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1178 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1180 /* Write IOSF control register */
1181 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1183 ret = ixgbe_iosf_wait(hw, &command);
1185 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1186 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1187 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1188 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1189 "Failed to read, error %x\n", error);
1190 ret = IXGBE_ERR_PHY;
1193 if (ret == IXGBE_SUCCESS)
1194 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1197 ixgbe_release_swfw_semaphore(hw, gssr);
1202 * ixgbe_get_phy_token - Get the token for shared phy access
1203 * @hw: Pointer to hardware structure
1206 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1208 struct ixgbe_hic_phy_token_req token_cmd;
1211 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1212 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1213 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1214 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1215 token_cmd.port_number = hw->bus.lan_id;
1216 token_cmd.command_type = FW_PHY_TOKEN_REQ;
1218 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1220 IXGBE_HI_COMMAND_TIMEOUT,
1224 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1225 return IXGBE_SUCCESS;
1226 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1227 return IXGBE_ERR_FW_RESP_INVALID;
1229 return IXGBE_ERR_TOKEN_RETRY;
1233 * ixgbe_put_phy_token - Put the token for shared phy access
1234 * @hw: Pointer to hardware structure
1237 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1239 struct ixgbe_hic_phy_token_req token_cmd;
1242 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1243 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1244 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1245 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1246 token_cmd.port_number = hw->bus.lan_id;
1247 token_cmd.command_type = FW_PHY_TOKEN_REL;
1249 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1251 IXGBE_HI_COMMAND_TIMEOUT,
1255 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1256 return IXGBE_SUCCESS;
1258 DEBUGOUT("Put PHY Token host interface command failed");
1259 return IXGBE_ERR_FW_RESP_INVALID;
1263 * ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1264 * of the IOSF device
1265 * @hw: pointer to hardware structure
1266 * @reg_addr: 32 bit PHY register to write
1267 * @device_type: 3 bit device type
1268 * @data: Data to write to the register
1270 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1271 u32 device_type, u32 data)
1273 struct ixgbe_hic_internal_phy_req write_cmd;
1275 UNREFERENCED_1PARAMETER(device_type);
1277 memset(&write_cmd, 0, sizeof(write_cmd));
1278 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1279 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1280 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1281 write_cmd.port_number = hw->bus.lan_id;
1282 write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1283 write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1284 write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1286 status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1288 IXGBE_HI_COMMAND_TIMEOUT, false);
1294 * ixgbe_read_iosf_sb_reg_x550a - Writes a value to specified register
1295 * of the IOSF device.
1296 * @hw: pointer to hardware structure
1297 * @reg_addr: 32 bit PHY register to write
1298 * @device_type: 3 bit device type
1299 * @data: Pointer to read data from the register
1301 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1302 u32 device_type, u32 *data)
1305 struct ixgbe_hic_internal_phy_req cmd;
1306 struct ixgbe_hic_internal_phy_resp rsp;
1309 UNREFERENCED_1PARAMETER(device_type);
1311 memset(&hic, 0, sizeof(hic));
1312 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1313 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1314 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1315 hic.cmd.port_number = hw->bus.lan_id;
1316 hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1317 hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1319 status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1321 IXGBE_HI_COMMAND_TIMEOUT, true);
1323 /* Extract the register value from the response. */
1324 *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1330 * ixgbe_disable_mdd_X550
1331 * @hw: pointer to hardware structure
1333 * Disable malicious driver detection
1335 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1339 DEBUGFUNC("ixgbe_disable_mdd_X550");
1341 /* Disable MDD for TX DMA and interrupt */
1342 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1343 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1344 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1346 /* Disable MDD for RX and interrupt */
1347 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1348 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1349 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1353 * ixgbe_enable_mdd_X550
1354 * @hw: pointer to hardware structure
1356 * Enable malicious driver detection
1358 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1362 DEBUGFUNC("ixgbe_enable_mdd_X550");
1364 /* Enable MDD for TX DMA and interrupt */
1365 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1366 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1367 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1369 /* Enable MDD for RX and interrupt */
1370 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1371 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1372 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1376 * ixgbe_restore_mdd_vf_X550
1377 * @hw: pointer to hardware structure
1380 * Restore VF that was disabled during malicious driver detection event
1382 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1384 u32 idx, reg, num_qs, start_q, bitmask;
1386 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1388 /* Map VF to queues */
1389 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1390 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1391 case IXGBE_MRQC_VMDQRT8TCEN:
1392 num_qs = 8; /* 16 VFs / pools */
1393 bitmask = 0x000000FF;
1395 case IXGBE_MRQC_VMDQRSS32EN:
1396 case IXGBE_MRQC_VMDQRT4TCEN:
1397 num_qs = 4; /* 32 VFs / pools */
1398 bitmask = 0x0000000F;
1400 default: /* 64 VFs / pools */
1402 bitmask = 0x00000003;
1405 start_q = vf * num_qs;
1407 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1410 reg |= (bitmask << (start_q % 32));
1411 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1412 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1416 * ixgbe_mdd_event_X550
1417 * @hw: pointer to hardware structure
1418 * @vf_bitmap: vf bitmap of malicious vfs
1420 * Handle malicious driver detection event.
1422 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1425 u32 i, j, reg, q, shift, vf, idx;
1427 DEBUGFUNC("ixgbe_mdd_event_X550");
1429 /* figure out pool size for mapping to vf's */
1430 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1431 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1432 case IXGBE_MRQC_VMDQRT8TCEN:
1433 shift = 3; /* 16 VFs / pools */
1435 case IXGBE_MRQC_VMDQRSS32EN:
1436 case IXGBE_MRQC_VMDQRT4TCEN:
1437 shift = 2; /* 32 VFs / pools */
1440 shift = 1; /* 64 VFs / pools */
1444 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1445 for (i = 0; i < 4; i++) {
1446 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1447 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1452 /* Get malicious queue */
1453 for (j = 0; j < 32 && wqbr; j++) {
1455 if (!(wqbr & (1 << j)))
1458 /* Get queue from bitmask */
1461 /* Map queue to vf */
1464 /* Set vf bit in vf_bitmap */
1466 vf_bitmap[idx] |= (1 << (vf % 32));
1473 * ixgbe_get_media_type_X550em - Get media type
1474 * @hw: pointer to hardware structure
1476 * Returns the media type (fiber, copper, backplane)
1478 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1480 enum ixgbe_media_type media_type;
1482 DEBUGFUNC("ixgbe_get_media_type_X550em");
1484 /* Detect if there is a copper PHY attached. */
1485 switch (hw->device_id) {
1486 case IXGBE_DEV_ID_X550EM_X_KR:
1487 case IXGBE_DEV_ID_X550EM_X_KX4:
1488 case IXGBE_DEV_ID_X550EM_A_KR:
1489 case IXGBE_DEV_ID_X550EM_A_KR_L:
1490 media_type = ixgbe_media_type_backplane;
1492 case IXGBE_DEV_ID_X550EM_X_SFP:
1493 case IXGBE_DEV_ID_X550EM_A_SFP:
1494 case IXGBE_DEV_ID_X550EM_A_SFP_N:
1495 case IXGBE_DEV_ID_X550EM_A_QSFP:
1496 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1497 media_type = ixgbe_media_type_fiber;
1499 case IXGBE_DEV_ID_X550EM_X_1G_T:
1500 case IXGBE_DEV_ID_X550EM_X_10G_T:
1501 case IXGBE_DEV_ID_X550EM_A_10G_T:
1502 media_type = ixgbe_media_type_copper;
1504 case IXGBE_DEV_ID_X550EM_A_SGMII:
1505 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1506 media_type = ixgbe_media_type_backplane;
1507 hw->phy.type = ixgbe_phy_sgmii;
1509 case IXGBE_DEV_ID_X550EM_A_1G_T:
1510 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1511 media_type = ixgbe_media_type_copper;
1514 media_type = ixgbe_media_type_unknown;
1521 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1522 * @hw: pointer to hardware structure
1523 * @linear: true if SFP module is linear
1525 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1527 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1529 switch (hw->phy.sfp_type) {
1530 case ixgbe_sfp_type_not_present:
1531 return IXGBE_ERR_SFP_NOT_PRESENT;
1532 case ixgbe_sfp_type_da_cu_core0:
1533 case ixgbe_sfp_type_da_cu_core1:
1536 case ixgbe_sfp_type_srlr_core0:
1537 case ixgbe_sfp_type_srlr_core1:
1538 case ixgbe_sfp_type_da_act_lmt_core0:
1539 case ixgbe_sfp_type_da_act_lmt_core1:
1540 case ixgbe_sfp_type_1g_sx_core0:
1541 case ixgbe_sfp_type_1g_sx_core1:
1542 case ixgbe_sfp_type_1g_lx_core0:
1543 case ixgbe_sfp_type_1g_lx_core1:
1546 case ixgbe_sfp_type_unknown:
1547 case ixgbe_sfp_type_1g_cu_core0:
1548 case ixgbe_sfp_type_1g_cu_core1:
1550 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1553 return IXGBE_SUCCESS;
1557 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1558 * @hw: pointer to hardware structure
1560 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1562 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1567 DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1569 status = ixgbe_identify_module_generic(hw);
1571 if (status != IXGBE_SUCCESS)
1574 /* Check if SFP module is supported */
1575 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1581 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1582 * @hw: pointer to hardware structure
1584 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1589 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1591 /* Check if SFP module is supported */
1592 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1594 if (status != IXGBE_SUCCESS)
1597 ixgbe_init_mac_link_ops_X550em(hw);
1598 hw->phy.ops.reset = NULL;
1600 return IXGBE_SUCCESS;
1604 * ixgbe_setup_sgmii - Set up link for sgmii
1605 * @hw: pointer to hardware structure
1607 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1610 struct ixgbe_mac_info *mac = &hw->mac;
1614 rc = mac->ops.read_iosf_sb_reg(hw,
1615 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1616 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1620 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1621 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1622 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1623 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1624 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1625 rc = mac->ops.write_iosf_sb_reg(hw,
1626 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1627 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1631 rc = mac->ops.read_iosf_sb_reg(hw,
1632 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1633 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1637 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1638 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1639 rc = mac->ops.write_iosf_sb_reg(hw,
1640 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1641 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1645 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1646 rc = mac->ops.write_iosf_sb_reg(hw,
1647 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1648 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1652 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1656 * ixgbe_setup_sgmii_m88 - Set up link for sgmii with Marvell PHYs
1657 * @hw: pointer to hardware structure
1659 STATIC s32 ixgbe_setup_sgmii_m88(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1662 struct ixgbe_mac_info *mac = &hw->mac;
1666 rc = mac->ops.read_iosf_sb_reg(hw,
1667 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1668 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1672 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1673 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1674 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1675 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1676 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1677 rc = mac->ops.write_iosf_sb_reg(hw,
1678 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1679 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1683 rc = mac->ops.read_iosf_sb_reg(hw,
1684 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1685 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1689 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1690 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1691 rc = mac->ops.write_iosf_sb_reg(hw,
1692 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1693 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1697 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1698 rc = mac->ops.write_iosf_sb_reg(hw,
1699 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1700 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1704 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1708 * ixgbe_check_link_m88 - Poll PHY for link
1709 * @hw: pointer to hardware structure
1710 * @speed: pointer to link speed
1711 * @link_up: true when link is up
1712 * @link_up_wait: bool indicating whether to wait for link
1714 * Check that both the MAC and PHY have link.
1717 ixgbe_check_link_m88(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1718 bool *link_up, bool link_up_wait)
1724 rc = ixgbe_check_mac_link_generic(hw, speed, link_up, link_up_wait);
1725 if (rc || !*link_up)
1728 rc = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_PHY_SPEC_STATUS, 0, ®);
1730 /* MAC link is up, so check external PHY link */
1731 *link_up = !!(reg & IXGBE_M88E1500_PHY_SPEC_STATUS_LINK);
1734 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
1736 (reg & IXGBE_M88E1500_PHY_SPEC_STATUS_LINK)) {
1742 rc = hw->phy.ops.read_reg(hw,
1743 IXGBE_M88E1500_PHY_SPEC_STATUS,
1748 #define M88_SPEED(x) (IXGBE_M88E1500_PHY_SPEC_STATUS_RESOLVED | \
1749 IXGBE_M88E1500_PHY_SPEC_STATUS_DUPLEX | \
1750 ((IXGBE_M88E1500_PHY_SPEC_STATUS_SPEED_##x) <<\
1751 IXGBE_M88E1500_PHY_SPEC_STATUS_SPEED_SHIFT))
1753 reg &= M88_SPEED(MASK);
1756 *speed = IXGBE_LINK_SPEED_10_FULL;
1758 case M88_SPEED(100):
1759 *speed = IXGBE_LINK_SPEED_100_FULL;
1761 case M88_SPEED(1000):
1762 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1765 *speed = IXGBE_LINK_SPEED_UNKNOWN;
1774 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1775 * @hw: pointer to hardware structure
1777 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1779 struct ixgbe_mac_info *mac = &hw->mac;
1781 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1783 switch (hw->mac.ops.get_media_type(hw)) {
1784 case ixgbe_media_type_fiber:
1785 /* CS4227 does not support autoneg, so disable the laser control
1786 * functions for SFP+ fiber
1788 mac->ops.disable_tx_laser = NULL;
1789 mac->ops.enable_tx_laser = NULL;
1790 mac->ops.flap_tx_laser = NULL;
1791 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1792 mac->ops.set_rate_select_speed =
1793 ixgbe_set_soft_rate_select_speed;
1794 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1795 (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1796 mac->ops.setup_mac_link =
1797 ixgbe_setup_mac_link_sfp_x550a;
1799 mac->ops.setup_mac_link =
1800 ixgbe_setup_mac_link_sfp_x550em;
1802 case ixgbe_media_type_copper:
1803 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
1804 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
1805 mac->ops.setup_link = ixgbe_setup_sgmii_m88;
1806 mac->ops.check_link = ixgbe_check_link_m88;
1808 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1809 mac->ops.check_link = ixgbe_check_link_t_X550em;
1812 case ixgbe_media_type_backplane:
1813 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1814 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1815 mac->ops.setup_link = ixgbe_setup_sgmii;
1823 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1824 * @hw: pointer to hardware structure
1825 * @speed: pointer to link speed
1826 * @autoneg: true when autoneg or autotry is enabled
1828 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1829 ixgbe_link_speed *speed,
1832 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1835 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1837 /* CS4227 SFP must not enable auto-negotiation */
1840 /* Check if 1G SFP module. */
1841 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1842 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1843 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1844 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1845 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1846 return IXGBE_SUCCESS;
1849 /* Link capabilities are based on SFP */
1850 if (hw->phy.multispeed_fiber)
1851 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1852 IXGBE_LINK_SPEED_1GB_FULL;
1854 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1856 switch (hw->phy.type) {
1858 *speed = IXGBE_LINK_SPEED_1GB_FULL |
1859 IXGBE_LINK_SPEED_100_FULL |
1860 IXGBE_LINK_SPEED_10_FULL;
1862 case ixgbe_phy_sgmii:
1863 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1866 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1867 IXGBE_LINK_SPEED_1GB_FULL;
1873 return IXGBE_SUCCESS;
1877 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1878 * @hw: pointer to hardware structure
1879 * @lsc: pointer to boolean flag which indicates whether external Base T
1880 * PHY interrupt is lsc
1882 * Determime if external Base T PHY interrupt cause is high temperature
1883 * failure alarm or link status change.
1885 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1886 * failure alarm, else return PHY access status.
1888 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1895 /* Vendor alarm triggered */
1896 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1897 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1900 if (status != IXGBE_SUCCESS ||
1901 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1904 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1905 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1906 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1909 if (status != IXGBE_SUCCESS ||
1910 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1911 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1914 /* Global alarm triggered */
1915 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1916 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1919 if (status != IXGBE_SUCCESS)
1922 /* If high temperature failure, then return over temp error and exit */
1923 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1924 /* power down the PHY in case the PHY FW didn't already */
1925 ixgbe_set_copper_phy_power(hw, false);
1926 return IXGBE_ERR_OVERTEMP;
1927 } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1928 /* device fault alarm triggered */
1929 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1930 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1933 if (status != IXGBE_SUCCESS)
1936 /* if device fault was due to high temp alarm handle and exit */
1937 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1938 /* power down the PHY in case the PHY FW didn't */
1939 ixgbe_set_copper_phy_power(hw, false);
1940 return IXGBE_ERR_OVERTEMP;
1944 /* Vendor alarm 2 triggered */
1945 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1946 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1948 if (status != IXGBE_SUCCESS ||
1949 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1952 /* link connect/disconnect event occurred */
1953 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1954 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1956 if (status != IXGBE_SUCCESS)
1960 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1963 return IXGBE_SUCCESS;
1967 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1968 * @hw: pointer to hardware structure
1970 * Enable link status change and temperature failure alarm for the external
1973 * Returns PHY access status
1975 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1981 /* Clear interrupt flags */
1982 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1984 /* Enable link status change alarm */
1985 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1986 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1988 if (status != IXGBE_SUCCESS)
1991 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1993 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1994 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1996 if (status != IXGBE_SUCCESS)
1999 /* Enable high temperature failure and global fault alarms */
2000 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2001 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2004 if (status != IXGBE_SUCCESS)
2007 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2008 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2010 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2011 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2014 if (status != IXGBE_SUCCESS)
2017 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2018 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2019 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2022 if (status != IXGBE_SUCCESS)
2025 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2026 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2028 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2029 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2032 if (status != IXGBE_SUCCESS)
2035 /* Enable chip-wide vendor alarm */
2036 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2037 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2040 if (status != IXGBE_SUCCESS)
2043 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2045 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2046 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2053 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2054 * @hw: pointer to hardware structure
2055 * @speed: link speed
2057 * Configures the integrated KR PHY.
2059 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2060 ixgbe_link_speed speed)
2065 status = hw->mac.ops.read_iosf_sb_reg(hw,
2066 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2067 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2071 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2072 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2073 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2075 /* Advertise 10G support. */
2076 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2077 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2079 /* Advertise 1G support. */
2080 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2081 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2083 /* Restart auto-negotiation. */
2084 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2085 status = hw->mac.ops.write_iosf_sb_reg(hw,
2086 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2087 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2093 * ixgbe_setup_m88 - setup m88 PHY
2094 * @hw: pointer to hardware structure
2096 STATIC s32 ixgbe_setup_m88(struct ixgbe_hw *hw)
2098 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2102 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2103 return IXGBE_SUCCESS;
2105 rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2109 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2112 if (reg & IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN) {
2113 reg &= ~IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN;
2114 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2118 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, ®);
2121 if (reg & IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN) {
2122 reg &= ~IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN;
2123 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0,
2127 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 2);
2131 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2135 if (reg & IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN) {
2136 reg &= ~IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN;
2137 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2139 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2143 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2147 reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2148 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2152 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2158 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2162 if (!(reg & IXGBE_M88E1500_COPPER_CTRL_AN_EN)) {
2163 reg |= IXGBE_M88E1500_COPPER_CTRL_AN_EN;
2164 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2168 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, ®);
2171 reg &= ~IXGBE_M88E1500_1000T_CTRL_HALF_DUPLEX;
2172 reg &= ~IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2173 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
2174 reg |= IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2175 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, reg);
2177 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, ®);
2180 reg &= ~IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
2181 reg &= ~IXGBE_M88E1500_COPPER_AN_PAUSE;
2182 reg &= ~IXGBE_M88E1500_COPPER_AN_T4;
2183 reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_FD;
2184 reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_HD;
2185 reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_FD;
2186 reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_HD;
2187 switch (hw->fc.current_mode) {
2189 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
2191 case ixgbe_fc_rx_pause:
2192 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
2193 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
2195 case ixgbe_fc_tx_pause:
2196 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
2202 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
2203 reg |= IXGBE_M88E1500_COPPER_AN_100TX_FD;
2204 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL)
2205 reg |= IXGBE_M88E1500_COPPER_AN_10TX_FD;
2206 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, reg);
2208 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2211 reg |= IXGBE_M88E1500_COPPER_CTRL_RESTART_AN;
2212 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2215 hw->mac.ops.release_swfw_sync(hw, mask);
2219 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2220 hw->mac.ops.release_swfw_sync(hw, mask);
2225 * ixgbe_reset_phy_m88e1500 - Reset m88e1500 PHY
2226 * @hw: pointer to hardware structure
2228 * The PHY token must be held when calling this function.
2230 static s32 ixgbe_reset_phy_m88e1500(struct ixgbe_hw *hw)
2235 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2239 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2243 reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2244 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2252 * ixgbe_reset_phy_m88e1543 - Reset m88e1543 PHY
2253 * @hw: pointer to hardware structure
2255 * The PHY token must be held when calling this function.
2257 static s32 ixgbe_reset_phy_m88e1543(struct ixgbe_hw *hw)
2259 return hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2263 * ixgbe_reset_phy_m88 - Reset m88 PHY
2264 * @hw: pointer to hardware structure
2266 STATIC s32 ixgbe_reset_phy_m88(struct ixgbe_hw *hw)
2268 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2272 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2273 return IXGBE_SUCCESS;
2275 rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2279 switch (hw->phy.id) {
2280 case IXGBE_M88E1500_E_PHY_ID:
2281 rc = ixgbe_reset_phy_m88e1500(hw);
2283 case IXGBE_M88E1543_E_PHY_ID:
2284 rc = ixgbe_reset_phy_m88e1543(hw);
2291 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2295 reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2296 IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2297 IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2298 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2302 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 18);
2306 reg = IXGBE_M88E1500_GEN_CTRL_RESET |
2307 IXGBE_M88E1500_GEN_CTRL_MODE_SGMII_COPPER;
2308 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_GEN_CTRL, 0, reg);
2312 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2316 reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2317 IXGBE_M88E1500_FIBER_CTRL_AN_EN |
2318 IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2319 IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2320 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2324 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2328 reg = (IXGBE_M88E1500_MAC_CTRL_1_DWN_4X <<
2329 IXGBE_M88E1500_MAC_CTRL_1_DWN_SHIFT) |
2330 (IXGBE_M88E1500_MAC_CTRL_1_ED_TM <<
2331 IXGBE_M88E1500_MAC_CTRL_1_ED_SHIFT) |
2332 (IXGBE_M88E1500_MAC_CTRL_1_MDIX_AUTO <<
2333 IXGBE_M88E1500_MAC_CTRL_1_MDIX_SHIFT);
2334 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, reg);
2338 reg = IXGBE_M88E1500_COPPER_CTRL_RESET |
2339 IXGBE_M88E1500_COPPER_CTRL_AN_EN |
2340 IXGBE_M88E1500_COPPER_CTRL_RESTART_AN |
2341 IXGBE_M88E1500_COPPER_CTRL_FULL_DUPLEX |
2342 IXGBE_M88E1500_COPPER_CTRL_SPEED_MSB;
2343 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2347 hw->mac.ops.release_swfw_sync(hw, mask);
2349 return ixgbe_setup_m88(hw);
2352 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2353 hw->mac.ops.release_swfw_sync(hw, mask);
2358 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2359 * @hw: pointer to hardware structure
2361 * Read NW_MNG_IF_SEL register and save field values, and check for valid field
2364 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2366 /* Save NW management interface connected on board. This is used
2367 * to determine internal PHY mode.
2369 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2371 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2372 * PHY address. This register field was has only been used for X552.
2374 if (hw->mac.type == ixgbe_mac_X550EM_a &&
2375 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2376 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2377 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2378 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2381 return IXGBE_SUCCESS;
2385 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2386 * @hw: pointer to hardware structure
2388 * Initialize any function pointers that were not able to be
2389 * set during init_shared_code because the PHY/SFP type was
2390 * not known. Perform the SFP init if necessary.
2392 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2394 struct ixgbe_phy_info *phy = &hw->phy;
2397 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2399 hw->mac.ops.set_lan_id(hw);
2401 ixgbe_read_mng_if_sel_x550em(hw);
2403 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2404 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2405 ixgbe_setup_mux_ctl(hw);
2406 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2409 switch (hw->device_id) {
2410 case IXGBE_DEV_ID_X550EM_A_1G_T:
2411 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2412 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2413 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2419 /* Identify the PHY or SFP module */
2420 ret_val = phy->ops.identify(hw);
2421 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
2424 /* Setup function pointers based on detected hardware */
2425 ixgbe_init_mac_link_ops_X550em(hw);
2426 if (phy->sfp_type != ixgbe_sfp_type_unknown)
2427 phy->ops.reset = NULL;
2429 /* Set functions pointers based on phy type */
2430 switch (hw->phy.type) {
2431 case ixgbe_phy_x550em_kx4:
2432 phy->ops.setup_link = NULL;
2433 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2434 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2436 case ixgbe_phy_x550em_kr:
2437 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2438 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2439 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2441 case ixgbe_phy_x550em_ext_t:
2442 /* If internal link mode is XFI, then setup iXFI internal link,
2443 * else setup KR now.
2445 phy->ops.setup_internal_link =
2446 ixgbe_setup_internal_phy_t_x550em;
2448 /* setup SW LPLU only for first revision of X550EM_x */
2449 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2450 !(IXGBE_FUSES0_REV_MASK &
2451 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2452 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2454 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2455 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2457 case ixgbe_phy_sgmii:
2458 phy->ops.setup_link = NULL;
2461 phy->ops.setup_link = ixgbe_setup_m88;
2462 phy->ops.reset = ixgbe_reset_phy_m88;
2471 * ixgbe_set_mdio_speed - Set MDIO clock speed
2472 * @hw: pointer to hardware structure
2474 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2478 switch (hw->device_id) {
2479 case IXGBE_DEV_ID_X550EM_X_10G_T:
2480 case IXGBE_DEV_ID_X550EM_A_SGMII:
2481 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2482 case IXGBE_DEV_ID_X550EM_A_1G_T:
2483 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2484 case IXGBE_DEV_ID_X550EM_A_10G_T:
2485 case IXGBE_DEV_ID_X550EM_A_SFP:
2486 case IXGBE_DEV_ID_X550EM_A_QSFP:
2487 /* Config MDIO clock speed before the first MDIO PHY access */
2488 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2489 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2490 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2498 * ixgbe_reset_hw_X550em - Perform hardware reset
2499 * @hw: pointer to hardware structure
2501 * Resets the hardware by resetting the transmit and receive units, masks
2502 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2505 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2507 ixgbe_link_speed link_speed;
2511 bool link_up = false;
2513 DEBUGFUNC("ixgbe_reset_hw_X550em");
2515 /* Call adapter stop to disable Tx/Rx and clear interrupts */
2516 status = hw->mac.ops.stop_adapter(hw);
2517 if (status != IXGBE_SUCCESS)
2520 /* flush pending Tx transactions */
2521 ixgbe_clear_tx_pending(hw);
2523 ixgbe_set_mdio_speed(hw);
2525 /* PHY ops must be identified and initialized prior to reset */
2526 status = hw->phy.ops.init(hw);
2528 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2531 /* start the external PHY */
2532 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2533 status = ixgbe_init_ext_t_x550em(hw);
2538 /* Setup SFP module if there is one present. */
2539 if (hw->phy.sfp_setup_needed) {
2540 status = hw->mac.ops.setup_sfp(hw);
2541 hw->phy.sfp_setup_needed = false;
2544 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2548 if (!hw->phy.reset_disable && hw->phy.ops.reset)
2549 hw->phy.ops.reset(hw);
2552 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
2553 * If link reset is used when link is up, it might reset the PHY when
2554 * mng is using it. If link is down or the flag to force full link
2555 * reset is set, then perform link reset.
2557 ctrl = IXGBE_CTRL_LNK_RST;
2558 if (!hw->force_full_reset) {
2559 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2561 ctrl = IXGBE_CTRL_RST;
2564 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2565 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2566 IXGBE_WRITE_FLUSH(hw);
2568 /* Poll for reset bit to self-clear meaning reset is complete */
2569 for (i = 0; i < 10; i++) {
2571 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2572 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2576 if (ctrl & IXGBE_CTRL_RST_MASK) {
2577 status = IXGBE_ERR_RESET_FAILED;
2578 DEBUGOUT("Reset polling failed to complete.\n");
2583 /* Double resets are required for recovery from certain error
2584 * conditions. Between resets, it is necessary to stall to
2585 * allow time for any pending HW events to complete.
2587 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2588 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2592 /* Store the permanent mac address */
2593 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2595 /* Store MAC address from RAR0, clear receive address registers, and
2596 * clear the multicast table. Also reset num_rar_entries to 128,
2597 * since we modify this value when programming the SAN MAC address.
2599 hw->mac.num_rar_entries = 128;
2600 hw->mac.ops.init_rx_addrs(hw);
2602 ixgbe_set_mdio_speed(hw);
2604 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2605 ixgbe_setup_mux_ctl(hw);
2611 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2612 * @hw: pointer to hardware structure
2614 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2619 status = hw->phy.ops.read_reg(hw,
2620 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2621 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2624 if (status != IXGBE_SUCCESS)
2627 /* If PHY FW reset completed bit is set then this is the first
2628 * SW instance after a power on so the PHY FW must be un-stalled.
2630 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2631 status = hw->phy.ops.read_reg(hw,
2632 IXGBE_MDIO_GLOBAL_RES_PR_10,
2633 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2636 if (status != IXGBE_SUCCESS)
2639 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2641 status = hw->phy.ops.write_reg(hw,
2642 IXGBE_MDIO_GLOBAL_RES_PR_10,
2643 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2646 if (status != IXGBE_SUCCESS)
2654 * ixgbe_setup_kr_x550em - Configure the KR PHY.
2655 * @hw: pointer to hardware structure
2657 * Configures the integrated KR PHY for X550EM_x.
2659 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2661 if (hw->mac.type != ixgbe_mac_X550EM_x)
2662 return IXGBE_SUCCESS;
2664 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2668 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2669 * @hw: pointer to hardware structure
2671 * Configure the external PHY and the integrated KR PHY for SFP support.
2673 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2674 ixgbe_link_speed speed,
2675 bool autoneg_wait_to_complete)
2678 u16 reg_slice, reg_val;
2679 bool setup_linear = false;
2680 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2682 /* Check if SFP module is supported and linear */
2683 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2685 /* If no SFP module present, then return success. Return success since
2686 * there is no reason to configure CS4227 and SFP not present error is
2687 * not excepted in the setup MAC link flow.
2689 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2690 return IXGBE_SUCCESS;
2692 if (ret_val != IXGBE_SUCCESS)
2695 /* Configure internal PHY for KR/KX. */
2696 ixgbe_setup_kr_speed_x550em(hw, speed);
2698 /* Configure CS4227 LINE side to proper mode. */
2699 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2700 (hw->bus.lan_id << 12);
2702 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2704 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2705 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2711 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2712 * @hw: pointer to hardware structure
2714 * Configure the the integrated PHY for SFP support.
2716 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2717 ixgbe_link_speed speed,
2718 bool autoneg_wait_to_complete)
2722 bool setup_linear = false;
2723 u32 reg_slice, reg_phy_int, slice_offset;
2725 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2727 /* Check if SFP module is supported and linear */
2728 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2730 /* If no SFP module present, then return success. Return success since
2731 * SFP not present error is not excepted in the setup MAC link flow.
2733 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2734 return IXGBE_SUCCESS;
2736 if (ret_val != IXGBE_SUCCESS)
2739 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2740 /* Configure internal PHY for native SFI */
2741 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2742 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2743 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int);
2745 if (ret_val != IXGBE_SUCCESS)
2749 reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LIMITING;
2750 reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LINEAR;
2752 reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LIMITING;
2753 reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LINEAR;
2756 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2757 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2758 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2760 if (ret_val != IXGBE_SUCCESS)
2763 /* Setup XFI/SFI internal link. */
2764 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2766 /* Configure internal PHY for KR/KX. */
2767 ixgbe_setup_kr_speed_x550em(hw, speed);
2769 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2771 DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2772 return IXGBE_ERR_PHY_ADDR_INVALID;
2775 /* Get external PHY device id */
2776 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_GLOBAL_ID_MSB,
2777 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
2779 if (ret_val != IXGBE_SUCCESS)
2782 /* When configuring quad port CS4223, the MAC instance is part
2783 * of the slice offset.
2785 if (reg_phy_ext == IXGBE_CS4223_PHY_ID)
2786 slice_offset = (hw->bus.lan_id +
2787 (hw->bus.instance_id << 1)) << 12;
2789 slice_offset = hw->bus.lan_id << 12;
2791 /* Configure CS4227/CS4223 LINE side to proper mode. */
2792 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2794 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2796 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2797 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2798 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2804 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2805 * @hw: pointer to hardware structure
2807 * iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2809 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2814 /* Disable training protocol FSM. */
2815 status = ixgbe_read_iosf_sb_reg_x550(hw,
2816 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2817 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2818 if (status != IXGBE_SUCCESS)
2820 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2821 status = ixgbe_write_iosf_sb_reg_x550(hw,
2822 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2823 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2824 if (status != IXGBE_SUCCESS)
2827 /* Disable Flex from training TXFFE. */
2828 status = ixgbe_read_iosf_sb_reg_x550(hw,
2829 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2830 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2831 if (status != IXGBE_SUCCESS)
2833 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2834 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2835 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2836 status = ixgbe_write_iosf_sb_reg_x550(hw,
2837 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2838 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2839 if (status != IXGBE_SUCCESS)
2841 status = ixgbe_read_iosf_sb_reg_x550(hw,
2842 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2843 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2844 if (status != IXGBE_SUCCESS)
2846 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2847 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2848 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2849 status = ixgbe_write_iosf_sb_reg_x550(hw,
2850 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2851 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2852 if (status != IXGBE_SUCCESS)
2855 /* Enable override for coefficients. */
2856 status = ixgbe_read_iosf_sb_reg_x550(hw,
2857 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2858 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2859 if (status != IXGBE_SUCCESS)
2861 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2862 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2863 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2864 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2865 status = ixgbe_write_iosf_sb_reg_x550(hw,
2866 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2867 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2872 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2873 * @hw: pointer to hardware structure
2874 * @speed: the link speed to force
2876 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
2877 * internal and external PHY at a specific speed, without autonegotiation.
2879 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2884 /* Disable AN and force speed to 10G Serial. */
2885 status = ixgbe_read_iosf_sb_reg_x550(hw,
2886 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2887 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2888 if (status != IXGBE_SUCCESS)
2891 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2892 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2894 /* Select forced link speed for internal PHY. */
2896 case IXGBE_LINK_SPEED_10GB_FULL:
2897 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2899 case IXGBE_LINK_SPEED_1GB_FULL:
2900 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2903 /* Other link speeds are not supported by internal KR PHY. */
2904 return IXGBE_ERR_LINK_SETUP;
2907 status = ixgbe_write_iosf_sb_reg_x550(hw,
2908 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2909 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2910 if (status != IXGBE_SUCCESS)
2913 /* Additional configuration needed for x550em_x */
2914 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2915 status = ixgbe_setup_ixfi_x550em_x(hw);
2916 if (status != IXGBE_SUCCESS)
2920 /* Toggle port SW reset by AN reset. */
2921 status = ixgbe_read_iosf_sb_reg_x550(hw,
2922 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2923 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2924 if (status != IXGBE_SUCCESS)
2926 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2927 status = ixgbe_write_iosf_sb_reg_x550(hw,
2928 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2929 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2935 * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2936 * @hw: address of hardware structure
2937 * @link_up: address of boolean to indicate link status
2939 * Returns error code if unable to get link status.
2941 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2948 /* read this twice back to back to indicate current status */
2949 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2950 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2952 if (ret != IXGBE_SUCCESS)
2955 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2956 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2958 if (ret != IXGBE_SUCCESS)
2961 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2963 return IXGBE_SUCCESS;
2967 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2968 * @hw: point to hardware structure
2970 * Configures the link between the integrated KR PHY and the external X557 PHY
2971 * The driver will call this function when it gets a link status change
2972 * interrupt from the X557 PHY. This function configures the link speed
2973 * between the PHYs to match the link speed of the BASE-T link.
2975 * A return of a non-zero value indicates an error, and the base driver should
2976 * not report link up.
2978 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2980 ixgbe_link_speed force_speed;
2985 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2986 return IXGBE_ERR_CONFIG;
2988 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2989 /* If link is down, there is no setup necessary so return */
2990 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2991 if (status != IXGBE_SUCCESS)
2995 return IXGBE_SUCCESS;
2997 status = hw->phy.ops.read_reg(hw,
2998 IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2999 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3001 if (status != IXGBE_SUCCESS)
3004 /* If link is still down - no setup is required so return */
3005 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3006 if (status != IXGBE_SUCCESS)
3009 return IXGBE_SUCCESS;
3011 /* clear everything but the speed and duplex bits */
3012 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
3015 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
3016 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3018 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
3019 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3022 /* Internal PHY does not support anything else */
3023 return IXGBE_ERR_INVALID_LINK_SETTINGS;
3026 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
3028 speed = IXGBE_LINK_SPEED_10GB_FULL |
3029 IXGBE_LINK_SPEED_1GB_FULL;
3030 return ixgbe_setup_kr_speed_x550em(hw, speed);
3035 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
3036 * @hw: pointer to hardware structure
3038 * Configures the integrated KR PHY to use internal loopback mode.
3040 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
3045 /* Disable AN and force speed to 10G Serial. */
3046 status = hw->mac.ops.read_iosf_sb_reg(hw,
3047 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3048 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3049 if (status != IXGBE_SUCCESS)
3051 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3052 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3053 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3054 status = hw->mac.ops.write_iosf_sb_reg(hw,
3055 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3056 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3057 if (status != IXGBE_SUCCESS)
3060 /* Set near-end loopback clocks. */
3061 status = hw->mac.ops.read_iosf_sb_reg(hw,
3062 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3063 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3064 if (status != IXGBE_SUCCESS)
3066 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3067 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3068 status = hw->mac.ops.write_iosf_sb_reg(hw,
3069 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3070 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3071 if (status != IXGBE_SUCCESS)
3074 /* Set loopback enable. */
3075 status = hw->mac.ops.read_iosf_sb_reg(hw,
3076 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3077 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3078 if (status != IXGBE_SUCCESS)
3080 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3081 status = hw->mac.ops.write_iosf_sb_reg(hw,
3082 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3083 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3084 if (status != IXGBE_SUCCESS)
3087 /* Training bypass. */
3088 status = hw->mac.ops.read_iosf_sb_reg(hw,
3089 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3090 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3091 if (status != IXGBE_SUCCESS)
3093 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3094 status = hw->mac.ops.write_iosf_sb_reg(hw,
3095 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3096 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3102 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3103 * assuming that the semaphore is already obtained.
3104 * @hw: pointer to hardware structure
3105 * @offset: offset of word in the EEPROM to read
3106 * @data: word read from the EEPROM
3108 * Reads a 16 bit word from the EEPROM using the hostif.
3110 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3114 struct ixgbe_hic_read_shadow_ram buffer;
3116 DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
3117 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3118 buffer.hdr.req.buf_lenh = 0;
3119 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3120 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3122 /* convert offset from words to bytes */
3123 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3125 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3127 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3129 IXGBE_HI_COMMAND_TIMEOUT, false);
3134 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3135 FW_NVM_DATA_OFFSET);
3141 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3142 * @hw: pointer to hardware structure
3143 * @offset: offset of word in the EEPROM to read
3144 * @data: word read from the EEPROM
3146 * Reads a 16 bit word from the EEPROM using the hostif.
3148 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3151 s32 status = IXGBE_SUCCESS;
3153 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3155 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3157 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
3158 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3160 status = IXGBE_ERR_SWFW_SYNC;
3167 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3168 * @hw: pointer to hardware structure
3169 * @offset: offset of word in the EEPROM to read
3170 * @words: number of words
3171 * @data: word(s) read from the EEPROM
3173 * Reads a 16 bit word(s) from the EEPROM using the hostif.
3175 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3176 u16 offset, u16 words, u16 *data)
3178 struct ixgbe_hic_read_shadow_ram buffer;
3179 u32 current_word = 0;
3184 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3186 /* Take semaphore for the entire operation. */
3187 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3189 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3193 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3194 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3196 words_to_read = words;
3198 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3199 buffer.hdr.req.buf_lenh = 0;
3200 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3201 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3203 /* convert offset from words to bytes */
3204 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3205 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3207 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3209 IXGBE_HI_COMMAND_TIMEOUT,
3213 DEBUGOUT("Host interface command failed\n");
3217 for (i = 0; i < words_to_read; i++) {
3218 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3220 u32 value = IXGBE_READ_REG(hw, reg);
3222 data[current_word] = (u16)(value & 0xffff);
3225 if (i < words_to_read) {
3227 data[current_word] = (u16)(value & 0xffff);
3231 words -= words_to_read;
3235 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3240 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3241 * @hw: pointer to hardware structure
3242 * @offset: offset of word in the EEPROM to write
3243 * @data: word write to the EEPROM
3245 * Write a 16 bit word to the EEPROM using the hostif.
3247 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3251 struct ixgbe_hic_write_shadow_ram buffer;
3253 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3255 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3256 buffer.hdr.req.buf_lenh = 0;
3257 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3258 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3261 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3263 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3265 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3267 IXGBE_HI_COMMAND_TIMEOUT, false);
3273 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3274 * @hw: pointer to hardware structure
3275 * @offset: offset of word in the EEPROM to write
3276 * @data: word write to the EEPROM
3278 * Write a 16 bit word to the EEPROM using the hostif.
3280 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3283 s32 status = IXGBE_SUCCESS;
3285 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3287 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3289 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3290 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3292 DEBUGOUT("write ee hostif failed to get semaphore");
3293 status = IXGBE_ERR_SWFW_SYNC;
3300 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3301 * @hw: pointer to hardware structure
3302 * @offset: offset of word in the EEPROM to write
3303 * @words: number of words
3304 * @data: word(s) write to the EEPROM
3306 * Write a 16 bit word(s) to the EEPROM using the hostif.
3308 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3309 u16 offset, u16 words, u16 *data)
3311 s32 status = IXGBE_SUCCESS;
3314 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3316 /* Take semaphore for the entire operation. */
3317 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3318 if (status != IXGBE_SUCCESS) {
3319 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3323 for (i = 0; i < words; i++) {
3324 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3327 if (status != IXGBE_SUCCESS) {
3328 DEBUGOUT("Eeprom buffered write failed\n");
3333 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3340 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3341 * @hw: pointer to hardware structure
3342 * @ptr: pointer offset in eeprom
3343 * @size: size of section pointed by ptr, if 0 first word will be used as size
3344 * @csum: address of checksum to update
3346 * Returns error status for any failure
3348 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3349 u16 size, u16 *csum, u16 *buffer,
3354 u16 length, bufsz, i, start;
3357 bufsz = sizeof(buf) / sizeof(buf[0]);
3359 /* Read a chunk at the pointer location */
3361 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3363 DEBUGOUT("Failed to read EEPROM image\n");
3368 if (buffer_size < ptr)
3369 return IXGBE_ERR_PARAM;
3370 local_buffer = &buffer[ptr];
3378 length = local_buffer[0];
3380 /* Skip pointer section if length is invalid. */
3381 if (length == 0xFFFF || length == 0 ||
3382 (ptr + length) >= hw->eeprom.word_size)
3383 return IXGBE_SUCCESS;
3386 if (buffer && ((u32)start + (u32)length > buffer_size))
3387 return IXGBE_ERR_PARAM;
3389 for (i = start; length; i++, length--) {
3390 if (i == bufsz && !buffer) {
3396 /* Read a chunk at the pointer location */
3397 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3400 DEBUGOUT("Failed to read EEPROM image\n");
3404 *csum += local_buffer[i];
3406 return IXGBE_SUCCESS;
3410 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3411 * @hw: pointer to hardware structure
3412 * @buffer: pointer to buffer containing calculated checksum
3413 * @buffer_size: size of buffer
3415 * Returns a negative error code on error, or the 16-bit checksum
3417 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3419 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3423 u16 pointer, i, size;
3425 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3427 hw->eeprom.ops.init_params(hw);
3430 /* Read pointer area */
3431 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3432 IXGBE_EEPROM_LAST_WORD + 1,
3435 DEBUGOUT("Failed to read EEPROM image\n");
3438 local_buffer = eeprom_ptrs;
3440 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3441 return IXGBE_ERR_PARAM;
3442 local_buffer = buffer;
3446 * For X550 hardware include 0x0-0x41 in the checksum, skip the
3447 * checksum word itself
3449 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3450 if (i != IXGBE_EEPROM_CHECKSUM)
3451 checksum += local_buffer[i];
3454 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
3455 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3457 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3458 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3461 pointer = local_buffer[i];
3463 /* Skip pointer section if the pointer is invalid. */
3464 if (pointer == 0xFFFF || pointer == 0 ||
3465 pointer >= hw->eeprom.word_size)
3469 case IXGBE_PCIE_GENERAL_PTR:
3470 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3472 case IXGBE_PCIE_CONFIG0_PTR:
3473 case IXGBE_PCIE_CONFIG1_PTR:
3474 size = IXGBE_PCIE_CONFIG_SIZE;
3481 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3482 buffer, buffer_size);
3487 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3489 return (s32)checksum;
3493 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3494 * @hw: pointer to hardware structure
3496 * Returns a negative error code on error, or the 16-bit checksum
3498 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3500 return ixgbe_calc_checksum_X550(hw, NULL, 0);
3504 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3505 * @hw: pointer to hardware structure
3506 * @checksum_val: calculated checksum
3508 * Performs checksum calculation and validates the EEPROM checksum. If the
3509 * caller does not need checksum_val, the value can be NULL.
3511 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3515 u16 read_checksum = 0;
3517 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3519 /* Read the first word from the EEPROM. If this times out or fails, do
3520 * not continue or we could be in for a very long wait while every
3523 status = hw->eeprom.ops.read(hw, 0, &checksum);
3525 DEBUGOUT("EEPROM read failed\n");
3529 status = hw->eeprom.ops.calc_checksum(hw);
3533 checksum = (u16)(status & 0xffff);
3535 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3540 /* Verify read checksum from EEPROM is the same as
3541 * calculated checksum
3543 if (read_checksum != checksum) {
3544 status = IXGBE_ERR_EEPROM_CHECKSUM;
3545 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3546 "Invalid EEPROM checksum");
3549 /* If the user cares, return the calculated checksum */
3551 *checksum_val = checksum;
3557 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3558 * @hw: pointer to hardware structure
3560 * After writing EEPROM to shadow RAM using EEWR register, software calculates
3561 * checksum and updates the EEPROM and instructs the hardware to update
3564 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3569 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3571 /* Read the first word from the EEPROM. If this times out or fails, do
3572 * not continue or we could be in for a very long wait while every
3575 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3577 DEBUGOUT("EEPROM read failed\n");
3581 status = ixgbe_calc_eeprom_checksum_X550(hw);
3585 checksum = (u16)(status & 0xffff);
3587 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3592 status = ixgbe_update_flash_X550(hw);
3598 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3599 * @hw: pointer to hardware structure
3601 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3603 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3605 s32 status = IXGBE_SUCCESS;
3606 union ixgbe_hic_hdr2 buffer;
3608 DEBUGFUNC("ixgbe_update_flash_X550");
3610 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3611 buffer.req.buf_lenh = 0;
3612 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3613 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3615 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3617 IXGBE_HI_COMMAND_TIMEOUT, false);
3623 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3624 * @hw: pointer to hardware structure
3626 * Determines physical layer capabilities of the current configuration.
3628 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3630 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3631 u16 ext_ability = 0;
3633 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3635 hw->phy.ops.identify(hw);
3637 switch (hw->phy.type) {
3638 case ixgbe_phy_x550em_kr:
3639 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3640 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3642 case ixgbe_phy_x550em_kx4:
3643 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3644 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3646 case ixgbe_phy_x550em_ext_t:
3647 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3648 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3650 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3651 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3652 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3653 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3659 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3660 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3662 return physical_layer;
3666 * ixgbe_get_bus_info_x550em - Set PCI bus info
3667 * @hw: pointer to hardware structure
3669 * Sets bus link width and speed to unknown because X550em is
3672 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3675 DEBUGFUNC("ixgbe_get_bus_info_x550em");
3677 hw->bus.width = ixgbe_bus_width_unknown;
3678 hw->bus.speed = ixgbe_bus_speed_unknown;
3680 hw->mac.ops.set_lan_id(hw);
3682 return IXGBE_SUCCESS;
3686 * ixgbe_disable_rx_x550 - Disable RX unit
3688 * Enables the Rx DMA unit for x550
3690 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3692 u32 rxctrl, pfdtxgswc;
3694 struct ixgbe_hic_disable_rxen fw_cmd;
3696 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3698 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3699 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3700 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3701 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3702 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3703 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3704 hw->mac.set_lben = true;
3706 hw->mac.set_lben = false;
3709 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3710 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3711 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3712 fw_cmd.port_number = (u8)hw->bus.lan_id;
3714 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3715 sizeof(struct ixgbe_hic_disable_rxen),
3716 IXGBE_HI_COMMAND_TIMEOUT, true);
3718 /* If we fail - disable RX using register write */
3720 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3721 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3722 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3723 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3730 * ixgbe_enter_lplu_x550em - Transition to low power states
3731 * @hw: pointer to hardware structure
3733 * Configures Low Power Link Up on transition to low power states
3734 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3735 * X557 PHY immediately prior to entering LPLU.
3737 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3739 u16 an_10g_cntl_reg, autoneg_reg, speed;
3741 ixgbe_link_speed lcd_speed;
3745 /* SW LPLU not required on later HW revisions. */
3746 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3747 (IXGBE_FUSES0_REV_MASK &
3748 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3749 return IXGBE_SUCCESS;
3751 /* If blocked by MNG FW, then don't restart AN */
3752 if (ixgbe_check_reset_blocked(hw))
3753 return IXGBE_SUCCESS;
3755 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3756 if (status != IXGBE_SUCCESS)
3759 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3761 if (status != IXGBE_SUCCESS)
3764 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3765 * disabled, then force link down by entering low power mode.
3767 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3768 !(hw->wol_enabled || ixgbe_mng_present(hw)))
3769 return ixgbe_set_copper_phy_power(hw, FALSE);
3772 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3774 if (status != IXGBE_SUCCESS)
3777 /* If no valid LCD link speed, then force link down and exit. */
3778 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3779 return ixgbe_set_copper_phy_power(hw, FALSE);
3781 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3782 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3785 if (status != IXGBE_SUCCESS)
3788 /* If no link now, speed is invalid so take link down */
3789 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3790 if (status != IXGBE_SUCCESS)
3791 return ixgbe_set_copper_phy_power(hw, false);
3793 /* clear everything but the speed bits */
3794 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3796 /* If current speed is already LCD, then exit. */
3797 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3798 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3799 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3800 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3803 /* Clear AN completed indication */
3804 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3805 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3808 if (status != IXGBE_SUCCESS)
3811 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3812 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3815 if (status != IXGBE_SUCCESS)
3818 status = hw->phy.ops.read_reg(hw,
3819 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3820 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3823 if (status != IXGBE_SUCCESS)
3826 save_autoneg = hw->phy.autoneg_advertised;
3828 /* Setup link at least common link speed */
3829 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3831 /* restore autoneg from before setting lplu speed */
3832 hw->phy.autoneg_advertised = save_autoneg;
3838 * ixgbe_get_lcd_x550em - Determine lowest common denominator
3839 * @hw: pointer to hardware structure
3840 * @lcd_speed: pointer to lowest common link speed
3842 * Determine lowest common link speed with link partner.
3844 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3848 u16 word = hw->eeprom.ctrl_word_3;
3850 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3852 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3853 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3856 if (status != IXGBE_SUCCESS)
3859 /* If link partner advertised 1G, return 1G */
3860 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3861 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3865 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3866 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3867 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3870 /* Link partner not capable of lower speeds, return 10G */
3871 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3876 * ixgbe_setup_fc_X550em - Set up flow control
3877 * @hw: pointer to hardware structure
3879 * Called at init time to set up flow control.
3881 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3883 s32 ret_val = IXGBE_SUCCESS;
3884 u32 pause, asm_dir, reg_val;
3886 DEBUGFUNC("ixgbe_setup_fc_X550em");
3888 /* Validate the requested mode */
3889 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3890 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3891 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3892 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3896 /* 10gig parts do not have a word in the EEPROM to determine the
3897 * default flow control setting, so we explicitly set it to full.
3899 if (hw->fc.requested_mode == ixgbe_fc_default)
3900 hw->fc.requested_mode = ixgbe_fc_full;
3902 /* Determine PAUSE and ASM_DIR bits. */
3903 switch (hw->fc.requested_mode) {
3908 case ixgbe_fc_tx_pause:
3912 case ixgbe_fc_rx_pause:
3913 /* Rx Flow control is enabled and Tx Flow control is
3914 * disabled by software override. Since there really
3915 * isn't a way to advertise that we are capable of RX
3916 * Pause ONLY, we will advertise that we support both
3917 * symmetric and asymmetric Rx PAUSE, as such we fall
3918 * through to the fc_full statement. Later, we will
3919 * disable the adapter's ability to send PAUSE frames.
3926 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3927 "Flow control param set incorrectly\n");
3928 ret_val = IXGBE_ERR_CONFIG;
3932 switch (hw->device_id) {
3933 case IXGBE_DEV_ID_X550EM_X_KR:
3934 case IXGBE_DEV_ID_X550EM_A_KR:
3935 case IXGBE_DEV_ID_X550EM_A_KR_L:
3936 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
3937 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3938 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3939 if (ret_val != IXGBE_SUCCESS)
3941 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3942 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3944 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3946 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3947 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
3948 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3949 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3951 /* This device does not fully support AN. */
3952 hw->fc.disable_fc_autoneg = true;
3963 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
3964 * @hw: pointer to hardware structure
3966 * Enable flow control according to IEEE clause 37.
3968 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
3970 u32 link_s1, lp_an_page_low, an_cntl_1;
3971 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
3972 ixgbe_link_speed speed;
3975 /* AN should have completed when the cable was plugged in.
3976 * Look for reasons to bail out. Bail out if:
3977 * - FC autoneg is disabled, or if
3980 if (hw->fc.disable_fc_autoneg) {
3981 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3982 "Flow control autoneg is disabled");
3986 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3988 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3992 /* Check at auto-negotiation has completed */
3993 status = hw->mac.ops.read_iosf_sb_reg(hw,
3994 IXGBE_KRM_LINK_S1(hw->bus.lan_id),
3995 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
3997 if (status != IXGBE_SUCCESS ||
3998 (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
3999 DEBUGOUT("Auto-Negotiation did not complete\n");
4000 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4004 /* Read the 10g AN autoc and LP ability registers and resolve
4005 * local flow control settings accordingly
4007 status = hw->mac.ops.read_iosf_sb_reg(hw,
4008 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4009 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
4011 if (status != IXGBE_SUCCESS) {
4012 DEBUGOUT("Auto-Negotiation did not complete\n");
4016 status = hw->mac.ops.read_iosf_sb_reg(hw,
4017 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
4018 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
4020 if (status != IXGBE_SUCCESS) {
4021 DEBUGOUT("Auto-Negotiation did not complete\n");
4025 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
4026 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
4027 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
4028 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
4029 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
4032 if (status == IXGBE_SUCCESS) {
4033 hw->fc.fc_was_autonegged = true;
4035 hw->fc.fc_was_autonegged = false;
4036 hw->fc.current_mode = hw->fc.requested_mode;
4041 * ixgbe_fc_autoneg_fiber_x550em_a - Enable flow control IEEE clause 37
4042 * @hw: pointer to hardware structure
4044 * Enable flow control according to IEEE clause 37.
4046 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
4048 u32 link_s1, pcs_an_lp, pcs_an;
4049 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4050 ixgbe_link_speed speed;
4053 /* AN should have completed when the cable was plugged in.
4054 * Look for reasons to bail out. Bail out if:
4055 * - FC autoneg is disabled, or if
4058 if (hw->fc.disable_fc_autoneg) {
4059 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4060 "Flow control autoneg is disabled");
4064 hw->mac.ops.check_link(hw, &speed, &link_up, false);
4066 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4070 /* Check if auto-negotiation has completed */
4071 status = hw->mac.ops.read_iosf_sb_reg(hw,
4072 IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4073 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4075 if (status != IXGBE_SUCCESS ||
4076 (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4077 DEBUGOUT("Auto-Negotiation did not complete\n");
4078 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4082 /* Determine advertised flow control */
4083 status = hw->mac.ops.read_iosf_sb_reg(hw,
4084 IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id),
4085 IXGBE_SB_IOSF_TARGET_KR_PHY, &pcs_an);
4087 if (status != IXGBE_SUCCESS) {
4088 DEBUGOUT("Auto-Negotiation did not complete\n");
4092 /* Determine link parter flow control */
4093 status = hw->mac.ops.read_iosf_sb_reg(hw,
4094 IXGBE_KRM_PCS_KX_AN_LP(hw->bus.lan_id),
4095 IXGBE_SB_IOSF_TARGET_KR_PHY, &pcs_an_lp);
4097 if (status != IXGBE_SUCCESS) {
4098 DEBUGOUT("Auto-Negotiation did not complete\n");
4102 status = ixgbe_negotiate_fc(hw, pcs_an, pcs_an_lp,
4103 IXGBE_KRM_PCS_KX_AN_SYM_PAUSE,
4104 IXGBE_KRM_PCS_KX_AN_ASM_PAUSE,
4105 IXGBE_KRM_PCS_KX_AN_LP_SYM_PAUSE,
4106 IXGBE_KRM_PCS_KX_AN_LP_ASM_PAUSE);
4109 if (status == IXGBE_SUCCESS) {
4110 hw->fc.fc_was_autonegged = true;
4112 hw->fc.fc_was_autonegged = false;
4113 hw->fc.current_mode = hw->fc.requested_mode;
4118 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4119 * @hw: pointer to hardware structure
4121 * Called at init time to set up flow control.
4123 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4125 s32 status = IXGBE_SUCCESS;
4126 u32 an_cntl, link_ctrl = 0;
4128 DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4130 /* Validate the requested mode */
4131 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4132 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4133 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4134 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4137 if (hw->fc.requested_mode == ixgbe_fc_default)
4138 hw->fc.requested_mode = ixgbe_fc_full;
4140 /* Set up the 1G and 10G flow control advertisement registers so the
4141 * HW will be able to do FC autoneg once the cable is plugged in. If
4142 * we link at 10G, the 1G advertisement is harmless and vice versa.
4144 status = hw->mac.ops.read_iosf_sb_reg(hw,
4145 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4146 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4148 if (status != IXGBE_SUCCESS) {
4149 DEBUGOUT("Auto-Negotiation did not complete\n");
4153 /* The possible values of fc.requested_mode are:
4154 * 0: Flow control is completely disabled
4155 * 1: Rx flow control is enabled (we can receive pause frames,
4156 * but not send pause frames).
4157 * 2: Tx flow control is enabled (we can send pause frames but
4158 * we do not support receiving pause frames).
4159 * 3: Both Rx and Tx flow control (symmetric) are enabled.
4162 switch (hw->fc.requested_mode) {
4164 /* Flow control completely disabled by software override. */
4165 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4166 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4168 case ixgbe_fc_tx_pause:
4169 /* Tx Flow control is enabled, and Rx Flow control is
4170 * disabled by software override.
4172 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4173 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4175 case ixgbe_fc_rx_pause:
4176 /* Rx Flow control is enabled and Tx Flow control is
4177 * disabled by software override. Since there really
4178 * isn't a way to advertise that we are capable of RX
4179 * Pause ONLY, we will advertise that we support both
4180 * symmetric and asymmetric Rx PAUSE, as such we fall
4181 * through to the fc_full statement. Later, we will
4182 * disable the adapter's ability to send PAUSE frames.
4185 /* Flow control (both Rx and Tx) is enabled by SW override. */
4186 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4187 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4190 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4191 "Flow control param set incorrectly\n");
4192 return IXGBE_ERR_CONFIG;
4195 status = hw->mac.ops.write_iosf_sb_reg(hw,
4196 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4197 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4199 /* Restart auto-negotiation. */
4200 status = hw->mac.ops.read_iosf_sb_reg(hw,
4201 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4202 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
4204 if (status != IXGBE_SUCCESS) {
4205 DEBUGOUT("Auto-Negotiation did not complete\n");
4209 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
4210 status = hw->mac.ops.write_iosf_sb_reg(hw,
4211 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4212 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
4218 * ixgbe_setup_fc_fiber_x550em_a - Set up flow control
4219 * @hw: pointer to hardware structure
4221 * Called at init time to set up flow control.
4223 s32 ixgbe_setup_fc_fiber_x550em_a(struct ixgbe_hw *hw)
4225 struct ixgbe_mac_info *mac = &hw->mac;
4226 s32 rc = IXGBE_SUCCESS;
4227 u32 an_cntl4, lctrl, pcs_an;
4229 DEBUGFUNC("ixgbe_setup_fc_fiber_x550em_a");
4231 /* Validate the requested mode */
4232 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4233 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4234 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4235 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4238 /* Enable clause 37 auto-negotiation in KRM_LINK_CTRL_1 */
4239 if (hw->fc.requested_mode == ixgbe_fc_default)
4240 hw->fc.requested_mode = ixgbe_fc_full;
4242 rc = mac->ops.read_iosf_sb_reg(hw,
4243 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4244 IXGBE_SB_IOSF_TARGET_KR_PHY, &lctrl);
4248 lctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
4249 lctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
4251 rc = mac->ops.write_iosf_sb_reg(hw,
4252 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4253 IXGBE_SB_IOSF_TARGET_KR_PHY, lctrl);
4257 /* Enable clause 37 over 73 in KRM_AN_CNTL_4 */
4258 rc = mac->ops.read_iosf_sb_reg(hw,
4259 IXGBE_KRM_AN_CNTL_4(hw->bus.lan_id),
4260 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl4);
4264 an_cntl4 |= IXGBE_KRM_AN_CNTL_4_ECSR_AN37_OVER_73;
4266 rc = mac->ops.write_iosf_sb_reg(hw,
4267 IXGBE_KRM_AN_CNTL_4(hw->bus.lan_id),
4268 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl4);
4272 rc = hw->mac.ops.read_iosf_sb_reg(hw,
4273 IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id),
4274 IXGBE_SB_IOSF_TARGET_KR_PHY, &pcs_an);
4279 /* The possible values of fc.requested_mode are:
4280 * 0: Flow control is completely disabled
4281 * 1: Rx flow control is enabled (we can receive pause frames,
4282 * but not send pause frames).
4283 * 2: Tx flow control is enabled (we can send pause frames but
4284 * we do not support receiving pause frames).
4285 * 3: Both Rx and Tx flow control (symmetric) are enabled.
4288 switch (hw->fc.requested_mode) {
4290 /* Flow control completely disabled by software override. */
4291 pcs_an &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4292 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4294 case ixgbe_fc_tx_pause:
4295 /* Tx Flow control is enabled, and Rx Flow control is
4296 * disabled by software override.
4298 pcs_an |= IXGBE_KRM_PCS_KX_AN_ASM_PAUSE;
4299 pcs_an &= ~IXGBE_KRM_PCS_KX_AN_SYM_PAUSE;
4301 case ixgbe_fc_rx_pause:
4302 /* Rx Flow control is enabled and Tx Flow control is
4303 * disabled by software override. Since there really
4304 * isn't a way to advertise that we are capable of RX
4305 * Pause ONLY, we will advertise that we support both
4306 * symmetric and asymmetric Rx PAUSE, as such we fall
4307 * through to the fc_full statement. Later, we will
4308 * disable the adapter's ability to send PAUSE frames.
4311 /* Flow control (both Rx and Tx) is enabled by SW override. */
4312 pcs_an |= IXGBE_KRM_PCS_KX_AN_SYM_PAUSE |
4313 IXGBE_KRM_PCS_KX_AN_ASM_PAUSE;
4316 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4317 "Flow control param set incorrectly\n");
4318 return IXGBE_ERR_CONFIG;
4321 rc = hw->mac.ops.write_iosf_sb_reg(hw,
4322 IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id),
4323 IXGBE_SB_IOSF_TARGET_KR_PHY, pcs_an);
4325 /* Restart auto-negotiation. */
4326 rc = hw->mac.ops.read_iosf_sb_reg(hw,
4327 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4328 IXGBE_SB_IOSF_TARGET_KR_PHY, &lctrl);
4331 DEBUGOUT("Auto-Negotiation did not complete\n");
4335 lctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
4336 rc = hw->mac.ops.write_iosf_sb_reg(hw,
4337 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4338 IXGBE_SB_IOSF_TARGET_KR_PHY, lctrl);
4344 * ixgbe_set_mux - Set mux for port 1 access with CS4227
4345 * @hw: pointer to hardware structure
4346 * @state: set mux if 1, clear if 0
4348 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4352 if (!hw->bus.lan_id)
4354 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4356 esdp |= IXGBE_ESDP_SDP1;
4358 esdp &= ~IXGBE_ESDP_SDP1;
4359 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4360 IXGBE_WRITE_FLUSH(hw);
4364 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4365 * @hw: pointer to hardware structure
4366 * @mask: Mask to specify which semaphore to acquire
4368 * Acquires the SWFW semaphore and sets the I2C MUX
4370 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4374 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4376 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4380 if (mask & IXGBE_GSSR_I2C_MASK)
4381 ixgbe_set_mux(hw, 1);
4383 return IXGBE_SUCCESS;
4387 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4388 * @hw: pointer to hardware structure
4389 * @mask: Mask to specify which semaphore to release
4391 * Releases the SWFW semaphore and sets the I2C MUX
4393 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4395 DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4397 if (mask & IXGBE_GSSR_I2C_MASK)
4398 ixgbe_set_mux(hw, 0);
4400 ixgbe_release_swfw_sync_X540(hw, mask);
4404 * ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4405 * @hw: pointer to hardware structure
4406 * @mask: Mask to specify which semaphore to acquire
4408 * Acquires the SWFW semaphore and get the shared phy token as needed
4410 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4412 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4413 int retries = FW_PHY_TOKEN_RETRIES;
4414 s32 status = IXGBE_SUCCESS;
4416 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4419 status = IXGBE_SUCCESS;
4421 status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4424 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4425 return IXGBE_SUCCESS;
4427 status = ixgbe_get_phy_token(hw);
4428 if (status == IXGBE_SUCCESS)
4429 return IXGBE_SUCCESS;
4432 ixgbe_release_swfw_sync_X540(hw, hmask);
4433 if (status != IXGBE_ERR_TOKEN_RETRY)
4435 msec_delay(FW_PHY_TOKEN_DELAY);
4442 * ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4443 * @hw: pointer to hardware structure
4444 * @mask: Mask to specify which semaphore to release
4446 * Releases the SWFW semaphore and puts the shared phy token as needed
4448 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4450 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4452 DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4454 if (mask & IXGBE_GSSR_TOKEN_SM)
4455 ixgbe_put_phy_token(hw);
4458 ixgbe_release_swfw_sync_X540(hw, hmask);
4462 * ixgbe_read_phy_reg_x550a - Reads specified PHY register
4463 * @hw: pointer to hardware structure
4464 * @reg_addr: 32 bit address of PHY register to read
4465 * @phy_data: Pointer to read data from PHY register
4467 * Reads a value from a specified PHY register using the SWFW lock and PHY
4468 * Token. The PHY Token is needed since the MDIO is shared between to MAC
4471 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4472 u32 device_type, u16 *phy_data)
4475 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4477 DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4479 if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4480 return IXGBE_ERR_SWFW_SYNC;
4482 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4484 hw->mac.ops.release_swfw_sync(hw, mask);
4490 * ixgbe_write_phy_reg_x550a - Writes specified PHY register
4491 * @hw: pointer to hardware structure
4492 * @reg_addr: 32 bit PHY register to write
4493 * @device_type: 5 bit device type
4494 * @phy_data: Data to write to the PHY register
4496 * Writes a value to specified PHY register using the SWFW lock and PHY Token.
4497 * The PHY Token is needed since the MDIO is shared between to MAC instances.
4499 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4500 u32 device_type, u16 phy_data)
4503 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4505 DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4507 if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4508 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
4510 hw->mac.ops.release_swfw_sync(hw, mask);
4512 status = IXGBE_ERR_SWFW_SYNC;
4519 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4520 * @hw: pointer to hardware structure
4522 * Handle external Base T PHY interrupt. If high temperature
4523 * failure alarm then return error, else if link status change
4524 * then setup internal/external PHY link
4526 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4527 * failure alarm, else return PHY access status.
4529 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4534 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4536 if (status != IXGBE_SUCCESS)
4540 return ixgbe_setup_internal_phy(hw);
4542 return IXGBE_SUCCESS;
4546 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4547 * @hw: pointer to hardware structure
4548 * @speed: new link speed
4549 * @autoneg_wait_to_complete: true when waiting for completion is needed
4551 * Setup internal/external PHY link speed based on link speed, then set
4552 * external PHY auto advertised link speed.
4554 * Returns error status for any failure
4556 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4557 ixgbe_link_speed speed,
4558 bool autoneg_wait_to_complete)
4561 ixgbe_link_speed force_speed;
4563 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4565 /* Setup internal/external PHY link speed to iXFI (10G), unless
4566 * only 1G is auto advertised then setup KX link.
4568 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4569 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4571 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4573 /* If internal link mode is XFI, then setup XFI internal link. */
4574 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4575 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4577 if (status != IXGBE_SUCCESS)
4581 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4585 * ixgbe_check_link_t_X550em - Determine link and speed status
4586 * @hw: pointer to hardware structure
4587 * @speed: pointer to link speed
4588 * @link_up: true when link is up
4589 * @link_up_wait_to_complete: bool used to wait for link up or not
4591 * Check that both the MAC and X557 external PHY have link.
4593 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4594 bool *link_up, bool link_up_wait_to_complete)
4599 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4600 return IXGBE_ERR_CONFIG;
4602 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4603 link_up_wait_to_complete);
4605 /* If check link fails or MAC link is not up, then return */
4606 if (status != IXGBE_SUCCESS || !(*link_up))
4609 /* MAC link is up, so check external PHY link.
4610 * Read this twice back to back to indicate current status.
4612 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4613 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4616 if (status != IXGBE_SUCCESS)
4619 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4620 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4623 if (status != IXGBE_SUCCESS)
4626 /* If external PHY link is not up, then indicate link not up */
4627 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4630 return IXGBE_SUCCESS;
4634 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4635 * @hw: pointer to hardware structure
4637 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4641 status = ixgbe_reset_phy_generic(hw);
4643 if (status != IXGBE_SUCCESS)
4646 /* Configure Link Status Alarm and Temperature Threshold interrupts */
4647 return ixgbe_enable_lasi_ext_t_x550em(hw);
4651 * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4652 * @hw: pointer to hardware structure
4653 * @led_idx: led number to turn on
4655 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4659 DEBUGFUNC("ixgbe_led_on_t_X550em");
4661 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4662 return IXGBE_ERR_PARAM;
4664 /* To turn on the LED, set mode to ON. */
4665 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4666 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4667 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4668 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4669 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4671 return IXGBE_SUCCESS;
4675 * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4676 * @hw: pointer to hardware structure
4677 * @led_idx: led number to turn off
4679 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4683 DEBUGFUNC("ixgbe_led_off_t_X550em");
4685 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4686 return IXGBE_ERR_PARAM;
4688 /* To turn on the LED, set mode to ON. */
4689 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4690 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4691 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4692 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4693 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4695 return IXGBE_SUCCESS;