1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
44 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw);
47 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
48 * @hw: pointer to hardware structure
50 * Initialize the function pointers and assign the MAC type for X550.
51 * Does not touch the hardware.
53 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
55 struct ixgbe_mac_info *mac = &hw->mac;
56 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
59 DEBUGFUNC("ixgbe_init_ops_X550");
61 ret_val = ixgbe_init_ops_X540(hw);
62 mac->ops.dmac_config = ixgbe_dmac_config_X550;
63 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
64 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
65 mac->ops.setup_eee = NULL;
66 mac->ops.set_source_address_pruning =
67 ixgbe_set_source_address_pruning_X550;
68 mac->ops.set_ethertype_anti_spoofing =
69 ixgbe_set_ethertype_anti_spoofing_X550;
71 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
72 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
73 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
74 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
75 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
76 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
77 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
78 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
79 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
81 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
82 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
83 mac->ops.mdd_event = ixgbe_mdd_event_X550;
84 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
85 mac->ops.disable_rx = ixgbe_disable_rx_x550;
86 /* Manageability interface */
87 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_x550;
88 switch (hw->device_id) {
89 case IXGBE_DEV_ID_X550EM_X_10G_T:
90 case IXGBE_DEV_ID_X550EM_A_10G_T:
91 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
92 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
101 * ixgbe_read_cs4227 - Read CS4227 register
102 * @hw: pointer to hardware structure
103 * @reg: register number to write
104 * @value: pointer to receive value read
106 * Returns status code
108 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
110 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
114 * ixgbe_write_cs4227 - Write CS4227 register
115 * @hw: pointer to hardware structure
116 * @reg: register number to write
117 * @value: value to write to register
119 * Returns status code
121 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
123 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
127 * ixgbe_read_pe - Read register from port expander
128 * @hw: pointer to hardware structure
129 * @reg: register number to read
130 * @value: pointer to receive read value
132 * Returns status code
134 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
138 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
139 if (status != IXGBE_SUCCESS)
140 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
141 "port expander access failed with %d\n", status);
146 * ixgbe_write_pe - Write register to port expander
147 * @hw: pointer to hardware structure
148 * @reg: register number to write
149 * @value: value to write
151 * Returns status code
153 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
157 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
158 if (status != IXGBE_SUCCESS)
159 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
160 "port expander access failed with %d\n", status);
165 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
166 * @hw: pointer to hardware structure
168 * This function assumes that the caller has acquired the proper semaphore.
171 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
178 /* Trigger hard reset. */
179 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
180 if (status != IXGBE_SUCCESS)
182 reg |= IXGBE_PE_BIT1;
183 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
184 if (status != IXGBE_SUCCESS)
187 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
188 if (status != IXGBE_SUCCESS)
190 reg &= ~IXGBE_PE_BIT1;
191 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
192 if (status != IXGBE_SUCCESS)
195 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
196 if (status != IXGBE_SUCCESS)
198 reg &= ~IXGBE_PE_BIT1;
199 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
200 if (status != IXGBE_SUCCESS)
203 usec_delay(IXGBE_CS4227_RESET_HOLD);
205 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
206 if (status != IXGBE_SUCCESS)
208 reg |= IXGBE_PE_BIT1;
209 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
210 if (status != IXGBE_SUCCESS)
213 /* Wait for the reset to complete. */
214 msec_delay(IXGBE_CS4227_RESET_DELAY);
215 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
216 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
218 if (status == IXGBE_SUCCESS &&
219 value == IXGBE_CS4227_EEPROM_LOAD_OK)
221 msec_delay(IXGBE_CS4227_CHECK_DELAY);
223 if (retry == IXGBE_CS4227_RETRIES) {
224 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
225 "CS4227 reset did not complete.");
226 return IXGBE_ERR_PHY;
229 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
230 if (status != IXGBE_SUCCESS ||
231 !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
232 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
233 "CS4227 EEPROM did not load successfully.");
234 return IXGBE_ERR_PHY;
237 return IXGBE_SUCCESS;
241 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
242 * @hw: pointer to hardware structure
244 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
246 s32 status = IXGBE_SUCCESS;
247 u32 swfw_mask = hw->phy.phy_semaphore_mask;
251 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
252 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
253 if (status != IXGBE_SUCCESS) {
254 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
255 "semaphore failed with %d", status);
256 msec_delay(IXGBE_CS4227_CHECK_DELAY);
260 /* Get status of reset flow. */
261 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
263 if (status == IXGBE_SUCCESS &&
264 value == IXGBE_CS4227_RESET_COMPLETE)
267 if (status != IXGBE_SUCCESS ||
268 value != IXGBE_CS4227_RESET_PENDING)
271 /* Reset is pending. Wait and check again. */
272 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
273 msec_delay(IXGBE_CS4227_CHECK_DELAY);
276 /* If still pending, assume other instance failed. */
277 if (retry == IXGBE_CS4227_RETRIES) {
278 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
279 if (status != IXGBE_SUCCESS) {
280 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
281 "semaphore failed with %d", status);
286 /* Reset the CS4227. */
287 status = ixgbe_reset_cs4227(hw);
288 if (status != IXGBE_SUCCESS) {
289 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
290 "CS4227 reset failed: %d", status);
294 /* Reset takes so long, temporarily release semaphore in case the
295 * other driver instance is waiting for the reset indication.
297 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
298 IXGBE_CS4227_RESET_PENDING);
299 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
301 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
302 if (status != IXGBE_SUCCESS) {
303 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
304 "semaphore failed with %d", status);
308 /* Record completion for next time. */
309 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
310 IXGBE_CS4227_RESET_COMPLETE);
313 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
314 msec_delay(hw->eeprom.semaphore_delay);
318 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
319 * @hw: pointer to hardware structure
321 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
323 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
325 if (hw->bus.lan_id) {
326 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
327 esdp |= IXGBE_ESDP_SDP1_DIR;
329 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
330 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
331 IXGBE_WRITE_FLUSH(hw);
335 * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
336 * @hw: pointer to hardware structure
337 * @reg_addr: 32 bit address of PHY register to read
338 * @dev_type: always unused
339 * @phy_data: Pointer to read data from PHY register
341 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
342 u32 dev_type, u16 *phy_data)
344 u32 i, data, command;
345 UNREFERENCED_1PARAMETER(dev_type);
347 /* Setup and write the read command */
348 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
349 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
350 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
351 IXGBE_MSCA_MDI_COMMAND;
353 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
355 /* Check every 10 usec to see if the access completed.
356 * The MDI Command bit will clear when the operation is
359 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
362 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
363 if (!(command & IXGBE_MSCA_MDI_COMMAND))
367 if (command & IXGBE_MSCA_MDI_COMMAND) {
368 ERROR_REPORT1(IXGBE_ERROR_POLLING,
369 "PHY read command did not complete.\n");
370 return IXGBE_ERR_PHY;
373 /* Read operation is complete. Get the data from MSRWD */
374 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
375 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
376 *phy_data = (u16)data;
378 return IXGBE_SUCCESS;
382 * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
383 * @hw: pointer to hardware structure
384 * @reg_addr: 32 bit PHY register to write
385 * @dev_type: always unused
386 * @phy_data: Data to write to the PHY register
388 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
389 u32 dev_type, u16 phy_data)
392 UNREFERENCED_1PARAMETER(dev_type);
394 /* Put the data in the MDI single read and write data register*/
395 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
397 /* Setup and write the write command */
398 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
399 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
400 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
401 IXGBE_MSCA_MDI_COMMAND;
403 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
405 /* Check every 10 usec to see if the access completed.
406 * The MDI Command bit will clear when the operation is
409 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
412 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
413 if (!(command & IXGBE_MSCA_MDI_COMMAND))
417 if (command & IXGBE_MSCA_MDI_COMMAND) {
418 ERROR_REPORT1(IXGBE_ERROR_POLLING,
419 "PHY write cmd didn't complete\n");
420 return IXGBE_ERR_PHY;
423 return IXGBE_SUCCESS;
427 * ixgbe_identify_phy_x550em - Get PHY type based on device id
428 * @hw: pointer to hardware structure
432 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
434 hw->mac.ops.set_lan_id(hw);
436 ixgbe_read_mng_if_sel_x550em(hw);
438 switch (hw->device_id) {
439 case IXGBE_DEV_ID_X550EM_A_SFP:
440 return ixgbe_identify_module_generic(hw);
441 case IXGBE_DEV_ID_X550EM_X_SFP:
442 /* set up for CS4227 usage */
443 ixgbe_setup_mux_ctl(hw);
444 ixgbe_check_cs4227(hw);
447 case IXGBE_DEV_ID_X550EM_A_SFP_N:
448 return ixgbe_identify_module_generic(hw);
450 case IXGBE_DEV_ID_X550EM_X_KX4:
451 hw->phy.type = ixgbe_phy_x550em_kx4;
453 case IXGBE_DEV_ID_X550EM_X_XFI:
454 hw->phy.type = ixgbe_phy_x550em_xfi;
456 case IXGBE_DEV_ID_X550EM_X_KR:
457 case IXGBE_DEV_ID_X550EM_A_KR:
458 case IXGBE_DEV_ID_X550EM_A_KR_L:
459 hw->phy.type = ixgbe_phy_x550em_kr;
461 case IXGBE_DEV_ID_X550EM_A_10G_T:
462 case IXGBE_DEV_ID_X550EM_X_1G_T:
463 case IXGBE_DEV_ID_X550EM_X_10G_T:
464 return ixgbe_identify_phy_generic(hw);
465 case IXGBE_DEV_ID_X550EM_A_1G_T:
466 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
467 hw->phy.type = ixgbe_phy_fw;
468 hw->phy.ops.read_reg = NULL;
469 hw->phy.ops.write_reg = NULL;
471 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
473 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
478 return IXGBE_SUCCESS;
482 * ixgbe_fw_phy_activity - Perform an activity on a PHY
483 * @hw: pointer to hardware structure
484 * @activity: activity to perform
485 * @data: Pointer to 4 32-bit words of data
487 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,
488 u32 (*data)[FW_PHY_ACT_DATA_COUNT])
491 struct ixgbe_hic_phy_activity_req cmd;
492 struct ixgbe_hic_phy_activity_resp rsp;
494 u16 retries = FW_PHY_ACT_RETRIES;
499 memset(&hic, 0, sizeof(hic));
500 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD;
501 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN;
502 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
503 hic.cmd.port_number = hw->bus.lan_id;
504 hic.cmd.activity_id = IXGBE_CPU_TO_LE16(activity);
505 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
506 hic.cmd.data[i] = IXGBE_CPU_TO_BE32((*data)[i]);
508 rc = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
510 IXGBE_HI_COMMAND_TIMEOUT,
512 if (rc != IXGBE_SUCCESS)
514 if (hic.rsp.hdr.cmd_or_resp.ret_status ==
515 FW_CEM_RESP_STATUS_SUCCESS) {
516 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
517 (*data)[i] = IXGBE_BE32_TO_CPU(hic.rsp.data[i]);
518 return IXGBE_SUCCESS;
522 } while (retries > 0);
524 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
527 static const struct {
529 ixgbe_link_speed phy_speed;
531 { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL },
532 { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL },
533 { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL },
534 { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL },
535 { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL },
536 { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL },
540 * ixgbe_get_phy_id_fw - Get the phy ID via firmware command
541 * @hw: pointer to hardware structure
545 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw)
547 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
553 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info);
557 hw->phy.speeds_supported = 0;
558 phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK;
559 for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
560 if (phy_speeds & ixgbe_fw_map[i].fw_speed)
561 hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed;
563 if (!hw->phy.autoneg_advertised)
564 hw->phy.autoneg_advertised = hw->phy.speeds_supported;
566 hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK;
567 phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK;
568 hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK;
569 hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK;
570 if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK)
571 return IXGBE_ERR_PHY_ADDR_INVALID;
572 return IXGBE_SUCCESS;
576 * ixgbe_identify_phy_fw - Get PHY type based on firmware command
577 * @hw: pointer to hardware structure
581 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw)
584 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
586 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
588 hw->phy.type = ixgbe_phy_fw;
589 hw->phy.ops.read_reg = NULL;
590 hw->phy.ops.write_reg = NULL;
591 return ixgbe_get_phy_id_fw(hw);
595 * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY
596 * @hw: pointer to hardware structure
600 s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw)
602 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
604 setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF;
605 return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup);
608 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
609 u32 device_type, u16 *phy_data)
611 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
612 return IXGBE_NOT_IMPLEMENTED;
615 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
616 u32 device_type, u16 phy_data)
618 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
619 return IXGBE_NOT_IMPLEMENTED;
623 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
624 * @hw: pointer to the hardware structure
625 * @addr: I2C bus address to read from
626 * @reg: I2C device register to read from
627 * @val: pointer to location to receive read value
629 * Returns an error code on error.
631 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
634 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
638 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
639 * @hw: pointer to the hardware structure
640 * @addr: I2C bus address to read from
641 * @reg: I2C device register to read from
642 * @val: pointer to location to receive read value
644 * Returns an error code on error.
647 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
650 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
654 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
655 * @hw: pointer to the hardware structure
656 * @addr: I2C bus address to write to
657 * @reg: I2C device register to write to
658 * @val: value to write
660 * Returns an error code on error.
662 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
663 u8 addr, u16 reg, u16 val)
665 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
669 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
670 * @hw: pointer to the hardware structure
671 * @addr: I2C bus address to write to
672 * @reg: I2C device register to write to
673 * @val: value to write
675 * Returns an error code on error.
678 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
679 u8 addr, u16 reg, u16 val)
681 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
685 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
686 * @hw: pointer to hardware structure
688 * Initialize the function pointers and for MAC type X550EM.
689 * Does not touch the hardware.
691 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
693 struct ixgbe_mac_info *mac = &hw->mac;
694 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
695 struct ixgbe_phy_info *phy = &hw->phy;
698 DEBUGFUNC("ixgbe_init_ops_X550EM");
700 /* Similar to X550 so start there. */
701 ret_val = ixgbe_init_ops_X550(hw);
703 /* Since this function eventually calls
704 * ixgbe_init_ops_540 by design, we are setting
705 * the pointers to NULL explicitly here to overwrite
706 * the values being set in the x540 function.
708 /* Thermal sensor not supported in x550EM */
709 mac->ops.get_thermal_sensor_data = NULL;
710 mac->ops.init_thermal_sensor_thresh = NULL;
711 mac->thermal_sensor_enabled = false;
713 /* FCOE not supported in x550EM */
714 mac->ops.get_san_mac_addr = NULL;
715 mac->ops.set_san_mac_addr = NULL;
716 mac->ops.get_wwn_prefix = NULL;
717 mac->ops.get_fcoe_boot_status = NULL;
719 /* IPsec not supported in x550EM */
720 mac->ops.disable_sec_rx_path = NULL;
721 mac->ops.enable_sec_rx_path = NULL;
723 /* AUTOC register is not present in x550EM. */
724 mac->ops.prot_autoc_read = NULL;
725 mac->ops.prot_autoc_write = NULL;
727 /* X550EM bus type is internal*/
728 hw->bus.type = ixgbe_bus_type_internal;
729 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
732 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
733 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
734 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
735 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
736 mac->ops.get_supported_physical_layer =
737 ixgbe_get_supported_physical_layer_X550em;
739 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
740 mac->ops.setup_fc = ixgbe_setup_fc_generic;
742 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
745 phy->ops.init = ixgbe_init_phy_ops_X550em;
746 switch (hw->device_id) {
747 case IXGBE_DEV_ID_X550EM_A_1G_T:
748 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
749 mac->ops.setup_fc = NULL;
750 phy->ops.identify = ixgbe_identify_phy_fw;
751 phy->ops.set_phy_power = NULL;
752 phy->ops.get_firmware_version = NULL;
755 phy->ops.identify = ixgbe_identify_phy_x550em;
758 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
759 phy->ops.set_phy_power = NULL;
763 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
764 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
765 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
766 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
767 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
768 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
769 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
770 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
776 * ixgbe_setup_fw_link - Setup firmware-controlled PHYs
777 * @hw: pointer to hardware structure
779 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw)
781 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
785 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
788 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
789 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
790 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
791 return IXGBE_ERR_INVALID_LINK_SETTINGS;
794 switch (hw->fc.requested_mode) {
796 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX <<
797 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
799 case ixgbe_fc_rx_pause:
800 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX <<
801 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
803 case ixgbe_fc_tx_pause:
804 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX <<
805 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
811 for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
812 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)
813 setup[0] |= ixgbe_fw_map[i].fw_speed;
815 setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN;
817 if (hw->phy.eee_speeds_advertised)
818 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE;
820 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup);
823 if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN)
824 return IXGBE_ERR_OVERTEMP;
825 return IXGBE_SUCCESS;
829 * ixgbe_fc_autoneg_fw _ Set up flow control for FW-controlled PHYs
830 * @hw: pointer to hardware structure
832 * Called at init time to set up flow control.
834 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw)
836 if (hw->fc.requested_mode == ixgbe_fc_default)
837 hw->fc.requested_mode = ixgbe_fc_full;
839 return ixgbe_setup_fw_link(hw);
843 * ixgbe_setup_eee_fw - Enable/disable EEE support
844 * @hw: pointer to the HW structure
845 * @enable_eee: boolean flag to enable EEE
847 * Enable/disable EEE based on enable_eee flag.
848 * This function controls EEE for firmware-based PHY implementations.
850 static s32 ixgbe_setup_eee_fw(struct ixgbe_hw *hw, bool enable_eee)
852 if (!!hw->phy.eee_speeds_advertised == enable_eee)
853 return IXGBE_SUCCESS;
855 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
857 hw->phy.eee_speeds_advertised = 0;
858 return hw->phy.ops.setup_link(hw);
862 * ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
863 * @hw: pointer to hardware structure
865 * Initialize the function pointers and for MAC type X550EM_a.
866 * Does not touch the hardware.
868 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
870 struct ixgbe_mac_info *mac = &hw->mac;
873 DEBUGFUNC("ixgbe_init_ops_X550EM_a");
875 /* Start with generic X550EM init */
876 ret_val = ixgbe_init_ops_X550EM(hw);
878 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
879 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) {
880 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
881 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
883 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
884 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
886 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
887 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
889 switch (mac->ops.get_media_type(hw)) {
890 case ixgbe_media_type_fiber:
891 mac->ops.setup_fc = NULL;
892 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
894 case ixgbe_media_type_backplane:
895 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
896 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
902 switch (hw->device_id) {
903 case IXGBE_DEV_ID_X550EM_A_1G_T:
904 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
905 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
906 mac->ops.setup_fc = ixgbe_fc_autoneg_fw;
907 mac->ops.setup_eee = ixgbe_setup_eee_fw;
908 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL |
909 IXGBE_LINK_SPEED_1GB_FULL;
910 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
920 * ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
921 * @hw: pointer to hardware structure
923 * Initialize the function pointers and for MAC type X550EM_x.
924 * Does not touch the hardware.
926 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
928 struct ixgbe_mac_info *mac = &hw->mac;
929 struct ixgbe_link_info *link = &hw->link;
932 DEBUGFUNC("ixgbe_init_ops_X550EM_x");
934 /* Start with generic X550EM init */
935 ret_val = ixgbe_init_ops_X550EM(hw);
937 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
938 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
939 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
940 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
941 link->ops.read_link = ixgbe_read_i2c_combined_generic;
942 link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
943 link->ops.write_link = ixgbe_write_i2c_combined_generic;
944 link->ops.write_link_unlocked =
945 ixgbe_write_i2c_combined_generic_unlocked;
946 link->addr = IXGBE_CS4227;
953 * ixgbe_dmac_config_X550
954 * @hw: pointer to hardware structure
956 * Configure DMA coalescing. If enabling dmac, dmac is activated.
957 * When disabling dmac, dmac enable dmac bit is cleared.
959 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
961 u32 reg, high_pri_tc;
963 DEBUGFUNC("ixgbe_dmac_config_X550");
965 /* Disable DMA coalescing before configuring */
966 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
967 reg &= ~IXGBE_DMACR_DMAC_EN;
968 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
970 /* Disable DMA Coalescing if the watchdog timer is 0 */
971 if (!hw->mac.dmac_config.watchdog_timer)
974 ixgbe_dmac_config_tcs_X550(hw);
976 /* Configure DMA Coalescing Control Register */
977 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
979 /* Set the watchdog timer in units of 40.96 usec */
980 reg &= ~IXGBE_DMACR_DMACWT_MASK;
981 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
983 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
984 /* If fcoe is enabled, set high priority traffic class */
985 if (hw->mac.dmac_config.fcoe_en) {
986 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
987 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
988 IXGBE_DMACR_HIGH_PRI_TC_MASK);
990 reg |= IXGBE_DMACR_EN_MNG_IND;
992 /* Enable DMA coalescing after configuration */
993 reg |= IXGBE_DMACR_DMAC_EN;
994 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
997 return IXGBE_SUCCESS;
1001 * ixgbe_dmac_config_tcs_X550
1002 * @hw: pointer to hardware structure
1004 * Configure DMA coalescing threshold per TC. The dmac enable bit must
1005 * be cleared before configuring.
1007 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
1009 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
1011 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
1013 /* Configure DMA coalescing enabled */
1014 switch (hw->mac.dmac_config.link_speed) {
1015 case IXGBE_LINK_SPEED_10_FULL:
1016 case IXGBE_LINK_SPEED_100_FULL:
1017 pb_headroom = IXGBE_DMACRXT_100M;
1019 case IXGBE_LINK_SPEED_1GB_FULL:
1020 pb_headroom = IXGBE_DMACRXT_1G;
1023 pb_headroom = IXGBE_DMACRXT_10G;
1027 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
1028 IXGBE_MHADD_MFS_SHIFT) / 1024);
1030 /* Set the per Rx packet buffer receive threshold */
1031 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
1032 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
1033 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
1035 if (tc < hw->mac.dmac_config.num_tcs) {
1036 /* Get Rx PB size */
1037 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
1038 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
1039 IXGBE_RXPBSIZE_SHIFT;
1041 /* Calculate receive buffer threshold in kilobytes */
1042 if (rx_pb_size > pb_headroom)
1043 rx_pb_size = rx_pb_size - pb_headroom;
1047 /* Minimum of MFS shall be set for DMCTH */
1048 reg |= (rx_pb_size > maxframe_size_kb) ?
1049 rx_pb_size : maxframe_size_kb;
1051 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
1053 return IXGBE_SUCCESS;
1057 * ixgbe_dmac_update_tcs_X550
1058 * @hw: pointer to hardware structure
1060 * Disables dmac, updates per TC settings, and then enables dmac.
1062 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
1066 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
1068 /* Disable DMA coalescing before configuring */
1069 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
1070 reg &= ~IXGBE_DMACR_DMAC_EN;
1071 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
1073 ixgbe_dmac_config_tcs_X550(hw);
1075 /* Enable DMA coalescing after configuration */
1076 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
1077 reg |= IXGBE_DMACR_DMAC_EN;
1078 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
1080 return IXGBE_SUCCESS;
1084 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
1085 * @hw: pointer to hardware structure
1087 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
1088 * ixgbe_hw struct in order to set up EEPROM access.
1090 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
1092 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1096 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
1098 if (eeprom->type == ixgbe_eeprom_uninitialized) {
1099 eeprom->semaphore_delay = 10;
1100 eeprom->type = ixgbe_flash;
1102 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1103 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1104 IXGBE_EEC_SIZE_SHIFT);
1105 eeprom->word_size = 1 << (eeprom_size +
1106 IXGBE_EEPROM_WORD_SIZE_SHIFT);
1108 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
1109 eeprom->type, eeprom->word_size);
1112 return IXGBE_SUCCESS;
1116 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1117 * @hw: pointer to hardware structure
1118 * @enable: enable or disable source address pruning
1119 * @pool: Rx pool to set source address pruning for
1121 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1126 /* max rx pool is 63 */
1130 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1131 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1134 pfflp |= (1ULL << pool);
1136 pfflp &= ~(1ULL << pool);
1138 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1139 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1143 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1144 * @hw: pointer to hardware structure
1145 * @enable: enable or disable switch for Ethertype anti-spoofing
1146 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1149 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1150 bool enable, int vf)
1152 int vf_target_reg = vf >> 3;
1153 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1156 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1158 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1160 pfvfspoof |= (1 << vf_target_shift);
1162 pfvfspoof &= ~(1 << vf_target_shift);
1164 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1168 * ixgbe_iosf_wait - Wait for IOSF command completion
1169 * @hw: pointer to hardware structure
1170 * @ctrl: pointer to location to receive final IOSF control value
1172 * Returns failing status on timeout
1174 * Note: ctrl can be NULL if the IOSF control register value is not needed
1176 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1180 /* Check every 10 usec to see if the address cycle completed.
1181 * The SB IOSF BUSY bit will clear when the operation is
1184 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1185 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1186 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1192 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1193 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1194 return IXGBE_ERR_PHY;
1197 return IXGBE_SUCCESS;
1201 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register
1202 * of the IOSF device
1203 * @hw: pointer to hardware structure
1204 * @reg_addr: 32 bit PHY register to write
1205 * @device_type: 3 bit device type
1206 * @data: Data to write to the register
1208 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1209 u32 device_type, u32 data)
1211 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1215 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1216 if (ret != IXGBE_SUCCESS)
1219 ret = ixgbe_iosf_wait(hw, NULL);
1220 if (ret != IXGBE_SUCCESS)
1223 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1224 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1226 /* Write IOSF control register */
1227 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1229 /* Write IOSF data register */
1230 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1232 ret = ixgbe_iosf_wait(hw, &command);
1234 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1235 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1236 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1237 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1238 "Failed to write, error %x\n", error);
1239 ret = IXGBE_ERR_PHY;
1243 ixgbe_release_swfw_semaphore(hw, gssr);
1248 * ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device
1249 * @hw: pointer to hardware structure
1250 * @reg_addr: 32 bit PHY register to write
1251 * @device_type: 3 bit device type
1252 * @data: Pointer to read data from the register
1254 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1255 u32 device_type, u32 *data)
1257 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1261 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1262 if (ret != IXGBE_SUCCESS)
1265 ret = ixgbe_iosf_wait(hw, NULL);
1266 if (ret != IXGBE_SUCCESS)
1269 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1270 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1272 /* Write IOSF control register */
1273 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1275 ret = ixgbe_iosf_wait(hw, &command);
1277 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1278 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1279 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1280 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1281 "Failed to read, error %x\n", error);
1282 ret = IXGBE_ERR_PHY;
1285 if (ret == IXGBE_SUCCESS)
1286 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1289 ixgbe_release_swfw_semaphore(hw, gssr);
1294 * ixgbe_get_phy_token - Get the token for shared phy access
1295 * @hw: Pointer to hardware structure
1298 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1300 struct ixgbe_hic_phy_token_req token_cmd;
1303 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1304 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1305 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1306 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1307 token_cmd.port_number = hw->bus.lan_id;
1308 token_cmd.command_type = FW_PHY_TOKEN_REQ;
1310 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1312 IXGBE_HI_COMMAND_TIMEOUT,
1315 DEBUGOUT1("Issuing host interface command failed with Status = %d\n",
1319 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1320 return IXGBE_SUCCESS;
1321 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY) {
1322 DEBUGOUT1("Host interface command returned 0x%08x , returning IXGBE_ERR_FW_RESP_INVALID\n",
1323 token_cmd.hdr.cmd_or_resp.ret_status);
1324 return IXGBE_ERR_FW_RESP_INVALID;
1327 DEBUGOUT("Returning IXGBE_ERR_TOKEN_RETRY\n");
1328 return IXGBE_ERR_TOKEN_RETRY;
1332 * ixgbe_put_phy_token - Put the token for shared phy access
1333 * @hw: Pointer to hardware structure
1336 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1338 struct ixgbe_hic_phy_token_req token_cmd;
1341 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1342 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1343 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1344 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1345 token_cmd.port_number = hw->bus.lan_id;
1346 token_cmd.command_type = FW_PHY_TOKEN_REL;
1348 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1350 IXGBE_HI_COMMAND_TIMEOUT,
1354 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1355 return IXGBE_SUCCESS;
1357 DEBUGOUT("Put PHY Token host interface command failed");
1358 return IXGBE_ERR_FW_RESP_INVALID;
1362 * ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1363 * of the IOSF device
1364 * @hw: pointer to hardware structure
1365 * @reg_addr: 32 bit PHY register to write
1366 * @device_type: 3 bit device type
1367 * @data: Data to write to the register
1369 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1370 u32 device_type, u32 data)
1372 struct ixgbe_hic_internal_phy_req write_cmd;
1374 UNREFERENCED_1PARAMETER(device_type);
1376 memset(&write_cmd, 0, sizeof(write_cmd));
1377 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1378 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1379 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1380 write_cmd.port_number = hw->bus.lan_id;
1381 write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1382 write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1383 write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1385 status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1387 IXGBE_HI_COMMAND_TIMEOUT, false);
1393 * ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device
1394 * @hw: pointer to hardware structure
1395 * @reg_addr: 32 bit PHY register to write
1396 * @device_type: 3 bit device type
1397 * @data: Pointer to read data from the register
1399 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1400 u32 device_type, u32 *data)
1403 struct ixgbe_hic_internal_phy_req cmd;
1404 struct ixgbe_hic_internal_phy_resp rsp;
1407 UNREFERENCED_1PARAMETER(device_type);
1409 memset(&hic, 0, sizeof(hic));
1410 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1411 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1412 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1413 hic.cmd.port_number = hw->bus.lan_id;
1414 hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1415 hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1417 status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1419 IXGBE_HI_COMMAND_TIMEOUT, true);
1421 /* Extract the register value from the response. */
1422 *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1428 * ixgbe_disable_mdd_X550
1429 * @hw: pointer to hardware structure
1431 * Disable malicious driver detection
1433 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1437 DEBUGFUNC("ixgbe_disable_mdd_X550");
1439 /* Disable MDD for TX DMA and interrupt */
1440 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1441 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1442 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1444 /* Disable MDD for RX and interrupt */
1445 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1446 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1447 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1451 * ixgbe_enable_mdd_X550
1452 * @hw: pointer to hardware structure
1454 * Enable malicious driver detection
1456 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1460 DEBUGFUNC("ixgbe_enable_mdd_X550");
1462 /* Enable MDD for TX DMA and interrupt */
1463 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1464 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1465 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1467 /* Enable MDD for RX and interrupt */
1468 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1469 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1470 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1474 * ixgbe_restore_mdd_vf_X550
1475 * @hw: pointer to hardware structure
1478 * Restore VF that was disabled during malicious driver detection event
1480 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1482 u32 idx, reg, num_qs, start_q, bitmask;
1484 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1486 /* Map VF to queues */
1487 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1488 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1489 case IXGBE_MRQC_VMDQRT8TCEN:
1490 num_qs = 8; /* 16 VFs / pools */
1491 bitmask = 0x000000FF;
1493 case IXGBE_MRQC_VMDQRSS32EN:
1494 case IXGBE_MRQC_VMDQRT4TCEN:
1495 num_qs = 4; /* 32 VFs / pools */
1496 bitmask = 0x0000000F;
1498 default: /* 64 VFs / pools */
1500 bitmask = 0x00000003;
1503 start_q = vf * num_qs;
1505 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1508 reg |= (bitmask << (start_q % 32));
1509 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1510 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1514 * ixgbe_mdd_event_X550
1515 * @hw: pointer to hardware structure
1516 * @vf_bitmap: vf bitmap of malicious vfs
1518 * Handle malicious driver detection event.
1520 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1523 u32 i, j, reg, q, shift, vf, idx;
1525 DEBUGFUNC("ixgbe_mdd_event_X550");
1527 /* figure out pool size for mapping to vf's */
1528 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1529 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1530 case IXGBE_MRQC_VMDQRT8TCEN:
1531 shift = 3; /* 16 VFs / pools */
1533 case IXGBE_MRQC_VMDQRSS32EN:
1534 case IXGBE_MRQC_VMDQRT4TCEN:
1535 shift = 2; /* 32 VFs / pools */
1538 shift = 1; /* 64 VFs / pools */
1542 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1543 for (i = 0; i < 4; i++) {
1544 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1545 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1550 /* Get malicious queue */
1551 for (j = 0; j < 32 && wqbr; j++) {
1553 if (!(wqbr & (1 << j)))
1556 /* Get queue from bitmask */
1559 /* Map queue to vf */
1562 /* Set vf bit in vf_bitmap */
1564 vf_bitmap[idx] |= (1 << (vf % 32));
1571 * ixgbe_get_media_type_X550em - Get media type
1572 * @hw: pointer to hardware structure
1574 * Returns the media type (fiber, copper, backplane)
1576 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1578 enum ixgbe_media_type media_type;
1580 DEBUGFUNC("ixgbe_get_media_type_X550em");
1582 /* Detect if there is a copper PHY attached. */
1583 switch (hw->device_id) {
1584 case IXGBE_DEV_ID_X550EM_X_KR:
1585 case IXGBE_DEV_ID_X550EM_X_KX4:
1586 case IXGBE_DEV_ID_X550EM_X_XFI:
1587 case IXGBE_DEV_ID_X550EM_A_KR:
1588 case IXGBE_DEV_ID_X550EM_A_KR_L:
1589 media_type = ixgbe_media_type_backplane;
1591 case IXGBE_DEV_ID_X550EM_X_SFP:
1592 case IXGBE_DEV_ID_X550EM_A_SFP:
1593 case IXGBE_DEV_ID_X550EM_A_SFP_N:
1594 case IXGBE_DEV_ID_X550EM_A_QSFP:
1595 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1596 media_type = ixgbe_media_type_fiber;
1598 case IXGBE_DEV_ID_X550EM_X_1G_T:
1599 case IXGBE_DEV_ID_X550EM_X_10G_T:
1600 case IXGBE_DEV_ID_X550EM_A_10G_T:
1601 media_type = ixgbe_media_type_copper;
1603 case IXGBE_DEV_ID_X550EM_A_SGMII:
1604 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1605 media_type = ixgbe_media_type_backplane;
1606 hw->phy.type = ixgbe_phy_sgmii;
1608 case IXGBE_DEV_ID_X550EM_A_1G_T:
1609 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1610 media_type = ixgbe_media_type_copper;
1613 media_type = ixgbe_media_type_unknown;
1620 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1621 * @hw: pointer to hardware structure
1622 * @linear: true if SFP module is linear
1624 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1626 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1628 switch (hw->phy.sfp_type) {
1629 case ixgbe_sfp_type_not_present:
1630 return IXGBE_ERR_SFP_NOT_PRESENT;
1631 case ixgbe_sfp_type_da_cu_core0:
1632 case ixgbe_sfp_type_da_cu_core1:
1635 case ixgbe_sfp_type_srlr_core0:
1636 case ixgbe_sfp_type_srlr_core1:
1637 case ixgbe_sfp_type_da_act_lmt_core0:
1638 case ixgbe_sfp_type_da_act_lmt_core1:
1639 case ixgbe_sfp_type_1g_sx_core0:
1640 case ixgbe_sfp_type_1g_sx_core1:
1641 case ixgbe_sfp_type_1g_lx_core0:
1642 case ixgbe_sfp_type_1g_lx_core1:
1645 case ixgbe_sfp_type_unknown:
1646 case ixgbe_sfp_type_1g_cu_core0:
1647 case ixgbe_sfp_type_1g_cu_core1:
1649 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1652 return IXGBE_SUCCESS;
1656 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1657 * @hw: pointer to hardware structure
1659 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1661 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1666 DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1668 status = ixgbe_identify_module_generic(hw);
1670 if (status != IXGBE_SUCCESS)
1673 /* Check if SFP module is supported */
1674 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1680 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1681 * @hw: pointer to hardware structure
1683 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1688 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1690 /* Check if SFP module is supported */
1691 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1693 if (status != IXGBE_SUCCESS)
1696 ixgbe_init_mac_link_ops_X550em(hw);
1697 hw->phy.ops.reset = NULL;
1699 return IXGBE_SUCCESS;
1703 * ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1705 * @hw: pointer to hardware structure
1707 STATIC s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1712 /* Restart auto-negotiation. */
1713 status = hw->mac.ops.read_iosf_sb_reg(hw,
1714 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1715 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1718 DEBUGOUT("Auto-negotiation did not complete\n");
1722 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1723 status = hw->mac.ops.write_iosf_sb_reg(hw,
1724 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1725 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1727 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1730 /* Indicate to FW that AN restart has been asserted */
1731 status = hw->mac.ops.read_iosf_sb_reg(hw,
1732 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1733 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1736 DEBUGOUT("Auto-negotiation did not complete\n");
1740 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1741 status = hw->mac.ops.write_iosf_sb_reg(hw,
1742 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1743 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1750 * ixgbe_setup_sgmii - Set up link for sgmii
1751 * @hw: pointer to hardware structure
1753 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1756 struct ixgbe_mac_info *mac = &hw->mac;
1757 u32 lval, sval, flx_val;
1760 rc = mac->ops.read_iosf_sb_reg(hw,
1761 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1762 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1766 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1767 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1768 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1769 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1770 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1771 rc = mac->ops.write_iosf_sb_reg(hw,
1772 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1773 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1777 rc = mac->ops.read_iosf_sb_reg(hw,
1778 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1779 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1783 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1784 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1785 rc = mac->ops.write_iosf_sb_reg(hw,
1786 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1787 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1791 rc = mac->ops.read_iosf_sb_reg(hw,
1792 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1793 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1797 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1798 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1799 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1800 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1801 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1803 rc = mac->ops.write_iosf_sb_reg(hw,
1804 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1805 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1809 rc = ixgbe_restart_an_internal_phy_x550em(hw);
1813 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1817 * ixgbe_setup_sgmii_fw - Set up link for sgmii with firmware-controlled PHYs
1818 * @hw: pointer to hardware structure
1820 STATIC s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1823 struct ixgbe_mac_info *mac = &hw->mac;
1824 u32 lval, sval, flx_val;
1827 rc = mac->ops.read_iosf_sb_reg(hw,
1828 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1829 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1833 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1834 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1835 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1836 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1837 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1838 rc = mac->ops.write_iosf_sb_reg(hw,
1839 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1840 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1844 rc = mac->ops.read_iosf_sb_reg(hw,
1845 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1846 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1850 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1851 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1852 rc = mac->ops.write_iosf_sb_reg(hw,
1853 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1854 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1858 rc = mac->ops.write_iosf_sb_reg(hw,
1859 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1860 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1864 rc = mac->ops.read_iosf_sb_reg(hw,
1865 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1866 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1870 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1871 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
1872 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1873 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1874 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1876 rc = mac->ops.write_iosf_sb_reg(hw,
1877 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1878 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1882 rc = ixgbe_restart_an_internal_phy_x550em(hw);
1884 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1888 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1889 * @hw: pointer to hardware structure
1891 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1893 struct ixgbe_mac_info *mac = &hw->mac;
1895 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1897 switch (hw->mac.ops.get_media_type(hw)) {
1898 case ixgbe_media_type_fiber:
1899 /* CS4227 does not support autoneg, so disable the laser control
1900 * functions for SFP+ fiber
1902 mac->ops.disable_tx_laser = NULL;
1903 mac->ops.enable_tx_laser = NULL;
1904 mac->ops.flap_tx_laser = NULL;
1905 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1906 mac->ops.set_rate_select_speed =
1907 ixgbe_set_soft_rate_select_speed;
1909 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1910 (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1911 mac->ops.setup_mac_link =
1912 ixgbe_setup_mac_link_sfp_x550a;
1914 mac->ops.setup_mac_link =
1915 ixgbe_setup_mac_link_sfp_x550em;
1917 case ixgbe_media_type_copper:
1918 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1919 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
1920 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
1921 mac->ops.setup_link = ixgbe_setup_sgmii_fw;
1922 mac->ops.check_link =
1923 ixgbe_check_mac_link_generic;
1925 mac->ops.setup_link =
1926 ixgbe_setup_mac_link_t_X550em;
1929 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1930 mac->ops.check_link = ixgbe_check_link_t_X550em;
1933 case ixgbe_media_type_backplane:
1934 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1935 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1936 mac->ops.setup_link = ixgbe_setup_sgmii;
1944 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1945 * @hw: pointer to hardware structure
1946 * @speed: pointer to link speed
1947 * @autoneg: true when autoneg or autotry is enabled
1949 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1950 ixgbe_link_speed *speed,
1953 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1956 if (hw->phy.type == ixgbe_phy_fw) {
1958 *speed = hw->phy.speeds_supported;
1963 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1965 /* CS4227 SFP must not enable auto-negotiation */
1968 /* Check if 1G SFP module. */
1969 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1970 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1971 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1972 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1973 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1974 return IXGBE_SUCCESS;
1977 /* Link capabilities are based on SFP */
1978 if (hw->phy.multispeed_fiber)
1979 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1980 IXGBE_LINK_SPEED_1GB_FULL;
1982 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1984 switch (hw->phy.type) {
1985 case ixgbe_phy_ext_1g_t:
1986 case ixgbe_phy_sgmii:
1987 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1989 case ixgbe_phy_x550em_kr:
1990 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1991 /* check different backplane modes */
1992 if (hw->phy.nw_mng_if_sel &
1993 IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
1994 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
1996 } else if (hw->device_id ==
1997 IXGBE_DEV_ID_X550EM_A_KR_L) {
1998 *speed = IXGBE_LINK_SPEED_1GB_FULL;
2004 *speed = IXGBE_LINK_SPEED_10GB_FULL |
2005 IXGBE_LINK_SPEED_1GB_FULL;
2011 return IXGBE_SUCCESS;
2015 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
2016 * @hw: pointer to hardware structure
2017 * @lsc: pointer to boolean flag which indicates whether external Base T
2018 * PHY interrupt is lsc
2020 * Determime if external Base T PHY interrupt cause is high temperature
2021 * failure alarm or link status change.
2023 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2024 * failure alarm, else return PHY access status.
2026 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
2033 /* Vendor alarm triggered */
2034 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2035 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2038 if (status != IXGBE_SUCCESS ||
2039 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
2042 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
2043 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
2044 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2047 if (status != IXGBE_SUCCESS ||
2048 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2049 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
2052 /* Global alarm triggered */
2053 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
2054 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2057 if (status != IXGBE_SUCCESS)
2060 /* If high temperature failure, then return over temp error and exit */
2061 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
2062 /* power down the PHY in case the PHY FW didn't already */
2063 ixgbe_set_copper_phy_power(hw, false);
2064 return IXGBE_ERR_OVERTEMP;
2065 } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
2066 /* device fault alarm triggered */
2067 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
2068 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2071 if (status != IXGBE_SUCCESS)
2074 /* if device fault was due to high temp alarm handle and exit */
2075 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
2076 /* power down the PHY in case the PHY FW didn't */
2077 ixgbe_set_copper_phy_power(hw, false);
2078 return IXGBE_ERR_OVERTEMP;
2082 /* Vendor alarm 2 triggered */
2083 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2084 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
2086 if (status != IXGBE_SUCCESS ||
2087 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
2090 /* link connect/disconnect event occurred */
2091 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
2092 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
2094 if (status != IXGBE_SUCCESS)
2098 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2101 return IXGBE_SUCCESS;
2105 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2106 * @hw: pointer to hardware structure
2108 * Enable link status change and temperature failure alarm for the external
2111 * Returns PHY access status
2113 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2119 /* Clear interrupt flags */
2120 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2122 /* Enable link status change alarm */
2124 /* Enable the LASI interrupts on X552 devices to receive notifications
2125 * of the link configurations of the external PHY and correspondingly
2126 * support the configuration of the internal iXFI link, since iXFI does
2127 * not support auto-negotiation. This is not required for X553 devices
2128 * having KR support, which performs auto-negotiations and which is used
2129 * as the internal link to the external PHY. Hence adding a check here
2130 * to avoid enabling LASI interrupts for X553 devices.
2132 if (hw->mac.type != ixgbe_mac_X550EM_a) {
2133 status = hw->phy.ops.read_reg(hw,
2134 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2135 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
2137 if (status != IXGBE_SUCCESS)
2140 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2142 status = hw->phy.ops.write_reg(hw,
2143 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2144 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
2146 if (status != IXGBE_SUCCESS)
2150 /* Enable high temperature failure and global fault alarms */
2151 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2152 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2155 if (status != IXGBE_SUCCESS)
2158 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2159 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2161 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2162 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2165 if (status != IXGBE_SUCCESS)
2168 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2169 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2170 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2173 if (status != IXGBE_SUCCESS)
2176 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2177 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2179 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2180 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2183 if (status != IXGBE_SUCCESS)
2186 /* Enable chip-wide vendor alarm */
2187 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2188 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2191 if (status != IXGBE_SUCCESS)
2194 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2196 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2197 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2204 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2205 * @hw: pointer to hardware structure
2206 * @speed: link speed
2208 * Configures the integrated KR PHY.
2210 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2211 ixgbe_link_speed speed)
2216 status = hw->mac.ops.read_iosf_sb_reg(hw,
2217 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2218 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2222 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2223 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2224 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2226 /* Advertise 10G support. */
2227 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2228 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2230 /* Advertise 1G support. */
2231 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2232 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2234 status = hw->mac.ops.write_iosf_sb_reg(hw,
2235 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2236 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2238 if (hw->mac.type == ixgbe_mac_X550EM_a) {
2239 /* Set lane mode to KR auto negotiation */
2240 status = hw->mac.ops.read_iosf_sb_reg(hw,
2241 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2242 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2247 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2248 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2249 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2250 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2251 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2253 status = hw->mac.ops.write_iosf_sb_reg(hw,
2254 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2255 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2258 return ixgbe_restart_an_internal_phy_x550em(hw);
2262 * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs
2263 * @hw: pointer to hardware structure
2265 static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw)
2267 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
2270 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2271 return IXGBE_SUCCESS;
2273 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store);
2276 memset(store, 0, sizeof(store));
2278 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store);
2282 return ixgbe_setup_fw_link(hw);
2286 * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp
2287 * @hw: pointer to hardware structure
2289 static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw)
2291 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
2294 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store);
2298 if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) {
2299 ixgbe_shutdown_fw_phy(hw);
2300 return IXGBE_ERR_OVERTEMP;
2302 return IXGBE_SUCCESS;
2306 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2307 * @hw: pointer to hardware structure
2309 * Read NW_MNG_IF_SEL register and save field values, and check for valid field
2312 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2314 /* Save NW management interface connected on board. This is used
2315 * to determine internal PHY mode.
2317 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2319 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2320 * PHY address. This register field was has only been used for X552.
2322 if (hw->mac.type == ixgbe_mac_X550EM_a &&
2323 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2324 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2325 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2326 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2329 return IXGBE_SUCCESS;
2333 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2334 * @hw: pointer to hardware structure
2336 * Initialize any function pointers that were not able to be
2337 * set during init_shared_code because the PHY/SFP type was
2338 * not known. Perform the SFP init if necessary.
2340 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2342 struct ixgbe_phy_info *phy = &hw->phy;
2345 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2347 hw->mac.ops.set_lan_id(hw);
2348 ixgbe_read_mng_if_sel_x550em(hw);
2350 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2351 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2352 ixgbe_setup_mux_ctl(hw);
2353 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2356 switch (hw->device_id) {
2357 case IXGBE_DEV_ID_X550EM_A_1G_T:
2358 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2359 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2360 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2361 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2362 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2363 phy->ops.check_overtemp = ixgbe_check_overtemp_fw;
2365 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2367 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2370 case IXGBE_DEV_ID_X550EM_A_10G_T:
2371 case IXGBE_DEV_ID_X550EM_A_SFP:
2372 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2373 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2375 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2377 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2379 case IXGBE_DEV_ID_X550EM_X_SFP:
2380 /* set up for CS4227 usage */
2381 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2383 case IXGBE_DEV_ID_X550EM_X_1G_T:
2384 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2385 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2391 /* Identify the PHY or SFP module */
2392 ret_val = phy->ops.identify(hw);
2393 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED ||
2394 ret_val == IXGBE_ERR_PHY_ADDR_INVALID)
2397 /* Setup function pointers based on detected hardware */
2398 ixgbe_init_mac_link_ops_X550em(hw);
2399 if (phy->sfp_type != ixgbe_sfp_type_unknown)
2400 phy->ops.reset = NULL;
2402 /* Set functions pointers based on phy type */
2403 switch (hw->phy.type) {
2404 case ixgbe_phy_x550em_kx4:
2405 phy->ops.setup_link = NULL;
2406 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2407 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2409 case ixgbe_phy_x550em_kr:
2410 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2411 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2412 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2414 case ixgbe_phy_ext_1g_t:
2415 /* link is managed by FW */
2416 phy->ops.setup_link = NULL;
2418 case ixgbe_phy_x550em_xfi:
2419 /* link is managed by HW */
2420 phy->ops.setup_link = NULL;
2421 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2422 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2424 case ixgbe_phy_x550em_ext_t:
2425 /* If internal link mode is XFI, then setup iXFI internal link,
2426 * else setup KR now.
2428 phy->ops.setup_internal_link =
2429 ixgbe_setup_internal_phy_t_x550em;
2431 /* setup SW LPLU only for first revision of X550EM_x */
2432 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2433 !(IXGBE_FUSES0_REV_MASK &
2434 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2435 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2437 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2438 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2440 case ixgbe_phy_sgmii:
2441 phy->ops.setup_link = NULL;
2444 phy->ops.setup_link = ixgbe_setup_fw_link;
2445 phy->ops.reset = ixgbe_reset_phy_fw;
2454 * ixgbe_set_mdio_speed - Set MDIO clock speed
2455 * @hw: pointer to hardware structure
2457 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2461 switch (hw->device_id) {
2462 case IXGBE_DEV_ID_X550EM_X_10G_T:
2463 case IXGBE_DEV_ID_X550EM_A_SGMII:
2464 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2465 case IXGBE_DEV_ID_X550EM_A_10G_T:
2466 case IXGBE_DEV_ID_X550EM_A_SFP:
2467 case IXGBE_DEV_ID_X550EM_A_QSFP:
2468 /* Config MDIO clock speed before the first MDIO PHY access */
2469 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2470 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2471 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2473 case IXGBE_DEV_ID_X550EM_A_1G_T:
2474 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2475 /* Select fast MDIO clock speed for these devices */
2476 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2477 hlreg0 |= IXGBE_HLREG0_MDCSPD;
2478 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2486 * ixgbe_reset_hw_X550em - Perform hardware reset
2487 * @hw: pointer to hardware structure
2489 * Resets the hardware by resetting the transmit and receive units, masks
2490 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2493 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2495 ixgbe_link_speed link_speed;
2499 bool link_up = false;
2501 DEBUGFUNC("ixgbe_reset_hw_X550em");
2503 /* Call adapter stop to disable Tx/Rx and clear interrupts */
2504 status = hw->mac.ops.stop_adapter(hw);
2505 if (status != IXGBE_SUCCESS) {
2506 DEBUGOUT1("Failed to stop adapter, STATUS = %d\n", status);
2509 /* flush pending Tx transactions */
2510 ixgbe_clear_tx_pending(hw);
2512 ixgbe_set_mdio_speed(hw);
2514 /* PHY ops must be identified and initialized prior to reset */
2515 status = hw->phy.ops.init(hw);
2518 DEBUGOUT1("Failed to initialize PHY ops, STATUS = %d\n",
2521 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2522 DEBUGOUT("Returning from reset HW due to PHY init failure\n");
2526 /* start the external PHY */
2527 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2528 status = ixgbe_init_ext_t_x550em(hw);
2530 DEBUGOUT1("Failed to start the external PHY, STATUS = %d\n",
2536 /* Setup SFP module if there is one present. */
2537 if (hw->phy.sfp_setup_needed) {
2538 status = hw->mac.ops.setup_sfp(hw);
2539 hw->phy.sfp_setup_needed = false;
2542 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2546 if (!hw->phy.reset_disable && hw->phy.ops.reset) {
2547 if (hw->phy.ops.reset(hw) == IXGBE_ERR_OVERTEMP)
2548 return IXGBE_ERR_OVERTEMP;
2552 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
2553 * If link reset is used when link is up, it might reset the PHY when
2554 * mng is using it. If link is down or the flag to force full link
2555 * reset is set, then perform link reset.
2557 ctrl = IXGBE_CTRL_LNK_RST;
2558 if (!hw->force_full_reset) {
2559 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2561 ctrl = IXGBE_CTRL_RST;
2564 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2565 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2566 IXGBE_WRITE_FLUSH(hw);
2568 /* Poll for reset bit to self-clear meaning reset is complete */
2569 for (i = 0; i < 10; i++) {
2571 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2572 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2576 if (ctrl & IXGBE_CTRL_RST_MASK) {
2577 status = IXGBE_ERR_RESET_FAILED;
2578 DEBUGOUT("Reset polling failed to complete.\n");
2583 /* Double resets are required for recovery from certain error
2584 * conditions. Between resets, it is necessary to stall to
2585 * allow time for any pending HW events to complete.
2587 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2588 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2592 /* Store the permanent mac address */
2593 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2595 /* Store MAC address from RAR0, clear receive address registers, and
2596 * clear the multicast table. Also reset num_rar_entries to 128,
2597 * since we modify this value when programming the SAN MAC address.
2599 hw->mac.num_rar_entries = 128;
2600 hw->mac.ops.init_rx_addrs(hw);
2602 ixgbe_set_mdio_speed(hw);
2604 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2605 ixgbe_setup_mux_ctl(hw);
2607 if (status != IXGBE_SUCCESS)
2608 DEBUGOUT1("Reset HW failed, STATUS = %d\n", status);
2614 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2615 * @hw: pointer to hardware structure
2617 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2622 status = hw->phy.ops.read_reg(hw,
2623 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2624 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2627 if (status != IXGBE_SUCCESS)
2630 /* If PHY FW reset completed bit is set then this is the first
2631 * SW instance after a power on so the PHY FW must be un-stalled.
2633 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2634 status = hw->phy.ops.read_reg(hw,
2635 IXGBE_MDIO_GLOBAL_RES_PR_10,
2636 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2639 if (status != IXGBE_SUCCESS)
2642 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2644 status = hw->phy.ops.write_reg(hw,
2645 IXGBE_MDIO_GLOBAL_RES_PR_10,
2646 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2649 if (status != IXGBE_SUCCESS)
2657 * ixgbe_setup_kr_x550em - Configure the KR PHY.
2658 * @hw: pointer to hardware structure
2660 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2662 /* leave link alone for 2.5G */
2663 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL)
2664 return IXGBE_SUCCESS;
2666 if (ixgbe_check_reset_blocked(hw))
2669 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2673 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2674 * @hw: pointer to hardware structure
2676 * Configure the external PHY and the integrated KR PHY for SFP support.
2678 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2679 ixgbe_link_speed speed,
2680 bool autoneg_wait_to_complete)
2683 u16 reg_slice, reg_val;
2684 bool setup_linear = false;
2685 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2687 /* Check if SFP module is supported and linear */
2688 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2690 /* If no SFP module present, then return success. Return success since
2691 * there is no reason to configure CS4227 and SFP not present error is
2692 * not excepted in the setup MAC link flow.
2694 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2695 return IXGBE_SUCCESS;
2697 if (ret_val != IXGBE_SUCCESS)
2700 /* Configure internal PHY for KR/KX. */
2701 ixgbe_setup_kr_speed_x550em(hw, speed);
2703 /* Configure CS4227 LINE side to proper mode. */
2704 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2705 (hw->bus.lan_id << 12);
2707 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2709 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2710 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2716 * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
2717 * @hw: pointer to hardware structure
2718 * @speed: the link speed to force
2720 * Configures the integrated PHY for native SFI mode. Used to connect the
2721 * internal PHY directly to an SFP cage, without autonegotiation.
2723 STATIC s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2725 struct ixgbe_mac_info *mac = &hw->mac;
2729 /* Disable all AN and force speed to 10G Serial. */
2730 status = mac->ops.read_iosf_sb_reg(hw,
2731 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2732 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2733 if (status != IXGBE_SUCCESS)
2736 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2737 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2738 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2739 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2741 /* Select forced link speed for internal PHY. */
2743 case IXGBE_LINK_SPEED_10GB_FULL:
2744 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
2746 case IXGBE_LINK_SPEED_1GB_FULL:
2747 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2750 /* Other link speeds are not supported by internal PHY. */
2751 return IXGBE_ERR_LINK_SETUP;
2754 status = mac->ops.write_iosf_sb_reg(hw,
2755 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2756 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2758 /* Toggle port SW reset by AN reset. */
2759 status = ixgbe_restart_an_internal_phy_x550em(hw);
2765 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2766 * @hw: pointer to hardware structure
2768 * Configure the the integrated PHY for SFP support.
2770 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2771 ixgbe_link_speed speed,
2772 bool autoneg_wait_to_complete)
2776 bool setup_linear = false;
2777 u32 reg_slice, reg_phy_int, slice_offset;
2779 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2781 /* Check if SFP module is supported and linear */
2782 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2784 /* If no SFP module present, then return success. Return success since
2785 * SFP not present error is not excepted in the setup MAC link flow.
2787 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2788 return IXGBE_SUCCESS;
2790 if (ret_val != IXGBE_SUCCESS)
2793 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2794 /* Configure internal PHY for native SFI based on module type */
2795 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2796 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2797 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int);
2799 if (ret_val != IXGBE_SUCCESS)
2802 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
2804 reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
2806 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2807 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2808 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2810 if (ret_val != IXGBE_SUCCESS)
2813 /* Setup SFI internal link. */
2814 ret_val = ixgbe_setup_sfi_x550a(hw, &speed);
2816 /* Configure internal PHY for KR/KX. */
2817 ixgbe_setup_kr_speed_x550em(hw, speed);
2819 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2821 DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2822 return IXGBE_ERR_PHY_ADDR_INVALID;
2825 /* Get external PHY SKU id */
2826 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,
2827 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
2829 if (ret_val != IXGBE_SUCCESS)
2832 /* When configuring quad port CS4223, the MAC instance is part
2833 * of the slice offset.
2835 if (reg_phy_ext == IXGBE_CS4223_SKU_ID)
2836 slice_offset = (hw->bus.lan_id +
2837 (hw->bus.instance_id << 1)) << 12;
2839 slice_offset = hw->bus.lan_id << 12;
2841 /* Configure CS4227/CS4223 LINE side to proper mode. */
2842 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2844 ret_val = hw->phy.ops.read_reg(hw, reg_slice,
2845 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
2847 if (ret_val != IXGBE_SUCCESS)
2850 reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) |
2851 (IXGBE_CS4227_EDC_MODE_SR << 1));
2854 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2856 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2857 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2858 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2860 /* Flush previous write with a read */
2861 ret_val = hw->phy.ops.read_reg(hw, reg_slice,
2862 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
2868 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2869 * @hw: pointer to hardware structure
2871 * iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2873 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2875 struct ixgbe_mac_info *mac = &hw->mac;
2879 /* Disable training protocol FSM. */
2880 status = mac->ops.read_iosf_sb_reg(hw,
2881 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2882 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2883 if (status != IXGBE_SUCCESS)
2885 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2886 status = mac->ops.write_iosf_sb_reg(hw,
2887 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2888 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2889 if (status != IXGBE_SUCCESS)
2892 /* Disable Flex from training TXFFE. */
2893 status = mac->ops.read_iosf_sb_reg(hw,
2894 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2895 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2896 if (status != IXGBE_SUCCESS)
2898 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2899 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2900 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2901 status = mac->ops.write_iosf_sb_reg(hw,
2902 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2903 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2904 if (status != IXGBE_SUCCESS)
2906 status = mac->ops.read_iosf_sb_reg(hw,
2907 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2908 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2909 if (status != IXGBE_SUCCESS)
2911 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2912 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2913 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2914 status = mac->ops.write_iosf_sb_reg(hw,
2915 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2916 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2917 if (status != IXGBE_SUCCESS)
2920 /* Enable override for coefficients. */
2921 status = mac->ops.read_iosf_sb_reg(hw,
2922 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2923 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2924 if (status != IXGBE_SUCCESS)
2926 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2927 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2928 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2929 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2930 status = mac->ops.write_iosf_sb_reg(hw,
2931 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2932 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2937 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2938 * @hw: pointer to hardware structure
2939 * @speed: the link speed to force
2941 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
2942 * internal and external PHY at a specific speed, without autonegotiation.
2944 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2946 struct ixgbe_mac_info *mac = &hw->mac;
2950 /* iXFI is only supported with X552 */
2951 if (mac->type != ixgbe_mac_X550EM_x)
2952 return IXGBE_ERR_LINK_SETUP;
2954 /* Disable AN and force speed to 10G Serial. */
2955 status = mac->ops.read_iosf_sb_reg(hw,
2956 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2957 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2958 if (status != IXGBE_SUCCESS)
2961 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2962 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2964 /* Select forced link speed for internal PHY. */
2966 case IXGBE_LINK_SPEED_10GB_FULL:
2967 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2969 case IXGBE_LINK_SPEED_1GB_FULL:
2970 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2973 /* Other link speeds are not supported by internal KR PHY. */
2974 return IXGBE_ERR_LINK_SETUP;
2977 status = mac->ops.write_iosf_sb_reg(hw,
2978 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2979 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2980 if (status != IXGBE_SUCCESS)
2983 /* Additional configuration needed for x550em_x */
2984 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2985 status = ixgbe_setup_ixfi_x550em_x(hw);
2986 if (status != IXGBE_SUCCESS)
2990 /* Toggle port SW reset by AN reset. */
2991 status = ixgbe_restart_an_internal_phy_x550em(hw);
2997 * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2998 * @hw: address of hardware structure
2999 * @link_up: address of boolean to indicate link status
3001 * Returns error code if unable to get link status.
3003 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
3010 /* read this twice back to back to indicate current status */
3011 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3012 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3014 if (ret != IXGBE_SUCCESS)
3017 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3018 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3020 if (ret != IXGBE_SUCCESS)
3023 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
3025 return IXGBE_SUCCESS;
3029 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
3030 * @hw: point to hardware structure
3032 * Configures the link between the integrated KR PHY and the external X557 PHY
3033 * The driver will call this function when it gets a link status change
3034 * interrupt from the X557 PHY. This function configures the link speed
3035 * between the PHYs to match the link speed of the BASE-T link.
3037 * A return of a non-zero value indicates an error, and the base driver should
3038 * not report link up.
3040 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
3042 ixgbe_link_speed force_speed;
3047 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3048 return IXGBE_ERR_CONFIG;
3050 if (hw->mac.type == ixgbe_mac_X550EM_x &&
3051 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3052 /* If link is down, there is no setup necessary so return */
3053 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3054 if (status != IXGBE_SUCCESS)
3058 return IXGBE_SUCCESS;
3060 status = hw->phy.ops.read_reg(hw,
3061 IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3062 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3064 if (status != IXGBE_SUCCESS)
3067 /* If link is still down - no setup is required so return */
3068 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3069 if (status != IXGBE_SUCCESS)
3072 return IXGBE_SUCCESS;
3074 /* clear everything but the speed and duplex bits */
3075 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
3078 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
3079 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3081 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
3082 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3085 /* Internal PHY does not support anything else */
3086 return IXGBE_ERR_INVALID_LINK_SETTINGS;
3089 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
3091 speed = IXGBE_LINK_SPEED_10GB_FULL |
3092 IXGBE_LINK_SPEED_1GB_FULL;
3093 return ixgbe_setup_kr_speed_x550em(hw, speed);
3098 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
3099 * @hw: pointer to hardware structure
3101 * Configures the integrated KR PHY to use internal loopback mode.
3103 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
3108 /* Disable AN and force speed to 10G Serial. */
3109 status = hw->mac.ops.read_iosf_sb_reg(hw,
3110 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3111 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3112 if (status != IXGBE_SUCCESS)
3114 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3115 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3116 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3117 status = hw->mac.ops.write_iosf_sb_reg(hw,
3118 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3119 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3120 if (status != IXGBE_SUCCESS)
3123 /* Set near-end loopback clocks. */
3124 status = hw->mac.ops.read_iosf_sb_reg(hw,
3125 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3126 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3127 if (status != IXGBE_SUCCESS)
3129 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3130 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3131 status = hw->mac.ops.write_iosf_sb_reg(hw,
3132 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3133 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3134 if (status != IXGBE_SUCCESS)
3137 /* Set loopback enable. */
3138 status = hw->mac.ops.read_iosf_sb_reg(hw,
3139 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3140 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3141 if (status != IXGBE_SUCCESS)
3143 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3144 status = hw->mac.ops.write_iosf_sb_reg(hw,
3145 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3146 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3147 if (status != IXGBE_SUCCESS)
3150 /* Training bypass. */
3151 status = hw->mac.ops.read_iosf_sb_reg(hw,
3152 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3153 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3154 if (status != IXGBE_SUCCESS)
3156 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3157 status = hw->mac.ops.write_iosf_sb_reg(hw,
3158 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3159 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3165 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3166 * assuming that the semaphore is already obtained.
3167 * @hw: pointer to hardware structure
3168 * @offset: offset of word in the EEPROM to read
3169 * @data: word read from the EEPROM
3171 * Reads a 16 bit word from the EEPROM using the hostif.
3173 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
3175 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3176 struct ixgbe_hic_read_shadow_ram buffer;
3179 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3180 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3181 buffer.hdr.req.buf_lenh = 0;
3182 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3183 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3185 /* convert offset from words to bytes */
3186 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3188 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3190 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3194 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3195 IXGBE_HI_COMMAND_TIMEOUT);
3197 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3198 FW_NVM_DATA_OFFSET);
3201 hw->mac.ops.release_swfw_sync(hw, mask);
3206 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3207 * @hw: pointer to hardware structure
3208 * @offset: offset of word in the EEPROM to read
3209 * @words: number of words
3210 * @data: word(s) read from the EEPROM
3212 * Reads a 16 bit word(s) from the EEPROM using the hostif.
3214 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3215 u16 offset, u16 words, u16 *data)
3217 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3218 struct ixgbe_hic_read_shadow_ram buffer;
3219 u32 current_word = 0;
3224 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3226 /* Take semaphore for the entire operation. */
3227 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3229 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3234 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3235 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3237 words_to_read = words;
3239 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3240 buffer.hdr.req.buf_lenh = 0;
3241 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3242 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3244 /* convert offset from words to bytes */
3245 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3246 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3248 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3249 IXGBE_HI_COMMAND_TIMEOUT);
3252 DEBUGOUT("Host interface command failed\n");
3256 for (i = 0; i < words_to_read; i++) {
3257 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3259 u32 value = IXGBE_READ_REG(hw, reg);
3261 data[current_word] = (u16)(value & 0xffff);
3264 if (i < words_to_read) {
3266 data[current_word] = (u16)(value & 0xffff);
3270 words -= words_to_read;
3274 hw->mac.ops.release_swfw_sync(hw, mask);
3279 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3280 * @hw: pointer to hardware structure
3281 * @offset: offset of word in the EEPROM to write
3282 * @data: word write to the EEPROM
3284 * Write a 16 bit word to the EEPROM using the hostif.
3286 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3290 struct ixgbe_hic_write_shadow_ram buffer;
3292 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3294 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3295 buffer.hdr.req.buf_lenh = 0;
3296 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3297 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3300 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3302 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3304 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3306 IXGBE_HI_COMMAND_TIMEOUT, false);
3312 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3313 * @hw: pointer to hardware structure
3314 * @offset: offset of word in the EEPROM to write
3315 * @data: word write to the EEPROM
3317 * Write a 16 bit word to the EEPROM using the hostif.
3319 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3322 s32 status = IXGBE_SUCCESS;
3324 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3326 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3328 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3329 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3331 DEBUGOUT("write ee hostif failed to get semaphore");
3332 status = IXGBE_ERR_SWFW_SYNC;
3339 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3340 * @hw: pointer to hardware structure
3341 * @offset: offset of word in the EEPROM to write
3342 * @words: number of words
3343 * @data: word(s) write to the EEPROM
3345 * Write a 16 bit word(s) to the EEPROM using the hostif.
3347 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3348 u16 offset, u16 words, u16 *data)
3350 s32 status = IXGBE_SUCCESS;
3353 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3355 /* Take semaphore for the entire operation. */
3356 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3357 if (status != IXGBE_SUCCESS) {
3358 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3362 for (i = 0; i < words; i++) {
3363 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3366 if (status != IXGBE_SUCCESS) {
3367 DEBUGOUT("Eeprom buffered write failed\n");
3372 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3379 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3380 * @hw: pointer to hardware structure
3381 * @ptr: pointer offset in eeprom
3382 * @size: size of section pointed by ptr, if 0 first word will be used as size
3383 * @csum: address of checksum to update
3385 * Returns error status for any failure
3387 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3388 u16 size, u16 *csum, u16 *buffer,
3393 u16 length, bufsz, i, start;
3396 bufsz = sizeof(buf) / sizeof(buf[0]);
3398 /* Read a chunk at the pointer location */
3400 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3402 DEBUGOUT("Failed to read EEPROM image\n");
3407 if (buffer_size < ptr)
3408 return IXGBE_ERR_PARAM;
3409 local_buffer = &buffer[ptr];
3417 length = local_buffer[0];
3419 /* Skip pointer section if length is invalid. */
3420 if (length == 0xFFFF || length == 0 ||
3421 (ptr + length) >= hw->eeprom.word_size)
3422 return IXGBE_SUCCESS;
3425 if (buffer && ((u32)start + (u32)length > buffer_size))
3426 return IXGBE_ERR_PARAM;
3428 for (i = start; length; i++, length--) {
3429 if (i == bufsz && !buffer) {
3435 /* Read a chunk at the pointer location */
3436 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3439 DEBUGOUT("Failed to read EEPROM image\n");
3443 *csum += local_buffer[i];
3445 return IXGBE_SUCCESS;
3449 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3450 * @hw: pointer to hardware structure
3451 * @buffer: pointer to buffer containing calculated checksum
3452 * @buffer_size: size of buffer
3454 * Returns a negative error code on error, or the 16-bit checksum
3456 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3458 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3462 u16 pointer, i, size;
3464 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3466 hw->eeprom.ops.init_params(hw);
3469 /* Read pointer area */
3470 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3471 IXGBE_EEPROM_LAST_WORD + 1,
3474 DEBUGOUT("Failed to read EEPROM image\n");
3477 local_buffer = eeprom_ptrs;
3479 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3480 return IXGBE_ERR_PARAM;
3481 local_buffer = buffer;
3485 * For X550 hardware include 0x0-0x41 in the checksum, skip the
3486 * checksum word itself
3488 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3489 if (i != IXGBE_EEPROM_CHECKSUM)
3490 checksum += local_buffer[i];
3493 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
3494 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3496 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3497 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3500 pointer = local_buffer[i];
3502 /* Skip pointer section if the pointer is invalid. */
3503 if (pointer == 0xFFFF || pointer == 0 ||
3504 pointer >= hw->eeprom.word_size)
3508 case IXGBE_PCIE_GENERAL_PTR:
3509 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3511 case IXGBE_PCIE_CONFIG0_PTR:
3512 case IXGBE_PCIE_CONFIG1_PTR:
3513 size = IXGBE_PCIE_CONFIG_SIZE;
3520 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3521 buffer, buffer_size);
3526 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3528 return (s32)checksum;
3532 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3533 * @hw: pointer to hardware structure
3535 * Returns a negative error code on error, or the 16-bit checksum
3537 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3539 return ixgbe_calc_checksum_X550(hw, NULL, 0);
3543 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3544 * @hw: pointer to hardware structure
3545 * @checksum_val: calculated checksum
3547 * Performs checksum calculation and validates the EEPROM checksum. If the
3548 * caller does not need checksum_val, the value can be NULL.
3550 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3554 u16 read_checksum = 0;
3556 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3558 /* Read the first word from the EEPROM. If this times out or fails, do
3559 * not continue or we could be in for a very long wait while every
3562 status = hw->eeprom.ops.read(hw, 0, &checksum);
3564 DEBUGOUT("EEPROM read failed\n");
3568 status = hw->eeprom.ops.calc_checksum(hw);
3572 checksum = (u16)(status & 0xffff);
3574 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3579 /* Verify read checksum from EEPROM is the same as
3580 * calculated checksum
3582 if (read_checksum != checksum) {
3583 status = IXGBE_ERR_EEPROM_CHECKSUM;
3584 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3585 "Invalid EEPROM checksum");
3588 /* If the user cares, return the calculated checksum */
3590 *checksum_val = checksum;
3596 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3597 * @hw: pointer to hardware structure
3599 * After writing EEPROM to shadow RAM using EEWR register, software calculates
3600 * checksum and updates the EEPROM and instructs the hardware to update
3603 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3608 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3610 /* Read the first word from the EEPROM. If this times out or fails, do
3611 * not continue or we could be in for a very long wait while every
3614 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3616 DEBUGOUT("EEPROM read failed\n");
3620 status = ixgbe_calc_eeprom_checksum_X550(hw);
3624 checksum = (u16)(status & 0xffff);
3626 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3631 status = ixgbe_update_flash_X550(hw);
3637 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3638 * @hw: pointer to hardware structure
3640 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3642 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3644 s32 status = IXGBE_SUCCESS;
3645 union ixgbe_hic_hdr2 buffer;
3647 DEBUGFUNC("ixgbe_update_flash_X550");
3649 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3650 buffer.req.buf_lenh = 0;
3651 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3652 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3654 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3656 IXGBE_HI_COMMAND_TIMEOUT, false);
3662 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3663 * @hw: pointer to hardware structure
3665 * Determines physical layer capabilities of the current configuration.
3667 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3669 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3670 u16 ext_ability = 0;
3672 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3674 hw->phy.ops.identify(hw);
3676 switch (hw->phy.type) {
3677 case ixgbe_phy_x550em_kr:
3678 case ixgbe_phy_x550em_xfi:
3679 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3680 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3682 case ixgbe_phy_x550em_kx4:
3683 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3684 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3686 case ixgbe_phy_x550em_ext_t:
3687 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3688 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3690 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3691 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3692 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3693 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3696 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_1GB_FULL)
3697 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3698 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_100_FULL)
3699 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
3700 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_10_FULL)
3701 physical_layer |= IXGBE_PHYSICAL_LAYER_10BASE_T;
3703 case ixgbe_phy_sgmii:
3704 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3706 case ixgbe_phy_ext_1g_t:
3707 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3713 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3714 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3716 return physical_layer;
3720 * ixgbe_get_bus_info_x550em - Set PCI bus info
3721 * @hw: pointer to hardware structure
3723 * Sets bus link width and speed to unknown because X550em is
3726 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3729 DEBUGFUNC("ixgbe_get_bus_info_x550em");
3731 hw->bus.width = ixgbe_bus_width_unknown;
3732 hw->bus.speed = ixgbe_bus_speed_unknown;
3734 hw->mac.ops.set_lan_id(hw);
3736 return IXGBE_SUCCESS;
3740 * ixgbe_disable_rx_x550 - Disable RX unit
3742 * Enables the Rx DMA unit for x550
3744 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3746 u32 rxctrl, pfdtxgswc;
3748 struct ixgbe_hic_disable_rxen fw_cmd;
3750 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3752 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3753 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3754 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3755 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3756 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3757 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3758 hw->mac.set_lben = true;
3760 hw->mac.set_lben = false;
3763 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3764 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3765 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3766 fw_cmd.port_number = (u8)hw->bus.lan_id;
3768 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3769 sizeof(struct ixgbe_hic_disable_rxen),
3770 IXGBE_HI_COMMAND_TIMEOUT, true);
3772 /* If we fail - disable RX using register write */
3774 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3775 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3776 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3777 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3784 * ixgbe_enter_lplu_x550em - Transition to low power states
3785 * @hw: pointer to hardware structure
3787 * Configures Low Power Link Up on transition to low power states
3788 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3789 * X557 PHY immediately prior to entering LPLU.
3791 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3793 u16 an_10g_cntl_reg, autoneg_reg, speed;
3795 ixgbe_link_speed lcd_speed;
3799 /* SW LPLU not required on later HW revisions. */
3800 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3801 (IXGBE_FUSES0_REV_MASK &
3802 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3803 return IXGBE_SUCCESS;
3805 /* If blocked by MNG FW, then don't restart AN */
3806 if (ixgbe_check_reset_blocked(hw))
3807 return IXGBE_SUCCESS;
3809 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3810 if (status != IXGBE_SUCCESS)
3813 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3815 if (status != IXGBE_SUCCESS)
3818 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3819 * disabled, then force link down by entering low power mode.
3821 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3822 !(hw->wol_enabled || ixgbe_mng_present(hw)))
3823 return ixgbe_set_copper_phy_power(hw, FALSE);
3826 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3828 if (status != IXGBE_SUCCESS)
3831 /* If no valid LCD link speed, then force link down and exit. */
3832 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3833 return ixgbe_set_copper_phy_power(hw, FALSE);
3835 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3836 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3839 if (status != IXGBE_SUCCESS)
3842 /* If no link now, speed is invalid so take link down */
3843 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3844 if (status != IXGBE_SUCCESS)
3845 return ixgbe_set_copper_phy_power(hw, false);
3847 /* clear everything but the speed bits */
3848 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3850 /* If current speed is already LCD, then exit. */
3851 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3852 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3853 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3854 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3857 /* Clear AN completed indication */
3858 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3859 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3862 if (status != IXGBE_SUCCESS)
3865 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3866 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3869 if (status != IXGBE_SUCCESS)
3872 status = hw->phy.ops.read_reg(hw,
3873 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3874 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3877 if (status != IXGBE_SUCCESS)
3880 save_autoneg = hw->phy.autoneg_advertised;
3882 /* Setup link at least common link speed */
3883 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3885 /* restore autoneg from before setting lplu speed */
3886 hw->phy.autoneg_advertised = save_autoneg;
3892 * ixgbe_get_lcd_x550em - Determine lowest common denominator
3893 * @hw: pointer to hardware structure
3894 * @lcd_speed: pointer to lowest common link speed
3896 * Determine lowest common link speed with link partner.
3898 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3902 u16 word = hw->eeprom.ctrl_word_3;
3904 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3906 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3907 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3910 if (status != IXGBE_SUCCESS)
3913 /* If link partner advertised 1G, return 1G */
3914 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3915 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3919 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3920 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3921 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3924 /* Link partner not capable of lower speeds, return 10G */
3925 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3930 * ixgbe_setup_fc_X550em - Set up flow control
3931 * @hw: pointer to hardware structure
3933 * Called at init time to set up flow control.
3935 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3937 s32 ret_val = IXGBE_SUCCESS;
3938 u32 pause, asm_dir, reg_val;
3940 DEBUGFUNC("ixgbe_setup_fc_X550em");
3942 /* Validate the requested mode */
3943 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3944 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3945 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3946 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3950 /* 10gig parts do not have a word in the EEPROM to determine the
3951 * default flow control setting, so we explicitly set it to full.
3953 if (hw->fc.requested_mode == ixgbe_fc_default)
3954 hw->fc.requested_mode = ixgbe_fc_full;
3956 /* Determine PAUSE and ASM_DIR bits. */
3957 switch (hw->fc.requested_mode) {
3962 case ixgbe_fc_tx_pause:
3966 case ixgbe_fc_rx_pause:
3967 /* Rx Flow control is enabled and Tx Flow control is
3968 * disabled by software override. Since there really
3969 * isn't a way to advertise that we are capable of RX
3970 * Pause ONLY, we will advertise that we support both
3971 * symmetric and asymmetric Rx PAUSE, as such we fall
3972 * through to the fc_full statement. Later, we will
3973 * disable the adapter's ability to send PAUSE frames.
3980 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3981 "Flow control param set incorrectly\n");
3982 ret_val = IXGBE_ERR_CONFIG;
3986 switch (hw->device_id) {
3987 case IXGBE_DEV_ID_X550EM_X_KR:
3988 case IXGBE_DEV_ID_X550EM_A_KR:
3989 case IXGBE_DEV_ID_X550EM_A_KR_L:
3990 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
3991 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3992 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3993 if (ret_val != IXGBE_SUCCESS)
3995 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3996 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3998 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4000 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4001 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
4002 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4003 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
4005 /* This device does not fully support AN. */
4006 hw->fc.disable_fc_autoneg = true;
4008 case IXGBE_DEV_ID_X550EM_X_XFI:
4009 hw->fc.disable_fc_autoneg = true;
4020 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
4021 * @hw: pointer to hardware structure
4023 * Enable flow control according to IEEE clause 37.
4025 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
4027 u32 link_s1, lp_an_page_low, an_cntl_1;
4028 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4029 ixgbe_link_speed speed;
4032 /* AN should have completed when the cable was plugged in.
4033 * Look for reasons to bail out. Bail out if:
4034 * - FC autoneg is disabled, or if
4037 if (hw->fc.disable_fc_autoneg) {
4038 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4039 "Flow control autoneg is disabled");
4043 hw->mac.ops.check_link(hw, &speed, &link_up, false);
4045 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4049 /* Check at auto-negotiation has completed */
4050 status = hw->mac.ops.read_iosf_sb_reg(hw,
4051 IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4052 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4054 if (status != IXGBE_SUCCESS ||
4055 (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4056 DEBUGOUT("Auto-Negotiation did not complete\n");
4057 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4061 /* Read the 10g AN autoc and LP ability registers and resolve
4062 * local flow control settings accordingly
4064 status = hw->mac.ops.read_iosf_sb_reg(hw,
4065 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4066 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
4068 if (status != IXGBE_SUCCESS) {
4069 DEBUGOUT("Auto-Negotiation did not complete\n");
4073 status = hw->mac.ops.read_iosf_sb_reg(hw,
4074 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
4075 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
4077 if (status != IXGBE_SUCCESS) {
4078 DEBUGOUT("Auto-Negotiation did not complete\n");
4082 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
4083 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
4084 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
4085 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
4086 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
4089 if (status == IXGBE_SUCCESS) {
4090 hw->fc.fc_was_autonegged = true;
4092 hw->fc.fc_was_autonegged = false;
4093 hw->fc.current_mode = hw->fc.requested_mode;
4098 * ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
4099 * @hw: pointer to hardware structure
4102 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
4104 hw->fc.fc_was_autonegged = false;
4105 hw->fc.current_mode = hw->fc.requested_mode;
4109 * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
4110 * @hw: pointer to hardware structure
4112 * Enable flow control according to IEEE clause 37.
4114 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
4116 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4117 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
4118 ixgbe_link_speed speed;
4121 /* AN should have completed when the cable was plugged in.
4122 * Look for reasons to bail out. Bail out if:
4123 * - FC autoneg is disabled, or if
4126 if (hw->fc.disable_fc_autoneg) {
4127 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4128 "Flow control autoneg is disabled");
4132 hw->mac.ops.check_link(hw, &speed, &link_up, false);
4134 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4138 /* Check if auto-negotiation has completed */
4139 status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info);
4140 if (status != IXGBE_SUCCESS ||
4141 !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) {
4142 DEBUGOUT("Auto-Negotiation did not complete\n");
4143 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4147 /* Negotiate the flow control */
4148 status = ixgbe_negotiate_fc(hw, info[0], info[0],
4149 FW_PHY_ACT_GET_LINK_INFO_FC_RX,
4150 FW_PHY_ACT_GET_LINK_INFO_FC_TX,
4151 FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX,
4152 FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX);
4155 if (status == IXGBE_SUCCESS) {
4156 hw->fc.fc_was_autonegged = true;
4158 hw->fc.fc_was_autonegged = false;
4159 hw->fc.current_mode = hw->fc.requested_mode;
4164 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4165 * @hw: pointer to hardware structure
4167 * Called at init time to set up flow control.
4169 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4171 s32 status = IXGBE_SUCCESS;
4174 DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4176 /* Validate the requested mode */
4177 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4178 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4179 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4180 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4183 if (hw->fc.requested_mode == ixgbe_fc_default)
4184 hw->fc.requested_mode = ixgbe_fc_full;
4186 /* Set up the 1G and 10G flow control advertisement registers so the
4187 * HW will be able to do FC autoneg once the cable is plugged in. If
4188 * we link at 10G, the 1G advertisement is harmless and vice versa.
4190 status = hw->mac.ops.read_iosf_sb_reg(hw,
4191 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4192 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4194 if (status != IXGBE_SUCCESS) {
4195 DEBUGOUT("Auto-Negotiation did not complete\n");
4199 /* The possible values of fc.requested_mode are:
4200 * 0: Flow control is completely disabled
4201 * 1: Rx flow control is enabled (we can receive pause frames,
4202 * but not send pause frames).
4203 * 2: Tx flow control is enabled (we can send pause frames but
4204 * we do not support receiving pause frames).
4205 * 3: Both Rx and Tx flow control (symmetric) are enabled.
4208 switch (hw->fc.requested_mode) {
4210 /* Flow control completely disabled by software override. */
4211 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4212 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4214 case ixgbe_fc_tx_pause:
4215 /* Tx Flow control is enabled, and Rx Flow control is
4216 * disabled by software override.
4218 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4219 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4221 case ixgbe_fc_rx_pause:
4222 /* Rx Flow control is enabled and Tx Flow control is
4223 * disabled by software override. Since there really
4224 * isn't a way to advertise that we are capable of RX
4225 * Pause ONLY, we will advertise that we support both
4226 * symmetric and asymmetric Rx PAUSE, as such we fall
4227 * through to the fc_full statement. Later, we will
4228 * disable the adapter's ability to send PAUSE frames.
4231 /* Flow control (both Rx and Tx) is enabled by SW override. */
4232 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4233 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4236 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4237 "Flow control param set incorrectly\n");
4238 return IXGBE_ERR_CONFIG;
4241 status = hw->mac.ops.write_iosf_sb_reg(hw,
4242 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4243 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4245 /* Restart auto-negotiation. */
4246 status = ixgbe_restart_an_internal_phy_x550em(hw);
4252 * ixgbe_set_mux - Set mux for port 1 access with CS4227
4253 * @hw: pointer to hardware structure
4254 * @state: set mux if 1, clear if 0
4256 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4260 if (!hw->bus.lan_id)
4262 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4264 esdp |= IXGBE_ESDP_SDP1;
4266 esdp &= ~IXGBE_ESDP_SDP1;
4267 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4268 IXGBE_WRITE_FLUSH(hw);
4272 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4273 * @hw: pointer to hardware structure
4274 * @mask: Mask to specify which semaphore to acquire
4276 * Acquires the SWFW semaphore and sets the I2C MUX
4278 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4282 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4284 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4288 if (mask & IXGBE_GSSR_I2C_MASK)
4289 ixgbe_set_mux(hw, 1);
4291 return IXGBE_SUCCESS;
4295 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4296 * @hw: pointer to hardware structure
4297 * @mask: Mask to specify which semaphore to release
4299 * Releases the SWFW semaphore and sets the I2C MUX
4301 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4303 DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4305 if (mask & IXGBE_GSSR_I2C_MASK)
4306 ixgbe_set_mux(hw, 0);
4308 ixgbe_release_swfw_sync_X540(hw, mask);
4312 * ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4313 * @hw: pointer to hardware structure
4314 * @mask: Mask to specify which semaphore to acquire
4316 * Acquires the SWFW semaphore and get the shared phy token as needed
4318 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4320 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4321 int retries = FW_PHY_TOKEN_RETRIES;
4322 s32 status = IXGBE_SUCCESS;
4324 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4327 status = IXGBE_SUCCESS;
4329 status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4331 DEBUGOUT1("Could not acquire SWFW semaphore, Status = %d\n",
4335 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4336 return IXGBE_SUCCESS;
4338 status = ixgbe_get_phy_token(hw);
4339 if (status == IXGBE_ERR_TOKEN_RETRY)
4340 DEBUGOUT1("Could not acquire PHY token, Status = %d\n",
4343 if (status == IXGBE_SUCCESS)
4344 return IXGBE_SUCCESS;
4347 ixgbe_release_swfw_sync_X540(hw, hmask);
4349 if (status != IXGBE_ERR_TOKEN_RETRY) {
4350 DEBUGOUT1("Unable to retry acquiring the PHY token, Status = %d\n",
4356 DEBUGOUT1("Semaphore acquisition retries failed!: PHY ID = 0x%08X\n",
4362 * ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4363 * @hw: pointer to hardware structure
4364 * @mask: Mask to specify which semaphore to release
4366 * Releases the SWFW semaphore and puts the shared phy token as needed
4368 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4370 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4372 DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4374 if (mask & IXGBE_GSSR_TOKEN_SM)
4375 ixgbe_put_phy_token(hw);
4378 ixgbe_release_swfw_sync_X540(hw, hmask);
4382 * ixgbe_read_phy_reg_x550a - Reads specified PHY register
4383 * @hw: pointer to hardware structure
4384 * @reg_addr: 32 bit address of PHY register to read
4385 * @phy_data: Pointer to read data from PHY register
4387 * Reads a value from a specified PHY register using the SWFW lock and PHY
4388 * Token. The PHY Token is needed since the MDIO is shared between to MAC
4391 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4392 u32 device_type, u16 *phy_data)
4395 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4397 DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4399 if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4400 return IXGBE_ERR_SWFW_SYNC;
4402 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4404 hw->mac.ops.release_swfw_sync(hw, mask);
4410 * ixgbe_write_phy_reg_x550a - Writes specified PHY register
4411 * @hw: pointer to hardware structure
4412 * @reg_addr: 32 bit PHY register to write
4413 * @device_type: 5 bit device type
4414 * @phy_data: Data to write to the PHY register
4416 * Writes a value to specified PHY register using the SWFW lock and PHY Token.
4417 * The PHY Token is needed since the MDIO is shared between to MAC instances.
4419 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4420 u32 device_type, u16 phy_data)
4423 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4425 DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4427 if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4428 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
4430 hw->mac.ops.release_swfw_sync(hw, mask);
4432 status = IXGBE_ERR_SWFW_SYNC;
4439 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4440 * @hw: pointer to hardware structure
4442 * Handle external Base T PHY interrupt. If high temperature
4443 * failure alarm then return error, else if link status change
4444 * then setup internal/external PHY link
4446 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4447 * failure alarm, else return PHY access status.
4449 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4454 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4456 if (status != IXGBE_SUCCESS)
4460 return ixgbe_setup_internal_phy(hw);
4462 return IXGBE_SUCCESS;
4466 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4467 * @hw: pointer to hardware structure
4468 * @speed: new link speed
4469 * @autoneg_wait_to_complete: true when waiting for completion is needed
4471 * Setup internal/external PHY link speed based on link speed, then set
4472 * external PHY auto advertised link speed.
4474 * Returns error status for any failure
4476 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4477 ixgbe_link_speed speed,
4478 bool autoneg_wait_to_complete)
4481 ixgbe_link_speed force_speed;
4483 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4485 /* Setup internal/external PHY link speed to iXFI (10G), unless
4486 * only 1G is auto advertised then setup KX link.
4488 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4489 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4491 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4493 /* If X552 and internal link mode is XFI, then setup XFI internal link.
4495 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4496 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4497 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4499 if (status != IXGBE_SUCCESS)
4503 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4507 * ixgbe_check_link_t_X550em - Determine link and speed status
4508 * @hw: pointer to hardware structure
4509 * @speed: pointer to link speed
4510 * @link_up: true when link is up
4511 * @link_up_wait_to_complete: bool used to wait for link up or not
4513 * Check that both the MAC and X557 external PHY have link.
4515 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4516 bool *link_up, bool link_up_wait_to_complete)
4519 u16 i, autoneg_status = 0;
4521 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4522 return IXGBE_ERR_CONFIG;
4524 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4525 link_up_wait_to_complete);
4527 /* If check link fails or MAC link is not up, then return */
4528 if (status != IXGBE_SUCCESS || !(*link_up))
4531 /* MAC link is up, so check external PHY link.
4532 * X557 PHY. Link status is latching low, and can only be used to detect
4533 * link drop, and not the current status of the link without performing
4534 * back-to-back reads.
4536 for (i = 0; i < 2; i++) {
4537 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4538 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4541 if (status != IXGBE_SUCCESS)
4545 /* If external PHY link is not up, then indicate link not up */
4546 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4549 return IXGBE_SUCCESS;
4553 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4554 * @hw: pointer to hardware structure
4556 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4560 status = ixgbe_reset_phy_generic(hw);
4562 if (status != IXGBE_SUCCESS)
4565 /* Configure Link Status Alarm and Temperature Threshold interrupts */
4566 return ixgbe_enable_lasi_ext_t_x550em(hw);
4570 * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4571 * @hw: pointer to hardware structure
4572 * @led_idx: led number to turn on
4574 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4578 DEBUGFUNC("ixgbe_led_on_t_X550em");
4580 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4581 return IXGBE_ERR_PARAM;
4583 /* To turn on the LED, set mode to ON. */
4584 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4585 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4586 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4587 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4588 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4590 return IXGBE_SUCCESS;
4594 * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4595 * @hw: pointer to hardware structure
4596 * @led_idx: led number to turn off
4598 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4602 DEBUGFUNC("ixgbe_led_off_t_X550em");
4604 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4605 return IXGBE_ERR_PARAM;
4607 /* To turn on the LED, set mode to ON. */
4608 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4609 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4610 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4611 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4612 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4614 return IXGBE_SUCCESS;
4618 * ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware
4619 * @hw: pointer to the HW structure
4620 * @maj: driver version major number
4621 * @min: driver version minor number
4622 * @build: driver version build number
4623 * @sub: driver version sub build number
4624 * @len: length of driver_ver string
4625 * @driver_ver: driver string
4627 * Sends driver version number to firmware through the manageability
4628 * block. On success return IXGBE_SUCCESS
4629 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4630 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4632 s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,
4633 u8 build, u8 sub, u16 len, const char *driver_ver)
4635 struct ixgbe_hic_drv_info2 fw_cmd;
4636 s32 ret_val = IXGBE_SUCCESS;
4639 DEBUGFUNC("ixgbe_set_fw_drv_ver_x550");
4641 if ((len == 0) || (driver_ver == NULL) ||
4642 (len > sizeof(fw_cmd.driver_string)))
4643 return IXGBE_ERR_INVALID_ARGUMENT;
4645 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4646 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len;
4647 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4648 fw_cmd.port_num = (u8)hw->bus.func;
4649 fw_cmd.ver_maj = maj;
4650 fw_cmd.ver_min = min;
4651 fw_cmd.ver_build = build;
4652 fw_cmd.ver_sub = sub;
4653 fw_cmd.hdr.checksum = 0;
4654 memcpy(fw_cmd.driver_string, driver_ver, len);
4655 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4656 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4658 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4659 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4661 IXGBE_HI_COMMAND_TIMEOUT,
4663 if (ret_val != IXGBE_SUCCESS)
4666 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4667 FW_CEM_RESP_STATUS_SUCCESS)
4668 ret_val = IXGBE_SUCCESS;
4670 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;