1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
44 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
45 * @hw: pointer to hardware structure
47 * Initialize the function pointers and assign the MAC type for X550.
48 * Does not touch the hardware.
50 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
52 struct ixgbe_mac_info *mac = &hw->mac;
53 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
56 DEBUGFUNC("ixgbe_init_ops_X550");
58 ret_val = ixgbe_init_ops_X540(hw);
59 mac->ops.dmac_config = ixgbe_dmac_config_X550;
60 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
61 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
62 mac->ops.setup_eee = ixgbe_setup_eee_X550;
63 mac->ops.set_source_address_pruning =
64 ixgbe_set_source_address_pruning_X550;
65 mac->ops.set_ethertype_anti_spoofing =
66 ixgbe_set_ethertype_anti_spoofing_X550;
68 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
69 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
70 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
71 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
72 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
73 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
74 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
75 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
76 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
78 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
79 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
80 mac->ops.mdd_event = ixgbe_mdd_event_X550;
81 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
82 mac->ops.disable_rx = ixgbe_disable_rx_x550;
83 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
84 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
85 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
91 * ixgbe_read_cs4227 - Read CS4227 register
92 * @hw: pointer to hardware structure
93 * @reg: register number to write
94 * @value: pointer to receive value read
98 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
100 return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
104 * ixgbe_write_cs4227 - Write CS4227 register
105 * @hw: pointer to hardware structure
106 * @reg: register number to write
107 * @value: value to write to register
109 * Returns status code
111 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
113 return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
117 * ixgbe_get_cs4227_status - Return CS4227 status
118 * @hw: pointer to hardware structure
120 * Performs a diagnostic on the CS4227 chip. Returns an error if it is
121 * not operating correctly.
122 * This function assumes that the caller has acquired the proper semaphore.
124 STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
128 u16 reg_slice, reg_val;
131 /* Check register reads. */
132 for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) {
133 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB,
135 if (status != IXGBE_SUCCESS)
137 if (value == IXGBE_CS4227_GLOBAL_ID_VALUE)
139 msec_delay(IXGBE_CS4227_CHECK_DELAY);
141 if (value != IXGBE_CS4227_GLOBAL_ID_VALUE)
142 return IXGBE_ERR_PHY;
144 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
145 if (status != IXGBE_SUCCESS)
148 /* If this is the first time after power-on, check the ucode.
149 * Otherwise, this will disrupt link on all ports. Because we
150 * can only do this the first time, we must check all ports,
152 * While we are at it, set the LINE side to 10G SR, which is
153 * what it needs to be regardless of the actual link.
155 if (value != IXGBE_CS4227_SCRATCH_VALUE) {
156 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB;
157 reg_val = IXGBE_CS4227_SPEED_10G;
158 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
159 if (status != IXGBE_SUCCESS)
162 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB;
163 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
164 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
165 if (status != IXGBE_SUCCESS)
168 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB;
169 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
170 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
171 if (status != IXGBE_SUCCESS)
174 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB + (1 << 12);
175 reg_val = IXGBE_CS4227_SPEED_10G;
176 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
177 if (status != IXGBE_SUCCESS)
180 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (1 << 12);
181 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
182 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
183 if (status != IXGBE_SUCCESS)
186 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (1 << 12);
187 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
188 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
189 if (status != IXGBE_SUCCESS)
195 /* Verify that the ucode is operational on all ports. */
196 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB;
198 status = ixgbe_read_cs4227(hw, reg_slice, ®_val);
199 if (status != IXGBE_SUCCESS)
202 return IXGBE_ERR_PHY;
204 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB;
206 status = ixgbe_read_cs4227(hw, reg_slice, ®_val);
207 if (status != IXGBE_SUCCESS)
210 return IXGBE_ERR_PHY;
212 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (1 << 12);
214 status = ixgbe_read_cs4227(hw, reg_slice, ®_val);
215 if (status != IXGBE_SUCCESS)
218 return IXGBE_ERR_PHY;
220 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (1 << 12);
222 status = ixgbe_read_cs4227(hw, reg_slice, ®_val);
223 if (status != IXGBE_SUCCESS)
226 return IXGBE_ERR_PHY;
228 /* Set scratch indicating that the diagnostic was successful. */
229 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
230 IXGBE_CS4227_SCRATCH_VALUE);
231 if (status != IXGBE_SUCCESS)
233 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
234 if (status != IXGBE_SUCCESS)
236 if (value != IXGBE_CS4227_SCRATCH_VALUE)
237 return IXGBE_ERR_PHY;
239 return IXGBE_SUCCESS;
243 * ixgbe_read_pe - Read register from port expander
244 * @hw: pointer to hardware structure
245 * @reg: register number to read
246 * @value: pointer to receive read value
248 * Returns status code
250 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
254 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
255 if (status != IXGBE_SUCCESS)
256 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
257 "port expander access failed with %d\n", status);
262 * ixgbe_write_pe - Write register to port expander
263 * @hw: pointer to hardware structure
264 * @reg: register number to write
265 * @value: value to write
267 * Returns status code
269 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
273 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
274 if (status != IXGBE_SUCCESS)
275 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
276 "port expander access failed with %d\n", status);
281 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
282 * @hw: pointer to hardware structure
286 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
291 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
292 if (status != IXGBE_SUCCESS)
294 reg |= IXGBE_PE_BIT1;
295 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
296 if (status != IXGBE_SUCCESS)
299 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
300 if (status != IXGBE_SUCCESS)
302 reg &= ~IXGBE_PE_BIT1;
303 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
304 if (status != IXGBE_SUCCESS)
307 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
308 if (status != IXGBE_SUCCESS)
310 reg &= ~IXGBE_PE_BIT1;
311 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
312 if (status != IXGBE_SUCCESS)
315 usec_delay(IXGBE_CS4227_RESET_HOLD);
317 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
318 if (status != IXGBE_SUCCESS)
320 reg |= IXGBE_PE_BIT1;
321 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
322 if (status != IXGBE_SUCCESS)
325 msec_delay(IXGBE_CS4227_RESET_DELAY);
327 return IXGBE_SUCCESS;
331 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
332 * @hw: pointer to hardware structure
334 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
336 u32 swfw_mask = hw->phy.phy_semaphore_mask;
340 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
341 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
342 if (status != IXGBE_SUCCESS) {
343 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
344 "semaphore failed with %d\n", status);
347 status = ixgbe_get_cs4227_status(hw);
348 if (status == IXGBE_SUCCESS) {
349 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
350 msec_delay(hw->eeprom.semaphore_delay);
353 ixgbe_reset_cs4227(hw);
354 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
355 msec_delay(hw->eeprom.semaphore_delay);
357 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
358 "Unable to initialize CS4227, err=%d\n", status);
362 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
363 * @hw: pointer to hardware structure
365 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
367 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
369 if (hw->bus.lan_id) {
370 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
371 esdp |= IXGBE_ESDP_SDP1_DIR;
373 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
374 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
375 IXGBE_WRITE_FLUSH(hw);
379 * ixgbe_identify_phy_x550em - Get PHY type based on device id
380 * @hw: pointer to hardware structure
384 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
386 switch (hw->device_id) {
387 case IXGBE_DEV_ID_X550EM_X_SFP:
388 /* set up for CS4227 usage */
389 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
390 ixgbe_setup_mux_ctl(hw);
391 ixgbe_check_cs4227(hw);
393 return ixgbe_identify_module_generic(hw);
395 case IXGBE_DEV_ID_X550EM_X_KX4:
396 hw->phy.type = ixgbe_phy_x550em_kx4;
398 case IXGBE_DEV_ID_X550EM_X_KR:
399 hw->phy.type = ixgbe_phy_x550em_kr;
401 case IXGBE_DEV_ID_X550EM_X_1G_T:
402 case IXGBE_DEV_ID_X550EM_X_10G_T:
403 return ixgbe_identify_phy_generic(hw);
407 return IXGBE_SUCCESS;
410 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
411 u32 device_type, u16 *phy_data)
413 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
414 return IXGBE_NOT_IMPLEMENTED;
417 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
418 u32 device_type, u16 phy_data)
420 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
421 return IXGBE_NOT_IMPLEMENTED;
425 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
426 * @hw: pointer to hardware structure
428 * Initialize the function pointers and for MAC type X550EM.
429 * Does not touch the hardware.
431 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
433 struct ixgbe_mac_info *mac = &hw->mac;
434 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
435 struct ixgbe_phy_info *phy = &hw->phy;
438 DEBUGFUNC("ixgbe_init_ops_X550EM");
440 /* Similar to X550 so start there. */
441 ret_val = ixgbe_init_ops_X550(hw);
443 /* Since this function eventually calls
444 * ixgbe_init_ops_540 by design, we are setting
445 * the pointers to NULL explicitly here to overwrite
446 * the values being set in the x540 function.
448 /* Thermal sensor not supported in x550EM */
449 mac->ops.get_thermal_sensor_data = NULL;
450 mac->ops.init_thermal_sensor_thresh = NULL;
451 mac->thermal_sensor_enabled = false;
453 /* FCOE not supported in x550EM */
454 mac->ops.get_san_mac_addr = NULL;
455 mac->ops.set_san_mac_addr = NULL;
456 mac->ops.get_wwn_prefix = NULL;
457 mac->ops.get_fcoe_boot_status = NULL;
459 /* IPsec not supported in x550EM */
460 mac->ops.disable_sec_rx_path = NULL;
461 mac->ops.enable_sec_rx_path = NULL;
463 /* AUTOC register is not present in x550EM. */
464 mac->ops.prot_autoc_read = NULL;
465 mac->ops.prot_autoc_write = NULL;
467 /* X550EM bus type is internal*/
468 hw->bus.type = ixgbe_bus_type_internal;
469 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
471 if (hw->mac.type == ixgbe_mac_X550EM_x) {
472 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
473 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
474 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
475 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
478 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
479 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
480 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
481 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
482 mac->ops.get_supported_physical_layer =
483 ixgbe_get_supported_physical_layer_X550em;
485 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
486 mac->ops.setup_fc = ixgbe_setup_fc_generic;
488 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
491 if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
492 mac->ops.setup_eee = NULL;
495 phy->ops.init = ixgbe_init_phy_ops_X550em;
496 phy->ops.identify = ixgbe_identify_phy_x550em;
497 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
498 phy->ops.set_phy_power = NULL;
502 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
503 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
504 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
505 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
506 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
507 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
508 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
509 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
515 * ixgbe_dmac_config_X550
516 * @hw: pointer to hardware structure
518 * Configure DMA coalescing. If enabling dmac, dmac is activated.
519 * When disabling dmac, dmac enable dmac bit is cleared.
521 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
523 u32 reg, high_pri_tc;
525 DEBUGFUNC("ixgbe_dmac_config_X550");
527 /* Disable DMA coalescing before configuring */
528 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
529 reg &= ~IXGBE_DMACR_DMAC_EN;
530 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
532 /* Disable DMA Coalescing if the watchdog timer is 0 */
533 if (!hw->mac.dmac_config.watchdog_timer)
536 ixgbe_dmac_config_tcs_X550(hw);
538 /* Configure DMA Coalescing Control Register */
539 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
541 /* Set the watchdog timer in units of 40.96 usec */
542 reg &= ~IXGBE_DMACR_DMACWT_MASK;
543 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
545 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
546 /* If fcoe is enabled, set high priority traffic class */
547 if (hw->mac.dmac_config.fcoe_en) {
548 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
549 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
550 IXGBE_DMACR_HIGH_PRI_TC_MASK);
552 reg |= IXGBE_DMACR_EN_MNG_IND;
554 /* Enable DMA coalescing after configuration */
555 reg |= IXGBE_DMACR_DMAC_EN;
556 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
559 return IXGBE_SUCCESS;
563 * ixgbe_dmac_config_tcs_X550
564 * @hw: pointer to hardware structure
566 * Configure DMA coalescing threshold per TC. The dmac enable bit must
567 * be cleared before configuring.
569 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
571 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
573 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
575 /* Configure DMA coalescing enabled */
576 switch (hw->mac.dmac_config.link_speed) {
577 case IXGBE_LINK_SPEED_100_FULL:
578 pb_headroom = IXGBE_DMACRXT_100M;
580 case IXGBE_LINK_SPEED_1GB_FULL:
581 pb_headroom = IXGBE_DMACRXT_1G;
584 pb_headroom = IXGBE_DMACRXT_10G;
588 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
589 IXGBE_MHADD_MFS_SHIFT) / 1024);
591 /* Set the per Rx packet buffer receive threshold */
592 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
593 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
594 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
596 if (tc < hw->mac.dmac_config.num_tcs) {
598 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
599 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
600 IXGBE_RXPBSIZE_SHIFT;
602 /* Calculate receive buffer threshold in kilobytes */
603 if (rx_pb_size > pb_headroom)
604 rx_pb_size = rx_pb_size - pb_headroom;
608 /* Minimum of MFS shall be set for DMCTH */
609 reg |= (rx_pb_size > maxframe_size_kb) ?
610 rx_pb_size : maxframe_size_kb;
612 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
614 return IXGBE_SUCCESS;
618 * ixgbe_dmac_update_tcs_X550
619 * @hw: pointer to hardware structure
621 * Disables dmac, updates per TC settings, and then enables dmac.
623 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
627 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
629 /* Disable DMA coalescing before configuring */
630 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
631 reg &= ~IXGBE_DMACR_DMAC_EN;
632 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
634 ixgbe_dmac_config_tcs_X550(hw);
636 /* Enable DMA coalescing after configuration */
637 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
638 reg |= IXGBE_DMACR_DMAC_EN;
639 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
641 return IXGBE_SUCCESS;
645 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
646 * @hw: pointer to hardware structure
648 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
649 * ixgbe_hw struct in order to set up EEPROM access.
651 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
653 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
657 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
659 if (eeprom->type == ixgbe_eeprom_uninitialized) {
660 eeprom->semaphore_delay = 10;
661 eeprom->type = ixgbe_flash;
663 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
664 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
665 IXGBE_EEC_SIZE_SHIFT);
666 eeprom->word_size = 1 << (eeprom_size +
667 IXGBE_EEPROM_WORD_SIZE_SHIFT);
669 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
670 eeprom->type, eeprom->word_size);
673 return IXGBE_SUCCESS;
677 * ixgbe_setup_eee_X550 - Enable/disable EEE support
678 * @hw: pointer to the HW structure
679 * @enable_eee: boolean flag to enable EEE
681 * Enable/disable EEE based on enable_eee flag.
682 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
686 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
694 DEBUGFUNC("ixgbe_setup_eee_X550");
696 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
697 /* Enable or disable EEE per flag */
699 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
701 if (hw->device_id == IXGBE_DEV_ID_X550T) {
702 /* Advertise EEE capability */
703 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
704 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
706 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
707 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
708 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
710 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
711 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
712 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
713 /* Not supported on first revision. */
714 fuse = IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0));
715 if (!(fuse & IXGBE_FUSES0_REV1))
716 return IXGBE_SUCCESS;
718 status = ixgbe_read_iosf_sb_reg_x550(hw,
719 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
720 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
721 if (status != IXGBE_SUCCESS)
724 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
725 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
727 /* Don't advertise FEC capability when EEE enabled. */
728 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
730 status = ixgbe_write_iosf_sb_reg_x550(hw,
731 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
732 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
733 if (status != IXGBE_SUCCESS)
737 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
739 if (hw->device_id == IXGBE_DEV_ID_X550T) {
740 /* Disable advertised EEE capability */
741 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
742 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
744 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
745 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
746 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
748 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
749 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
750 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
751 status = ixgbe_read_iosf_sb_reg_x550(hw,
752 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
753 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
754 if (status != IXGBE_SUCCESS)
757 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
758 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
760 /* Advertise FEC capability when EEE is disabled. */
761 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
763 status = ixgbe_write_iosf_sb_reg_x550(hw,
764 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
765 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
766 if (status != IXGBE_SUCCESS)
770 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
772 return IXGBE_SUCCESS;
776 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
777 * @hw: pointer to hardware structure
778 * @enable: enable or disable source address pruning
779 * @pool: Rx pool to set source address pruning for
781 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
786 /* max rx pool is 63 */
790 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
791 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
794 pfflp |= (1ULL << pool);
796 pfflp &= ~(1ULL << pool);
798 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
799 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
803 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
804 * @hw: pointer to hardware structure
805 * @enable: enable or disable switch for Ethertype anti-spoofing
806 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
809 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
812 int vf_target_reg = vf >> 3;
813 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
816 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
818 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
820 pfvfspoof |= (1 << vf_target_shift);
822 pfvfspoof &= ~(1 << vf_target_shift);
824 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
828 * ixgbe_iosf_wait - Wait for IOSF command completion
829 * @hw: pointer to hardware structure
830 * @ctrl: pointer to location to receive final IOSF control value
832 * Returns failing status on timeout
834 * Note: ctrl can be NULL if the IOSF control register value is not needed
836 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
840 /* Check every 10 usec to see if the address cycle completed.
841 * The SB IOSF BUSY bit will clear when the operation is
844 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
845 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
846 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
852 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
853 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
854 return IXGBE_ERR_PHY;
857 return IXGBE_SUCCESS;
861 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
863 * @hw: pointer to hardware structure
864 * @reg_addr: 32 bit PHY register to write
865 * @device_type: 3 bit device type
866 * @data: Data to write to the register
868 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
869 u32 device_type, u32 data)
871 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
875 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
876 if (ret != IXGBE_SUCCESS)
879 ret = ixgbe_iosf_wait(hw, NULL);
880 if (ret != IXGBE_SUCCESS)
883 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
884 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
886 /* Write IOSF control register */
887 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
889 /* Write IOSF data register */
890 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
892 ret = ixgbe_iosf_wait(hw, &command);
894 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
895 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
896 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
897 ERROR_REPORT2(IXGBE_ERROR_POLLING,
898 "Failed to write, error %x\n", error);
903 ixgbe_release_swfw_semaphore(hw, gssr);
908 * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
910 * @hw: pointer to hardware structure
911 * @reg_addr: 32 bit PHY register to write
912 * @device_type: 3 bit device type
913 * @phy_data: Pointer to read data from the register
915 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
916 u32 device_type, u32 *data)
918 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
922 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
923 if (ret != IXGBE_SUCCESS)
926 ret = ixgbe_iosf_wait(hw, NULL);
927 if (ret != IXGBE_SUCCESS)
930 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
931 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
933 /* Write IOSF control register */
934 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
936 ret = ixgbe_iosf_wait(hw, &command);
938 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
939 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
940 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
941 ERROR_REPORT2(IXGBE_ERROR_POLLING,
942 "Failed to read, error %x\n", error);
946 if (ret == IXGBE_SUCCESS)
947 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
950 ixgbe_release_swfw_semaphore(hw, gssr);
955 * ixgbe_disable_mdd_X550
956 * @hw: pointer to hardware structure
958 * Disable malicious driver detection
960 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
964 DEBUGFUNC("ixgbe_disable_mdd_X550");
966 /* Disable MDD for TX DMA and interrupt */
967 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
968 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
969 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
971 /* Disable MDD for RX and interrupt */
972 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
973 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
974 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
978 * ixgbe_enable_mdd_X550
979 * @hw: pointer to hardware structure
981 * Enable malicious driver detection
983 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
987 DEBUGFUNC("ixgbe_enable_mdd_X550");
989 /* Enable MDD for TX DMA and interrupt */
990 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
991 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
992 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
994 /* Enable MDD for RX and interrupt */
995 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
996 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
997 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1001 * ixgbe_restore_mdd_vf_X550
1002 * @hw: pointer to hardware structure
1005 * Restore VF that was disabled during malicious driver detection event
1007 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1009 u32 idx, reg, num_qs, start_q, bitmask;
1011 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1013 /* Map VF to queues */
1014 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1015 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1016 case IXGBE_MRQC_VMDQRT8TCEN:
1017 num_qs = 8; /* 16 VFs / pools */
1018 bitmask = 0x000000FF;
1020 case IXGBE_MRQC_VMDQRSS32EN:
1021 case IXGBE_MRQC_VMDQRT4TCEN:
1022 num_qs = 4; /* 32 VFs / pools */
1023 bitmask = 0x0000000F;
1025 default: /* 64 VFs / pools */
1027 bitmask = 0x00000003;
1030 start_q = vf * num_qs;
1032 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1035 reg |= (bitmask << (start_q % 32));
1036 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1037 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1041 * ixgbe_mdd_event_X550
1042 * @hw: pointer to hardware structure
1043 * @vf_bitmap: vf bitmap of malicious vfs
1045 * Handle malicious driver detection event.
1047 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1050 u32 i, j, reg, q, shift, vf, idx;
1052 DEBUGFUNC("ixgbe_mdd_event_X550");
1054 /* figure out pool size for mapping to vf's */
1055 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1056 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1057 case IXGBE_MRQC_VMDQRT8TCEN:
1058 shift = 3; /* 16 VFs / pools */
1060 case IXGBE_MRQC_VMDQRSS32EN:
1061 case IXGBE_MRQC_VMDQRT4TCEN:
1062 shift = 2; /* 32 VFs / pools */
1065 shift = 1; /* 64 VFs / pools */
1069 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1070 for (i = 0; i < 4; i++) {
1071 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1072 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1077 /* Get malicious queue */
1078 for (j = 0; j < 32 && wqbr; j++) {
1080 if (!(wqbr & (1 << j)))
1083 /* Get queue from bitmask */
1086 /* Map queue to vf */
1089 /* Set vf bit in vf_bitmap */
1091 vf_bitmap[idx] |= (1 << (vf % 32));
1098 * ixgbe_get_media_type_X550em - Get media type
1099 * @hw: pointer to hardware structure
1101 * Returns the media type (fiber, copper, backplane)
1103 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1105 enum ixgbe_media_type media_type;
1107 DEBUGFUNC("ixgbe_get_media_type_X550em");
1109 /* Detect if there is a copper PHY attached. */
1110 switch (hw->device_id) {
1111 case IXGBE_DEV_ID_X550EM_X_KR:
1112 case IXGBE_DEV_ID_X550EM_X_KX4:
1113 media_type = ixgbe_media_type_backplane;
1115 case IXGBE_DEV_ID_X550EM_X_SFP:
1116 media_type = ixgbe_media_type_fiber;
1118 case IXGBE_DEV_ID_X550EM_X_1G_T:
1119 case IXGBE_DEV_ID_X550EM_X_10G_T:
1120 media_type = ixgbe_media_type_copper;
1123 media_type = ixgbe_media_type_unknown;
1130 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1131 * @hw: pointer to hardware structure
1132 * @linear: true if SFP module is linear
1134 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1136 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1138 switch (hw->phy.sfp_type) {
1139 case ixgbe_sfp_type_not_present:
1140 return IXGBE_ERR_SFP_NOT_PRESENT;
1141 case ixgbe_sfp_type_da_cu_core0:
1142 case ixgbe_sfp_type_da_cu_core1:
1145 case ixgbe_sfp_type_srlr_core0:
1146 case ixgbe_sfp_type_srlr_core1:
1147 case ixgbe_sfp_type_da_act_lmt_core0:
1148 case ixgbe_sfp_type_da_act_lmt_core1:
1149 case ixgbe_sfp_type_1g_sx_core0:
1150 case ixgbe_sfp_type_1g_sx_core1:
1151 case ixgbe_sfp_type_1g_lx_core0:
1152 case ixgbe_sfp_type_1g_lx_core1:
1155 case ixgbe_sfp_type_unknown:
1156 case ixgbe_sfp_type_1g_cu_core0:
1157 case ixgbe_sfp_type_1g_cu_core1:
1159 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1162 return IXGBE_SUCCESS;
1166 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1167 * @hw: pointer to hardware structure
1169 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1171 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1176 DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1178 status = ixgbe_identify_module_generic(hw);
1180 if (status != IXGBE_SUCCESS)
1183 /* Check if SFP module is supported */
1184 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1190 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1191 * @hw: pointer to hardware structure
1193 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1198 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1200 /* Check if SFP module is supported */
1201 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1203 if (status != IXGBE_SUCCESS)
1206 ixgbe_init_mac_link_ops_X550em(hw);
1207 hw->phy.ops.reset = NULL;
1209 return IXGBE_SUCCESS;
1213 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1214 * @hw: pointer to hardware structure
1216 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1218 struct ixgbe_mac_info *mac = &hw->mac;
1220 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1222 switch (hw->mac.ops.get_media_type(hw)) {
1223 case ixgbe_media_type_fiber:
1224 /* CS4227 does not support autoneg, so disable the laser control
1225 * functions for SFP+ fiber
1227 mac->ops.disable_tx_laser = NULL;
1228 mac->ops.enable_tx_laser = NULL;
1229 mac->ops.flap_tx_laser = NULL;
1230 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1231 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1232 mac->ops.set_rate_select_speed =
1233 ixgbe_set_soft_rate_select_speed;
1235 case ixgbe_media_type_copper:
1236 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1237 mac->ops.check_link = ixgbe_check_link_t_X550em;
1245 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1246 * @hw: pointer to hardware structure
1247 * @speed: pointer to link speed
1248 * @autoneg: true when autoneg or autotry is enabled
1250 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1251 ixgbe_link_speed *speed,
1254 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1257 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1259 /* CS4227 SFP must not enable auto-negotiation */
1262 /* Check if 1G SFP module. */
1263 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1264 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1265 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1266 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1267 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1268 return IXGBE_SUCCESS;
1271 /* Link capabilities are based on SFP */
1272 if (hw->phy.multispeed_fiber)
1273 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1274 IXGBE_LINK_SPEED_1GB_FULL;
1276 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1278 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1279 IXGBE_LINK_SPEED_1GB_FULL;
1283 return IXGBE_SUCCESS;
1287 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1288 * @hw: pointer to hardware structure
1289 * @lsc: pointer to boolean flag which indicates whether external Base T
1290 * PHY interrupt is lsc
1292 * Determime if external Base T PHY interrupt cause is high temperature
1293 * failure alarm or link status change.
1295 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1296 * failure alarm, else return PHY access status.
1298 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1305 /* Vendor alarm triggered */
1306 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1307 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1310 if (status != IXGBE_SUCCESS ||
1311 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1314 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1315 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1316 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1319 if (status != IXGBE_SUCCESS ||
1320 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1321 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1324 /* High temperature failure alarm triggered */
1325 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1326 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1329 if (status != IXGBE_SUCCESS)
1332 /* If high temperature failure, then return over temp error and exit */
1333 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1334 /* power down the PHY in case the PHY FW didn't already */
1335 ixgbe_set_copper_phy_power(hw, false);
1336 return IXGBE_ERR_OVERTEMP;
1339 /* Vendor alarm 2 triggered */
1340 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1341 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1343 if (status != IXGBE_SUCCESS ||
1344 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1347 /* link connect/disconnect event occurred */
1348 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1349 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1351 if (status != IXGBE_SUCCESS)
1355 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1358 return IXGBE_SUCCESS;
1362 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1363 * @hw: pointer to hardware structure
1365 * Enable link status change and temperature failure alarm for the external
1368 * Returns PHY access status
1370 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1376 /* Clear interrupt flags */
1377 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1379 /* Enable link status change alarm */
1380 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1381 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1383 if (status != IXGBE_SUCCESS)
1386 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1388 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1389 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1391 if (status != IXGBE_SUCCESS)
1394 /* Enables high temperature failure alarm */
1395 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1396 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1399 if (status != IXGBE_SUCCESS)
1402 reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;
1404 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1405 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1408 if (status != IXGBE_SUCCESS)
1411 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1412 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1413 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1416 if (status != IXGBE_SUCCESS)
1419 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1420 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1422 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1423 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1426 if (status != IXGBE_SUCCESS)
1429 /* Enable chip-wide vendor alarm */
1430 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1431 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1434 if (status != IXGBE_SUCCESS)
1437 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1439 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1440 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1447 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1448 * @hw: pointer to hardware structure
1449 * @speed: link speed
1451 * Configures the integrated KR PHY.
1453 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1454 ixgbe_link_speed speed)
1459 status = ixgbe_read_iosf_sb_reg_x550(hw,
1460 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1461 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1465 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1466 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1467 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1469 /* Advertise 10G support. */
1470 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1471 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1473 /* Advertise 1G support. */
1474 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1475 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1477 /* Restart auto-negotiation. */
1478 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1479 status = ixgbe_write_iosf_sb_reg_x550(hw,
1480 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1481 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1487 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1488 * @hw: pointer to hardware structure
1490 * Initialize any function pointers that were not able to be
1491 * set during init_shared_code because the PHY/SFP type was
1492 * not known. Perform the SFP init if necessary.
1494 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1496 struct ixgbe_phy_info *phy = &hw->phy;
1497 ixgbe_link_speed speed;
1500 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1502 hw->mac.ops.set_lan_id(hw);
1504 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1505 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1506 ixgbe_setup_mux_ctl(hw);
1508 /* Save NW management interface connected on board. This is used
1509 * to determine internal PHY mode.
1511 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1513 /* If internal PHY mode is KR, then initialize KR link */
1514 if (phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) {
1515 speed = IXGBE_LINK_SPEED_10GB_FULL |
1516 IXGBE_LINK_SPEED_1GB_FULL;
1517 ret_val = ixgbe_setup_kr_speed_x550em(hw, speed);
1520 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
1523 /* Identify the PHY or SFP module */
1524 ret_val = phy->ops.identify(hw);
1525 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1528 /* Setup function pointers based on detected hardware */
1529 ixgbe_init_mac_link_ops_X550em(hw);
1530 if (phy->sfp_type != ixgbe_sfp_type_unknown)
1531 phy->ops.reset = NULL;
1533 /* Set functions pointers based on phy type */
1534 switch (hw->phy.type) {
1535 case ixgbe_phy_x550em_kx4:
1536 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
1537 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1538 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1540 case ixgbe_phy_x550em_kr:
1541 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1542 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1543 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1545 case ixgbe_phy_x550em_ext_t:
1546 /* Save NW management interface connected on board. This is used
1547 * to determine internal PHY mode
1549 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1551 /* If internal link mode is XFI, then setup iXFI internal link,
1552 * else setup KR now.
1554 if (!(phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1555 phy->ops.setup_internal_link =
1556 ixgbe_setup_internal_phy_t_x550em;
1558 speed = IXGBE_LINK_SPEED_10GB_FULL |
1559 IXGBE_LINK_SPEED_1GB_FULL;
1560 ret_val = ixgbe_setup_kr_speed_x550em(hw, speed);
1563 /* setup SW LPLU only for first revision */
1564 if (!(IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw,
1565 IXGBE_FUSES0_GROUP(0))))
1566 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1568 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1569 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1578 * ixgbe_reset_hw_X550em - Perform hardware reset
1579 * @hw: pointer to hardware structure
1581 * Resets the hardware by resetting the transmit and receive units, masks
1582 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1585 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1587 ixgbe_link_speed link_speed;
1592 bool link_up = false;
1594 DEBUGFUNC("ixgbe_reset_hw_X550em");
1596 /* Call adapter stop to disable Tx/Rx and clear interrupts */
1597 status = hw->mac.ops.stop_adapter(hw);
1598 if (status != IXGBE_SUCCESS)
1601 /* flush pending Tx transactions */
1602 ixgbe_clear_tx_pending(hw);
1604 /* PHY ops must be identified and initialized prior to reset */
1606 /* Identify PHY and related function pointers */
1607 status = hw->phy.ops.init(hw);
1609 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1612 /* start the external PHY */
1613 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1614 status = ixgbe_init_ext_t_x550em(hw);
1619 /* Setup SFP module if there is one present. */
1620 if (hw->phy.sfp_setup_needed) {
1621 status = hw->mac.ops.setup_sfp(hw);
1622 hw->phy.sfp_setup_needed = false;
1625 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1629 if (!hw->phy.reset_disable && hw->phy.ops.reset)
1630 hw->phy.ops.reset(hw);
1633 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
1634 * If link reset is used when link is up, it might reset the PHY when
1635 * mng is using it. If link is down or the flag to force full link
1636 * reset is set, then perform link reset.
1638 ctrl = IXGBE_CTRL_LNK_RST;
1639 if (!hw->force_full_reset) {
1640 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1642 ctrl = IXGBE_CTRL_RST;
1645 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1646 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1647 IXGBE_WRITE_FLUSH(hw);
1649 /* Poll for reset bit to self-clear meaning reset is complete */
1650 for (i = 0; i < 10; i++) {
1652 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1653 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1657 if (ctrl & IXGBE_CTRL_RST_MASK) {
1658 status = IXGBE_ERR_RESET_FAILED;
1659 DEBUGOUT("Reset polling failed to complete.\n");
1664 /* Double resets are required for recovery from certain error
1665 * conditions. Between resets, it is necessary to stall to
1666 * allow time for any pending HW events to complete.
1668 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1669 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1673 /* Store the permanent mac address */
1674 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1676 /* Store MAC address from RAR0, clear receive address registers, and
1677 * clear the multicast table. Also reset num_rar_entries to 128,
1678 * since we modify this value when programming the SAN MAC address.
1680 hw->mac.num_rar_entries = 128;
1681 hw->mac.ops.init_rx_addrs(hw);
1683 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
1684 /* Config MDIO clock speed. */
1685 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1686 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
1687 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1690 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1691 ixgbe_setup_mux_ctl(hw);
1697 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1698 * @hw: pointer to hardware structure
1700 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1705 status = hw->phy.ops.read_reg(hw,
1706 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1707 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1710 if (status != IXGBE_SUCCESS)
1713 /* If PHY FW reset completed bit is set then this is the first
1714 * SW instance after a power on so the PHY FW must be un-stalled.
1716 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1717 status = hw->phy.ops.read_reg(hw,
1718 IXGBE_MDIO_GLOBAL_RES_PR_10,
1719 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1722 if (status != IXGBE_SUCCESS)
1725 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1727 status = hw->phy.ops.write_reg(hw,
1728 IXGBE_MDIO_GLOBAL_RES_PR_10,
1729 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1732 if (status != IXGBE_SUCCESS)
1740 * ixgbe_setup_kr_x550em - Configure the KR PHY.
1741 * @hw: pointer to hardware structure
1743 * Configures the integrated KR PHY.
1745 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1747 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
1751 * ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1752 * @hw: pointer to hardware structure
1754 * Configures the integrated KX4 PHY.
1756 s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1761 status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1762 IXGBE_SB_IOSF_TARGET_KX4_PCS, ®_val);
1766 reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1767 IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1769 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1771 /* Advertise 10G support. */
1772 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1773 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1775 /* Advertise 1G support. */
1776 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1777 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1779 /* Restart auto-negotiation. */
1780 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1781 status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1782 IXGBE_SB_IOSF_TARGET_KX4_PCS, reg_val);
1788 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
1789 * @hw: pointer to hardware structure
1791 * Configure the external PHY and the integrated KR PHY for SFP support.
1793 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1794 ixgbe_link_speed speed,
1795 bool autoneg_wait_to_complete)
1798 u16 reg_slice, reg_val;
1799 bool setup_linear = false;
1800 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1802 /* Check if SFP module is supported and linear */
1803 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1805 /* If no SFP module present, then return success. Return success since
1806 * there is no reason to configure CS4227 and SFP not present error is
1807 * not excepted in the setup MAC link flow.
1809 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1810 return IXGBE_SUCCESS;
1812 if (ret_val != IXGBE_SUCCESS)
1815 /* Configure CS4227 LINE side to 10G SR. */
1816 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB + (hw->bus.lan_id << 12);
1817 reg_val = IXGBE_CS4227_SPEED_10G;
1818 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1821 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1822 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1823 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1826 /* Configure CS4227 for HOST connection rate then type. */
1827 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB + (hw->bus.lan_id << 12);
1828 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
1829 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
1830 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1833 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (hw->bus.lan_id << 12);
1835 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1837 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1838 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1841 /* If internal link mode is XFI, then setup XFI internal link. */
1842 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE))
1843 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
1849 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1850 * @hw: pointer to hardware structure
1851 * @speed: the link speed to force
1853 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
1854 * internal and external PHY at a specific speed, without autonegotiation.
1856 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1861 /* Disable AN and force speed to 10G Serial. */
1862 status = ixgbe_read_iosf_sb_reg_x550(hw,
1863 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1864 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1865 if (status != IXGBE_SUCCESS)
1868 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1869 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1871 /* Select forced link speed for internal PHY. */
1873 case IXGBE_LINK_SPEED_10GB_FULL:
1874 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1876 case IXGBE_LINK_SPEED_1GB_FULL:
1877 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1880 /* Other link speeds are not supported by internal KR PHY. */
1881 return IXGBE_ERR_LINK_SETUP;
1884 status = ixgbe_write_iosf_sb_reg_x550(hw,
1885 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1886 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1887 if (status != IXGBE_SUCCESS)
1890 /* Disable training protocol FSM. */
1891 status = ixgbe_read_iosf_sb_reg_x550(hw,
1892 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1893 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1894 if (status != IXGBE_SUCCESS)
1896 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1897 status = ixgbe_write_iosf_sb_reg_x550(hw,
1898 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1899 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1900 if (status != IXGBE_SUCCESS)
1903 /* Disable Flex from training TXFFE. */
1904 status = ixgbe_read_iosf_sb_reg_x550(hw,
1905 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1906 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1907 if (status != IXGBE_SUCCESS)
1909 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1910 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1911 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1912 status = ixgbe_write_iosf_sb_reg_x550(hw,
1913 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1914 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1915 if (status != IXGBE_SUCCESS)
1917 status = ixgbe_read_iosf_sb_reg_x550(hw,
1918 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1919 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1920 if (status != IXGBE_SUCCESS)
1922 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1923 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1924 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1925 status = ixgbe_write_iosf_sb_reg_x550(hw,
1926 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1927 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1928 if (status != IXGBE_SUCCESS)
1931 /* Enable override for coefficients. */
1932 status = ixgbe_read_iosf_sb_reg_x550(hw,
1933 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1934 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1935 if (status != IXGBE_SUCCESS)
1937 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1938 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1939 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1940 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1941 status = ixgbe_write_iosf_sb_reg_x550(hw,
1942 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1943 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1944 if (status != IXGBE_SUCCESS)
1947 /* Toggle port SW reset by AN reset. */
1948 status = ixgbe_read_iosf_sb_reg_x550(hw,
1949 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1950 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1951 if (status != IXGBE_SUCCESS)
1953 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1954 status = ixgbe_write_iosf_sb_reg_x550(hw,
1955 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1956 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1962 * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
1963 * @hw: address of hardware structure
1964 * @link_up: address of boolean to indicate link status
1966 * Returns error code if unable to get link status.
1968 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
1975 /* read this twice back to back to indicate current status */
1976 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1977 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1979 if (ret != IXGBE_SUCCESS)
1982 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1983 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1985 if (ret != IXGBE_SUCCESS)
1988 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
1990 return IXGBE_SUCCESS;
1994 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1995 * @hw: point to hardware structure
1997 * Configures the link between the integrated KR PHY and the external X557 PHY
1998 * The driver will call this function when it gets a link status change
1999 * interrupt from the X557 PHY. This function configures the link speed
2000 * between the PHYs to match the link speed of the BASE-T link.
2002 * A return of a non-zero value indicates an error, and the base driver should
2003 * not report link up.
2005 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2007 ixgbe_link_speed force_speed;
2012 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2013 return IXGBE_ERR_CONFIG;
2015 /* If link is not up, then there is no setup necessary so return */
2016 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2017 if (status != IXGBE_SUCCESS)
2021 return IXGBE_SUCCESS;
2023 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2024 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2026 if (status != IXGBE_SUCCESS)
2029 /* If link is not still up, then no setup is necessary so return */
2030 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2031 if (status != IXGBE_SUCCESS)
2034 return IXGBE_SUCCESS;
2036 /* clear everything but the speed and duplex bits */
2037 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2040 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2041 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2043 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2044 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2047 /* Internal PHY does not support anything else */
2048 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2051 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2055 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
2056 * @hw: pointer to hardware structure
2058 * Configures the integrated KR PHY to use internal loopback mode.
2060 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
2065 /* Disable AN and force speed to 10G Serial. */
2066 status = ixgbe_read_iosf_sb_reg_x550(hw,
2067 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2068 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2069 if (status != IXGBE_SUCCESS)
2071 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2072 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2073 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2074 status = ixgbe_write_iosf_sb_reg_x550(hw,
2075 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2076 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2077 if (status != IXGBE_SUCCESS)
2080 /* Set near-end loopback clocks. */
2081 status = ixgbe_read_iosf_sb_reg_x550(hw,
2082 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2083 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2084 if (status != IXGBE_SUCCESS)
2086 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2087 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2088 status = ixgbe_write_iosf_sb_reg_x550(hw,
2089 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2090 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2091 if (status != IXGBE_SUCCESS)
2094 /* Set loopback enable. */
2095 status = ixgbe_read_iosf_sb_reg_x550(hw,
2096 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2097 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2098 if (status != IXGBE_SUCCESS)
2100 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2101 status = ixgbe_write_iosf_sb_reg_x550(hw,
2102 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2103 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2104 if (status != IXGBE_SUCCESS)
2107 /* Training bypass. */
2108 status = ixgbe_read_iosf_sb_reg_x550(hw,
2109 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2110 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2111 if (status != IXGBE_SUCCESS)
2113 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2114 status = ixgbe_write_iosf_sb_reg_x550(hw,
2115 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2116 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2122 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2123 * assuming that the semaphore is already obtained.
2124 * @hw: pointer to hardware structure
2125 * @offset: offset of word in the EEPROM to read
2126 * @data: word read from the EEPROM
2128 * Reads a 16 bit word from the EEPROM using the hostif.
2130 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2134 struct ixgbe_hic_read_shadow_ram buffer;
2136 DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2137 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2138 buffer.hdr.req.buf_lenh = 0;
2139 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2140 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2142 /* convert offset from words to bytes */
2143 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2145 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2147 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2149 IXGBE_HI_COMMAND_TIMEOUT, false);
2154 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2155 FW_NVM_DATA_OFFSET);
2161 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2162 * @hw: pointer to hardware structure
2163 * @offset: offset of word in the EEPROM to read
2164 * @data: word read from the EEPROM
2166 * Reads a 16 bit word from the EEPROM using the hostif.
2168 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2171 s32 status = IXGBE_SUCCESS;
2173 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2175 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2177 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2178 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2180 status = IXGBE_ERR_SWFW_SYNC;
2187 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2188 * @hw: pointer to hardware structure
2189 * @offset: offset of word in the EEPROM to read
2190 * @words: number of words
2191 * @data: word(s) read from the EEPROM
2193 * Reads a 16 bit word(s) from the EEPROM using the hostif.
2195 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2196 u16 offset, u16 words, u16 *data)
2198 struct ixgbe_hic_read_shadow_ram buffer;
2199 u32 current_word = 0;
2204 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2206 /* Take semaphore for the entire operation. */
2207 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2209 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2213 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2214 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2216 words_to_read = words;
2218 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2219 buffer.hdr.req.buf_lenh = 0;
2220 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2221 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2223 /* convert offset from words to bytes */
2224 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2225 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2227 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2229 IXGBE_HI_COMMAND_TIMEOUT,
2233 DEBUGOUT("Host interface command failed\n");
2237 for (i = 0; i < words_to_read; i++) {
2238 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
2240 u32 value = IXGBE_READ_REG(hw, reg);
2242 data[current_word] = (u16)(value & 0xffff);
2245 if (i < words_to_read) {
2247 data[current_word] = (u16)(value & 0xffff);
2251 words -= words_to_read;
2255 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2260 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2261 * @hw: pointer to hardware structure
2262 * @offset: offset of word in the EEPROM to write
2263 * @data: word write to the EEPROM
2265 * Write a 16 bit word to the EEPROM using the hostif.
2267 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2271 struct ixgbe_hic_write_shadow_ram buffer;
2273 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
2275 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
2276 buffer.hdr.req.buf_lenh = 0;
2277 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
2278 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2281 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2283 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2285 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2287 IXGBE_HI_COMMAND_TIMEOUT, false);
2293 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2294 * @hw: pointer to hardware structure
2295 * @offset: offset of word in the EEPROM to write
2296 * @data: word write to the EEPROM
2298 * Write a 16 bit word to the EEPROM using the hostif.
2300 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2303 s32 status = IXGBE_SUCCESS;
2305 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2307 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2309 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2310 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2312 DEBUGOUT("write ee hostif failed to get semaphore");
2313 status = IXGBE_ERR_SWFW_SYNC;
2320 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2321 * @hw: pointer to hardware structure
2322 * @offset: offset of word in the EEPROM to write
2323 * @words: number of words
2324 * @data: word(s) write to the EEPROM
2326 * Write a 16 bit word(s) to the EEPROM using the hostif.
2328 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2329 u16 offset, u16 words, u16 *data)
2331 s32 status = IXGBE_SUCCESS;
2334 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2336 /* Take semaphore for the entire operation. */
2337 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2338 if (status != IXGBE_SUCCESS) {
2339 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2343 for (i = 0; i < words; i++) {
2344 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2347 if (status != IXGBE_SUCCESS) {
2348 DEBUGOUT("Eeprom buffered write failed\n");
2353 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2360 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2361 * @hw: pointer to hardware structure
2362 * @ptr: pointer offset in eeprom
2363 * @size: size of section pointed by ptr, if 0 first word will be used as size
2364 * @csum: address of checksum to update
2366 * Returns error status for any failure
2368 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2369 u16 size, u16 *csum, u16 *buffer,
2374 u16 length, bufsz, i, start;
2377 bufsz = sizeof(buf) / sizeof(buf[0]);
2379 /* Read a chunk at the pointer location */
2381 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2383 DEBUGOUT("Failed to read EEPROM image\n");
2388 if (buffer_size < ptr)
2389 return IXGBE_ERR_PARAM;
2390 local_buffer = &buffer[ptr];
2398 length = local_buffer[0];
2400 /* Skip pointer section if length is invalid. */
2401 if (length == 0xFFFF || length == 0 ||
2402 (ptr + length) >= hw->eeprom.word_size)
2403 return IXGBE_SUCCESS;
2406 if (buffer && ((u32)start + (u32)length > buffer_size))
2407 return IXGBE_ERR_PARAM;
2409 for (i = start; length; i++, length--) {
2410 if (i == bufsz && !buffer) {
2416 /* Read a chunk at the pointer location */
2417 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2420 DEBUGOUT("Failed to read EEPROM image\n");
2424 *csum += local_buffer[i];
2426 return IXGBE_SUCCESS;
2430 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2431 * @hw: pointer to hardware structure
2432 * @buffer: pointer to buffer containing calculated checksum
2433 * @buffer_size: size of buffer
2435 * Returns a negative error code on error, or the 16-bit checksum
2437 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2439 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2443 u16 pointer, i, size;
2445 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2447 hw->eeprom.ops.init_params(hw);
2450 /* Read pointer area */
2451 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2452 IXGBE_EEPROM_LAST_WORD + 1,
2455 DEBUGOUT("Failed to read EEPROM image\n");
2458 local_buffer = eeprom_ptrs;
2460 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2461 return IXGBE_ERR_PARAM;
2462 local_buffer = buffer;
2466 * For X550 hardware include 0x0-0x41 in the checksum, skip the
2467 * checksum word itself
2469 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2470 if (i != IXGBE_EEPROM_CHECKSUM)
2471 checksum += local_buffer[i];
2474 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
2475 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2477 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2478 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2481 pointer = local_buffer[i];
2483 /* Skip pointer section if the pointer is invalid. */
2484 if (pointer == 0xFFFF || pointer == 0 ||
2485 pointer >= hw->eeprom.word_size)
2489 case IXGBE_PCIE_GENERAL_PTR:
2490 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2492 case IXGBE_PCIE_CONFIG0_PTR:
2493 case IXGBE_PCIE_CONFIG1_PTR:
2494 size = IXGBE_PCIE_CONFIG_SIZE;
2501 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2502 buffer, buffer_size);
2507 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2509 return (s32)checksum;
2513 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2514 * @hw: pointer to hardware structure
2516 * Returns a negative error code on error, or the 16-bit checksum
2518 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2520 return ixgbe_calc_checksum_X550(hw, NULL, 0);
2524 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2525 * @hw: pointer to hardware structure
2526 * @checksum_val: calculated checksum
2528 * Performs checksum calculation and validates the EEPROM checksum. If the
2529 * caller does not need checksum_val, the value can be NULL.
2531 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2535 u16 read_checksum = 0;
2537 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2539 /* Read the first word from the EEPROM. If this times out or fails, do
2540 * not continue or we could be in for a very long wait while every
2543 status = hw->eeprom.ops.read(hw, 0, &checksum);
2545 DEBUGOUT("EEPROM read failed\n");
2549 status = hw->eeprom.ops.calc_checksum(hw);
2553 checksum = (u16)(status & 0xffff);
2555 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2560 /* Verify read checksum from EEPROM is the same as
2561 * calculated checksum
2563 if (read_checksum != checksum) {
2564 status = IXGBE_ERR_EEPROM_CHECKSUM;
2565 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2566 "Invalid EEPROM checksum");
2569 /* If the user cares, return the calculated checksum */
2571 *checksum_val = checksum;
2577 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2578 * @hw: pointer to hardware structure
2580 * After writing EEPROM to shadow RAM using EEWR register, software calculates
2581 * checksum and updates the EEPROM and instructs the hardware to update
2584 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2589 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2591 /* Read the first word from the EEPROM. If this times out or fails, do
2592 * not continue or we could be in for a very long wait while every
2595 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2597 DEBUGOUT("EEPROM read failed\n");
2601 status = ixgbe_calc_eeprom_checksum_X550(hw);
2605 checksum = (u16)(status & 0xffff);
2607 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2612 status = ixgbe_update_flash_X550(hw);
2618 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2619 * @hw: pointer to hardware structure
2621 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2623 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2625 s32 status = IXGBE_SUCCESS;
2626 union ixgbe_hic_hdr2 buffer;
2628 DEBUGFUNC("ixgbe_update_flash_X550");
2630 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2631 buffer.req.buf_lenh = 0;
2632 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2633 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2635 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2637 IXGBE_HI_COMMAND_TIMEOUT, false);
2643 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2644 * @hw: pointer to hardware structure
2646 * Determines physical layer capabilities of the current configuration.
2648 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2650 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2651 u16 ext_ability = 0;
2653 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2655 hw->phy.ops.identify(hw);
2657 switch (hw->phy.type) {
2658 case ixgbe_phy_x550em_kr:
2659 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2660 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2662 case ixgbe_phy_x550em_kx4:
2663 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2664 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2666 case ixgbe_phy_x550em_ext_t:
2667 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2668 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2670 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2671 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2672 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2673 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2679 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2680 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2682 return physical_layer;
2686 * ixgbe_get_bus_info_x550em - Set PCI bus info
2687 * @hw: pointer to hardware structure
2689 * Sets bus link width and speed to unknown because X550em is
2692 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2695 DEBUGFUNC("ixgbe_get_bus_info_x550em");
2697 hw->bus.width = ixgbe_bus_width_unknown;
2698 hw->bus.speed = ixgbe_bus_speed_unknown;
2700 hw->mac.ops.set_lan_id(hw);
2702 return IXGBE_SUCCESS;
2706 * ixgbe_disable_rx_x550 - Disable RX unit
2708 * Enables the Rx DMA unit for x550
2710 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2712 u32 rxctrl, pfdtxgswc;
2714 struct ixgbe_hic_disable_rxen fw_cmd;
2716 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2718 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2719 if (rxctrl & IXGBE_RXCTRL_RXEN) {
2720 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2721 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2722 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2723 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2724 hw->mac.set_lben = true;
2726 hw->mac.set_lben = false;
2729 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2730 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2731 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2732 fw_cmd.port_number = (u8)hw->bus.lan_id;
2734 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2735 sizeof(struct ixgbe_hic_disable_rxen),
2736 IXGBE_HI_COMMAND_TIMEOUT, true);
2738 /* If we fail - disable RX using register write */
2740 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2741 if (rxctrl & IXGBE_RXCTRL_RXEN) {
2742 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2743 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2750 * ixgbe_enter_lplu_x550em - Transition to low power states
2751 * @hw: pointer to hardware structure
2753 * Configures Low Power Link Up on transition to low power states
2754 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2755 * X557 PHY immediately prior to entering LPLU.
2757 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2759 u16 an_10g_cntl_reg, autoneg_reg, speed;
2761 ixgbe_link_speed lcd_speed;
2765 /* SW LPLU not required on later HW revisions. */
2766 if (IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)))
2767 return IXGBE_SUCCESS;
2769 /* If blocked by MNG FW, then don't restart AN */
2770 if (ixgbe_check_reset_blocked(hw))
2771 return IXGBE_SUCCESS;
2773 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2774 if (status != IXGBE_SUCCESS)
2777 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2779 if (status != IXGBE_SUCCESS)
2782 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2783 * disabled, then force link down by entering low power mode.
2785 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2786 !(hw->wol_enabled || ixgbe_mng_present(hw)))
2787 return ixgbe_set_copper_phy_power(hw, FALSE);
2790 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2792 if (status != IXGBE_SUCCESS)
2795 /* If no valid LCD link speed, then force link down and exit. */
2796 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2797 return ixgbe_set_copper_phy_power(hw, FALSE);
2799 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2800 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2803 if (status != IXGBE_SUCCESS)
2806 /* If no link now, speed is invalid so take link down */
2807 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2808 if (status != IXGBE_SUCCESS)
2809 return ixgbe_set_copper_phy_power(hw, false);
2811 /* clear everything but the speed bits */
2812 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2814 /* If current speed is already LCD, then exit. */
2815 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2816 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2817 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2818 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2821 /* Clear AN completed indication */
2822 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2823 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2826 if (status != IXGBE_SUCCESS)
2829 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2830 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2833 if (status != IXGBE_SUCCESS)
2836 status = hw->phy.ops.read_reg(hw,
2837 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2838 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2841 if (status != IXGBE_SUCCESS)
2844 save_autoneg = hw->phy.autoneg_advertised;
2846 /* Setup link at least common link speed */
2847 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
2849 /* restore autoneg from before setting lplu speed */
2850 hw->phy.autoneg_advertised = save_autoneg;
2856 * ixgbe_get_lcd_x550em - Determine lowest common denominator
2857 * @hw: pointer to hardware structure
2858 * @lcd_speed: pointer to lowest common link speed
2860 * Determine lowest common link speed with link partner.
2862 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2866 u16 word = hw->eeprom.ctrl_word_3;
2868 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2870 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2871 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2874 if (status != IXGBE_SUCCESS)
2877 /* If link partner advertised 1G, return 1G */
2878 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2879 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2883 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2884 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2885 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2888 /* Link partner not capable of lower speeds, return 10G */
2889 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2894 * ixgbe_setup_fc_X550em - Set up flow control
2895 * @hw: pointer to hardware structure
2897 * Called at init time to set up flow control.
2899 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
2901 s32 ret_val = IXGBE_SUCCESS;
2902 u32 pause, asm_dir, reg_val;
2904 DEBUGFUNC("ixgbe_setup_fc_X550em");
2906 /* Validate the requested mode */
2907 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2908 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2909 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2910 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2914 /* 10gig parts do not have a word in the EEPROM to determine the
2915 * default flow control setting, so we explicitly set it to full.
2917 if (hw->fc.requested_mode == ixgbe_fc_default)
2918 hw->fc.requested_mode = ixgbe_fc_full;
2920 /* Determine PAUSE and ASM_DIR bits. */
2921 switch (hw->fc.requested_mode) {
2926 case ixgbe_fc_tx_pause:
2930 case ixgbe_fc_rx_pause:
2931 /* Rx Flow control is enabled and Tx Flow control is
2932 * disabled by software override. Since there really
2933 * isn't a way to advertise that we are capable of RX
2934 * Pause ONLY, we will advertise that we support both
2935 * symmetric and asymmetric Rx PAUSE, as such we fall
2936 * through to the fc_full statement. Later, we will
2937 * disable the adapter's ability to send PAUSE frames.
2944 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2945 "Flow control param set incorrectly\n");
2946 ret_val = IXGBE_ERR_CONFIG;
2950 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
2951 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
2952 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2953 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2954 if (ret_val != IXGBE_SUCCESS)
2956 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2957 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2959 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2961 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2962 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
2963 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2964 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2966 /* This device does not fully support AN. */
2967 hw->fc.disable_fc_autoneg = true;
2975 * ixgbe_set_mux - Set mux for port 1 access with CS4227
2976 * @hw: pointer to hardware structure
2977 * @state: set mux if 1, clear if 0
2979 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2983 if (!hw->bus.lan_id)
2985 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2987 esdp |= IXGBE_ESDP_SDP1;
2989 esdp &= ~IXGBE_ESDP_SDP1;
2990 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2991 IXGBE_WRITE_FLUSH(hw);
2995 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2996 * @hw: pointer to hardware structure
2997 * @mask: Mask to specify which semaphore to acquire
2999 * Acquires the SWFW semaphore and sets the I2C MUX
3001 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3005 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
3007 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
3011 if (mask & IXGBE_GSSR_I2C_MASK)
3012 ixgbe_set_mux(hw, 1);
3014 return IXGBE_SUCCESS;
3018 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
3019 * @hw: pointer to hardware structure
3020 * @mask: Mask to specify which semaphore to release
3022 * Releases the SWFW semaphore and sets the I2C MUX
3024 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3026 DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
3028 if (mask & IXGBE_GSSR_I2C_MASK)
3029 ixgbe_set_mux(hw, 0);
3031 ixgbe_release_swfw_sync_X540(hw, mask);
3035 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
3036 * @hw: pointer to hardware structure
3038 * Handle external Base T PHY interrupt. If high temperature
3039 * failure alarm then return error, else if link status change
3040 * then setup internal/external PHY link
3042 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
3043 * failure alarm, else return PHY access status.
3045 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
3050 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
3052 if (status != IXGBE_SUCCESS)
3056 return ixgbe_setup_internal_phy(hw);
3058 return IXGBE_SUCCESS;
3062 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
3063 * @hw: pointer to hardware structure
3064 * @speed: new link speed
3065 * @autoneg_wait_to_complete: true when waiting for completion is needed
3067 * Setup internal/external PHY link speed based on link speed, then set
3068 * external PHY auto advertised link speed.
3070 * Returns error status for any failure
3072 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
3073 ixgbe_link_speed speed,
3074 bool autoneg_wait_to_complete)
3077 ixgbe_link_speed force_speed;
3079 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
3081 /* Setup internal/external PHY link speed to iXFI (10G), unless
3082 * only 1G is auto advertised then setup KX link.
3084 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
3085 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3087 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3089 /* If internal link mode is XFI, then setup XFI internal link. */
3090 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3091 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
3093 if (status != IXGBE_SUCCESS)
3097 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
3101 * ixgbe_check_link_t_X550em - Determine link and speed status
3102 * @hw: pointer to hardware structure
3103 * @speed: pointer to link speed
3104 * @link_up: true when link is up
3105 * @link_up_wait_to_complete: bool used to wait for link up or not
3107 * Check that both the MAC and X557 external PHY have link.
3109 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3110 bool *link_up, bool link_up_wait_to_complete)
3115 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3116 return IXGBE_ERR_CONFIG;
3118 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
3119 link_up_wait_to_complete);
3121 /* If check link fails or MAC link is not up, then return */
3122 if (status != IXGBE_SUCCESS || !(*link_up))
3125 /* MAC link is up, so check external PHY link.
3126 * Read this twice back to back to indicate current status.
3128 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3129 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3132 if (status != IXGBE_SUCCESS)
3135 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3136 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3139 if (status != IXGBE_SUCCESS)
3142 /* If external PHY link is not up, then indicate link not up */
3143 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
3146 return IXGBE_SUCCESS;
3150 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
3151 * @hw: pointer to hardware structure
3153 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
3157 status = ixgbe_reset_phy_generic(hw);
3159 if (status != IXGBE_SUCCESS)
3162 /* Configure Link Status Alarm and Temperature Threshold interrupts */
3163 return ixgbe_enable_lasi_ext_t_x550em(hw);
3167 * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
3168 * @hw: pointer to hardware structure
3169 * @led_idx: led number to turn on
3171 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3175 DEBUGFUNC("ixgbe_led_on_t_X550em");
3177 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3178 return IXGBE_ERR_PARAM;
3180 /* To turn on the LED, set mode to ON. */
3181 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3182 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3183 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
3184 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3185 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3187 return IXGBE_SUCCESS;
3191 * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
3192 * @hw: pointer to hardware structure
3193 * @led_idx: led number to turn off
3195 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3199 DEBUGFUNC("ixgbe_led_off_t_X550em");
3201 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3202 return IXGBE_ERR_PARAM;
3204 /* To turn on the LED, set mode to ON. */
3205 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3206 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3207 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
3208 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3209 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3211 return IXGBE_SUCCESS;