1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
42 static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
43 static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
46 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
47 * @hw: pointer to hardware structure
49 * Initialize the function pointers and assign the MAC type for X550.
50 * Does not touch the hardware.
52 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
54 struct ixgbe_mac_info *mac = &hw->mac;
55 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
58 DEBUGFUNC("ixgbe_init_ops_X550");
60 ret_val = ixgbe_init_ops_X540(hw);
61 mac->ops.dmac_config = ixgbe_dmac_config_X550;
62 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
63 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
64 mac->ops.setup_eee = ixgbe_setup_eee_X550;
65 mac->ops.set_source_address_pruning =
66 ixgbe_set_source_address_pruning_X550;
67 mac->ops.set_ethertype_anti_spoofing =
68 ixgbe_set_ethertype_anti_spoofing_X550;
70 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
71 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
72 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
73 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
74 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
75 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
76 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
77 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
78 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
80 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
81 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
82 mac->ops.mdd_event = ixgbe_mdd_event_X550;
83 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
84 mac->ops.disable_rx = ixgbe_disable_rx_x550;
85 switch (hw->device_id) {
86 case IXGBE_DEV_ID_X550EM_X_10G_T:
87 case IXGBE_DEV_ID_X550EM_A_10G_T:
88 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
89 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
98 * ixgbe_read_cs4227 - Read CS4227 register
99 * @hw: pointer to hardware structure
100 * @reg: register number to write
101 * @value: pointer to receive value read
103 * Returns status code
105 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
107 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
111 * ixgbe_write_cs4227 - Write CS4227 register
112 * @hw: pointer to hardware structure
113 * @reg: register number to write
114 * @value: value to write to register
116 * Returns status code
118 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
120 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
124 * ixgbe_read_pe - Read register from port expander
125 * @hw: pointer to hardware structure
126 * @reg: register number to read
127 * @value: pointer to receive read value
129 * Returns status code
131 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
135 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
136 if (status != IXGBE_SUCCESS)
137 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
138 "port expander access failed with %d\n", status);
143 * ixgbe_write_pe - Write register to port expander
144 * @hw: pointer to hardware structure
145 * @reg: register number to write
146 * @value: value to write
148 * Returns status code
150 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
154 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
155 if (status != IXGBE_SUCCESS)
156 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
157 "port expander access failed with %d\n", status);
162 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
163 * @hw: pointer to hardware structure
165 * This function assumes that the caller has acquired the proper semaphore.
168 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
175 /* Trigger hard reset. */
176 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
177 if (status != IXGBE_SUCCESS)
179 reg |= IXGBE_PE_BIT1;
180 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
181 if (status != IXGBE_SUCCESS)
184 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
185 if (status != IXGBE_SUCCESS)
187 reg &= ~IXGBE_PE_BIT1;
188 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
189 if (status != IXGBE_SUCCESS)
192 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
193 if (status != IXGBE_SUCCESS)
195 reg &= ~IXGBE_PE_BIT1;
196 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
197 if (status != IXGBE_SUCCESS)
200 usec_delay(IXGBE_CS4227_RESET_HOLD);
202 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
203 if (status != IXGBE_SUCCESS)
205 reg |= IXGBE_PE_BIT1;
206 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
207 if (status != IXGBE_SUCCESS)
210 /* Wait for the reset to complete. */
211 msec_delay(IXGBE_CS4227_RESET_DELAY);
212 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
213 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
215 if (status == IXGBE_SUCCESS &&
216 value == IXGBE_CS4227_EEPROM_LOAD_OK)
218 msec_delay(IXGBE_CS4227_CHECK_DELAY);
220 if (retry == IXGBE_CS4227_RETRIES) {
221 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
222 "CS4227 reset did not complete.");
223 return IXGBE_ERR_PHY;
226 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
227 if (status != IXGBE_SUCCESS ||
228 !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
229 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
230 "CS4227 EEPROM did not load successfully.");
231 return IXGBE_ERR_PHY;
234 return IXGBE_SUCCESS;
238 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
239 * @hw: pointer to hardware structure
241 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
243 s32 status = IXGBE_SUCCESS;
244 u32 swfw_mask = hw->phy.phy_semaphore_mask;
248 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
249 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
250 if (status != IXGBE_SUCCESS) {
251 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
252 "semaphore failed with %d", status);
253 msec_delay(IXGBE_CS4227_CHECK_DELAY);
257 /* Get status of reset flow. */
258 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
260 if (status == IXGBE_SUCCESS &&
261 value == IXGBE_CS4227_RESET_COMPLETE)
264 if (status != IXGBE_SUCCESS ||
265 value != IXGBE_CS4227_RESET_PENDING)
268 /* Reset is pending. Wait and check again. */
269 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
270 msec_delay(IXGBE_CS4227_CHECK_DELAY);
273 /* If still pending, assume other instance failed. */
274 if (retry == IXGBE_CS4227_RETRIES) {
275 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
276 if (status != IXGBE_SUCCESS) {
277 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
278 "semaphore failed with %d", status);
283 /* Reset the CS4227. */
284 status = ixgbe_reset_cs4227(hw);
285 if (status != IXGBE_SUCCESS) {
286 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
287 "CS4227 reset failed: %d", status);
291 /* Reset takes so long, temporarily release semaphore in case the
292 * other driver instance is waiting for the reset indication.
294 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
295 IXGBE_CS4227_RESET_PENDING);
296 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
298 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
299 if (status != IXGBE_SUCCESS) {
300 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
301 "semaphore failed with %d", status);
305 /* Record completion for next time. */
306 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
307 IXGBE_CS4227_RESET_COMPLETE);
310 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
311 msec_delay(hw->eeprom.semaphore_delay);
315 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
316 * @hw: pointer to hardware structure
318 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
320 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
322 if (hw->bus.lan_id) {
323 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
324 esdp |= IXGBE_ESDP_SDP1_DIR;
326 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
327 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
328 IXGBE_WRITE_FLUSH(hw);
332 * ixgbe_identify_phy_1g - Get 1g PHY type based on device id
333 * @hw: pointer to hardware structure
337 static s32 ixgbe_identify_phy_1g(struct ixgbe_hw *hw)
341 u32 val = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
343 hw->phy.addr = (val >> 3) & 0x1F;
344 val = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
345 hw->phy.addr, &phy_id_high);
346 if (val || phy_id_high == 0xFFFF) {
347 hw->phy.type = ixgbe_phy_sgmii;
351 val = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
352 hw->phy.addr, &phy_id_low);
356 hw->phy.id = (u32)phy_id_high << 16;
357 hw->phy.id |= phy_id_low & IXGBE_PHY_REVISION_MASK;
358 hw->phy.revision = (u32)phy_id_low & ~IXGBE_PHY_REVISION_MASK;
359 hw->phy.type = ixgbe_phy_m88;
365 * ixgbe_identify_phy_x550em - Get PHY type based on device id
366 * @hw: pointer to hardware structure
370 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
372 switch (hw->device_id) {
373 case IXGBE_DEV_ID_X550EM_A_SFP:
374 hw->phy.phy_semaphore_mask = IXGBE_GSSR_TOKEN_SM;
376 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
378 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
379 return ixgbe_identify_module_generic(hw);
380 case IXGBE_DEV_ID_X550EM_X_SFP:
381 /* set up for CS4227 usage */
382 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
383 ixgbe_setup_mux_ctl(hw);
384 ixgbe_check_cs4227(hw);
387 case IXGBE_DEV_ID_X550EM_A_SFP_N:
388 return ixgbe_identify_module_generic(hw);
390 case IXGBE_DEV_ID_X550EM_X_KX4:
391 hw->phy.type = ixgbe_phy_x550em_kx4;
393 case IXGBE_DEV_ID_X550EM_X_KR:
394 case IXGBE_DEV_ID_X550EM_A_KR:
395 case IXGBE_DEV_ID_X550EM_A_KR_L:
396 hw->phy.type = ixgbe_phy_x550em_kr;
398 case IXGBE_DEV_ID_X550EM_X_1G_T:
399 case IXGBE_DEV_ID_X550EM_X_10G_T:
400 case IXGBE_DEV_ID_X550EM_A_10G_T:
401 return ixgbe_identify_phy_generic(hw);
402 case IXGBE_DEV_ID_X550EM_A_1G_T:
403 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
404 return ixgbe_identify_phy_1g(hw);
408 return IXGBE_SUCCESS;
411 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
412 u32 device_type, u16 *phy_data)
414 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
415 return IXGBE_NOT_IMPLEMENTED;
418 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
419 u32 device_type, u16 phy_data)
421 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
422 return IXGBE_NOT_IMPLEMENTED;
426 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
427 * @hw: pointer to the hardware structure
428 * @addr: I2C bus address to read from
429 * @reg: I2C device register to read from
430 * @val: pointer to location to receive read value
432 * Returns an error code on error.
434 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
437 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
441 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
442 * @hw: pointer to the hardware structure
443 * @addr: I2C bus address to read from
444 * @reg: I2C device register to read from
445 * @val: pointer to location to receive read value
447 * Returns an error code on error.
450 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
453 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
457 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
458 * @hw: pointer to the hardware structure
459 * @addr: I2C bus address to write to
460 * @reg: I2C device register to write to
461 * @val: value to write
463 * Returns an error code on error.
465 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
466 u8 addr, u16 reg, u16 val)
468 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
472 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
473 * @hw: pointer to the hardware structure
474 * @addr: I2C bus address to write to
475 * @reg: I2C device register to write to
476 * @val: value to write
478 * Returns an error code on error.
481 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
482 u8 addr, u16 reg, u16 val)
484 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
488 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
489 * @hw: pointer to hardware structure
491 * Initialize the function pointers and for MAC type X550EM.
492 * Does not touch the hardware.
494 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
496 struct ixgbe_mac_info *mac = &hw->mac;
497 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
498 struct ixgbe_phy_info *phy = &hw->phy;
499 struct ixgbe_link_info *link = &hw->link;
502 DEBUGFUNC("ixgbe_init_ops_X550EM");
504 /* Similar to X550 so start there. */
505 ret_val = ixgbe_init_ops_X550(hw);
507 /* Since this function eventually calls
508 * ixgbe_init_ops_540 by design, we are setting
509 * the pointers to NULL explicitly here to overwrite
510 * the values being set in the x540 function.
512 /* Thermal sensor not supported in x550EM */
513 mac->ops.get_thermal_sensor_data = NULL;
514 mac->ops.init_thermal_sensor_thresh = NULL;
515 mac->thermal_sensor_enabled = false;
517 /* FCOE not supported in x550EM */
518 mac->ops.get_san_mac_addr = NULL;
519 mac->ops.set_san_mac_addr = NULL;
520 mac->ops.get_wwn_prefix = NULL;
521 mac->ops.get_fcoe_boot_status = NULL;
523 /* IPsec not supported in x550EM */
524 mac->ops.disable_sec_rx_path = NULL;
525 mac->ops.enable_sec_rx_path = NULL;
527 /* AUTOC register is not present in x550EM. */
528 mac->ops.prot_autoc_read = NULL;
529 mac->ops.prot_autoc_write = NULL;
531 /* X550EM bus type is internal*/
532 hw->bus.type = ixgbe_bus_type_internal;
533 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
535 if (hw->mac.type == ixgbe_mac_X550EM_x) {
536 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
537 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
538 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
539 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
540 link->ops.read_link = ixgbe_read_i2c_combined_generic;
541 link->ops.read_link_unlocked =
542 ixgbe_read_i2c_combined_generic_unlocked;
543 link->ops.write_link = ixgbe_write_i2c_combined_generic;
544 link->ops.write_link_unlocked =
545 ixgbe_write_i2c_combined_generic_unlocked;
546 link->addr = IXGBE_CS4227;
548 if (hw->mac.type == ixgbe_mac_X550EM_a) {
549 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
550 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
551 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
552 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
555 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
556 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
557 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
558 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
559 mac->ops.get_supported_physical_layer =
560 ixgbe_get_supported_physical_layer_X550em;
562 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
563 mac->ops.setup_fc = ixgbe_setup_fc_generic;
565 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
568 if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
569 mac->ops.setup_eee = NULL;
572 phy->ops.init = ixgbe_init_phy_ops_X550em;
573 phy->ops.identify = ixgbe_identify_phy_x550em;
574 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
575 phy->ops.set_phy_power = NULL;
579 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
580 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
581 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
582 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
583 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
584 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
585 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
586 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
592 * ixgbe_dmac_config_X550
593 * @hw: pointer to hardware structure
595 * Configure DMA coalescing. If enabling dmac, dmac is activated.
596 * When disabling dmac, dmac enable dmac bit is cleared.
598 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
600 u32 reg, high_pri_tc;
602 DEBUGFUNC("ixgbe_dmac_config_X550");
604 /* Disable DMA coalescing before configuring */
605 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
606 reg &= ~IXGBE_DMACR_DMAC_EN;
607 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
609 /* Disable DMA Coalescing if the watchdog timer is 0 */
610 if (!hw->mac.dmac_config.watchdog_timer)
613 ixgbe_dmac_config_tcs_X550(hw);
615 /* Configure DMA Coalescing Control Register */
616 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
618 /* Set the watchdog timer in units of 40.96 usec */
619 reg &= ~IXGBE_DMACR_DMACWT_MASK;
620 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
622 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
623 /* If fcoe is enabled, set high priority traffic class */
624 if (hw->mac.dmac_config.fcoe_en) {
625 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
626 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
627 IXGBE_DMACR_HIGH_PRI_TC_MASK);
629 reg |= IXGBE_DMACR_EN_MNG_IND;
631 /* Enable DMA coalescing after configuration */
632 reg |= IXGBE_DMACR_DMAC_EN;
633 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
636 return IXGBE_SUCCESS;
640 * ixgbe_dmac_config_tcs_X550
641 * @hw: pointer to hardware structure
643 * Configure DMA coalescing threshold per TC. The dmac enable bit must
644 * be cleared before configuring.
646 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
648 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
650 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
652 /* Configure DMA coalescing enabled */
653 switch (hw->mac.dmac_config.link_speed) {
654 case IXGBE_LINK_SPEED_100_FULL:
655 pb_headroom = IXGBE_DMACRXT_100M;
657 case IXGBE_LINK_SPEED_1GB_FULL:
658 pb_headroom = IXGBE_DMACRXT_1G;
661 pb_headroom = IXGBE_DMACRXT_10G;
665 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
666 IXGBE_MHADD_MFS_SHIFT) / 1024);
668 /* Set the per Rx packet buffer receive threshold */
669 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
670 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
671 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
673 if (tc < hw->mac.dmac_config.num_tcs) {
675 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
676 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
677 IXGBE_RXPBSIZE_SHIFT;
679 /* Calculate receive buffer threshold in kilobytes */
680 if (rx_pb_size > pb_headroom)
681 rx_pb_size = rx_pb_size - pb_headroom;
685 /* Minimum of MFS shall be set for DMCTH */
686 reg |= (rx_pb_size > maxframe_size_kb) ?
687 rx_pb_size : maxframe_size_kb;
689 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
691 return IXGBE_SUCCESS;
695 * ixgbe_dmac_update_tcs_X550
696 * @hw: pointer to hardware structure
698 * Disables dmac, updates per TC settings, and then enables dmac.
700 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
704 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
706 /* Disable DMA coalescing before configuring */
707 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
708 reg &= ~IXGBE_DMACR_DMAC_EN;
709 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
711 ixgbe_dmac_config_tcs_X550(hw);
713 /* Enable DMA coalescing after configuration */
714 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
715 reg |= IXGBE_DMACR_DMAC_EN;
716 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
718 return IXGBE_SUCCESS;
722 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
723 * @hw: pointer to hardware structure
725 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
726 * ixgbe_hw struct in order to set up EEPROM access.
728 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
730 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
734 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
736 if (eeprom->type == ixgbe_eeprom_uninitialized) {
737 eeprom->semaphore_delay = 10;
738 eeprom->type = ixgbe_flash;
740 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
741 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
742 IXGBE_EEC_SIZE_SHIFT);
743 eeprom->word_size = 1 << (eeprom_size +
744 IXGBE_EEPROM_WORD_SIZE_SHIFT);
746 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
747 eeprom->type, eeprom->word_size);
750 return IXGBE_SUCCESS;
754 * ixgbe_enable_eee_x550 - Enable EEE support
755 * @hw: pointer to hardware structure
757 static s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
763 if (hw->mac.type == ixgbe_mac_X550) {
764 /* Advertise EEE capability */
765 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
766 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
769 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
770 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
771 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
773 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
774 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
776 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
778 status = ixgbe_read_iosf_sb_reg_x550(hw,
779 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
780 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
781 if (status != IXGBE_SUCCESS)
784 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
785 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
787 /* Don't advertise FEC capability when EEE enabled. */
788 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
790 status = ixgbe_write_iosf_sb_reg_x550(hw,
791 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
792 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
793 if (status != IXGBE_SUCCESS)
797 return IXGBE_SUCCESS;
801 * ixgbe_disable_eee_x550 - Disable EEE support
802 * @hw: pointer to hardware structure
804 static s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
810 if (hw->mac.type == ixgbe_mac_X550) {
811 /* Disable advertised EEE capability */
812 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
813 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
816 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
817 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
818 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
820 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
821 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
823 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
824 status = ixgbe_read_iosf_sb_reg_x550(hw,
825 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
826 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
827 if (status != IXGBE_SUCCESS)
830 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
831 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
833 /* Advertise FEC capability when EEE is disabled. */
834 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
836 status = ixgbe_write_iosf_sb_reg_x550(hw,
837 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
838 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
839 if (status != IXGBE_SUCCESS)
843 return IXGBE_SUCCESS;
847 * ixgbe_setup_eee_X550 - Enable/disable EEE support
848 * @hw: pointer to the HW structure
849 * @enable_eee: boolean flag to enable EEE
851 * Enable/disable EEE based on enable_eee flag.
852 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
856 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
861 DEBUGFUNC("ixgbe_setup_eee_X550");
863 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
864 /* Enable or disable EEE per flag */
866 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
868 /* Not supported on first revision of X550EM_x. */
869 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
870 !(IXGBE_FUSES0_REV_MASK &
871 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
872 return IXGBE_SUCCESS;
873 status = ixgbe_enable_eee_x550(hw);
877 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
879 status = ixgbe_disable_eee_x550(hw);
883 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
885 return IXGBE_SUCCESS;
889 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
890 * @hw: pointer to hardware structure
891 * @enable: enable or disable source address pruning
892 * @pool: Rx pool to set source address pruning for
894 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
899 /* max rx pool is 63 */
903 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
904 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
907 pfflp |= (1ULL << pool);
909 pfflp &= ~(1ULL << pool);
911 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
912 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
916 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
917 * @hw: pointer to hardware structure
918 * @enable: enable or disable switch for Ethertype anti-spoofing
919 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
922 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
925 int vf_target_reg = vf >> 3;
926 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
929 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
931 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
933 pfvfspoof |= (1 << vf_target_shift);
935 pfvfspoof &= ~(1 << vf_target_shift);
937 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
941 * ixgbe_iosf_wait - Wait for IOSF command completion
942 * @hw: pointer to hardware structure
943 * @ctrl: pointer to location to receive final IOSF control value
945 * Returns failing status on timeout
947 * Note: ctrl can be NULL if the IOSF control register value is not needed
949 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
953 /* Check every 10 usec to see if the address cycle completed.
954 * The SB IOSF BUSY bit will clear when the operation is
957 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
958 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
959 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
965 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
966 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
967 return IXGBE_ERR_PHY;
970 return IXGBE_SUCCESS;
974 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
976 * @hw: pointer to hardware structure
977 * @reg_addr: 32 bit PHY register to write
978 * @device_type: 3 bit device type
979 * @data: Data to write to the register
981 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
982 u32 device_type, u32 data)
984 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
988 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
989 if (ret != IXGBE_SUCCESS)
992 ret = ixgbe_iosf_wait(hw, NULL);
993 if (ret != IXGBE_SUCCESS)
996 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
997 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
999 /* Write IOSF control register */
1000 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1002 /* Write IOSF data register */
1003 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1005 ret = ixgbe_iosf_wait(hw, &command);
1007 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1008 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1009 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1010 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1011 "Failed to write, error %x\n", error);
1012 ret = IXGBE_ERR_PHY;
1016 ixgbe_release_swfw_semaphore(hw, gssr);
1021 * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
1023 * @hw: pointer to hardware structure
1024 * @reg_addr: 32 bit PHY register to write
1025 * @device_type: 3 bit device type
1026 * @phy_data: Pointer to read data from the register
1028 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1029 u32 device_type, u32 *data)
1031 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1035 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1036 if (ret != IXGBE_SUCCESS)
1039 ret = ixgbe_iosf_wait(hw, NULL);
1040 if (ret != IXGBE_SUCCESS)
1043 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1044 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1046 /* Write IOSF control register */
1047 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1049 ret = ixgbe_iosf_wait(hw, &command);
1051 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1052 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1053 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1054 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1055 "Failed to read, error %x\n", error);
1056 ret = IXGBE_ERR_PHY;
1059 if (ret == IXGBE_SUCCESS)
1060 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1063 ixgbe_release_swfw_semaphore(hw, gssr);
1068 * ixgbe_get_phy_token - Get the token for shared phy access
1069 * @hw: Pointer to hardware structure
1072 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1074 struct ixgbe_hic_phy_token_req token_cmd;
1077 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1078 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1079 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1080 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1081 token_cmd.port_number = hw->bus.lan_id;
1082 token_cmd.command_type = FW_PHY_TOKEN_REQ;
1084 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1086 IXGBE_HI_COMMAND_TIMEOUT,
1090 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1091 return IXGBE_SUCCESS;
1092 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1093 return IXGBE_ERR_FW_RESP_INVALID;
1095 return IXGBE_ERR_TOKEN_RETRY;
1099 * ixgbe_put_phy_token - Put the token for shared phy access
1100 * @hw: Pointer to hardware structure
1103 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1105 struct ixgbe_hic_phy_token_req token_cmd;
1108 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1109 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1110 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1111 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1112 token_cmd.port_number = hw->bus.lan_id;
1113 token_cmd.command_type = FW_PHY_TOKEN_REL;
1115 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1117 IXGBE_HI_COMMAND_TIMEOUT,
1121 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1122 return IXGBE_SUCCESS;
1123 return IXGBE_ERR_FW_RESP_INVALID;
1127 * ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1128 * of the IOSF device
1129 * @hw: pointer to hardware structure
1130 * @reg_addr: 32 bit PHY register to write
1131 * @device_type: 3 bit device type
1132 * @data: Data to write to the register
1134 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1135 u32 device_type, u32 data)
1137 struct ixgbe_hic_internal_phy_req write_cmd;
1139 UNREFERENCED_1PARAMETER(device_type);
1141 memset(&write_cmd, 0, sizeof(write_cmd));
1142 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1143 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1144 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1145 write_cmd.port_number = hw->bus.lan_id;
1146 write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1147 write_cmd.address = (u16)reg_addr;
1148 write_cmd.write_data = data;
1150 status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1152 IXGBE_HI_COMMAND_TIMEOUT, false);
1158 * ixgbe_read_iosf_sb_reg_x550a - Writes a value to specified register
1159 * of the IOSF device.
1160 * @hw: pointer to hardware structure
1161 * @reg_addr: 32 bit PHY register to write
1162 * @device_type: 3 bit device type
1163 * @data: Pointer to read data from the register
1165 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1166 u32 device_type, u32 *data)
1168 struct ixgbe_hic_internal_phy_req read_cmd;
1170 UNREFERENCED_1PARAMETER(device_type);
1172 memset(&read_cmd, 0, sizeof(read_cmd));
1173 read_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1174 read_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1175 read_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1176 read_cmd.port_number = hw->bus.lan_id;
1177 read_cmd.command_type = FW_INT_PHY_REQ_READ;
1178 read_cmd.address = (u16)reg_addr;
1180 status = ixgbe_host_interface_command(hw, (u32 *)&read_cmd,
1182 IXGBE_HI_COMMAND_TIMEOUT, true);
1184 /* Extract the register value from the response. */
1185 *data = ((struct ixgbe_hic_internal_phy_resp *)&read_cmd)->read_data;
1191 * ixgbe_disable_mdd_X550
1192 * @hw: pointer to hardware structure
1194 * Disable malicious driver detection
1196 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1200 DEBUGFUNC("ixgbe_disable_mdd_X550");
1202 /* Disable MDD for TX DMA and interrupt */
1203 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1204 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1205 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1207 /* Disable MDD for RX and interrupt */
1208 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1209 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1210 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1214 * ixgbe_enable_mdd_X550
1215 * @hw: pointer to hardware structure
1217 * Enable malicious driver detection
1219 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1223 DEBUGFUNC("ixgbe_enable_mdd_X550");
1225 /* Enable MDD for TX DMA and interrupt */
1226 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1227 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1228 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1230 /* Enable MDD for RX and interrupt */
1231 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1232 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1233 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1237 * ixgbe_restore_mdd_vf_X550
1238 * @hw: pointer to hardware structure
1241 * Restore VF that was disabled during malicious driver detection event
1243 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1245 u32 idx, reg, num_qs, start_q, bitmask;
1247 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1249 /* Map VF to queues */
1250 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1251 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1252 case IXGBE_MRQC_VMDQRT8TCEN:
1253 num_qs = 8; /* 16 VFs / pools */
1254 bitmask = 0x000000FF;
1256 case IXGBE_MRQC_VMDQRSS32EN:
1257 case IXGBE_MRQC_VMDQRT4TCEN:
1258 num_qs = 4; /* 32 VFs / pools */
1259 bitmask = 0x0000000F;
1261 default: /* 64 VFs / pools */
1263 bitmask = 0x00000003;
1266 start_q = vf * num_qs;
1268 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1271 reg |= (bitmask << (start_q % 32));
1272 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1273 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1277 * ixgbe_mdd_event_X550
1278 * @hw: pointer to hardware structure
1279 * @vf_bitmap: vf bitmap of malicious vfs
1281 * Handle malicious driver detection event.
1283 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1286 u32 i, j, reg, q, shift, vf, idx;
1288 DEBUGFUNC("ixgbe_mdd_event_X550");
1290 /* figure out pool size for mapping to vf's */
1291 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1292 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1293 case IXGBE_MRQC_VMDQRT8TCEN:
1294 shift = 3; /* 16 VFs / pools */
1296 case IXGBE_MRQC_VMDQRSS32EN:
1297 case IXGBE_MRQC_VMDQRT4TCEN:
1298 shift = 2; /* 32 VFs / pools */
1301 shift = 1; /* 64 VFs / pools */
1305 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1306 for (i = 0; i < 4; i++) {
1307 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1308 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1313 /* Get malicious queue */
1314 for (j = 0; j < 32 && wqbr; j++) {
1316 if (!(wqbr & (1 << j)))
1319 /* Get queue from bitmask */
1322 /* Map queue to vf */
1325 /* Set vf bit in vf_bitmap */
1327 vf_bitmap[idx] |= (1 << (vf % 32));
1334 * ixgbe_get_media_type_X550em - Get media type
1335 * @hw: pointer to hardware structure
1337 * Returns the media type (fiber, copper, backplane)
1339 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1341 enum ixgbe_media_type media_type;
1343 DEBUGFUNC("ixgbe_get_media_type_X550em");
1345 /* Detect if there is a copper PHY attached. */
1346 switch (hw->device_id) {
1347 case IXGBE_DEV_ID_X550EM_X_KR:
1348 case IXGBE_DEV_ID_X550EM_X_KX4:
1349 case IXGBE_DEV_ID_X550EM_A_KR:
1350 case IXGBE_DEV_ID_X550EM_A_KR_L:
1351 media_type = ixgbe_media_type_backplane;
1353 case IXGBE_DEV_ID_X550EM_X_SFP:
1354 case IXGBE_DEV_ID_X550EM_A_SFP:
1355 case IXGBE_DEV_ID_X550EM_A_SFP_N:
1356 case IXGBE_DEV_ID_X550EM_A_QSFP:
1357 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1358 media_type = ixgbe_media_type_fiber;
1360 case IXGBE_DEV_ID_X550EM_X_1G_T:
1361 case IXGBE_DEV_ID_X550EM_X_10G_T:
1362 case IXGBE_DEV_ID_X550EM_A_10G_T:
1363 media_type = ixgbe_media_type_copper;
1365 case IXGBE_DEV_ID_X550EM_A_1G_T:
1366 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1367 media_type = ixgbe_media_type_sgmii;
1368 hw->phy.type = ixgbe_phy_sgmii;
1371 media_type = ixgbe_media_type_unknown;
1378 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1379 * @hw: pointer to hardware structure
1380 * @linear: true if SFP module is linear
1382 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1384 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1386 switch (hw->phy.sfp_type) {
1387 case ixgbe_sfp_type_not_present:
1388 return IXGBE_ERR_SFP_NOT_PRESENT;
1389 case ixgbe_sfp_type_da_cu_core0:
1390 case ixgbe_sfp_type_da_cu_core1:
1393 case ixgbe_sfp_type_srlr_core0:
1394 case ixgbe_sfp_type_srlr_core1:
1395 case ixgbe_sfp_type_da_act_lmt_core0:
1396 case ixgbe_sfp_type_da_act_lmt_core1:
1397 case ixgbe_sfp_type_1g_sx_core0:
1398 case ixgbe_sfp_type_1g_sx_core1:
1399 case ixgbe_sfp_type_1g_lx_core0:
1400 case ixgbe_sfp_type_1g_lx_core1:
1403 case ixgbe_sfp_type_unknown:
1404 case ixgbe_sfp_type_1g_cu_core0:
1405 case ixgbe_sfp_type_1g_cu_core1:
1407 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1410 return IXGBE_SUCCESS;
1414 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1415 * @hw: pointer to hardware structure
1417 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1419 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1424 DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1426 status = ixgbe_identify_module_generic(hw);
1428 if (status != IXGBE_SUCCESS)
1431 /* Check if SFP module is supported */
1432 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1438 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1439 * @hw: pointer to hardware structure
1441 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1446 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1448 /* Check if SFP module is supported */
1449 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1451 if (status != IXGBE_SUCCESS)
1454 ixgbe_init_mac_link_ops_X550em(hw);
1455 hw->phy.ops.reset = NULL;
1457 return IXGBE_SUCCESS;
1461 * ixgbe_setup_sgmii - Set up link for sgmii
1462 * @hw: pointer to hardware structure
1464 static s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1465 bool autoneg_wait_to_complete)
1467 struct ixgbe_mac_info *mac = &hw->mac;
1470 UNREFERENCED_2PARAMETER(speed, autoneg_wait_to_complete);
1472 rc = mac->ops.read_iosf_sb_reg(hw,
1473 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1474 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1478 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1479 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1480 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1481 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1482 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1483 rc = mac->ops.write_iosf_sb_reg(hw,
1484 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1485 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1489 rc = mac->ops.read_iosf_sb_reg(hw,
1490 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1491 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1495 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1496 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1497 rc = mac->ops.write_iosf_sb_reg(hw,
1498 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1499 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1503 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1504 rc = mac->ops.write_iosf_sb_reg(hw,
1505 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1506 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1512 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1513 * @hw: pointer to hardware structure
1515 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1517 struct ixgbe_mac_info *mac = &hw->mac;
1519 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1521 switch (hw->mac.ops.get_media_type(hw)) {
1522 case ixgbe_media_type_fiber:
1523 /* CS4227 does not support autoneg, so disable the laser control
1524 * functions for SFP+ fiber
1526 mac->ops.disable_tx_laser = NULL;
1527 mac->ops.enable_tx_laser = NULL;
1528 mac->ops.flap_tx_laser = NULL;
1529 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1530 mac->ops.set_rate_select_speed =
1531 ixgbe_set_soft_rate_select_speed;
1532 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N)
1533 mac->ops.setup_mac_link =
1534 ixgbe_setup_mac_link_sfp_x550a;
1536 mac->ops.setup_mac_link =
1537 ixgbe_setup_mac_link_sfp_x550em;
1539 case ixgbe_media_type_copper:
1540 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1541 mac->ops.check_link = ixgbe_check_link_t_X550em;
1543 case ixgbe_media_type_backplane:
1545 case ixgbe_media_type_sgmii:
1546 mac->ops.setup_link = ixgbe_setup_sgmii;
1554 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1555 * @hw: pointer to hardware structure
1556 * @speed: pointer to link speed
1557 * @autoneg: true when autoneg or autotry is enabled
1559 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1560 ixgbe_link_speed *speed,
1563 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1566 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1568 /* CS4227 SFP must not enable auto-negotiation */
1571 /* Check if 1G SFP module. */
1572 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1573 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1574 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1575 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1576 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1577 return IXGBE_SUCCESS;
1580 /* Link capabilities are based on SFP */
1581 if (hw->phy.multispeed_fiber)
1582 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1583 IXGBE_LINK_SPEED_1GB_FULL;
1585 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1587 switch (hw->phy.type) {
1589 *speed = IXGBE_LINK_SPEED_100_FULL |
1590 IXGBE_LINK_SPEED_1GB_FULL;
1592 case ixgbe_phy_sgmii:
1593 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1596 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1597 IXGBE_LINK_SPEED_1GB_FULL;
1603 return IXGBE_SUCCESS;
1607 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1608 * @hw: pointer to hardware structure
1609 * @lsc: pointer to boolean flag which indicates whether external Base T
1610 * PHY interrupt is lsc
1612 * Determime if external Base T PHY interrupt cause is high temperature
1613 * failure alarm or link status change.
1615 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1616 * failure alarm, else return PHY access status.
1618 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1625 /* Vendor alarm triggered */
1626 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1627 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1630 if (status != IXGBE_SUCCESS ||
1631 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1634 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1635 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1636 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1639 if (status != IXGBE_SUCCESS ||
1640 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1641 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1644 /* Global alarm triggered */
1645 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1646 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1649 if (status != IXGBE_SUCCESS)
1652 /* If high temperature failure, then return over temp error and exit */
1653 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1654 /* power down the PHY in case the PHY FW didn't already */
1655 ixgbe_set_copper_phy_power(hw, false);
1656 return IXGBE_ERR_OVERTEMP;
1657 } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1658 /* device fault alarm triggered */
1659 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1660 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1663 if (status != IXGBE_SUCCESS)
1666 /* if device fault was due to high temp alarm handle and exit */
1667 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1668 /* power down the PHY in case the PHY FW didn't */
1669 ixgbe_set_copper_phy_power(hw, false);
1670 return IXGBE_ERR_OVERTEMP;
1674 /* Vendor alarm 2 triggered */
1675 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1676 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1678 if (status != IXGBE_SUCCESS ||
1679 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1682 /* link connect/disconnect event occurred */
1683 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1684 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1686 if (status != IXGBE_SUCCESS)
1690 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1693 return IXGBE_SUCCESS;
1697 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1698 * @hw: pointer to hardware structure
1700 * Enable link status change and temperature failure alarm for the external
1703 * Returns PHY access status
1705 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1711 /* Clear interrupt flags */
1712 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1714 /* Enable link status change alarm */
1715 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1716 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1718 if (status != IXGBE_SUCCESS)
1721 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1723 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1724 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1726 if (status != IXGBE_SUCCESS)
1729 /* Enable high temperature failure and global fault alarms */
1730 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1731 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1734 if (status != IXGBE_SUCCESS)
1737 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
1738 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
1740 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1741 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1744 if (status != IXGBE_SUCCESS)
1747 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1748 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1749 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1752 if (status != IXGBE_SUCCESS)
1755 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1756 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1758 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1759 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1762 if (status != IXGBE_SUCCESS)
1765 /* Enable chip-wide vendor alarm */
1766 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1767 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1770 if (status != IXGBE_SUCCESS)
1773 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1775 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1776 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1783 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1784 * @hw: pointer to hardware structure
1785 * @speed: link speed
1787 * Configures the integrated KR PHY.
1789 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1790 ixgbe_link_speed speed)
1795 status = ixgbe_read_iosf_sb_reg_x550(hw,
1796 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1797 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1801 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1802 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1803 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1805 /* Advertise 10G support. */
1806 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1807 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1809 /* Advertise 1G support. */
1810 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1811 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1813 /* Restart auto-negotiation. */
1814 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1815 status = ixgbe_write_iosf_sb_reg_x550(hw,
1816 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1817 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1823 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1824 * @hw: pointer to hardware structure
1826 * Initialize any function pointers that were not able to be
1827 * set during init_shared_code because the PHY/SFP type was
1828 * not known. Perform the SFP init if necessary.
1830 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1832 struct ixgbe_phy_info *phy = &hw->phy;
1835 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1837 hw->mac.ops.set_lan_id(hw);
1839 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1840 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1841 ixgbe_setup_mux_ctl(hw);
1843 /* Save NW management interface connected on board. This is used
1844 * to determine internal PHY mode.
1846 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1847 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
1850 /* Identify the PHY or SFP module */
1851 ret_val = phy->ops.identify(hw);
1852 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1855 /* Setup function pointers based on detected hardware */
1856 ixgbe_init_mac_link_ops_X550em(hw);
1857 if (phy->sfp_type != ixgbe_sfp_type_unknown)
1858 phy->ops.reset = NULL;
1860 /* Set functions pointers based on phy type */
1861 switch (hw->phy.type) {
1862 case ixgbe_phy_x550em_kx4:
1863 phy->ops.setup_link = NULL;
1864 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1865 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1867 case ixgbe_phy_x550em_kr:
1868 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1869 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1870 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1872 case ixgbe_phy_x550em_ext_t:
1873 /* Save NW management interface connected on board. This is used
1874 * to determine internal PHY mode
1876 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1878 /* If internal link mode is XFI, then setup iXFI internal link,
1879 * else setup KR now.
1881 phy->ops.setup_internal_link =
1882 ixgbe_setup_internal_phy_t_x550em;
1884 /* setup SW LPLU only for first revision of X550EM_x */
1885 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
1886 !(IXGBE_FUSES0_REV_MASK &
1887 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
1888 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1890 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1891 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1893 case ixgbe_phy_sgmii:
1894 phy->ops.setup_link = NULL;
1905 * ixgbe_set_mdio_speed - Set MDIO clock speed
1906 * @hw: pointer to hardware structure
1908 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
1912 switch (hw->device_id) {
1913 case IXGBE_DEV_ID_X550EM_X_10G_T:
1914 case IXGBE_DEV_ID_X550EM_A_1G_T:
1915 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1916 case IXGBE_DEV_ID_X550EM_A_10G_T:
1917 case IXGBE_DEV_ID_X550EM_A_SFP:
1918 case IXGBE_DEV_ID_X550EM_A_QSFP:
1919 /* Config MDIO clock speed before the first MDIO PHY access */
1920 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1921 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
1922 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1930 * ixgbe_reset_hw_X550em - Perform hardware reset
1931 * @hw: pointer to hardware structure
1933 * Resets the hardware by resetting the transmit and receive units, masks
1934 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1937 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1939 ixgbe_link_speed link_speed;
1943 bool link_up = false;
1945 DEBUGFUNC("ixgbe_reset_hw_X550em");
1947 /* Call adapter stop to disable Tx/Rx and clear interrupts */
1948 status = hw->mac.ops.stop_adapter(hw);
1949 if (status != IXGBE_SUCCESS)
1952 /* flush pending Tx transactions */
1953 ixgbe_clear_tx_pending(hw);
1955 ixgbe_set_mdio_speed(hw);
1957 /* PHY ops must be identified and initialized prior to reset */
1958 status = hw->phy.ops.init(hw);
1960 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1963 /* start the external PHY */
1964 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1965 status = ixgbe_init_ext_t_x550em(hw);
1970 /* Setup SFP module if there is one present. */
1971 if (hw->phy.sfp_setup_needed) {
1972 status = hw->mac.ops.setup_sfp(hw);
1973 hw->phy.sfp_setup_needed = false;
1976 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1980 if (!hw->phy.reset_disable && hw->phy.ops.reset)
1981 hw->phy.ops.reset(hw);
1984 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
1985 * If link reset is used when link is up, it might reset the PHY when
1986 * mng is using it. If link is down or the flag to force full link
1987 * reset is set, then perform link reset.
1989 ctrl = IXGBE_CTRL_LNK_RST;
1990 if (!hw->force_full_reset) {
1991 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1993 ctrl = IXGBE_CTRL_RST;
1996 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1997 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1998 IXGBE_WRITE_FLUSH(hw);
2000 /* Poll for reset bit to self-clear meaning reset is complete */
2001 for (i = 0; i < 10; i++) {
2003 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2004 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2008 if (ctrl & IXGBE_CTRL_RST_MASK) {
2009 status = IXGBE_ERR_RESET_FAILED;
2010 DEBUGOUT("Reset polling failed to complete.\n");
2015 /* Double resets are required for recovery from certain error
2016 * conditions. Between resets, it is necessary to stall to
2017 * allow time for any pending HW events to complete.
2019 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2020 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2024 /* Store the permanent mac address */
2025 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2027 /* Store MAC address from RAR0, clear receive address registers, and
2028 * clear the multicast table. Also reset num_rar_entries to 128,
2029 * since we modify this value when programming the SAN MAC address.
2031 hw->mac.num_rar_entries = 128;
2032 hw->mac.ops.init_rx_addrs(hw);
2034 ixgbe_set_mdio_speed(hw);
2036 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2037 ixgbe_setup_mux_ctl(hw);
2043 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2044 * @hw: pointer to hardware structure
2046 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2051 status = hw->phy.ops.read_reg(hw,
2052 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2053 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2056 if (status != IXGBE_SUCCESS)
2059 /* If PHY FW reset completed bit is set then this is the first
2060 * SW instance after a power on so the PHY FW must be un-stalled.
2062 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2063 status = hw->phy.ops.read_reg(hw,
2064 IXGBE_MDIO_GLOBAL_RES_PR_10,
2065 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2068 if (status != IXGBE_SUCCESS)
2071 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2073 status = hw->phy.ops.write_reg(hw,
2074 IXGBE_MDIO_GLOBAL_RES_PR_10,
2075 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2078 if (status != IXGBE_SUCCESS)
2086 * ixgbe_setup_kr_x550em - Configure the KR PHY.
2087 * @hw: pointer to hardware structure
2089 * Configures the integrated KR PHY.
2091 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2093 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2097 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2098 * @hw: pointer to hardware structure
2100 * Configure the external PHY and the integrated KR PHY for SFP support.
2102 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2103 ixgbe_link_speed speed,
2104 bool autoneg_wait_to_complete)
2107 u16 reg_slice, reg_val;
2108 bool setup_linear = false;
2109 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2111 /* Check if SFP module is supported and linear */
2112 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2114 /* If no SFP module present, then return success. Return success since
2115 * there is no reason to configure CS4227 and SFP not present error is
2116 * not excepted in the setup MAC link flow.
2118 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2119 return IXGBE_SUCCESS;
2121 if (ret_val != IXGBE_SUCCESS)
2124 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2125 /* Configure CS4227 LINE side to 10G SR. */
2126 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
2127 (hw->bus.lan_id << 12);
2128 reg_val = IXGBE_CS4227_SPEED_10G;
2129 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2132 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2133 (hw->bus.lan_id << 12);
2134 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2135 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2138 /* Configure CS4227 for HOST connection rate then type. */
2139 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
2140 (hw->bus.lan_id << 12);
2141 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
2142 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
2143 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2146 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
2147 (hw->bus.lan_id << 12);
2149 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2151 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2152 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2155 /* Setup XFI internal link. */
2156 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2158 /* Configure internal PHY for KR/KX. */
2159 ixgbe_setup_kr_speed_x550em(hw, speed);
2161 /* Configure CS4227 LINE side to proper mode. */
2162 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2163 (hw->bus.lan_id << 12);
2165 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2167 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2168 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2175 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2176 * @hw: pointer to hardware structure
2178 * Configure the the integrated PHY for SFP support.
2180 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2181 ixgbe_link_speed speed,
2182 bool autoneg_wait_to_complete)
2186 bool setup_linear = false;
2188 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2190 /* Check if SFP module is supported and linear */
2191 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2193 /* If no SFP module present, then return success. Return success since
2194 * SFP not present error is not excepted in the setup MAC link flow.
2196 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2197 return IXGBE_SUCCESS;
2199 if (ret_val != IXGBE_SUCCESS)
2202 /* Configure internal PHY for native SFI */
2203 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2204 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2205 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2207 if (ret_val != IXGBE_SUCCESS)
2211 reg_val &= ~IXGBE_KRM_AN_CNTL_8_LIMITING;
2212 reg_val |= IXGBE_KRM_AN_CNTL_8_LINEAR;
2214 reg_val |= IXGBE_KRM_AN_CNTL_8_LIMITING;
2215 reg_val &= ~IXGBE_KRM_AN_CNTL_8_LINEAR;
2218 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2219 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2220 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2222 if (ret_val != IXGBE_SUCCESS)
2225 /* Setup XFI/SFI internal link. */
2226 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2232 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2233 * @hw: pointer to hardware structure
2235 * iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2237 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2242 /* Disable training protocol FSM. */
2243 status = ixgbe_read_iosf_sb_reg_x550(hw,
2244 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2245 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2246 if (status != IXGBE_SUCCESS)
2248 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2249 status = ixgbe_write_iosf_sb_reg_x550(hw,
2250 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2251 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2252 if (status != IXGBE_SUCCESS)
2255 /* Disable Flex from training TXFFE. */
2256 status = ixgbe_read_iosf_sb_reg_x550(hw,
2257 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2258 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2259 if (status != IXGBE_SUCCESS)
2261 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2262 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2263 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2264 status = ixgbe_write_iosf_sb_reg_x550(hw,
2265 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2266 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2267 if (status != IXGBE_SUCCESS)
2269 status = ixgbe_read_iosf_sb_reg_x550(hw,
2270 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2271 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2272 if (status != IXGBE_SUCCESS)
2274 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2275 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2276 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2277 status = ixgbe_write_iosf_sb_reg_x550(hw,
2278 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2279 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2280 if (status != IXGBE_SUCCESS)
2283 /* Enable override for coefficients. */
2284 status = ixgbe_read_iosf_sb_reg_x550(hw,
2285 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2286 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2287 if (status != IXGBE_SUCCESS)
2289 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2290 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2291 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2292 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2293 status = ixgbe_write_iosf_sb_reg_x550(hw,
2294 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2295 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2300 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2301 * @hw: pointer to hardware structure
2302 * @speed: the link speed to force
2304 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
2305 * internal and external PHY at a specific speed, without autonegotiation.
2307 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2312 /* Disable AN and force speed to 10G Serial. */
2313 status = ixgbe_read_iosf_sb_reg_x550(hw,
2314 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2315 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2316 if (status != IXGBE_SUCCESS)
2319 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2320 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2322 /* Select forced link speed for internal PHY. */
2324 case IXGBE_LINK_SPEED_10GB_FULL:
2325 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2327 case IXGBE_LINK_SPEED_1GB_FULL:
2328 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2331 /* Other link speeds are not supported by internal KR PHY. */
2332 return IXGBE_ERR_LINK_SETUP;
2335 status = ixgbe_write_iosf_sb_reg_x550(hw,
2336 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2337 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2338 if (status != IXGBE_SUCCESS)
2341 /* Additional configuration needed for x550em_x */
2342 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2343 status = ixgbe_setup_ixfi_x550em_x(hw);
2344 if (status != IXGBE_SUCCESS)
2348 /* Toggle port SW reset by AN reset. */
2349 status = ixgbe_read_iosf_sb_reg_x550(hw,
2350 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2351 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2352 if (status != IXGBE_SUCCESS)
2354 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2355 status = ixgbe_write_iosf_sb_reg_x550(hw,
2356 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2357 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2363 * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2364 * @hw: address of hardware structure
2365 * @link_up: address of boolean to indicate link status
2367 * Returns error code if unable to get link status.
2369 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2376 /* read this twice back to back to indicate current status */
2377 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2378 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2380 if (ret != IXGBE_SUCCESS)
2383 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2384 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2386 if (ret != IXGBE_SUCCESS)
2389 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2391 return IXGBE_SUCCESS;
2395 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2396 * @hw: point to hardware structure
2398 * Configures the link between the integrated KR PHY and the external X557 PHY
2399 * The driver will call this function when it gets a link status change
2400 * interrupt from the X557 PHY. This function configures the link speed
2401 * between the PHYs to match the link speed of the BASE-T link.
2403 * A return of a non-zero value indicates an error, and the base driver should
2404 * not report link up.
2406 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2408 ixgbe_link_speed force_speed;
2413 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2414 return IXGBE_ERR_CONFIG;
2416 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2417 /* If link is down, there is no setup necessary so return */
2418 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2419 if (status != IXGBE_SUCCESS)
2423 return IXGBE_SUCCESS;
2425 status = hw->phy.ops.read_reg(hw,
2426 IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2427 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2429 if (status != IXGBE_SUCCESS)
2432 /* If link is still down - no setup is required so return */
2433 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2434 if (status != IXGBE_SUCCESS)
2437 return IXGBE_SUCCESS;
2439 /* clear everything but the speed and duplex bits */
2440 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2443 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2444 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2446 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2447 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2450 /* Internal PHY does not support anything else */
2451 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2454 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2456 speed = IXGBE_LINK_SPEED_10GB_FULL |
2457 IXGBE_LINK_SPEED_1GB_FULL;
2458 return ixgbe_setup_kr_speed_x550em(hw, speed);
2463 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
2464 * @hw: pointer to hardware structure
2466 * Configures the integrated KR PHY to use internal loopback mode.
2468 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
2473 /* Disable AN and force speed to 10G Serial. */
2474 status = ixgbe_read_iosf_sb_reg_x550(hw,
2475 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2476 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2477 if (status != IXGBE_SUCCESS)
2479 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2480 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2481 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2482 status = ixgbe_write_iosf_sb_reg_x550(hw,
2483 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2484 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2485 if (status != IXGBE_SUCCESS)
2488 /* Set near-end loopback clocks. */
2489 status = ixgbe_read_iosf_sb_reg_x550(hw,
2490 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2491 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2492 if (status != IXGBE_SUCCESS)
2494 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2495 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2496 status = ixgbe_write_iosf_sb_reg_x550(hw,
2497 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2498 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2499 if (status != IXGBE_SUCCESS)
2502 /* Set loopback enable. */
2503 status = ixgbe_read_iosf_sb_reg_x550(hw,
2504 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2505 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2506 if (status != IXGBE_SUCCESS)
2508 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2509 status = ixgbe_write_iosf_sb_reg_x550(hw,
2510 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2511 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2512 if (status != IXGBE_SUCCESS)
2515 /* Training bypass. */
2516 status = ixgbe_read_iosf_sb_reg_x550(hw,
2517 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2518 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2519 if (status != IXGBE_SUCCESS)
2521 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2522 status = ixgbe_write_iosf_sb_reg_x550(hw,
2523 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2524 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2530 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2531 * assuming that the semaphore is already obtained.
2532 * @hw: pointer to hardware structure
2533 * @offset: offset of word in the EEPROM to read
2534 * @data: word read from the EEPROM
2536 * Reads a 16 bit word from the EEPROM using the hostif.
2538 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2542 struct ixgbe_hic_read_shadow_ram buffer;
2544 DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2545 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2546 buffer.hdr.req.buf_lenh = 0;
2547 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2548 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2550 /* convert offset from words to bytes */
2551 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2553 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2555 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2557 IXGBE_HI_COMMAND_TIMEOUT, false);
2562 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2563 FW_NVM_DATA_OFFSET);
2569 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2570 * @hw: pointer to hardware structure
2571 * @offset: offset of word in the EEPROM to read
2572 * @data: word read from the EEPROM
2574 * Reads a 16 bit word from the EEPROM using the hostif.
2576 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2579 s32 status = IXGBE_SUCCESS;
2581 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2583 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2585 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2586 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2588 status = IXGBE_ERR_SWFW_SYNC;
2595 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2596 * @hw: pointer to hardware structure
2597 * @offset: offset of word in the EEPROM to read
2598 * @words: number of words
2599 * @data: word(s) read from the EEPROM
2601 * Reads a 16 bit word(s) from the EEPROM using the hostif.
2603 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2604 u16 offset, u16 words, u16 *data)
2606 struct ixgbe_hic_read_shadow_ram buffer;
2607 u32 current_word = 0;
2612 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2614 /* Take semaphore for the entire operation. */
2615 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2617 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2621 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2622 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2624 words_to_read = words;
2626 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2627 buffer.hdr.req.buf_lenh = 0;
2628 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2629 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2631 /* convert offset from words to bytes */
2632 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2633 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2635 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2637 IXGBE_HI_COMMAND_TIMEOUT,
2641 DEBUGOUT("Host interface command failed\n");
2645 for (i = 0; i < words_to_read; i++) {
2646 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
2648 u32 value = IXGBE_READ_REG(hw, reg);
2650 data[current_word] = (u16)(value & 0xffff);
2653 if (i < words_to_read) {
2655 data[current_word] = (u16)(value & 0xffff);
2659 words -= words_to_read;
2663 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2668 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2669 * @hw: pointer to hardware structure
2670 * @offset: offset of word in the EEPROM to write
2671 * @data: word write to the EEPROM
2673 * Write a 16 bit word to the EEPROM using the hostif.
2675 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2679 struct ixgbe_hic_write_shadow_ram buffer;
2681 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
2683 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
2684 buffer.hdr.req.buf_lenh = 0;
2685 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
2686 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2689 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2691 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2693 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2695 IXGBE_HI_COMMAND_TIMEOUT, false);
2701 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2702 * @hw: pointer to hardware structure
2703 * @offset: offset of word in the EEPROM to write
2704 * @data: word write to the EEPROM
2706 * Write a 16 bit word to the EEPROM using the hostif.
2708 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2711 s32 status = IXGBE_SUCCESS;
2713 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2715 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2717 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2718 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2720 DEBUGOUT("write ee hostif failed to get semaphore");
2721 status = IXGBE_ERR_SWFW_SYNC;
2728 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2729 * @hw: pointer to hardware structure
2730 * @offset: offset of word in the EEPROM to write
2731 * @words: number of words
2732 * @data: word(s) write to the EEPROM
2734 * Write a 16 bit word(s) to the EEPROM using the hostif.
2736 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2737 u16 offset, u16 words, u16 *data)
2739 s32 status = IXGBE_SUCCESS;
2742 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2744 /* Take semaphore for the entire operation. */
2745 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2746 if (status != IXGBE_SUCCESS) {
2747 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2751 for (i = 0; i < words; i++) {
2752 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2755 if (status != IXGBE_SUCCESS) {
2756 DEBUGOUT("Eeprom buffered write failed\n");
2761 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2768 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2769 * @hw: pointer to hardware structure
2770 * @ptr: pointer offset in eeprom
2771 * @size: size of section pointed by ptr, if 0 first word will be used as size
2772 * @csum: address of checksum to update
2774 * Returns error status for any failure
2776 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2777 u16 size, u16 *csum, u16 *buffer,
2782 u16 length, bufsz, i, start;
2785 bufsz = sizeof(buf) / sizeof(buf[0]);
2787 /* Read a chunk at the pointer location */
2789 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2791 DEBUGOUT("Failed to read EEPROM image\n");
2796 if (buffer_size < ptr)
2797 return IXGBE_ERR_PARAM;
2798 local_buffer = &buffer[ptr];
2806 length = local_buffer[0];
2808 /* Skip pointer section if length is invalid. */
2809 if (length == 0xFFFF || length == 0 ||
2810 (ptr + length) >= hw->eeprom.word_size)
2811 return IXGBE_SUCCESS;
2814 if (buffer && ((u32)start + (u32)length > buffer_size))
2815 return IXGBE_ERR_PARAM;
2817 for (i = start; length; i++, length--) {
2818 if (i == bufsz && !buffer) {
2824 /* Read a chunk at the pointer location */
2825 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2828 DEBUGOUT("Failed to read EEPROM image\n");
2832 *csum += local_buffer[i];
2834 return IXGBE_SUCCESS;
2838 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2839 * @hw: pointer to hardware structure
2840 * @buffer: pointer to buffer containing calculated checksum
2841 * @buffer_size: size of buffer
2843 * Returns a negative error code on error, or the 16-bit checksum
2845 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2847 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2851 u16 pointer, i, size;
2853 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2855 hw->eeprom.ops.init_params(hw);
2858 /* Read pointer area */
2859 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2860 IXGBE_EEPROM_LAST_WORD + 1,
2863 DEBUGOUT("Failed to read EEPROM image\n");
2866 local_buffer = eeprom_ptrs;
2868 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2869 return IXGBE_ERR_PARAM;
2870 local_buffer = buffer;
2874 * For X550 hardware include 0x0-0x41 in the checksum, skip the
2875 * checksum word itself
2877 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2878 if (i != IXGBE_EEPROM_CHECKSUM)
2879 checksum += local_buffer[i];
2882 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
2883 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2885 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2886 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2889 pointer = local_buffer[i];
2891 /* Skip pointer section if the pointer is invalid. */
2892 if (pointer == 0xFFFF || pointer == 0 ||
2893 pointer >= hw->eeprom.word_size)
2897 case IXGBE_PCIE_GENERAL_PTR:
2898 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2900 case IXGBE_PCIE_CONFIG0_PTR:
2901 case IXGBE_PCIE_CONFIG1_PTR:
2902 size = IXGBE_PCIE_CONFIG_SIZE;
2909 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2910 buffer, buffer_size);
2915 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2917 return (s32)checksum;
2921 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2922 * @hw: pointer to hardware structure
2924 * Returns a negative error code on error, or the 16-bit checksum
2926 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2928 return ixgbe_calc_checksum_X550(hw, NULL, 0);
2932 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2933 * @hw: pointer to hardware structure
2934 * @checksum_val: calculated checksum
2936 * Performs checksum calculation and validates the EEPROM checksum. If the
2937 * caller does not need checksum_val, the value can be NULL.
2939 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2943 u16 read_checksum = 0;
2945 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2947 /* Read the first word from the EEPROM. If this times out or fails, do
2948 * not continue or we could be in for a very long wait while every
2951 status = hw->eeprom.ops.read(hw, 0, &checksum);
2953 DEBUGOUT("EEPROM read failed\n");
2957 status = hw->eeprom.ops.calc_checksum(hw);
2961 checksum = (u16)(status & 0xffff);
2963 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2968 /* Verify read checksum from EEPROM is the same as
2969 * calculated checksum
2971 if (read_checksum != checksum) {
2972 status = IXGBE_ERR_EEPROM_CHECKSUM;
2973 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2974 "Invalid EEPROM checksum");
2977 /* If the user cares, return the calculated checksum */
2979 *checksum_val = checksum;
2985 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2986 * @hw: pointer to hardware structure
2988 * After writing EEPROM to shadow RAM using EEWR register, software calculates
2989 * checksum and updates the EEPROM and instructs the hardware to update
2992 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2997 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2999 /* Read the first word from the EEPROM. If this times out or fails, do
3000 * not continue or we could be in for a very long wait while every
3003 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3005 DEBUGOUT("EEPROM read failed\n");
3009 status = ixgbe_calc_eeprom_checksum_X550(hw);
3013 checksum = (u16)(status & 0xffff);
3015 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3020 status = ixgbe_update_flash_X550(hw);
3026 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3027 * @hw: pointer to hardware structure
3029 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3031 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3033 s32 status = IXGBE_SUCCESS;
3034 union ixgbe_hic_hdr2 buffer;
3036 DEBUGFUNC("ixgbe_update_flash_X550");
3038 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3039 buffer.req.buf_lenh = 0;
3040 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3041 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3043 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3045 IXGBE_HI_COMMAND_TIMEOUT, false);
3051 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3052 * @hw: pointer to hardware structure
3054 * Determines physical layer capabilities of the current configuration.
3056 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3058 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3059 u16 ext_ability = 0;
3061 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3063 hw->phy.ops.identify(hw);
3065 switch (hw->phy.type) {
3066 case ixgbe_phy_x550em_kr:
3067 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3068 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3070 case ixgbe_phy_x550em_kx4:
3071 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3072 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3074 case ixgbe_phy_x550em_ext_t:
3075 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3076 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3078 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3079 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3080 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3081 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3087 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3088 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3090 return physical_layer;
3094 * ixgbe_get_bus_info_x550em - Set PCI bus info
3095 * @hw: pointer to hardware structure
3097 * Sets bus link width and speed to unknown because X550em is
3100 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3103 DEBUGFUNC("ixgbe_get_bus_info_x550em");
3105 hw->bus.width = ixgbe_bus_width_unknown;
3106 hw->bus.speed = ixgbe_bus_speed_unknown;
3108 hw->mac.ops.set_lan_id(hw);
3110 return IXGBE_SUCCESS;
3114 * ixgbe_disable_rx_x550 - Disable RX unit
3116 * Enables the Rx DMA unit for x550
3118 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3120 u32 rxctrl, pfdtxgswc;
3122 struct ixgbe_hic_disable_rxen fw_cmd;
3124 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3126 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3127 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3128 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3129 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3130 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3131 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3132 hw->mac.set_lben = true;
3134 hw->mac.set_lben = false;
3137 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3138 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3139 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3140 fw_cmd.port_number = (u8)hw->bus.lan_id;
3142 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3143 sizeof(struct ixgbe_hic_disable_rxen),
3144 IXGBE_HI_COMMAND_TIMEOUT, true);
3146 /* If we fail - disable RX using register write */
3148 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3149 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3150 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3151 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3158 * ixgbe_enter_lplu_x550em - Transition to low power states
3159 * @hw: pointer to hardware structure
3161 * Configures Low Power Link Up on transition to low power states
3162 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3163 * X557 PHY immediately prior to entering LPLU.
3165 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3167 u16 an_10g_cntl_reg, autoneg_reg, speed;
3169 ixgbe_link_speed lcd_speed;
3173 /* SW LPLU not required on later HW revisions. */
3174 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3175 (IXGBE_FUSES0_REV_MASK &
3176 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3177 return IXGBE_SUCCESS;
3179 /* If blocked by MNG FW, then don't restart AN */
3180 if (ixgbe_check_reset_blocked(hw))
3181 return IXGBE_SUCCESS;
3183 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3184 if (status != IXGBE_SUCCESS)
3187 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3189 if (status != IXGBE_SUCCESS)
3192 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3193 * disabled, then force link down by entering low power mode.
3195 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3196 !(hw->wol_enabled || ixgbe_mng_present(hw)))
3197 return ixgbe_set_copper_phy_power(hw, FALSE);
3200 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3202 if (status != IXGBE_SUCCESS)
3205 /* If no valid LCD link speed, then force link down and exit. */
3206 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3207 return ixgbe_set_copper_phy_power(hw, FALSE);
3209 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3210 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3213 if (status != IXGBE_SUCCESS)
3216 /* If no link now, speed is invalid so take link down */
3217 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3218 if (status != IXGBE_SUCCESS)
3219 return ixgbe_set_copper_phy_power(hw, false);
3221 /* clear everything but the speed bits */
3222 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3224 /* If current speed is already LCD, then exit. */
3225 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3226 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3227 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3228 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3231 /* Clear AN completed indication */
3232 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3233 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3236 if (status != IXGBE_SUCCESS)
3239 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3240 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3243 if (status != IXGBE_SUCCESS)
3246 status = hw->phy.ops.read_reg(hw,
3247 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3248 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3251 if (status != IXGBE_SUCCESS)
3254 save_autoneg = hw->phy.autoneg_advertised;
3256 /* Setup link at least common link speed */
3257 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3259 /* restore autoneg from before setting lplu speed */
3260 hw->phy.autoneg_advertised = save_autoneg;
3266 * ixgbe_get_lcd_x550em - Determine lowest common denominator
3267 * @hw: pointer to hardware structure
3268 * @lcd_speed: pointer to lowest common link speed
3270 * Determine lowest common link speed with link partner.
3272 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3276 u16 word = hw->eeprom.ctrl_word_3;
3278 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3280 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3281 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3284 if (status != IXGBE_SUCCESS)
3287 /* If link partner advertised 1G, return 1G */
3288 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3289 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3293 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3294 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3295 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3298 /* Link partner not capable of lower speeds, return 10G */
3299 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3304 * ixgbe_setup_fc_X550em - Set up flow control
3305 * @hw: pointer to hardware structure
3307 * Called at init time to set up flow control.
3309 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3311 s32 ret_val = IXGBE_SUCCESS;
3312 u32 pause, asm_dir, reg_val;
3314 DEBUGFUNC("ixgbe_setup_fc_X550em");
3316 /* Validate the requested mode */
3317 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3318 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3319 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3320 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3324 /* 10gig parts do not have a word in the EEPROM to determine the
3325 * default flow control setting, so we explicitly set it to full.
3327 if (hw->fc.requested_mode == ixgbe_fc_default)
3328 hw->fc.requested_mode = ixgbe_fc_full;
3330 /* Determine PAUSE and ASM_DIR bits. */
3331 switch (hw->fc.requested_mode) {
3336 case ixgbe_fc_tx_pause:
3340 case ixgbe_fc_rx_pause:
3341 /* Rx Flow control is enabled and Tx Flow control is
3342 * disabled by software override. Since there really
3343 * isn't a way to advertise that we are capable of RX
3344 * Pause ONLY, we will advertise that we support both
3345 * symmetric and asymmetric Rx PAUSE, as such we fall
3346 * through to the fc_full statement. Later, we will
3347 * disable the adapter's ability to send PAUSE frames.
3354 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3355 "Flow control param set incorrectly\n");
3356 ret_val = IXGBE_ERR_CONFIG;
3360 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
3361 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
3362 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3363 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3364 if (ret_val != IXGBE_SUCCESS)
3366 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3367 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3369 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3371 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3372 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
3373 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3374 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3376 /* This device does not fully support AN. */
3377 hw->fc.disable_fc_autoneg = true;
3385 * ixgbe_set_mux - Set mux for port 1 access with CS4227
3386 * @hw: pointer to hardware structure
3387 * @state: set mux if 1, clear if 0
3389 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
3393 if (!hw->bus.lan_id)
3395 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3397 esdp |= IXGBE_ESDP_SDP1;
3399 esdp &= ~IXGBE_ESDP_SDP1;
3400 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
3401 IXGBE_WRITE_FLUSH(hw);
3405 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
3406 * @hw: pointer to hardware structure
3407 * @mask: Mask to specify which semaphore to acquire
3409 * Acquires the SWFW semaphore and sets the I2C MUX
3411 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3415 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
3417 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
3421 if (mask & IXGBE_GSSR_I2C_MASK)
3422 ixgbe_set_mux(hw, 1);
3424 return IXGBE_SUCCESS;
3428 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
3429 * @hw: pointer to hardware structure
3430 * @mask: Mask to specify which semaphore to release
3432 * Releases the SWFW semaphore and sets the I2C MUX
3434 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3436 DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
3438 if (mask & IXGBE_GSSR_I2C_MASK)
3439 ixgbe_set_mux(hw, 0);
3441 ixgbe_release_swfw_sync_X540(hw, mask);
3445 * ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
3446 * @hw: pointer to hardware structure
3447 * @mask: Mask to specify which semaphore to acquire
3449 * Acquires the SWFW semaphore and get the shared phy token as needed
3451 static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
3453 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3454 int retries = FW_PHY_TOKEN_RETRIES;
3455 s32 status = IXGBE_SUCCESS;
3457 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
3461 status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
3464 if (!(mask & IXGBE_GSSR_TOKEN_SM))
3466 status = ixgbe_get_phy_token(hw);
3467 if (status != IXGBE_ERR_TOKEN_RETRY)
3470 ixgbe_release_swfw_sync_X540(hw, hmask);
3471 msec_delay(FW_PHY_TOKEN_DELAY);
3478 * ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
3479 * @hw: pointer to hardware structure
3480 * @mask: Mask to specify which semaphore to release
3482 * Releases the SWFW semaphore and puts the shared phy token as needed
3484 static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
3486 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3488 DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
3490 if (mask & IXGBE_GSSR_TOKEN_SM)
3491 ixgbe_put_phy_token(hw);
3494 ixgbe_release_swfw_sync_X540(hw, hmask);
3498 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
3499 * @hw: pointer to hardware structure
3501 * Handle external Base T PHY interrupt. If high temperature
3502 * failure alarm then return error, else if link status change
3503 * then setup internal/external PHY link
3505 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
3506 * failure alarm, else return PHY access status.
3508 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
3513 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
3515 if (status != IXGBE_SUCCESS)
3519 return ixgbe_setup_internal_phy(hw);
3521 return IXGBE_SUCCESS;
3525 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
3526 * @hw: pointer to hardware structure
3527 * @speed: new link speed
3528 * @autoneg_wait_to_complete: true when waiting for completion is needed
3530 * Setup internal/external PHY link speed based on link speed, then set
3531 * external PHY auto advertised link speed.
3533 * Returns error status for any failure
3535 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
3536 ixgbe_link_speed speed,
3537 bool autoneg_wait_to_complete)
3540 ixgbe_link_speed force_speed;
3542 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
3544 /* Setup internal/external PHY link speed to iXFI (10G), unless
3545 * only 1G is auto advertised then setup KX link.
3547 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
3548 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3550 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3552 /* If internal link mode is XFI, then setup XFI internal link. */
3553 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3554 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
3556 if (status != IXGBE_SUCCESS)
3560 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
3564 * ixgbe_check_link_t_X550em - Determine link and speed status
3565 * @hw: pointer to hardware structure
3566 * @speed: pointer to link speed
3567 * @link_up: true when link is up
3568 * @link_up_wait_to_complete: bool used to wait for link up or not
3570 * Check that both the MAC and X557 external PHY have link.
3572 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3573 bool *link_up, bool link_up_wait_to_complete)
3578 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3579 return IXGBE_ERR_CONFIG;
3581 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
3582 link_up_wait_to_complete);
3584 /* If check link fails or MAC link is not up, then return */
3585 if (status != IXGBE_SUCCESS || !(*link_up))
3588 /* MAC link is up, so check external PHY link.
3589 * Read this twice back to back to indicate current status.
3591 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3592 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3595 if (status != IXGBE_SUCCESS)
3598 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3599 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3602 if (status != IXGBE_SUCCESS)
3605 /* If external PHY link is not up, then indicate link not up */
3606 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
3609 return IXGBE_SUCCESS;
3613 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
3614 * @hw: pointer to hardware structure
3616 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
3620 status = ixgbe_reset_phy_generic(hw);
3622 if (status != IXGBE_SUCCESS)
3625 /* Configure Link Status Alarm and Temperature Threshold interrupts */
3626 return ixgbe_enable_lasi_ext_t_x550em(hw);
3630 * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
3631 * @hw: pointer to hardware structure
3632 * @led_idx: led number to turn on
3634 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3638 DEBUGFUNC("ixgbe_led_on_t_X550em");
3640 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3641 return IXGBE_ERR_PARAM;
3643 /* To turn on the LED, set mode to ON. */
3644 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3645 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3646 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
3647 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3648 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3650 return IXGBE_SUCCESS;
3654 * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
3655 * @hw: pointer to hardware structure
3656 * @led_idx: led number to turn off
3658 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3662 DEBUGFUNC("ixgbe_led_off_t_X550em");
3664 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3665 return IXGBE_ERR_PARAM;
3667 /* To turn on the LED, set mode to ON. */
3668 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3669 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3670 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
3671 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3672 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3674 return IXGBE_SUCCESS;