1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
43 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
44 * @hw: pointer to hardware structure
46 * Initialize the function pointers and assign the MAC type for X550.
47 * Does not touch the hardware.
49 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
51 struct ixgbe_mac_info *mac = &hw->mac;
52 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
55 DEBUGFUNC("ixgbe_init_ops_X550");
57 ret_val = ixgbe_init_ops_X540(hw);
58 mac->ops.dmac_config = ixgbe_dmac_config_X550;
59 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
60 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
61 mac->ops.setup_eee = ixgbe_setup_eee_X550;
62 mac->ops.set_source_address_pruning =
63 ixgbe_set_source_address_pruning_X550;
64 mac->ops.set_ethertype_anti_spoofing =
65 ixgbe_set_ethertype_anti_spoofing_X550;
67 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
68 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
69 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
70 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
71 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
72 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
73 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
74 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
75 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
77 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
78 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
79 mac->ops.mdd_event = ixgbe_mdd_event_X550;
80 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
81 mac->ops.disable_rx = ixgbe_disable_rx_x550;
86 * ixgbe_read_cs4227 - Read CS4227 register
87 * @hw: pointer to hardware structure
88 * @reg: register number to write
89 * @value: pointer to receive value read
93 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
95 return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
99 * ixgbe_write_cs4227 - Write CS4227 register
100 * @hw: pointer to hardware structure
101 * @reg: register number to write
102 * @value: value to write to register
104 * Returns status code
106 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
108 return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
112 * ixgbe_get_cs4227_status - Return CS4227 status
113 * @hw: pointer to hardware structure
115 * Returns error if CS4227 not successfully initialized
117 STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
123 for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) {
124 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB,
126 if (status != IXGBE_SUCCESS)
128 if (value == IXGBE_CS4227_GLOBAL_ID_VALUE)
130 msec_delay(IXGBE_CS4227_CHECK_DELAY);
132 if (value != IXGBE_CS4227_GLOBAL_ID_VALUE)
133 return IXGBE_ERR_PHY;
135 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
136 IXGBE_CS4227_SCRATCH_VALUE);
137 if (status != IXGBE_SUCCESS)
139 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
140 if (status != IXGBE_SUCCESS)
142 if (value != IXGBE_CS4227_SCRATCH_VALUE)
143 return IXGBE_ERR_PHY;
144 return IXGBE_SUCCESS;
148 * ixgbe_read_pe - Read register from port expander
149 * @hw: pointer to hardware structure
150 * @reg: register number to read
151 * @value: pointer to receive read value
153 * Returns status code
155 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
159 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
160 if (status != IXGBE_SUCCESS)
161 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
162 "port expander access failed with %d\n", status);
167 * ixgbe_write_pe - Write register to port expander
168 * @hw: pointer to hardware structure
169 * @reg: register number to write
170 * @value: value to write
172 * Returns status code
174 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
178 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
179 if (status != IXGBE_SUCCESS)
180 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
181 "port expander access failed with %d\n", status);
186 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
187 * @hw: pointer to hardware structure
191 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
196 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
197 if (status != IXGBE_SUCCESS)
199 reg |= IXGBE_PE_BIT1;
200 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
201 if (status != IXGBE_SUCCESS)
204 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
205 if (status != IXGBE_SUCCESS)
207 reg &= ~IXGBE_PE_BIT1;
208 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
209 if (status != IXGBE_SUCCESS)
212 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
213 if (status != IXGBE_SUCCESS)
215 reg &= ~IXGBE_PE_BIT1;
216 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
217 if (status != IXGBE_SUCCESS)
220 usec_delay(IXGBE_CS4227_RESET_HOLD);
222 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
223 if (status != IXGBE_SUCCESS)
225 reg |= IXGBE_PE_BIT1;
226 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
227 if (status != IXGBE_SUCCESS)
230 msec_delay(IXGBE_CS4227_RESET_DELAY);
232 return IXGBE_SUCCESS;
236 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
237 * @hw: pointer to hardware structure
239 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
241 u32 swfw_mask = hw->phy.phy_semaphore_mask;
245 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
246 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
247 if (status != IXGBE_SUCCESS) {
248 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
249 "semaphore failed with %d\n", status);
252 status = ixgbe_get_cs4227_status(hw);
253 if (status == IXGBE_SUCCESS) {
254 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
255 msec_delay(hw->eeprom.semaphore_delay);
258 ixgbe_reset_cs4227(hw);
259 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
260 msec_delay(hw->eeprom.semaphore_delay);
262 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
263 "Unable to initialize CS4227, err=%d\n", status);
267 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
268 * @hw: pointer to hardware structure
270 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
272 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
274 if (hw->bus.lan_id) {
275 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
276 esdp |= IXGBE_ESDP_SDP1_DIR;
278 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
279 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
280 IXGBE_WRITE_FLUSH(hw);
284 * ixgbe_identify_phy_x550em - Get PHY type based on device id
285 * @hw: pointer to hardware structure
289 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
291 switch (hw->device_id) {
292 case IXGBE_DEV_ID_X550EM_X_SFP:
293 /* set up for CS4227 usage */
294 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
295 ixgbe_setup_mux_ctl(hw);
296 ixgbe_check_cs4227(hw);
298 return ixgbe_identify_module_generic(hw);
300 case IXGBE_DEV_ID_X550EM_X_KX4:
301 hw->phy.type = ixgbe_phy_x550em_kx4;
303 case IXGBE_DEV_ID_X550EM_X_KR:
304 hw->phy.type = ixgbe_phy_x550em_kr;
306 case IXGBE_DEV_ID_X550EM_X_1G_T:
307 case IXGBE_DEV_ID_X550EM_X_10G_T:
308 return ixgbe_identify_phy_generic(hw);
312 return IXGBE_SUCCESS;
315 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
316 u32 device_type, u16 *phy_data)
318 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
319 return IXGBE_NOT_IMPLEMENTED;
322 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
323 u32 device_type, u16 phy_data)
325 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
326 return IXGBE_NOT_IMPLEMENTED;
330 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
331 * @hw: pointer to hardware structure
333 * Initialize the function pointers and for MAC type X550EM.
334 * Does not touch the hardware.
336 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
338 struct ixgbe_mac_info *mac = &hw->mac;
339 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
340 struct ixgbe_phy_info *phy = &hw->phy;
343 DEBUGFUNC("ixgbe_init_ops_X550EM");
345 /* Similar to X550 so start there. */
346 ret_val = ixgbe_init_ops_X550(hw);
348 /* Since this function eventually calls
349 * ixgbe_init_ops_540 by design, we are setting
350 * the pointers to NULL explicitly here to overwrite
351 * the values being set in the x540 function.
353 /* Thermal sensor not supported in x550EM */
354 mac->ops.get_thermal_sensor_data = NULL;
355 mac->ops.init_thermal_sensor_thresh = NULL;
356 mac->thermal_sensor_enabled = false;
358 /* FCOE not supported in x550EM */
359 mac->ops.get_san_mac_addr = NULL;
360 mac->ops.set_san_mac_addr = NULL;
361 mac->ops.get_wwn_prefix = NULL;
362 mac->ops.get_fcoe_boot_status = NULL;
364 /* IPsec not supported in x550EM */
365 mac->ops.disable_sec_rx_path = NULL;
366 mac->ops.enable_sec_rx_path = NULL;
368 /* AUTOC register is not present in x550EM. */
369 mac->ops.prot_autoc_read = NULL;
370 mac->ops.prot_autoc_write = NULL;
372 /* X550EM bus type is internal*/
373 hw->bus.type = ixgbe_bus_type_internal;
374 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
376 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
377 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
378 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
379 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
380 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
381 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
382 mac->ops.get_supported_physical_layer =
383 ixgbe_get_supported_physical_layer_X550em;
385 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
386 mac->ops.setup_fc = ixgbe_setup_fc_generic;
388 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
390 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
391 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
393 if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
394 mac->ops.setup_eee = NULL;
397 phy->ops.init = ixgbe_init_phy_ops_X550em;
398 phy->ops.identify = ixgbe_identify_phy_x550em;
399 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
400 phy->ops.set_phy_power = NULL;
404 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
405 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
406 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
407 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
408 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
409 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
410 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
411 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
417 * ixgbe_dmac_config_X550
418 * @hw: pointer to hardware structure
420 * Configure DMA coalescing. If enabling dmac, dmac is activated.
421 * When disabling dmac, dmac enable dmac bit is cleared.
423 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
425 u32 reg, high_pri_tc;
427 DEBUGFUNC("ixgbe_dmac_config_X550");
429 /* Disable DMA coalescing before configuring */
430 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
431 reg &= ~IXGBE_DMACR_DMAC_EN;
432 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
434 /* Disable DMA Coalescing if the watchdog timer is 0 */
435 if (!hw->mac.dmac_config.watchdog_timer)
438 ixgbe_dmac_config_tcs_X550(hw);
440 /* Configure DMA Coalescing Control Register */
441 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
443 /* Set the watchdog timer in units of 40.96 usec */
444 reg &= ~IXGBE_DMACR_DMACWT_MASK;
445 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
447 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
448 /* If fcoe is enabled, set high priority traffic class */
449 if (hw->mac.dmac_config.fcoe_en) {
450 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
451 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
452 IXGBE_DMACR_HIGH_PRI_TC_MASK);
454 reg |= IXGBE_DMACR_EN_MNG_IND;
456 /* Enable DMA coalescing after configuration */
457 reg |= IXGBE_DMACR_DMAC_EN;
458 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
461 return IXGBE_SUCCESS;
465 * ixgbe_dmac_config_tcs_X550
466 * @hw: pointer to hardware structure
468 * Configure DMA coalescing threshold per TC. The dmac enable bit must
469 * be cleared before configuring.
471 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
473 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
475 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
477 /* Configure DMA coalescing enabled */
478 switch (hw->mac.dmac_config.link_speed) {
479 case IXGBE_LINK_SPEED_100_FULL:
480 pb_headroom = IXGBE_DMACRXT_100M;
482 case IXGBE_LINK_SPEED_1GB_FULL:
483 pb_headroom = IXGBE_DMACRXT_1G;
486 pb_headroom = IXGBE_DMACRXT_10G;
490 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
491 IXGBE_MHADD_MFS_SHIFT) / 1024);
493 /* Set the per Rx packet buffer receive threshold */
494 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
495 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
496 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
498 if (tc < hw->mac.dmac_config.num_tcs) {
500 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
501 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
502 IXGBE_RXPBSIZE_SHIFT;
504 /* Calculate receive buffer threshold in kilobytes */
505 if (rx_pb_size > pb_headroom)
506 rx_pb_size = rx_pb_size - pb_headroom;
510 /* Minimum of MFS shall be set for DMCTH */
511 reg |= (rx_pb_size > maxframe_size_kb) ?
512 rx_pb_size : maxframe_size_kb;
514 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
516 return IXGBE_SUCCESS;
520 * ixgbe_dmac_update_tcs_X550
521 * @hw: pointer to hardware structure
523 * Disables dmac, updates per TC settings, and then enables dmac.
525 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
529 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
531 /* Disable DMA coalescing before configuring */
532 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
533 reg &= ~IXGBE_DMACR_DMAC_EN;
534 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
536 ixgbe_dmac_config_tcs_X550(hw);
538 /* Enable DMA coalescing after configuration */
539 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
540 reg |= IXGBE_DMACR_DMAC_EN;
541 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
543 return IXGBE_SUCCESS;
547 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
548 * @hw: pointer to hardware structure
550 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
551 * ixgbe_hw struct in order to set up EEPROM access.
553 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
555 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
559 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
561 if (eeprom->type == ixgbe_eeprom_uninitialized) {
562 eeprom->semaphore_delay = 10;
563 eeprom->type = ixgbe_flash;
565 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
566 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
567 IXGBE_EEC_SIZE_SHIFT);
568 eeprom->word_size = 1 << (eeprom_size +
569 IXGBE_EEPROM_WORD_SIZE_SHIFT);
571 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
572 eeprom->type, eeprom->word_size);
575 return IXGBE_SUCCESS;
579 * ixgbe_setup_eee_X550 - Enable/disable EEE support
580 * @hw: pointer to the HW structure
581 * @enable_eee: boolean flag to enable EEE
583 * Enable/disable EEE based on enable_eee flag.
584 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
588 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
595 DEBUGFUNC("ixgbe_setup_eee_X550");
597 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
598 /* Enable or disable EEE per flag */
600 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
602 if (hw->device_id == IXGBE_DEV_ID_X550T) {
603 /* Advertise EEE capability */
604 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
605 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
607 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
608 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
609 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
611 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
612 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
613 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
614 status = ixgbe_read_iosf_sb_reg_x550(hw,
615 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
616 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
617 if (status != IXGBE_SUCCESS)
620 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
621 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
623 status = ixgbe_write_iosf_sb_reg_x550(hw,
624 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
625 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
626 if (status != IXGBE_SUCCESS)
630 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
632 if (hw->device_id == IXGBE_DEV_ID_X550T) {
633 /* Disable advertised EEE capability */
634 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
635 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
637 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
638 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
639 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
641 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
642 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
643 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
644 status = ixgbe_read_iosf_sb_reg_x550(hw,
645 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
646 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
647 if (status != IXGBE_SUCCESS)
650 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
651 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
653 status = ixgbe_write_iosf_sb_reg_x550(hw,
654 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
655 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
656 if (status != IXGBE_SUCCESS)
660 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
662 return IXGBE_SUCCESS;
666 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
667 * @hw: pointer to hardware structure
668 * @enable: enable or disable source address pruning
669 * @pool: Rx pool to set source address pruning for
671 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
676 /* max rx pool is 63 */
680 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
681 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
684 pfflp |= (1ULL << pool);
686 pfflp &= ~(1ULL << pool);
688 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
689 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
693 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
694 * @hw: pointer to hardware structure
695 * @enable: enable or disable switch for Ethertype anti-spoofing
696 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
699 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
702 int vf_target_reg = vf >> 3;
703 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
706 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
708 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
710 pfvfspoof |= (1 << vf_target_shift);
712 pfvfspoof &= ~(1 << vf_target_shift);
714 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
718 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
720 * @hw: pointer to hardware structure
721 * @reg_addr: 32 bit PHY register to write
722 * @device_type: 3 bit device type
723 * @data: Data to write to the register
725 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
726 u32 device_type, u32 data)
728 u32 i, command, error;
730 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
731 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
733 /* Write IOSF control register */
734 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
736 /* Write IOSF data register */
737 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
739 * Check every 10 usec to see if the address cycle completed.
740 * The SB IOSF BUSY bit will clear when the operation is
743 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
746 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
747 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
751 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
752 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
753 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
754 ERROR_REPORT2(IXGBE_ERROR_POLLING,
755 "Failed to write, error %x\n", error);
756 return IXGBE_ERR_PHY;
759 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
760 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Write timed out\n");
761 return IXGBE_ERR_PHY;
764 return IXGBE_SUCCESS;
768 * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
770 * @hw: pointer to hardware structure
771 * @reg_addr: 32 bit PHY register to write
772 * @device_type: 3 bit device type
773 * @phy_data: Pointer to read data from the register
775 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
776 u32 device_type, u32 *data)
778 u32 i, command, error;
780 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
781 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
783 /* Write IOSF control register */
784 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
787 * Check every 10 usec to see if the address cycle completed.
788 * The SB IOSF BUSY bit will clear when the operation is
791 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
794 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
795 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
799 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
800 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
801 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
802 ERROR_REPORT2(IXGBE_ERROR_POLLING,
803 "Failed to read, error %x\n", error);
804 return IXGBE_ERR_PHY;
807 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
808 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Read timed out\n");
809 return IXGBE_ERR_PHY;
812 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
814 return IXGBE_SUCCESS;
818 * ixgbe_disable_mdd_X550
819 * @hw: pointer to hardware structure
821 * Disable malicious driver detection
823 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
827 DEBUGFUNC("ixgbe_disable_mdd_X550");
829 /* Disable MDD for TX DMA and interrupt */
830 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
831 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
832 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
834 /* Disable MDD for RX and interrupt */
835 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
836 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
837 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
841 * ixgbe_enable_mdd_X550
842 * @hw: pointer to hardware structure
844 * Enable malicious driver detection
846 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
850 DEBUGFUNC("ixgbe_enable_mdd_X550");
852 /* Enable MDD for TX DMA and interrupt */
853 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
854 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
855 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
857 /* Enable MDD for RX and interrupt */
858 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
859 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
860 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
864 * ixgbe_restore_mdd_vf_X550
865 * @hw: pointer to hardware structure
868 * Restore VF that was disabled during malicious driver detection event
870 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
872 u32 idx, reg, num_qs, start_q, bitmask;
874 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
876 /* Map VF to queues */
877 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
878 switch (reg & IXGBE_MRQC_MRQE_MASK) {
879 case IXGBE_MRQC_VMDQRT8TCEN:
880 num_qs = 8; /* 16 VFs / pools */
881 bitmask = 0x000000FF;
883 case IXGBE_MRQC_VMDQRSS32EN:
884 case IXGBE_MRQC_VMDQRT4TCEN:
885 num_qs = 4; /* 32 VFs / pools */
886 bitmask = 0x0000000F;
888 default: /* 64 VFs / pools */
890 bitmask = 0x00000003;
893 start_q = vf * num_qs;
895 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
898 reg |= (bitmask << (start_q % 32));
899 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
900 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
904 * ixgbe_mdd_event_X550
905 * @hw: pointer to hardware structure
906 * @vf_bitmap: vf bitmap of malicious vfs
908 * Handle malicious driver detection event.
910 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
913 u32 i, j, reg, q, shift, vf, idx;
915 DEBUGFUNC("ixgbe_mdd_event_X550");
917 /* figure out pool size for mapping to vf's */
918 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
919 switch (reg & IXGBE_MRQC_MRQE_MASK) {
920 case IXGBE_MRQC_VMDQRT8TCEN:
921 shift = 3; /* 16 VFs / pools */
923 case IXGBE_MRQC_VMDQRSS32EN:
924 case IXGBE_MRQC_VMDQRT4TCEN:
925 shift = 2; /* 32 VFs / pools */
928 shift = 1; /* 64 VFs / pools */
932 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
933 for (i = 0; i < 4; i++) {
934 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
935 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
940 /* Get malicious queue */
941 for (j = 0; j < 32 && wqbr; j++) {
943 if (!(wqbr & (1 << j)))
946 /* Get queue from bitmask */
949 /* Map queue to vf */
952 /* Set vf bit in vf_bitmap */
954 vf_bitmap[idx] |= (1 << (vf % 32));
961 * ixgbe_get_media_type_X550em - Get media type
962 * @hw: pointer to hardware structure
964 * Returns the media type (fiber, copper, backplane)
966 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
968 enum ixgbe_media_type media_type;
970 DEBUGFUNC("ixgbe_get_media_type_X550em");
972 /* Detect if there is a copper PHY attached. */
973 switch (hw->device_id) {
974 case IXGBE_DEV_ID_X550EM_X_KR:
975 case IXGBE_DEV_ID_X550EM_X_KX4:
976 media_type = ixgbe_media_type_backplane;
978 case IXGBE_DEV_ID_X550EM_X_SFP:
979 media_type = ixgbe_media_type_fiber;
981 case IXGBE_DEV_ID_X550EM_X_1G_T:
982 case IXGBE_DEV_ID_X550EM_X_10G_T:
983 media_type = ixgbe_media_type_copper;
986 media_type = ixgbe_media_type_unknown;
993 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
994 * @hw: pointer to hardware structure
996 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
998 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1000 ixgbe_init_mac_link_ops_X550em(hw);
1001 hw->phy.ops.reset = NULL;
1003 return IXGBE_SUCCESS;
1007 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1008 * @hw: pointer to hardware structure
1010 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1012 struct ixgbe_mac_info *mac = &hw->mac;
1014 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1016 switch (hw->mac.ops.get_media_type(hw)) {
1017 case ixgbe_media_type_fiber:
1018 /* CS4227 does not support autoneg, so disable the laser control
1019 * functions for SFP+ fiber
1021 mac->ops.disable_tx_laser = NULL;
1022 mac->ops.enable_tx_laser = NULL;
1023 mac->ops.flap_tx_laser = NULL;
1024 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1025 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1026 mac->ops.set_rate_select_speed =
1027 ixgbe_set_soft_rate_select_speed;
1029 case ixgbe_media_type_copper:
1030 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1031 mac->ops.check_link = ixgbe_check_link_t_X550em;
1039 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1040 * @hw: pointer to hardware structure
1041 * @speed: pointer to link speed
1042 * @autoneg: true when autoneg or autotry is enabled
1044 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1045 ixgbe_link_speed *speed,
1048 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1051 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1053 /* CS4227 SFP must not enable auto-negotiation */
1056 /* Check if 1G SFP module. */
1057 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1058 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1059 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1060 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1061 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1062 return IXGBE_SUCCESS;
1065 /* Link capabilities are based on SFP */
1066 if (hw->phy.multispeed_fiber)
1067 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1068 IXGBE_LINK_SPEED_1GB_FULL;
1070 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1072 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1073 IXGBE_LINK_SPEED_1GB_FULL;
1077 return IXGBE_SUCCESS;
1081 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1082 * @hw: pointer to hardware structure
1083 * @lsc: pointer to boolean flag which indicates whether external Base T
1084 * PHY interrupt is lsc
1086 * Determime if external Base T PHY interrupt cause is high temperature
1087 * failure alarm or link status change.
1089 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1090 * failure alarm, else return PHY access status.
1092 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1099 /* Vendor alarm triggered */
1100 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1101 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1104 if (status != IXGBE_SUCCESS ||
1105 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1108 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1109 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1110 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1113 if (status != IXGBE_SUCCESS ||
1114 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1115 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1118 /* High temperature failure alarm triggered */
1119 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1120 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1123 if (status != IXGBE_SUCCESS)
1126 /* If high temperature failure, then return over temp error and exit */
1127 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL)
1128 return IXGBE_ERR_OVERTEMP;
1130 /* Vendor alarm 2 triggered */
1131 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1132 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1134 if (status != IXGBE_SUCCESS ||
1135 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1138 /* link connect/disconnect event occurred */
1139 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1140 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1142 if (status != IXGBE_SUCCESS)
1146 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1149 return IXGBE_SUCCESS;
1153 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1154 * @hw: pointer to hardware structure
1156 * Enable link status change and temperature failure alarm for the external
1159 * Returns PHY access status
1161 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1167 /* Clear interrupt flags */
1168 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1170 /* Enable link status change alarm */
1171 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1172 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1174 if (status != IXGBE_SUCCESS)
1177 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1179 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1180 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1182 if (status != IXGBE_SUCCESS)
1185 /* Enables high temperature failure alarm */
1186 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1187 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1190 if (status != IXGBE_SUCCESS)
1193 reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;
1195 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1196 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1199 if (status != IXGBE_SUCCESS)
1202 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1203 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1204 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1207 if (status != IXGBE_SUCCESS)
1210 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1211 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1213 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1214 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1217 if (status != IXGBE_SUCCESS)
1220 /* Enable chip-wide vendor alarm */
1221 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1222 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1225 if (status != IXGBE_SUCCESS)
1228 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1230 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1231 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1238 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1239 * @hw: pointer to hardware structure
1241 * Initialize any function pointers that were not able to be
1242 * set during init_shared_code because the PHY/SFP type was
1243 * not known. Perform the SFP init if necessary.
1245 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1247 struct ixgbe_phy_info *phy = &hw->phy;
1250 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1252 hw->mac.ops.set_lan_id(hw);
1254 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1255 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1256 ixgbe_setup_mux_ctl(hw);
1259 /* Identify the PHY or SFP module */
1260 ret_val = phy->ops.identify(hw);
1261 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1264 /* Setup function pointers based on detected hardware */
1265 ixgbe_init_mac_link_ops_X550em(hw);
1266 if (phy->sfp_type != ixgbe_sfp_type_unknown)
1267 phy->ops.reset = NULL;
1269 /* Set functions pointers based on phy type */
1270 switch (hw->phy.type) {
1271 case ixgbe_phy_x550em_kx4:
1272 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
1273 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1274 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1276 case ixgbe_phy_x550em_kr:
1277 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1278 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1279 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1281 case ixgbe_phy_x550em_ext_t:
1282 phy->ops.setup_internal_link =
1283 ixgbe_setup_internal_phy_t_x550em;
1284 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1285 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1286 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1295 * ixgbe_reset_hw_X550em - Perform hardware reset
1296 * @hw: pointer to hardware structure
1298 * Resets the hardware by resetting the transmit and receive units, masks
1299 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1302 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1304 ixgbe_link_speed link_speed;
1308 bool link_up = false;
1310 DEBUGFUNC("ixgbe_reset_hw_X550em");
1312 /* Call adapter stop to disable Tx/Rx and clear interrupts */
1313 status = hw->mac.ops.stop_adapter(hw);
1314 if (status != IXGBE_SUCCESS)
1317 /* flush pending Tx transactions */
1318 ixgbe_clear_tx_pending(hw);
1320 /* PHY ops must be identified and initialized prior to reset */
1322 /* Identify PHY and related function pointers */
1323 status = hw->phy.ops.init(hw);
1325 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1328 /* start the external PHY */
1329 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1330 status = ixgbe_init_ext_t_x550em(hw);
1335 /* Setup SFP module if there is one present. */
1336 if (hw->phy.sfp_setup_needed) {
1337 status = hw->mac.ops.setup_sfp(hw);
1338 hw->phy.sfp_setup_needed = false;
1341 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1345 if (!hw->phy.reset_disable && hw->phy.ops.reset)
1346 hw->phy.ops.reset(hw);
1349 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
1350 * If link reset is used when link is up, it might reset the PHY when
1351 * mng is using it. If link is down or the flag to force full link
1352 * reset is set, then perform link reset.
1354 ctrl = IXGBE_CTRL_LNK_RST;
1355 if (!hw->force_full_reset) {
1356 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1358 ctrl = IXGBE_CTRL_RST;
1361 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1362 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1363 IXGBE_WRITE_FLUSH(hw);
1365 /* Poll for reset bit to self-clear meaning reset is complete */
1366 for (i = 0; i < 10; i++) {
1368 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1369 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1373 if (ctrl & IXGBE_CTRL_RST_MASK) {
1374 status = IXGBE_ERR_RESET_FAILED;
1375 DEBUGOUT("Reset polling failed to complete.\n");
1380 /* Double resets are required for recovery from certain error
1381 * conditions. Between resets, it is necessary to stall to
1382 * allow time for any pending HW events to complete.
1384 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1385 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1389 /* Store the permanent mac address */
1390 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1392 /* Store MAC address from RAR0, clear receive address registers, and
1393 * clear the multicast table. Also reset num_rar_entries to 128,
1394 * since we modify this value when programming the SAN MAC address.
1396 hw->mac.num_rar_entries = 128;
1397 hw->mac.ops.init_rx_addrs(hw);
1400 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1401 ixgbe_setup_mux_ctl(hw);
1407 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1408 * @hw: pointer to hardware structure
1410 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1415 status = hw->phy.ops.read_reg(hw,
1416 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1417 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1420 if (status != IXGBE_SUCCESS)
1423 /* If PHY FW reset completed bit is set then this is the first
1424 * SW instance after a power on so the PHY FW must be un-stalled.
1426 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1427 status = hw->phy.ops.read_reg(hw,
1428 IXGBE_MDIO_GLOBAL_RES_PR_10,
1429 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1432 if (status != IXGBE_SUCCESS)
1435 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1437 status = hw->phy.ops.write_reg(hw,
1438 IXGBE_MDIO_GLOBAL_RES_PR_10,
1439 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1442 if (status != IXGBE_SUCCESS)
1450 * ixgbe_setup_kr_x550em - Configure the KR PHY.
1451 * @hw: pointer to hardware structure
1453 * Configures the integrated KR PHY.
1455 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1460 status = ixgbe_read_iosf_sb_reg_x550(hw,
1461 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1462 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1466 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1467 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ |
1468 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC);
1469 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1470 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1472 /* Advertise 10G support. */
1473 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1474 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1476 /* Advertise 1G support. */
1477 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1478 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1480 /* Restart auto-negotiation. */
1481 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1482 status = ixgbe_write_iosf_sb_reg_x550(hw,
1483 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1484 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1490 * ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1491 * @hw: pointer to hardware structure
1493 * Configures the integrated KX4 PHY.
1495 s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1500 status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1501 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, ®_val);
1505 reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1506 IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1508 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1510 /* Advertise 10G support. */
1511 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1512 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1514 /* Advertise 1G support. */
1515 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1516 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1518 /* Restart auto-negotiation. */
1519 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1520 status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1521 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, reg_val);
1527 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1528 * @hw: pointer to hardware structure
1529 * @speed: the link speed to force
1531 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
1532 * internal and external PHY at a specific speed, without autonegotiation.
1534 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1539 /* Disable AN and force speed to 10G Serial. */
1540 status = ixgbe_read_iosf_sb_reg_x550(hw,
1541 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1542 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1543 if (status != IXGBE_SUCCESS)
1546 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1547 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1549 /* Select forced link speed for internal PHY. */
1551 case IXGBE_LINK_SPEED_10GB_FULL:
1552 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1554 case IXGBE_LINK_SPEED_1GB_FULL:
1555 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1558 /* Other link speeds are not supported by internal KR PHY. */
1559 return IXGBE_ERR_LINK_SETUP;
1562 status = ixgbe_write_iosf_sb_reg_x550(hw,
1563 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1564 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1565 if (status != IXGBE_SUCCESS)
1568 /* Disable training protocol FSM. */
1569 status = ixgbe_read_iosf_sb_reg_x550(hw,
1570 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1571 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1572 if (status != IXGBE_SUCCESS)
1574 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1575 status = ixgbe_write_iosf_sb_reg_x550(hw,
1576 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1577 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1578 if (status != IXGBE_SUCCESS)
1581 /* Disable Flex from training TXFFE. */
1582 status = ixgbe_read_iosf_sb_reg_x550(hw,
1583 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1584 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1585 if (status != IXGBE_SUCCESS)
1587 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1588 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1589 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1590 status = ixgbe_write_iosf_sb_reg_x550(hw,
1591 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1592 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1593 if (status != IXGBE_SUCCESS)
1595 status = ixgbe_read_iosf_sb_reg_x550(hw,
1596 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1597 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1598 if (status != IXGBE_SUCCESS)
1600 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1601 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1602 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1603 status = ixgbe_write_iosf_sb_reg_x550(hw,
1604 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1605 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1606 if (status != IXGBE_SUCCESS)
1609 /* Enable override for coefficients. */
1610 status = ixgbe_read_iosf_sb_reg_x550(hw,
1611 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1612 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1613 if (status != IXGBE_SUCCESS)
1615 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1616 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1617 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1618 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1619 status = ixgbe_write_iosf_sb_reg_x550(hw,
1620 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1621 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1622 if (status != IXGBE_SUCCESS)
1625 /* Toggle port SW reset by AN reset. */
1626 status = ixgbe_read_iosf_sb_reg_x550(hw,
1627 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1628 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1629 if (status != IXGBE_SUCCESS)
1631 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1632 status = ixgbe_write_iosf_sb_reg_x550(hw,
1633 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1634 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1640 * ixgbe_setup_mac_link_sfp_x550em - Configure the CS4227 & KR PHY for SFP
1641 * @hw: pointer to hardware structure
1643 * Configure the external CS4227 PHY and the integrated KR PHY for SFP support.
1645 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1646 ixgbe_link_speed speed,
1647 bool autoneg_wait_to_complete)
1650 u16 reg_slice, reg_val;
1651 bool setup_linear = false;
1652 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1654 /* Configure the external PHY. */
1655 switch (hw->phy.sfp_type) {
1656 case ixgbe_sfp_type_unknown:
1657 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1658 case ixgbe_sfp_type_not_present:
1659 return IXGBE_SUCCESS;
1660 case ixgbe_sfp_type_da_cu_core0:
1661 case ixgbe_sfp_type_da_cu_core1:
1662 setup_linear = true;
1664 case ixgbe_sfp_type_srlr_core0:
1665 case ixgbe_sfp_type_srlr_core1:
1666 case ixgbe_sfp_type_da_act_lmt_core0:
1667 case ixgbe_sfp_type_da_act_lmt_core1:
1668 case ixgbe_sfp_type_1g_sx_core0:
1669 case ixgbe_sfp_type_1g_sx_core1:
1670 #ifdef SUPPORT_1000BASE_LX
1671 case ixgbe_sfp_type_1g_lx_core0:
1672 case ixgbe_sfp_type_1g_lx_core1:
1673 #endif /* SUPPORT_1000BASE_LX */
1674 setup_linear = false;
1677 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1680 /* Configure CS4227 for connection rate. */
1681 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB + (hw->bus.lan_id << 12);
1682 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000;
1683 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1686 /* Configure CS4227 for connection type. */
1687 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1689 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1691 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1692 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1695 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB + (hw->bus.lan_id << 12);
1696 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000;
1697 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1700 /* Configure CS4227 for connection type. */
1701 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (hw->bus.lan_id << 12);
1703 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1705 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1706 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1709 /* Configure the internal PHY. */
1710 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
1716 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1717 * @hw: point to hardware structure
1719 * Configures the link between the integrated KR PHY and the external X557 PHY
1720 * The driver will call this function when it gets a link status change
1721 * interrupt from the X557 PHY. This function configures the link speed
1722 * between the PHYs to match the link speed of the BASE-T link.
1724 * A return of a non-zero value indicates an error, and the base driver should
1725 * not report link up.
1727 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
1730 u16 autoneg_status, speed;
1731 ixgbe_link_speed force_speed;
1733 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1734 return IXGBE_ERR_CONFIG;
1736 /* read this twice back to back to indicate current status */
1737 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1738 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1740 if (status != IXGBE_SUCCESS)
1743 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1744 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1746 if (status != IXGBE_SUCCESS)
1749 /* If link is not up, then there is no setup necessary so return */
1750 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1751 return IXGBE_SUCCESS;
1753 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1754 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1757 /* clear everything but the speed and duplex bits */
1758 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1761 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1762 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1764 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1765 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1768 /* Internal PHY does not support anything else */
1769 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1772 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1776 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1777 * @hw: pointer to hardware structure
1779 * Configures the integrated KR PHY to use internal loopback mode.
1781 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1786 /* Disable AN and force speed to 10G Serial. */
1787 status = ixgbe_read_iosf_sb_reg_x550(hw,
1788 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1789 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1790 if (status != IXGBE_SUCCESS)
1792 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1793 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1794 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1795 status = ixgbe_write_iosf_sb_reg_x550(hw,
1796 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1797 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1798 if (status != IXGBE_SUCCESS)
1801 /* Set near-end loopback clocks. */
1802 status = ixgbe_read_iosf_sb_reg_x550(hw,
1803 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1804 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1805 if (status != IXGBE_SUCCESS)
1807 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1808 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1809 status = ixgbe_write_iosf_sb_reg_x550(hw,
1810 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1811 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1812 if (status != IXGBE_SUCCESS)
1815 /* Set loopback enable. */
1816 status = ixgbe_read_iosf_sb_reg_x550(hw,
1817 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1818 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1819 if (status != IXGBE_SUCCESS)
1821 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1822 status = ixgbe_write_iosf_sb_reg_x550(hw,
1823 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1824 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1825 if (status != IXGBE_SUCCESS)
1828 /* Training bypass. */
1829 status = ixgbe_read_iosf_sb_reg_x550(hw,
1830 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1831 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1832 if (status != IXGBE_SUCCESS)
1834 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
1835 status = ixgbe_write_iosf_sb_reg_x550(hw,
1836 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1837 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1843 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1844 * assuming that the semaphore is already obtained.
1845 * @hw: pointer to hardware structure
1846 * @offset: offset of word in the EEPROM to read
1847 * @data: word read from the EEPROM
1849 * Reads a 16 bit word from the EEPROM using the hostif.
1851 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1855 struct ixgbe_hic_read_shadow_ram buffer;
1857 DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
1858 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1859 buffer.hdr.req.buf_lenh = 0;
1860 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1861 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1863 /* convert offset from words to bytes */
1864 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1866 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1868 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1870 IXGBE_HI_COMMAND_TIMEOUT, false);
1875 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1876 FW_NVM_DATA_OFFSET);
1882 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1883 * @hw: pointer to hardware structure
1884 * @offset: offset of word in the EEPROM to read
1885 * @data: word read from the EEPROM
1887 * Reads a 16 bit word from the EEPROM using the hostif.
1889 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1892 s32 status = IXGBE_SUCCESS;
1894 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
1896 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1898 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
1899 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1901 status = IXGBE_ERR_SWFW_SYNC;
1908 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
1909 * @hw: pointer to hardware structure
1910 * @offset: offset of word in the EEPROM to read
1911 * @words: number of words
1912 * @data: word(s) read from the EEPROM
1914 * Reads a 16 bit word(s) from the EEPROM using the hostif.
1916 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1917 u16 offset, u16 words, u16 *data)
1919 struct ixgbe_hic_read_shadow_ram buffer;
1920 u32 current_word = 0;
1925 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
1927 /* Take semaphore for the entire operation. */
1928 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1930 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
1934 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
1935 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
1937 words_to_read = words;
1939 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1940 buffer.hdr.req.buf_lenh = 0;
1941 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1942 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1944 /* convert offset from words to bytes */
1945 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
1946 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
1948 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1950 IXGBE_HI_COMMAND_TIMEOUT,
1954 DEBUGOUT("Host interface command failed\n");
1958 for (i = 0; i < words_to_read; i++) {
1959 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
1961 u32 value = IXGBE_READ_REG(hw, reg);
1963 data[current_word] = (u16)(value & 0xffff);
1966 if (i < words_to_read) {
1968 data[current_word] = (u16)(value & 0xffff);
1972 words -= words_to_read;
1976 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1981 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1982 * @hw: pointer to hardware structure
1983 * @offset: offset of word in the EEPROM to write
1984 * @data: word write to the EEPROM
1986 * Write a 16 bit word to the EEPROM using the hostif.
1988 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1992 struct ixgbe_hic_write_shadow_ram buffer;
1994 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
1996 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
1997 buffer.hdr.req.buf_lenh = 0;
1998 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
1999 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2002 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2004 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2006 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2008 IXGBE_HI_COMMAND_TIMEOUT, false);
2014 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2015 * @hw: pointer to hardware structure
2016 * @offset: offset of word in the EEPROM to write
2017 * @data: word write to the EEPROM
2019 * Write a 16 bit word to the EEPROM using the hostif.
2021 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2024 s32 status = IXGBE_SUCCESS;
2026 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2028 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2030 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2031 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2033 DEBUGOUT("write ee hostif failed to get semaphore");
2034 status = IXGBE_ERR_SWFW_SYNC;
2041 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2042 * @hw: pointer to hardware structure
2043 * @offset: offset of word in the EEPROM to write
2044 * @words: number of words
2045 * @data: word(s) write to the EEPROM
2047 * Write a 16 bit word(s) to the EEPROM using the hostif.
2049 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2050 u16 offset, u16 words, u16 *data)
2052 s32 status = IXGBE_SUCCESS;
2055 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2057 /* Take semaphore for the entire operation. */
2058 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2059 if (status != IXGBE_SUCCESS) {
2060 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2064 for (i = 0; i < words; i++) {
2065 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2068 if (status != IXGBE_SUCCESS) {
2069 DEBUGOUT("Eeprom buffered write failed\n");
2074 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2081 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2082 * @hw: pointer to hardware structure
2083 * @ptr: pointer offset in eeprom
2084 * @size: size of section pointed by ptr, if 0 first word will be used as size
2085 * @csum: address of checksum to update
2087 * Returns error status for any failure
2089 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2090 u16 size, u16 *csum, u16 *buffer,
2095 u16 length, bufsz, i, start;
2098 bufsz = sizeof(buf) / sizeof(buf[0]);
2100 /* Read a chunk at the pointer location */
2102 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2104 DEBUGOUT("Failed to read EEPROM image\n");
2109 if (buffer_size < ptr)
2110 return IXGBE_ERR_PARAM;
2111 local_buffer = &buffer[ptr];
2119 length = local_buffer[0];
2121 /* Skip pointer section if length is invalid. */
2122 if (length == 0xFFFF || length == 0 ||
2123 (ptr + length) >= hw->eeprom.word_size)
2124 return IXGBE_SUCCESS;
2127 if (buffer && ((u32)start + (u32)length > buffer_size))
2128 return IXGBE_ERR_PARAM;
2130 for (i = start; length; i++, length--) {
2131 if (i == bufsz && !buffer) {
2137 /* Read a chunk at the pointer location */
2138 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2141 DEBUGOUT("Failed to read EEPROM image\n");
2145 *csum += local_buffer[i];
2147 return IXGBE_SUCCESS;
2151 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2152 * @hw: pointer to hardware structure
2153 * @buffer: pointer to buffer containing calculated checksum
2154 * @buffer_size: size of buffer
2156 * Returns a negative error code on error, or the 16-bit checksum
2158 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2160 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2164 u16 pointer, i, size;
2166 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2168 hw->eeprom.ops.init_params(hw);
2171 /* Read pointer area */
2172 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2173 IXGBE_EEPROM_LAST_WORD + 1,
2176 DEBUGOUT("Failed to read EEPROM image\n");
2179 local_buffer = eeprom_ptrs;
2181 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2182 return IXGBE_ERR_PARAM;
2183 local_buffer = buffer;
2187 * For X550 hardware include 0x0-0x41 in the checksum, skip the
2188 * checksum word itself
2190 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2191 if (i != IXGBE_EEPROM_CHECKSUM)
2192 checksum += local_buffer[i];
2195 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
2196 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2198 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2199 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2202 pointer = local_buffer[i];
2204 /* Skip pointer section if the pointer is invalid. */
2205 if (pointer == 0xFFFF || pointer == 0 ||
2206 pointer >= hw->eeprom.word_size)
2210 case IXGBE_PCIE_GENERAL_PTR:
2211 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2213 case IXGBE_PCIE_CONFIG0_PTR:
2214 case IXGBE_PCIE_CONFIG1_PTR:
2215 size = IXGBE_PCIE_CONFIG_SIZE;
2222 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2223 buffer, buffer_size);
2228 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2230 return (s32)checksum;
2234 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2235 * @hw: pointer to hardware structure
2237 * Returns a negative error code on error, or the 16-bit checksum
2239 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2241 return ixgbe_calc_checksum_X550(hw, NULL, 0);
2245 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2246 * @hw: pointer to hardware structure
2247 * @checksum_val: calculated checksum
2249 * Performs checksum calculation and validates the EEPROM checksum. If the
2250 * caller does not need checksum_val, the value can be NULL.
2252 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2256 u16 read_checksum = 0;
2258 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2260 /* Read the first word from the EEPROM. If this times out or fails, do
2261 * not continue or we could be in for a very long wait while every
2264 status = hw->eeprom.ops.read(hw, 0, &checksum);
2266 DEBUGOUT("EEPROM read failed\n");
2270 status = hw->eeprom.ops.calc_checksum(hw);
2274 checksum = (u16)(status & 0xffff);
2276 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2281 /* Verify read checksum from EEPROM is the same as
2282 * calculated checksum
2284 if (read_checksum != checksum) {
2285 status = IXGBE_ERR_EEPROM_CHECKSUM;
2286 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2287 "Invalid EEPROM checksum");
2290 /* If the user cares, return the calculated checksum */
2292 *checksum_val = checksum;
2298 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2299 * @hw: pointer to hardware structure
2301 * After writing EEPROM to shadow RAM using EEWR register, software calculates
2302 * checksum and updates the EEPROM and instructs the hardware to update
2305 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2310 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2312 /* Read the first word from the EEPROM. If this times out or fails, do
2313 * not continue or we could be in for a very long wait while every
2316 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2318 DEBUGOUT("EEPROM read failed\n");
2322 status = ixgbe_calc_eeprom_checksum_X550(hw);
2326 checksum = (u16)(status & 0xffff);
2328 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2333 status = ixgbe_update_flash_X550(hw);
2339 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2340 * @hw: pointer to hardware structure
2342 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2344 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2346 s32 status = IXGBE_SUCCESS;
2347 union ixgbe_hic_hdr2 buffer;
2349 DEBUGFUNC("ixgbe_update_flash_X550");
2351 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2352 buffer.req.buf_lenh = 0;
2353 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2354 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2356 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2358 IXGBE_HI_COMMAND_TIMEOUT, false);
2364 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2365 * @hw: pointer to hardware structure
2367 * Determines physical layer capabilities of the current configuration.
2369 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2371 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2372 u16 ext_ability = 0;
2374 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2376 hw->phy.ops.identify(hw);
2378 switch (hw->phy.type) {
2379 case ixgbe_phy_x550em_kr:
2380 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2381 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2383 case ixgbe_phy_x550em_kx4:
2384 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2385 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2387 case ixgbe_phy_x550em_ext_t:
2388 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2389 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2391 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2392 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2393 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2394 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2400 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2401 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2403 return physical_layer;
2407 * ixgbe_get_bus_info_x550em - Set PCI bus info
2408 * @hw: pointer to hardware structure
2410 * Sets bus link width and speed to unknown because X550em is
2413 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2416 DEBUGFUNC("ixgbe_get_bus_info_x550em");
2418 hw->bus.width = ixgbe_bus_width_unknown;
2419 hw->bus.speed = ixgbe_bus_speed_unknown;
2421 hw->mac.ops.set_lan_id(hw);
2423 return IXGBE_SUCCESS;
2427 * ixgbe_disable_rx_x550 - Disable RX unit
2429 * Enables the Rx DMA unit for x550
2431 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2433 u32 rxctrl, pfdtxgswc;
2435 struct ixgbe_hic_disable_rxen fw_cmd;
2437 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2439 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2440 if (rxctrl & IXGBE_RXCTRL_RXEN) {
2441 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2442 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2443 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2444 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2445 hw->mac.set_lben = true;
2447 hw->mac.set_lben = false;
2450 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2451 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2452 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2453 fw_cmd.port_number = (u8)hw->bus.lan_id;
2455 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2456 sizeof(struct ixgbe_hic_disable_rxen),
2457 IXGBE_HI_COMMAND_TIMEOUT, true);
2459 /* If we fail - disable RX using register write */
2461 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2462 if (rxctrl & IXGBE_RXCTRL_RXEN) {
2463 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2464 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2471 * ixgbe_enter_lplu_x550em - Transition to low power states
2472 * @hw: pointer to hardware structure
2474 * Configures Low Power Link Up on transition to low power states
2475 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2476 * X557 PHY immediately prior to entering LPLU.
2478 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2480 u16 autoneg_status, an_10g_cntl_reg, autoneg_reg, speed;
2482 ixgbe_link_speed lcd_speed;
2485 /* If blocked by MNG FW, then don't restart AN */
2486 if (ixgbe_check_reset_blocked(hw))
2487 return IXGBE_SUCCESS;
2489 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2490 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2493 if (status != IXGBE_SUCCESS)
2496 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2498 if (status != IXGBE_SUCCESS)
2501 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2502 * disabled, then force link down by entering low power mode.
2504 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS) ||
2505 !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2506 !(hw->wol_enabled || ixgbe_mng_present(hw)))
2507 return ixgbe_set_copper_phy_power(hw, FALSE);
2510 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2512 if (status != IXGBE_SUCCESS)
2515 /* If no valid LCD link speed, then force link down and exit. */
2516 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2517 return ixgbe_set_copper_phy_power(hw, FALSE);
2519 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2520 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2523 if (status != IXGBE_SUCCESS)
2526 /* clear everything but the speed bits */
2527 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2529 /* If current speed is already LCD, then exit. */
2530 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2531 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2532 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2533 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2536 /* Clear AN completed indication */
2537 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2538 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2541 if (status != IXGBE_SUCCESS)
2544 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2545 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2548 if (status != IXGBE_SUCCESS)
2551 status = hw->phy.ops.read_reg(hw,
2552 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2553 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2556 if (status != IXGBE_SUCCESS)
2559 save_autoneg = hw->phy.autoneg_advertised;
2561 /* Setup link at least common link speed */
2562 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
2564 /* restore autoneg from before setting lplu speed */
2565 hw->phy.autoneg_advertised = save_autoneg;
2571 * ixgbe_get_lcd_x550em - Determine lowest common denominator
2572 * @hw: pointer to hardware structure
2573 * @lcd_speed: pointer to lowest common link speed
2575 * Determine lowest common link speed with link partner.
2577 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2581 u16 word = hw->eeprom.ctrl_word_3;
2583 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2585 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2586 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2589 if (status != IXGBE_SUCCESS)
2592 /* If link partner advertised 1G, return 1G */
2593 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2594 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2598 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2599 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2600 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2603 /* Link partner not capable of lower speeds, return 10G */
2604 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2609 * ixgbe_setup_fc_X550em - Set up flow control
2610 * @hw: pointer to hardware structure
2612 * Called at init time to set up flow control.
2614 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
2616 s32 ret_val = IXGBE_SUCCESS;
2617 u32 pause, asm_dir, reg_val;
2619 DEBUGFUNC("ixgbe_setup_fc_X550em");
2621 /* Validate the requested mode */
2622 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2623 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2624 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2625 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2629 /* 10gig parts do not have a word in the EEPROM to determine the
2630 * default flow control setting, so we explicitly set it to full.
2632 if (hw->fc.requested_mode == ixgbe_fc_default)
2633 hw->fc.requested_mode = ixgbe_fc_full;
2635 /* Determine PAUSE and ASM_DIR bits. */
2636 switch (hw->fc.requested_mode) {
2641 case ixgbe_fc_tx_pause:
2645 case ixgbe_fc_rx_pause:
2646 /* Rx Flow control is enabled and Tx Flow control is
2647 * disabled by software override. Since there really
2648 * isn't a way to advertise that we are capable of RX
2649 * Pause ONLY, we will advertise that we support both
2650 * symmetric and asymmetric Rx PAUSE, as such we fall
2651 * through to the fc_full statement. Later, we will
2652 * disable the adapter's ability to send PAUSE frames.
2659 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2660 "Flow control param set incorrectly\n");
2661 ret_val = IXGBE_ERR_CONFIG;
2665 if (hw->phy.media_type == ixgbe_media_type_backplane) {
2666 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
2667 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2668 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2669 if (ret_val != IXGBE_SUCCESS)
2671 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2672 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2674 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2676 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2677 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
2678 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2679 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2681 /* Not all devices fully support AN. */
2682 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR)
2683 hw->fc.disable_fc_autoneg = true;
2691 * ixgbe_set_mux - Set mux for port 1 access with CS4227
2692 * @hw: pointer to hardware structure
2693 * @state: set mux if 1, clear if 0
2695 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2699 if (!hw->bus.lan_id)
2701 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2703 esdp |= IXGBE_ESDP_SDP1;
2705 esdp &= ~IXGBE_ESDP_SDP1;
2706 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2707 IXGBE_WRITE_FLUSH(hw);
2711 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2712 * @hw: pointer to hardware structure
2713 * @mask: Mask to specify which semaphore to acquire
2715 * Acquires the SWFW semaphore and sets the I2C MUX
2717 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2721 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
2723 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2727 if (mask & IXGBE_GSSR_I2C_MASK)
2728 ixgbe_set_mux(hw, 1);
2730 return IXGBE_SUCCESS;
2734 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2735 * @hw: pointer to hardware structure
2736 * @mask: Mask to specify which semaphore to release
2738 * Releases the SWFW semaphore and sets the I2C MUX
2740 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2742 DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
2744 if (mask & IXGBE_GSSR_I2C_MASK)
2745 ixgbe_set_mux(hw, 0);
2747 ixgbe_release_swfw_sync_X540(hw, mask);
2751 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2752 * @hw: pointer to hardware structure
2754 * Handle external Base T PHY interrupt. If high temperature
2755 * failure alarm then return error, else if link status change
2756 * then setup internal/external PHY link
2758 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2759 * failure alarm, else return PHY access status.
2761 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2766 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2768 if (status != IXGBE_SUCCESS)
2772 return ixgbe_setup_internal_phy_t_x550em(hw);
2774 return IXGBE_SUCCESS;
2778 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
2779 * @hw: pointer to hardware structure
2780 * @speed: new link speed
2781 * @autoneg_wait_to_complete: true when waiting for completion is needed
2783 * Setup internal/external PHY link speed based on link speed, then set
2784 * external PHY auto advertised link speed.
2786 * Returns error status for any failure
2788 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
2789 ixgbe_link_speed speed,
2790 bool autoneg_wait_to_complete)
2793 ixgbe_link_speed force_speed;
2795 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
2797 /* Setup internal/external PHY link speed to iXFI (10G), unless
2798 * only 1G is auto advertised then setup KX link.
2800 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2801 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2803 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2805 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
2807 if (status != IXGBE_SUCCESS)
2810 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
2814 * ixgbe_check_link_t_X550em - Determine link and speed status
2815 * @hw: pointer to hardware structure
2816 * @speed: pointer to link speed
2817 * @link_up: true when link is up
2818 * @link_up_wait_to_complete: bool used to wait for link up or not
2820 * Check that both the MAC and X557 external PHY have link.
2822 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
2823 bool *link_up, bool link_up_wait_to_complete)
2828 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2829 return IXGBE_ERR_CONFIG;
2831 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
2832 link_up_wait_to_complete);
2834 /* If check link fails or MAC link is not up, then return */
2835 if (status != IXGBE_SUCCESS || !(*link_up))
2838 /* MAC link is up, so check external PHY link.
2839 * Read this twice back to back to indicate current status.
2841 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2842 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2845 if (status != IXGBE_SUCCESS)
2848 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2849 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2852 if (status != IXGBE_SUCCESS)
2855 /* If external PHY link is not up, then indicate link not up */
2856 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
2859 return IXGBE_SUCCESS;
2863 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
2864 * @hw: pointer to hardware structure
2866 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
2870 status = ixgbe_reset_phy_generic(hw);
2872 if (status != IXGBE_SUCCESS)
2875 /* Configure Link Status Alarm and Temperature Threshold interrupts */
2876 return ixgbe_enable_lasi_ext_t_x550em(hw);