drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42
  43 /**
  44  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  45  *  @hw: pointer to hardware structure
  46  *
  47  *  Initialize the function pointers and assign the MAC type for X550.
  48  *  Does not touch the hardware.
  49  **/
  50 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  51 {
  52         struct ixgbe_mac_info *mac = &hw->mac;
  53         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  54         s32 ret_val;
  55
  56         DEBUGFUNC("ixgbe_init_ops_X550");
  57
  58         ret_val = ixgbe_init_ops_X540(hw);
  59         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  60         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  61         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  62         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  63         mac->ops.set_source_address_pruning =
  64                         ixgbe_set_source_address_pruning_X550;
  65         mac->ops.set_ethertype_anti_spoofing =
  66                         ixgbe_set_ethertype_anti_spoofing_X550;
  67
  68         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  69         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  70         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  71         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  72         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  73         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  74         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  75         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  76         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  77
  78         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  79         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  80         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  81         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  82         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  83         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
  84                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  85                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  86         }
  87         return ret_val;
  88 }
  89
  90 /**
  91  * ixgbe_read_cs4227 - Read CS4227 register
  92  * @hw: pointer to hardware structure
  93  * @reg: register number to write
  94  * @value: pointer to receive value read
  95  *
  96  * Returns status code
  97  **/
  98 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  99 {
 100         return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 101 }
 102
 103 /**
 104  * ixgbe_write_cs4227 - Write CS4227 register
 105  * @hw: pointer to hardware structure
 106  * @reg: register number to write
 107  * @value: value to write to register
 108  *
 109  * Returns status code
 110  **/
 111 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 112 {
 113         return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 114 }
 115
 116 /**
 117  * ixgbe_get_cs4227_status - Return CS4227 status
 118  * @hw: pointer to hardware structure
 119  *
 120  * Returns error if CS4227 not successfully initialized
 121  **/
 122 STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
 123 {
 124         s32 status;
 125         u16 value = 0;
 126         u16 reg_slice, reg_val;
 127         u8 retry;
 128
 129         for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) {
 130                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB,
 131                                            &value);
 132                 if (status != IXGBE_SUCCESS)
 133                         return status;
 134                 if (value == IXGBE_CS4227_GLOBAL_ID_VALUE)
 135                         break;
 136                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 137         }
 138         if (value != IXGBE_CS4227_GLOBAL_ID_VALUE)
 139                 return IXGBE_ERR_PHY;
 140
 141         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 142         if (status != IXGBE_SUCCESS)
 143                 return status;
 144
 145         /* If this is the first time after power-on, check the ucode.
 146          * Otherwise, this will disrupt link on all ports. Because we
 147          * can only do this the first time, we must check all ports,
 148          * not just our own.
 149          */
 150         if (value != IXGBE_CS4227_SCRATCH_VALUE) {
 151                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB;
 152                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
 153                 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
 154                 if (status != IXGBE_SUCCESS)
 155                         return status;
 156
 157                 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB;
 158                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
 159                 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
 160                 if (status != IXGBE_SUCCESS)
 161                         return status;
 162
 163                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (1 << 12);
 164                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
 165                 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
 166                 if (status != IXGBE_SUCCESS)
 167                         return status;
 168
 169                 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (1 << 12);
 170                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
 171                 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
 172                 if (status != IXGBE_SUCCESS)
 173                         return status;
 174
 175                 msec_delay(10);
 176         }
 177
 178         /* Verify that the ucode is operational on all ports. */
 179         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB;
 180         reg_val = 0xFFFF;
 181         status = ixgbe_read_cs4227(hw, reg_slice, &reg_val);
 182         if (status != IXGBE_SUCCESS)
 183                 return status;
 184         if (reg_val != 0)
 185                 return IXGBE_ERR_PHY;
 186
 187         reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB;
 188         reg_val = 0xFFFF;
 189         status = ixgbe_read_cs4227(hw, reg_slice, &reg_val);
 190         if (status != IXGBE_SUCCESS)
 191                 return status;
 192         if (reg_val != 0)
 193                 return IXGBE_ERR_PHY;
 194
 195         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (1 << 12);
 196         reg_val = 0xFFFF;
 197         status = ixgbe_read_cs4227(hw, reg_slice, &reg_val);
 198         if (status != IXGBE_SUCCESS)
 199                 return status;
 200         if (reg_val != 0)
 201                 return IXGBE_ERR_PHY;
 202
 203         reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (1 << 12);
 204         reg_val = 0xFFFF;
 205         status = ixgbe_read_cs4227(hw, reg_slice, &reg_val);
 206         if (status != IXGBE_SUCCESS)
 207                 return status;
 208         if (reg_val != 0)
 209                 return IXGBE_ERR_PHY;
 210
 211         /* Set scratch indicating that the diagnostic was successful. */
 212         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 213                                     IXGBE_CS4227_SCRATCH_VALUE);
 214         if (status != IXGBE_SUCCESS)
 215                 return status;
 216         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 217         if (status != IXGBE_SUCCESS)
 218                 return status;
 219         if (value != IXGBE_CS4227_SCRATCH_VALUE)
 220                 return IXGBE_ERR_PHY;
 221
 222         return IXGBE_SUCCESS;
 223 }
 224
 225 /**
 226  * ixgbe_read_pe - Read register from port expander
 227  * @hw: pointer to hardware structure
 228  * @reg: register number to read
 229  * @value: pointer to receive read value
 230  *
 231  * Returns status code
 232  **/
 233 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 234 {
 235         s32 status;
 236
 237         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 238         if (status != IXGBE_SUCCESS)
 239                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 240                               "port expander access failed with %d\n", status);
 241         return status;
 242 }
 243
 244 /**
 245  * ixgbe_write_pe - Write register to port expander
 246  * @hw: pointer to hardware structure
 247  * @reg: register number to write
 248  * @value: value to write
 249  *
 250  * Returns status code
 251  **/
 252 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 253 {
 254         s32 status;
 255
 256         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 257         if (status != IXGBE_SUCCESS)
 258                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 259                               "port expander access failed with %d\n", status);
 260         return status;
 261 }
 262
 263 /**
 264  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 265  * @hw: pointer to hardware structure
 266  *
 267  * Returns error code
 268  **/
 269 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 270 {
 271         s32 status;
 272         u8 reg;
 273
 274         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 275         if (status != IXGBE_SUCCESS)
 276                 return status;
 277         reg |= IXGBE_PE_BIT1;
 278         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 279         if (status != IXGBE_SUCCESS)
 280                 return status;
 281
 282         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 283         if (status != IXGBE_SUCCESS)
 284                 return status;
 285         reg &= ~IXGBE_PE_BIT1;
 286         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 287         if (status != IXGBE_SUCCESS)
 288                 return status;
 289
 290         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 291         if (status != IXGBE_SUCCESS)
 292                 return status;
 293         reg &= ~IXGBE_PE_BIT1;
 294         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 295         if (status != IXGBE_SUCCESS)
 296                 return status;
 297
 298         usec_delay(IXGBE_CS4227_RESET_HOLD);
 299
 300         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 301         if (status != IXGBE_SUCCESS)
 302                 return status;
 303         reg |= IXGBE_PE_BIT1;
 304         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 305         if (status != IXGBE_SUCCESS)
 306                 return status;
 307
 308         msec_delay(IXGBE_CS4227_RESET_DELAY);
 309
 310         return IXGBE_SUCCESS;
 311 }
 312
 313 /**
 314  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 315  * @hw: pointer to hardware structure
 316  **/
 317 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 318 {
 319         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 320         s32 status;
 321         u8 retry;
 322
 323         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 324                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 325                 if (status != IXGBE_SUCCESS) {
 326                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 327                                       "semaphore failed with %d\n", status);
 328                         return;
 329                 }
 330                 status = ixgbe_get_cs4227_status(hw);
 331                 if (status == IXGBE_SUCCESS) {
 332                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 333                         msec_delay(hw->eeprom.semaphore_delay);
 334                         return;
 335                 }
 336                 ixgbe_reset_cs4227(hw);
 337                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 338                 msec_delay(hw->eeprom.semaphore_delay);
 339         }
 340         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 341                       "Unable to initialize CS4227, err=%d\n", status);
 342 }
 343
 344 /**
 345  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 346  * @hw: pointer to hardware structure
 347  **/
 348 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 349 {
 350         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 351
 352         if (hw->bus.lan_id) {
 353                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 354                 esdp |= IXGBE_ESDP_SDP1_DIR;
 355         }
 356         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 357         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 358         IXGBE_WRITE_FLUSH(hw);
 359 }
 360
 361 /**
 362  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 363  * @hw: pointer to hardware structure
 364  *
 365  * Returns error code
 366  */
 367 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 368 {
 369         switch (hw->device_id) {
 370         case IXGBE_DEV_ID_X550EM_X_SFP:
 371                 /* set up for CS4227 usage */
 372                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 373                 ixgbe_setup_mux_ctl(hw);
 374                 ixgbe_check_cs4227(hw);
 375
 376                 return ixgbe_identify_module_generic(hw);
 377                 break;
 378         case IXGBE_DEV_ID_X550EM_X_KX4:
 379                 hw->phy.type = ixgbe_phy_x550em_kx4;
 380                 break;
 381         case IXGBE_DEV_ID_X550EM_X_KR:
 382                 hw->phy.type = ixgbe_phy_x550em_kr;
 383                 break;
 384         case IXGBE_DEV_ID_X550EM_X_1G_T:
 385         case IXGBE_DEV_ID_X550EM_X_10G_T:
 386                 return ixgbe_identify_phy_generic(hw);
 387         default:
 388                 break;
 389         }
 390         return IXGBE_SUCCESS;
 391 }
 392
 393 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 394                                      u32 device_type, u16 *phy_data)
 395 {
 396         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 397         return IXGBE_NOT_IMPLEMENTED;
 398 }
 399
 400 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 401                                       u32 device_type, u16 phy_data)
 402 {
 403         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 404         return IXGBE_NOT_IMPLEMENTED;
 405 }
 406
 407 /**
 408 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 409 *  @hw: pointer to hardware structure
 410 *
 411 *  Initialize the function pointers and for MAC type X550EM.
 412 *  Does not touch the hardware.
 413 **/
 414 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 415 {
 416         struct ixgbe_mac_info *mac = &hw->mac;
 417         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 418         struct ixgbe_phy_info *phy = &hw->phy;
 419         s32 ret_val;
 420
 421         DEBUGFUNC("ixgbe_init_ops_X550EM");
 422
 423         /* Similar to X550 so start there. */
 424         ret_val = ixgbe_init_ops_X550(hw);
 425
 426         /* Since this function eventually calls
 427          * ixgbe_init_ops_540 by design, we are setting
 428          * the pointers to NULL explicitly here to overwrite
 429          * the values being set in the x540 function.
 430          */
 431         /* Thermal sensor not supported in x550EM */
 432         mac->ops.get_thermal_sensor_data = NULL;
 433         mac->ops.init_thermal_sensor_thresh = NULL;
 434         mac->thermal_sensor_enabled = false;
 435
 436         /* FCOE not supported in x550EM */
 437         mac->ops.get_san_mac_addr = NULL;
 438         mac->ops.set_san_mac_addr = NULL;
 439         mac->ops.get_wwn_prefix = NULL;
 440         mac->ops.get_fcoe_boot_status = NULL;
 441
 442         /* IPsec not supported in x550EM */
 443         mac->ops.disable_sec_rx_path = NULL;
 444         mac->ops.enable_sec_rx_path = NULL;
 445
 446         /* AUTOC register is not present in x550EM. */
 447         mac->ops.prot_autoc_read = NULL;
 448         mac->ops.prot_autoc_write = NULL;
 449
 450         /* X550EM bus type is internal*/
 451         hw->bus.type = ixgbe_bus_type_internal;
 452         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 453
 454         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 455         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 456         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 457         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 458         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 459         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 460         mac->ops.get_supported_physical_layer =
 461                                     ixgbe_get_supported_physical_layer_X550em;
 462
 463         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 464                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 465         else
 466                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 467
 468         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 469         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 470
 471         if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
 472                 mac->ops.setup_eee = NULL;
 473
 474         /* PHY */
 475         phy->ops.init = ixgbe_init_phy_ops_X550em;
 476         phy->ops.identify = ixgbe_identify_phy_x550em;
 477         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 478                 phy->ops.set_phy_power = NULL;
 479
 480
 481         /* EEPROM */
 482         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 483         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 484         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 485         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 486         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 487         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 488         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 489         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 490
 491         return ret_val;
 492 }
 493
 494 /**
 495  *  ixgbe_dmac_config_X550
 496  *  @hw: pointer to hardware structure
 497  *
 498  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 499  *  When disabling dmac, dmac enable dmac bit is cleared.
 500  **/
 501 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 502 {
 503         u32 reg, high_pri_tc;
 504
 505         DEBUGFUNC("ixgbe_dmac_config_X550");
 506
 507         /* Disable DMA coalescing before configuring */
 508         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 509         reg &= ~IXGBE_DMACR_DMAC_EN;
 510         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 511
 512         /* Disable DMA Coalescing if the watchdog timer is 0 */
 513         if (!hw->mac.dmac_config.watchdog_timer)
 514                 goto out;
 515
 516         ixgbe_dmac_config_tcs_X550(hw);
 517
 518         /* Configure DMA Coalescing Control Register */
 519         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 520
 521         /* Set the watchdog timer in units of 40.96 usec */
 522         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 523         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 524
 525         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 526         /* If fcoe is enabled, set high priority traffic class */
 527         if (hw->mac.dmac_config.fcoe_en) {
 528                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 529                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 530                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 531         }
 532         reg |= IXGBE_DMACR_EN_MNG_IND;
 533
 534         /* Enable DMA coalescing after configuration */
 535         reg |= IXGBE_DMACR_DMAC_EN;
 536         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 537
 538 out:
 539         return IXGBE_SUCCESS;
 540 }
 541
 542 /**
 543  *  ixgbe_dmac_config_tcs_X550
 544  *  @hw: pointer to hardware structure
 545  *
 546  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 547  *  be cleared before configuring.
 548  **/
 549 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 550 {
 551         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 552
 553         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 554
 555         /* Configure DMA coalescing enabled */
 556         switch (hw->mac.dmac_config.link_speed) {
 557         case IXGBE_LINK_SPEED_100_FULL:
 558                 pb_headroom = IXGBE_DMACRXT_100M;
 559                 break;
 560         case IXGBE_LINK_SPEED_1GB_FULL:
 561                 pb_headroom = IXGBE_DMACRXT_1G;
 562                 break;
 563         default:
 564                 pb_headroom = IXGBE_DMACRXT_10G;
 565                 break;
 566         }
 567
 568         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 569                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 570
 571         /* Set the per Rx packet buffer receive threshold */
 572         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 573                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 574                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 575
 576                 if (tc < hw->mac.dmac_config.num_tcs) {
 577                         /* Get Rx PB size */
 578                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 579                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 580                                 IXGBE_RXPBSIZE_SHIFT;
 581
 582                         /* Calculate receive buffer threshold in kilobytes */
 583                         if (rx_pb_size > pb_headroom)
 584                                 rx_pb_size = rx_pb_size - pb_headroom;
 585                         else
 586                                 rx_pb_size = 0;
 587
 588                         /* Minimum of MFS shall be set for DMCTH */
 589                         reg |= (rx_pb_size > maxframe_size_kb) ?
 590                                 rx_pb_size : maxframe_size_kb;
 591                 }
 592                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 593         }
 594         return IXGBE_SUCCESS;
 595 }
 596
 597 /**
 598  *  ixgbe_dmac_update_tcs_X550
 599  *  @hw: pointer to hardware structure
 600  *
 601  *  Disables dmac, updates per TC settings, and then enables dmac.
 602  **/
 603 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 604 {
 605         u32 reg;
 606
 607         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 608
 609         /* Disable DMA coalescing before configuring */
 610         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 611         reg &= ~IXGBE_DMACR_DMAC_EN;
 612         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 613
 614         ixgbe_dmac_config_tcs_X550(hw);
 615
 616         /* Enable DMA coalescing after configuration */
 617         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 618         reg |= IXGBE_DMACR_DMAC_EN;
 619         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 620
 621         return IXGBE_SUCCESS;
 622 }
 623
 624 /**
 625  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 626  *  @hw: pointer to hardware structure
 627  *
 628  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 629  *  ixgbe_hw struct in order to set up EEPROM access.
 630  **/
 631 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 632 {
 633         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 634         u32 eec;
 635         u16 eeprom_size;
 636
 637         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 638
 639         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 640                 eeprom->semaphore_delay = 10;
 641                 eeprom->type = ixgbe_flash;
 642
 643                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 644                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 645                                     IXGBE_EEC_SIZE_SHIFT);
 646                 eeprom->word_size = 1 << (eeprom_size +
 647                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 648
 649                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 650                           eeprom->type, eeprom->word_size);
 651         }
 652
 653         return IXGBE_SUCCESS;
 654 }
 655
 656 /**
 657  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 658  *  @hw: pointer to the HW structure
 659  *  @enable_eee: boolean flag to enable EEE
 660  *
 661  *  Enable/disable EEE based on enable_eee flag.
 662  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 663  *  are modified.
 664  *
 665  **/
 666 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 667 {
 668         u32 eeer;
 669         u16 autoneg_eee_reg;
 670         u32 link_reg;
 671         s32 status;
 672         u32 fuse;
 673
 674         DEBUGFUNC("ixgbe_setup_eee_X550");
 675
 676         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 677         /* Enable or disable EEE per flag */
 678         if (enable_eee) {
 679                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 680
 681                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 682                         /* Advertise EEE capability */
 683                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 684                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 685
 686                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 687                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 688                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 689
 690                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 691                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 692                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 693                         /* Not supported on first revision. */
 694                         fuse = IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0));
 695                         if (!(fuse & IXGBE_FUSES0_REV1))
 696                                 return IXGBE_SUCCESS;
 697
 698                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 699                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 700                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 701                         if (status != IXGBE_SUCCESS)
 702                                 return status;
 703
 704                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 705                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 706
 707                         /* Don't advertise FEC capability when EEE enabled. */
 708                         link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 709
 710                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 711                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 712                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 713                         if (status != IXGBE_SUCCESS)
 714                                 return status;
 715                 }
 716         } else {
 717                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 718
 719                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 720                         /* Disable advertised EEE capability */
 721                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 722                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 723
 724                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 725                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 726                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 727
 728                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 729                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 730                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 731                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 732                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 733                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 734                         if (status != IXGBE_SUCCESS)
 735                                 return status;
 736
 737                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 738                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 739
 740                         /* Advertise FEC capability when EEE is disabled. */
 741                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 742
 743                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 744                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 745                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 746                         if (status != IXGBE_SUCCESS)
 747                                 return status;
 748                 }
 749         }
 750         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 751
 752         return IXGBE_SUCCESS;
 753 }
 754
 755 /**
 756  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 757  * @hw: pointer to hardware structure
 758  * @enable: enable or disable source address pruning
 759  * @pool: Rx pool to set source address pruning for
 760  **/
 761 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 762                                            unsigned int pool)
 763 {
 764         u64 pfflp;
 765
 766         /* max rx pool is 63 */
 767         if (pool > 63)
 768                 return;
 769
 770         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 771         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 772
 773         if (enable)
 774                 pfflp |= (1ULL << pool);
 775         else
 776                 pfflp &= ~(1ULL << pool);
 777
 778         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 779         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 780 }
 781
 782 /**
 783  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 784  *  @hw: pointer to hardware structure
 785  *  @enable: enable or disable switch for Ethertype anti-spoofing
 786  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 787  *
 788  **/
 789 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 790                 bool enable, int vf)
 791 {
 792         int vf_target_reg = vf >> 3;
 793         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 794         u32 pfvfspoof;
 795
 796         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 797
 798         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 799         if (enable)
 800                 pfvfspoof |= (1 << vf_target_shift);
 801         else
 802                 pfvfspoof &= ~(1 << vf_target_shift);
 803
 804         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 805 }
 806
 807 /**
 808  * ixgbe_iosf_wait - Wait for IOSF command completion
 809  * @hw: pointer to hardware structure
 810  * @ctrl: pointer to location to receive final IOSF control value
 811  *
 812  * Returns failing status on timeout
 813  *
 814  * Note: ctrl can be NULL if the IOSF control register value is not needed
 815  **/
 816 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
 817 {
 818         u32 i, command = 0;
 819
 820         /* Check every 10 usec to see if the address cycle completed.
 821          * The SB IOSF BUSY bit will clear when the operation is
 822          * complete
 823          */
 824         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 825                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 826                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 827                         break;
 828                 usec_delay(10);
 829         }
 830         if (ctrl)
 831                 *ctrl = command;
 832         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 833                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
 834                 return IXGBE_ERR_PHY;
 835         }
 836
 837         return IXGBE_SUCCESS;
 838 }
 839
 840 /**
 841  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 842  *  device
 843  *  @hw: pointer to hardware structure
 844  *  @reg_addr: 32 bit PHY register to write
 845  *  @device_type: 3 bit device type
 846  *  @data: Data to write to the register
 847  **/
 848 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 849                             u32 device_type, u32 data)
 850 {
 851         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 852         u32 command, error;
 853         s32 ret;
 854
 855         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
 856         if (ret != IXGBE_SUCCESS)
 857                 return ret;
 858
 859         ret = ixgbe_iosf_wait(hw, NULL);
 860         if (ret != IXGBE_SUCCESS)
 861                 goto out;
 862
 863         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 864                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 865
 866         /* Write IOSF control register */
 867         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 868
 869         /* Write IOSF data register */
 870         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 871
 872         ret = ixgbe_iosf_wait(hw, &command);
 873
 874         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 875                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 876                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 877                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 878                               "Failed to write, error %x\n", error);
 879                 ret = IXGBE_ERR_PHY;
 880         }
 881
 882 out:
 883         ixgbe_release_swfw_semaphore(hw, gssr);
 884         return ret;
 885 }
 886
 887 /**
 888  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 889  *  device
 890  *  @hw: pointer to hardware structure
 891  *  @reg_addr: 32 bit PHY register to write
 892  *  @device_type: 3 bit device type
 893  *  @phy_data: Pointer to read data from the register
 894  **/
 895 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 896                            u32 device_type, u32 *data)
 897 {
 898         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 899         u32 command, error;
 900         s32 ret;
 901
 902         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
 903         if (ret != IXGBE_SUCCESS)
 904                 return ret;
 905
 906         ret = ixgbe_iosf_wait(hw, NULL);
 907         if (ret != IXGBE_SUCCESS)
 908                 goto out;
 909
 910         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 911                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 912
 913         /* Write IOSF control register */
 914         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 915
 916         ret = ixgbe_iosf_wait(hw, &command);
 917
 918         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 919                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 920                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 921                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 922                                 "Failed to read, error %x\n", error);
 923                 ret = IXGBE_ERR_PHY;
 924         }
 925
 926         if (ret == IXGBE_SUCCESS)
 927                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 928
 929 out:
 930         ixgbe_release_swfw_semaphore(hw, gssr);
 931         return ret;
 932 }
 933
 934 /**
 935  *  ixgbe_disable_mdd_X550
 936  *  @hw: pointer to hardware structure
 937  *
 938  *  Disable malicious driver detection
 939  **/
 940 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
 941 {
 942         u32 reg;
 943
 944         DEBUGFUNC("ixgbe_disable_mdd_X550");
 945
 946         /* Disable MDD for TX DMA and interrupt */
 947         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 948         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 949         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 950
 951         /* Disable MDD for RX and interrupt */
 952         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 953         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 954         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 955 }
 956
 957 /**
 958  *  ixgbe_enable_mdd_X550
 959  *  @hw: pointer to hardware structure
 960  *
 961  *  Enable malicious driver detection
 962  **/
 963 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
 964 {
 965         u32 reg;
 966
 967         DEBUGFUNC("ixgbe_enable_mdd_X550");
 968
 969         /* Enable MDD for TX DMA and interrupt */
 970         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 971         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 972         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 973
 974         /* Enable MDD for RX and interrupt */
 975         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 976         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 977         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 978 }
 979
 980 /**
 981  *  ixgbe_restore_mdd_vf_X550
 982  *  @hw: pointer to hardware structure
 983  *  @vf: vf index
 984  *
 985  *  Restore VF that was disabled during malicious driver detection event
 986  **/
 987 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
 988 {
 989         u32 idx, reg, num_qs, start_q, bitmask;
 990
 991         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
 992
 993         /* Map VF to queues */
 994         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 995         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 996         case IXGBE_MRQC_VMDQRT8TCEN:
 997                 num_qs = 8;  /* 16 VFs / pools */
 998                 bitmask = 0x000000FF;
 999                 break;
1000         case IXGBE_MRQC_VMDQRSS32EN:
1001         case IXGBE_MRQC_VMDQRT4TCEN:
1002                 num_qs = 4;  /* 32 VFs / pools */
1003                 bitmask = 0x0000000F;
1004                 break;
1005         default:            /* 64 VFs / pools */
1006                 num_qs = 2;
1007                 bitmask = 0x00000003;
1008                 break;
1009         }
1010         start_q = vf * num_qs;
1011
1012         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1013         idx = start_q / 32;
1014         reg = 0;
1015         reg |= (bitmask << (start_q % 32));
1016         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1017         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1018 }
1019
1020 /**
1021  *  ixgbe_mdd_event_X550
1022  *  @hw: pointer to hardware structure
1023  *  @vf_bitmap: vf bitmap of malicious vfs
1024  *
1025  *  Handle malicious driver detection event.
1026  **/
1027 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1028 {
1029         u32 wqbr;
1030         u32 i, j, reg, q, shift, vf, idx;
1031
1032         DEBUGFUNC("ixgbe_mdd_event_X550");
1033
1034         /* figure out pool size for mapping to vf's */
1035         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1036         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1037         case IXGBE_MRQC_VMDQRT8TCEN:
1038                 shift = 3;  /* 16 VFs / pools */
1039                 break;
1040         case IXGBE_MRQC_VMDQRSS32EN:
1041         case IXGBE_MRQC_VMDQRT4TCEN:
1042                 shift = 2;  /* 32 VFs / pools */
1043                 break;
1044         default:
1045                 shift = 1;  /* 64 VFs / pools */
1046                 break;
1047         }
1048
1049         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1050         for (i = 0; i < 4; i++) {
1051                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1052                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1053
1054                 if (!wqbr)
1055                         continue;
1056
1057                 /* Get malicious queue */
1058                 for (j = 0; j < 32 && wqbr; j++) {
1059
1060                         if (!(wqbr & (1 << j)))
1061                                 continue;
1062
1063                         /* Get queue from bitmask */
1064                         q = j + (i * 32);
1065
1066                         /* Map queue to vf */
1067                         vf = (q >> shift);
1068
1069                         /* Set vf bit in vf_bitmap */
1070                         idx = vf / 32;
1071                         vf_bitmap[idx] |= (1 << (vf % 32));
1072                         wqbr &= ~(1 << j);
1073                 }
1074         }
1075 }
1076
1077 /**
1078  *  ixgbe_get_media_type_X550em - Get media type
1079  *  @hw: pointer to hardware structure
1080  *
1081  *  Returns the media type (fiber, copper, backplane)
1082  */
1083 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1084 {
1085         enum ixgbe_media_type media_type;
1086
1087         DEBUGFUNC("ixgbe_get_media_type_X550em");
1088
1089         /* Detect if there is a copper PHY attached. */
1090         switch (hw->device_id) {
1091         case IXGBE_DEV_ID_X550EM_X_KR:
1092         case IXGBE_DEV_ID_X550EM_X_KX4:
1093                 media_type = ixgbe_media_type_backplane;
1094                 break;
1095         case IXGBE_DEV_ID_X550EM_X_SFP:
1096                 media_type = ixgbe_media_type_fiber;
1097                 break;
1098         case IXGBE_DEV_ID_X550EM_X_1G_T:
1099         case IXGBE_DEV_ID_X550EM_X_10G_T:
1100                 media_type = ixgbe_media_type_copper;
1101                 break;
1102         default:
1103                 media_type = ixgbe_media_type_unknown;
1104                 break;
1105         }
1106         return media_type;
1107 }
1108
1109 /**
1110  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1111  *  @hw: pointer to hardware structure
1112  *  @linear: true if SFP module is linear
1113  */
1114 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1115 {
1116         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1117
1118         switch (hw->phy.sfp_type) {
1119         case ixgbe_sfp_type_not_present:
1120                 return IXGBE_ERR_SFP_NOT_PRESENT;
1121         case ixgbe_sfp_type_da_cu_core0:
1122         case ixgbe_sfp_type_da_cu_core1:
1123                 *linear = true;
1124                 break;
1125         case ixgbe_sfp_type_srlr_core0:
1126         case ixgbe_sfp_type_srlr_core1:
1127         case ixgbe_sfp_type_da_act_lmt_core0:
1128         case ixgbe_sfp_type_da_act_lmt_core1:
1129         case ixgbe_sfp_type_1g_sx_core0:
1130         case ixgbe_sfp_type_1g_sx_core1:
1131         case ixgbe_sfp_type_1g_lx_core0:
1132         case ixgbe_sfp_type_1g_lx_core1:
1133                 *linear = false;
1134                 break;
1135         case ixgbe_sfp_type_unknown:
1136         case ixgbe_sfp_type_1g_cu_core0:
1137         case ixgbe_sfp_type_1g_cu_core1:
1138         default:
1139                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1140         }
1141
1142         return IXGBE_SUCCESS;
1143 }
1144
1145 /**
1146  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1147  *  @hw: pointer to hardware structure
1148  *
1149  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1150  **/
1151 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1152 {
1153         s32 status;
1154         bool linear;
1155
1156         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1157
1158         status = ixgbe_identify_module_generic(hw);
1159
1160         if (status != IXGBE_SUCCESS)
1161                 return status;
1162
1163         /* Check if SFP module is supported */
1164         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1165
1166         return status;
1167 }
1168
1169 /**
1170  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1171  *  @hw: pointer to hardware structure
1172  */
1173 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1174 {
1175         s32 status;
1176         bool linear;
1177
1178         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1179
1180         /* Check if SFP module is supported */
1181         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1182
1183         if (status != IXGBE_SUCCESS)
1184                 return status;
1185
1186         ixgbe_init_mac_link_ops_X550em(hw);
1187         hw->phy.ops.reset = NULL;
1188
1189         return IXGBE_SUCCESS;
1190 }
1191
1192 /**
1193  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1194  *  @hw: pointer to hardware structure
1195  */
1196 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1197 {
1198         struct ixgbe_mac_info *mac = &hw->mac;
1199
1200         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1201
1202          switch (hw->mac.ops.get_media_type(hw)) {
1203          case ixgbe_media_type_fiber:
1204                 /* CS4227 does not support autoneg, so disable the laser control
1205                  * functions for SFP+ fiber
1206                  */
1207                 mac->ops.disable_tx_laser = NULL;
1208                 mac->ops.enable_tx_laser = NULL;
1209                 mac->ops.flap_tx_laser = NULL;
1210                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1211                 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1212                 mac->ops.set_rate_select_speed =
1213                                         ixgbe_set_soft_rate_select_speed;
1214                 break;
1215         case ixgbe_media_type_copper:
1216                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1217                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1218                 break;
1219         default:
1220                 break;
1221          }
1222 }
1223
1224 /**
1225  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1226  *  @hw: pointer to hardware structure
1227  *  @speed: pointer to link speed
1228  *  @autoneg: true when autoneg or autotry is enabled
1229  */
1230 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1231                                        ixgbe_link_speed *speed,
1232                                        bool *autoneg)
1233 {
1234         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1235
1236         /* SFP */
1237         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1238
1239                 /* CS4227 SFP must not enable auto-negotiation */
1240                 *autoneg = false;
1241
1242                 /* Check if 1G SFP module. */
1243                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1244                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1245                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1246                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1247                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1248                         return IXGBE_SUCCESS;
1249                 }
1250
1251                 /* Link capabilities are based on SFP */
1252                 if (hw->phy.multispeed_fiber)
1253                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1254                                  IXGBE_LINK_SPEED_1GB_FULL;
1255                 else
1256                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1257         } else {
1258                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1259                          IXGBE_LINK_SPEED_1GB_FULL;
1260                 *autoneg = true;
1261         }
1262
1263         return IXGBE_SUCCESS;
1264 }
1265
1266 /**
1267  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1268  * @hw: pointer to hardware structure
1269  * @lsc: pointer to boolean flag which indicates whether external Base T
1270  *       PHY interrupt is lsc
1271  *
1272  * Determime if external Base T PHY interrupt cause is high temperature
1273  * failure alarm or link status change.
1274  *
1275  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1276  * failure alarm, else return PHY access status.
1277  */
1278 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1279 {
1280         u32 status;
1281         u16 reg;
1282
1283         *lsc = false;
1284
1285         /* Vendor alarm triggered */
1286         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1287                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1288                                       &reg);
1289
1290         if (status != IXGBE_SUCCESS ||
1291             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1292                 return status;
1293
1294         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1295         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1296                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1297                                       &reg);
1298
1299         if (status != IXGBE_SUCCESS ||
1300             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1301             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1302                 return status;
1303
1304         /* High temperature failure alarm triggered */
1305         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1306                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1307                                       &reg);
1308
1309         if (status != IXGBE_SUCCESS)
1310                 return status;
1311
1312         /* If high temperature failure, then return over temp error and exit */
1313         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1314                 /* power down the PHY in case the PHY FW didn't already */
1315                 ixgbe_set_copper_phy_power(hw, false);
1316                 return IXGBE_ERR_OVERTEMP;
1317         }
1318
1319         /* Vendor alarm 2 triggered */
1320         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1321                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1322
1323         if (status != IXGBE_SUCCESS ||
1324             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1325                 return status;
1326
1327         /* link connect/disconnect event occurred */
1328         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1329                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1330
1331         if (status != IXGBE_SUCCESS)
1332                 return status;
1333
1334         /* Indicate LSC */
1335         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1336                 *lsc = true;
1337
1338         return IXGBE_SUCCESS;
1339 }
1340
1341 /**
1342  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1343  * @hw: pointer to hardware structure
1344  *
1345  * Enable link status change and temperature failure alarm for the external
1346  * Base T PHY
1347  *
1348  * Returns PHY access status
1349  */
1350 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1351 {
1352         u32 status;
1353         u16 reg;
1354         bool lsc;
1355
1356         /* Clear interrupt flags */
1357         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1358
1359         /* Enable link status change alarm */
1360         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1361                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1362
1363         if (status != IXGBE_SUCCESS)
1364                 return status;
1365
1366         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1367
1368         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1369                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1370
1371         if (status != IXGBE_SUCCESS)
1372                 return status;
1373
1374         /* Enables high temperature failure alarm */
1375         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1376                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1377                                       &reg);
1378
1379         if (status != IXGBE_SUCCESS)
1380                 return status;
1381
1382         reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;
1383
1384         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1385                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1386                                        reg);
1387
1388         if (status != IXGBE_SUCCESS)
1389                 return status;
1390
1391         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1392         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1393                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1394                                       &reg);
1395
1396         if (status != IXGBE_SUCCESS)
1397                 return status;
1398
1399         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1400                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1401
1402         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1403                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1404                                        reg);
1405
1406         if (status != IXGBE_SUCCESS)
1407                 return status;
1408
1409         /* Enable chip-wide vendor alarm */
1410         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1411                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1412                                       &reg);
1413
1414         if (status != IXGBE_SUCCESS)
1415                 return status;
1416
1417         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1418
1419         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1420                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1421                                        reg);
1422
1423         return status;
1424 }
1425
1426 /**
1427  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1428  *  @hw: pointer to hardware structure
1429  *  @speed: link speed
1430  *
1431  *  Configures the integrated KR PHY.
1432  **/
1433 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1434                                        ixgbe_link_speed speed)
1435 {
1436         s32 status;
1437         u32 reg_val;
1438
1439         status = ixgbe_read_iosf_sb_reg_x550(hw,
1440                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1441                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1442         if (status)
1443                 return status;
1444
1445         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1446         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1447                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1448
1449         /* Advertise 10G support. */
1450         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1451                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1452
1453         /* Advertise 1G support. */
1454         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1455                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1456
1457         /* Restart auto-negotiation. */
1458         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1459         status = ixgbe_write_iosf_sb_reg_x550(hw,
1460                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1461                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1462
1463         return status;
1464 }
1465
1466 /**
1467  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1468  *  @hw: pointer to hardware structure
1469  *
1470  *  Initialize any function pointers that were not able to be
1471  *  set during init_shared_code because the PHY/SFP type was
1472  *  not known.  Perform the SFP init if necessary.
1473  */
1474 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1475 {
1476         struct ixgbe_phy_info *phy = &hw->phy;
1477         ixgbe_link_speed speed;
1478         s32 ret_val;
1479
1480         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1481
1482         hw->mac.ops.set_lan_id(hw);
1483
1484         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1485                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1486                 ixgbe_setup_mux_ctl(hw);
1487
1488                 /* Save NW management interface connected on board. This is used
1489                  * to determine internal PHY mode.
1490                  */
1491                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1492
1493                 /* If internal PHY mode is KR, then initialize KR link */
1494                 if (phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) {
1495                         speed = IXGBE_LINK_SPEED_10GB_FULL |
1496                                 IXGBE_LINK_SPEED_1GB_FULL;
1497                         ret_val = ixgbe_setup_kr_speed_x550em(hw, speed);
1498                 }
1499
1500                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
1501         }
1502
1503         /* Identify the PHY or SFP module */
1504         ret_val = phy->ops.identify(hw);
1505         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1506                 return ret_val;
1507
1508         /* Setup function pointers based on detected hardware */
1509         ixgbe_init_mac_link_ops_X550em(hw);
1510         if (phy->sfp_type != ixgbe_sfp_type_unknown)
1511                 phy->ops.reset = NULL;
1512
1513         /* Set functions pointers based on phy type */
1514         switch (hw->phy.type) {
1515         case ixgbe_phy_x550em_kx4:
1516                 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
1517                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1518                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1519                 break;
1520         case ixgbe_phy_x550em_kr:
1521                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1522                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1523                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1524                 break;
1525         case ixgbe_phy_x550em_ext_t:
1526                 /* Save NW management interface connected on board. This is used
1527                  * to determine internal PHY mode
1528                  */
1529                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1530
1531                 /* If internal link mode is XFI, then setup iXFI internal link,
1532                  * else setup KR now.
1533                  */
1534                 if (!(phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1535                         phy->ops.setup_internal_link =
1536                                               ixgbe_setup_internal_phy_t_x550em;
1537                 } else {
1538                         speed = IXGBE_LINK_SPEED_10GB_FULL |
1539                                 IXGBE_LINK_SPEED_1GB_FULL;
1540                         ret_val = ixgbe_setup_kr_speed_x550em(hw, speed);
1541                 }
1542
1543                 /* setup SW LPLU only for first revision */
1544                 if (!(IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw,
1545                                                        IXGBE_FUSES0_GROUP(0))))
1546                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1547
1548                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1549                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1550                 break;
1551         default:
1552                 break;
1553         }
1554         return ret_val;
1555 }
1556
1557 /**
1558  *  ixgbe_reset_hw_X550em - Perform hardware reset
1559  *  @hw: pointer to hardware structure
1560  *
1561  *  Resets the hardware by resetting the transmit and receive units, masks
1562  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1563  *  reset.
1564  */
1565 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1566 {
1567         ixgbe_link_speed link_speed;
1568         s32 status;
1569         u32 ctrl = 0;
1570         u32 i;
1571         u32 hlreg0;
1572         bool link_up = false;
1573
1574         DEBUGFUNC("ixgbe_reset_hw_X550em");
1575
1576         /* Call adapter stop to disable Tx/Rx and clear interrupts */
1577         status = hw->mac.ops.stop_adapter(hw);
1578         if (status != IXGBE_SUCCESS)
1579                 return status;
1580
1581         /* flush pending Tx transactions */
1582         ixgbe_clear_tx_pending(hw);
1583
1584         /* PHY ops must be identified and initialized prior to reset */
1585
1586         /* Identify PHY and related function pointers */
1587         status = hw->phy.ops.init(hw);
1588
1589         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1590                 return status;
1591
1592         /* start the external PHY */
1593         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1594                 status = ixgbe_init_ext_t_x550em(hw);
1595                 if (status)
1596                         return status;
1597         }
1598
1599         /* Setup SFP module if there is one present. */
1600         if (hw->phy.sfp_setup_needed) {
1601                 status = hw->mac.ops.setup_sfp(hw);
1602                 hw->phy.sfp_setup_needed = false;
1603         }
1604
1605         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1606                 return status;
1607
1608         /* Reset PHY */
1609         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1610                 hw->phy.ops.reset(hw);
1611
1612 mac_reset_top:
1613         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1614          * If link reset is used when link is up, it might reset the PHY when
1615          * mng is using it.  If link is down or the flag to force full link
1616          * reset is set, then perform link reset.
1617          */
1618         ctrl = IXGBE_CTRL_LNK_RST;
1619         if (!hw->force_full_reset) {
1620                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1621                 if (link_up)
1622                         ctrl = IXGBE_CTRL_RST;
1623         }
1624
1625         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1626         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1627         IXGBE_WRITE_FLUSH(hw);
1628
1629         /* Poll for reset bit to self-clear meaning reset is complete */
1630         for (i = 0; i < 10; i++) {
1631                 usec_delay(1);
1632                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1633                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1634                         break;
1635         }
1636
1637         if (ctrl & IXGBE_CTRL_RST_MASK) {
1638                 status = IXGBE_ERR_RESET_FAILED;
1639                 DEBUGOUT("Reset polling failed to complete.\n");
1640         }
1641
1642         msec_delay(50);
1643
1644         /* Double resets are required for recovery from certain error
1645          * conditions.  Between resets, it is necessary to stall to
1646          * allow time for any pending HW events to complete.
1647          */
1648         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1649                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1650                 goto mac_reset_top;
1651         }
1652
1653         /* Store the permanent mac address */
1654         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1655
1656         /* Store MAC address from RAR0, clear receive address registers, and
1657          * clear the multicast table.  Also reset num_rar_entries to 128,
1658          * since we modify this value when programming the SAN MAC address.
1659          */
1660         hw->mac.num_rar_entries = 128;
1661         hw->mac.ops.init_rx_addrs(hw);
1662
1663         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
1664                 /* Config MDIO clock speed. */
1665                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1666                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
1667                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1668         }
1669
1670         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1671                 ixgbe_setup_mux_ctl(hw);
1672
1673         return status;
1674 }
1675
1676 /**
1677  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1678  * @hw: pointer to hardware structure
1679  */
1680 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1681 {
1682         u32 status;
1683         u16 reg;
1684
1685         status = hw->phy.ops.read_reg(hw,
1686                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1687                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1688                                       &reg);
1689
1690         if (status != IXGBE_SUCCESS)
1691                 return status;
1692
1693         /* If PHY FW reset completed bit is set then this is the first
1694          * SW instance after a power on so the PHY FW must be un-stalled.
1695          */
1696         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1697                 status = hw->phy.ops.read_reg(hw,
1698                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1699                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1700                                         &reg);
1701
1702                 if (status != IXGBE_SUCCESS)
1703                         return status;
1704
1705                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1706
1707                 status = hw->phy.ops.write_reg(hw,
1708                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1709                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1710                                         reg);
1711
1712                 if (status != IXGBE_SUCCESS)
1713                         return status;
1714         }
1715
1716         return status;
1717 }
1718
1719 /**
1720  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1721  *  @hw: pointer to hardware structure
1722  *
1723  *  Configures the integrated KR PHY.
1724  **/
1725 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1726 {
1727         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
1728 }
1729
1730 /**
1731  *  ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1732  *  @hw: pointer to hardware structure
1733  *
1734  *  Configures the integrated KX4 PHY.
1735  **/
1736 s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1737 {
1738         s32 status;
1739         u32 reg_val;
1740
1741         status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1742                 IXGBE_SB_IOSF_TARGET_KX4_PCS, &reg_val);
1743         if (status)
1744                 return status;
1745
1746         reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1747                         IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1748
1749         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1750
1751         /* Advertise 10G support. */
1752         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1753                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1754
1755         /* Advertise 1G support. */
1756         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1757                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1758
1759         /* Restart auto-negotiation. */
1760         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1761         status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1762                 IXGBE_SB_IOSF_TARGET_KX4_PCS, reg_val);
1763
1764         return status;
1765 }
1766
1767 /**
1768  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1769  *  @hw: pointer to hardware structure
1770  *  @speed: the link speed to force
1771  *
1772  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1773  *  internal and external PHY at a specific speed, without autonegotiation.
1774  **/
1775 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1776 {
1777         s32 status;
1778         u32 reg_val;
1779
1780         /* Disable AN and force speed to 10G Serial. */
1781         status = ixgbe_read_iosf_sb_reg_x550(hw,
1782                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1783                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1784         if (status != IXGBE_SUCCESS)
1785                 return status;
1786
1787         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1788         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1789
1790         /* Select forced link speed for internal PHY. */
1791         switch (*speed) {
1792         case IXGBE_LINK_SPEED_10GB_FULL:
1793                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1794                 break;
1795         case IXGBE_LINK_SPEED_1GB_FULL:
1796                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1797                 break;
1798         default:
1799                 /* Other link speeds are not supported by internal KR PHY. */
1800                 return IXGBE_ERR_LINK_SETUP;
1801         }
1802
1803         status = ixgbe_write_iosf_sb_reg_x550(hw,
1804                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1805                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1806         if (status != IXGBE_SUCCESS)
1807                 return status;
1808
1809         /* Disable training protocol FSM. */
1810         status = ixgbe_read_iosf_sb_reg_x550(hw,
1811                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1812                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1813         if (status != IXGBE_SUCCESS)
1814                 return status;
1815         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1816         status = ixgbe_write_iosf_sb_reg_x550(hw,
1817                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1818                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1819         if (status != IXGBE_SUCCESS)
1820                 return status;
1821
1822         /* Disable Flex from training TXFFE. */
1823         status = ixgbe_read_iosf_sb_reg_x550(hw,
1824                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1825                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1826         if (status != IXGBE_SUCCESS)
1827                 return status;
1828         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1829         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1830         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1831         status = ixgbe_write_iosf_sb_reg_x550(hw,
1832                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1833                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1834         if (status != IXGBE_SUCCESS)
1835                 return status;
1836         status = ixgbe_read_iosf_sb_reg_x550(hw,
1837                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1838                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1839         if (status != IXGBE_SUCCESS)
1840                 return status;
1841         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1842         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1843         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1844         status = ixgbe_write_iosf_sb_reg_x550(hw,
1845                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1846                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1847         if (status != IXGBE_SUCCESS)
1848                 return status;
1849
1850         /* Enable override for coefficients. */
1851         status = ixgbe_read_iosf_sb_reg_x550(hw,
1852                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1853                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1854         if (status != IXGBE_SUCCESS)
1855                 return status;
1856         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1857         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1858         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1859         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1860         status = ixgbe_write_iosf_sb_reg_x550(hw,
1861                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1862                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1863         if (status != IXGBE_SUCCESS)
1864                 return status;
1865
1866         /* Toggle port SW reset by AN reset. */
1867         status = ixgbe_read_iosf_sb_reg_x550(hw,
1868                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1869                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1870         if (status != IXGBE_SUCCESS)
1871                 return status;
1872         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1873         status = ixgbe_write_iosf_sb_reg_x550(hw,
1874                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1875                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1876
1877         return status;
1878 }
1879
1880 /**
1881  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
1882  * @hw: address of hardware structure
1883  * @link_up: address of boolean to indicate link status
1884  *
1885  * Returns error code if unable to get link status.
1886  */
1887 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
1888 {
1889         u32 ret;
1890         u16 autoneg_status;
1891
1892         *link_up = false;
1893
1894         /* read this twice back to back to indicate current status */
1895         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1896                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1897                                    &autoneg_status);
1898         if (ret != IXGBE_SUCCESS)
1899                 return ret;
1900
1901         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1902                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1903                                    &autoneg_status);
1904         if (ret != IXGBE_SUCCESS)
1905                 return ret;
1906
1907         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
1908
1909         return IXGBE_SUCCESS;
1910 }
1911
1912 /**
1913  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
1914  *  @hw: pointer to hardware structure
1915  *
1916  *  Configure the external PHY and the integrated KR PHY for SFP support.
1917  **/
1918 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1919                                     ixgbe_link_speed speed,
1920                                     bool autoneg_wait_to_complete)
1921 {
1922         s32 ret_val;
1923         u16 reg_slice, reg_val;
1924         bool setup_linear = false;
1925         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1926
1927         /* Check if SFP module is supported and linear */
1928         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1929
1930         /* If no SFP module present, then return success. Return success since
1931          * there is no reason to configure CS4227 and SFP not present error is
1932          * not excepted in the setup MAC link flow.
1933          */
1934         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1935                 return IXGBE_SUCCESS;
1936
1937         if (ret_val != IXGBE_SUCCESS)
1938                 return ret_val;
1939
1940         /* Configure CS4227 for LINE connection rate then type. */
1941         reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB + (hw->bus.lan_id << 12);
1942         reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000;
1943         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1944                                            reg_val);
1945
1946         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1947         if (setup_linear)
1948                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1949         else
1950                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1951         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1952                                            reg_val);
1953
1954         /* Configure CS4227 for HOST connection rate then type. */
1955         reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB + (hw->bus.lan_id << 12);
1956         reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000;
1957         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1958                                            reg_val);
1959
1960         reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (hw->bus.lan_id << 12);
1961         if (setup_linear)
1962                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1963         else
1964                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1965         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1966                                            reg_val);
1967
1968         /* If internal link mode is XFI, then setup XFI internal link. */
1969         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE))
1970                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
1971
1972         return ret_val;
1973 }
1974
1975 /**
1976  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1977  * @hw: point to hardware structure
1978  *
1979  * Configures the link between the integrated KR PHY and the external X557 PHY
1980  * The driver will call this function when it gets a link status change
1981  * interrupt from the X557 PHY. This function configures the link speed
1982  * between the PHYs to match the link speed of the BASE-T link.
1983  *
1984  * A return of a non-zero value indicates an error, and the base driver should
1985  * not report link up.
1986  */
1987 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
1988 {
1989         ixgbe_link_speed force_speed;
1990         bool link_up;
1991         u32 status;
1992         u16 speed;
1993
1994         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1995                 return IXGBE_ERR_CONFIG;
1996
1997         /* If link is not up, then there is no setup necessary so return  */
1998         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1999         if (status != IXGBE_SUCCESS)
2000                 return status;
2001
2002         if (!link_up)
2003                 return IXGBE_SUCCESS;
2004
2005         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2006                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2007                                       &speed);
2008         if (status != IXGBE_SUCCESS)
2009                 return status;
2010
2011         /* If link is not still up, then no setup is necessary so return */
2012         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2013         if (status != IXGBE_SUCCESS)
2014                 return status;
2015         if (!link_up)
2016                 return IXGBE_SUCCESS;
2017
2018         /* clear everything but the speed and duplex bits */
2019         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2020
2021         switch (speed) {
2022         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2023                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2024                 break;
2025         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2026                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2027                 break;
2028         default:
2029                 /* Internal PHY does not support anything else */
2030                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2031         }
2032
2033         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2034 }
2035
2036 /**
2037  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
2038  *  @hw: pointer to hardware structure
2039  *
2040  *  Configures the integrated KR PHY to use internal loopback mode.
2041  **/
2042 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
2043 {
2044         s32 status;
2045         u32 reg_val;
2046
2047         /* Disable AN and force speed to 10G Serial. */
2048         status = ixgbe_read_iosf_sb_reg_x550(hw,
2049                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2050                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2051         if (status != IXGBE_SUCCESS)
2052                 return status;
2053         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2054         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2055         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2056         status = ixgbe_write_iosf_sb_reg_x550(hw,
2057                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2058                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2059         if (status != IXGBE_SUCCESS)
2060                 return status;
2061
2062         /* Set near-end loopback clocks. */
2063         status = ixgbe_read_iosf_sb_reg_x550(hw,
2064                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2065                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2066         if (status != IXGBE_SUCCESS)
2067                 return status;
2068         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2069         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2070         status = ixgbe_write_iosf_sb_reg_x550(hw,
2071                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2072                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2073         if (status != IXGBE_SUCCESS)
2074                 return status;
2075
2076         /* Set loopback enable. */
2077         status = ixgbe_read_iosf_sb_reg_x550(hw,
2078                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2079                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2080         if (status != IXGBE_SUCCESS)
2081                 return status;
2082         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2083         status = ixgbe_write_iosf_sb_reg_x550(hw,
2084                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2085                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2086         if (status != IXGBE_SUCCESS)
2087                 return status;
2088
2089         /* Training bypass. */
2090         status = ixgbe_read_iosf_sb_reg_x550(hw,
2091                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2092                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2093         if (status != IXGBE_SUCCESS)
2094                 return status;
2095         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2096         status = ixgbe_write_iosf_sb_reg_x550(hw,
2097                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2098                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2099
2100         return status;
2101 }
2102
2103 /**
2104  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2105  *  assuming that the semaphore is already obtained.
2106  *  @hw: pointer to hardware structure
2107  *  @offset: offset of  word in the EEPROM to read
2108  *  @data: word read from the EEPROM
2109  *
2110  *  Reads a 16 bit word from the EEPROM using the hostif.
2111  **/
2112 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2113                                    u16 *data)
2114 {
2115         s32 status;
2116         struct ixgbe_hic_read_shadow_ram buffer;
2117
2118         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2119         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2120         buffer.hdr.req.buf_lenh = 0;
2121         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2122         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2123
2124         /* convert offset from words to bytes */
2125         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2126         /* one word */
2127         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2128
2129         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2130                                               sizeof(buffer),
2131                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2132
2133         if (status)
2134                 return status;
2135
2136         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2137                                           FW_NVM_DATA_OFFSET);
2138
2139         return 0;
2140 }
2141
2142 /**
2143  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2144  *  @hw: pointer to hardware structure
2145  *  @offset: offset of  word in the EEPROM to read
2146  *  @data: word read from the EEPROM
2147  *
2148  *  Reads a 16 bit word from the EEPROM using the hostif.
2149  **/
2150 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2151                               u16 *data)
2152 {
2153         s32 status = IXGBE_SUCCESS;
2154
2155         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2156
2157         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2158             IXGBE_SUCCESS) {
2159                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2160                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2161         } else {
2162                 status = IXGBE_ERR_SWFW_SYNC;
2163         }
2164
2165         return status;
2166 }
2167
2168 /**
2169  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2170  *  @hw: pointer to hardware structure
2171  *  @offset: offset of  word in the EEPROM to read
2172  *  @words: number of words
2173  *  @data: word(s) read from the EEPROM
2174  *
2175  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
2176  **/
2177 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2178                                      u16 offset, u16 words, u16 *data)
2179 {
2180         struct ixgbe_hic_read_shadow_ram buffer;
2181         u32 current_word = 0;
2182         u16 words_to_read;
2183         s32 status;
2184         u32 i;
2185
2186         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2187
2188         /* Take semaphore for the entire operation. */
2189         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2190         if (status) {
2191                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2192                 return status;
2193         }
2194         while (words) {
2195                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2196                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2197                 else
2198                         words_to_read = words;
2199
2200                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2201                 buffer.hdr.req.buf_lenh = 0;
2202                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2203                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2204
2205                 /* convert offset from words to bytes */
2206                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2207                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2208
2209                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2210                                                       sizeof(buffer),
2211                                                       IXGBE_HI_COMMAND_TIMEOUT,
2212                                                       false);
2213
2214                 if (status) {
2215                         DEBUGOUT("Host interface command failed\n");
2216                         goto out;
2217                 }
2218
2219                 for (i = 0; i < words_to_read; i++) {
2220                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
2221                                   2 * i;
2222                         u32 value = IXGBE_READ_REG(hw, reg);
2223
2224                         data[current_word] = (u16)(value & 0xffff);
2225                         current_word++;
2226                         i++;
2227                         if (i < words_to_read) {
2228                                 value >>= 16;
2229                                 data[current_word] = (u16)(value & 0xffff);
2230                                 current_word++;
2231                         }
2232                 }
2233                 words -= words_to_read;
2234         }
2235
2236 out:
2237         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2238         return status;
2239 }
2240
2241 /**
2242  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2243  *  @hw: pointer to hardware structure
2244  *  @offset: offset of  word in the EEPROM to write
2245  *  @data: word write to the EEPROM
2246  *
2247  *  Write a 16 bit word to the EEPROM using the hostif.
2248  **/
2249 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2250                                     u16 data)
2251 {
2252         s32 status;
2253         struct ixgbe_hic_write_shadow_ram buffer;
2254
2255         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
2256
2257         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
2258         buffer.hdr.req.buf_lenh = 0;
2259         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
2260         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2261
2262          /* one word */
2263         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2264         buffer.data = data;
2265         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2266
2267         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2268                                               sizeof(buffer),
2269                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2270
2271         return status;
2272 }
2273
2274 /**
2275  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2276  *  @hw: pointer to hardware structure
2277  *  @offset: offset of  word in the EEPROM to write
2278  *  @data: word write to the EEPROM
2279  *
2280  *  Write a 16 bit word to the EEPROM using the hostif.
2281  **/
2282 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2283                                u16 data)
2284 {
2285         s32 status = IXGBE_SUCCESS;
2286
2287         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2288
2289         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2290             IXGBE_SUCCESS) {
2291                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2292                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2293         } else {
2294                 DEBUGOUT("write ee hostif failed to get semaphore");
2295                 status = IXGBE_ERR_SWFW_SYNC;
2296         }
2297
2298         return status;
2299 }
2300
2301 /**
2302  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2303  *  @hw: pointer to hardware structure
2304  *  @offset: offset of  word in the EEPROM to write
2305  *  @words: number of words
2306  *  @data: word(s) write to the EEPROM
2307  *
2308  *  Write a 16 bit word(s) to the EEPROM using the hostif.
2309  **/
2310 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2311                                       u16 offset, u16 words, u16 *data)
2312 {
2313         s32 status = IXGBE_SUCCESS;
2314         u32 i = 0;
2315
2316         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2317
2318         /* Take semaphore for the entire operation. */
2319         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2320         if (status != IXGBE_SUCCESS) {
2321                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2322                 goto out;
2323         }
2324
2325         for (i = 0; i < words; i++) {
2326                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2327                                                          data[i]);
2328
2329                 if (status != IXGBE_SUCCESS) {
2330                         DEBUGOUT("Eeprom buffered write failed\n");
2331                         break;
2332                 }
2333         }
2334
2335         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2336 out:
2337
2338         return status;
2339 }
2340
2341 /**
2342  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2343  * @hw: pointer to hardware structure
2344  * @ptr: pointer offset in eeprom
2345  * @size: size of section pointed by ptr, if 0 first word will be used as size
2346  * @csum: address of checksum to update
2347  *
2348  * Returns error status for any failure
2349  */
2350 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2351                                    u16 size, u16 *csum, u16 *buffer,
2352                                    u32 buffer_size)
2353 {
2354         u16 buf[256];
2355         s32 status;
2356         u16 length, bufsz, i, start;
2357         u16 *local_buffer;
2358
2359         bufsz = sizeof(buf) / sizeof(buf[0]);
2360
2361         /* Read a chunk at the pointer location */
2362         if (!buffer) {
2363                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2364                 if (status) {
2365                         DEBUGOUT("Failed to read EEPROM image\n");
2366                         return status;
2367                 }
2368                 local_buffer = buf;
2369         } else {
2370                 if (buffer_size < ptr)
2371                         return  IXGBE_ERR_PARAM;
2372                 local_buffer = &buffer[ptr];
2373         }
2374
2375         if (size) {
2376                 start = 0;
2377                 length = size;
2378         } else {
2379                 start = 1;
2380                 length = local_buffer[0];
2381
2382                 /* Skip pointer section if length is invalid. */
2383                 if (length == 0xFFFF || length == 0 ||
2384                     (ptr + length) >= hw->eeprom.word_size)
2385                         return IXGBE_SUCCESS;
2386         }
2387
2388         if (buffer && ((u32)start + (u32)length > buffer_size))
2389                 return IXGBE_ERR_PARAM;
2390
2391         for (i = start; length; i++, length--) {
2392                 if (i == bufsz && !buffer) {
2393                         ptr += bufsz;
2394                         i = 0;
2395                         if (length < bufsz)
2396                                 bufsz = length;
2397
2398                         /* Read a chunk at the pointer location */
2399                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2400                                                                   bufsz, buf);
2401                         if (status) {
2402                                 DEBUGOUT("Failed to read EEPROM image\n");
2403                                 return status;
2404                         }
2405                 }
2406                 *csum += local_buffer[i];
2407         }
2408         return IXGBE_SUCCESS;
2409 }
2410
2411 /**
2412  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2413  *  @hw: pointer to hardware structure
2414  *  @buffer: pointer to buffer containing calculated checksum
2415  *  @buffer_size: size of buffer
2416  *
2417  *  Returns a negative error code on error, or the 16-bit checksum
2418  **/
2419 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2420 {
2421         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2422         u16 *local_buffer;
2423         s32 status;
2424         u16 checksum = 0;
2425         u16 pointer, i, size;
2426
2427         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2428
2429         hw->eeprom.ops.init_params(hw);
2430
2431         if (!buffer) {
2432                 /* Read pointer area */
2433                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2434                                                      IXGBE_EEPROM_LAST_WORD + 1,
2435                                                      eeprom_ptrs);
2436                 if (status) {
2437                         DEBUGOUT("Failed to read EEPROM image\n");
2438                         return status;
2439                 }
2440                 local_buffer = eeprom_ptrs;
2441         } else {
2442                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2443                         return IXGBE_ERR_PARAM;
2444                 local_buffer = buffer;
2445         }
2446
2447         /*
2448          * For X550 hardware include 0x0-0x41 in the checksum, skip the
2449          * checksum word itself
2450          */
2451         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2452                 if (i != IXGBE_EEPROM_CHECKSUM)
2453                         checksum += local_buffer[i];
2454
2455         /*
2456          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
2457          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2458          */
2459         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2460                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2461                         continue;
2462
2463                 pointer = local_buffer[i];
2464
2465                 /* Skip pointer section if the pointer is invalid. */
2466                 if (pointer == 0xFFFF || pointer == 0 ||
2467                     pointer >= hw->eeprom.word_size)
2468                         continue;
2469
2470                 switch (i) {
2471                 case IXGBE_PCIE_GENERAL_PTR:
2472                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2473                         break;
2474                 case IXGBE_PCIE_CONFIG0_PTR:
2475                 case IXGBE_PCIE_CONFIG1_PTR:
2476                         size = IXGBE_PCIE_CONFIG_SIZE;
2477                         break;
2478                 default:
2479                         size = 0;
2480                         break;
2481                 }
2482
2483                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2484                                                 buffer, buffer_size);
2485                 if (status)
2486                         return status;
2487         }
2488
2489         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2490
2491         return (s32)checksum;
2492 }
2493
2494 /**
2495  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2496  *  @hw: pointer to hardware structure
2497  *
2498  *  Returns a negative error code on error, or the 16-bit checksum
2499  **/
2500 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2501 {
2502         return ixgbe_calc_checksum_X550(hw, NULL, 0);
2503 }
2504
2505 /**
2506  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2507  *  @hw: pointer to hardware structure
2508  *  @checksum_val: calculated checksum
2509  *
2510  *  Performs checksum calculation and validates the EEPROM checksum.  If the
2511  *  caller does not need checksum_val, the value can be NULL.
2512  **/
2513 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2514 {
2515         s32 status;
2516         u16 checksum;
2517         u16 read_checksum = 0;
2518
2519         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2520
2521         /* Read the first word from the EEPROM. If this times out or fails, do
2522          * not continue or we could be in for a very long wait while every
2523          * EEPROM read fails
2524          */
2525         status = hw->eeprom.ops.read(hw, 0, &checksum);
2526         if (status) {
2527                 DEBUGOUT("EEPROM read failed\n");
2528                 return status;
2529         }
2530
2531         status = hw->eeprom.ops.calc_checksum(hw);
2532         if (status < 0)
2533                 return status;
2534
2535         checksum = (u16)(status & 0xffff);
2536
2537         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2538                                            &read_checksum);
2539         if (status)
2540                 return status;
2541
2542         /* Verify read checksum from EEPROM is the same as
2543          * calculated checksum
2544          */
2545         if (read_checksum != checksum) {
2546                 status = IXGBE_ERR_EEPROM_CHECKSUM;
2547                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2548                              "Invalid EEPROM checksum");
2549         }
2550
2551         /* If the user cares, return the calculated checksum */
2552         if (checksum_val)
2553                 *checksum_val = checksum;
2554
2555         return status;
2556 }
2557
2558 /**
2559  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2560  * @hw: pointer to hardware structure
2561  *
2562  * After writing EEPROM to shadow RAM using EEWR register, software calculates
2563  * checksum and updates the EEPROM and instructs the hardware to update
2564  * the flash.
2565  **/
2566 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2567 {
2568         s32 status;
2569         u16 checksum = 0;
2570
2571         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2572
2573         /* Read the first word from the EEPROM. If this times out or fails, do
2574          * not continue or we could be in for a very long wait while every
2575          * EEPROM read fails
2576          */
2577         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2578         if (status) {
2579                 DEBUGOUT("EEPROM read failed\n");
2580                 return status;
2581         }
2582
2583         status = ixgbe_calc_eeprom_checksum_X550(hw);
2584         if (status < 0)
2585                 return status;
2586
2587         checksum = (u16)(status & 0xffff);
2588
2589         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2590                                             checksum);
2591         if (status)
2592                 return status;
2593
2594         status = ixgbe_update_flash_X550(hw);
2595
2596         return status;
2597 }
2598
2599 /**
2600  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2601  *  @hw: pointer to hardware structure
2602  *
2603  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2604  **/
2605 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2606 {
2607         s32 status = IXGBE_SUCCESS;
2608         union ixgbe_hic_hdr2 buffer;
2609
2610         DEBUGFUNC("ixgbe_update_flash_X550");
2611
2612         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2613         buffer.req.buf_lenh = 0;
2614         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2615         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2616
2617         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2618                                               sizeof(buffer),
2619                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2620
2621         return status;
2622 }
2623
2624 /**
2625  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2626  *  @hw: pointer to hardware structure
2627  *
2628  *  Determines physical layer capabilities of the current configuration.
2629  **/
2630 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2631 {
2632         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2633         u16 ext_ability = 0;
2634
2635         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2636
2637         hw->phy.ops.identify(hw);
2638
2639         switch (hw->phy.type) {
2640         case ixgbe_phy_x550em_kr:
2641                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2642                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2643                 break;
2644         case ixgbe_phy_x550em_kx4:
2645                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2646                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2647                 break;
2648         case ixgbe_phy_x550em_ext_t:
2649                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2650                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2651                                      &ext_ability);
2652                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2653                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2654                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2655                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2656                 break;
2657         default:
2658                 break;
2659         }
2660
2661         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2662                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2663
2664         return physical_layer;
2665 }
2666
2667 /**
2668  * ixgbe_get_bus_info_x550em - Set PCI bus info
2669  * @hw: pointer to hardware structure
2670  *
2671  * Sets bus link width and speed to unknown because X550em is
2672  * not a PCI device.
2673  **/
2674 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2675 {
2676
2677         DEBUGFUNC("ixgbe_get_bus_info_x550em");
2678
2679         hw->bus.width = ixgbe_bus_width_unknown;
2680         hw->bus.speed = ixgbe_bus_speed_unknown;
2681
2682         hw->mac.ops.set_lan_id(hw);
2683
2684         return IXGBE_SUCCESS;
2685 }
2686
2687 /**
2688  * ixgbe_disable_rx_x550 - Disable RX unit
2689  *
2690  * Enables the Rx DMA unit for x550
2691  **/
2692 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2693 {
2694         u32 rxctrl, pfdtxgswc;
2695         s32 status;
2696         struct ixgbe_hic_disable_rxen fw_cmd;
2697
2698         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2699
2700         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2701         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2702                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2703                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2704                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2705                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2706                         hw->mac.set_lben = true;
2707                 } else {
2708                         hw->mac.set_lben = false;
2709                 }
2710
2711                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2712                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2713                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2714                 fw_cmd.port_number = (u8)hw->bus.lan_id;
2715
2716                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2717                                         sizeof(struct ixgbe_hic_disable_rxen),
2718                                         IXGBE_HI_COMMAND_TIMEOUT, true);
2719
2720                 /* If we fail - disable RX using register write */
2721                 if (status) {
2722                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2723                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2724                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2725                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2726                         }
2727                 }
2728         }
2729 }
2730
2731 /**
2732  * ixgbe_enter_lplu_x550em - Transition to low power states
2733  *  @hw: pointer to hardware structure
2734  *
2735  * Configures Low Power Link Up on transition to low power states
2736  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2737  * X557 PHY immediately prior to entering LPLU.
2738  **/
2739 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2740 {
2741         u16 an_10g_cntl_reg, autoneg_reg, speed;
2742         s32 status;
2743         ixgbe_link_speed lcd_speed;
2744         u32 save_autoneg;
2745         bool link_up;
2746
2747         /* SW LPLU not required on later HW revisions. */
2748         if (IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)))
2749                 return IXGBE_SUCCESS;
2750
2751         /* If blocked by MNG FW, then don't restart AN */
2752         if (ixgbe_check_reset_blocked(hw))
2753                 return IXGBE_SUCCESS;
2754
2755         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2756         if (status != IXGBE_SUCCESS)
2757                 return status;
2758
2759         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2760
2761         if (status != IXGBE_SUCCESS)
2762                 return status;
2763
2764         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2765          * disabled, then force link down by entering low power mode.
2766          */
2767         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2768             !(hw->wol_enabled || ixgbe_mng_present(hw)))
2769                 return ixgbe_set_copper_phy_power(hw, FALSE);
2770
2771         /* Determine LCD */
2772         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2773
2774         if (status != IXGBE_SUCCESS)
2775                 return status;
2776
2777         /* If no valid LCD link speed, then force link down and exit. */
2778         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2779                 return ixgbe_set_copper_phy_power(hw, FALSE);
2780
2781         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2782                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2783                                       &speed);
2784
2785         if (status != IXGBE_SUCCESS)
2786                 return status;
2787
2788         /* If no link now, speed is invalid so take link down */
2789         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2790         if (status != IXGBE_SUCCESS)
2791                 return ixgbe_set_copper_phy_power(hw, false);
2792
2793         /* clear everything but the speed bits */
2794         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2795
2796         /* If current speed is already LCD, then exit. */
2797         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2798              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2799             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2800              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2801                 return status;
2802
2803         /* Clear AN completed indication */
2804         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2805                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2806                                       &autoneg_reg);
2807
2808         if (status != IXGBE_SUCCESS)
2809                 return status;
2810
2811         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2812                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2813                              &an_10g_cntl_reg);
2814
2815         if (status != IXGBE_SUCCESS)
2816                 return status;
2817
2818         status = hw->phy.ops.read_reg(hw,
2819                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2820                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2821                              &autoneg_reg);
2822
2823         if (status != IXGBE_SUCCESS)
2824                 return status;
2825
2826         save_autoneg = hw->phy.autoneg_advertised;
2827
2828         /* Setup link at least common link speed */
2829         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
2830
2831         /* restore autoneg from before setting lplu speed */
2832         hw->phy.autoneg_advertised = save_autoneg;
2833
2834         return status;
2835 }
2836
2837 /**
2838  * ixgbe_get_lcd_x550em - Determine lowest common denominator
2839  *  @hw: pointer to hardware structure
2840  *  @lcd_speed: pointer to lowest common link speed
2841  *
2842  * Determine lowest common link speed with link partner.
2843  **/
2844 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2845 {
2846         u16 an_lp_status;
2847         s32 status;
2848         u16 word = hw->eeprom.ctrl_word_3;
2849
2850         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2851
2852         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2853                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2854                                       &an_lp_status);
2855
2856         if (status != IXGBE_SUCCESS)
2857                 return status;
2858
2859         /* If link partner advertised 1G, return 1G */
2860         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2861                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2862                 return status;
2863         }
2864
2865         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2866         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2867             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2868                 return status;
2869
2870         /* Link partner not capable of lower speeds, return 10G */
2871         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2872         return status;
2873 }
2874
2875 /**
2876  *  ixgbe_setup_fc_X550em - Set up flow control
2877  *  @hw: pointer to hardware structure
2878  *
2879  *  Called at init time to set up flow control.
2880  **/
2881 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
2882 {
2883         s32 ret_val = IXGBE_SUCCESS;
2884         u32 pause, asm_dir, reg_val;
2885
2886         DEBUGFUNC("ixgbe_setup_fc_X550em");
2887
2888         /* Validate the requested mode */
2889         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2890                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2891                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2892                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2893                 goto out;
2894         }
2895
2896         /* 10gig parts do not have a word in the EEPROM to determine the
2897          * default flow control setting, so we explicitly set it to full.
2898          */
2899         if (hw->fc.requested_mode == ixgbe_fc_default)
2900                 hw->fc.requested_mode = ixgbe_fc_full;
2901
2902         /* Determine PAUSE and ASM_DIR bits. */
2903         switch (hw->fc.requested_mode) {
2904         case ixgbe_fc_none:
2905                 pause = 0;
2906                 asm_dir = 0;
2907                 break;
2908         case ixgbe_fc_tx_pause:
2909                 pause = 0;
2910                 asm_dir = 1;
2911                 break;
2912         case ixgbe_fc_rx_pause:
2913                 /* Rx Flow control is enabled and Tx Flow control is
2914                  * disabled by software override. Since there really
2915                  * isn't a way to advertise that we are capable of RX
2916                  * Pause ONLY, we will advertise that we support both
2917                  * symmetric and asymmetric Rx PAUSE, as such we fall
2918                  * through to the fc_full statement.  Later, we will
2919                  * disable the adapter's ability to send PAUSE frames.
2920                  */
2921         case ixgbe_fc_full:
2922                 pause = 1;
2923                 asm_dir = 1;
2924                 break;
2925         default:
2926                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2927                         "Flow control param set incorrectly\n");
2928                 ret_val = IXGBE_ERR_CONFIG;
2929                 goto out;
2930         }
2931
2932         if (hw->phy.media_type == ixgbe_media_type_backplane) {
2933                 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
2934                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2935                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2936                 if (ret_val != IXGBE_SUCCESS)
2937                         goto out;
2938                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2939                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2940                 if (pause)
2941                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2942                 if (asm_dir)
2943                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2944                 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
2945                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2946                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2947
2948                 /* Not all devices fully support AN. */
2949                 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR)
2950                         hw->fc.disable_fc_autoneg = true;
2951         }
2952
2953 out:
2954         return ret_val;
2955 }
2956
2957 /**
2958  * ixgbe_set_mux - Set mux for port 1 access with CS4227
2959  * @hw: pointer to hardware structure
2960  * @state: set mux if 1, clear if 0
2961  */
2962 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2963 {
2964         u32 esdp;
2965
2966         if (!hw->bus.lan_id)
2967                 return;
2968         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2969         if (state)
2970                 esdp |= IXGBE_ESDP_SDP1;
2971         else
2972                 esdp &= ~IXGBE_ESDP_SDP1;
2973         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2974         IXGBE_WRITE_FLUSH(hw);
2975 }
2976
2977 /**
2978  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2979  *  @hw: pointer to hardware structure
2980  *  @mask: Mask to specify which semaphore to acquire
2981  *
2982  *  Acquires the SWFW semaphore and sets the I2C MUX
2983  **/
2984 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2985 {
2986         s32 status;
2987
2988         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
2989
2990         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2991         if (status)
2992                 return status;
2993
2994         if (mask & IXGBE_GSSR_I2C_MASK)
2995                 ixgbe_set_mux(hw, 1);
2996
2997         return IXGBE_SUCCESS;
2998 }
2999
3000 /**
3001  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
3002  *  @hw: pointer to hardware structure
3003  *  @mask: Mask to specify which semaphore to release
3004  *
3005  *  Releases the SWFW semaphore and sets the I2C MUX
3006  **/
3007 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3008 {
3009         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
3010
3011         if (mask & IXGBE_GSSR_I2C_MASK)
3012                 ixgbe_set_mux(hw, 0);
3013
3014         ixgbe_release_swfw_sync_X540(hw, mask);
3015 }
3016
3017 /**
3018  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
3019  * @hw: pointer to hardware structure
3020  *
3021  * Handle external Base T PHY interrupt. If high temperature
3022  * failure alarm then return error, else if link status change
3023  * then setup internal/external PHY link
3024  *
3025  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
3026  * failure alarm, else return PHY access status.
3027  */
3028 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
3029 {
3030         bool lsc;
3031         u32 status;
3032
3033         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
3034
3035         if (status != IXGBE_SUCCESS)
3036                 return status;
3037
3038         if (lsc)
3039                 return ixgbe_setup_internal_phy(hw);
3040
3041         return IXGBE_SUCCESS;
3042 }
3043
3044 /**
3045  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
3046  * @hw: pointer to hardware structure
3047  * @speed: new link speed
3048  * @autoneg_wait_to_complete: true when waiting for completion is needed
3049  *
3050  * Setup internal/external PHY link speed based on link speed, then set
3051  * external PHY auto advertised link speed.
3052  *
3053  * Returns error status for any failure
3054  **/
3055 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
3056                                   ixgbe_link_speed speed,
3057                                   bool autoneg_wait_to_complete)
3058 {
3059         s32 status;
3060         ixgbe_link_speed force_speed;
3061
3062         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
3063
3064         /* Setup internal/external PHY link speed to iXFI (10G), unless
3065          * only 1G is auto advertised then setup KX link.
3066          */
3067         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
3068                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3069         else
3070                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3071
3072         /* If internal link mode is XFI, then setup XFI internal link. */
3073         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3074                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
3075
3076                 if (status != IXGBE_SUCCESS)
3077                         return status;
3078         }
3079
3080         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
3081 }
3082
3083 /**
3084  * ixgbe_check_link_t_X550em - Determine link and speed status
3085  * @hw: pointer to hardware structure
3086  * @speed: pointer to link speed
3087  * @link_up: true when link is up
3088  * @link_up_wait_to_complete: bool used to wait for link up or not
3089  *
3090  * Check that both the MAC and X557 external PHY have link.
3091  **/
3092 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3093                               bool *link_up, bool link_up_wait_to_complete)
3094 {
3095         u32 status;
3096         u16 autoneg_status;
3097
3098         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3099                 return IXGBE_ERR_CONFIG;
3100
3101         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
3102                                               link_up_wait_to_complete);
3103
3104         /* If check link fails or MAC link is not up, then return */
3105         if (status != IXGBE_SUCCESS || !(*link_up))
3106                 return status;
3107
3108         /* MAC link is up, so check external PHY link.
3109          * Read this twice back to back to indicate current status.
3110          */
3111         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3112                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3113                                       &autoneg_status);
3114
3115         if (status != IXGBE_SUCCESS)
3116                 return status;
3117
3118         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3119                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3120                                       &autoneg_status);
3121
3122         if (status != IXGBE_SUCCESS)
3123                 return status;
3124
3125         /* If external PHY link is not up, then indicate link not up */
3126         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
3127                 *link_up = false;
3128
3129         return IXGBE_SUCCESS;
3130 }
3131
3132 /**
3133  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
3134  *  @hw: pointer to hardware structure
3135  **/
3136 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
3137 {
3138         s32 status;
3139
3140         status = ixgbe_reset_phy_generic(hw);
3141
3142         if (status != IXGBE_SUCCESS)
3143                 return status;
3144
3145         /* Configure Link Status Alarm and Temperature Threshold interrupts */
3146         return ixgbe_enable_lasi_ext_t_x550em(hw);
3147 }
3148
3149 /**
3150  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
3151  *  @hw: pointer to hardware structure
3152  *  @led_idx: led number to turn on
3153  **/
3154 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3155 {
3156         u16 phy_data;
3157
3158         DEBUGFUNC("ixgbe_led_on_t_X550em");
3159
3160         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3161                 return IXGBE_ERR_PARAM;
3162
3163         /* To turn on the LED, set mode to ON. */
3164         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3165                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3166         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
3167         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3168                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3169
3170         return IXGBE_SUCCESS;
3171 }
3172
3173 /**
3174  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
3175  *  @hw: pointer to hardware structure
3176  *  @led_idx: led number to turn off
3177  **/
3178 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3179 {
3180         u16 phy_data;
3181
3182         DEBUGFUNC("ixgbe_led_off_t_X550em");
3183
3184         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3185                 return IXGBE_ERR_PARAM;
3186
3187         /* To turn on the LED, set mode to ON. */
3188         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3189                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3190         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
3191         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3192                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3193
3194         return IXGBE_SUCCESS;
3195 }