1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
43 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
44 * @hw: pointer to hardware structure
46 * Initialize the function pointers and assign the MAC type for X550.
47 * Does not touch the hardware.
49 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
51 struct ixgbe_mac_info *mac = &hw->mac;
52 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
55 DEBUGFUNC("ixgbe_init_ops_X550");
57 ret_val = ixgbe_init_ops_X540(hw);
58 mac->ops.dmac_config = ixgbe_dmac_config_X550;
59 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
60 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
61 mac->ops.setup_eee = ixgbe_setup_eee_X550;
62 mac->ops.set_source_address_pruning =
63 ixgbe_set_source_address_pruning_X550;
64 mac->ops.set_ethertype_anti_spoofing =
65 ixgbe_set_ethertype_anti_spoofing_X550;
67 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
68 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
69 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
70 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
71 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
72 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
73 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
74 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
75 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
77 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
78 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
79 mac->ops.mdd_event = ixgbe_mdd_event_X550;
80 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
81 mac->ops.disable_rx = ixgbe_disable_rx_x550;
86 * ixgbe_read_cs4227 - Read CS4227 register
87 * @hw: pointer to hardware structure
88 * @reg: register number to write
89 * @value: pointer to receive value read
93 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
95 return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
99 * ixgbe_write_cs4227 - Write CS4227 register
100 * @hw: pointer to hardware structure
101 * @reg: register number to write
102 * @value: value to write to register
104 * Returns status code
106 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
108 return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
112 * ixgbe_get_cs4227_status - Return CS4227 status
113 * @hw: pointer to hardware structure
115 * Returns error if CS4227 not successfully initialized
117 STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
121 u16 reg_slice, reg_val;
124 for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) {
125 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB,
127 if (status != IXGBE_SUCCESS)
129 if (value == IXGBE_CS4227_GLOBAL_ID_VALUE)
131 msec_delay(IXGBE_CS4227_CHECK_DELAY);
133 if (value != IXGBE_CS4227_GLOBAL_ID_VALUE)
134 return IXGBE_ERR_PHY;
136 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
137 if (status != IXGBE_SUCCESS)
140 /* If this is the first time after power-on, check the ucode.
141 * Otherwise, this will disrupt link on all ports. Because we
142 * can only do this the first time, we must check all ports,
145 if (value != IXGBE_CS4227_SCRATCH_VALUE) {
146 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB;
147 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
148 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
149 if (status != IXGBE_SUCCESS)
152 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB;
153 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
154 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
155 if (status != IXGBE_SUCCESS)
158 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (1 << 12);
159 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
160 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
161 if (status != IXGBE_SUCCESS)
164 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (1 << 12);
165 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
166 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
167 if (status != IXGBE_SUCCESS)
173 /* Verify that the ucode is operational on all ports. */
174 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB;
176 status = ixgbe_read_cs4227(hw, reg_slice, ®_val);
177 if (status != IXGBE_SUCCESS)
180 return IXGBE_ERR_PHY;
182 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB;
184 status = ixgbe_read_cs4227(hw, reg_slice, ®_val);
185 if (status != IXGBE_SUCCESS)
188 return IXGBE_ERR_PHY;
190 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (1 << 12);
192 status = ixgbe_read_cs4227(hw, reg_slice, ®_val);
193 if (status != IXGBE_SUCCESS)
196 return IXGBE_ERR_PHY;
198 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (1 << 12);
200 status = ixgbe_read_cs4227(hw, reg_slice, ®_val);
201 if (status != IXGBE_SUCCESS)
204 return IXGBE_ERR_PHY;
206 /* Set scratch indicating that the diagnostic was successful. */
207 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
208 IXGBE_CS4227_SCRATCH_VALUE);
209 if (status != IXGBE_SUCCESS)
211 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
212 if (status != IXGBE_SUCCESS)
214 if (value != IXGBE_CS4227_SCRATCH_VALUE)
215 return IXGBE_ERR_PHY;
217 return IXGBE_SUCCESS;
221 * ixgbe_read_pe - Read register from port expander
222 * @hw: pointer to hardware structure
223 * @reg: register number to read
224 * @value: pointer to receive read value
226 * Returns status code
228 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
232 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
233 if (status != IXGBE_SUCCESS)
234 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
235 "port expander access failed with %d\n", status);
240 * ixgbe_write_pe - Write register to port expander
241 * @hw: pointer to hardware structure
242 * @reg: register number to write
243 * @value: value to write
245 * Returns status code
247 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
251 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
252 if (status != IXGBE_SUCCESS)
253 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
254 "port expander access failed with %d\n", status);
259 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
260 * @hw: pointer to hardware structure
264 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
269 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
270 if (status != IXGBE_SUCCESS)
272 reg |= IXGBE_PE_BIT1;
273 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
274 if (status != IXGBE_SUCCESS)
277 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
278 if (status != IXGBE_SUCCESS)
280 reg &= ~IXGBE_PE_BIT1;
281 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
282 if (status != IXGBE_SUCCESS)
285 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
286 if (status != IXGBE_SUCCESS)
288 reg &= ~IXGBE_PE_BIT1;
289 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
290 if (status != IXGBE_SUCCESS)
293 usec_delay(IXGBE_CS4227_RESET_HOLD);
295 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
296 if (status != IXGBE_SUCCESS)
298 reg |= IXGBE_PE_BIT1;
299 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
300 if (status != IXGBE_SUCCESS)
303 msec_delay(IXGBE_CS4227_RESET_DELAY);
305 return IXGBE_SUCCESS;
309 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
310 * @hw: pointer to hardware structure
312 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
314 u32 swfw_mask = hw->phy.phy_semaphore_mask;
318 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
319 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
320 if (status != IXGBE_SUCCESS) {
321 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
322 "semaphore failed with %d\n", status);
325 status = ixgbe_get_cs4227_status(hw);
326 if (status == IXGBE_SUCCESS) {
327 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
328 msec_delay(hw->eeprom.semaphore_delay);
331 ixgbe_reset_cs4227(hw);
332 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
333 msec_delay(hw->eeprom.semaphore_delay);
335 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
336 "Unable to initialize CS4227, err=%d\n", status);
340 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
341 * @hw: pointer to hardware structure
343 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
345 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
347 if (hw->bus.lan_id) {
348 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
349 esdp |= IXGBE_ESDP_SDP1_DIR;
351 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
352 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
353 IXGBE_WRITE_FLUSH(hw);
357 * ixgbe_identify_phy_x550em - Get PHY type based on device id
358 * @hw: pointer to hardware structure
362 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
364 switch (hw->device_id) {
365 case IXGBE_DEV_ID_X550EM_X_SFP:
366 /* set up for CS4227 usage */
367 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
368 ixgbe_setup_mux_ctl(hw);
369 ixgbe_check_cs4227(hw);
371 return ixgbe_identify_module_generic(hw);
373 case IXGBE_DEV_ID_X550EM_X_KX4:
374 hw->phy.type = ixgbe_phy_x550em_kx4;
376 case IXGBE_DEV_ID_X550EM_X_KR:
377 hw->phy.type = ixgbe_phy_x550em_kr;
379 case IXGBE_DEV_ID_X550EM_X_1G_T:
380 case IXGBE_DEV_ID_X550EM_X_10G_T:
381 return ixgbe_identify_phy_generic(hw);
385 return IXGBE_SUCCESS;
388 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
389 u32 device_type, u16 *phy_data)
391 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
392 return IXGBE_NOT_IMPLEMENTED;
395 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
396 u32 device_type, u16 phy_data)
398 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
399 return IXGBE_NOT_IMPLEMENTED;
403 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
404 * @hw: pointer to hardware structure
406 * Initialize the function pointers and for MAC type X550EM.
407 * Does not touch the hardware.
409 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
411 struct ixgbe_mac_info *mac = &hw->mac;
412 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
413 struct ixgbe_phy_info *phy = &hw->phy;
416 DEBUGFUNC("ixgbe_init_ops_X550EM");
418 /* Similar to X550 so start there. */
419 ret_val = ixgbe_init_ops_X550(hw);
421 /* Since this function eventually calls
422 * ixgbe_init_ops_540 by design, we are setting
423 * the pointers to NULL explicitly here to overwrite
424 * the values being set in the x540 function.
426 /* Thermal sensor not supported in x550EM */
427 mac->ops.get_thermal_sensor_data = NULL;
428 mac->ops.init_thermal_sensor_thresh = NULL;
429 mac->thermal_sensor_enabled = false;
431 /* FCOE not supported in x550EM */
432 mac->ops.get_san_mac_addr = NULL;
433 mac->ops.set_san_mac_addr = NULL;
434 mac->ops.get_wwn_prefix = NULL;
435 mac->ops.get_fcoe_boot_status = NULL;
437 /* IPsec not supported in x550EM */
438 mac->ops.disable_sec_rx_path = NULL;
439 mac->ops.enable_sec_rx_path = NULL;
441 /* AUTOC register is not present in x550EM. */
442 mac->ops.prot_autoc_read = NULL;
443 mac->ops.prot_autoc_write = NULL;
445 /* X550EM bus type is internal*/
446 hw->bus.type = ixgbe_bus_type_internal;
447 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
449 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
450 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
451 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
452 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
453 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
454 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
455 mac->ops.get_supported_physical_layer =
456 ixgbe_get_supported_physical_layer_X550em;
458 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
459 mac->ops.setup_fc = ixgbe_setup_fc_generic;
461 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
463 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
464 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
466 if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
467 mac->ops.setup_eee = NULL;
470 phy->ops.init = ixgbe_init_phy_ops_X550em;
471 phy->ops.identify = ixgbe_identify_phy_x550em;
472 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
473 phy->ops.set_phy_power = NULL;
477 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
478 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
479 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
480 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
481 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
482 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
483 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
484 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
490 * ixgbe_dmac_config_X550
491 * @hw: pointer to hardware structure
493 * Configure DMA coalescing. If enabling dmac, dmac is activated.
494 * When disabling dmac, dmac enable dmac bit is cleared.
496 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
498 u32 reg, high_pri_tc;
500 DEBUGFUNC("ixgbe_dmac_config_X550");
502 /* Disable DMA coalescing before configuring */
503 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
504 reg &= ~IXGBE_DMACR_DMAC_EN;
505 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
507 /* Disable DMA Coalescing if the watchdog timer is 0 */
508 if (!hw->mac.dmac_config.watchdog_timer)
511 ixgbe_dmac_config_tcs_X550(hw);
513 /* Configure DMA Coalescing Control Register */
514 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
516 /* Set the watchdog timer in units of 40.96 usec */
517 reg &= ~IXGBE_DMACR_DMACWT_MASK;
518 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
520 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
521 /* If fcoe is enabled, set high priority traffic class */
522 if (hw->mac.dmac_config.fcoe_en) {
523 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
524 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
525 IXGBE_DMACR_HIGH_PRI_TC_MASK);
527 reg |= IXGBE_DMACR_EN_MNG_IND;
529 /* Enable DMA coalescing after configuration */
530 reg |= IXGBE_DMACR_DMAC_EN;
531 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
534 return IXGBE_SUCCESS;
538 * ixgbe_dmac_config_tcs_X550
539 * @hw: pointer to hardware structure
541 * Configure DMA coalescing threshold per TC. The dmac enable bit must
542 * be cleared before configuring.
544 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
546 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
548 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
550 /* Configure DMA coalescing enabled */
551 switch (hw->mac.dmac_config.link_speed) {
552 case IXGBE_LINK_SPEED_100_FULL:
553 pb_headroom = IXGBE_DMACRXT_100M;
555 case IXGBE_LINK_SPEED_1GB_FULL:
556 pb_headroom = IXGBE_DMACRXT_1G;
559 pb_headroom = IXGBE_DMACRXT_10G;
563 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
564 IXGBE_MHADD_MFS_SHIFT) / 1024);
566 /* Set the per Rx packet buffer receive threshold */
567 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
568 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
569 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
571 if (tc < hw->mac.dmac_config.num_tcs) {
573 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
574 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
575 IXGBE_RXPBSIZE_SHIFT;
577 /* Calculate receive buffer threshold in kilobytes */
578 if (rx_pb_size > pb_headroom)
579 rx_pb_size = rx_pb_size - pb_headroom;
583 /* Minimum of MFS shall be set for DMCTH */
584 reg |= (rx_pb_size > maxframe_size_kb) ?
585 rx_pb_size : maxframe_size_kb;
587 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
589 return IXGBE_SUCCESS;
593 * ixgbe_dmac_update_tcs_X550
594 * @hw: pointer to hardware structure
596 * Disables dmac, updates per TC settings, and then enables dmac.
598 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
602 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
604 /* Disable DMA coalescing before configuring */
605 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
606 reg &= ~IXGBE_DMACR_DMAC_EN;
607 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
609 ixgbe_dmac_config_tcs_X550(hw);
611 /* Enable DMA coalescing after configuration */
612 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
613 reg |= IXGBE_DMACR_DMAC_EN;
614 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
616 return IXGBE_SUCCESS;
620 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
621 * @hw: pointer to hardware structure
623 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
624 * ixgbe_hw struct in order to set up EEPROM access.
626 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
628 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
632 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
634 if (eeprom->type == ixgbe_eeprom_uninitialized) {
635 eeprom->semaphore_delay = 10;
636 eeprom->type = ixgbe_flash;
638 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
639 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
640 IXGBE_EEC_SIZE_SHIFT);
641 eeprom->word_size = 1 << (eeprom_size +
642 IXGBE_EEPROM_WORD_SIZE_SHIFT);
644 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
645 eeprom->type, eeprom->word_size);
648 return IXGBE_SUCCESS;
652 * ixgbe_setup_eee_X550 - Enable/disable EEE support
653 * @hw: pointer to the HW structure
654 * @enable_eee: boolean flag to enable EEE
656 * Enable/disable EEE based on enable_eee flag.
657 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
661 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
669 DEBUGFUNC("ixgbe_setup_eee_X550");
671 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
672 /* Enable or disable EEE per flag */
674 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
676 if (hw->device_id == IXGBE_DEV_ID_X550T) {
677 /* Advertise EEE capability */
678 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
679 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
681 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
682 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
683 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
685 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
686 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
687 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
688 /* Not supported on first revision. */
689 fuse = IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0));
690 if (!(fuse & IXGBE_FUSES0_REV1))
691 return IXGBE_SUCCESS;
693 status = ixgbe_read_iosf_sb_reg_x550(hw,
694 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
695 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
696 if (status != IXGBE_SUCCESS)
699 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
700 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
702 /* Don't advertise FEC capability when EEE enabled. */
703 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
705 status = ixgbe_write_iosf_sb_reg_x550(hw,
706 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
707 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
708 if (status != IXGBE_SUCCESS)
712 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
714 if (hw->device_id == IXGBE_DEV_ID_X550T) {
715 /* Disable advertised EEE capability */
716 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
717 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
719 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
720 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
721 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
723 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
724 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
725 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
726 status = ixgbe_read_iosf_sb_reg_x550(hw,
727 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
728 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
729 if (status != IXGBE_SUCCESS)
732 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
733 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
735 /* Advertise FEC capability when EEE is disabled. */
736 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
738 status = ixgbe_write_iosf_sb_reg_x550(hw,
739 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
740 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
741 if (status != IXGBE_SUCCESS)
745 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
747 return IXGBE_SUCCESS;
751 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
752 * @hw: pointer to hardware structure
753 * @enable: enable or disable source address pruning
754 * @pool: Rx pool to set source address pruning for
756 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
761 /* max rx pool is 63 */
765 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
766 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
769 pfflp |= (1ULL << pool);
771 pfflp &= ~(1ULL << pool);
773 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
774 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
778 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
779 * @hw: pointer to hardware structure
780 * @enable: enable or disable switch for Ethertype anti-spoofing
781 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
784 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
787 int vf_target_reg = vf >> 3;
788 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
791 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
793 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
795 pfvfspoof |= (1 << vf_target_shift);
797 pfvfspoof &= ~(1 << vf_target_shift);
799 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
803 * ixgbe_iosf_wait - Wait for IOSF command completion
804 * @hw: pointer to hardware structure
805 * @ctrl: pointer to location to receive final IOSF control value
807 * Returns failing status on timeout
809 * Note: ctrl can be NULL if the IOSF control register value is not needed
811 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
815 /* Check every 10 usec to see if the address cycle completed.
816 * The SB IOSF BUSY bit will clear when the operation is
819 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
820 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
821 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
827 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
828 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
829 return IXGBE_ERR_PHY;
832 return IXGBE_SUCCESS;
836 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
838 * @hw: pointer to hardware structure
839 * @reg_addr: 32 bit PHY register to write
840 * @device_type: 3 bit device type
841 * @data: Data to write to the register
843 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
844 u32 device_type, u32 data)
846 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
850 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
851 if (ret != IXGBE_SUCCESS)
854 ret = ixgbe_iosf_wait(hw, NULL);
855 if (ret != IXGBE_SUCCESS)
858 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
859 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
861 /* Write IOSF control register */
862 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
864 /* Write IOSF data register */
865 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
867 ret = ixgbe_iosf_wait(hw, &command);
869 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
870 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
871 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
872 ERROR_REPORT2(IXGBE_ERROR_POLLING,
873 "Failed to write, error %x\n", error);
878 ixgbe_release_swfw_semaphore(hw, gssr);
883 * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
885 * @hw: pointer to hardware structure
886 * @reg_addr: 32 bit PHY register to write
887 * @device_type: 3 bit device type
888 * @phy_data: Pointer to read data from the register
890 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
891 u32 device_type, u32 *data)
893 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
897 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
898 if (ret != IXGBE_SUCCESS)
901 ret = ixgbe_iosf_wait(hw, NULL);
902 if (ret != IXGBE_SUCCESS)
905 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
906 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
908 /* Write IOSF control register */
909 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
911 ret = ixgbe_iosf_wait(hw, &command);
913 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
914 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
915 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
916 ERROR_REPORT2(IXGBE_ERROR_POLLING,
917 "Failed to read, error %x\n", error);
921 if (ret == IXGBE_SUCCESS)
922 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
925 ixgbe_release_swfw_semaphore(hw, gssr);
930 * ixgbe_disable_mdd_X550
931 * @hw: pointer to hardware structure
933 * Disable malicious driver detection
935 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
939 DEBUGFUNC("ixgbe_disable_mdd_X550");
941 /* Disable MDD for TX DMA and interrupt */
942 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
943 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
944 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
946 /* Disable MDD for RX and interrupt */
947 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
948 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
949 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
953 * ixgbe_enable_mdd_X550
954 * @hw: pointer to hardware structure
956 * Enable malicious driver detection
958 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
962 DEBUGFUNC("ixgbe_enable_mdd_X550");
964 /* Enable MDD for TX DMA and interrupt */
965 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
966 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
967 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
969 /* Enable MDD for RX and interrupt */
970 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
971 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
972 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
976 * ixgbe_restore_mdd_vf_X550
977 * @hw: pointer to hardware structure
980 * Restore VF that was disabled during malicious driver detection event
982 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
984 u32 idx, reg, num_qs, start_q, bitmask;
986 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
988 /* Map VF to queues */
989 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
990 switch (reg & IXGBE_MRQC_MRQE_MASK) {
991 case IXGBE_MRQC_VMDQRT8TCEN:
992 num_qs = 8; /* 16 VFs / pools */
993 bitmask = 0x000000FF;
995 case IXGBE_MRQC_VMDQRSS32EN:
996 case IXGBE_MRQC_VMDQRT4TCEN:
997 num_qs = 4; /* 32 VFs / pools */
998 bitmask = 0x0000000F;
1000 default: /* 64 VFs / pools */
1002 bitmask = 0x00000003;
1005 start_q = vf * num_qs;
1007 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1010 reg |= (bitmask << (start_q % 32));
1011 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1012 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1016 * ixgbe_mdd_event_X550
1017 * @hw: pointer to hardware structure
1018 * @vf_bitmap: vf bitmap of malicious vfs
1020 * Handle malicious driver detection event.
1022 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1025 u32 i, j, reg, q, shift, vf, idx;
1027 DEBUGFUNC("ixgbe_mdd_event_X550");
1029 /* figure out pool size for mapping to vf's */
1030 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1031 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1032 case IXGBE_MRQC_VMDQRT8TCEN:
1033 shift = 3; /* 16 VFs / pools */
1035 case IXGBE_MRQC_VMDQRSS32EN:
1036 case IXGBE_MRQC_VMDQRT4TCEN:
1037 shift = 2; /* 32 VFs / pools */
1040 shift = 1; /* 64 VFs / pools */
1044 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1045 for (i = 0; i < 4; i++) {
1046 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1047 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1052 /* Get malicious queue */
1053 for (j = 0; j < 32 && wqbr; j++) {
1055 if (!(wqbr & (1 << j)))
1058 /* Get queue from bitmask */
1061 /* Map queue to vf */
1064 /* Set vf bit in vf_bitmap */
1066 vf_bitmap[idx] |= (1 << (vf % 32));
1073 * ixgbe_get_media_type_X550em - Get media type
1074 * @hw: pointer to hardware structure
1076 * Returns the media type (fiber, copper, backplane)
1078 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1080 enum ixgbe_media_type media_type;
1082 DEBUGFUNC("ixgbe_get_media_type_X550em");
1084 /* Detect if there is a copper PHY attached. */
1085 switch (hw->device_id) {
1086 case IXGBE_DEV_ID_X550EM_X_KR:
1087 case IXGBE_DEV_ID_X550EM_X_KX4:
1088 media_type = ixgbe_media_type_backplane;
1090 case IXGBE_DEV_ID_X550EM_X_SFP:
1091 media_type = ixgbe_media_type_fiber;
1093 case IXGBE_DEV_ID_X550EM_X_1G_T:
1094 case IXGBE_DEV_ID_X550EM_X_10G_T:
1095 media_type = ixgbe_media_type_copper;
1098 media_type = ixgbe_media_type_unknown;
1105 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1106 * @hw: pointer to hardware structure
1107 * @linear: true if SFP module is linear
1109 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1111 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1113 switch (hw->phy.sfp_type) {
1114 case ixgbe_sfp_type_not_present:
1115 return IXGBE_ERR_SFP_NOT_PRESENT;
1116 case ixgbe_sfp_type_da_cu_core0:
1117 case ixgbe_sfp_type_da_cu_core1:
1120 case ixgbe_sfp_type_srlr_core0:
1121 case ixgbe_sfp_type_srlr_core1:
1122 case ixgbe_sfp_type_da_act_lmt_core0:
1123 case ixgbe_sfp_type_da_act_lmt_core1:
1124 case ixgbe_sfp_type_1g_sx_core0:
1125 case ixgbe_sfp_type_1g_sx_core1:
1126 case ixgbe_sfp_type_1g_lx_core0:
1127 case ixgbe_sfp_type_1g_lx_core1:
1130 case ixgbe_sfp_type_unknown:
1131 case ixgbe_sfp_type_1g_cu_core0:
1132 case ixgbe_sfp_type_1g_cu_core1:
1134 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1137 return IXGBE_SUCCESS;
1141 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1142 * @hw: pointer to hardware structure
1144 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1146 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1151 DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1153 status = ixgbe_identify_module_generic(hw);
1155 if (status != IXGBE_SUCCESS)
1158 /* Check if SFP module is supported */
1159 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1165 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1166 * @hw: pointer to hardware structure
1168 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1173 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1175 /* Check if SFP module is supported */
1176 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1178 if (status != IXGBE_SUCCESS)
1181 ixgbe_init_mac_link_ops_X550em(hw);
1182 hw->phy.ops.reset = NULL;
1184 return IXGBE_SUCCESS;
1188 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1189 * @hw: pointer to hardware structure
1191 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1193 struct ixgbe_mac_info *mac = &hw->mac;
1195 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1197 switch (hw->mac.ops.get_media_type(hw)) {
1198 case ixgbe_media_type_fiber:
1199 /* CS4227 does not support autoneg, so disable the laser control
1200 * functions for SFP+ fiber
1202 mac->ops.disable_tx_laser = NULL;
1203 mac->ops.enable_tx_laser = NULL;
1204 mac->ops.flap_tx_laser = NULL;
1205 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1206 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1207 mac->ops.set_rate_select_speed =
1208 ixgbe_set_soft_rate_select_speed;
1210 case ixgbe_media_type_copper:
1211 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1212 mac->ops.check_link = ixgbe_check_link_t_X550em;
1220 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1221 * @hw: pointer to hardware structure
1222 * @speed: pointer to link speed
1223 * @autoneg: true when autoneg or autotry is enabled
1225 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1226 ixgbe_link_speed *speed,
1229 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1232 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1234 /* CS4227 SFP must not enable auto-negotiation */
1237 /* Check if 1G SFP module. */
1238 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1239 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1240 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1241 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1242 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1243 return IXGBE_SUCCESS;
1246 /* Link capabilities are based on SFP */
1247 if (hw->phy.multispeed_fiber)
1248 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1249 IXGBE_LINK_SPEED_1GB_FULL;
1251 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1253 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1254 IXGBE_LINK_SPEED_1GB_FULL;
1258 return IXGBE_SUCCESS;
1262 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1263 * @hw: pointer to hardware structure
1264 * @lsc: pointer to boolean flag which indicates whether external Base T
1265 * PHY interrupt is lsc
1267 * Determime if external Base T PHY interrupt cause is high temperature
1268 * failure alarm or link status change.
1270 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1271 * failure alarm, else return PHY access status.
1273 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1280 /* Vendor alarm triggered */
1281 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1282 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1285 if (status != IXGBE_SUCCESS ||
1286 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1289 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1290 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1291 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1294 if (status != IXGBE_SUCCESS ||
1295 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1296 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1299 /* High temperature failure alarm triggered */
1300 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1301 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1304 if (status != IXGBE_SUCCESS)
1307 /* If high temperature failure, then return over temp error and exit */
1308 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1309 /* power down the PHY in case the PHY FW didn't already */
1310 ixgbe_set_copper_phy_power(hw, false);
1311 return IXGBE_ERR_OVERTEMP;
1314 /* Vendor alarm 2 triggered */
1315 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1316 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1318 if (status != IXGBE_SUCCESS ||
1319 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1322 /* link connect/disconnect event occurred */
1323 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1324 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1326 if (status != IXGBE_SUCCESS)
1330 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1333 return IXGBE_SUCCESS;
1337 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1338 * @hw: pointer to hardware structure
1340 * Enable link status change and temperature failure alarm for the external
1343 * Returns PHY access status
1345 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1351 /* Clear interrupt flags */
1352 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1354 /* Enable link status change alarm */
1355 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1356 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1358 if (status != IXGBE_SUCCESS)
1361 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1363 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1364 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1366 if (status != IXGBE_SUCCESS)
1369 /* Enables high temperature failure alarm */
1370 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1371 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1374 if (status != IXGBE_SUCCESS)
1377 reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;
1379 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1380 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1383 if (status != IXGBE_SUCCESS)
1386 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1387 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1388 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1391 if (status != IXGBE_SUCCESS)
1394 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1395 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1397 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1398 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1401 if (status != IXGBE_SUCCESS)
1404 /* Enable chip-wide vendor alarm */
1405 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1406 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1409 if (status != IXGBE_SUCCESS)
1412 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1414 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1415 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1422 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1423 * @hw: pointer to hardware structure
1424 * @speed: link speed
1426 * Configures the integrated KR PHY.
1428 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1429 ixgbe_link_speed speed)
1434 status = ixgbe_read_iosf_sb_reg_x550(hw,
1435 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1436 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1440 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1441 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ |
1442 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC);
1443 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1444 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1446 /* Advertise 10G support. */
1447 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1448 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1450 /* Advertise 1G support. */
1451 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1452 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1454 /* Restart auto-negotiation. */
1455 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1456 status = ixgbe_write_iosf_sb_reg_x550(hw,
1457 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1458 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1464 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1465 * @hw: pointer to hardware structure
1467 * Initialize any function pointers that were not able to be
1468 * set during init_shared_code because the PHY/SFP type was
1469 * not known. Perform the SFP init if necessary.
1471 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1473 struct ixgbe_phy_info *phy = &hw->phy;
1474 ixgbe_link_speed speed;
1477 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1479 hw->mac.ops.set_lan_id(hw);
1481 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1482 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1483 ixgbe_setup_mux_ctl(hw);
1485 /* Save NW management interface connected on board. This is used
1486 * to determine internal PHY mode.
1488 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1490 /* If internal PHY mode is KR, then initialize KR link */
1491 if (phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) {
1492 speed = IXGBE_LINK_SPEED_10GB_FULL |
1493 IXGBE_LINK_SPEED_1GB_FULL;
1494 ret_val = ixgbe_setup_kr_speed_x550em(hw, speed);
1497 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
1500 /* Identify the PHY or SFP module */
1501 ret_val = phy->ops.identify(hw);
1502 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1505 /* Setup function pointers based on detected hardware */
1506 ixgbe_init_mac_link_ops_X550em(hw);
1507 if (phy->sfp_type != ixgbe_sfp_type_unknown)
1508 phy->ops.reset = NULL;
1510 /* Set functions pointers based on phy type */
1511 switch (hw->phy.type) {
1512 case ixgbe_phy_x550em_kx4:
1513 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
1514 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1515 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1517 case ixgbe_phy_x550em_kr:
1518 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1519 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1520 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1522 case ixgbe_phy_x550em_ext_t:
1523 /* Save NW management interface connected on board. This is used
1524 * to determine internal PHY mode
1526 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1528 /* If internal link mode is XFI, then setup iXFI internal link,
1529 * else setup KR now.
1531 if (!(phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1532 phy->ops.setup_internal_link =
1533 ixgbe_setup_internal_phy_t_x550em;
1535 speed = IXGBE_LINK_SPEED_10GB_FULL |
1536 IXGBE_LINK_SPEED_1GB_FULL;
1537 ret_val = ixgbe_setup_kr_speed_x550em(hw, speed);
1540 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1541 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1542 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1551 * ixgbe_reset_hw_X550em - Perform hardware reset
1552 * @hw: pointer to hardware structure
1554 * Resets the hardware by resetting the transmit and receive units, masks
1555 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1558 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1560 ixgbe_link_speed link_speed;
1564 bool link_up = false;
1566 DEBUGFUNC("ixgbe_reset_hw_X550em");
1568 /* Call adapter stop to disable Tx/Rx and clear interrupts */
1569 status = hw->mac.ops.stop_adapter(hw);
1570 if (status != IXGBE_SUCCESS)
1573 /* flush pending Tx transactions */
1574 ixgbe_clear_tx_pending(hw);
1576 /* PHY ops must be identified and initialized prior to reset */
1578 /* Identify PHY and related function pointers */
1579 status = hw->phy.ops.init(hw);
1581 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1584 /* start the external PHY */
1585 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1586 status = ixgbe_init_ext_t_x550em(hw);
1591 /* Setup SFP module if there is one present. */
1592 if (hw->phy.sfp_setup_needed) {
1593 status = hw->mac.ops.setup_sfp(hw);
1594 hw->phy.sfp_setup_needed = false;
1597 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1601 if (!hw->phy.reset_disable && hw->phy.ops.reset)
1602 hw->phy.ops.reset(hw);
1605 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
1606 * If link reset is used when link is up, it might reset the PHY when
1607 * mng is using it. If link is down or the flag to force full link
1608 * reset is set, then perform link reset.
1610 ctrl = IXGBE_CTRL_LNK_RST;
1611 if (!hw->force_full_reset) {
1612 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1614 ctrl = IXGBE_CTRL_RST;
1617 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1618 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1619 IXGBE_WRITE_FLUSH(hw);
1621 /* Poll for reset bit to self-clear meaning reset is complete */
1622 for (i = 0; i < 10; i++) {
1624 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1625 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1629 if (ctrl & IXGBE_CTRL_RST_MASK) {
1630 status = IXGBE_ERR_RESET_FAILED;
1631 DEBUGOUT("Reset polling failed to complete.\n");
1636 /* Double resets are required for recovery from certain error
1637 * conditions. Between resets, it is necessary to stall to
1638 * allow time for any pending HW events to complete.
1640 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1641 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1645 /* Store the permanent mac address */
1646 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1648 /* Store MAC address from RAR0, clear receive address registers, and
1649 * clear the multicast table. Also reset num_rar_entries to 128,
1650 * since we modify this value when programming the SAN MAC address.
1652 hw->mac.num_rar_entries = 128;
1653 hw->mac.ops.init_rx_addrs(hw);
1656 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1657 ixgbe_setup_mux_ctl(hw);
1663 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1664 * @hw: pointer to hardware structure
1666 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1671 status = hw->phy.ops.read_reg(hw,
1672 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1673 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1676 if (status != IXGBE_SUCCESS)
1679 /* If PHY FW reset completed bit is set then this is the first
1680 * SW instance after a power on so the PHY FW must be un-stalled.
1682 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1683 status = hw->phy.ops.read_reg(hw,
1684 IXGBE_MDIO_GLOBAL_RES_PR_10,
1685 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1688 if (status != IXGBE_SUCCESS)
1691 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1693 status = hw->phy.ops.write_reg(hw,
1694 IXGBE_MDIO_GLOBAL_RES_PR_10,
1695 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1698 if (status != IXGBE_SUCCESS)
1706 * ixgbe_setup_kr_x550em - Configure the KR PHY.
1707 * @hw: pointer to hardware structure
1709 * Configures the integrated KR PHY.
1711 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1713 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
1717 * ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1718 * @hw: pointer to hardware structure
1720 * Configures the integrated KX4 PHY.
1722 s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1727 status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1728 IXGBE_SB_IOSF_TARGET_KX4_PCS, ®_val);
1732 reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1733 IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1735 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1737 /* Advertise 10G support. */
1738 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1739 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1741 /* Advertise 1G support. */
1742 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1743 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1745 /* Restart auto-negotiation. */
1746 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1747 status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1748 IXGBE_SB_IOSF_TARGET_KX4_PCS, reg_val);
1754 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1755 * @hw: pointer to hardware structure
1756 * @speed: the link speed to force
1758 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
1759 * internal and external PHY at a specific speed, without autonegotiation.
1761 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1766 /* Disable AN and force speed to 10G Serial. */
1767 status = ixgbe_read_iosf_sb_reg_x550(hw,
1768 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1769 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1770 if (status != IXGBE_SUCCESS)
1773 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1774 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1776 /* Select forced link speed for internal PHY. */
1778 case IXGBE_LINK_SPEED_10GB_FULL:
1779 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1781 case IXGBE_LINK_SPEED_1GB_FULL:
1782 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1785 /* Other link speeds are not supported by internal KR PHY. */
1786 return IXGBE_ERR_LINK_SETUP;
1789 status = ixgbe_write_iosf_sb_reg_x550(hw,
1790 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1791 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1792 if (status != IXGBE_SUCCESS)
1795 /* Disable training protocol FSM. */
1796 status = ixgbe_read_iosf_sb_reg_x550(hw,
1797 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1798 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1799 if (status != IXGBE_SUCCESS)
1801 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1802 status = ixgbe_write_iosf_sb_reg_x550(hw,
1803 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1804 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1805 if (status != IXGBE_SUCCESS)
1808 /* Disable Flex from training TXFFE. */
1809 status = ixgbe_read_iosf_sb_reg_x550(hw,
1810 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1811 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1812 if (status != IXGBE_SUCCESS)
1814 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1815 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1816 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1817 status = ixgbe_write_iosf_sb_reg_x550(hw,
1818 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1819 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1820 if (status != IXGBE_SUCCESS)
1822 status = ixgbe_read_iosf_sb_reg_x550(hw,
1823 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1824 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1825 if (status != IXGBE_SUCCESS)
1827 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1828 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1829 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1830 status = ixgbe_write_iosf_sb_reg_x550(hw,
1831 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1832 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1833 if (status != IXGBE_SUCCESS)
1836 /* Enable override for coefficients. */
1837 status = ixgbe_read_iosf_sb_reg_x550(hw,
1838 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1839 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1840 if (status != IXGBE_SUCCESS)
1842 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1843 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1844 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1845 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1846 status = ixgbe_write_iosf_sb_reg_x550(hw,
1847 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1848 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1849 if (status != IXGBE_SUCCESS)
1852 /* Toggle port SW reset by AN reset. */
1853 status = ixgbe_read_iosf_sb_reg_x550(hw,
1854 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1855 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1856 if (status != IXGBE_SUCCESS)
1858 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1859 status = ixgbe_write_iosf_sb_reg_x550(hw,
1860 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1861 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1867 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
1868 * @hw: pointer to hardware structure
1870 * Configure the external PHY and the integrated KR PHY for SFP support.
1872 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1873 ixgbe_link_speed speed,
1874 bool autoneg_wait_to_complete)
1877 u16 reg_slice, reg_val;
1878 bool setup_linear = false;
1879 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1881 /* Check if SFP module is supported and linear */
1882 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1884 /* If no SFP module present, then return success. Return success since
1885 * there is no reason to configure CS4227 and SFP not present error is
1886 * not excepted in the setup MAC link flow.
1888 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1889 return IXGBE_SUCCESS;
1891 if (ret_val != IXGBE_SUCCESS)
1894 /* Configure CS4227 for LINE connection rate then type. */
1895 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB + (hw->bus.lan_id << 12);
1896 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000;
1897 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1900 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1902 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1904 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1905 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1908 /* Configure CS4227 for HOST connection rate then type. */
1909 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB + (hw->bus.lan_id << 12);
1910 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000;
1911 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1914 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (hw->bus.lan_id << 12);
1916 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1918 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1919 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1922 /* If internal link mode is XFI, then setup XFI internal link. */
1923 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE))
1924 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
1930 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1931 * @hw: point to hardware structure
1933 * Configures the link between the integrated KR PHY and the external X557 PHY
1934 * The driver will call this function when it gets a link status change
1935 * interrupt from the X557 PHY. This function configures the link speed
1936 * between the PHYs to match the link speed of the BASE-T link.
1938 * A return of a non-zero value indicates an error, and the base driver should
1939 * not report link up.
1941 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
1944 u16 autoneg_status, speed;
1945 ixgbe_link_speed force_speed;
1947 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1948 return IXGBE_ERR_CONFIG;
1950 /* read this twice back to back to indicate current status */
1951 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1952 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1954 if (status != IXGBE_SUCCESS)
1957 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1958 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1960 if (status != IXGBE_SUCCESS)
1963 /* If link is not up, then there is no setup necessary so return */
1964 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1965 return IXGBE_SUCCESS;
1967 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1968 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1971 /* clear everything but the speed and duplex bits */
1972 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1975 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1976 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1978 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1979 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1982 /* Internal PHY does not support anything else */
1983 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1986 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1990 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1991 * @hw: pointer to hardware structure
1993 * Configures the integrated KR PHY to use internal loopback mode.
1995 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
2000 /* Disable AN and force speed to 10G Serial. */
2001 status = ixgbe_read_iosf_sb_reg_x550(hw,
2002 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2003 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2004 if (status != IXGBE_SUCCESS)
2006 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2007 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2008 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2009 status = ixgbe_write_iosf_sb_reg_x550(hw,
2010 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2011 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2012 if (status != IXGBE_SUCCESS)
2015 /* Set near-end loopback clocks. */
2016 status = ixgbe_read_iosf_sb_reg_x550(hw,
2017 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2018 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2019 if (status != IXGBE_SUCCESS)
2021 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2022 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2023 status = ixgbe_write_iosf_sb_reg_x550(hw,
2024 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2025 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2026 if (status != IXGBE_SUCCESS)
2029 /* Set loopback enable. */
2030 status = ixgbe_read_iosf_sb_reg_x550(hw,
2031 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2032 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2033 if (status != IXGBE_SUCCESS)
2035 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2036 status = ixgbe_write_iosf_sb_reg_x550(hw,
2037 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2038 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2039 if (status != IXGBE_SUCCESS)
2042 /* Training bypass. */
2043 status = ixgbe_read_iosf_sb_reg_x550(hw,
2044 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2045 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2046 if (status != IXGBE_SUCCESS)
2048 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2049 status = ixgbe_write_iosf_sb_reg_x550(hw,
2050 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2051 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2057 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2058 * assuming that the semaphore is already obtained.
2059 * @hw: pointer to hardware structure
2060 * @offset: offset of word in the EEPROM to read
2061 * @data: word read from the EEPROM
2063 * Reads a 16 bit word from the EEPROM using the hostif.
2065 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2069 struct ixgbe_hic_read_shadow_ram buffer;
2071 DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2072 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2073 buffer.hdr.req.buf_lenh = 0;
2074 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2075 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2077 /* convert offset from words to bytes */
2078 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2080 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2082 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2084 IXGBE_HI_COMMAND_TIMEOUT, false);
2089 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2090 FW_NVM_DATA_OFFSET);
2096 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2097 * @hw: pointer to hardware structure
2098 * @offset: offset of word in the EEPROM to read
2099 * @data: word read from the EEPROM
2101 * Reads a 16 bit word from the EEPROM using the hostif.
2103 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2106 s32 status = IXGBE_SUCCESS;
2108 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2110 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2112 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2113 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2115 status = IXGBE_ERR_SWFW_SYNC;
2122 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2123 * @hw: pointer to hardware structure
2124 * @offset: offset of word in the EEPROM to read
2125 * @words: number of words
2126 * @data: word(s) read from the EEPROM
2128 * Reads a 16 bit word(s) from the EEPROM using the hostif.
2130 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2131 u16 offset, u16 words, u16 *data)
2133 struct ixgbe_hic_read_shadow_ram buffer;
2134 u32 current_word = 0;
2139 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2141 /* Take semaphore for the entire operation. */
2142 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2144 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2148 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2149 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2151 words_to_read = words;
2153 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2154 buffer.hdr.req.buf_lenh = 0;
2155 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2156 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2158 /* convert offset from words to bytes */
2159 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2160 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2162 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2164 IXGBE_HI_COMMAND_TIMEOUT,
2168 DEBUGOUT("Host interface command failed\n");
2172 for (i = 0; i < words_to_read; i++) {
2173 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
2175 u32 value = IXGBE_READ_REG(hw, reg);
2177 data[current_word] = (u16)(value & 0xffff);
2180 if (i < words_to_read) {
2182 data[current_word] = (u16)(value & 0xffff);
2186 words -= words_to_read;
2190 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2195 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2196 * @hw: pointer to hardware structure
2197 * @offset: offset of word in the EEPROM to write
2198 * @data: word write to the EEPROM
2200 * Write a 16 bit word to the EEPROM using the hostif.
2202 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2206 struct ixgbe_hic_write_shadow_ram buffer;
2208 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
2210 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
2211 buffer.hdr.req.buf_lenh = 0;
2212 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
2213 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2216 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2218 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2220 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2222 IXGBE_HI_COMMAND_TIMEOUT, false);
2228 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2229 * @hw: pointer to hardware structure
2230 * @offset: offset of word in the EEPROM to write
2231 * @data: word write to the EEPROM
2233 * Write a 16 bit word to the EEPROM using the hostif.
2235 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2238 s32 status = IXGBE_SUCCESS;
2240 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2242 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2244 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2245 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2247 DEBUGOUT("write ee hostif failed to get semaphore");
2248 status = IXGBE_ERR_SWFW_SYNC;
2255 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2256 * @hw: pointer to hardware structure
2257 * @offset: offset of word in the EEPROM to write
2258 * @words: number of words
2259 * @data: word(s) write to the EEPROM
2261 * Write a 16 bit word(s) to the EEPROM using the hostif.
2263 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2264 u16 offset, u16 words, u16 *data)
2266 s32 status = IXGBE_SUCCESS;
2269 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2271 /* Take semaphore for the entire operation. */
2272 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2273 if (status != IXGBE_SUCCESS) {
2274 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2278 for (i = 0; i < words; i++) {
2279 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2282 if (status != IXGBE_SUCCESS) {
2283 DEBUGOUT("Eeprom buffered write failed\n");
2288 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2295 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2296 * @hw: pointer to hardware structure
2297 * @ptr: pointer offset in eeprom
2298 * @size: size of section pointed by ptr, if 0 first word will be used as size
2299 * @csum: address of checksum to update
2301 * Returns error status for any failure
2303 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2304 u16 size, u16 *csum, u16 *buffer,
2309 u16 length, bufsz, i, start;
2312 bufsz = sizeof(buf) / sizeof(buf[0]);
2314 /* Read a chunk at the pointer location */
2316 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2318 DEBUGOUT("Failed to read EEPROM image\n");
2323 if (buffer_size < ptr)
2324 return IXGBE_ERR_PARAM;
2325 local_buffer = &buffer[ptr];
2333 length = local_buffer[0];
2335 /* Skip pointer section if length is invalid. */
2336 if (length == 0xFFFF || length == 0 ||
2337 (ptr + length) >= hw->eeprom.word_size)
2338 return IXGBE_SUCCESS;
2341 if (buffer && ((u32)start + (u32)length > buffer_size))
2342 return IXGBE_ERR_PARAM;
2344 for (i = start; length; i++, length--) {
2345 if (i == bufsz && !buffer) {
2351 /* Read a chunk at the pointer location */
2352 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2355 DEBUGOUT("Failed to read EEPROM image\n");
2359 *csum += local_buffer[i];
2361 return IXGBE_SUCCESS;
2365 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2366 * @hw: pointer to hardware structure
2367 * @buffer: pointer to buffer containing calculated checksum
2368 * @buffer_size: size of buffer
2370 * Returns a negative error code on error, or the 16-bit checksum
2372 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2374 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2378 u16 pointer, i, size;
2380 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2382 hw->eeprom.ops.init_params(hw);
2385 /* Read pointer area */
2386 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2387 IXGBE_EEPROM_LAST_WORD + 1,
2390 DEBUGOUT("Failed to read EEPROM image\n");
2393 local_buffer = eeprom_ptrs;
2395 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2396 return IXGBE_ERR_PARAM;
2397 local_buffer = buffer;
2401 * For X550 hardware include 0x0-0x41 in the checksum, skip the
2402 * checksum word itself
2404 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2405 if (i != IXGBE_EEPROM_CHECKSUM)
2406 checksum += local_buffer[i];
2409 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
2410 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2412 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2413 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2416 pointer = local_buffer[i];
2418 /* Skip pointer section if the pointer is invalid. */
2419 if (pointer == 0xFFFF || pointer == 0 ||
2420 pointer >= hw->eeprom.word_size)
2424 case IXGBE_PCIE_GENERAL_PTR:
2425 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2427 case IXGBE_PCIE_CONFIG0_PTR:
2428 case IXGBE_PCIE_CONFIG1_PTR:
2429 size = IXGBE_PCIE_CONFIG_SIZE;
2436 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2437 buffer, buffer_size);
2442 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2444 return (s32)checksum;
2448 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2449 * @hw: pointer to hardware structure
2451 * Returns a negative error code on error, or the 16-bit checksum
2453 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2455 return ixgbe_calc_checksum_X550(hw, NULL, 0);
2459 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2460 * @hw: pointer to hardware structure
2461 * @checksum_val: calculated checksum
2463 * Performs checksum calculation and validates the EEPROM checksum. If the
2464 * caller does not need checksum_val, the value can be NULL.
2466 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2470 u16 read_checksum = 0;
2472 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2474 /* Read the first word from the EEPROM. If this times out or fails, do
2475 * not continue or we could be in for a very long wait while every
2478 status = hw->eeprom.ops.read(hw, 0, &checksum);
2480 DEBUGOUT("EEPROM read failed\n");
2484 status = hw->eeprom.ops.calc_checksum(hw);
2488 checksum = (u16)(status & 0xffff);
2490 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2495 /* Verify read checksum from EEPROM is the same as
2496 * calculated checksum
2498 if (read_checksum != checksum) {
2499 status = IXGBE_ERR_EEPROM_CHECKSUM;
2500 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2501 "Invalid EEPROM checksum");
2504 /* If the user cares, return the calculated checksum */
2506 *checksum_val = checksum;
2512 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2513 * @hw: pointer to hardware structure
2515 * After writing EEPROM to shadow RAM using EEWR register, software calculates
2516 * checksum and updates the EEPROM and instructs the hardware to update
2519 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2524 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2526 /* Read the first word from the EEPROM. If this times out or fails, do
2527 * not continue or we could be in for a very long wait while every
2530 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2532 DEBUGOUT("EEPROM read failed\n");
2536 status = ixgbe_calc_eeprom_checksum_X550(hw);
2540 checksum = (u16)(status & 0xffff);
2542 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2547 status = ixgbe_update_flash_X550(hw);
2553 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2554 * @hw: pointer to hardware structure
2556 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2558 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2560 s32 status = IXGBE_SUCCESS;
2561 union ixgbe_hic_hdr2 buffer;
2563 DEBUGFUNC("ixgbe_update_flash_X550");
2565 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2566 buffer.req.buf_lenh = 0;
2567 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2568 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2570 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2572 IXGBE_HI_COMMAND_TIMEOUT, false);
2578 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2579 * @hw: pointer to hardware structure
2581 * Determines physical layer capabilities of the current configuration.
2583 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2585 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2586 u16 ext_ability = 0;
2588 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2590 hw->phy.ops.identify(hw);
2592 switch (hw->phy.type) {
2593 case ixgbe_phy_x550em_kr:
2594 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2595 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2597 case ixgbe_phy_x550em_kx4:
2598 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2599 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2601 case ixgbe_phy_x550em_ext_t:
2602 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2603 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2605 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2606 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2607 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2608 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2614 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2615 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2617 return physical_layer;
2621 * ixgbe_get_bus_info_x550em - Set PCI bus info
2622 * @hw: pointer to hardware structure
2624 * Sets bus link width and speed to unknown because X550em is
2627 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2630 DEBUGFUNC("ixgbe_get_bus_info_x550em");
2632 hw->bus.width = ixgbe_bus_width_unknown;
2633 hw->bus.speed = ixgbe_bus_speed_unknown;
2635 hw->mac.ops.set_lan_id(hw);
2637 return IXGBE_SUCCESS;
2641 * ixgbe_disable_rx_x550 - Disable RX unit
2643 * Enables the Rx DMA unit for x550
2645 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2647 u32 rxctrl, pfdtxgswc;
2649 struct ixgbe_hic_disable_rxen fw_cmd;
2651 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2653 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2654 if (rxctrl & IXGBE_RXCTRL_RXEN) {
2655 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2656 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2657 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2658 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2659 hw->mac.set_lben = true;
2661 hw->mac.set_lben = false;
2664 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2665 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2666 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2667 fw_cmd.port_number = (u8)hw->bus.lan_id;
2669 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2670 sizeof(struct ixgbe_hic_disable_rxen),
2671 IXGBE_HI_COMMAND_TIMEOUT, true);
2673 /* If we fail - disable RX using register write */
2675 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2676 if (rxctrl & IXGBE_RXCTRL_RXEN) {
2677 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2678 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2685 * ixgbe_enter_lplu_x550em - Transition to low power states
2686 * @hw: pointer to hardware structure
2688 * Configures Low Power Link Up on transition to low power states
2689 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2690 * X557 PHY immediately prior to entering LPLU.
2692 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2694 u16 autoneg_status, an_10g_cntl_reg, autoneg_reg, speed;
2696 ixgbe_link_speed lcd_speed;
2699 /* If blocked by MNG FW, then don't restart AN */
2700 if (ixgbe_check_reset_blocked(hw))
2701 return IXGBE_SUCCESS;
2703 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2704 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2707 if (status != IXGBE_SUCCESS)
2710 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2712 if (status != IXGBE_SUCCESS)
2715 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2716 * disabled, then force link down by entering low power mode.
2718 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS) ||
2719 !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2720 !(hw->wol_enabled || ixgbe_mng_present(hw)))
2721 return ixgbe_set_copper_phy_power(hw, FALSE);
2724 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2726 if (status != IXGBE_SUCCESS)
2729 /* If no valid LCD link speed, then force link down and exit. */
2730 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2731 return ixgbe_set_copper_phy_power(hw, FALSE);
2733 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2734 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2737 if (status != IXGBE_SUCCESS)
2740 /* clear everything but the speed bits */
2741 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2743 /* If current speed is already LCD, then exit. */
2744 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2745 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2746 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2747 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2750 /* Clear AN completed indication */
2751 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2752 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2755 if (status != IXGBE_SUCCESS)
2758 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2759 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2762 if (status != IXGBE_SUCCESS)
2765 status = hw->phy.ops.read_reg(hw,
2766 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2767 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2770 if (status != IXGBE_SUCCESS)
2773 save_autoneg = hw->phy.autoneg_advertised;
2775 /* Setup link at least common link speed */
2776 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
2778 /* restore autoneg from before setting lplu speed */
2779 hw->phy.autoneg_advertised = save_autoneg;
2785 * ixgbe_get_lcd_x550em - Determine lowest common denominator
2786 * @hw: pointer to hardware structure
2787 * @lcd_speed: pointer to lowest common link speed
2789 * Determine lowest common link speed with link partner.
2791 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2795 u16 word = hw->eeprom.ctrl_word_3;
2797 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2799 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2800 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2803 if (status != IXGBE_SUCCESS)
2806 /* If link partner advertised 1G, return 1G */
2807 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2808 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2812 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2813 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2814 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2817 /* Link partner not capable of lower speeds, return 10G */
2818 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2823 * ixgbe_setup_fc_X550em - Set up flow control
2824 * @hw: pointer to hardware structure
2826 * Called at init time to set up flow control.
2828 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
2830 s32 ret_val = IXGBE_SUCCESS;
2831 u32 pause, asm_dir, reg_val;
2833 DEBUGFUNC("ixgbe_setup_fc_X550em");
2835 /* Validate the requested mode */
2836 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2837 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2838 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2839 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2843 /* 10gig parts do not have a word in the EEPROM to determine the
2844 * default flow control setting, so we explicitly set it to full.
2846 if (hw->fc.requested_mode == ixgbe_fc_default)
2847 hw->fc.requested_mode = ixgbe_fc_full;
2849 /* Determine PAUSE and ASM_DIR bits. */
2850 switch (hw->fc.requested_mode) {
2855 case ixgbe_fc_tx_pause:
2859 case ixgbe_fc_rx_pause:
2860 /* Rx Flow control is enabled and Tx Flow control is
2861 * disabled by software override. Since there really
2862 * isn't a way to advertise that we are capable of RX
2863 * Pause ONLY, we will advertise that we support both
2864 * symmetric and asymmetric Rx PAUSE, as such we fall
2865 * through to the fc_full statement. Later, we will
2866 * disable the adapter's ability to send PAUSE frames.
2873 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2874 "Flow control param set incorrectly\n");
2875 ret_val = IXGBE_ERR_CONFIG;
2879 if (hw->phy.media_type == ixgbe_media_type_backplane) {
2880 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
2881 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2882 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2883 if (ret_val != IXGBE_SUCCESS)
2885 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2886 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2888 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2890 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2891 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
2892 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2893 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2895 /* Not all devices fully support AN. */
2896 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR)
2897 hw->fc.disable_fc_autoneg = true;
2905 * ixgbe_set_mux - Set mux for port 1 access with CS4227
2906 * @hw: pointer to hardware structure
2907 * @state: set mux if 1, clear if 0
2909 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2913 if (!hw->bus.lan_id)
2915 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2917 esdp |= IXGBE_ESDP_SDP1;
2919 esdp &= ~IXGBE_ESDP_SDP1;
2920 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2921 IXGBE_WRITE_FLUSH(hw);
2925 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2926 * @hw: pointer to hardware structure
2927 * @mask: Mask to specify which semaphore to acquire
2929 * Acquires the SWFW semaphore and sets the I2C MUX
2931 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2935 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
2937 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2941 if (mask & IXGBE_GSSR_I2C_MASK)
2942 ixgbe_set_mux(hw, 1);
2944 return IXGBE_SUCCESS;
2948 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2949 * @hw: pointer to hardware structure
2950 * @mask: Mask to specify which semaphore to release
2952 * Releases the SWFW semaphore and sets the I2C MUX
2954 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2956 DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
2958 if (mask & IXGBE_GSSR_I2C_MASK)
2959 ixgbe_set_mux(hw, 0);
2961 ixgbe_release_swfw_sync_X540(hw, mask);
2965 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2966 * @hw: pointer to hardware structure
2968 * Handle external Base T PHY interrupt. If high temperature
2969 * failure alarm then return error, else if link status change
2970 * then setup internal/external PHY link
2972 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2973 * failure alarm, else return PHY access status.
2975 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2980 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2982 if (status != IXGBE_SUCCESS)
2986 return ixgbe_setup_internal_phy(hw);
2988 return IXGBE_SUCCESS;
2992 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
2993 * @hw: pointer to hardware structure
2994 * @speed: new link speed
2995 * @autoneg_wait_to_complete: true when waiting for completion is needed
2997 * Setup internal/external PHY link speed based on link speed, then set
2998 * external PHY auto advertised link speed.
3000 * Returns error status for any failure
3002 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
3003 ixgbe_link_speed speed,
3004 bool autoneg_wait_to_complete)
3007 ixgbe_link_speed force_speed;
3009 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
3011 /* Setup internal/external PHY link speed to iXFI (10G), unless
3012 * only 1G is auto advertised then setup KX link.
3014 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
3015 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3017 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3019 /* If internal link mode is XFI, then setup XFI internal link. */
3020 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3021 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
3023 if (status != IXGBE_SUCCESS)
3027 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
3031 * ixgbe_check_link_t_X550em - Determine link and speed status
3032 * @hw: pointer to hardware structure
3033 * @speed: pointer to link speed
3034 * @link_up: true when link is up
3035 * @link_up_wait_to_complete: bool used to wait for link up or not
3037 * Check that both the MAC and X557 external PHY have link.
3039 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3040 bool *link_up, bool link_up_wait_to_complete)
3045 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3046 return IXGBE_ERR_CONFIG;
3048 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
3049 link_up_wait_to_complete);
3051 /* If check link fails or MAC link is not up, then return */
3052 if (status != IXGBE_SUCCESS || !(*link_up))
3055 /* MAC link is up, so check external PHY link.
3056 * Read this twice back to back to indicate current status.
3058 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3059 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3062 if (status != IXGBE_SUCCESS)
3065 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3066 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3069 if (status != IXGBE_SUCCESS)
3072 /* If external PHY link is not up, then indicate link not up */
3073 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
3076 return IXGBE_SUCCESS;
3080 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
3081 * @hw: pointer to hardware structure
3083 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
3087 status = ixgbe_reset_phy_generic(hw);
3089 if (status != IXGBE_SUCCESS)
3092 /* Configure Link Status Alarm and Temperature Threshold interrupts */
3093 return ixgbe_enable_lasi_ext_t_x550em(hw);