drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  44 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw);
  45
  46 /**
  47  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  48  *  @hw: pointer to hardware structure
  49  *
  50  *  Initialize the function pointers and assign the MAC type for X550.
  51  *  Does not touch the hardware.
  52  **/
  53 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  54 {
  55         struct ixgbe_mac_info *mac = &hw->mac;
  56         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  57         s32 ret_val;
  58
  59         DEBUGFUNC("ixgbe_init_ops_X550");
  60
  61         ret_val = ixgbe_init_ops_X540(hw);
  62         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  63         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  64         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  65         mac->ops.setup_eee = NULL;
  66         mac->ops.set_source_address_pruning =
  67                         ixgbe_set_source_address_pruning_X550;
  68         mac->ops.set_ethertype_anti_spoofing =
  69                         ixgbe_set_ethertype_anti_spoofing_X550;
  70
  71         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  72         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  73         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  74         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  75         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  76         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  77         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  78         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  79         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  80
  81         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  82         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  83         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  84         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  85         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  86         /* Manageability interface */
  87         mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_x550;
  88         switch (hw->device_id) {
  89         case IXGBE_DEV_ID_X550EM_X_1G_T:
  90                 hw->mac.ops.led_on = NULL;
  91                 hw->mac.ops.led_off = NULL;
  92                 break;
  93         case IXGBE_DEV_ID_X550EM_X_10G_T:
  94         case IXGBE_DEV_ID_X550EM_A_10G_T:
  95                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  96                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  97                 break;
  98         default:
  99                 break;
 100         }
 101         return ret_val;
 102 }
 103
 104 /**
 105  * ixgbe_read_cs4227 - Read CS4227 register
 106  * @hw: pointer to hardware structure
 107  * @reg: register number to write
 108  * @value: pointer to receive value read
 109  *
 110  * Returns status code
 111  **/
 112 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
 113 {
 114         return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
 115 }
 116
 117 /**
 118  * ixgbe_write_cs4227 - Write CS4227 register
 119  * @hw: pointer to hardware structure
 120  * @reg: register number to write
 121  * @value: value to write to register
 122  *
 123  * Returns status code
 124  **/
 125 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 126 {
 127         return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
 128 }
 129
 130 /**
 131  * ixgbe_read_pe - Read register from port expander
 132  * @hw: pointer to hardware structure
 133  * @reg: register number to read
 134  * @value: pointer to receive read value
 135  *
 136  * Returns status code
 137  **/
 138 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 139 {
 140         s32 status;
 141
 142         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 143         if (status != IXGBE_SUCCESS)
 144                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 145                               "port expander access failed with %d\n", status);
 146         return status;
 147 }
 148
 149 /**
 150  * ixgbe_write_pe - Write register to port expander
 151  * @hw: pointer to hardware structure
 152  * @reg: register number to write
 153  * @value: value to write
 154  *
 155  * Returns status code
 156  **/
 157 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 158 {
 159         s32 status;
 160
 161         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 162         if (status != IXGBE_SUCCESS)
 163                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 164                               "port expander access failed with %d\n", status);
 165         return status;
 166 }
 167
 168 /**
 169  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 170  * @hw: pointer to hardware structure
 171  *
 172  * This function assumes that the caller has acquired the proper semaphore.
 173  * Returns error code
 174  **/
 175 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 176 {
 177         s32 status;
 178         u32 retry;
 179         u16 value;
 180         u8 reg;
 181
 182         /* Trigger hard reset. */
 183         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 184         if (status != IXGBE_SUCCESS)
 185                 return status;
 186         reg |= IXGBE_PE_BIT1;
 187         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 188         if (status != IXGBE_SUCCESS)
 189                 return status;
 190
 191         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 192         if (status != IXGBE_SUCCESS)
 193                 return status;
 194         reg &= ~IXGBE_PE_BIT1;
 195         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 196         if (status != IXGBE_SUCCESS)
 197                 return status;
 198
 199         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 200         if (status != IXGBE_SUCCESS)
 201                 return status;
 202         reg &= ~IXGBE_PE_BIT1;
 203         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 204         if (status != IXGBE_SUCCESS)
 205                 return status;
 206
 207         usec_delay(IXGBE_CS4227_RESET_HOLD);
 208
 209         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 210         if (status != IXGBE_SUCCESS)
 211                 return status;
 212         reg |= IXGBE_PE_BIT1;
 213         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 214         if (status != IXGBE_SUCCESS)
 215                 return status;
 216
 217         /* Wait for the reset to complete. */
 218         msec_delay(IXGBE_CS4227_RESET_DELAY);
 219         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 220                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 221                                            &value);
 222                 if (status == IXGBE_SUCCESS &&
 223                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 224                         break;
 225                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 226         }
 227         if (retry == IXGBE_CS4227_RETRIES) {
 228                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 229                         "CS4227 reset did not complete.");
 230                 return IXGBE_ERR_PHY;
 231         }
 232
 233         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 234         if (status != IXGBE_SUCCESS ||
 235             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 236                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 237                         "CS4227 EEPROM did not load successfully.");
 238                 return IXGBE_ERR_PHY;
 239         }
 240
 241         return IXGBE_SUCCESS;
 242 }
 243
 244 /**
 245  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 246  * @hw: pointer to hardware structure
 247  **/
 248 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 249 {
 250         s32 status = IXGBE_SUCCESS;
 251         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 252         u16 value = 0;
 253         u8 retry;
 254
 255         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 256                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 257                 if (status != IXGBE_SUCCESS) {
 258                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 259                                 "semaphore failed with %d", status);
 260                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 261                         continue;
 262                 }
 263
 264                 /* Get status of reset flow. */
 265                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 266
 267                 if (status == IXGBE_SUCCESS &&
 268                     value == IXGBE_CS4227_RESET_COMPLETE)
 269                         goto out;
 270
 271                 if (status != IXGBE_SUCCESS ||
 272                     value != IXGBE_CS4227_RESET_PENDING)
 273                         break;
 274
 275                 /* Reset is pending. Wait and check again. */
 276                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 277                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 278         }
 279
 280         /* If still pending, assume other instance failed. */
 281         if (retry == IXGBE_CS4227_RETRIES) {
 282                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 283                 if (status != IXGBE_SUCCESS) {
 284                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 285                                       "semaphore failed with %d", status);
 286                         return;
 287                 }
 288         }
 289
 290         /* Reset the CS4227. */
 291         status = ixgbe_reset_cs4227(hw);
 292         if (status != IXGBE_SUCCESS) {
 293                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 294                         "CS4227 reset failed: %d", status);
 295                 goto out;
 296         }
 297
 298         /* Reset takes so long, temporarily release semaphore in case the
 299          * other driver instance is waiting for the reset indication.
 300          */
 301         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 302                            IXGBE_CS4227_RESET_PENDING);
 303         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 304         msec_delay(10);
 305         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 306         if (status != IXGBE_SUCCESS) {
 307                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 308                         "semaphore failed with %d", status);
 309                 return;
 310         }
 311
 312         /* Record completion for next time. */
 313         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 314                 IXGBE_CS4227_RESET_COMPLETE);
 315
 316 out:
 317         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 318         msec_delay(hw->eeprom.semaphore_delay);
 319 }
 320
 321 /**
 322  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 323  * @hw: pointer to hardware structure
 324  **/
 325 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 326 {
 327         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 328
 329         if (hw->bus.lan_id) {
 330                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 331                 esdp |= IXGBE_ESDP_SDP1_DIR;
 332         }
 333         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 334         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 335         IXGBE_WRITE_FLUSH(hw);
 336 }
 337
 338 /**
 339  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 340  * @hw: pointer to hardware structure
 341  *
 342  * Returns error code
 343  */
 344 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 345 {
 346         hw->mac.ops.set_lan_id(hw);
 347
 348         ixgbe_read_mng_if_sel_x550em(hw);
 349
 350         switch (hw->device_id) {
 351         case IXGBE_DEV_ID_X550EM_A_SFP:
 352                 return ixgbe_identify_module_generic(hw);
 353         case IXGBE_DEV_ID_X550EM_X_SFP:
 354                 /* set up for CS4227 usage */
 355                 ixgbe_setup_mux_ctl(hw);
 356                 ixgbe_check_cs4227(hw);
 357                 /* Fallthrough */
 358
 359         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 360                 return ixgbe_identify_module_generic(hw);
 361                 break;
 362         case IXGBE_DEV_ID_X550EM_X_KX4:
 363                 hw->phy.type = ixgbe_phy_x550em_kx4;
 364                 break;
 365         case IXGBE_DEV_ID_X550EM_X_XFI:
 366                 hw->phy.type = ixgbe_phy_x550em_xfi;
 367                 break;
 368         case IXGBE_DEV_ID_X550EM_X_KR:
 369         case IXGBE_DEV_ID_X550EM_A_KR:
 370         case IXGBE_DEV_ID_X550EM_A_KR_L:
 371                 hw->phy.type = ixgbe_phy_x550em_kr;
 372                 break;
 373         case IXGBE_DEV_ID_X550EM_A_10G_T:
 374         case IXGBE_DEV_ID_X550EM_X_10G_T:
 375                 return ixgbe_identify_phy_generic(hw);
 376         case IXGBE_DEV_ID_X550EM_X_1G_T:
 377                 hw->phy.type = ixgbe_phy_ext_1g_t;
 378                 break;
 379         case IXGBE_DEV_ID_X550EM_A_1G_T:
 380         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 381                 hw->phy.type = ixgbe_phy_fw;
 382                 if (hw->bus.lan_id)
 383                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 384                 else
 385                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 386                 break;
 387         default:
 388                 break;
 389         }
 390         return IXGBE_SUCCESS;
 391 }
 392
 393 /**
 394  * ixgbe_fw_phy_activity - Perform an activity on a PHY
 395  * @hw: pointer to hardware structure
 396  * @activity: activity to perform
 397  * @data: Pointer to 4 32-bit words of data
 398  */
 399 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,
 400                           u32 (*data)[FW_PHY_ACT_DATA_COUNT])
 401 {
 402         union {
 403                 struct ixgbe_hic_phy_activity_req cmd;
 404                 struct ixgbe_hic_phy_activity_resp rsp;
 405         } hic;
 406         u16 retries = FW_PHY_ACT_RETRIES;
 407         s32 rc;
 408         u16 i;
 409
 410         do {
 411                 memset(&hic, 0, sizeof(hic));
 412                 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD;
 413                 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN;
 414                 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 415                 hic.cmd.port_number = hw->bus.lan_id;
 416                 hic.cmd.activity_id = IXGBE_CPU_TO_LE16(activity);
 417                 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
 418                         hic.cmd.data[i] = IXGBE_CPU_TO_BE32((*data)[i]);
 419
 420                 rc = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
 421                                                   sizeof(hic.cmd),
 422                                                   IXGBE_HI_COMMAND_TIMEOUT,
 423                                                   true);
 424                 if (rc != IXGBE_SUCCESS)
 425                         return rc;
 426                 if (hic.rsp.hdr.cmd_or_resp.ret_status ==
 427                     FW_CEM_RESP_STATUS_SUCCESS) {
 428                         for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
 429                                 (*data)[i] = IXGBE_BE32_TO_CPU(hic.rsp.data[i]);
 430                         return IXGBE_SUCCESS;
 431                 }
 432                 usec_delay(20);
 433                 --retries;
 434         } while (retries > 0);
 435
 436         return IXGBE_ERR_HOST_INTERFACE_COMMAND;
 437 }
 438
 439 static const struct {
 440         u16 fw_speed;
 441         ixgbe_link_speed phy_speed;
 442 } ixgbe_fw_map[] = {
 443         { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL },
 444         { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL },
 445         { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL },
 446         { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL },
 447         { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL },
 448         { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL },
 449 };
 450
 451 /**
 452  * ixgbe_get_phy_id_fw - Get the phy ID via firmware command
 453  * @hw: pointer to hardware structure
 454  *
 455  * Returns error code
 456  */
 457 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw)
 458 {
 459         u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
 460         u16 phy_speeds;
 461         u16 phy_id_lo;
 462         s32 rc;
 463         u16 i;
 464
 465         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info);
 466         if (rc)
 467                 return rc;
 468
 469         hw->phy.speeds_supported = 0;
 470         phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK;
 471         for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
 472                 if (phy_speeds & ixgbe_fw_map[i].fw_speed)
 473                         hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed;
 474         }
 475         if (!hw->phy.autoneg_advertised)
 476                 hw->phy.autoneg_advertised = hw->phy.speeds_supported;
 477
 478         hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK;
 479         phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK;
 480         hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK;
 481         hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK;
 482         if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK)
 483                 return IXGBE_ERR_PHY_ADDR_INVALID;
 484         return IXGBE_SUCCESS;
 485 }
 486
 487 /**
 488  * ixgbe_identify_phy_fw - Get PHY type based on firmware command
 489  * @hw: pointer to hardware structure
 490  *
 491  * Returns error code
 492  */
 493 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw)
 494 {
 495         if (hw->bus.lan_id)
 496                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 497         else
 498                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 499
 500         hw->phy.type = ixgbe_phy_fw;
 501         hw->phy.ops.read_reg = NULL;
 502         hw->phy.ops.write_reg = NULL;
 503         return ixgbe_get_phy_id_fw(hw);
 504 }
 505
 506 /**
 507  * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY
 508  * @hw: pointer to hardware structure
 509  *
 510  * Returns error code
 511  */
 512 s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw)
 513 {
 514         u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
 515
 516         setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF;
 517         return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup);
 518 }
 519
 520 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 521                                      u32 device_type, u16 *phy_data)
 522 {
 523         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 524         return IXGBE_NOT_IMPLEMENTED;
 525 }
 526
 527 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 528                                       u32 device_type, u16 phy_data)
 529 {
 530         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 531         return IXGBE_NOT_IMPLEMENTED;
 532 }
 533
 534 /**
 535  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 536  * @hw: pointer to the hardware structure
 537  * @addr: I2C bus address to read from
 538  * @reg: I2C device register to read from
 539  * @val: pointer to location to receive read value
 540  *
 541  * Returns an error code on error.
 542  **/
 543 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 544                                            u16 reg, u16 *val)
 545 {
 546         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 547 }
 548
 549 /**
 550  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 551  * @hw: pointer to the hardware structure
 552  * @addr: I2C bus address to read from
 553  * @reg: I2C device register to read from
 554  * @val: pointer to location to receive read value
 555  *
 556  * Returns an error code on error.
 557  **/
 558 STATIC s32
 559 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 560                                          u16 reg, u16 *val)
 561 {
 562         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 563 }
 564
 565 /**
 566  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 567  * @hw: pointer to the hardware structure
 568  * @addr: I2C bus address to write to
 569  * @reg: I2C device register to write to
 570  * @val: value to write
 571  *
 572  * Returns an error code on error.
 573  **/
 574 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 575                                             u8 addr, u16 reg, u16 val)
 576 {
 577         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 578 }
 579
 580 /**
 581  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 582  * @hw: pointer to the hardware structure
 583  * @addr: I2C bus address to write to
 584  * @reg: I2C device register to write to
 585  * @val: value to write
 586  *
 587  * Returns an error code on error.
 588  **/
 589 STATIC s32
 590 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 591                                           u8 addr, u16 reg, u16 val)
 592 {
 593         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 594 }
 595
 596 /**
 597 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 598 *  @hw: pointer to hardware structure
 599 *
 600 *  Initialize the function pointers and for MAC type X550EM.
 601 *  Does not touch the hardware.
 602 **/
 603 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 604 {
 605         struct ixgbe_mac_info *mac = &hw->mac;
 606         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 607         struct ixgbe_phy_info *phy = &hw->phy;
 608         s32 ret_val;
 609
 610         DEBUGFUNC("ixgbe_init_ops_X550EM");
 611
 612         /* Similar to X550 so start there. */
 613         ret_val = ixgbe_init_ops_X550(hw);
 614
 615         /* Since this function eventually calls
 616          * ixgbe_init_ops_540 by design, we are setting
 617          * the pointers to NULL explicitly here to overwrite
 618          * the values being set in the x540 function.
 619          */
 620         /* Thermal sensor not supported in x550EM */
 621         mac->ops.get_thermal_sensor_data = NULL;
 622         mac->ops.init_thermal_sensor_thresh = NULL;
 623         mac->thermal_sensor_enabled = false;
 624
 625         /* FCOE not supported in x550EM */
 626         mac->ops.get_san_mac_addr = NULL;
 627         mac->ops.set_san_mac_addr = NULL;
 628         mac->ops.get_wwn_prefix = NULL;
 629         mac->ops.get_fcoe_boot_status = NULL;
 630
 631         /* IPsec not supported in x550EM */
 632         mac->ops.disable_sec_rx_path = NULL;
 633         mac->ops.enable_sec_rx_path = NULL;
 634
 635         /* AUTOC register is not present in x550EM. */
 636         mac->ops.prot_autoc_read = NULL;
 637         mac->ops.prot_autoc_write = NULL;
 638
 639         /* X550EM bus type is internal*/
 640         hw->bus.type = ixgbe_bus_type_internal;
 641         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 642
 643
 644         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 645         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 646         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 647         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 648         mac->ops.get_supported_physical_layer =
 649                                     ixgbe_get_supported_physical_layer_X550em;
 650
 651         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 652                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 653         else
 654                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 655
 656         /* PHY */
 657         phy->ops.init = ixgbe_init_phy_ops_X550em;
 658         switch (hw->device_id) {
 659         case IXGBE_DEV_ID_X550EM_A_1G_T:
 660         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 661                 mac->ops.setup_fc = NULL;
 662                 phy->ops.identify = ixgbe_identify_phy_fw;
 663                 phy->ops.set_phy_power = NULL;
 664                 phy->ops.get_firmware_version = NULL;
 665                 break;
 666         case IXGBE_DEV_ID_X550EM_X_1G_T:
 667                 mac->ops.setup_fc = NULL;
 668                 phy->ops.identify = ixgbe_identify_phy_x550em;
 669                 phy->ops.set_phy_power = NULL;
 670                 break;
 671         default:
 672                 phy->ops.identify = ixgbe_identify_phy_x550em;
 673         }
 674
 675         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 676                 phy->ops.set_phy_power = NULL;
 677
 678
 679         /* EEPROM */
 680         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 681         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 682         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 683         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 684         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 685         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 686         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 687         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 688
 689         return ret_val;
 690 }
 691
 692 /**
 693  * ixgbe_setup_fw_link - Setup firmware-controlled PHYs
 694  * @hw: pointer to hardware structure
 695  */
 696 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw)
 697 {
 698         u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
 699         s32 rc;
 700         u16 i;
 701
 702         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
 703                 return 0;
 704
 705         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
 706                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
 707                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
 708                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
 709         }
 710
 711         switch (hw->fc.requested_mode) {
 712         case ixgbe_fc_full:
 713                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX <<
 714                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 715                 break;
 716         case ixgbe_fc_rx_pause:
 717                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX <<
 718                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 719                 break;
 720         case ixgbe_fc_tx_pause:
 721                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX <<
 722                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 723                 break;
 724         default:
 725                 break;
 726         }
 727
 728         for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
 729                 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)
 730                         setup[0] |= ixgbe_fw_map[i].fw_speed;
 731         }
 732         setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN;
 733
 734         if (hw->phy.eee_speeds_advertised)
 735                 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE;
 736
 737         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup);
 738         if (rc)
 739                 return rc;
 740         if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN)
 741                 return IXGBE_ERR_OVERTEMP;
 742         return IXGBE_SUCCESS;
 743 }
 744
 745 /**
 746  * ixgbe_fc_autoneg_fw _ Set up flow control for FW-controlled PHYs
 747  * @hw: pointer to hardware structure
 748  *
 749  *  Called at init time to set up flow control.
 750  */
 751 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw)
 752 {
 753         if (hw->fc.requested_mode == ixgbe_fc_default)
 754                 hw->fc.requested_mode = ixgbe_fc_full;
 755
 756         return ixgbe_setup_fw_link(hw);
 757 }
 758
 759 /**
 760  * ixgbe_setup_eee_fw - Enable/disable EEE support
 761  * @hw: pointer to the HW structurewrite_reg_mdi
 762  * @enable_eee: boolean flag to enable EEE
 763  *
 764  * Enable/disable EEE based on enable_eee flag.
 765  * This function controls EEE for firmware-based PHY implementations.
 766  */
 767 static s32 ixgbe_setup_eee_fw(struct ixgbe_hw *hw, bool enable_eee)
 768 {
 769         if (!!hw->phy.eee_speeds_advertised == enable_eee)
 770                 return IXGBE_SUCCESS;
 771         if (enable_eee)
 772                 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
 773         else
 774                 hw->phy.eee_speeds_advertised = 0;
 775         return hw->phy.ops.setup_link(hw);
 776 }
 777
 778 /**
 779 *  ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
 780 *  @hw: pointer to hardware structure
 781 *
 782 *  Initialize the function pointers and for MAC type X550EM_a.
 783 *  Does not touch the hardware.
 784 **/
 785 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
 786 {
 787         struct ixgbe_mac_info *mac = &hw->mac;
 788         s32 ret_val;
 789
 790         DEBUGFUNC("ixgbe_init_ops_X550EM_a");
 791
 792         /* Start with generic X550EM init */
 793         ret_val = ixgbe_init_ops_X550EM(hw);
 794
 795         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
 796             hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) {
 797                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 798                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 799         } else {
 800                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
 801                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
 802         }
 803         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
 804         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
 805
 806         switch (mac->ops.get_media_type(hw)) {
 807         case ixgbe_media_type_fiber:
 808                 mac->ops.setup_fc = NULL;
 809                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
 810                 break;
 811         case ixgbe_media_type_backplane:
 812                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
 813                 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
 814                 break;
 815         default:
 816                 break;
 817         }
 818
 819         switch (hw->device_id) {
 820         case IXGBE_DEV_ID_X550EM_A_1G_T:
 821         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 822                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
 823                 mac->ops.setup_fc = ixgbe_fc_autoneg_fw;
 824                 mac->ops.setup_eee = ixgbe_setup_eee_fw;
 825                 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL |
 826                                                IXGBE_LINK_SPEED_1GB_FULL;
 827                 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
 828                 break;
 829         default:
 830                 break;
 831         }
 832
 833         return ret_val;
 834 }
 835
 836 /**
 837 *  ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
 838 *  @hw: pointer to hardware structure
 839 *
 840 *  Initialize the function pointers and for MAC type X550EM_x.
 841 *  Does not touch the hardware.
 842 **/
 843 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
 844 {
 845         struct ixgbe_mac_info *mac = &hw->mac;
 846         struct ixgbe_link_info *link = &hw->link;
 847         s32 ret_val;
 848
 849         DEBUGFUNC("ixgbe_init_ops_X550EM_x");
 850
 851         /* Start with generic X550EM init */
 852         ret_val = ixgbe_init_ops_X550EM(hw);
 853
 854         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 855         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 856         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 857         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 858         link->ops.read_link = ixgbe_read_i2c_combined_generic;
 859         link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
 860         link->ops.write_link = ixgbe_write_i2c_combined_generic;
 861         link->ops.write_link_unlocked =
 862                                       ixgbe_write_i2c_combined_generic_unlocked;
 863         link->addr = IXGBE_CS4227;
 864
 865         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T) {
 866                 mac->ops.setup_fc = NULL;
 867                 mac->ops.setup_eee = NULL;
 868                 mac->ops.init_led_link_act = NULL;
 869         }
 870
 871         return ret_val;
 872 }
 873
 874 /**
 875  *  ixgbe_dmac_config_X550
 876  *  @hw: pointer to hardware structure
 877  *
 878  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 879  *  When disabling dmac, dmac enable dmac bit is cleared.
 880  **/
 881 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 882 {
 883         u32 reg, high_pri_tc;
 884
 885         DEBUGFUNC("ixgbe_dmac_config_X550");
 886
 887         /* Disable DMA coalescing before configuring */
 888         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 889         reg &= ~IXGBE_DMACR_DMAC_EN;
 890         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 891
 892         /* Disable DMA Coalescing if the watchdog timer is 0 */
 893         if (!hw->mac.dmac_config.watchdog_timer)
 894                 goto out;
 895
 896         ixgbe_dmac_config_tcs_X550(hw);
 897
 898         /* Configure DMA Coalescing Control Register */
 899         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 900
 901         /* Set the watchdog timer in units of 40.96 usec */
 902         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 903         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 904
 905         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 906         /* If fcoe is enabled, set high priority traffic class */
 907         if (hw->mac.dmac_config.fcoe_en) {
 908                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 909                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 910                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 911         }
 912         reg |= IXGBE_DMACR_EN_MNG_IND;
 913
 914         /* Enable DMA coalescing after configuration */
 915         reg |= IXGBE_DMACR_DMAC_EN;
 916         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 917
 918 out:
 919         return IXGBE_SUCCESS;
 920 }
 921
 922 /**
 923  *  ixgbe_dmac_config_tcs_X550
 924  *  @hw: pointer to hardware structure
 925  *
 926  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 927  *  be cleared before configuring.
 928  **/
 929 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 930 {
 931         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 932
 933         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 934
 935         /* Configure DMA coalescing enabled */
 936         switch (hw->mac.dmac_config.link_speed) {
 937         case IXGBE_LINK_SPEED_10_FULL:
 938         case IXGBE_LINK_SPEED_100_FULL:
 939                 pb_headroom = IXGBE_DMACRXT_100M;
 940                 break;
 941         case IXGBE_LINK_SPEED_1GB_FULL:
 942                 pb_headroom = IXGBE_DMACRXT_1G;
 943                 break;
 944         default:
 945                 pb_headroom = IXGBE_DMACRXT_10G;
 946                 break;
 947         }
 948
 949         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 950                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 951
 952         /* Set the per Rx packet buffer receive threshold */
 953         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 954                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 955                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 956
 957                 if (tc < hw->mac.dmac_config.num_tcs) {
 958                         /* Get Rx PB size */
 959                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 960                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 961                                 IXGBE_RXPBSIZE_SHIFT;
 962
 963                         /* Calculate receive buffer threshold in kilobytes */
 964                         if (rx_pb_size > pb_headroom)
 965                                 rx_pb_size = rx_pb_size - pb_headroom;
 966                         else
 967                                 rx_pb_size = 0;
 968
 969                         /* Minimum of MFS shall be set for DMCTH */
 970                         reg |= (rx_pb_size > maxframe_size_kb) ?
 971                                 rx_pb_size : maxframe_size_kb;
 972                 }
 973                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 974         }
 975         return IXGBE_SUCCESS;
 976 }
 977
 978 /**
 979  *  ixgbe_dmac_update_tcs_X550
 980  *  @hw: pointer to hardware structure
 981  *
 982  *  Disables dmac, updates per TC settings, and then enables dmac.
 983  **/
 984 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 985 {
 986         u32 reg;
 987
 988         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 989
 990         /* Disable DMA coalescing before configuring */
 991         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 992         reg &= ~IXGBE_DMACR_DMAC_EN;
 993         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 994
 995         ixgbe_dmac_config_tcs_X550(hw);
 996
 997         /* Enable DMA coalescing after configuration */
 998         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 999         reg |= IXGBE_DMACR_DMAC_EN;
1000         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
1001
1002         return IXGBE_SUCCESS;
1003 }
1004
1005 /**
1006  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
1007  *  @hw: pointer to hardware structure
1008  *
1009  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
1010  *  ixgbe_hw struct in order to set up EEPROM access.
1011  **/
1012 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
1013 {
1014         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1015         u32 eec;
1016         u16 eeprom_size;
1017
1018         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
1019
1020         if (eeprom->type == ixgbe_eeprom_uninitialized) {
1021                 eeprom->semaphore_delay = 10;
1022                 eeprom->type = ixgbe_flash;
1023
1024                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1025                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1026                                     IXGBE_EEC_SIZE_SHIFT);
1027                 eeprom->word_size = 1 << (eeprom_size +
1028                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
1029
1030                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
1031                           eeprom->type, eeprom->word_size);
1032         }
1033
1034         return IXGBE_SUCCESS;
1035 }
1036
1037 /**
1038  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1039  * @hw: pointer to hardware structure
1040  * @enable: enable or disable source address pruning
1041  * @pool: Rx pool to set source address pruning for
1042  **/
1043 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1044                                            unsigned int pool)
1045 {
1046         u64 pfflp;
1047
1048         /* max rx pool is 63 */
1049         if (pool > 63)
1050                 return;
1051
1052         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1053         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1054
1055         if (enable)
1056                 pfflp |= (1ULL << pool);
1057         else
1058                 pfflp &= ~(1ULL << pool);
1059
1060         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1061         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1062 }
1063
1064 /**
1065  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1066  *  @hw: pointer to hardware structure
1067  *  @enable: enable or disable switch for Ethertype anti-spoofing
1068  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1069  *
1070  **/
1071 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1072                 bool enable, int vf)
1073 {
1074         int vf_target_reg = vf >> 3;
1075         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1076         u32 pfvfspoof;
1077
1078         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1079
1080         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1081         if (enable)
1082                 pfvfspoof |= (1 << vf_target_shift);
1083         else
1084                 pfvfspoof &= ~(1 << vf_target_shift);
1085
1086         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1087 }
1088
1089 /**
1090  * ixgbe_iosf_wait - Wait for IOSF command completion
1091  * @hw: pointer to hardware structure
1092  * @ctrl: pointer to location to receive final IOSF control value
1093  *
1094  * Returns failing status on timeout
1095  *
1096  * Note: ctrl can be NULL if the IOSF control register value is not needed
1097  **/
1098 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1099 {
1100         u32 i, command = 0;
1101
1102         /* Check every 10 usec to see if the address cycle completed.
1103          * The SB IOSF BUSY bit will clear when the operation is
1104          * complete
1105          */
1106         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1107                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1108                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1109                         break;
1110                 usec_delay(10);
1111         }
1112         if (ctrl)
1113                 *ctrl = command;
1114         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1115                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1116                 return IXGBE_ERR_PHY;
1117         }
1118
1119         return IXGBE_SUCCESS;
1120 }
1121
1122 /**
1123  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register
1124  *  of the IOSF device
1125  *  @hw: pointer to hardware structure
1126  *  @reg_addr: 32 bit PHY register to write
1127  *  @device_type: 3 bit device type
1128  *  @data: Data to write to the register
1129  **/
1130 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1131                             u32 device_type, u32 data)
1132 {
1133         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1134         u32 command, error;
1135         s32 ret;
1136
1137         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1138         if (ret != IXGBE_SUCCESS)
1139                 return ret;
1140
1141         ret = ixgbe_iosf_wait(hw, NULL);
1142         if (ret != IXGBE_SUCCESS)
1143                 goto out;
1144
1145         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1146                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1147
1148         /* Write IOSF control register */
1149         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1150
1151         /* Write IOSF data register */
1152         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1153
1154         ret = ixgbe_iosf_wait(hw, &command);
1155
1156         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1157                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1158                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1159                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1160                               "Failed to write, error %x\n", error);
1161                 ret = IXGBE_ERR_PHY;
1162         }
1163
1164 out:
1165         ixgbe_release_swfw_semaphore(hw, gssr);
1166         return ret;
1167 }
1168
1169 /**
1170  *  ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device
1171  *  @hw: pointer to hardware structure
1172  *  @reg_addr: 32 bit PHY register to write
1173  *  @device_type: 3 bit device type
1174  *  @data: Pointer to read data from the register
1175  **/
1176 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1177                            u32 device_type, u32 *data)
1178 {
1179         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1180         u32 command, error;
1181         s32 ret;
1182
1183         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1184         if (ret != IXGBE_SUCCESS)
1185                 return ret;
1186
1187         ret = ixgbe_iosf_wait(hw, NULL);
1188         if (ret != IXGBE_SUCCESS)
1189                 goto out;
1190
1191         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1192                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1193
1194         /* Write IOSF control register */
1195         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1196
1197         ret = ixgbe_iosf_wait(hw, &command);
1198
1199         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1200                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1201                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1202                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1203                                 "Failed to read, error %x\n", error);
1204                 ret = IXGBE_ERR_PHY;
1205         }
1206
1207         if (ret == IXGBE_SUCCESS)
1208                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1209
1210 out:
1211         ixgbe_release_swfw_semaphore(hw, gssr);
1212         return ret;
1213 }
1214
1215 /**
1216  * ixgbe_get_phy_token - Get the token for shared phy access
1217  * @hw: Pointer to hardware structure
1218  */
1219
1220 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1221 {
1222         struct ixgbe_hic_phy_token_req token_cmd;
1223         s32 status;
1224
1225         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1226         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1227         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1228         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1229         token_cmd.port_number = hw->bus.lan_id;
1230         token_cmd.command_type = FW_PHY_TOKEN_REQ;
1231         token_cmd.pad = 0;
1232         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1233                                               sizeof(token_cmd),
1234                                               IXGBE_HI_COMMAND_TIMEOUT,
1235                                               true);
1236         if (status) {
1237                 DEBUGOUT1("Issuing host interface command failed with Status = %d\n",
1238                           status);
1239                 return status;
1240         }
1241         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1242                 return IXGBE_SUCCESS;
1243         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY) {
1244                 DEBUGOUT1("Host interface command returned 0x%08x , returning IXGBE_ERR_FW_RESP_INVALID\n",
1245                           token_cmd.hdr.cmd_or_resp.ret_status);
1246                 return IXGBE_ERR_FW_RESP_INVALID;
1247         }
1248
1249         DEBUGOUT("Returning  IXGBE_ERR_TOKEN_RETRY\n");
1250         return IXGBE_ERR_TOKEN_RETRY;
1251 }
1252
1253 /**
1254  * ixgbe_put_phy_token - Put the token for shared phy access
1255  * @hw: Pointer to hardware structure
1256  */
1257
1258 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1259 {
1260         struct ixgbe_hic_phy_token_req token_cmd;
1261         s32 status;
1262
1263         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1264         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1265         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1266         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1267         token_cmd.port_number = hw->bus.lan_id;
1268         token_cmd.command_type = FW_PHY_TOKEN_REL;
1269         token_cmd.pad = 0;
1270         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1271                                               sizeof(token_cmd),
1272                                               IXGBE_HI_COMMAND_TIMEOUT,
1273                                               true);
1274         if (status)
1275                 return status;
1276         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1277                 return IXGBE_SUCCESS;
1278
1279         DEBUGOUT("Put PHY Token host interface command failed");
1280         return IXGBE_ERR_FW_RESP_INVALID;
1281 }
1282
1283 /**
1284  *  ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1285  *  of the IOSF device
1286  *  @hw: pointer to hardware structure
1287  *  @reg_addr: 32 bit PHY register to write
1288  *  @device_type: 3 bit device type
1289  *  @data: Data to write to the register
1290  **/
1291 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1292                                   u32 device_type, u32 data)
1293 {
1294         struct ixgbe_hic_internal_phy_req write_cmd;
1295         s32 status;
1296         UNREFERENCED_1PARAMETER(device_type);
1297
1298         memset(&write_cmd, 0, sizeof(write_cmd));
1299         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1300         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1301         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1302         write_cmd.port_number = hw->bus.lan_id;
1303         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1304         write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1305         write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1306
1307         status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1308                                               sizeof(write_cmd),
1309                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1310
1311         return status;
1312 }
1313
1314 /**
1315  *  ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device
1316  *  @hw: pointer to hardware structure
1317  *  @reg_addr: 32 bit PHY register to write
1318  *  @device_type: 3 bit device type
1319  *  @data: Pointer to read data from the register
1320  **/
1321 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1322                                  u32 device_type, u32 *data)
1323 {
1324         union {
1325                 struct ixgbe_hic_internal_phy_req cmd;
1326                 struct ixgbe_hic_internal_phy_resp rsp;
1327         } hic;
1328         s32 status;
1329         UNREFERENCED_1PARAMETER(device_type);
1330
1331         memset(&hic, 0, sizeof(hic));
1332         hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1333         hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1334         hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1335         hic.cmd.port_number = hw->bus.lan_id;
1336         hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1337         hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1338
1339         status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1340                                               sizeof(hic.cmd),
1341                                               IXGBE_HI_COMMAND_TIMEOUT, true);
1342
1343         /* Extract the register value from the response. */
1344         *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1345
1346         return status;
1347 }
1348
1349 /**
1350  *  ixgbe_disable_mdd_X550
1351  *  @hw: pointer to hardware structure
1352  *
1353  *  Disable malicious driver detection
1354  **/
1355 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1356 {
1357         u32 reg;
1358
1359         DEBUGFUNC("ixgbe_disable_mdd_X550");
1360
1361         /* Disable MDD for TX DMA and interrupt */
1362         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1363         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1364         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1365
1366         /* Disable MDD for RX and interrupt */
1367         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1368         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1369         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1370 }
1371
1372 /**
1373  *  ixgbe_enable_mdd_X550
1374  *  @hw: pointer to hardware structure
1375  *
1376  *  Enable malicious driver detection
1377  **/
1378 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1379 {
1380         u32 reg;
1381
1382         DEBUGFUNC("ixgbe_enable_mdd_X550");
1383
1384         /* Enable MDD for TX DMA and interrupt */
1385         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1386         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1387         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1388
1389         /* Enable MDD for RX and interrupt */
1390         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1391         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1392         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1393 }
1394
1395 /**
1396  *  ixgbe_restore_mdd_vf_X550
1397  *  @hw: pointer to hardware structure
1398  *  @vf: vf index
1399  *
1400  *  Restore VF that was disabled during malicious driver detection event
1401  **/
1402 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1403 {
1404         u32 idx, reg, num_qs, start_q, bitmask;
1405
1406         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1407
1408         /* Map VF to queues */
1409         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1410         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1411         case IXGBE_MRQC_VMDQRT8TCEN:
1412                 num_qs = 8;  /* 16 VFs / pools */
1413                 bitmask = 0x000000FF;
1414                 break;
1415         case IXGBE_MRQC_VMDQRSS32EN:
1416         case IXGBE_MRQC_VMDQRT4TCEN:
1417                 num_qs = 4;  /* 32 VFs / pools */
1418                 bitmask = 0x0000000F;
1419                 break;
1420         default:            /* 64 VFs / pools */
1421                 num_qs = 2;
1422                 bitmask = 0x00000003;
1423                 break;
1424         }
1425         start_q = vf * num_qs;
1426
1427         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1428         idx = start_q / 32;
1429         reg = 0;
1430         reg |= (bitmask << (start_q % 32));
1431         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1432         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1433 }
1434
1435 /**
1436  *  ixgbe_mdd_event_X550
1437  *  @hw: pointer to hardware structure
1438  *  @vf_bitmap: vf bitmap of malicious vfs
1439  *
1440  *  Handle malicious driver detection event.
1441  **/
1442 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1443 {
1444         u32 wqbr;
1445         u32 i, j, reg, q, shift, vf, idx;
1446
1447         DEBUGFUNC("ixgbe_mdd_event_X550");
1448
1449         /* figure out pool size for mapping to vf's */
1450         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1451         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1452         case IXGBE_MRQC_VMDQRT8TCEN:
1453                 shift = 3;  /* 16 VFs / pools */
1454                 break;
1455         case IXGBE_MRQC_VMDQRSS32EN:
1456         case IXGBE_MRQC_VMDQRT4TCEN:
1457                 shift = 2;  /* 32 VFs / pools */
1458                 break;
1459         default:
1460                 shift = 1;  /* 64 VFs / pools */
1461                 break;
1462         }
1463
1464         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1465         for (i = 0; i < 4; i++) {
1466                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1467                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1468
1469                 if (!wqbr)
1470                         continue;
1471
1472                 /* Get malicious queue */
1473                 for (j = 0; j < 32 && wqbr; j++) {
1474
1475                         if (!(wqbr & (1 << j)))
1476                                 continue;
1477
1478                         /* Get queue from bitmask */
1479                         q = j + (i * 32);
1480
1481                         /* Map queue to vf */
1482                         vf = (q >> shift);
1483
1484                         /* Set vf bit in vf_bitmap */
1485                         idx = vf / 32;
1486                         vf_bitmap[idx] |= (1 << (vf % 32));
1487                         wqbr &= ~(1 << j);
1488                 }
1489         }
1490 }
1491
1492 /**
1493  *  ixgbe_get_media_type_X550em - Get media type
1494  *  @hw: pointer to hardware structure
1495  *
1496  *  Returns the media type (fiber, copper, backplane)
1497  */
1498 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1499 {
1500         enum ixgbe_media_type media_type;
1501
1502         DEBUGFUNC("ixgbe_get_media_type_X550em");
1503
1504         /* Detect if there is a copper PHY attached. */
1505         switch (hw->device_id) {
1506         case IXGBE_DEV_ID_X550EM_X_KR:
1507         case IXGBE_DEV_ID_X550EM_X_KX4:
1508         case IXGBE_DEV_ID_X550EM_X_XFI:
1509         case IXGBE_DEV_ID_X550EM_A_KR:
1510         case IXGBE_DEV_ID_X550EM_A_KR_L:
1511                 media_type = ixgbe_media_type_backplane;
1512                 break;
1513         case IXGBE_DEV_ID_X550EM_X_SFP:
1514         case IXGBE_DEV_ID_X550EM_A_SFP:
1515         case IXGBE_DEV_ID_X550EM_A_SFP_N:
1516         case IXGBE_DEV_ID_X550EM_A_QSFP:
1517         case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1518                 media_type = ixgbe_media_type_fiber;
1519                 break;
1520         case IXGBE_DEV_ID_X550EM_X_1G_T:
1521         case IXGBE_DEV_ID_X550EM_X_10G_T:
1522         case IXGBE_DEV_ID_X550EM_A_10G_T:
1523                 media_type = ixgbe_media_type_copper;
1524                 break;
1525         case IXGBE_DEV_ID_X550EM_A_SGMII:
1526         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1527                 media_type = ixgbe_media_type_backplane;
1528                 hw->phy.type = ixgbe_phy_sgmii;
1529                 break;
1530         case IXGBE_DEV_ID_X550EM_A_1G_T:
1531         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1532                 media_type = ixgbe_media_type_copper;
1533                 break;
1534         default:
1535                 media_type = ixgbe_media_type_unknown;
1536                 break;
1537         }
1538         return media_type;
1539 }
1540
1541 /**
1542  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1543  *  @hw: pointer to hardware structure
1544  *  @linear: true if SFP module is linear
1545  */
1546 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1547 {
1548         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1549
1550         switch (hw->phy.sfp_type) {
1551         case ixgbe_sfp_type_not_present:
1552                 return IXGBE_ERR_SFP_NOT_PRESENT;
1553         case ixgbe_sfp_type_da_cu_core0:
1554         case ixgbe_sfp_type_da_cu_core1:
1555                 *linear = true;
1556                 break;
1557         case ixgbe_sfp_type_srlr_core0:
1558         case ixgbe_sfp_type_srlr_core1:
1559         case ixgbe_sfp_type_da_act_lmt_core0:
1560         case ixgbe_sfp_type_da_act_lmt_core1:
1561         case ixgbe_sfp_type_1g_sx_core0:
1562         case ixgbe_sfp_type_1g_sx_core1:
1563         case ixgbe_sfp_type_1g_lx_core0:
1564         case ixgbe_sfp_type_1g_lx_core1:
1565                 *linear = false;
1566                 break;
1567         case ixgbe_sfp_type_unknown:
1568         case ixgbe_sfp_type_1g_cu_core0:
1569         case ixgbe_sfp_type_1g_cu_core1:
1570         default:
1571                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1572         }
1573
1574         return IXGBE_SUCCESS;
1575 }
1576
1577 /**
1578  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1579  *  @hw: pointer to hardware structure
1580  *
1581  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1582  **/
1583 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1584 {
1585         s32 status;
1586         bool linear;
1587
1588         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1589
1590         status = ixgbe_identify_module_generic(hw);
1591
1592         if (status != IXGBE_SUCCESS)
1593                 return status;
1594
1595         /* Check if SFP module is supported */
1596         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1597
1598         return status;
1599 }
1600
1601 /**
1602  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1603  *  @hw: pointer to hardware structure
1604  */
1605 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1606 {
1607         s32 status;
1608         bool linear;
1609
1610         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1611
1612         /* Check if SFP module is supported */
1613         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1614
1615         if (status != IXGBE_SUCCESS)
1616                 return status;
1617
1618         ixgbe_init_mac_link_ops_X550em(hw);
1619         hw->phy.ops.reset = NULL;
1620
1621         return IXGBE_SUCCESS;
1622 }
1623
1624 /**
1625 *  ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1626 *  internal PHY
1627 *  @hw: pointer to hardware structure
1628 **/
1629 STATIC s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1630 {
1631         s32 status;
1632         u32 link_ctrl;
1633
1634         /* Restart auto-negotiation. */
1635         status = hw->mac.ops.read_iosf_sb_reg(hw,
1636                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1637                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1638
1639         if (status) {
1640                 DEBUGOUT("Auto-negotiation did not complete\n");
1641                 return status;
1642         }
1643
1644         link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1645         status = hw->mac.ops.write_iosf_sb_reg(hw,
1646                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1647                                         IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1648
1649         if (hw->mac.type == ixgbe_mac_X550EM_a) {
1650                 u32 flx_mask_st20;
1651
1652                 /* Indicate to FW that AN restart has been asserted */
1653                 status = hw->mac.ops.read_iosf_sb_reg(hw,
1654                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1655                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1656
1657                 if (status) {
1658                         DEBUGOUT("Auto-negotiation did not complete\n");
1659                         return status;
1660                 }
1661
1662                 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1663                 status = hw->mac.ops.write_iosf_sb_reg(hw,
1664                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1665                                 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1666         }
1667
1668         return status;
1669 }
1670
1671 #ifndef PREBOOT_SUPPORT
1672 /**
1673  * ixgbe_setup_sgmii - Set up link for sgmii
1674  * @hw: pointer to hardware structure
1675  * @speed: new link speed
1676  * @autoneg_wait: true when waiting for completion is needed
1677  */
1678 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1679                              bool autoneg_wait)
1680 {
1681         struct ixgbe_mac_info *mac = &hw->mac;
1682         u32 lval, sval, flx_val;
1683         s32 rc;
1684
1685         rc = mac->ops.read_iosf_sb_reg(hw,
1686                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1687                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1688         if (rc)
1689                 return rc;
1690
1691         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1692         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1693         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1694         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1695         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1696         rc = mac->ops.write_iosf_sb_reg(hw,
1697                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1698                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1699         if (rc)
1700                 return rc;
1701
1702         rc = mac->ops.read_iosf_sb_reg(hw,
1703                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1704                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1705         if (rc)
1706                 return rc;
1707
1708         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1709         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1710         rc = mac->ops.write_iosf_sb_reg(hw,
1711                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1712                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1713         if (rc)
1714                 return rc;
1715
1716         rc = mac->ops.read_iosf_sb_reg(hw,
1717                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1718                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1719         if (rc)
1720                 return rc;
1721
1722         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1723         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1724         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1725         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1726         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1727
1728         rc = mac->ops.write_iosf_sb_reg(hw,
1729                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1730                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1731         if (rc)
1732                 return rc;
1733
1734         rc = ixgbe_restart_an_internal_phy_x550em(hw);
1735         if (rc)
1736                 return rc;
1737
1738         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1739 }
1740
1741 #endif /* PREBOOT_SUPPORT */
1742 /**
1743  * ixgbe_setup_sgmii_fw - Set up link for internal PHY SGMII auto-negotiation
1744  * @hw: pointer to hardware structure
1745  * @speed: new link speed
1746  * @autoneg_wait: true when waiting for completion is needed
1747  */
1748 STATIC s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1749                                 bool autoneg_wait)
1750 {
1751         struct ixgbe_mac_info *mac = &hw->mac;
1752         u32 lval, sval, flx_val;
1753         s32 rc;
1754
1755         rc = mac->ops.read_iosf_sb_reg(hw,
1756                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1757                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1758         if (rc)
1759                 return rc;
1760
1761         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1762         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1763         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1764         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1765         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1766         rc = mac->ops.write_iosf_sb_reg(hw,
1767                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1768                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1769         if (rc)
1770                 return rc;
1771
1772         rc = mac->ops.read_iosf_sb_reg(hw,
1773                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1774                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1775         if (rc)
1776                 return rc;
1777
1778         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1779         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1780         rc = mac->ops.write_iosf_sb_reg(hw,
1781                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1782                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1783         if (rc)
1784                 return rc;
1785
1786         rc = mac->ops.write_iosf_sb_reg(hw,
1787                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1788                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1789         if (rc)
1790                 return rc;
1791
1792         rc = mac->ops.read_iosf_sb_reg(hw,
1793                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1794                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1795         if (rc)
1796                 return rc;
1797
1798         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1799         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
1800         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1801         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1802         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1803
1804         rc = mac->ops.write_iosf_sb_reg(hw,
1805                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1806                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1807         if (rc)
1808                 return rc;
1809
1810         rc = ixgbe_restart_an_internal_phy_x550em(hw);
1811
1812         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1813 }
1814
1815 /**
1816  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1817  *  @hw: pointer to hardware structure
1818  */
1819 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1820 {
1821         struct ixgbe_mac_info *mac = &hw->mac;
1822
1823         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1824
1825         switch (hw->mac.ops.get_media_type(hw)) {
1826         case ixgbe_media_type_fiber:
1827                 /* CS4227 does not support autoneg, so disable the laser control
1828                  * functions for SFP+ fiber
1829                  */
1830                 mac->ops.disable_tx_laser = NULL;
1831                 mac->ops.enable_tx_laser = NULL;
1832                 mac->ops.flap_tx_laser = NULL;
1833                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1834                 mac->ops.set_rate_select_speed =
1835                                         ixgbe_set_soft_rate_select_speed;
1836
1837                 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1838                     (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1839                         mac->ops.setup_mac_link =
1840                                                 ixgbe_setup_mac_link_sfp_x550a;
1841                 else
1842                         mac->ops.setup_mac_link =
1843                                                 ixgbe_setup_mac_link_sfp_x550em;
1844                 break;
1845         case ixgbe_media_type_copper:
1846                 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T)
1847                         break;
1848                 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1849                         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
1850                             hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
1851                                 mac->ops.setup_link = ixgbe_setup_sgmii_fw;
1852                                 mac->ops.check_link =
1853                                                    ixgbe_check_mac_link_generic;
1854                         } else {
1855                                 mac->ops.setup_link =
1856                                                   ixgbe_setup_mac_link_t_X550em;
1857                         }
1858                 } else {
1859                         mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1860                         mac->ops.check_link = ixgbe_check_link_t_X550em;
1861                 }
1862                 break;
1863         case ixgbe_media_type_backplane:
1864                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1865                     hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1866 #ifdef PREBOOT_SUPPORT
1867                         mac->ops.setup_link = ixgbe_setup_sgmii_fw;
1868 #else
1869                         mac->ops.setup_link = ixgbe_setup_sgmii;
1870 #endif /* PREBOOT_SUPPORT */
1871                 break;
1872         default:
1873                 break;
1874         }
1875 }
1876
1877 /**
1878  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1879  *  @hw: pointer to hardware structure
1880  *  @speed: pointer to link speed
1881  *  @autoneg: true when autoneg or autotry is enabled
1882  */
1883 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1884                                        ixgbe_link_speed *speed,
1885                                        bool *autoneg)
1886 {
1887         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1888
1889
1890         if (hw->phy.type == ixgbe_phy_fw) {
1891                 *autoneg = true;
1892                 *speed = hw->phy.speeds_supported;
1893                 return 0;
1894         }
1895
1896         /* SFP */
1897         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1898
1899                 /* CS4227 SFP must not enable auto-negotiation */
1900                 *autoneg = false;
1901
1902                 /* Check if 1G SFP module. */
1903                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1904                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1905                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1906                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1907                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1908                         return IXGBE_SUCCESS;
1909                 }
1910
1911                 /* Link capabilities are based on SFP */
1912                 if (hw->phy.multispeed_fiber)
1913                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1914                                  IXGBE_LINK_SPEED_1GB_FULL;
1915                 else
1916                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1917         } else {
1918                 switch (hw->phy.type) {
1919                 case ixgbe_phy_ext_1g_t:
1920 #ifdef PREBOOT_SUPPORT
1921                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1922                         break;
1923 #endif /* PREBOOT_SUPPORT */
1924                 case ixgbe_phy_sgmii:
1925 #ifdef PREBOOT_SUPPORT
1926                         *speed = IXGBE_LINK_SPEED_1GB_FULL |
1927                                  IXGBE_LINK_SPEED_100_FULL |
1928                                  IXGBE_LINK_SPEED_10_FULL;
1929 #else
1930                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1931 #endif /* PREBOOT_SUPPORT */
1932                         break;
1933                 case ixgbe_phy_x550em_kr:
1934                         if (hw->mac.type == ixgbe_mac_X550EM_a) {
1935                                 /* check different backplane modes */
1936                                 if (hw->phy.nw_mng_if_sel &
1937                                            IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
1938                                         *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
1939                                         break;
1940                                 } else if (hw->device_id ==
1941                                                    IXGBE_DEV_ID_X550EM_A_KR_L) {
1942                                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1943                                         break;
1944                                 }
1945                         }
1946                         /* fall through */
1947                 default:
1948                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1949                                  IXGBE_LINK_SPEED_1GB_FULL;
1950                         break;
1951                 }
1952                 *autoneg = true;
1953         }
1954
1955         return IXGBE_SUCCESS;
1956 }
1957
1958 /**
1959  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1960  * @hw: pointer to hardware structure
1961  * @lsc: pointer to boolean flag which indicates whether external Base T
1962  *       PHY interrupt is lsc
1963  *
1964  * Determime if external Base T PHY interrupt cause is high temperature
1965  * failure alarm or link status change.
1966  *
1967  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1968  * failure alarm, else return PHY access status.
1969  */
1970 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1971 {
1972         u32 status;
1973         u16 reg;
1974
1975         *lsc = false;
1976
1977         /* Vendor alarm triggered */
1978         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1979                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1980                                       &reg);
1981
1982         if (status != IXGBE_SUCCESS ||
1983             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1984                 return status;
1985
1986         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1987         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1988                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1989                                       &reg);
1990
1991         if (status != IXGBE_SUCCESS ||
1992             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1993             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1994                 return status;
1995
1996         /* Global alarm triggered */
1997         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1998                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1999                                       &reg);
2000
2001         if (status != IXGBE_SUCCESS)
2002                 return status;
2003
2004         /* If high temperature failure, then return over temp error and exit */
2005         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
2006                 /* power down the PHY in case the PHY FW didn't already */
2007                 ixgbe_set_copper_phy_power(hw, false);
2008                 return IXGBE_ERR_OVERTEMP;
2009         } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
2010                 /*  device fault alarm triggered */
2011                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
2012                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2013                                           &reg);
2014
2015                 if (status != IXGBE_SUCCESS)
2016                         return status;
2017
2018                 /* if device fault was due to high temp alarm handle and exit */
2019                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
2020                         /* power down the PHY in case the PHY FW didn't */
2021                         ixgbe_set_copper_phy_power(hw, false);
2022                         return IXGBE_ERR_OVERTEMP;
2023                 }
2024         }
2025
2026         /* Vendor alarm 2 triggered */
2027         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2028                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2029
2030         if (status != IXGBE_SUCCESS ||
2031             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
2032                 return status;
2033
2034         /* link connect/disconnect event occurred */
2035         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
2036                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2037
2038         if (status != IXGBE_SUCCESS)
2039                 return status;
2040
2041         /* Indicate LSC */
2042         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2043                 *lsc = true;
2044
2045         return IXGBE_SUCCESS;
2046 }
2047
2048 /**
2049  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2050  * @hw: pointer to hardware structure
2051  *
2052  * Enable link status change and temperature failure alarm for the external
2053  * Base T PHY
2054  *
2055  * Returns PHY access status
2056  */
2057 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2058 {
2059         u32 status;
2060         u16 reg;
2061         bool lsc;
2062
2063         /* Clear interrupt flags */
2064         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2065
2066         /* Enable link status change alarm */
2067
2068         /* Enable the LASI interrupts on X552 devices to receive notifications
2069          * of the link configurations of the external PHY and correspondingly
2070          * support the configuration of the internal iXFI link, since iXFI does
2071          * not support auto-negotiation. This is not required for X553 devices
2072          * having KR support, which performs auto-negotiations and which is used
2073          * as the internal link to the external PHY. Hence adding a check here
2074          * to avoid enabling LASI interrupts for X553 devices.
2075          */
2076         if (hw->mac.type != ixgbe_mac_X550EM_a) {
2077                 status = hw->phy.ops.read_reg(hw,
2078                                         IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2079                                         IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2080
2081                 if (status != IXGBE_SUCCESS)
2082                         return status;
2083
2084                 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2085
2086                 status = hw->phy.ops.write_reg(hw,
2087                                         IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2088                                         IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
2089
2090                 if (status != IXGBE_SUCCESS)
2091                         return status;
2092         }
2093
2094         /* Enable high temperature failure and global fault alarms */
2095         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2096                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2097                                       &reg);
2098
2099         if (status != IXGBE_SUCCESS)
2100                 return status;
2101
2102         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2103                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2104
2105         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2106                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2107                                        reg);
2108
2109         if (status != IXGBE_SUCCESS)
2110                 return status;
2111
2112         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2113         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2114                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2115                                       &reg);
2116
2117         if (status != IXGBE_SUCCESS)
2118                 return status;
2119
2120         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2121                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2122
2123         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2124                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2125                                        reg);
2126
2127         if (status != IXGBE_SUCCESS)
2128                 return status;
2129
2130         /* Enable chip-wide vendor alarm */
2131         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2132                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2133                                       &reg);
2134
2135         if (status != IXGBE_SUCCESS)
2136                 return status;
2137
2138         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2139
2140         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2141                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2142                                        reg);
2143
2144         return status;
2145 }
2146
2147 /**
2148  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2149  *  @hw: pointer to hardware structure
2150  *  @speed: link speed
2151  *
2152  *  Configures the integrated KR PHY.
2153  **/
2154 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2155                                        ixgbe_link_speed speed)
2156 {
2157         s32 status;
2158         u32 reg_val;
2159
2160         status = hw->mac.ops.read_iosf_sb_reg(hw,
2161                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2162                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2163         if (status)
2164                 return status;
2165
2166         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2167         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2168                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2169
2170         /* Advertise 10G support. */
2171         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2172                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2173
2174         /* Advertise 1G support. */
2175         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2176                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2177
2178         status = hw->mac.ops.write_iosf_sb_reg(hw,
2179                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2180                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2181
2182         if (hw->mac.type == ixgbe_mac_X550EM_a) {
2183                 /* Set lane mode  to KR auto negotiation */
2184                 status = hw->mac.ops.read_iosf_sb_reg(hw,
2185                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2186                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2187
2188                 if (status)
2189                         return status;
2190
2191                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2192                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2193                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2194                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2195                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2196
2197                 status = hw->mac.ops.write_iosf_sb_reg(hw,
2198                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2199                                     IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2200         }
2201
2202         return ixgbe_restart_an_internal_phy_x550em(hw);
2203 }
2204
2205 /**
2206  * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs
2207  * @hw: pointer to hardware structure
2208  */
2209 static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw)
2210 {
2211         u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
2212         s32 rc;
2213
2214         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2215                 return IXGBE_SUCCESS;
2216
2217         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store);
2218         if (rc)
2219                 return rc;
2220         memset(store, 0, sizeof(store));
2221
2222         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store);
2223         if (rc)
2224                 return rc;
2225
2226         return ixgbe_setup_fw_link(hw);
2227 }
2228
2229 /**
2230  * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp
2231  * @hw: pointer to hardware structure
2232  */
2233 static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw)
2234 {
2235         u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
2236         s32 rc;
2237
2238         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store);
2239         if (rc)
2240                 return rc;
2241
2242         if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) {
2243                 ixgbe_shutdown_fw_phy(hw);
2244                 return IXGBE_ERR_OVERTEMP;
2245         }
2246         return IXGBE_SUCCESS;
2247 }
2248
2249 /**
2250  *  ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2251  *  @hw: pointer to hardware structure
2252  *
2253  *  Read NW_MNG_IF_SEL register and save field values, and check for valid field
2254  *  values.
2255  **/
2256 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2257 {
2258         /* Save NW management interface connected on board. This is used
2259          * to determine internal PHY mode.
2260          */
2261         hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2262
2263         /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2264          * PHY address. This register field was has only been used for X552.
2265          */
2266         if (hw->mac.type == ixgbe_mac_X550EM_a &&
2267             hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2268                 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2269                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2270                                IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2271         }
2272
2273         return IXGBE_SUCCESS;
2274 }
2275
2276 /**
2277  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2278  *  @hw: pointer to hardware structure
2279  *
2280  *  Initialize any function pointers that were not able to be
2281  *  set during init_shared_code because the PHY/SFP type was
2282  *  not known.  Perform the SFP init if necessary.
2283  */
2284 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2285 {
2286         struct ixgbe_phy_info *phy = &hw->phy;
2287         s32 ret_val;
2288
2289         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2290
2291         hw->mac.ops.set_lan_id(hw);
2292         ixgbe_read_mng_if_sel_x550em(hw);
2293
2294         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2295                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2296                 ixgbe_setup_mux_ctl(hw);
2297                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2298         }
2299
2300         switch (hw->device_id) {
2301         case IXGBE_DEV_ID_X550EM_A_1G_T:
2302         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2303                 phy->ops.read_reg_mdi = NULL;
2304                 phy->ops.write_reg_mdi = NULL;
2305                 hw->phy.ops.read_reg = NULL;
2306                 hw->phy.ops.write_reg = NULL;
2307                 phy->ops.check_overtemp = ixgbe_check_overtemp_fw;
2308                 if (hw->bus.lan_id)
2309                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2310                 else
2311                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2312
2313                 break;
2314         case IXGBE_DEV_ID_X550EM_A_10G_T:
2315         case IXGBE_DEV_ID_X550EM_A_SFP:
2316                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2317                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2318                 if (hw->bus.lan_id)
2319                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2320                 else
2321                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2322                 break;
2323         case IXGBE_DEV_ID_X550EM_X_SFP:
2324                 /* set up for CS4227 usage */
2325                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2326                 break;
2327         case IXGBE_DEV_ID_X550EM_X_1G_T:
2328                 phy->ops.read_reg_mdi = NULL;
2329                 phy->ops.write_reg_mdi = NULL;
2330         default:
2331                 break;
2332         }
2333
2334         /* Identify the PHY or SFP module */
2335         ret_val = phy->ops.identify(hw);
2336         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED ||
2337             ret_val == IXGBE_ERR_PHY_ADDR_INVALID)
2338                 return ret_val;
2339
2340         /* Setup function pointers based on detected hardware */
2341         ixgbe_init_mac_link_ops_X550em(hw);
2342         if (phy->sfp_type != ixgbe_sfp_type_unknown)
2343                 phy->ops.reset = NULL;
2344
2345         /* Set functions pointers based on phy type */
2346         switch (hw->phy.type) {
2347         case ixgbe_phy_x550em_kx4:
2348                 phy->ops.setup_link = NULL;
2349                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2350                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2351                 break;
2352         case ixgbe_phy_x550em_kr:
2353                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2354                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2355                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2356                 break;
2357         case ixgbe_phy_ext_1g_t:
2358                 /* link is managed by FW */
2359                 phy->ops.setup_link = NULL;
2360                 phy->ops.reset = NULL;
2361                 break;
2362         case ixgbe_phy_x550em_xfi:
2363                 /* link is managed by HW */
2364                 phy->ops.setup_link = NULL;
2365                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2366                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2367                 break;
2368         case ixgbe_phy_x550em_ext_t:
2369                 /* If internal link mode is XFI, then setup iXFI internal link,
2370                  * else setup KR now.
2371                  */
2372                 phy->ops.setup_internal_link =
2373                                               ixgbe_setup_internal_phy_t_x550em;
2374
2375                 /* setup SW LPLU only for first revision of X550EM_x */
2376                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2377                     !(IXGBE_FUSES0_REV_MASK &
2378                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2379                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2380
2381                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2382                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2383                 break;
2384         case ixgbe_phy_sgmii:
2385                 phy->ops.setup_link = NULL;
2386                 break;
2387         case ixgbe_phy_fw:
2388                 phy->ops.setup_link = ixgbe_setup_fw_link;
2389                 phy->ops.reset = ixgbe_reset_phy_fw;
2390                 break;
2391         default:
2392                 break;
2393         }
2394         return ret_val;
2395 }
2396
2397 /**
2398  * ixgbe_set_mdio_speed - Set MDIO clock speed
2399  *  @hw: pointer to hardware structure
2400  */
2401 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2402 {
2403         u32 hlreg0;
2404
2405         switch (hw->device_id) {
2406         case IXGBE_DEV_ID_X550EM_X_10G_T:
2407         case IXGBE_DEV_ID_X550EM_A_SGMII:
2408         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2409         case IXGBE_DEV_ID_X550EM_A_10G_T:
2410         case IXGBE_DEV_ID_X550EM_A_SFP:
2411         case IXGBE_DEV_ID_X550EM_A_QSFP:
2412                 /* Config MDIO clock speed before the first MDIO PHY access */
2413                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2414                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2415                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2416                 break;
2417         case IXGBE_DEV_ID_X550EM_A_1G_T:
2418         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2419                 /* Select fast MDIO clock speed for these devices */
2420                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2421                 hlreg0 |= IXGBE_HLREG0_MDCSPD;
2422                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2423                 break;
2424         default:
2425                 break;
2426         }
2427 }
2428
2429 /**
2430  *  ixgbe_reset_hw_X550em - Perform hardware reset
2431  *  @hw: pointer to hardware structure
2432  *
2433  *  Resets the hardware by resetting the transmit and receive units, masks
2434  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2435  *  reset.
2436  */
2437 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2438 {
2439         ixgbe_link_speed link_speed;
2440         s32 status;
2441         u32 ctrl = 0;
2442         u32 i;
2443         bool link_up = false;
2444         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2445
2446         DEBUGFUNC("ixgbe_reset_hw_X550em");
2447
2448         /* Call adapter stop to disable Tx/Rx and clear interrupts */
2449         status = hw->mac.ops.stop_adapter(hw);
2450         if (status != IXGBE_SUCCESS) {
2451                 DEBUGOUT1("Failed to stop adapter, STATUS = %d\n", status);
2452                 return status;
2453         }
2454         /* flush pending Tx transactions */
2455         ixgbe_clear_tx_pending(hw);
2456
2457         ixgbe_set_mdio_speed(hw);
2458
2459         /* PHY ops must be identified and initialized prior to reset */
2460         status = hw->phy.ops.init(hw);
2461
2462         if (status)
2463                 DEBUGOUT1("Failed to initialize PHY ops, STATUS = %d\n",
2464                           status);
2465
2466         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED ||
2467             status == IXGBE_ERR_PHY_ADDR_INVALID) {
2468                 DEBUGOUT("Returning from reset HW due to PHY init failure\n");
2469                 return status;
2470         }
2471
2472         /* start the external PHY */
2473         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2474                 status = ixgbe_init_ext_t_x550em(hw);
2475                 if (status) {
2476                         DEBUGOUT1("Failed to start the external PHY, STATUS = %d\n",
2477                                   status);
2478                         return status;
2479                 }
2480         }
2481
2482         /* Setup SFP module if there is one present. */
2483         if (hw->phy.sfp_setup_needed) {
2484                 status = hw->mac.ops.setup_sfp(hw);
2485                 hw->phy.sfp_setup_needed = false;
2486         }
2487
2488         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2489                 return status;
2490
2491         /* Reset PHY */
2492         if (!hw->phy.reset_disable && hw->phy.ops.reset) {
2493                 if (hw->phy.ops.reset(hw) == IXGBE_ERR_OVERTEMP)
2494                         return IXGBE_ERR_OVERTEMP;
2495         }
2496
2497 mac_reset_top:
2498         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2499          * If link reset is used when link is up, it might reset the PHY when
2500          * mng is using it.  If link is down or the flag to force full link
2501          * reset is set, then perform link reset.
2502          */
2503         ctrl = IXGBE_CTRL_LNK_RST;
2504         if (!hw->force_full_reset) {
2505                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2506                 if (link_up)
2507                         ctrl = IXGBE_CTRL_RST;
2508         }
2509
2510         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
2511         if (status != IXGBE_SUCCESS) {
2512                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
2513                         "semaphore failed with %d", status);
2514                 return IXGBE_ERR_SWFW_SYNC;
2515         }
2516         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2517         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2518         IXGBE_WRITE_FLUSH(hw);
2519         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2520
2521         /* Poll for reset bit to self-clear meaning reset is complete */
2522         for (i = 0; i < 10; i++) {
2523                 usec_delay(1);
2524                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2525                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2526                         break;
2527         }
2528
2529         if (ctrl & IXGBE_CTRL_RST_MASK) {
2530                 status = IXGBE_ERR_RESET_FAILED;
2531                 DEBUGOUT("Reset polling failed to complete.\n");
2532         }
2533
2534         msec_delay(50);
2535
2536         /* Double resets are required for recovery from certain error
2537          * conditions.  Between resets, it is necessary to stall to
2538          * allow time for any pending HW events to complete.
2539          */
2540         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2541                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2542                 goto mac_reset_top;
2543         }
2544
2545         /* Store the permanent mac address */
2546         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2547
2548         /* Store MAC address from RAR0, clear receive address registers, and
2549          * clear the multicast table.  Also reset num_rar_entries to 128,
2550          * since we modify this value when programming the SAN MAC address.
2551          */
2552         hw->mac.num_rar_entries = 128;
2553         hw->mac.ops.init_rx_addrs(hw);
2554
2555         ixgbe_set_mdio_speed(hw);
2556
2557         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2558                 ixgbe_setup_mux_ctl(hw);
2559
2560         if (status != IXGBE_SUCCESS)
2561                 DEBUGOUT1("Reset HW failed, STATUS = %d\n", status);
2562
2563         return status;
2564 }
2565
2566 /**
2567  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2568  * @hw: pointer to hardware structure
2569  */
2570 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2571 {
2572         u32 status;
2573         u16 reg;
2574
2575         status = hw->phy.ops.read_reg(hw,
2576                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2577                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2578                                       &reg);
2579
2580         if (status != IXGBE_SUCCESS)
2581                 return status;
2582
2583         /* If PHY FW reset completed bit is set then this is the first
2584          * SW instance after a power on so the PHY FW must be un-stalled.
2585          */
2586         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2587                 status = hw->phy.ops.read_reg(hw,
2588                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2589                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2590                                         &reg);
2591
2592                 if (status != IXGBE_SUCCESS)
2593                         return status;
2594
2595                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2596
2597                 status = hw->phy.ops.write_reg(hw,
2598                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2599                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2600                                         reg);
2601
2602                 if (status != IXGBE_SUCCESS)
2603                         return status;
2604         }
2605
2606         return status;
2607 }
2608
2609 /**
2610  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
2611  *  @hw: pointer to hardware structure
2612  **/
2613 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2614 {
2615         /* leave link alone for 2.5G */
2616         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL)
2617                 return IXGBE_SUCCESS;
2618
2619         if (ixgbe_check_reset_blocked(hw))
2620                 return 0;
2621
2622         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2623 }
2624
2625 /**
2626  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2627  *  @hw: pointer to hardware structure
2628  *
2629  *  Configure the external PHY and the integrated KR PHY for SFP support.
2630  **/
2631 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2632                                     ixgbe_link_speed speed,
2633                                     bool autoneg_wait_to_complete)
2634 {
2635         s32 ret_val;
2636         u16 reg_slice, reg_val;
2637         bool setup_linear = false;
2638         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2639
2640         /* Check if SFP module is supported and linear */
2641         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2642
2643         /* If no SFP module present, then return success. Return success since
2644          * there is no reason to configure CS4227 and SFP not present error is
2645          * not excepted in the setup MAC link flow.
2646          */
2647         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2648                 return IXGBE_SUCCESS;
2649
2650         if (ret_val != IXGBE_SUCCESS)
2651                 return ret_val;
2652
2653         /* Configure internal PHY for KR/KX. */
2654         ixgbe_setup_kr_speed_x550em(hw, speed);
2655
2656         /* Configure CS4227 LINE side to proper mode. */
2657         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2658                     (hw->bus.lan_id << 12);
2659         if (setup_linear)
2660                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2661         else
2662                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2663         ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2664                                           reg_val);
2665         return ret_val;
2666 }
2667
2668 /**
2669  *  ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
2670  *  @hw: pointer to hardware structure
2671  *  @speed: the link speed to force
2672  *
2673  *  Configures the integrated PHY for native SFI mode. Used to connect the
2674  *  internal PHY directly to an SFP cage, without autonegotiation.
2675  **/
2676 STATIC s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2677 {
2678         struct ixgbe_mac_info *mac = &hw->mac;
2679         s32 status;
2680         u32 reg_val;
2681
2682         /* Disable all AN and force speed to 10G Serial. */
2683         status = mac->ops.read_iosf_sb_reg(hw,
2684                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2685                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2686         if (status != IXGBE_SUCCESS)
2687                 return status;
2688
2689         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2690         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2691         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2692         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2693
2694         /* Select forced link speed for internal PHY. */
2695         switch (*speed) {
2696         case IXGBE_LINK_SPEED_10GB_FULL:
2697                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
2698                 break;
2699         case IXGBE_LINK_SPEED_1GB_FULL:
2700                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2701                 break;
2702         default:
2703                 /* Other link speeds are not supported by internal PHY. */
2704                 return IXGBE_ERR_LINK_SETUP;
2705         }
2706
2707         status = mac->ops.write_iosf_sb_reg(hw,
2708                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2709                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2710
2711         /* Toggle port SW reset by AN reset. */
2712         status = ixgbe_restart_an_internal_phy_x550em(hw);
2713
2714         return status;
2715 }
2716
2717 /**
2718  *  ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2719  *  @hw: pointer to hardware structure
2720  *
2721  *  Configure the integrated PHY for SFP support.
2722  **/
2723 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2724                                     ixgbe_link_speed speed,
2725                                     bool autoneg_wait_to_complete)
2726 {
2727         s32 ret_val;
2728         u16 reg_phy_ext;
2729         bool setup_linear = false;
2730         u32 reg_slice, reg_phy_int, slice_offset;
2731
2732         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2733
2734         /* Check if SFP module is supported and linear */
2735         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2736
2737         /* If no SFP module present, then return success. Return success since
2738          * SFP not present error is not excepted in the setup MAC link flow.
2739          */
2740         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2741                 return IXGBE_SUCCESS;
2742
2743         if (ret_val != IXGBE_SUCCESS)
2744                 return ret_val;
2745
2746         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2747                 /* Configure internal PHY for native SFI based on module type */
2748                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2749                                    IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2750                                    IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_phy_int);
2751
2752                 if (ret_val != IXGBE_SUCCESS)
2753                         return ret_val;
2754
2755                 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
2756                 if (!setup_linear)
2757                         reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
2758
2759                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2760                                    IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2761                                    IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2762
2763                 if (ret_val != IXGBE_SUCCESS)
2764                         return ret_val;
2765
2766                 /* Setup SFI internal link. */
2767                 ret_val = ixgbe_setup_sfi_x550a(hw, &speed);
2768         } else {
2769                 /* Configure internal PHY for KR/KX. */
2770                 ixgbe_setup_kr_speed_x550em(hw, speed);
2771
2772                 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2773                         /* Find Address */
2774                         DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2775                         return IXGBE_ERR_PHY_ADDR_INVALID;
2776                 }
2777
2778                 /* Get external PHY SKU id */
2779                 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,
2780                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2781
2782                 if (ret_val != IXGBE_SUCCESS)
2783                         return ret_val;
2784
2785                 /* When configuring quad port CS4223, the MAC instance is part
2786                  * of the slice offset.
2787                  */
2788                 if (reg_phy_ext == IXGBE_CS4223_SKU_ID)
2789                         slice_offset = (hw->bus.lan_id +
2790                                         (hw->bus.instance_id << 1)) << 12;
2791                 else
2792                         slice_offset = hw->bus.lan_id << 12;
2793
2794                 /* Configure CS4227/CS4223 LINE side to proper mode. */
2795                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2796
2797                 ret_val = hw->phy.ops.read_reg(hw, reg_slice,
2798                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2799
2800                 if (ret_val != IXGBE_SUCCESS)
2801                         return ret_val;
2802
2803                 reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) |
2804                                  (IXGBE_CS4227_EDC_MODE_SR << 1));
2805
2806                 if (setup_linear)
2807                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2808                 else
2809                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2810                 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2811                                          IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2812
2813                 /* Flush previous write with a read */
2814                 ret_val = hw->phy.ops.read_reg(hw, reg_slice,
2815                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2816         }
2817         return ret_val;
2818 }
2819
2820 /**
2821  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2822  *  @hw: pointer to hardware structure
2823  *
2824  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2825  **/
2826 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2827 {
2828         struct ixgbe_mac_info *mac = &hw->mac;
2829         s32 status;
2830         u32 reg_val;
2831
2832         /* Disable training protocol FSM. */
2833         status = mac->ops.read_iosf_sb_reg(hw,
2834                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2835                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2836         if (status != IXGBE_SUCCESS)
2837                 return status;
2838         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2839         status = mac->ops.write_iosf_sb_reg(hw,
2840                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2841                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2842         if (status != IXGBE_SUCCESS)
2843                 return status;
2844
2845         /* Disable Flex from training TXFFE. */
2846         status = mac->ops.read_iosf_sb_reg(hw,
2847                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2848                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2849         if (status != IXGBE_SUCCESS)
2850                 return status;
2851         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2852         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2853         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2854         status = mac->ops.write_iosf_sb_reg(hw,
2855                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2856                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2857         if (status != IXGBE_SUCCESS)
2858                 return status;
2859         status = mac->ops.read_iosf_sb_reg(hw,
2860                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2861                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2862         if (status != IXGBE_SUCCESS)
2863                 return status;
2864         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2865         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2866         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2867         status = mac->ops.write_iosf_sb_reg(hw,
2868                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2869                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2870         if (status != IXGBE_SUCCESS)
2871                 return status;
2872
2873         /* Enable override for coefficients. */
2874         status = mac->ops.read_iosf_sb_reg(hw,
2875                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2876                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2877         if (status != IXGBE_SUCCESS)
2878                 return status;
2879         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2880         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2881         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2882         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2883         status = mac->ops.write_iosf_sb_reg(hw,
2884                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2885                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2886         return status;
2887 }
2888
2889 /**
2890  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2891  *  @hw: pointer to hardware structure
2892  *  @speed: the link speed to force
2893  *
2894  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
2895  *  internal and external PHY at a specific speed, without autonegotiation.
2896  **/
2897 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2898 {
2899         struct ixgbe_mac_info *mac = &hw->mac;
2900         s32 status;
2901         u32 reg_val;
2902
2903         /* iXFI is only supported with X552 */
2904         if (mac->type != ixgbe_mac_X550EM_x)
2905                 return IXGBE_ERR_LINK_SETUP;
2906
2907         /* Disable AN and force speed to 10G Serial. */
2908         status = mac->ops.read_iosf_sb_reg(hw,
2909                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2910                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2911         if (status != IXGBE_SUCCESS)
2912                 return status;
2913
2914         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2915         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2916
2917         /* Select forced link speed for internal PHY. */
2918         switch (*speed) {
2919         case IXGBE_LINK_SPEED_10GB_FULL:
2920                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2921                 break;
2922         case IXGBE_LINK_SPEED_1GB_FULL:
2923                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2924                 break;
2925         default:
2926                 /* Other link speeds are not supported by internal KR PHY. */
2927                 return IXGBE_ERR_LINK_SETUP;
2928         }
2929
2930         status = mac->ops.write_iosf_sb_reg(hw,
2931                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2932                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2933         if (status != IXGBE_SUCCESS)
2934                 return status;
2935
2936         /* Additional configuration needed for x550em_x */
2937         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2938                 status = ixgbe_setup_ixfi_x550em_x(hw);
2939                 if (status != IXGBE_SUCCESS)
2940                         return status;
2941         }
2942
2943         /* Toggle port SW reset by AN reset. */
2944         status = ixgbe_restart_an_internal_phy_x550em(hw);
2945
2946         return status;
2947 }
2948
2949 /**
2950  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2951  * @hw: address of hardware structure
2952  * @link_up: address of boolean to indicate link status
2953  *
2954  * Returns error code if unable to get link status.
2955  */
2956 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2957 {
2958         u32 ret;
2959         u16 autoneg_status;
2960
2961         *link_up = false;
2962
2963         /* read this twice back to back to indicate current status */
2964         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2965                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2966                                    &autoneg_status);
2967         if (ret != IXGBE_SUCCESS)
2968                 return ret;
2969
2970         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2971                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2972                                    &autoneg_status);
2973         if (ret != IXGBE_SUCCESS)
2974                 return ret;
2975
2976         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2977
2978         return IXGBE_SUCCESS;
2979 }
2980
2981 /**
2982  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2983  * @hw: point to hardware structure
2984  *
2985  * Configures the link between the integrated KR PHY and the external X557 PHY
2986  * The driver will call this function when it gets a link status change
2987  * interrupt from the X557 PHY. This function configures the link speed
2988  * between the PHYs to match the link speed of the BASE-T link.
2989  *
2990  * A return of a non-zero value indicates an error, and the base driver should
2991  * not report link up.
2992  */
2993 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2994 {
2995         ixgbe_link_speed force_speed;
2996         bool link_up;
2997         u32 status;
2998         u16 speed;
2999
3000         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3001                 return IXGBE_ERR_CONFIG;
3002
3003         if (hw->mac.type == ixgbe_mac_X550EM_x &&
3004             !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3005                 /* If link is down, there is no setup necessary so return  */
3006                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3007                 if (status != IXGBE_SUCCESS)
3008                         return status;
3009
3010                 if (!link_up)
3011                         return IXGBE_SUCCESS;
3012
3013                 status = hw->phy.ops.read_reg(hw,
3014                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3015                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3016                                               &speed);
3017                 if (status != IXGBE_SUCCESS)
3018                         return status;
3019
3020                 /* If link is still down - no setup is required so return */
3021                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3022                 if (status != IXGBE_SUCCESS)
3023                         return status;
3024                 if (!link_up)
3025                         return IXGBE_SUCCESS;
3026
3027                 /* clear everything but the speed and duplex bits */
3028                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
3029
3030                 switch (speed) {
3031                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
3032                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3033                         break;
3034                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
3035                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3036                         break;
3037                 default:
3038                         /* Internal PHY does not support anything else */
3039                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
3040                 }
3041
3042                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
3043         } else {
3044                 speed = IXGBE_LINK_SPEED_10GB_FULL |
3045                         IXGBE_LINK_SPEED_1GB_FULL;
3046                 return ixgbe_setup_kr_speed_x550em(hw, speed);
3047         }
3048 }
3049
3050 /**
3051  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
3052  *  @hw: pointer to hardware structure
3053  *
3054  *  Configures the integrated KR PHY to use internal loopback mode.
3055  **/
3056 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
3057 {
3058         s32 status;
3059         u32 reg_val;
3060
3061         /* Disable AN and force speed to 10G Serial. */
3062         status = hw->mac.ops.read_iosf_sb_reg(hw,
3063                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3064                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3065         if (status != IXGBE_SUCCESS)
3066                 return status;
3067         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3068         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3069         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3070         status = hw->mac.ops.write_iosf_sb_reg(hw,
3071                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3072                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3073         if (status != IXGBE_SUCCESS)
3074                 return status;
3075
3076         /* Set near-end loopback clocks. */
3077         status = hw->mac.ops.read_iosf_sb_reg(hw,
3078                                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3079                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3080         if (status != IXGBE_SUCCESS)
3081                 return status;
3082         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3083         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3084         status = hw->mac.ops.write_iosf_sb_reg(hw,
3085                                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3086                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3087         if (status != IXGBE_SUCCESS)
3088                 return status;
3089
3090         /* Set loopback enable. */
3091         status = hw->mac.ops.read_iosf_sb_reg(hw,
3092                                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3093                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3094         if (status != IXGBE_SUCCESS)
3095                 return status;
3096         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3097         status = hw->mac.ops.write_iosf_sb_reg(hw,
3098                                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3099                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3100         if (status != IXGBE_SUCCESS)
3101                 return status;
3102
3103         /* Training bypass. */
3104         status = hw->mac.ops.read_iosf_sb_reg(hw,
3105                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3106                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3107         if (status != IXGBE_SUCCESS)
3108                 return status;
3109         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3110         status = hw->mac.ops.write_iosf_sb_reg(hw,
3111                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3112                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3113
3114         return status;
3115 }
3116
3117 /**
3118  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3119  *  assuming that the semaphore is already obtained.
3120  *  @hw: pointer to hardware structure
3121  *  @offset: offset of  word in the EEPROM to read
3122  *  @data: word read from the EEPROM
3123  *
3124  *  Reads a 16 bit word from the EEPROM using the hostif.
3125  **/
3126 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
3127 {
3128         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3129         struct ixgbe_hic_read_shadow_ram buffer;
3130         s32 status;
3131
3132         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3133         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3134         buffer.hdr.req.buf_lenh = 0;
3135         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3136         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3137
3138         /* convert offset from words to bytes */
3139         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3140         /* one word */
3141         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3142         buffer.pad2 = 0;
3143         buffer.pad3 = 0;
3144
3145         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3146         if (status)
3147                 return status;
3148
3149         status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3150                                     IXGBE_HI_COMMAND_TIMEOUT);
3151         if (!status) {
3152                 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3153                                                   FW_NVM_DATA_OFFSET);
3154         }
3155
3156         hw->mac.ops.release_swfw_sync(hw, mask);
3157         return status;
3158 }
3159
3160 /**
3161  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3162  *  @hw: pointer to hardware structure
3163  *  @offset: offset of  word in the EEPROM to read
3164  *  @words: number of words
3165  *  @data: word(s) read from the EEPROM
3166  *
3167  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
3168  **/
3169 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3170                                      u16 offset, u16 words, u16 *data)
3171 {
3172         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3173         struct ixgbe_hic_read_shadow_ram buffer;
3174         u32 current_word = 0;
3175         u16 words_to_read;
3176         s32 status;
3177         u32 i;
3178
3179         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3180
3181         /* Take semaphore for the entire operation. */
3182         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3183         if (status) {
3184                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3185                 return status;
3186         }
3187
3188         while (words) {
3189                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3190                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3191                 else
3192                         words_to_read = words;
3193
3194                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3195                 buffer.hdr.req.buf_lenh = 0;
3196                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3197                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3198
3199                 /* convert offset from words to bytes */
3200                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3201                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3202                 buffer.pad2 = 0;
3203                 buffer.pad3 = 0;
3204
3205                 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3206                                             IXGBE_HI_COMMAND_TIMEOUT);
3207
3208                 if (status) {
3209                         DEBUGOUT("Host interface command failed\n");
3210                         goto out;
3211                 }
3212
3213                 for (i = 0; i < words_to_read; i++) {
3214                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3215                                   2 * i;
3216                         u32 value = IXGBE_READ_REG(hw, reg);
3217
3218                         data[current_word] = (u16)(value & 0xffff);
3219                         current_word++;
3220                         i++;
3221                         if (i < words_to_read) {
3222                                 value >>= 16;
3223                                 data[current_word] = (u16)(value & 0xffff);
3224                                 current_word++;
3225                         }
3226                 }
3227                 words -= words_to_read;
3228         }
3229
3230 out:
3231         hw->mac.ops.release_swfw_sync(hw, mask);
3232         return status;
3233 }
3234
3235 /**
3236  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3237  *  @hw: pointer to hardware structure
3238  *  @offset: offset of  word in the EEPROM to write
3239  *  @data: word write to the EEPROM
3240  *
3241  *  Write a 16 bit word to the EEPROM using the hostif.
3242  **/
3243 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3244                                     u16 data)
3245 {
3246         s32 status;
3247         struct ixgbe_hic_write_shadow_ram buffer;
3248
3249         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3250
3251         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3252         buffer.hdr.req.buf_lenh = 0;
3253         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3254         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3255
3256          /* one word */
3257         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3258         buffer.data = data;
3259         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3260
3261         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3262                                               sizeof(buffer),
3263                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3264
3265         return status;
3266 }
3267
3268 /**
3269  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3270  *  @hw: pointer to hardware structure
3271  *  @offset: offset of  word in the EEPROM to write
3272  *  @data: word write to the EEPROM
3273  *
3274  *  Write a 16 bit word to the EEPROM using the hostif.
3275  **/
3276 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3277                                u16 data)
3278 {
3279         s32 status = IXGBE_SUCCESS;
3280
3281         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3282
3283         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3284             IXGBE_SUCCESS) {
3285                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3286                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3287         } else {
3288                 DEBUGOUT("write ee hostif failed to get semaphore");
3289                 status = IXGBE_ERR_SWFW_SYNC;
3290         }
3291
3292         return status;
3293 }
3294
3295 /**
3296  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3297  *  @hw: pointer to hardware structure
3298  *  @offset: offset of  word in the EEPROM to write
3299  *  @words: number of words
3300  *  @data: word(s) write to the EEPROM
3301  *
3302  *  Write a 16 bit word(s) to the EEPROM using the hostif.
3303  **/
3304 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3305                                       u16 offset, u16 words, u16 *data)
3306 {
3307         s32 status = IXGBE_SUCCESS;
3308         u32 i = 0;
3309
3310         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3311
3312         /* Take semaphore for the entire operation. */
3313         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3314         if (status != IXGBE_SUCCESS) {
3315                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3316                 goto out;
3317         }
3318
3319         for (i = 0; i < words; i++) {
3320                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3321                                                          data[i]);
3322
3323                 if (status != IXGBE_SUCCESS) {
3324                         DEBUGOUT("Eeprom buffered write failed\n");
3325                         break;
3326                 }
3327         }
3328
3329         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3330 out:
3331
3332         return status;
3333 }
3334
3335 /**
3336  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3337  * @hw: pointer to hardware structure
3338  * @ptr: pointer offset in eeprom
3339  * @size: size of section pointed by ptr, if 0 first word will be used as size
3340  * @csum: address of checksum to update
3341  *
3342  * Returns error status for any failure
3343  */
3344 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3345                                    u16 size, u16 *csum, u16 *buffer,
3346                                    u32 buffer_size)
3347 {
3348         u16 buf[256];
3349         s32 status;
3350         u16 length, bufsz, i, start;
3351         u16 *local_buffer;
3352
3353         bufsz = sizeof(buf) / sizeof(buf[0]);
3354
3355         /* Read a chunk at the pointer location */
3356         if (!buffer) {
3357                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3358                 if (status) {
3359                         DEBUGOUT("Failed to read EEPROM image\n");
3360                         return status;
3361                 }
3362                 local_buffer = buf;
3363         } else {
3364                 if (buffer_size < ptr)
3365                         return  IXGBE_ERR_PARAM;
3366                 local_buffer = &buffer[ptr];
3367         }
3368
3369         if (size) {
3370                 start = 0;
3371                 length = size;
3372         } else {
3373                 start = 1;
3374                 length = local_buffer[0];
3375
3376                 /* Skip pointer section if length is invalid. */
3377                 if (length == 0xFFFF || length == 0 ||
3378                     (ptr + length) >= hw->eeprom.word_size)
3379                         return IXGBE_SUCCESS;
3380         }
3381
3382         if (buffer && ((u32)start + (u32)length > buffer_size))
3383                 return IXGBE_ERR_PARAM;
3384
3385         for (i = start; length; i++, length--) {
3386                 if (i == bufsz && !buffer) {
3387                         ptr += bufsz;
3388                         i = 0;
3389                         if (length < bufsz)
3390                                 bufsz = length;
3391
3392                         /* Read a chunk at the pointer location */
3393                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3394                                                                   bufsz, buf);
3395                         if (status) {
3396                                 DEBUGOUT("Failed to read EEPROM image\n");
3397                                 return status;
3398                         }
3399                 }
3400                 *csum += local_buffer[i];
3401         }
3402         return IXGBE_SUCCESS;
3403 }
3404
3405 /**
3406  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3407  *  @hw: pointer to hardware structure
3408  *  @buffer: pointer to buffer containing calculated checksum
3409  *  @buffer_size: size of buffer
3410  *
3411  *  Returns a negative error code on error, or the 16-bit checksum
3412  **/
3413 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3414 {
3415         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3416         u16 *local_buffer;
3417         s32 status;
3418         u16 checksum = 0;
3419         u16 pointer, i, size;
3420
3421         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3422
3423         hw->eeprom.ops.init_params(hw);
3424
3425         if (!buffer) {
3426                 /* Read pointer area */
3427                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3428                                                      IXGBE_EEPROM_LAST_WORD + 1,
3429                                                      eeprom_ptrs);
3430                 if (status) {
3431                         DEBUGOUT("Failed to read EEPROM image\n");
3432                         return status;
3433                 }
3434                 local_buffer = eeprom_ptrs;
3435         } else {
3436                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3437                         return IXGBE_ERR_PARAM;
3438                 local_buffer = buffer;
3439         }
3440
3441         /*
3442          * For X550 hardware include 0x0-0x41 in the checksum, skip the
3443          * checksum word itself
3444          */
3445         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3446                 if (i != IXGBE_EEPROM_CHECKSUM)
3447                         checksum += local_buffer[i];
3448
3449         /*
3450          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
3451          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3452          */
3453         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3454                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3455                         continue;
3456
3457                 pointer = local_buffer[i];
3458
3459                 /* Skip pointer section if the pointer is invalid. */
3460                 if (pointer == 0xFFFF || pointer == 0 ||
3461                     pointer >= hw->eeprom.word_size)
3462                         continue;
3463
3464                 switch (i) {
3465                 case IXGBE_PCIE_GENERAL_PTR:
3466                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3467                         break;
3468                 case IXGBE_PCIE_CONFIG0_PTR:
3469                 case IXGBE_PCIE_CONFIG1_PTR:
3470                         size = IXGBE_PCIE_CONFIG_SIZE;
3471                         break;
3472                 default:
3473                         size = 0;
3474                         break;
3475                 }
3476
3477                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3478                                                 buffer, buffer_size);
3479                 if (status)
3480                         return status;
3481         }
3482
3483         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3484
3485         return (s32)checksum;
3486 }
3487
3488 /**
3489  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3490  *  @hw: pointer to hardware structure
3491  *
3492  *  Returns a negative error code on error, or the 16-bit checksum
3493  **/
3494 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3495 {
3496         return ixgbe_calc_checksum_X550(hw, NULL, 0);
3497 }
3498
3499 /**
3500  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3501  *  @hw: pointer to hardware structure
3502  *  @checksum_val: calculated checksum
3503  *
3504  *  Performs checksum calculation and validates the EEPROM checksum.  If the
3505  *  caller does not need checksum_val, the value can be NULL.
3506  **/
3507 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3508 {
3509         s32 status;
3510         u16 checksum;
3511         u16 read_checksum = 0;
3512
3513         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3514
3515         /* Read the first word from the EEPROM. If this times out or fails, do
3516          * not continue or we could be in for a very long wait while every
3517          * EEPROM read fails
3518          */
3519         status = hw->eeprom.ops.read(hw, 0, &checksum);
3520         if (status) {
3521                 DEBUGOUT("EEPROM read failed\n");
3522                 return status;
3523         }
3524
3525         status = hw->eeprom.ops.calc_checksum(hw);
3526         if (status < 0)
3527                 return status;
3528
3529         checksum = (u16)(status & 0xffff);
3530
3531         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3532                                            &read_checksum);
3533         if (status)
3534                 return status;
3535
3536         /* Verify read checksum from EEPROM is the same as
3537          * calculated checksum
3538          */
3539         if (read_checksum != checksum) {
3540                 status = IXGBE_ERR_EEPROM_CHECKSUM;
3541                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3542                              "Invalid EEPROM checksum");
3543         }
3544
3545         /* If the user cares, return the calculated checksum */
3546         if (checksum_val)
3547                 *checksum_val = checksum;
3548
3549         return status;
3550 }
3551
3552 /**
3553  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3554  * @hw: pointer to hardware structure
3555  *
3556  * After writing EEPROM to shadow RAM using EEWR register, software calculates
3557  * checksum and updates the EEPROM and instructs the hardware to update
3558  * the flash.
3559  **/
3560 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3561 {
3562         s32 status;
3563         u16 checksum = 0;
3564
3565         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3566
3567         /* Read the first word from the EEPROM. If this times out or fails, do
3568          * not continue or we could be in for a very long wait while every
3569          * EEPROM read fails
3570          */
3571         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3572         if (status) {
3573                 DEBUGOUT("EEPROM read failed\n");
3574                 return status;
3575         }
3576
3577         status = ixgbe_calc_eeprom_checksum_X550(hw);
3578         if (status < 0)
3579                 return status;
3580
3581         checksum = (u16)(status & 0xffff);
3582
3583         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3584                                             checksum);
3585         if (status)
3586                 return status;
3587
3588         status = ixgbe_update_flash_X550(hw);
3589
3590         return status;
3591 }
3592
3593 /**
3594  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3595  *  @hw: pointer to hardware structure
3596  *
3597  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3598  **/
3599 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3600 {
3601         s32 status = IXGBE_SUCCESS;
3602         union ixgbe_hic_hdr2 buffer;
3603
3604         DEBUGFUNC("ixgbe_update_flash_X550");
3605
3606         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3607         buffer.req.buf_lenh = 0;
3608         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3609         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3610
3611         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3612                                               sizeof(buffer),
3613                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3614
3615         return status;
3616 }
3617
3618 /**
3619  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3620  *  @hw: pointer to hardware structure
3621  *
3622  *  Determines physical layer capabilities of the current configuration.
3623  **/
3624 u64 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3625 {
3626         u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3627         u16 ext_ability = 0;
3628
3629         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3630
3631         hw->phy.ops.identify(hw);
3632
3633         switch (hw->phy.type) {
3634         case ixgbe_phy_x550em_kr:
3635                 if (hw->mac.type == ixgbe_mac_X550EM_a) {
3636                         if (hw->phy.nw_mng_if_sel &
3637                             IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
3638                                 physical_layer =
3639                                         IXGBE_PHYSICAL_LAYER_2500BASE_KX;
3640                                 break;
3641                         } else if (hw->device_id ==
3642                                    IXGBE_DEV_ID_X550EM_A_KR_L) {
3643                                 physical_layer =
3644                                         IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3645                                 break;
3646                         }
3647                 }
3648                 /* fall through */
3649         case ixgbe_phy_x550em_xfi:
3650                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3651                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3652                 break;
3653         case ixgbe_phy_x550em_kx4:
3654                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3655                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3656                 break;
3657         case ixgbe_phy_x550em_ext_t:
3658                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3659                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3660                                      &ext_ability);
3661                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3662                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3663                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3664                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3665                 break;
3666         case ixgbe_phy_fw:
3667                 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_1GB_FULL)
3668                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3669                 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_100_FULL)
3670                         physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
3671                 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_10_FULL)
3672                         physical_layer |= IXGBE_PHYSICAL_LAYER_10BASE_T;
3673                 break;
3674         case ixgbe_phy_sgmii:
3675 #ifdef PREBOOT_SUPPORT
3676                 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
3677                                  IXGBE_PHYSICAL_LAYER_100BASE_TX |
3678                                  IXGBE_PHYSICAL_LAYER_10BASE_T;
3679 #else
3680                 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3681 #endif /* PREBOOT_SUPPORT */
3682                 break;
3683         case ixgbe_phy_ext_1g_t:
3684                 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3685                 break;
3686         default:
3687                 break;
3688         }
3689
3690         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3691                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3692
3693         return physical_layer;
3694 }
3695
3696 /**
3697  * ixgbe_get_bus_info_x550em - Set PCI bus info
3698  * @hw: pointer to hardware structure
3699  *
3700  * Sets bus link width and speed to unknown because X550em is
3701  * not a PCI device.
3702  **/
3703 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3704 {
3705
3706         DEBUGFUNC("ixgbe_get_bus_info_x550em");
3707
3708         hw->bus.width = ixgbe_bus_width_unknown;
3709         hw->bus.speed = ixgbe_bus_speed_unknown;
3710
3711         hw->mac.ops.set_lan_id(hw);
3712
3713         return IXGBE_SUCCESS;
3714 }
3715
3716 /**
3717  * ixgbe_disable_rx_x550 - Disable RX unit
3718  *
3719  * Enables the Rx DMA unit for x550
3720  **/
3721 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3722 {
3723         u32 rxctrl, pfdtxgswc;
3724         s32 status;
3725         struct ixgbe_hic_disable_rxen fw_cmd;
3726
3727         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3728
3729         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3730         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3731                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3732                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3733                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3734                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3735                         hw->mac.set_lben = true;
3736                 } else {
3737                         hw->mac.set_lben = false;
3738                 }
3739
3740                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3741                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3742                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3743                 fw_cmd.port_number = (u8)hw->bus.lan_id;
3744
3745                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3746                                         sizeof(struct ixgbe_hic_disable_rxen),
3747                                         IXGBE_HI_COMMAND_TIMEOUT, true);
3748
3749                 /* If we fail - disable RX using register write */
3750                 if (status) {
3751                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3752                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3753                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3754                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3755                         }
3756                 }
3757         }
3758 }
3759
3760 /**
3761  * ixgbe_enter_lplu_x550em - Transition to low power states
3762  *  @hw: pointer to hardware structure
3763  *
3764  * Configures Low Power Link Up on transition to low power states
3765  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3766  * X557 PHY immediately prior to entering LPLU.
3767  **/
3768 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3769 {
3770         u16 an_10g_cntl_reg, autoneg_reg, speed;
3771         s32 status;
3772         ixgbe_link_speed lcd_speed;
3773         u32 save_autoneg;
3774         bool link_up;
3775
3776         /* SW LPLU not required on later HW revisions. */
3777         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3778             (IXGBE_FUSES0_REV_MASK &
3779              IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3780                 return IXGBE_SUCCESS;
3781
3782         /* If blocked by MNG FW, then don't restart AN */
3783         if (ixgbe_check_reset_blocked(hw))
3784                 return IXGBE_SUCCESS;
3785
3786         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3787         if (status != IXGBE_SUCCESS)
3788                 return status;
3789
3790         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3791
3792         if (status != IXGBE_SUCCESS)
3793                 return status;
3794
3795         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3796          * disabled, then force link down by entering low power mode.
3797          */
3798         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3799             !(hw->wol_enabled || ixgbe_mng_present(hw)))
3800                 return ixgbe_set_copper_phy_power(hw, FALSE);
3801
3802         /* Determine LCD */
3803         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3804
3805         if (status != IXGBE_SUCCESS)
3806                 return status;
3807
3808         /* If no valid LCD link speed, then force link down and exit. */
3809         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3810                 return ixgbe_set_copper_phy_power(hw, FALSE);
3811
3812         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3813                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3814                                       &speed);
3815
3816         if (status != IXGBE_SUCCESS)
3817                 return status;
3818
3819         /* If no link now, speed is invalid so take link down */
3820         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3821         if (status != IXGBE_SUCCESS)
3822                 return ixgbe_set_copper_phy_power(hw, false);
3823
3824         /* clear everything but the speed bits */
3825         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3826
3827         /* If current speed is already LCD, then exit. */
3828         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3829              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3830             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3831              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3832                 return status;
3833
3834         /* Clear AN completed indication */
3835         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3836                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3837                                       &autoneg_reg);
3838
3839         if (status != IXGBE_SUCCESS)
3840                 return status;
3841
3842         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3843                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3844                              &an_10g_cntl_reg);
3845
3846         if (status != IXGBE_SUCCESS)
3847                 return status;
3848
3849         status = hw->phy.ops.read_reg(hw,
3850                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3851                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3852                              &autoneg_reg);
3853
3854         if (status != IXGBE_SUCCESS)
3855                 return status;
3856
3857         save_autoneg = hw->phy.autoneg_advertised;
3858
3859         /* Setup link at least common link speed */
3860         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3861
3862         /* restore autoneg from before setting lplu speed */
3863         hw->phy.autoneg_advertised = save_autoneg;
3864
3865         return status;
3866 }
3867
3868 /**
3869  * ixgbe_get_lcd_x550em - Determine lowest common denominator
3870  *  @hw: pointer to hardware structure
3871  *  @lcd_speed: pointer to lowest common link speed
3872  *
3873  * Determine lowest common link speed with link partner.
3874  **/
3875 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3876 {
3877         u16 an_lp_status;
3878         s32 status;
3879         u16 word = hw->eeprom.ctrl_word_3;
3880
3881         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3882
3883         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3884                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3885                                       &an_lp_status);
3886
3887         if (status != IXGBE_SUCCESS)
3888                 return status;
3889
3890         /* If link partner advertised 1G, return 1G */
3891         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3892                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3893                 return status;
3894         }
3895
3896         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3897         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3898             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3899                 return status;
3900
3901         /* Link partner not capable of lower speeds, return 10G */
3902         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3903         return status;
3904 }
3905
3906 /**
3907  *  ixgbe_setup_fc_X550em - Set up flow control
3908  *  @hw: pointer to hardware structure
3909  *
3910  *  Called at init time to set up flow control.
3911  **/
3912 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3913 {
3914         s32 ret_val = IXGBE_SUCCESS;
3915         u32 pause, asm_dir, reg_val;
3916
3917         DEBUGFUNC("ixgbe_setup_fc_X550em");
3918
3919         /* Validate the requested mode */
3920         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3921                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3922                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3923                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3924                 goto out;
3925         }
3926
3927         /* 10gig parts do not have a word in the EEPROM to determine the
3928          * default flow control setting, so we explicitly set it to full.
3929          */
3930         if (hw->fc.requested_mode == ixgbe_fc_default)
3931                 hw->fc.requested_mode = ixgbe_fc_full;
3932
3933         /* Determine PAUSE and ASM_DIR bits. */
3934         switch (hw->fc.requested_mode) {
3935         case ixgbe_fc_none:
3936                 pause = 0;
3937                 asm_dir = 0;
3938                 break;
3939         case ixgbe_fc_tx_pause:
3940                 pause = 0;
3941                 asm_dir = 1;
3942                 break;
3943         case ixgbe_fc_rx_pause:
3944                 /* Rx Flow control is enabled and Tx Flow control is
3945                  * disabled by software override. Since there really
3946                  * isn't a way to advertise that we are capable of RX
3947                  * Pause ONLY, we will advertise that we support both
3948                  * symmetric and asymmetric Rx PAUSE, as such we fall
3949                  * through to the fc_full statement.  Later, we will
3950                  * disable the adapter's ability to send PAUSE frames.
3951                  */
3952         case ixgbe_fc_full:
3953                 pause = 1;
3954                 asm_dir = 1;
3955                 break;
3956         default:
3957                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3958                         "Flow control param set incorrectly\n");
3959                 ret_val = IXGBE_ERR_CONFIG;
3960                 goto out;
3961         }
3962
3963         switch (hw->device_id) {
3964         case IXGBE_DEV_ID_X550EM_X_KR:
3965         case IXGBE_DEV_ID_X550EM_A_KR:
3966         case IXGBE_DEV_ID_X550EM_A_KR_L:
3967                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
3968                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3969                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3970                 if (ret_val != IXGBE_SUCCESS)
3971                         goto out;
3972                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3973                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3974                 if (pause)
3975                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3976                 if (asm_dir)
3977                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3978                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
3979                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3980                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3981
3982                 /* This device does not fully support AN. */
3983                 hw->fc.disable_fc_autoneg = true;
3984                 break;
3985         case IXGBE_DEV_ID_X550EM_X_XFI:
3986                 hw->fc.disable_fc_autoneg = true;
3987                 break;
3988         default:
3989                 break;
3990         }
3991
3992 out:
3993         return ret_val;
3994 }
3995
3996 /**
3997  *  ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
3998  *  @hw: pointer to hardware structure
3999  *
4000  *  Enable flow control according to IEEE clause 37.
4001  **/
4002 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
4003 {
4004         u32 link_s1, lp_an_page_low, an_cntl_1;
4005         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4006         ixgbe_link_speed speed;
4007         bool link_up;
4008
4009         /* AN should have completed when the cable was plugged in.
4010          * Look for reasons to bail out.  Bail out if:
4011          * - FC autoneg is disabled, or if
4012          * - link is not up.
4013          */
4014         if (hw->fc.disable_fc_autoneg) {
4015                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4016                              "Flow control autoneg is disabled");
4017                 goto out;
4018         }
4019
4020         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4021         if (!link_up) {
4022                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4023                 goto out;
4024         }
4025
4026         /* Check at auto-negotiation has completed */
4027         status = hw->mac.ops.read_iosf_sb_reg(hw,
4028                                         IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4029                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4030
4031         if (status != IXGBE_SUCCESS ||
4032             (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4033                 DEBUGOUT("Auto-Negotiation did not complete\n");
4034                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4035                 goto out;
4036         }
4037
4038         /* Read the 10g AN autoc and LP ability registers and resolve
4039          * local flow control settings accordingly
4040          */
4041         status = hw->mac.ops.read_iosf_sb_reg(hw,
4042                                 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4043                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
4044
4045         if (status != IXGBE_SUCCESS) {
4046                 DEBUGOUT("Auto-Negotiation did not complete\n");
4047                 goto out;
4048         }
4049
4050         status = hw->mac.ops.read_iosf_sb_reg(hw,
4051                                 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
4052                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
4053
4054         if (status != IXGBE_SUCCESS) {
4055                 DEBUGOUT("Auto-Negotiation did not complete\n");
4056                 goto out;
4057         }
4058
4059         status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
4060                                     IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
4061                                     IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
4062                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
4063                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
4064
4065 out:
4066         if (status == IXGBE_SUCCESS) {
4067                 hw->fc.fc_was_autonegged = true;
4068         } else {
4069                 hw->fc.fc_was_autonegged = false;
4070                 hw->fc.current_mode = hw->fc.requested_mode;
4071         }
4072 }
4073
4074 /**
4075  *  ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
4076  *  @hw: pointer to hardware structure
4077  *
4078  **/
4079 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
4080 {
4081         hw->fc.fc_was_autonegged = false;
4082         hw->fc.current_mode = hw->fc.requested_mode;
4083 }
4084
4085 /**
4086  *  ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
4087  *  @hw: pointer to hardware structure
4088  *
4089  *  Enable flow control according to IEEE clause 37.
4090  **/
4091 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
4092 {
4093         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4094         u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
4095         ixgbe_link_speed speed;
4096         bool link_up;
4097
4098         /* AN should have completed when the cable was plugged in.
4099          * Look for reasons to bail out.  Bail out if:
4100          * - FC autoneg is disabled, or if
4101          * - link is not up.
4102          */
4103         if (hw->fc.disable_fc_autoneg) {
4104                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4105                              "Flow control autoneg is disabled");
4106                 goto out;
4107         }
4108
4109         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4110         if (!link_up) {
4111                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4112                 goto out;
4113         }
4114
4115         /* Check if auto-negotiation has completed */
4116         status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info);
4117         if (status != IXGBE_SUCCESS ||
4118             !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) {
4119                 DEBUGOUT("Auto-Negotiation did not complete\n");
4120                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4121                 goto out;
4122         }
4123
4124         /* Negotiate the flow control */
4125         status = ixgbe_negotiate_fc(hw, info[0], info[0],
4126                                     FW_PHY_ACT_GET_LINK_INFO_FC_RX,
4127                                     FW_PHY_ACT_GET_LINK_INFO_FC_TX,
4128                                     FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX,
4129                                     FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX);
4130
4131 out:
4132         if (status == IXGBE_SUCCESS) {
4133                 hw->fc.fc_was_autonegged = true;
4134         } else {
4135                 hw->fc.fc_was_autonegged = false;
4136                 hw->fc.current_mode = hw->fc.requested_mode;
4137         }
4138 }
4139
4140 /**
4141  *  ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4142  *  @hw: pointer to hardware structure
4143  *
4144  *  Called at init time to set up flow control.
4145  **/
4146 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4147 {
4148         s32 status = IXGBE_SUCCESS;
4149         u32 an_cntl = 0;
4150
4151         DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4152
4153         /* Validate the requested mode */
4154         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4155                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4156                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4157                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4158         }
4159
4160         if (hw->fc.requested_mode == ixgbe_fc_default)
4161                 hw->fc.requested_mode = ixgbe_fc_full;
4162
4163         /* Set up the 1G and 10G flow control advertisement registers so the
4164          * HW will be able to do FC autoneg once the cable is plugged in.  If
4165          * we link at 10G, the 1G advertisement is harmless and vice versa.
4166          */
4167         status = hw->mac.ops.read_iosf_sb_reg(hw,
4168                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4169                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4170
4171         if (status != IXGBE_SUCCESS) {
4172                 DEBUGOUT("Auto-Negotiation did not complete\n");
4173                 return status;
4174         }
4175
4176         /* The possible values of fc.requested_mode are:
4177          * 0: Flow control is completely disabled
4178          * 1: Rx flow control is enabled (we can receive pause frames,
4179          *    but not send pause frames).
4180          * 2: Tx flow control is enabled (we can send pause frames but
4181          *    we do not support receiving pause frames).
4182          * 3: Both Rx and Tx flow control (symmetric) are enabled.
4183          * other: Invalid.
4184          */
4185         switch (hw->fc.requested_mode) {
4186         case ixgbe_fc_none:
4187                 /* Flow control completely disabled by software override. */
4188                 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4189                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4190                 break;
4191         case ixgbe_fc_tx_pause:
4192                 /* Tx Flow control is enabled, and Rx Flow control is
4193                  * disabled by software override.
4194                  */
4195                 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4196                 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4197                 break;
4198         case ixgbe_fc_rx_pause:
4199                 /* Rx Flow control is enabled and Tx Flow control is
4200                  * disabled by software override. Since there really
4201                  * isn't a way to advertise that we are capable of RX
4202                  * Pause ONLY, we will advertise that we support both
4203                  * symmetric and asymmetric Rx PAUSE, as such we fall
4204                  * through to the fc_full statement.  Later, we will
4205                  * disable the adapter's ability to send PAUSE frames.
4206                  */
4207         case ixgbe_fc_full:
4208                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4209                 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4210                            IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4211                 break;
4212         default:
4213                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4214                               "Flow control param set incorrectly\n");
4215                 return IXGBE_ERR_CONFIG;
4216         }
4217
4218         status = hw->mac.ops.write_iosf_sb_reg(hw,
4219                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4220                                         IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4221
4222         /* Restart auto-negotiation. */
4223         status = ixgbe_restart_an_internal_phy_x550em(hw);
4224
4225         return status;
4226 }
4227
4228 /**
4229  * ixgbe_set_mux - Set mux for port 1 access with CS4227
4230  * @hw: pointer to hardware structure
4231  * @state: set mux if 1, clear if 0
4232  */
4233 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4234 {
4235         u32 esdp;
4236
4237         if (!hw->bus.lan_id)
4238                 return;
4239         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4240         if (state)
4241                 esdp |= IXGBE_ESDP_SDP1;
4242         else
4243                 esdp &= ~IXGBE_ESDP_SDP1;
4244         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4245         IXGBE_WRITE_FLUSH(hw);
4246 }
4247
4248 /**
4249  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4250  *  @hw: pointer to hardware structure
4251  *  @mask: Mask to specify which semaphore to acquire
4252  *
4253  *  Acquires the SWFW semaphore and sets the I2C MUX
4254  **/
4255 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4256 {
4257         s32 status;
4258
4259         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4260
4261         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4262         if (status)
4263                 return status;
4264
4265         if (mask & IXGBE_GSSR_I2C_MASK)
4266                 ixgbe_set_mux(hw, 1);
4267
4268         return IXGBE_SUCCESS;
4269 }
4270
4271 /**
4272  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4273  *  @hw: pointer to hardware structure
4274  *  @mask: Mask to specify which semaphore to release
4275  *
4276  *  Releases the SWFW semaphore and sets the I2C MUX
4277  **/
4278 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4279 {
4280         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4281
4282         if (mask & IXGBE_GSSR_I2C_MASK)
4283                 ixgbe_set_mux(hw, 0);
4284
4285         ixgbe_release_swfw_sync_X540(hw, mask);
4286 }
4287
4288 /**
4289  *  ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4290  *  @hw: pointer to hardware structure
4291  *  @mask: Mask to specify which semaphore to acquire
4292  *
4293  *  Acquires the SWFW semaphore and get the shared phy token as needed
4294  */
4295 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4296 {
4297         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4298         int retries = FW_PHY_TOKEN_RETRIES;
4299         s32 status = IXGBE_SUCCESS;
4300
4301         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4302
4303         while (--retries) {
4304                 status = IXGBE_SUCCESS;
4305                 if (hmask)
4306                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4307                 if (status) {
4308                         DEBUGOUT1("Could not acquire SWFW semaphore, Status = %d\n",
4309                                   status);
4310                         return status;
4311                 }
4312                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4313                         return IXGBE_SUCCESS;
4314
4315                 status = ixgbe_get_phy_token(hw);
4316                 if (status == IXGBE_ERR_TOKEN_RETRY)
4317                         DEBUGOUT1("Could not acquire PHY token, Status = %d\n",
4318                                   status);
4319
4320                 if (status == IXGBE_SUCCESS)
4321                         return IXGBE_SUCCESS;
4322
4323                 if (hmask)
4324                         ixgbe_release_swfw_sync_X540(hw, hmask);
4325
4326                 if (status != IXGBE_ERR_TOKEN_RETRY) {
4327                         DEBUGOUT1("Unable to retry acquiring the PHY token, Status = %d\n",
4328                                   status);
4329                         return status;
4330                 }
4331         }
4332
4333         DEBUGOUT1("Semaphore acquisition retries failed!: PHY ID = 0x%08X\n",
4334                   hw->phy.id);
4335         return status;
4336 }
4337
4338 /**
4339  *  ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4340  *  @hw: pointer to hardware structure
4341  *  @mask: Mask to specify which semaphore to release
4342  *
4343  *  Releases the SWFW semaphore and puts the shared phy token as needed
4344  */
4345 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4346 {
4347         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4348
4349         DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4350
4351         if (mask & IXGBE_GSSR_TOKEN_SM)
4352                 ixgbe_put_phy_token(hw);
4353
4354         if (hmask)
4355                 ixgbe_release_swfw_sync_X540(hw, hmask);
4356 }
4357
4358 /**
4359  *  ixgbe_read_phy_reg_x550a  - Reads specified PHY register
4360  *  @hw: pointer to hardware structure
4361  *  @reg_addr: 32 bit address of PHY register to read
4362  *  @phy_data: Pointer to read data from PHY register
4363  *
4364  *  Reads a value from a specified PHY register using the SWFW lock and PHY
4365  *  Token. The PHY Token is needed since the MDIO is shared between to MAC
4366  *  instances.
4367  **/
4368 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4369                                u32 device_type, u16 *phy_data)
4370 {
4371         s32 status;
4372         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4373
4374         DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4375
4376         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4377                 return IXGBE_ERR_SWFW_SYNC;
4378
4379         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4380
4381         hw->mac.ops.release_swfw_sync(hw, mask);
4382
4383         return status;
4384 }
4385
4386 /**
4387  *  ixgbe_write_phy_reg_x550a - Writes specified PHY register
4388  *  @hw: pointer to hardware structure
4389  *  @reg_addr: 32 bit PHY register to write
4390  *  @device_type: 5 bit device type
4391  *  @phy_data: Data to write to the PHY register
4392  *
4393  *  Writes a value to specified PHY register using the SWFW lock and PHY Token.
4394  *  The PHY Token is needed since the MDIO is shared between to MAC instances.
4395  **/
4396 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4397                                 u32 device_type, u16 phy_data)
4398 {
4399         s32 status;
4400         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4401
4402         DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4403
4404         if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4405                 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
4406                                                  phy_data);
4407                 hw->mac.ops.release_swfw_sync(hw, mask);
4408         } else {
4409                 status = IXGBE_ERR_SWFW_SYNC;
4410         }
4411
4412         return status;
4413 }
4414
4415 /**
4416  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4417  * @hw: pointer to hardware structure
4418  *
4419  * Handle external Base T PHY interrupt. If high temperature
4420  * failure alarm then return error, else if link status change
4421  * then setup internal/external PHY link
4422  *
4423  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4424  * failure alarm, else return PHY access status.
4425  */
4426 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4427 {
4428         bool lsc;
4429         u32 status;
4430
4431         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4432
4433         if (status != IXGBE_SUCCESS)
4434                 return status;
4435
4436         if (lsc)
4437                 return ixgbe_setup_internal_phy(hw);
4438
4439         return IXGBE_SUCCESS;
4440 }
4441
4442 /**
4443  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4444  * @hw: pointer to hardware structure
4445  * @speed: new link speed
4446  * @autoneg_wait_to_complete: true when waiting for completion is needed
4447  *
4448  * Setup internal/external PHY link speed based on link speed, then set
4449  * external PHY auto advertised link speed.
4450  *
4451  * Returns error status for any failure
4452  **/
4453 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4454                                   ixgbe_link_speed speed,
4455                                   bool autoneg_wait_to_complete)
4456 {
4457         s32 status;
4458         ixgbe_link_speed force_speed;
4459
4460         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4461
4462         /* Setup internal/external PHY link speed to iXFI (10G), unless
4463          * only 1G is auto advertised then setup KX link.
4464          */
4465         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4466                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4467         else
4468                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4469
4470         /* If X552 and internal link mode is XFI, then setup XFI internal link.
4471          */
4472         if (hw->mac.type == ixgbe_mac_X550EM_x &&
4473             !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4474                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4475
4476                 if (status != IXGBE_SUCCESS)
4477                         return status;
4478         }
4479
4480         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4481 }
4482
4483 /**
4484  * ixgbe_check_link_t_X550em - Determine link and speed status
4485  * @hw: pointer to hardware structure
4486  * @speed: pointer to link speed
4487  * @link_up: true when link is up
4488  * @link_up_wait_to_complete: bool used to wait for link up or not
4489  *
4490  * Check that both the MAC and X557 external PHY have link.
4491  **/
4492 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4493                               bool *link_up, bool link_up_wait_to_complete)
4494 {
4495         u32 status;
4496         u16 i, autoneg_status = 0;
4497
4498         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4499                 return IXGBE_ERR_CONFIG;
4500
4501         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4502                                               link_up_wait_to_complete);
4503
4504         /* If check link fails or MAC link is not up, then return */
4505         if (status != IXGBE_SUCCESS || !(*link_up))
4506                 return status;
4507
4508         /* MAC link is up, so check external PHY link.
4509          * X557 PHY. Link status is latching low, and can only be used to detect
4510          * link drop, and not the current status of the link without performing
4511          * back-to-back reads.
4512          */
4513         for (i = 0; i < 2; i++) {
4514                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4515                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4516                                               &autoneg_status);
4517
4518                 if (status != IXGBE_SUCCESS)
4519                         return status;
4520         }
4521
4522         /* If external PHY link is not up, then indicate link not up */
4523         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4524                 *link_up = false;
4525
4526         return IXGBE_SUCCESS;
4527 }
4528
4529 /**
4530  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4531  *  @hw: pointer to hardware structure
4532  **/
4533 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4534 {
4535         s32 status;
4536
4537         status = ixgbe_reset_phy_generic(hw);
4538
4539         if (status != IXGBE_SUCCESS)
4540                 return status;
4541
4542         /* Configure Link Status Alarm and Temperature Threshold interrupts */
4543         return ixgbe_enable_lasi_ext_t_x550em(hw);
4544 }
4545
4546 /**
4547  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4548  *  @hw: pointer to hardware structure
4549  *  @led_idx: led number to turn on
4550  **/
4551 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4552 {
4553         u16 phy_data;
4554
4555         DEBUGFUNC("ixgbe_led_on_t_X550em");
4556
4557         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4558                 return IXGBE_ERR_PARAM;
4559
4560         /* To turn on the LED, set mode to ON. */
4561         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4562                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4563         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4564         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4565                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4566
4567         /* Some designs have the LEDs wired to the MAC */
4568         return ixgbe_led_on_generic(hw, led_idx);
4569 }
4570
4571 /**
4572  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4573  *  @hw: pointer to hardware structure
4574  *  @led_idx: led number to turn off
4575  **/
4576 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4577 {
4578         u16 phy_data;
4579
4580         DEBUGFUNC("ixgbe_led_off_t_X550em");
4581
4582         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4583                 return IXGBE_ERR_PARAM;
4584
4585         /* To turn on the LED, set mode to ON. */
4586         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4587                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4588         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4589         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4590                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4591
4592         /* Some designs have the LEDs wired to the MAC */
4593         return ixgbe_led_off_generic(hw, led_idx);
4594 }
4595
4596 /**
4597  *  ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware
4598  *  @hw: pointer to the HW structure
4599  *  @maj: driver version major number
4600  *  @min: driver version minor number
4601  *  @build: driver version build number
4602  *  @sub: driver version sub build number
4603  *  @len: length of driver_ver string
4604  *  @driver_ver: driver string
4605  *
4606  *  Sends driver version number to firmware through the manageability
4607  *  block.  On success return IXGBE_SUCCESS
4608  *  else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4609  *  semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4610  **/
4611 s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,
4612                               u8 build, u8 sub, u16 len, const char *driver_ver)
4613 {
4614         struct ixgbe_hic_drv_info2 fw_cmd;
4615         s32 ret_val = IXGBE_SUCCESS;
4616         int i;
4617
4618         DEBUGFUNC("ixgbe_set_fw_drv_ver_x550");
4619
4620         if ((len == 0) || (driver_ver == NULL) ||
4621            (len > sizeof(fw_cmd.driver_string)))
4622                 return IXGBE_ERR_INVALID_ARGUMENT;
4623
4624         fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4625         fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len;
4626         fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4627         fw_cmd.port_num = (u8)hw->bus.func;
4628         fw_cmd.ver_maj = maj;
4629         fw_cmd.ver_min = min;
4630         fw_cmd.ver_build = build;
4631         fw_cmd.ver_sub = sub;
4632         fw_cmd.hdr.checksum = 0;
4633         memcpy(fw_cmd.driver_string, driver_ver, len);
4634         fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4635                                 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4636
4637         for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4638                 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4639                                                        sizeof(fw_cmd),
4640                                                        IXGBE_HI_COMMAND_TIMEOUT,
4641                                                        true);
4642                 if (ret_val != IXGBE_SUCCESS)
4643                         continue;
4644
4645                 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4646                     FW_CEM_RESP_STATUS_SUCCESS)
4647                         ret_val = IXGBE_SUCCESS;
4648                 else
4649                         ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4650
4651                 break;
4652         }
4653
4654         return ret_val;
4655 }