1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
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16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
44 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw);
47 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
48 * @hw: pointer to hardware structure
50 * Initialize the function pointers and assign the MAC type for X550.
51 * Does not touch the hardware.
53 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
55 struct ixgbe_mac_info *mac = &hw->mac;
56 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
59 DEBUGFUNC("ixgbe_init_ops_X550");
61 ret_val = ixgbe_init_ops_X540(hw);
62 mac->ops.dmac_config = ixgbe_dmac_config_X550;
63 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
64 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
65 mac->ops.setup_eee = NULL;
66 mac->ops.set_source_address_pruning =
67 ixgbe_set_source_address_pruning_X550;
68 mac->ops.set_ethertype_anti_spoofing =
69 ixgbe_set_ethertype_anti_spoofing_X550;
71 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
72 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
73 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
74 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
75 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
76 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
77 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
78 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
79 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
81 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
82 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
83 mac->ops.mdd_event = ixgbe_mdd_event_X550;
84 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
85 mac->ops.disable_rx = ixgbe_disable_rx_x550;
86 /* Manageability interface */
87 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_x550;
88 switch (hw->device_id) {
89 case IXGBE_DEV_ID_X550EM_X_10G_T:
90 case IXGBE_DEV_ID_X550EM_A_10G_T:
91 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
92 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
101 * ixgbe_read_cs4227 - Read CS4227 register
102 * @hw: pointer to hardware structure
103 * @reg: register number to write
104 * @value: pointer to receive value read
106 * Returns status code
108 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
110 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
114 * ixgbe_write_cs4227 - Write CS4227 register
115 * @hw: pointer to hardware structure
116 * @reg: register number to write
117 * @value: value to write to register
119 * Returns status code
121 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
123 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
127 * ixgbe_read_pe - Read register from port expander
128 * @hw: pointer to hardware structure
129 * @reg: register number to read
130 * @value: pointer to receive read value
132 * Returns status code
134 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
138 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
139 if (status != IXGBE_SUCCESS)
140 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
141 "port expander access failed with %d\n", status);
146 * ixgbe_write_pe - Write register to port expander
147 * @hw: pointer to hardware structure
148 * @reg: register number to write
149 * @value: value to write
151 * Returns status code
153 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
157 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
158 if (status != IXGBE_SUCCESS)
159 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
160 "port expander access failed with %d\n", status);
165 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
166 * @hw: pointer to hardware structure
168 * This function assumes that the caller has acquired the proper semaphore.
171 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
178 /* Trigger hard reset. */
179 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
180 if (status != IXGBE_SUCCESS)
182 reg |= IXGBE_PE_BIT1;
183 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
184 if (status != IXGBE_SUCCESS)
187 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
188 if (status != IXGBE_SUCCESS)
190 reg &= ~IXGBE_PE_BIT1;
191 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
192 if (status != IXGBE_SUCCESS)
195 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
196 if (status != IXGBE_SUCCESS)
198 reg &= ~IXGBE_PE_BIT1;
199 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
200 if (status != IXGBE_SUCCESS)
203 usec_delay(IXGBE_CS4227_RESET_HOLD);
205 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
206 if (status != IXGBE_SUCCESS)
208 reg |= IXGBE_PE_BIT1;
209 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
210 if (status != IXGBE_SUCCESS)
213 /* Wait for the reset to complete. */
214 msec_delay(IXGBE_CS4227_RESET_DELAY);
215 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
216 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
218 if (status == IXGBE_SUCCESS &&
219 value == IXGBE_CS4227_EEPROM_LOAD_OK)
221 msec_delay(IXGBE_CS4227_CHECK_DELAY);
223 if (retry == IXGBE_CS4227_RETRIES) {
224 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
225 "CS4227 reset did not complete.");
226 return IXGBE_ERR_PHY;
229 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
230 if (status != IXGBE_SUCCESS ||
231 !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
232 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
233 "CS4227 EEPROM did not load successfully.");
234 return IXGBE_ERR_PHY;
237 return IXGBE_SUCCESS;
241 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
242 * @hw: pointer to hardware structure
244 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
246 s32 status = IXGBE_SUCCESS;
247 u32 swfw_mask = hw->phy.phy_semaphore_mask;
251 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
252 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
253 if (status != IXGBE_SUCCESS) {
254 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
255 "semaphore failed with %d", status);
256 msec_delay(IXGBE_CS4227_CHECK_DELAY);
260 /* Get status of reset flow. */
261 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
263 if (status == IXGBE_SUCCESS &&
264 value == IXGBE_CS4227_RESET_COMPLETE)
267 if (status != IXGBE_SUCCESS ||
268 value != IXGBE_CS4227_RESET_PENDING)
271 /* Reset is pending. Wait and check again. */
272 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
273 msec_delay(IXGBE_CS4227_CHECK_DELAY);
276 /* If still pending, assume other instance failed. */
277 if (retry == IXGBE_CS4227_RETRIES) {
278 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
279 if (status != IXGBE_SUCCESS) {
280 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
281 "semaphore failed with %d", status);
286 /* Reset the CS4227. */
287 status = ixgbe_reset_cs4227(hw);
288 if (status != IXGBE_SUCCESS) {
289 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
290 "CS4227 reset failed: %d", status);
294 /* Reset takes so long, temporarily release semaphore in case the
295 * other driver instance is waiting for the reset indication.
297 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
298 IXGBE_CS4227_RESET_PENDING);
299 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
301 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
302 if (status != IXGBE_SUCCESS) {
303 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
304 "semaphore failed with %d", status);
308 /* Record completion for next time. */
309 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
310 IXGBE_CS4227_RESET_COMPLETE);
313 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
314 msec_delay(hw->eeprom.semaphore_delay);
318 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
319 * @hw: pointer to hardware structure
321 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
323 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
325 if (hw->bus.lan_id) {
326 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
327 esdp |= IXGBE_ESDP_SDP1_DIR;
329 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
330 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
331 IXGBE_WRITE_FLUSH(hw);
335 * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
336 * @hw: pointer to hardware structure
337 * @reg_addr: 32 bit address of PHY register to read
338 * @dev_type: always unused
339 * @phy_data: Pointer to read data from PHY register
341 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
342 u32 dev_type, u16 *phy_data)
344 u32 i, data, command;
345 UNREFERENCED_1PARAMETER(dev_type);
347 /* Setup and write the read command */
348 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
349 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
350 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
351 IXGBE_MSCA_MDI_COMMAND;
353 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
355 /* Check every 10 usec to see if the access completed.
356 * The MDI Command bit will clear when the operation is
359 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
362 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
363 if (!(command & IXGBE_MSCA_MDI_COMMAND))
367 if (command & IXGBE_MSCA_MDI_COMMAND) {
368 ERROR_REPORT1(IXGBE_ERROR_POLLING,
369 "PHY read command did not complete.\n");
370 return IXGBE_ERR_PHY;
373 /* Read operation is complete. Get the data from MSRWD */
374 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
375 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
376 *phy_data = (u16)data;
378 return IXGBE_SUCCESS;
382 * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
383 * @hw: pointer to hardware structure
384 * @reg_addr: 32 bit PHY register to write
385 * @dev_type: always unused
386 * @phy_data: Data to write to the PHY register
388 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
389 u32 dev_type, u16 phy_data)
392 UNREFERENCED_1PARAMETER(dev_type);
394 /* Put the data in the MDI single read and write data register*/
395 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
397 /* Setup and write the write command */
398 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
399 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
400 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
401 IXGBE_MSCA_MDI_COMMAND;
403 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
405 /* Check every 10 usec to see if the access completed.
406 * The MDI Command bit will clear when the operation is
409 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
412 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
413 if (!(command & IXGBE_MSCA_MDI_COMMAND))
417 if (command & IXGBE_MSCA_MDI_COMMAND) {
418 ERROR_REPORT1(IXGBE_ERROR_POLLING,
419 "PHY write cmd didn't complete\n");
420 return IXGBE_ERR_PHY;
423 return IXGBE_SUCCESS;
427 * ixgbe_identify_phy_x550em - Get PHY type based on device id
428 * @hw: pointer to hardware structure
432 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
434 hw->mac.ops.set_lan_id(hw);
436 ixgbe_read_mng_if_sel_x550em(hw);
438 switch (hw->device_id) {
439 case IXGBE_DEV_ID_X550EM_A_SFP:
440 return ixgbe_identify_module_generic(hw);
441 case IXGBE_DEV_ID_X550EM_X_SFP:
442 /* set up for CS4227 usage */
443 ixgbe_setup_mux_ctl(hw);
444 ixgbe_check_cs4227(hw);
447 case IXGBE_DEV_ID_X550EM_A_SFP_N:
448 return ixgbe_identify_module_generic(hw);
450 case IXGBE_DEV_ID_X550EM_X_KX4:
451 hw->phy.type = ixgbe_phy_x550em_kx4;
453 case IXGBE_DEV_ID_X550EM_X_XFI:
454 hw->phy.type = ixgbe_phy_x550em_xfi;
456 case IXGBE_DEV_ID_X550EM_X_KR:
457 case IXGBE_DEV_ID_X550EM_A_KR:
458 case IXGBE_DEV_ID_X550EM_A_KR_L:
459 hw->phy.type = ixgbe_phy_x550em_kr;
461 case IXGBE_DEV_ID_X550EM_A_10G_T:
462 case IXGBE_DEV_ID_X550EM_X_1G_T:
463 case IXGBE_DEV_ID_X550EM_X_10G_T:
464 return ixgbe_identify_phy_generic(hw);
465 case IXGBE_DEV_ID_X550EM_A_1G_T:
466 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
467 hw->phy.type = ixgbe_phy_fw;
468 hw->phy.ops.read_reg = NULL;
469 hw->phy.ops.write_reg = NULL;
471 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
473 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
478 return IXGBE_SUCCESS;
482 * ixgbe_fw_phy_activity - Perform an activity on a PHY
483 * @hw: pointer to hardware structure
484 * @activity: activity to perform
485 * @data: Pointer to 4 32-bit words of data
487 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,
488 u32 (*data)[FW_PHY_ACT_DATA_COUNT])
491 struct ixgbe_hic_phy_activity_req cmd;
492 struct ixgbe_hic_phy_activity_resp rsp;
494 u16 retries = FW_PHY_ACT_RETRIES;
499 memset(&hic, 0, sizeof(hic));
500 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD;
501 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN;
502 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
503 hic.cmd.port_number = hw->bus.lan_id;
504 hic.cmd.activity_id = IXGBE_CPU_TO_LE16(activity);
505 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
506 hic.cmd.data[i] = IXGBE_CPU_TO_BE32((*data)[i]);
508 rc = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
510 IXGBE_HI_COMMAND_TIMEOUT,
512 if (rc != IXGBE_SUCCESS)
514 if (hic.rsp.hdr.cmd_or_resp.ret_status ==
515 FW_CEM_RESP_STATUS_SUCCESS) {
516 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
517 (*data)[i] = IXGBE_BE32_TO_CPU(hic.rsp.data[i]);
518 return IXGBE_SUCCESS;
522 } while (retries > 0);
524 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
527 static const struct {
529 ixgbe_link_speed phy_speed;
531 { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL },
532 { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL },
533 { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL },
534 { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL },
535 { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL },
536 { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL },
540 * ixgbe_get_phy_id_fw - Get the phy ID via firmware command
541 * @hw: pointer to hardware structure
545 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw)
547 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
553 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info);
557 hw->phy.speeds_supported = 0;
558 phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK;
559 for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
560 if (phy_speeds & ixgbe_fw_map[i].fw_speed)
561 hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed;
563 if (!hw->phy.autoneg_advertised)
564 hw->phy.autoneg_advertised = hw->phy.speeds_supported;
566 hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK;
567 phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK;
568 hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK;
569 hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK;
570 if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK)
571 return IXGBE_ERR_PHY_ADDR_INVALID;
572 return IXGBE_SUCCESS;
576 * ixgbe_identify_phy_fw - Get PHY type based on firmware command
577 * @hw: pointer to hardware structure
581 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw)
584 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
586 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
588 hw->phy.type = ixgbe_phy_fw;
589 hw->phy.ops.read_reg = NULL;
590 hw->phy.ops.write_reg = NULL;
591 return ixgbe_get_phy_id_fw(hw);
595 * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY
596 * @hw: pointer to hardware structure
600 s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw)
602 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
604 setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF;
605 return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup);
608 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
609 u32 device_type, u16 *phy_data)
611 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
612 return IXGBE_NOT_IMPLEMENTED;
615 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
616 u32 device_type, u16 phy_data)
618 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
619 return IXGBE_NOT_IMPLEMENTED;
623 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
624 * @hw: pointer to the hardware structure
625 * @addr: I2C bus address to read from
626 * @reg: I2C device register to read from
627 * @val: pointer to location to receive read value
629 * Returns an error code on error.
631 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
634 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
638 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
639 * @hw: pointer to the hardware structure
640 * @addr: I2C bus address to read from
641 * @reg: I2C device register to read from
642 * @val: pointer to location to receive read value
644 * Returns an error code on error.
647 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
650 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
654 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
655 * @hw: pointer to the hardware structure
656 * @addr: I2C bus address to write to
657 * @reg: I2C device register to write to
658 * @val: value to write
660 * Returns an error code on error.
662 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
663 u8 addr, u16 reg, u16 val)
665 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
669 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
670 * @hw: pointer to the hardware structure
671 * @addr: I2C bus address to write to
672 * @reg: I2C device register to write to
673 * @val: value to write
675 * Returns an error code on error.
678 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
679 u8 addr, u16 reg, u16 val)
681 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
685 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
686 * @hw: pointer to hardware structure
688 * Initialize the function pointers and for MAC type X550EM.
689 * Does not touch the hardware.
691 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
693 struct ixgbe_mac_info *mac = &hw->mac;
694 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
695 struct ixgbe_phy_info *phy = &hw->phy;
698 DEBUGFUNC("ixgbe_init_ops_X550EM");
700 /* Similar to X550 so start there. */
701 ret_val = ixgbe_init_ops_X550(hw);
703 /* Since this function eventually calls
704 * ixgbe_init_ops_540 by design, we are setting
705 * the pointers to NULL explicitly here to overwrite
706 * the values being set in the x540 function.
708 /* Thermal sensor not supported in x550EM */
709 mac->ops.get_thermal_sensor_data = NULL;
710 mac->ops.init_thermal_sensor_thresh = NULL;
711 mac->thermal_sensor_enabled = false;
713 /* FCOE not supported in x550EM */
714 mac->ops.get_san_mac_addr = NULL;
715 mac->ops.set_san_mac_addr = NULL;
716 mac->ops.get_wwn_prefix = NULL;
717 mac->ops.get_fcoe_boot_status = NULL;
719 /* IPsec not supported in x550EM */
720 mac->ops.disable_sec_rx_path = NULL;
721 mac->ops.enable_sec_rx_path = NULL;
723 /* AUTOC register is not present in x550EM. */
724 mac->ops.prot_autoc_read = NULL;
725 mac->ops.prot_autoc_write = NULL;
727 /* X550EM bus type is internal*/
728 hw->bus.type = ixgbe_bus_type_internal;
729 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
732 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
733 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
734 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
735 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
736 mac->ops.get_supported_physical_layer =
737 ixgbe_get_supported_physical_layer_X550em;
739 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
740 mac->ops.setup_fc = ixgbe_setup_fc_generic;
742 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
745 phy->ops.init = ixgbe_init_phy_ops_X550em;
746 switch (hw->device_id) {
747 case IXGBE_DEV_ID_X550EM_A_1G_T:
748 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
749 mac->ops.setup_fc = NULL;
750 phy->ops.identify = ixgbe_identify_phy_fw;
751 phy->ops.set_phy_power = NULL;
752 phy->ops.get_firmware_version = NULL;
755 phy->ops.identify = ixgbe_identify_phy_x550em;
758 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
759 phy->ops.set_phy_power = NULL;
763 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
764 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
765 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
766 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
767 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
768 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
769 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
770 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
776 * ixgbe_setup_fw_link - Setup firmware-controlled PHYs
777 * @hw: pointer to hardware structure
779 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw)
781 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
785 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
788 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
789 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
790 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
791 return IXGBE_ERR_INVALID_LINK_SETTINGS;
794 switch (hw->fc.requested_mode) {
796 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX <<
797 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
799 case ixgbe_fc_rx_pause:
800 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX <<
801 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
803 case ixgbe_fc_tx_pause:
804 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX <<
805 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
811 for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
812 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)
813 setup[0] |= ixgbe_fw_map[i].fw_speed;
815 setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN;
817 if (hw->phy.eee_speeds_advertised)
818 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE;
820 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup);
823 if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN)
824 return IXGBE_ERR_OVERTEMP;
825 return IXGBE_SUCCESS;
829 * ixgbe_fc_autoneg_fw _ Set up flow control for FW-controlled PHYs
830 * @hw: pointer to hardware structure
832 * Called at init time to set up flow control.
834 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw)
836 if (hw->fc.requested_mode == ixgbe_fc_default)
837 hw->fc.requested_mode = ixgbe_fc_full;
839 return ixgbe_setup_fw_link(hw);
843 * ixgbe_setup_eee_fw - Enable/disable EEE support
844 * @hw: pointer to the HW structure
845 * @enable_eee: boolean flag to enable EEE
847 * Enable/disable EEE based on enable_eee flag.
848 * This function controls EEE for firmware-based PHY implementations.
850 static s32 ixgbe_setup_eee_fw(struct ixgbe_hw *hw, bool enable_eee)
852 if (!!hw->phy.eee_speeds_advertised == enable_eee)
853 return IXGBE_SUCCESS;
855 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
857 hw->phy.eee_speeds_advertised = 0;
858 return hw->phy.ops.setup_link(hw);
862 * ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
863 * @hw: pointer to hardware structure
865 * Initialize the function pointers and for MAC type X550EM_a.
866 * Does not touch the hardware.
868 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
870 struct ixgbe_mac_info *mac = &hw->mac;
873 DEBUGFUNC("ixgbe_init_ops_X550EM_a");
875 /* Start with generic X550EM init */
876 ret_val = ixgbe_init_ops_X550EM(hw);
878 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
879 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) {
880 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
881 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
883 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
884 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
886 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
887 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
889 switch (mac->ops.get_media_type(hw)) {
890 case ixgbe_media_type_fiber:
891 mac->ops.setup_fc = NULL;
892 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
894 case ixgbe_media_type_backplane:
895 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
896 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
902 switch (hw->device_id) {
903 case IXGBE_DEV_ID_X550EM_A_1G_T:
904 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
905 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
906 mac->ops.setup_fc = ixgbe_fc_autoneg_fw;
907 mac->ops.setup_eee = ixgbe_setup_eee_fw;
908 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL |
909 IXGBE_LINK_SPEED_1GB_FULL;
910 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
920 * ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
921 * @hw: pointer to hardware structure
923 * Initialize the function pointers and for MAC type X550EM_x.
924 * Does not touch the hardware.
926 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
928 struct ixgbe_mac_info *mac = &hw->mac;
929 struct ixgbe_link_info *link = &hw->link;
932 DEBUGFUNC("ixgbe_init_ops_X550EM_x");
934 /* Start with generic X550EM init */
935 ret_val = ixgbe_init_ops_X550EM(hw);
937 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
938 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
939 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
940 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
941 link->ops.read_link = ixgbe_read_i2c_combined_generic;
942 link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
943 link->ops.write_link = ixgbe_write_i2c_combined_generic;
944 link->ops.write_link_unlocked =
945 ixgbe_write_i2c_combined_generic_unlocked;
946 link->addr = IXGBE_CS4227;
953 * ixgbe_dmac_config_X550
954 * @hw: pointer to hardware structure
956 * Configure DMA coalescing. If enabling dmac, dmac is activated.
957 * When disabling dmac, dmac enable dmac bit is cleared.
959 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
961 u32 reg, high_pri_tc;
963 DEBUGFUNC("ixgbe_dmac_config_X550");
965 /* Disable DMA coalescing before configuring */
966 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
967 reg &= ~IXGBE_DMACR_DMAC_EN;
968 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
970 /* Disable DMA Coalescing if the watchdog timer is 0 */
971 if (!hw->mac.dmac_config.watchdog_timer)
974 ixgbe_dmac_config_tcs_X550(hw);
976 /* Configure DMA Coalescing Control Register */
977 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
979 /* Set the watchdog timer in units of 40.96 usec */
980 reg &= ~IXGBE_DMACR_DMACWT_MASK;
981 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
983 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
984 /* If fcoe is enabled, set high priority traffic class */
985 if (hw->mac.dmac_config.fcoe_en) {
986 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
987 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
988 IXGBE_DMACR_HIGH_PRI_TC_MASK);
990 reg |= IXGBE_DMACR_EN_MNG_IND;
992 /* Enable DMA coalescing after configuration */
993 reg |= IXGBE_DMACR_DMAC_EN;
994 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
997 return IXGBE_SUCCESS;
1001 * ixgbe_dmac_config_tcs_X550
1002 * @hw: pointer to hardware structure
1004 * Configure DMA coalescing threshold per TC. The dmac enable bit must
1005 * be cleared before configuring.
1007 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
1009 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
1011 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
1013 /* Configure DMA coalescing enabled */
1014 switch (hw->mac.dmac_config.link_speed) {
1015 case IXGBE_LINK_SPEED_10_FULL:
1016 case IXGBE_LINK_SPEED_100_FULL:
1017 pb_headroom = IXGBE_DMACRXT_100M;
1019 case IXGBE_LINK_SPEED_1GB_FULL:
1020 pb_headroom = IXGBE_DMACRXT_1G;
1023 pb_headroom = IXGBE_DMACRXT_10G;
1027 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
1028 IXGBE_MHADD_MFS_SHIFT) / 1024);
1030 /* Set the per Rx packet buffer receive threshold */
1031 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
1032 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
1033 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
1035 if (tc < hw->mac.dmac_config.num_tcs) {
1036 /* Get Rx PB size */
1037 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
1038 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
1039 IXGBE_RXPBSIZE_SHIFT;
1041 /* Calculate receive buffer threshold in kilobytes */
1042 if (rx_pb_size > pb_headroom)
1043 rx_pb_size = rx_pb_size - pb_headroom;
1047 /* Minimum of MFS shall be set for DMCTH */
1048 reg |= (rx_pb_size > maxframe_size_kb) ?
1049 rx_pb_size : maxframe_size_kb;
1051 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
1053 return IXGBE_SUCCESS;
1057 * ixgbe_dmac_update_tcs_X550
1058 * @hw: pointer to hardware structure
1060 * Disables dmac, updates per TC settings, and then enables dmac.
1062 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
1066 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
1068 /* Disable DMA coalescing before configuring */
1069 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
1070 reg &= ~IXGBE_DMACR_DMAC_EN;
1071 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
1073 ixgbe_dmac_config_tcs_X550(hw);
1075 /* Enable DMA coalescing after configuration */
1076 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
1077 reg |= IXGBE_DMACR_DMAC_EN;
1078 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
1080 return IXGBE_SUCCESS;
1084 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
1085 * @hw: pointer to hardware structure
1087 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
1088 * ixgbe_hw struct in order to set up EEPROM access.
1090 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
1092 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1096 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
1098 if (eeprom->type == ixgbe_eeprom_uninitialized) {
1099 eeprom->semaphore_delay = 10;
1100 eeprom->type = ixgbe_flash;
1102 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1103 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1104 IXGBE_EEC_SIZE_SHIFT);
1105 eeprom->word_size = 1 << (eeprom_size +
1106 IXGBE_EEPROM_WORD_SIZE_SHIFT);
1108 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
1109 eeprom->type, eeprom->word_size);
1112 return IXGBE_SUCCESS;
1116 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1117 * @hw: pointer to hardware structure
1118 * @enable: enable or disable source address pruning
1119 * @pool: Rx pool to set source address pruning for
1121 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1126 /* max rx pool is 63 */
1130 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1131 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1134 pfflp |= (1ULL << pool);
1136 pfflp &= ~(1ULL << pool);
1138 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1139 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1143 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1144 * @hw: pointer to hardware structure
1145 * @enable: enable or disable switch for Ethertype anti-spoofing
1146 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1149 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1150 bool enable, int vf)
1152 int vf_target_reg = vf >> 3;
1153 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1156 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1158 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1160 pfvfspoof |= (1 << vf_target_shift);
1162 pfvfspoof &= ~(1 << vf_target_shift);
1164 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1168 * ixgbe_iosf_wait - Wait for IOSF command completion
1169 * @hw: pointer to hardware structure
1170 * @ctrl: pointer to location to receive final IOSF control value
1172 * Returns failing status on timeout
1174 * Note: ctrl can be NULL if the IOSF control register value is not needed
1176 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1180 /* Check every 10 usec to see if the address cycle completed.
1181 * The SB IOSF BUSY bit will clear when the operation is
1184 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1185 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1186 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1192 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1193 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1194 return IXGBE_ERR_PHY;
1197 return IXGBE_SUCCESS;
1201 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register
1202 * of the IOSF device
1203 * @hw: pointer to hardware structure
1204 * @reg_addr: 32 bit PHY register to write
1205 * @device_type: 3 bit device type
1206 * @data: Data to write to the register
1208 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1209 u32 device_type, u32 data)
1211 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1215 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1216 if (ret != IXGBE_SUCCESS)
1219 ret = ixgbe_iosf_wait(hw, NULL);
1220 if (ret != IXGBE_SUCCESS)
1223 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1224 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1226 /* Write IOSF control register */
1227 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1229 /* Write IOSF data register */
1230 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1232 ret = ixgbe_iosf_wait(hw, &command);
1234 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1235 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1236 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1237 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1238 "Failed to write, error %x\n", error);
1239 ret = IXGBE_ERR_PHY;
1243 ixgbe_release_swfw_semaphore(hw, gssr);
1248 * ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device
1249 * @hw: pointer to hardware structure
1250 * @reg_addr: 32 bit PHY register to write
1251 * @device_type: 3 bit device type
1252 * @data: Pointer to read data from the register
1254 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1255 u32 device_type, u32 *data)
1257 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1261 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1262 if (ret != IXGBE_SUCCESS)
1265 ret = ixgbe_iosf_wait(hw, NULL);
1266 if (ret != IXGBE_SUCCESS)
1269 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1270 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1272 /* Write IOSF control register */
1273 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1275 ret = ixgbe_iosf_wait(hw, &command);
1277 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1278 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1279 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1280 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1281 "Failed to read, error %x\n", error);
1282 ret = IXGBE_ERR_PHY;
1285 if (ret == IXGBE_SUCCESS)
1286 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1289 ixgbe_release_swfw_semaphore(hw, gssr);
1294 * ixgbe_get_phy_token - Get the token for shared phy access
1295 * @hw: Pointer to hardware structure
1298 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1300 struct ixgbe_hic_phy_token_req token_cmd;
1303 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1304 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1305 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1306 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1307 token_cmd.port_number = hw->bus.lan_id;
1308 token_cmd.command_type = FW_PHY_TOKEN_REQ;
1310 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1312 IXGBE_HI_COMMAND_TIMEOUT,
1315 DEBUGOUT1("Issuing host interface command failed with Status = %d\n",
1319 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1320 return IXGBE_SUCCESS;
1321 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY) {
1322 DEBUGOUT1("Host interface command returned 0x%08x , returning IXGBE_ERR_FW_RESP_INVALID\n",
1323 token_cmd.hdr.cmd_or_resp.ret_status);
1324 return IXGBE_ERR_FW_RESP_INVALID;
1327 DEBUGOUT("Returning IXGBE_ERR_TOKEN_RETRY\n");
1328 return IXGBE_ERR_TOKEN_RETRY;
1332 * ixgbe_put_phy_token - Put the token for shared phy access
1333 * @hw: Pointer to hardware structure
1336 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1338 struct ixgbe_hic_phy_token_req token_cmd;
1341 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1342 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1343 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1344 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1345 token_cmd.port_number = hw->bus.lan_id;
1346 token_cmd.command_type = FW_PHY_TOKEN_REL;
1348 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1350 IXGBE_HI_COMMAND_TIMEOUT,
1354 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1355 return IXGBE_SUCCESS;
1357 DEBUGOUT("Put PHY Token host interface command failed");
1358 return IXGBE_ERR_FW_RESP_INVALID;
1362 * ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1363 * of the IOSF device
1364 * @hw: pointer to hardware structure
1365 * @reg_addr: 32 bit PHY register to write
1366 * @device_type: 3 bit device type
1367 * @data: Data to write to the register
1369 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1370 u32 device_type, u32 data)
1372 struct ixgbe_hic_internal_phy_req write_cmd;
1374 UNREFERENCED_1PARAMETER(device_type);
1376 memset(&write_cmd, 0, sizeof(write_cmd));
1377 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1378 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1379 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1380 write_cmd.port_number = hw->bus.lan_id;
1381 write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1382 write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1383 write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1385 status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1387 IXGBE_HI_COMMAND_TIMEOUT, false);
1393 * ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device
1394 * @hw: pointer to hardware structure
1395 * @reg_addr: 32 bit PHY register to write
1396 * @device_type: 3 bit device type
1397 * @data: Pointer to read data from the register
1399 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1400 u32 device_type, u32 *data)
1403 struct ixgbe_hic_internal_phy_req cmd;
1404 struct ixgbe_hic_internal_phy_resp rsp;
1407 UNREFERENCED_1PARAMETER(device_type);
1409 memset(&hic, 0, sizeof(hic));
1410 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1411 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1412 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1413 hic.cmd.port_number = hw->bus.lan_id;
1414 hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1415 hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1417 status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1419 IXGBE_HI_COMMAND_TIMEOUT, true);
1421 /* Extract the register value from the response. */
1422 *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1428 * ixgbe_disable_mdd_X550
1429 * @hw: pointer to hardware structure
1431 * Disable malicious driver detection
1433 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1437 DEBUGFUNC("ixgbe_disable_mdd_X550");
1439 /* Disable MDD for TX DMA and interrupt */
1440 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1441 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1442 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1444 /* Disable MDD for RX and interrupt */
1445 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1446 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1447 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1451 * ixgbe_enable_mdd_X550
1452 * @hw: pointer to hardware structure
1454 * Enable malicious driver detection
1456 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1460 DEBUGFUNC("ixgbe_enable_mdd_X550");
1462 /* Enable MDD for TX DMA and interrupt */
1463 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1464 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1465 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1467 /* Enable MDD for RX and interrupt */
1468 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1469 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1470 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1474 * ixgbe_restore_mdd_vf_X550
1475 * @hw: pointer to hardware structure
1478 * Restore VF that was disabled during malicious driver detection event
1480 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1482 u32 idx, reg, num_qs, start_q, bitmask;
1484 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1486 /* Map VF to queues */
1487 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1488 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1489 case IXGBE_MRQC_VMDQRT8TCEN:
1490 num_qs = 8; /* 16 VFs / pools */
1491 bitmask = 0x000000FF;
1493 case IXGBE_MRQC_VMDQRSS32EN:
1494 case IXGBE_MRQC_VMDQRT4TCEN:
1495 num_qs = 4; /* 32 VFs / pools */
1496 bitmask = 0x0000000F;
1498 default: /* 64 VFs / pools */
1500 bitmask = 0x00000003;
1503 start_q = vf * num_qs;
1505 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1508 reg |= (bitmask << (start_q % 32));
1509 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1510 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1514 * ixgbe_mdd_event_X550
1515 * @hw: pointer to hardware structure
1516 * @vf_bitmap: vf bitmap of malicious vfs
1518 * Handle malicious driver detection event.
1520 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1523 u32 i, j, reg, q, shift, vf, idx;
1525 DEBUGFUNC("ixgbe_mdd_event_X550");
1527 /* figure out pool size for mapping to vf's */
1528 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1529 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1530 case IXGBE_MRQC_VMDQRT8TCEN:
1531 shift = 3; /* 16 VFs / pools */
1533 case IXGBE_MRQC_VMDQRSS32EN:
1534 case IXGBE_MRQC_VMDQRT4TCEN:
1535 shift = 2; /* 32 VFs / pools */
1538 shift = 1; /* 64 VFs / pools */
1542 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1543 for (i = 0; i < 4; i++) {
1544 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1545 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1550 /* Get malicious queue */
1551 for (j = 0; j < 32 && wqbr; j++) {
1553 if (!(wqbr & (1 << j)))
1556 /* Get queue from bitmask */
1559 /* Map queue to vf */
1562 /* Set vf bit in vf_bitmap */
1564 vf_bitmap[idx] |= (1 << (vf % 32));
1571 * ixgbe_get_media_type_X550em - Get media type
1572 * @hw: pointer to hardware structure
1574 * Returns the media type (fiber, copper, backplane)
1576 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1578 enum ixgbe_media_type media_type;
1580 DEBUGFUNC("ixgbe_get_media_type_X550em");
1582 /* Detect if there is a copper PHY attached. */
1583 switch (hw->device_id) {
1584 case IXGBE_DEV_ID_X550EM_X_KR:
1585 case IXGBE_DEV_ID_X550EM_X_KX4:
1586 case IXGBE_DEV_ID_X550EM_X_XFI:
1587 case IXGBE_DEV_ID_X550EM_A_KR:
1588 case IXGBE_DEV_ID_X550EM_A_KR_L:
1589 media_type = ixgbe_media_type_backplane;
1591 case IXGBE_DEV_ID_X550EM_X_SFP:
1592 case IXGBE_DEV_ID_X550EM_A_SFP:
1593 case IXGBE_DEV_ID_X550EM_A_SFP_N:
1594 case IXGBE_DEV_ID_X550EM_A_QSFP:
1595 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1596 media_type = ixgbe_media_type_fiber;
1598 case IXGBE_DEV_ID_X550EM_X_1G_T:
1599 case IXGBE_DEV_ID_X550EM_X_10G_T:
1600 case IXGBE_DEV_ID_X550EM_A_10G_T:
1601 media_type = ixgbe_media_type_copper;
1603 case IXGBE_DEV_ID_X550EM_A_SGMII:
1604 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1605 media_type = ixgbe_media_type_backplane;
1606 hw->phy.type = ixgbe_phy_sgmii;
1608 case IXGBE_DEV_ID_X550EM_A_1G_T:
1609 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1610 media_type = ixgbe_media_type_copper;
1613 media_type = ixgbe_media_type_unknown;
1620 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1621 * @hw: pointer to hardware structure
1622 * @linear: true if SFP module is linear
1624 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1626 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1628 switch (hw->phy.sfp_type) {
1629 case ixgbe_sfp_type_not_present:
1630 return IXGBE_ERR_SFP_NOT_PRESENT;
1631 case ixgbe_sfp_type_da_cu_core0:
1632 case ixgbe_sfp_type_da_cu_core1:
1635 case ixgbe_sfp_type_srlr_core0:
1636 case ixgbe_sfp_type_srlr_core1:
1637 case ixgbe_sfp_type_da_act_lmt_core0:
1638 case ixgbe_sfp_type_da_act_lmt_core1:
1639 case ixgbe_sfp_type_1g_sx_core0:
1640 case ixgbe_sfp_type_1g_sx_core1:
1641 case ixgbe_sfp_type_1g_lx_core0:
1642 case ixgbe_sfp_type_1g_lx_core1:
1645 case ixgbe_sfp_type_unknown:
1646 case ixgbe_sfp_type_1g_cu_core0:
1647 case ixgbe_sfp_type_1g_cu_core1:
1649 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1652 return IXGBE_SUCCESS;
1656 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1657 * @hw: pointer to hardware structure
1659 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1661 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1666 DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1668 status = ixgbe_identify_module_generic(hw);
1670 if (status != IXGBE_SUCCESS)
1673 /* Check if SFP module is supported */
1674 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1680 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1681 * @hw: pointer to hardware structure
1683 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1688 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1690 /* Check if SFP module is supported */
1691 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1693 if (status != IXGBE_SUCCESS)
1696 ixgbe_init_mac_link_ops_X550em(hw);
1697 hw->phy.ops.reset = NULL;
1699 return IXGBE_SUCCESS;
1703 * ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1705 * @hw: pointer to hardware structure
1707 STATIC s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1712 /* Restart auto-negotiation. */
1713 status = hw->mac.ops.read_iosf_sb_reg(hw,
1714 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1715 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1718 DEBUGOUT("Auto-negotiation did not complete\n");
1722 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1723 status = hw->mac.ops.write_iosf_sb_reg(hw,
1724 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1725 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1727 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1730 /* Indicate to FW that AN restart has been asserted */
1731 status = hw->mac.ops.read_iosf_sb_reg(hw,
1732 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1733 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1736 DEBUGOUT("Auto-negotiation did not complete\n");
1740 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1741 status = hw->mac.ops.write_iosf_sb_reg(hw,
1742 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1743 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1750 * ixgbe_setup_sgmii - Set up link for sgmii
1751 * @hw: pointer to hardware structure
1753 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1756 struct ixgbe_mac_info *mac = &hw->mac;
1757 u32 lval, sval, flx_val;
1760 rc = mac->ops.read_iosf_sb_reg(hw,
1761 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1762 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1766 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1767 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1768 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1769 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1770 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1771 rc = mac->ops.write_iosf_sb_reg(hw,
1772 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1773 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1777 rc = mac->ops.read_iosf_sb_reg(hw,
1778 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1779 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1783 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1784 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1785 rc = mac->ops.write_iosf_sb_reg(hw,
1786 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1787 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1791 rc = mac->ops.read_iosf_sb_reg(hw,
1792 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1793 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1797 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1798 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1799 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1800 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1801 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1803 rc = mac->ops.write_iosf_sb_reg(hw,
1804 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1805 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1809 rc = ixgbe_restart_an_internal_phy_x550em(hw);
1813 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1817 * ixgbe_setup_sgmii_fw - Set up link for sgmii with firmware-controlled PHYs
1818 * @hw: pointer to hardware structure
1820 STATIC s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1823 struct ixgbe_mac_info *mac = &hw->mac;
1824 u32 lval, sval, flx_val;
1827 rc = mac->ops.read_iosf_sb_reg(hw,
1828 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1829 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1833 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1834 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1835 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1836 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1837 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1838 rc = mac->ops.write_iosf_sb_reg(hw,
1839 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1840 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1844 rc = mac->ops.read_iosf_sb_reg(hw,
1845 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1846 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1850 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1851 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1852 rc = mac->ops.write_iosf_sb_reg(hw,
1853 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1854 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1858 rc = mac->ops.write_iosf_sb_reg(hw,
1859 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1860 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1864 rc = mac->ops.read_iosf_sb_reg(hw,
1865 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1866 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1870 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1871 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
1872 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1873 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1874 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1876 rc = mac->ops.write_iosf_sb_reg(hw,
1877 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1878 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1882 rc = ixgbe_restart_an_internal_phy_x550em(hw);
1884 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1888 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1889 * @hw: pointer to hardware structure
1891 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1893 struct ixgbe_mac_info *mac = &hw->mac;
1895 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1897 switch (hw->mac.ops.get_media_type(hw)) {
1898 case ixgbe_media_type_fiber:
1899 /* CS4227 does not support autoneg, so disable the laser control
1900 * functions for SFP+ fiber
1902 mac->ops.disable_tx_laser = NULL;
1903 mac->ops.enable_tx_laser = NULL;
1904 mac->ops.flap_tx_laser = NULL;
1905 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1906 mac->ops.set_rate_select_speed =
1907 ixgbe_set_soft_rate_select_speed;
1909 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1910 (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1911 mac->ops.setup_mac_link =
1912 ixgbe_setup_mac_link_sfp_x550a;
1914 mac->ops.setup_mac_link =
1915 ixgbe_setup_mac_link_sfp_x550em;
1917 case ixgbe_media_type_copper:
1918 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1919 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
1920 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
1921 mac->ops.setup_link = ixgbe_setup_sgmii_fw;
1922 mac->ops.check_link =
1923 ixgbe_check_mac_link_generic;
1925 mac->ops.setup_link =
1926 ixgbe_setup_mac_link_t_X550em;
1929 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1930 mac->ops.check_link = ixgbe_check_link_t_X550em;
1933 case ixgbe_media_type_backplane:
1934 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1935 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1936 mac->ops.setup_link = ixgbe_setup_sgmii;
1944 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1945 * @hw: pointer to hardware structure
1946 * @speed: pointer to link speed
1947 * @autoneg: true when autoneg or autotry is enabled
1949 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1950 ixgbe_link_speed *speed,
1953 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1956 if (hw->phy.type == ixgbe_phy_fw) {
1958 *speed = hw->phy.speeds_supported;
1963 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1965 /* CS4227 SFP must not enable auto-negotiation */
1968 /* Check if 1G SFP module. */
1969 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1970 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1971 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1972 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1973 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1974 return IXGBE_SUCCESS;
1977 /* Link capabilities are based on SFP */
1978 if (hw->phy.multispeed_fiber)
1979 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1980 IXGBE_LINK_SPEED_1GB_FULL;
1982 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1984 switch (hw->phy.type) {
1985 case ixgbe_phy_ext_1g_t:
1986 case ixgbe_phy_sgmii:
1987 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1989 case ixgbe_phy_x550em_kr:
1990 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1991 /* check different backplane modes */
1992 if (hw->phy.nw_mng_if_sel &
1993 IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
1994 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
1996 } else if (hw->device_id ==
1997 IXGBE_DEV_ID_X550EM_A_KR_L) {
1998 *speed = IXGBE_LINK_SPEED_1GB_FULL;
2004 *speed = IXGBE_LINK_SPEED_10GB_FULL |
2005 IXGBE_LINK_SPEED_1GB_FULL;
2011 return IXGBE_SUCCESS;
2015 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
2016 * @hw: pointer to hardware structure
2017 * @lsc: pointer to boolean flag which indicates whether external Base T
2018 * PHY interrupt is lsc
2020 * Determime if external Base T PHY interrupt cause is high temperature
2021 * failure alarm or link status change.
2023 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2024 * failure alarm, else return PHY access status.
2026 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
2033 /* Vendor alarm triggered */
2034 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2035 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2038 if (status != IXGBE_SUCCESS ||
2039 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
2042 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
2043 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
2044 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2047 if (status != IXGBE_SUCCESS ||
2048 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2049 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
2052 /* Global alarm triggered */
2053 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
2054 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2057 if (status != IXGBE_SUCCESS)
2060 /* If high temperature failure, then return over temp error and exit */
2061 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
2062 /* power down the PHY in case the PHY FW didn't already */
2063 ixgbe_set_copper_phy_power(hw, false);
2064 return IXGBE_ERR_OVERTEMP;
2065 } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
2066 /* device fault alarm triggered */
2067 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
2068 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2071 if (status != IXGBE_SUCCESS)
2074 /* if device fault was due to high temp alarm handle and exit */
2075 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
2076 /* power down the PHY in case the PHY FW didn't */
2077 ixgbe_set_copper_phy_power(hw, false);
2078 return IXGBE_ERR_OVERTEMP;
2082 /* Vendor alarm 2 triggered */
2083 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2084 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
2086 if (status != IXGBE_SUCCESS ||
2087 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
2090 /* link connect/disconnect event occurred */
2091 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
2092 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
2094 if (status != IXGBE_SUCCESS)
2098 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2101 return IXGBE_SUCCESS;
2105 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2106 * @hw: pointer to hardware structure
2108 * Enable link status change and temperature failure alarm for the external
2111 * Returns PHY access status
2113 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2119 /* Clear interrupt flags */
2120 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2122 /* Enable link status change alarm */
2124 /* Enable the LASI interrupts on X552 devices to receive notifications
2125 * of the link configurations of the external PHY and correspondingly
2126 * support the configuration of the internal iXFI link, since iXFI does
2127 * not support auto-negotiation. This is not required for X553 devices
2128 * having KR support, which performs auto-negotiations and which is used
2129 * as the internal link to the external PHY. Hence adding a check here
2130 * to avoid enabling LASI interrupts for X553 devices.
2132 if (hw->mac.type != ixgbe_mac_X550EM_a) {
2133 status = hw->phy.ops.read_reg(hw,
2134 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2135 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
2137 if (status != IXGBE_SUCCESS)
2140 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2142 status = hw->phy.ops.write_reg(hw,
2143 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2144 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
2146 if (status != IXGBE_SUCCESS)
2150 /* Enable high temperature failure and global fault alarms */
2151 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2152 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2155 if (status != IXGBE_SUCCESS)
2158 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2159 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2161 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2162 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2165 if (status != IXGBE_SUCCESS)
2168 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2169 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2170 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2173 if (status != IXGBE_SUCCESS)
2176 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2177 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2179 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2180 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2183 if (status != IXGBE_SUCCESS)
2186 /* Enable chip-wide vendor alarm */
2187 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2188 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2191 if (status != IXGBE_SUCCESS)
2194 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2196 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2197 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2204 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2205 * @hw: pointer to hardware structure
2206 * @speed: link speed
2208 * Configures the integrated KR PHY.
2210 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2211 ixgbe_link_speed speed)
2216 status = hw->mac.ops.read_iosf_sb_reg(hw,
2217 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2218 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2222 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2223 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2224 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2226 /* Advertise 10G support. */
2227 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2228 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2230 /* Advertise 1G support. */
2231 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2232 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2234 status = hw->mac.ops.write_iosf_sb_reg(hw,
2235 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2236 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2238 if (hw->mac.type == ixgbe_mac_X550EM_a) {
2239 /* Set lane mode to KR auto negotiation */
2240 status = hw->mac.ops.read_iosf_sb_reg(hw,
2241 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2242 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2247 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2248 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2249 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2250 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2251 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2253 status = hw->mac.ops.write_iosf_sb_reg(hw,
2254 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2255 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2258 return ixgbe_restart_an_internal_phy_x550em(hw);
2262 * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs
2263 * @hw: pointer to hardware structure
2265 static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw)
2267 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
2270 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2271 return IXGBE_SUCCESS;
2273 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store);
2276 memset(store, 0, sizeof(store));
2278 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store);
2282 return ixgbe_setup_fw_link(hw);
2286 * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp
2287 * @hw: pointer to hardware structure
2289 static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw)
2291 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
2294 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store);
2298 if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) {
2299 ixgbe_shutdown_fw_phy(hw);
2300 return IXGBE_ERR_OVERTEMP;
2302 return IXGBE_SUCCESS;
2306 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2307 * @hw: pointer to hardware structure
2309 * Read NW_MNG_IF_SEL register and save field values, and check for valid field
2312 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2314 /* Save NW management interface connected on board. This is used
2315 * to determine internal PHY mode.
2317 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2319 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2320 * PHY address. This register field was has only been used for X552.
2322 if (hw->mac.type == ixgbe_mac_X550EM_a &&
2323 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2324 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2325 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2326 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2329 return IXGBE_SUCCESS;
2333 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2334 * @hw: pointer to hardware structure
2336 * Initialize any function pointers that were not able to be
2337 * set during init_shared_code because the PHY/SFP type was
2338 * not known. Perform the SFP init if necessary.
2340 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2342 struct ixgbe_phy_info *phy = &hw->phy;
2345 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2347 hw->mac.ops.set_lan_id(hw);
2348 ixgbe_read_mng_if_sel_x550em(hw);
2350 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2351 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2352 ixgbe_setup_mux_ctl(hw);
2353 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2356 switch (hw->device_id) {
2357 case IXGBE_DEV_ID_X550EM_A_1G_T:
2358 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2359 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2360 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2361 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2362 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2363 phy->ops.check_overtemp = ixgbe_check_overtemp_fw;
2365 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2367 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2370 case IXGBE_DEV_ID_X550EM_A_10G_T:
2371 case IXGBE_DEV_ID_X550EM_A_SFP:
2372 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2373 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2375 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2377 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2379 case IXGBE_DEV_ID_X550EM_X_SFP:
2380 /* set up for CS4227 usage */
2381 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2383 case IXGBE_DEV_ID_X550EM_X_1G_T:
2384 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2385 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2391 /* Identify the PHY or SFP module */
2392 ret_val = phy->ops.identify(hw);
2393 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED ||
2394 ret_val == IXGBE_ERR_PHY_ADDR_INVALID)
2397 /* Setup function pointers based on detected hardware */
2398 ixgbe_init_mac_link_ops_X550em(hw);
2399 if (phy->sfp_type != ixgbe_sfp_type_unknown)
2400 phy->ops.reset = NULL;
2402 /* Set functions pointers based on phy type */
2403 switch (hw->phy.type) {
2404 case ixgbe_phy_x550em_kx4:
2405 phy->ops.setup_link = NULL;
2406 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2407 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2409 case ixgbe_phy_x550em_kr:
2410 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2411 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2412 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2414 case ixgbe_phy_ext_1g_t:
2415 /* link is managed by FW */
2416 phy->ops.setup_link = NULL;
2418 case ixgbe_phy_x550em_xfi:
2419 /* link is managed by HW */
2420 phy->ops.setup_link = NULL;
2421 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2422 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2424 case ixgbe_phy_x550em_ext_t:
2425 /* If internal link mode is XFI, then setup iXFI internal link,
2426 * else setup KR now.
2428 phy->ops.setup_internal_link =
2429 ixgbe_setup_internal_phy_t_x550em;
2431 /* setup SW LPLU only for first revision of X550EM_x */
2432 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2433 !(IXGBE_FUSES0_REV_MASK &
2434 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2435 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2437 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2438 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2440 case ixgbe_phy_sgmii:
2441 phy->ops.setup_link = NULL;
2444 phy->ops.setup_link = ixgbe_setup_fw_link;
2445 phy->ops.reset = ixgbe_reset_phy_fw;
2454 * ixgbe_set_mdio_speed - Set MDIO clock speed
2455 * @hw: pointer to hardware structure
2457 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2461 switch (hw->device_id) {
2462 case IXGBE_DEV_ID_X550EM_X_10G_T:
2463 case IXGBE_DEV_ID_X550EM_A_SGMII:
2464 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2465 case IXGBE_DEV_ID_X550EM_A_10G_T:
2466 case IXGBE_DEV_ID_X550EM_A_SFP:
2467 case IXGBE_DEV_ID_X550EM_A_QSFP:
2468 /* Config MDIO clock speed before the first MDIO PHY access */
2469 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2470 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2471 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2473 case IXGBE_DEV_ID_X550EM_A_1G_T:
2474 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2475 /* Select fast MDIO clock speed for these devices */
2476 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2477 hlreg0 |= IXGBE_HLREG0_MDCSPD;
2478 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2486 * ixgbe_reset_hw_X550em - Perform hardware reset
2487 * @hw: pointer to hardware structure
2489 * Resets the hardware by resetting the transmit and receive units, masks
2490 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2493 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2495 ixgbe_link_speed link_speed;
2499 bool link_up = false;
2500 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2502 DEBUGFUNC("ixgbe_reset_hw_X550em");
2504 /* Call adapter stop to disable Tx/Rx and clear interrupts */
2505 status = hw->mac.ops.stop_adapter(hw);
2506 if (status != IXGBE_SUCCESS) {
2507 DEBUGOUT1("Failed to stop adapter, STATUS = %d\n", status);
2510 /* flush pending Tx transactions */
2511 ixgbe_clear_tx_pending(hw);
2513 ixgbe_set_mdio_speed(hw);
2515 /* PHY ops must be identified and initialized prior to reset */
2516 status = hw->phy.ops.init(hw);
2519 DEBUGOUT1("Failed to initialize PHY ops, STATUS = %d\n",
2522 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2523 DEBUGOUT("Returning from reset HW due to PHY init failure\n");
2527 /* start the external PHY */
2528 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2529 status = ixgbe_init_ext_t_x550em(hw);
2531 DEBUGOUT1("Failed to start the external PHY, STATUS = %d\n",
2537 /* Setup SFP module if there is one present. */
2538 if (hw->phy.sfp_setup_needed) {
2539 status = hw->mac.ops.setup_sfp(hw);
2540 hw->phy.sfp_setup_needed = false;
2543 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2547 if (!hw->phy.reset_disable && hw->phy.ops.reset) {
2548 if (hw->phy.ops.reset(hw) == IXGBE_ERR_OVERTEMP)
2549 return IXGBE_ERR_OVERTEMP;
2553 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
2554 * If link reset is used when link is up, it might reset the PHY when
2555 * mng is using it. If link is down or the flag to force full link
2556 * reset is set, then perform link reset.
2558 ctrl = IXGBE_CTRL_LNK_RST;
2559 if (!hw->force_full_reset) {
2560 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2562 ctrl = IXGBE_CTRL_RST;
2565 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
2566 if (status != IXGBE_SUCCESS) {
2567 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
2568 "semaphore failed with %d", status);
2569 return IXGBE_ERR_SWFW_SYNC;
2572 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2573 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2574 IXGBE_WRITE_FLUSH(hw);
2575 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2577 /* Poll for reset bit to self-clear meaning reset is complete */
2578 for (i = 0; i < 10; i++) {
2580 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2581 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2585 if (ctrl & IXGBE_CTRL_RST_MASK) {
2586 status = IXGBE_ERR_RESET_FAILED;
2587 DEBUGOUT("Reset polling failed to complete.\n");
2592 /* Double resets are required for recovery from certain error
2593 * conditions. Between resets, it is necessary to stall to
2594 * allow time for any pending HW events to complete.
2596 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2597 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2601 /* Store the permanent mac address */
2602 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2604 /* Store MAC address from RAR0, clear receive address registers, and
2605 * clear the multicast table. Also reset num_rar_entries to 128,
2606 * since we modify this value when programming the SAN MAC address.
2608 hw->mac.num_rar_entries = 128;
2609 hw->mac.ops.init_rx_addrs(hw);
2611 ixgbe_set_mdio_speed(hw);
2613 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2614 ixgbe_setup_mux_ctl(hw);
2616 if (status != IXGBE_SUCCESS)
2617 DEBUGOUT1("Reset HW failed, STATUS = %d\n", status);
2623 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2624 * @hw: pointer to hardware structure
2626 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2631 status = hw->phy.ops.read_reg(hw,
2632 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2633 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2636 if (status != IXGBE_SUCCESS)
2639 /* If PHY FW reset completed bit is set then this is the first
2640 * SW instance after a power on so the PHY FW must be un-stalled.
2642 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2643 status = hw->phy.ops.read_reg(hw,
2644 IXGBE_MDIO_GLOBAL_RES_PR_10,
2645 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2648 if (status != IXGBE_SUCCESS)
2651 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2653 status = hw->phy.ops.write_reg(hw,
2654 IXGBE_MDIO_GLOBAL_RES_PR_10,
2655 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2658 if (status != IXGBE_SUCCESS)
2666 * ixgbe_setup_kr_x550em - Configure the KR PHY.
2667 * @hw: pointer to hardware structure
2669 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2671 /* leave link alone for 2.5G */
2672 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL)
2673 return IXGBE_SUCCESS;
2675 if (ixgbe_check_reset_blocked(hw))
2678 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2682 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2683 * @hw: pointer to hardware structure
2685 * Configure the external PHY and the integrated KR PHY for SFP support.
2687 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2688 ixgbe_link_speed speed,
2689 bool autoneg_wait_to_complete)
2692 u16 reg_slice, reg_val;
2693 bool setup_linear = false;
2694 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2696 /* Check if SFP module is supported and linear */
2697 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2699 /* If no SFP module present, then return success. Return success since
2700 * there is no reason to configure CS4227 and SFP not present error is
2701 * not excepted in the setup MAC link flow.
2703 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2704 return IXGBE_SUCCESS;
2706 if (ret_val != IXGBE_SUCCESS)
2709 /* Configure internal PHY for KR/KX. */
2710 ixgbe_setup_kr_speed_x550em(hw, speed);
2712 /* Configure CS4227 LINE side to proper mode. */
2713 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2714 (hw->bus.lan_id << 12);
2716 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2718 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2719 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2725 * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
2726 * @hw: pointer to hardware structure
2727 * @speed: the link speed to force
2729 * Configures the integrated PHY for native SFI mode. Used to connect the
2730 * internal PHY directly to an SFP cage, without autonegotiation.
2732 STATIC s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2734 struct ixgbe_mac_info *mac = &hw->mac;
2738 /* Disable all AN and force speed to 10G Serial. */
2739 status = mac->ops.read_iosf_sb_reg(hw,
2740 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2741 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2742 if (status != IXGBE_SUCCESS)
2745 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2746 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2747 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2748 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2750 /* Select forced link speed for internal PHY. */
2752 case IXGBE_LINK_SPEED_10GB_FULL:
2753 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
2755 case IXGBE_LINK_SPEED_1GB_FULL:
2756 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2759 /* Other link speeds are not supported by internal PHY. */
2760 return IXGBE_ERR_LINK_SETUP;
2763 status = mac->ops.write_iosf_sb_reg(hw,
2764 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2765 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2767 /* Toggle port SW reset by AN reset. */
2768 status = ixgbe_restart_an_internal_phy_x550em(hw);
2774 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2775 * @hw: pointer to hardware structure
2777 * Configure the the integrated PHY for SFP support.
2779 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2780 ixgbe_link_speed speed,
2781 bool autoneg_wait_to_complete)
2785 bool setup_linear = false;
2786 u32 reg_slice, reg_phy_int, slice_offset;
2788 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2790 /* Check if SFP module is supported and linear */
2791 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2793 /* If no SFP module present, then return success. Return success since
2794 * SFP not present error is not excepted in the setup MAC link flow.
2796 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2797 return IXGBE_SUCCESS;
2799 if (ret_val != IXGBE_SUCCESS)
2802 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2803 /* Configure internal PHY for native SFI based on module type */
2804 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2805 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2806 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int);
2808 if (ret_val != IXGBE_SUCCESS)
2811 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
2813 reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
2815 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2816 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2817 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2819 if (ret_val != IXGBE_SUCCESS)
2822 /* Setup SFI internal link. */
2823 ret_val = ixgbe_setup_sfi_x550a(hw, &speed);
2825 /* Configure internal PHY for KR/KX. */
2826 ixgbe_setup_kr_speed_x550em(hw, speed);
2828 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2830 DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2831 return IXGBE_ERR_PHY_ADDR_INVALID;
2834 /* Get external PHY SKU id */
2835 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,
2836 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
2838 if (ret_val != IXGBE_SUCCESS)
2841 /* When configuring quad port CS4223, the MAC instance is part
2842 * of the slice offset.
2844 if (reg_phy_ext == IXGBE_CS4223_SKU_ID)
2845 slice_offset = (hw->bus.lan_id +
2846 (hw->bus.instance_id << 1)) << 12;
2848 slice_offset = hw->bus.lan_id << 12;
2850 /* Configure CS4227/CS4223 LINE side to proper mode. */
2851 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2853 ret_val = hw->phy.ops.read_reg(hw, reg_slice,
2854 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
2856 if (ret_val != IXGBE_SUCCESS)
2859 reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) |
2860 (IXGBE_CS4227_EDC_MODE_SR << 1));
2863 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2865 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2866 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2867 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2869 /* Flush previous write with a read */
2870 ret_val = hw->phy.ops.read_reg(hw, reg_slice,
2871 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
2877 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2878 * @hw: pointer to hardware structure
2880 * iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2882 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2884 struct ixgbe_mac_info *mac = &hw->mac;
2888 /* Disable training protocol FSM. */
2889 status = mac->ops.read_iosf_sb_reg(hw,
2890 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2891 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2892 if (status != IXGBE_SUCCESS)
2894 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2895 status = mac->ops.write_iosf_sb_reg(hw,
2896 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2897 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2898 if (status != IXGBE_SUCCESS)
2901 /* Disable Flex from training TXFFE. */
2902 status = mac->ops.read_iosf_sb_reg(hw,
2903 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2904 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2905 if (status != IXGBE_SUCCESS)
2907 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2908 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2909 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2910 status = mac->ops.write_iosf_sb_reg(hw,
2911 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2912 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2913 if (status != IXGBE_SUCCESS)
2915 status = mac->ops.read_iosf_sb_reg(hw,
2916 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2917 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2918 if (status != IXGBE_SUCCESS)
2920 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2921 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2922 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2923 status = mac->ops.write_iosf_sb_reg(hw,
2924 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2925 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2926 if (status != IXGBE_SUCCESS)
2929 /* Enable override for coefficients. */
2930 status = mac->ops.read_iosf_sb_reg(hw,
2931 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2932 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2933 if (status != IXGBE_SUCCESS)
2935 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2936 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2937 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2938 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2939 status = mac->ops.write_iosf_sb_reg(hw,
2940 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2941 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2946 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2947 * @hw: pointer to hardware structure
2948 * @speed: the link speed to force
2950 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
2951 * internal and external PHY at a specific speed, without autonegotiation.
2953 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2955 struct ixgbe_mac_info *mac = &hw->mac;
2959 /* iXFI is only supported with X552 */
2960 if (mac->type != ixgbe_mac_X550EM_x)
2961 return IXGBE_ERR_LINK_SETUP;
2963 /* Disable AN and force speed to 10G Serial. */
2964 status = mac->ops.read_iosf_sb_reg(hw,
2965 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2966 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2967 if (status != IXGBE_SUCCESS)
2970 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2971 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2973 /* Select forced link speed for internal PHY. */
2975 case IXGBE_LINK_SPEED_10GB_FULL:
2976 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2978 case IXGBE_LINK_SPEED_1GB_FULL:
2979 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2982 /* Other link speeds are not supported by internal KR PHY. */
2983 return IXGBE_ERR_LINK_SETUP;
2986 status = mac->ops.write_iosf_sb_reg(hw,
2987 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2988 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2989 if (status != IXGBE_SUCCESS)
2992 /* Additional configuration needed for x550em_x */
2993 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2994 status = ixgbe_setup_ixfi_x550em_x(hw);
2995 if (status != IXGBE_SUCCESS)
2999 /* Toggle port SW reset by AN reset. */
3000 status = ixgbe_restart_an_internal_phy_x550em(hw);
3006 * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
3007 * @hw: address of hardware structure
3008 * @link_up: address of boolean to indicate link status
3010 * Returns error code if unable to get link status.
3012 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
3019 /* read this twice back to back to indicate current status */
3020 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3021 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3023 if (ret != IXGBE_SUCCESS)
3026 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3027 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3029 if (ret != IXGBE_SUCCESS)
3032 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
3034 return IXGBE_SUCCESS;
3038 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
3039 * @hw: point to hardware structure
3041 * Configures the link between the integrated KR PHY and the external X557 PHY
3042 * The driver will call this function when it gets a link status change
3043 * interrupt from the X557 PHY. This function configures the link speed
3044 * between the PHYs to match the link speed of the BASE-T link.
3046 * A return of a non-zero value indicates an error, and the base driver should
3047 * not report link up.
3049 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
3051 ixgbe_link_speed force_speed;
3056 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3057 return IXGBE_ERR_CONFIG;
3059 if (hw->mac.type == ixgbe_mac_X550EM_x &&
3060 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3061 /* If link is down, there is no setup necessary so return */
3062 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3063 if (status != IXGBE_SUCCESS)
3067 return IXGBE_SUCCESS;
3069 status = hw->phy.ops.read_reg(hw,
3070 IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3071 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3073 if (status != IXGBE_SUCCESS)
3076 /* If link is still down - no setup is required so return */
3077 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3078 if (status != IXGBE_SUCCESS)
3081 return IXGBE_SUCCESS;
3083 /* clear everything but the speed and duplex bits */
3084 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
3087 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
3088 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3090 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
3091 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3094 /* Internal PHY does not support anything else */
3095 return IXGBE_ERR_INVALID_LINK_SETTINGS;
3098 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
3100 speed = IXGBE_LINK_SPEED_10GB_FULL |
3101 IXGBE_LINK_SPEED_1GB_FULL;
3102 return ixgbe_setup_kr_speed_x550em(hw, speed);
3107 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
3108 * @hw: pointer to hardware structure
3110 * Configures the integrated KR PHY to use internal loopback mode.
3112 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
3117 /* Disable AN and force speed to 10G Serial. */
3118 status = hw->mac.ops.read_iosf_sb_reg(hw,
3119 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3120 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3121 if (status != IXGBE_SUCCESS)
3123 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3124 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3125 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3126 status = hw->mac.ops.write_iosf_sb_reg(hw,
3127 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3128 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3129 if (status != IXGBE_SUCCESS)
3132 /* Set near-end loopback clocks. */
3133 status = hw->mac.ops.read_iosf_sb_reg(hw,
3134 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3135 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3136 if (status != IXGBE_SUCCESS)
3138 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3139 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3140 status = hw->mac.ops.write_iosf_sb_reg(hw,
3141 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3142 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3143 if (status != IXGBE_SUCCESS)
3146 /* Set loopback enable. */
3147 status = hw->mac.ops.read_iosf_sb_reg(hw,
3148 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3149 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3150 if (status != IXGBE_SUCCESS)
3152 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3153 status = hw->mac.ops.write_iosf_sb_reg(hw,
3154 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3155 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3156 if (status != IXGBE_SUCCESS)
3159 /* Training bypass. */
3160 status = hw->mac.ops.read_iosf_sb_reg(hw,
3161 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3162 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3163 if (status != IXGBE_SUCCESS)
3165 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3166 status = hw->mac.ops.write_iosf_sb_reg(hw,
3167 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3168 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3174 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3175 * assuming that the semaphore is already obtained.
3176 * @hw: pointer to hardware structure
3177 * @offset: offset of word in the EEPROM to read
3178 * @data: word read from the EEPROM
3180 * Reads a 16 bit word from the EEPROM using the hostif.
3182 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
3184 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3185 struct ixgbe_hic_read_shadow_ram buffer;
3188 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3189 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3190 buffer.hdr.req.buf_lenh = 0;
3191 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3192 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3194 /* convert offset from words to bytes */
3195 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3197 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3199 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3203 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3204 IXGBE_HI_COMMAND_TIMEOUT);
3206 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3207 FW_NVM_DATA_OFFSET);
3210 hw->mac.ops.release_swfw_sync(hw, mask);
3215 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3216 * @hw: pointer to hardware structure
3217 * @offset: offset of word in the EEPROM to read
3218 * @words: number of words
3219 * @data: word(s) read from the EEPROM
3221 * Reads a 16 bit word(s) from the EEPROM using the hostif.
3223 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3224 u16 offset, u16 words, u16 *data)
3226 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3227 struct ixgbe_hic_read_shadow_ram buffer;
3228 u32 current_word = 0;
3233 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3235 /* Take semaphore for the entire operation. */
3236 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3238 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3243 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3244 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3246 words_to_read = words;
3248 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3249 buffer.hdr.req.buf_lenh = 0;
3250 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3251 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3253 /* convert offset from words to bytes */
3254 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3255 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3257 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3258 IXGBE_HI_COMMAND_TIMEOUT);
3261 DEBUGOUT("Host interface command failed\n");
3265 for (i = 0; i < words_to_read; i++) {
3266 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3268 u32 value = IXGBE_READ_REG(hw, reg);
3270 data[current_word] = (u16)(value & 0xffff);
3273 if (i < words_to_read) {
3275 data[current_word] = (u16)(value & 0xffff);
3279 words -= words_to_read;
3283 hw->mac.ops.release_swfw_sync(hw, mask);
3288 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3289 * @hw: pointer to hardware structure
3290 * @offset: offset of word in the EEPROM to write
3291 * @data: word write to the EEPROM
3293 * Write a 16 bit word to the EEPROM using the hostif.
3295 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3299 struct ixgbe_hic_write_shadow_ram buffer;
3301 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3303 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3304 buffer.hdr.req.buf_lenh = 0;
3305 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3306 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3309 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3311 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3313 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3315 IXGBE_HI_COMMAND_TIMEOUT, false);
3321 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3322 * @hw: pointer to hardware structure
3323 * @offset: offset of word in the EEPROM to write
3324 * @data: word write to the EEPROM
3326 * Write a 16 bit word to the EEPROM using the hostif.
3328 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3331 s32 status = IXGBE_SUCCESS;
3333 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3335 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3337 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3338 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3340 DEBUGOUT("write ee hostif failed to get semaphore");
3341 status = IXGBE_ERR_SWFW_SYNC;
3348 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3349 * @hw: pointer to hardware structure
3350 * @offset: offset of word in the EEPROM to write
3351 * @words: number of words
3352 * @data: word(s) write to the EEPROM
3354 * Write a 16 bit word(s) to the EEPROM using the hostif.
3356 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3357 u16 offset, u16 words, u16 *data)
3359 s32 status = IXGBE_SUCCESS;
3362 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3364 /* Take semaphore for the entire operation. */
3365 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3366 if (status != IXGBE_SUCCESS) {
3367 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3371 for (i = 0; i < words; i++) {
3372 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3375 if (status != IXGBE_SUCCESS) {
3376 DEBUGOUT("Eeprom buffered write failed\n");
3381 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3388 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3389 * @hw: pointer to hardware structure
3390 * @ptr: pointer offset in eeprom
3391 * @size: size of section pointed by ptr, if 0 first word will be used as size
3392 * @csum: address of checksum to update
3394 * Returns error status for any failure
3396 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3397 u16 size, u16 *csum, u16 *buffer,
3402 u16 length, bufsz, i, start;
3405 bufsz = sizeof(buf) / sizeof(buf[0]);
3407 /* Read a chunk at the pointer location */
3409 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3411 DEBUGOUT("Failed to read EEPROM image\n");
3416 if (buffer_size < ptr)
3417 return IXGBE_ERR_PARAM;
3418 local_buffer = &buffer[ptr];
3426 length = local_buffer[0];
3428 /* Skip pointer section if length is invalid. */
3429 if (length == 0xFFFF || length == 0 ||
3430 (ptr + length) >= hw->eeprom.word_size)
3431 return IXGBE_SUCCESS;
3434 if (buffer && ((u32)start + (u32)length > buffer_size))
3435 return IXGBE_ERR_PARAM;
3437 for (i = start; length; i++, length--) {
3438 if (i == bufsz && !buffer) {
3444 /* Read a chunk at the pointer location */
3445 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3448 DEBUGOUT("Failed to read EEPROM image\n");
3452 *csum += local_buffer[i];
3454 return IXGBE_SUCCESS;
3458 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3459 * @hw: pointer to hardware structure
3460 * @buffer: pointer to buffer containing calculated checksum
3461 * @buffer_size: size of buffer
3463 * Returns a negative error code on error, or the 16-bit checksum
3465 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3467 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3471 u16 pointer, i, size;
3473 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3475 hw->eeprom.ops.init_params(hw);
3478 /* Read pointer area */
3479 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3480 IXGBE_EEPROM_LAST_WORD + 1,
3483 DEBUGOUT("Failed to read EEPROM image\n");
3486 local_buffer = eeprom_ptrs;
3488 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3489 return IXGBE_ERR_PARAM;
3490 local_buffer = buffer;
3494 * For X550 hardware include 0x0-0x41 in the checksum, skip the
3495 * checksum word itself
3497 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3498 if (i != IXGBE_EEPROM_CHECKSUM)
3499 checksum += local_buffer[i];
3502 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
3503 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3505 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3506 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3509 pointer = local_buffer[i];
3511 /* Skip pointer section if the pointer is invalid. */
3512 if (pointer == 0xFFFF || pointer == 0 ||
3513 pointer >= hw->eeprom.word_size)
3517 case IXGBE_PCIE_GENERAL_PTR:
3518 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3520 case IXGBE_PCIE_CONFIG0_PTR:
3521 case IXGBE_PCIE_CONFIG1_PTR:
3522 size = IXGBE_PCIE_CONFIG_SIZE;
3529 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3530 buffer, buffer_size);
3535 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3537 return (s32)checksum;
3541 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3542 * @hw: pointer to hardware structure
3544 * Returns a negative error code on error, or the 16-bit checksum
3546 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3548 return ixgbe_calc_checksum_X550(hw, NULL, 0);
3552 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3553 * @hw: pointer to hardware structure
3554 * @checksum_val: calculated checksum
3556 * Performs checksum calculation and validates the EEPROM checksum. If the
3557 * caller does not need checksum_val, the value can be NULL.
3559 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3563 u16 read_checksum = 0;
3565 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3567 /* Read the first word from the EEPROM. If this times out or fails, do
3568 * not continue or we could be in for a very long wait while every
3571 status = hw->eeprom.ops.read(hw, 0, &checksum);
3573 DEBUGOUT("EEPROM read failed\n");
3577 status = hw->eeprom.ops.calc_checksum(hw);
3581 checksum = (u16)(status & 0xffff);
3583 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3588 /* Verify read checksum from EEPROM is the same as
3589 * calculated checksum
3591 if (read_checksum != checksum) {
3592 status = IXGBE_ERR_EEPROM_CHECKSUM;
3593 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3594 "Invalid EEPROM checksum");
3597 /* If the user cares, return the calculated checksum */
3599 *checksum_val = checksum;
3605 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3606 * @hw: pointer to hardware structure
3608 * After writing EEPROM to shadow RAM using EEWR register, software calculates
3609 * checksum and updates the EEPROM and instructs the hardware to update
3612 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3617 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3619 /* Read the first word from the EEPROM. If this times out or fails, do
3620 * not continue or we could be in for a very long wait while every
3623 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3625 DEBUGOUT("EEPROM read failed\n");
3629 status = ixgbe_calc_eeprom_checksum_X550(hw);
3633 checksum = (u16)(status & 0xffff);
3635 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3640 status = ixgbe_update_flash_X550(hw);
3646 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3647 * @hw: pointer to hardware structure
3649 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3651 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3653 s32 status = IXGBE_SUCCESS;
3654 union ixgbe_hic_hdr2 buffer;
3656 DEBUGFUNC("ixgbe_update_flash_X550");
3658 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3659 buffer.req.buf_lenh = 0;
3660 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3661 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3663 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3665 IXGBE_HI_COMMAND_TIMEOUT, false);
3671 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3672 * @hw: pointer to hardware structure
3674 * Determines physical layer capabilities of the current configuration.
3676 u64 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3678 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3679 u16 ext_ability = 0;
3681 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3683 hw->phy.ops.identify(hw);
3685 switch (hw->phy.type) {
3686 case ixgbe_phy_x550em_kr:
3687 if (hw->mac.type == ixgbe_mac_X550EM_a) {
3688 if (hw->phy.nw_mng_if_sel &
3689 IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
3691 IXGBE_PHYSICAL_LAYER_2500BASE_KX;
3693 } else if (hw->device_id ==
3694 IXGBE_DEV_ID_X550EM_A_KR_L) {
3696 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3701 case ixgbe_phy_x550em_xfi:
3702 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3703 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3705 case ixgbe_phy_x550em_kx4:
3706 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3707 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3709 case ixgbe_phy_x550em_ext_t:
3710 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3711 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3713 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3714 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3715 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3716 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3719 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_1GB_FULL)
3720 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3721 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_100_FULL)
3722 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
3723 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_10_FULL)
3724 physical_layer |= IXGBE_PHYSICAL_LAYER_10BASE_T;
3726 case ixgbe_phy_sgmii:
3727 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3729 case ixgbe_phy_ext_1g_t:
3730 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3736 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3737 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3739 return physical_layer;
3743 * ixgbe_get_bus_info_x550em - Set PCI bus info
3744 * @hw: pointer to hardware structure
3746 * Sets bus link width and speed to unknown because X550em is
3749 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3752 DEBUGFUNC("ixgbe_get_bus_info_x550em");
3754 hw->bus.width = ixgbe_bus_width_unknown;
3755 hw->bus.speed = ixgbe_bus_speed_unknown;
3757 hw->mac.ops.set_lan_id(hw);
3759 return IXGBE_SUCCESS;
3763 * ixgbe_disable_rx_x550 - Disable RX unit
3765 * Enables the Rx DMA unit for x550
3767 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3769 u32 rxctrl, pfdtxgswc;
3771 struct ixgbe_hic_disable_rxen fw_cmd;
3773 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3775 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3776 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3777 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3778 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3779 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3780 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3781 hw->mac.set_lben = true;
3783 hw->mac.set_lben = false;
3786 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3787 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3788 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3789 fw_cmd.port_number = (u8)hw->bus.lan_id;
3791 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3792 sizeof(struct ixgbe_hic_disable_rxen),
3793 IXGBE_HI_COMMAND_TIMEOUT, true);
3795 /* If we fail - disable RX using register write */
3797 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3798 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3799 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3800 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3807 * ixgbe_enter_lplu_x550em - Transition to low power states
3808 * @hw: pointer to hardware structure
3810 * Configures Low Power Link Up on transition to low power states
3811 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3812 * X557 PHY immediately prior to entering LPLU.
3814 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3816 u16 an_10g_cntl_reg, autoneg_reg, speed;
3818 ixgbe_link_speed lcd_speed;
3822 /* SW LPLU not required on later HW revisions. */
3823 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3824 (IXGBE_FUSES0_REV_MASK &
3825 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3826 return IXGBE_SUCCESS;
3828 /* If blocked by MNG FW, then don't restart AN */
3829 if (ixgbe_check_reset_blocked(hw))
3830 return IXGBE_SUCCESS;
3832 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3833 if (status != IXGBE_SUCCESS)
3836 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3838 if (status != IXGBE_SUCCESS)
3841 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3842 * disabled, then force link down by entering low power mode.
3844 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3845 !(hw->wol_enabled || ixgbe_mng_present(hw)))
3846 return ixgbe_set_copper_phy_power(hw, FALSE);
3849 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3851 if (status != IXGBE_SUCCESS)
3854 /* If no valid LCD link speed, then force link down and exit. */
3855 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3856 return ixgbe_set_copper_phy_power(hw, FALSE);
3858 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3859 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3862 if (status != IXGBE_SUCCESS)
3865 /* If no link now, speed is invalid so take link down */
3866 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3867 if (status != IXGBE_SUCCESS)
3868 return ixgbe_set_copper_phy_power(hw, false);
3870 /* clear everything but the speed bits */
3871 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3873 /* If current speed is already LCD, then exit. */
3874 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3875 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3876 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3877 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3880 /* Clear AN completed indication */
3881 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3882 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3885 if (status != IXGBE_SUCCESS)
3888 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3889 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3892 if (status != IXGBE_SUCCESS)
3895 status = hw->phy.ops.read_reg(hw,
3896 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3897 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3900 if (status != IXGBE_SUCCESS)
3903 save_autoneg = hw->phy.autoneg_advertised;
3905 /* Setup link at least common link speed */
3906 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3908 /* restore autoneg from before setting lplu speed */
3909 hw->phy.autoneg_advertised = save_autoneg;
3915 * ixgbe_get_lcd_x550em - Determine lowest common denominator
3916 * @hw: pointer to hardware structure
3917 * @lcd_speed: pointer to lowest common link speed
3919 * Determine lowest common link speed with link partner.
3921 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3925 u16 word = hw->eeprom.ctrl_word_3;
3927 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3929 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3930 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3933 if (status != IXGBE_SUCCESS)
3936 /* If link partner advertised 1G, return 1G */
3937 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3938 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3942 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3943 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3944 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3947 /* Link partner not capable of lower speeds, return 10G */
3948 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3953 * ixgbe_setup_fc_X550em - Set up flow control
3954 * @hw: pointer to hardware structure
3956 * Called at init time to set up flow control.
3958 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3960 s32 ret_val = IXGBE_SUCCESS;
3961 u32 pause, asm_dir, reg_val;
3963 DEBUGFUNC("ixgbe_setup_fc_X550em");
3965 /* Validate the requested mode */
3966 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3967 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3968 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3969 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3973 /* 10gig parts do not have a word in the EEPROM to determine the
3974 * default flow control setting, so we explicitly set it to full.
3976 if (hw->fc.requested_mode == ixgbe_fc_default)
3977 hw->fc.requested_mode = ixgbe_fc_full;
3979 /* Determine PAUSE and ASM_DIR bits. */
3980 switch (hw->fc.requested_mode) {
3985 case ixgbe_fc_tx_pause:
3989 case ixgbe_fc_rx_pause:
3990 /* Rx Flow control is enabled and Tx Flow control is
3991 * disabled by software override. Since there really
3992 * isn't a way to advertise that we are capable of RX
3993 * Pause ONLY, we will advertise that we support both
3994 * symmetric and asymmetric Rx PAUSE, as such we fall
3995 * through to the fc_full statement. Later, we will
3996 * disable the adapter's ability to send PAUSE frames.
4003 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4004 "Flow control param set incorrectly\n");
4005 ret_val = IXGBE_ERR_CONFIG;
4009 switch (hw->device_id) {
4010 case IXGBE_DEV_ID_X550EM_X_KR:
4011 case IXGBE_DEV_ID_X550EM_A_KR:
4012 case IXGBE_DEV_ID_X550EM_A_KR_L:
4013 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
4014 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4015 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
4016 if (ret_val != IXGBE_SUCCESS)
4018 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4019 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4021 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4023 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4024 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
4025 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4026 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
4028 /* This device does not fully support AN. */
4029 hw->fc.disable_fc_autoneg = true;
4031 case IXGBE_DEV_ID_X550EM_X_XFI:
4032 hw->fc.disable_fc_autoneg = true;
4043 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
4044 * @hw: pointer to hardware structure
4046 * Enable flow control according to IEEE clause 37.
4048 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
4050 u32 link_s1, lp_an_page_low, an_cntl_1;
4051 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4052 ixgbe_link_speed speed;
4055 /* AN should have completed when the cable was plugged in.
4056 * Look for reasons to bail out. Bail out if:
4057 * - FC autoneg is disabled, or if
4060 if (hw->fc.disable_fc_autoneg) {
4061 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4062 "Flow control autoneg is disabled");
4066 hw->mac.ops.check_link(hw, &speed, &link_up, false);
4068 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4072 /* Check at auto-negotiation has completed */
4073 status = hw->mac.ops.read_iosf_sb_reg(hw,
4074 IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4075 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4077 if (status != IXGBE_SUCCESS ||
4078 (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4079 DEBUGOUT("Auto-Negotiation did not complete\n");
4080 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4084 /* Read the 10g AN autoc and LP ability registers and resolve
4085 * local flow control settings accordingly
4087 status = hw->mac.ops.read_iosf_sb_reg(hw,
4088 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4089 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
4091 if (status != IXGBE_SUCCESS) {
4092 DEBUGOUT("Auto-Negotiation did not complete\n");
4096 status = hw->mac.ops.read_iosf_sb_reg(hw,
4097 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
4098 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
4100 if (status != IXGBE_SUCCESS) {
4101 DEBUGOUT("Auto-Negotiation did not complete\n");
4105 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
4106 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
4107 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
4108 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
4109 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
4112 if (status == IXGBE_SUCCESS) {
4113 hw->fc.fc_was_autonegged = true;
4115 hw->fc.fc_was_autonegged = false;
4116 hw->fc.current_mode = hw->fc.requested_mode;
4121 * ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
4122 * @hw: pointer to hardware structure
4125 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
4127 hw->fc.fc_was_autonegged = false;
4128 hw->fc.current_mode = hw->fc.requested_mode;
4132 * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
4133 * @hw: pointer to hardware structure
4135 * Enable flow control according to IEEE clause 37.
4137 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
4139 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4140 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
4141 ixgbe_link_speed speed;
4144 /* AN should have completed when the cable was plugged in.
4145 * Look for reasons to bail out. Bail out if:
4146 * - FC autoneg is disabled, or if
4149 if (hw->fc.disable_fc_autoneg) {
4150 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4151 "Flow control autoneg is disabled");
4155 hw->mac.ops.check_link(hw, &speed, &link_up, false);
4157 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4161 /* Check if auto-negotiation has completed */
4162 status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info);
4163 if (status != IXGBE_SUCCESS ||
4164 !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) {
4165 DEBUGOUT("Auto-Negotiation did not complete\n");
4166 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4170 /* Negotiate the flow control */
4171 status = ixgbe_negotiate_fc(hw, info[0], info[0],
4172 FW_PHY_ACT_GET_LINK_INFO_FC_RX,
4173 FW_PHY_ACT_GET_LINK_INFO_FC_TX,
4174 FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX,
4175 FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX);
4178 if (status == IXGBE_SUCCESS) {
4179 hw->fc.fc_was_autonegged = true;
4181 hw->fc.fc_was_autonegged = false;
4182 hw->fc.current_mode = hw->fc.requested_mode;
4187 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4188 * @hw: pointer to hardware structure
4190 * Called at init time to set up flow control.
4192 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4194 s32 status = IXGBE_SUCCESS;
4197 DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4199 /* Validate the requested mode */
4200 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4201 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4202 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4203 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4206 if (hw->fc.requested_mode == ixgbe_fc_default)
4207 hw->fc.requested_mode = ixgbe_fc_full;
4209 /* Set up the 1G and 10G flow control advertisement registers so the
4210 * HW will be able to do FC autoneg once the cable is plugged in. If
4211 * we link at 10G, the 1G advertisement is harmless and vice versa.
4213 status = hw->mac.ops.read_iosf_sb_reg(hw,
4214 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4215 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4217 if (status != IXGBE_SUCCESS) {
4218 DEBUGOUT("Auto-Negotiation did not complete\n");
4222 /* The possible values of fc.requested_mode are:
4223 * 0: Flow control is completely disabled
4224 * 1: Rx flow control is enabled (we can receive pause frames,
4225 * but not send pause frames).
4226 * 2: Tx flow control is enabled (we can send pause frames but
4227 * we do not support receiving pause frames).
4228 * 3: Both Rx and Tx flow control (symmetric) are enabled.
4231 switch (hw->fc.requested_mode) {
4233 /* Flow control completely disabled by software override. */
4234 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4235 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4237 case ixgbe_fc_tx_pause:
4238 /* Tx Flow control is enabled, and Rx Flow control is
4239 * disabled by software override.
4241 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4242 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4244 case ixgbe_fc_rx_pause:
4245 /* Rx Flow control is enabled and Tx Flow control is
4246 * disabled by software override. Since there really
4247 * isn't a way to advertise that we are capable of RX
4248 * Pause ONLY, we will advertise that we support both
4249 * symmetric and asymmetric Rx PAUSE, as such we fall
4250 * through to the fc_full statement. Later, we will
4251 * disable the adapter's ability to send PAUSE frames.
4254 /* Flow control (both Rx and Tx) is enabled by SW override. */
4255 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4256 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4259 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4260 "Flow control param set incorrectly\n");
4261 return IXGBE_ERR_CONFIG;
4264 status = hw->mac.ops.write_iosf_sb_reg(hw,
4265 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4266 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4268 /* Restart auto-negotiation. */
4269 status = ixgbe_restart_an_internal_phy_x550em(hw);
4275 * ixgbe_set_mux - Set mux for port 1 access with CS4227
4276 * @hw: pointer to hardware structure
4277 * @state: set mux if 1, clear if 0
4279 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4283 if (!hw->bus.lan_id)
4285 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4287 esdp |= IXGBE_ESDP_SDP1;
4289 esdp &= ~IXGBE_ESDP_SDP1;
4290 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4291 IXGBE_WRITE_FLUSH(hw);
4295 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4296 * @hw: pointer to hardware structure
4297 * @mask: Mask to specify which semaphore to acquire
4299 * Acquires the SWFW semaphore and sets the I2C MUX
4301 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4305 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4307 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4311 if (mask & IXGBE_GSSR_I2C_MASK)
4312 ixgbe_set_mux(hw, 1);
4314 return IXGBE_SUCCESS;
4318 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4319 * @hw: pointer to hardware structure
4320 * @mask: Mask to specify which semaphore to release
4322 * Releases the SWFW semaphore and sets the I2C MUX
4324 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4326 DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4328 if (mask & IXGBE_GSSR_I2C_MASK)
4329 ixgbe_set_mux(hw, 0);
4331 ixgbe_release_swfw_sync_X540(hw, mask);
4335 * ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4336 * @hw: pointer to hardware structure
4337 * @mask: Mask to specify which semaphore to acquire
4339 * Acquires the SWFW semaphore and get the shared phy token as needed
4341 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4343 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4344 int retries = FW_PHY_TOKEN_RETRIES;
4345 s32 status = IXGBE_SUCCESS;
4347 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4350 status = IXGBE_SUCCESS;
4352 status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4354 DEBUGOUT1("Could not acquire SWFW semaphore, Status = %d\n",
4358 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4359 return IXGBE_SUCCESS;
4361 status = ixgbe_get_phy_token(hw);
4362 if (status == IXGBE_ERR_TOKEN_RETRY)
4363 DEBUGOUT1("Could not acquire PHY token, Status = %d\n",
4366 if (status == IXGBE_SUCCESS)
4367 return IXGBE_SUCCESS;
4370 ixgbe_release_swfw_sync_X540(hw, hmask);
4372 if (status != IXGBE_ERR_TOKEN_RETRY) {
4373 DEBUGOUT1("Unable to retry acquiring the PHY token, Status = %d\n",
4379 DEBUGOUT1("Semaphore acquisition retries failed!: PHY ID = 0x%08X\n",
4385 * ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4386 * @hw: pointer to hardware structure
4387 * @mask: Mask to specify which semaphore to release
4389 * Releases the SWFW semaphore and puts the shared phy token as needed
4391 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4393 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4395 DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4397 if (mask & IXGBE_GSSR_TOKEN_SM)
4398 ixgbe_put_phy_token(hw);
4401 ixgbe_release_swfw_sync_X540(hw, hmask);
4405 * ixgbe_read_phy_reg_x550a - Reads specified PHY register
4406 * @hw: pointer to hardware structure
4407 * @reg_addr: 32 bit address of PHY register to read
4408 * @phy_data: Pointer to read data from PHY register
4410 * Reads a value from a specified PHY register using the SWFW lock and PHY
4411 * Token. The PHY Token is needed since the MDIO is shared between to MAC
4414 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4415 u32 device_type, u16 *phy_data)
4418 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4420 DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4422 if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4423 return IXGBE_ERR_SWFW_SYNC;
4425 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4427 hw->mac.ops.release_swfw_sync(hw, mask);
4433 * ixgbe_write_phy_reg_x550a - Writes specified PHY register
4434 * @hw: pointer to hardware structure
4435 * @reg_addr: 32 bit PHY register to write
4436 * @device_type: 5 bit device type
4437 * @phy_data: Data to write to the PHY register
4439 * Writes a value to specified PHY register using the SWFW lock and PHY Token.
4440 * The PHY Token is needed since the MDIO is shared between to MAC instances.
4442 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4443 u32 device_type, u16 phy_data)
4446 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4448 DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4450 if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4451 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
4453 hw->mac.ops.release_swfw_sync(hw, mask);
4455 status = IXGBE_ERR_SWFW_SYNC;
4462 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4463 * @hw: pointer to hardware structure
4465 * Handle external Base T PHY interrupt. If high temperature
4466 * failure alarm then return error, else if link status change
4467 * then setup internal/external PHY link
4469 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4470 * failure alarm, else return PHY access status.
4472 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4477 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4479 if (status != IXGBE_SUCCESS)
4483 return ixgbe_setup_internal_phy(hw);
4485 return IXGBE_SUCCESS;
4489 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4490 * @hw: pointer to hardware structure
4491 * @speed: new link speed
4492 * @autoneg_wait_to_complete: true when waiting for completion is needed
4494 * Setup internal/external PHY link speed based on link speed, then set
4495 * external PHY auto advertised link speed.
4497 * Returns error status for any failure
4499 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4500 ixgbe_link_speed speed,
4501 bool autoneg_wait_to_complete)
4504 ixgbe_link_speed force_speed;
4506 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4508 /* Setup internal/external PHY link speed to iXFI (10G), unless
4509 * only 1G is auto advertised then setup KX link.
4511 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4512 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4514 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4516 /* If X552 and internal link mode is XFI, then setup XFI internal link.
4518 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4519 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4520 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4522 if (status != IXGBE_SUCCESS)
4526 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4530 * ixgbe_check_link_t_X550em - Determine link and speed status
4531 * @hw: pointer to hardware structure
4532 * @speed: pointer to link speed
4533 * @link_up: true when link is up
4534 * @link_up_wait_to_complete: bool used to wait for link up or not
4536 * Check that both the MAC and X557 external PHY have link.
4538 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4539 bool *link_up, bool link_up_wait_to_complete)
4542 u16 i, autoneg_status = 0;
4544 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4545 return IXGBE_ERR_CONFIG;
4547 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4548 link_up_wait_to_complete);
4550 /* If check link fails or MAC link is not up, then return */
4551 if (status != IXGBE_SUCCESS || !(*link_up))
4554 /* MAC link is up, so check external PHY link.
4555 * X557 PHY. Link status is latching low, and can only be used to detect
4556 * link drop, and not the current status of the link without performing
4557 * back-to-back reads.
4559 for (i = 0; i < 2; i++) {
4560 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4561 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4564 if (status != IXGBE_SUCCESS)
4568 /* If external PHY link is not up, then indicate link not up */
4569 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4572 return IXGBE_SUCCESS;
4576 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4577 * @hw: pointer to hardware structure
4579 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4583 status = ixgbe_reset_phy_generic(hw);
4585 if (status != IXGBE_SUCCESS)
4588 /* Configure Link Status Alarm and Temperature Threshold interrupts */
4589 return ixgbe_enable_lasi_ext_t_x550em(hw);
4593 * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4594 * @hw: pointer to hardware structure
4595 * @led_idx: led number to turn on
4597 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4601 DEBUGFUNC("ixgbe_led_on_t_X550em");
4603 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4604 return IXGBE_ERR_PARAM;
4606 /* To turn on the LED, set mode to ON. */
4607 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4608 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4609 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4610 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4611 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4613 /* Some designs have the LEDs wired to the MAC */
4614 return ixgbe_led_on_generic(hw, led_idx);
4618 * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4619 * @hw: pointer to hardware structure
4620 * @led_idx: led number to turn off
4622 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4626 DEBUGFUNC("ixgbe_led_off_t_X550em");
4628 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4629 return IXGBE_ERR_PARAM;
4631 /* To turn on the LED, set mode to ON. */
4632 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4633 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4634 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4635 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4636 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4638 /* Some designs have the LEDs wired to the MAC */
4639 return ixgbe_led_off_generic(hw, led_idx);
4643 * ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware
4644 * @hw: pointer to the HW structure
4645 * @maj: driver version major number
4646 * @min: driver version minor number
4647 * @build: driver version build number
4648 * @sub: driver version sub build number
4649 * @len: length of driver_ver string
4650 * @driver_ver: driver string
4652 * Sends driver version number to firmware through the manageability
4653 * block. On success return IXGBE_SUCCESS
4654 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4655 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4657 s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,
4658 u8 build, u8 sub, u16 len, const char *driver_ver)
4660 struct ixgbe_hic_drv_info2 fw_cmd;
4661 s32 ret_val = IXGBE_SUCCESS;
4664 DEBUGFUNC("ixgbe_set_fw_drv_ver_x550");
4666 if ((len == 0) || (driver_ver == NULL) ||
4667 (len > sizeof(fw_cmd.driver_string)))
4668 return IXGBE_ERR_INVALID_ARGUMENT;
4670 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4671 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len;
4672 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4673 fw_cmd.port_num = (u8)hw->bus.func;
4674 fw_cmd.ver_maj = maj;
4675 fw_cmd.ver_min = min;
4676 fw_cmd.ver_build = build;
4677 fw_cmd.ver_sub = sub;
4678 fw_cmd.hdr.checksum = 0;
4679 memcpy(fw_cmd.driver_string, driver_ver, len);
4680 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4681 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4683 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4684 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4686 IXGBE_HI_COMMAND_TIMEOUT,
4688 if (ret_val != IXGBE_SUCCESS)
4691 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4692 FW_CEM_RESP_STATUS_SUCCESS)
4693 ret_val = IXGBE_SUCCESS;
4695 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;