1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
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16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
44 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw);
47 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
48 * @hw: pointer to hardware structure
50 * Initialize the function pointers and assign the MAC type for X550.
51 * Does not touch the hardware.
53 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
55 struct ixgbe_mac_info *mac = &hw->mac;
56 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
59 DEBUGFUNC("ixgbe_init_ops_X550");
61 ret_val = ixgbe_init_ops_X540(hw);
62 mac->ops.dmac_config = ixgbe_dmac_config_X550;
63 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
64 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
65 mac->ops.setup_eee = ixgbe_setup_eee_X550;
66 mac->ops.set_source_address_pruning =
67 ixgbe_set_source_address_pruning_X550;
68 mac->ops.set_ethertype_anti_spoofing =
69 ixgbe_set_ethertype_anti_spoofing_X550;
71 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
72 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
73 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
74 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
75 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
76 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
77 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
78 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
79 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
81 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
82 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
83 mac->ops.mdd_event = ixgbe_mdd_event_X550;
84 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
85 mac->ops.disable_rx = ixgbe_disable_rx_x550;
86 switch (hw->device_id) {
87 case IXGBE_DEV_ID_X550EM_X_10G_T:
88 case IXGBE_DEV_ID_X550EM_A_10G_T:
89 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
90 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
99 * ixgbe_read_cs4227 - Read CS4227 register
100 * @hw: pointer to hardware structure
101 * @reg: register number to write
102 * @value: pointer to receive value read
104 * Returns status code
106 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
108 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
112 * ixgbe_write_cs4227 - Write CS4227 register
113 * @hw: pointer to hardware structure
114 * @reg: register number to write
115 * @value: value to write to register
117 * Returns status code
119 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
121 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
125 * ixgbe_read_pe - Read register from port expander
126 * @hw: pointer to hardware structure
127 * @reg: register number to read
128 * @value: pointer to receive read value
130 * Returns status code
132 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
136 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
137 if (status != IXGBE_SUCCESS)
138 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
139 "port expander access failed with %d\n", status);
144 * ixgbe_write_pe - Write register to port expander
145 * @hw: pointer to hardware structure
146 * @reg: register number to write
147 * @value: value to write
149 * Returns status code
151 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
155 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
156 if (status != IXGBE_SUCCESS)
157 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
158 "port expander access failed with %d\n", status);
163 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
164 * @hw: pointer to hardware structure
166 * This function assumes that the caller has acquired the proper semaphore.
169 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
176 /* Trigger hard reset. */
177 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
178 if (status != IXGBE_SUCCESS)
180 reg |= IXGBE_PE_BIT1;
181 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
182 if (status != IXGBE_SUCCESS)
185 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
186 if (status != IXGBE_SUCCESS)
188 reg &= ~IXGBE_PE_BIT1;
189 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
190 if (status != IXGBE_SUCCESS)
193 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
194 if (status != IXGBE_SUCCESS)
196 reg &= ~IXGBE_PE_BIT1;
197 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
198 if (status != IXGBE_SUCCESS)
201 usec_delay(IXGBE_CS4227_RESET_HOLD);
203 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
204 if (status != IXGBE_SUCCESS)
206 reg |= IXGBE_PE_BIT1;
207 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
208 if (status != IXGBE_SUCCESS)
211 /* Wait for the reset to complete. */
212 msec_delay(IXGBE_CS4227_RESET_DELAY);
213 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
214 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
216 if (status == IXGBE_SUCCESS &&
217 value == IXGBE_CS4227_EEPROM_LOAD_OK)
219 msec_delay(IXGBE_CS4227_CHECK_DELAY);
221 if (retry == IXGBE_CS4227_RETRIES) {
222 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
223 "CS4227 reset did not complete.");
224 return IXGBE_ERR_PHY;
227 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
228 if (status != IXGBE_SUCCESS ||
229 !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
230 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
231 "CS4227 EEPROM did not load successfully.");
232 return IXGBE_ERR_PHY;
235 return IXGBE_SUCCESS;
239 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
240 * @hw: pointer to hardware structure
242 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
244 s32 status = IXGBE_SUCCESS;
245 u32 swfw_mask = hw->phy.phy_semaphore_mask;
249 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
250 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
251 if (status != IXGBE_SUCCESS) {
252 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
253 "semaphore failed with %d", status);
254 msec_delay(IXGBE_CS4227_CHECK_DELAY);
258 /* Get status of reset flow. */
259 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
261 if (status == IXGBE_SUCCESS &&
262 value == IXGBE_CS4227_RESET_COMPLETE)
265 if (status != IXGBE_SUCCESS ||
266 value != IXGBE_CS4227_RESET_PENDING)
269 /* Reset is pending. Wait and check again. */
270 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
271 msec_delay(IXGBE_CS4227_CHECK_DELAY);
274 /* If still pending, assume other instance failed. */
275 if (retry == IXGBE_CS4227_RETRIES) {
276 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
277 if (status != IXGBE_SUCCESS) {
278 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
279 "semaphore failed with %d", status);
284 /* Reset the CS4227. */
285 status = ixgbe_reset_cs4227(hw);
286 if (status != IXGBE_SUCCESS) {
287 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
288 "CS4227 reset failed: %d", status);
292 /* Reset takes so long, temporarily release semaphore in case the
293 * other driver instance is waiting for the reset indication.
295 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
296 IXGBE_CS4227_RESET_PENDING);
297 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
299 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
300 if (status != IXGBE_SUCCESS) {
301 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
302 "semaphore failed with %d", status);
306 /* Record completion for next time. */
307 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
308 IXGBE_CS4227_RESET_COMPLETE);
311 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
312 msec_delay(hw->eeprom.semaphore_delay);
316 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
317 * @hw: pointer to hardware structure
319 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
321 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
323 if (hw->bus.lan_id) {
324 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
325 esdp |= IXGBE_ESDP_SDP1_DIR;
327 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
328 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
329 IXGBE_WRITE_FLUSH(hw);
333 * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
334 * @hw: pointer to hardware structure
335 * @reg_addr: 32 bit address of PHY register to read
336 * @dev_type: always unused
337 * @phy_data: Pointer to read data from PHY register
339 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
340 u32 dev_type, u16 *phy_data)
342 u32 i, data, command;
343 UNREFERENCED_1PARAMETER(dev_type);
345 /* Setup and write the read command */
346 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
347 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
348 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
349 IXGBE_MSCA_MDI_COMMAND;
351 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
353 /* Check every 10 usec to see if the access completed.
354 * The MDI Command bit will clear when the operation is
357 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
360 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
361 if (!(command & IXGBE_MSCA_MDI_COMMAND))
365 if (command & IXGBE_MSCA_MDI_COMMAND) {
366 ERROR_REPORT1(IXGBE_ERROR_POLLING,
367 "PHY read command did not complete.\n");
368 return IXGBE_ERR_PHY;
371 /* Read operation is complete. Get the data from MSRWD */
372 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
373 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
374 *phy_data = (u16)data;
376 return IXGBE_SUCCESS;
380 * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
381 * @hw: pointer to hardware structure
382 * @reg_addr: 32 bit PHY register to write
383 * @dev_type: always unused
384 * @phy_data: Data to write to the PHY register
386 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
387 u32 dev_type, u16 phy_data)
390 UNREFERENCED_1PARAMETER(dev_type);
392 /* Put the data in the MDI single read and write data register*/
393 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
395 /* Setup and write the write command */
396 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
397 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
398 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
399 IXGBE_MSCA_MDI_COMMAND;
401 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
403 /* Check every 10 usec to see if the access completed.
404 * The MDI Command bit will clear when the operation is
407 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
410 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
411 if (!(command & IXGBE_MSCA_MDI_COMMAND))
415 if (command & IXGBE_MSCA_MDI_COMMAND) {
416 ERROR_REPORT1(IXGBE_ERROR_POLLING,
417 "PHY write cmd didn't complete\n");
418 return IXGBE_ERR_PHY;
421 return IXGBE_SUCCESS;
425 * ixgbe_identify_phy_x550em - Get PHY type based on device id
426 * @hw: pointer to hardware structure
430 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
432 hw->mac.ops.set_lan_id(hw);
434 ixgbe_read_mng_if_sel_x550em(hw);
436 switch (hw->device_id) {
437 case IXGBE_DEV_ID_X550EM_A_SFP:
438 return ixgbe_identify_module_generic(hw);
439 case IXGBE_DEV_ID_X550EM_X_SFP:
440 /* set up for CS4227 usage */
441 ixgbe_setup_mux_ctl(hw);
442 ixgbe_check_cs4227(hw);
445 case IXGBE_DEV_ID_X550EM_A_SFP_N:
446 return ixgbe_identify_module_generic(hw);
448 case IXGBE_DEV_ID_X550EM_X_KX4:
449 hw->phy.type = ixgbe_phy_x550em_kx4;
451 case IXGBE_DEV_ID_X550EM_X_KR:
452 case IXGBE_DEV_ID_X550EM_A_KR:
453 case IXGBE_DEV_ID_X550EM_A_KR_L:
454 hw->phy.type = ixgbe_phy_x550em_kr;
456 case IXGBE_DEV_ID_X550EM_A_10G_T:
457 case IXGBE_DEV_ID_X550EM_A_1G_T:
458 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
459 case IXGBE_DEV_ID_X550EM_X_1G_T:
460 case IXGBE_DEV_ID_X550EM_X_10G_T:
461 return ixgbe_identify_phy_generic(hw);
465 return IXGBE_SUCCESS;
468 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
469 u32 device_type, u16 *phy_data)
471 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
472 return IXGBE_NOT_IMPLEMENTED;
475 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
476 u32 device_type, u16 phy_data)
478 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
479 return IXGBE_NOT_IMPLEMENTED;
483 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
484 * @hw: pointer to the hardware structure
485 * @addr: I2C bus address to read from
486 * @reg: I2C device register to read from
487 * @val: pointer to location to receive read value
489 * Returns an error code on error.
491 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
494 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
498 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
499 * @hw: pointer to the hardware structure
500 * @addr: I2C bus address to read from
501 * @reg: I2C device register to read from
502 * @val: pointer to location to receive read value
504 * Returns an error code on error.
507 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
510 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
514 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
515 * @hw: pointer to the hardware structure
516 * @addr: I2C bus address to write to
517 * @reg: I2C device register to write to
518 * @val: value to write
520 * Returns an error code on error.
522 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
523 u8 addr, u16 reg, u16 val)
525 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
529 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
530 * @hw: pointer to the hardware structure
531 * @addr: I2C bus address to write to
532 * @reg: I2C device register to write to
533 * @val: value to write
535 * Returns an error code on error.
538 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
539 u8 addr, u16 reg, u16 val)
541 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
545 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
546 * @hw: pointer to hardware structure
548 * Initialize the function pointers and for MAC type X550EM.
549 * Does not touch the hardware.
551 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
553 struct ixgbe_mac_info *mac = &hw->mac;
554 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
555 struct ixgbe_phy_info *phy = &hw->phy;
558 DEBUGFUNC("ixgbe_init_ops_X550EM");
560 /* Similar to X550 so start there. */
561 ret_val = ixgbe_init_ops_X550(hw);
563 /* Since this function eventually calls
564 * ixgbe_init_ops_540 by design, we are setting
565 * the pointers to NULL explicitly here to overwrite
566 * the values being set in the x540 function.
568 /* Thermal sensor not supported in x550EM */
569 mac->ops.get_thermal_sensor_data = NULL;
570 mac->ops.init_thermal_sensor_thresh = NULL;
571 mac->thermal_sensor_enabled = false;
573 /* FCOE not supported in x550EM */
574 mac->ops.get_san_mac_addr = NULL;
575 mac->ops.set_san_mac_addr = NULL;
576 mac->ops.get_wwn_prefix = NULL;
577 mac->ops.get_fcoe_boot_status = NULL;
579 /* IPsec not supported in x550EM */
580 mac->ops.disable_sec_rx_path = NULL;
581 mac->ops.enable_sec_rx_path = NULL;
583 /* AUTOC register is not present in x550EM. */
584 mac->ops.prot_autoc_read = NULL;
585 mac->ops.prot_autoc_write = NULL;
587 /* X550EM bus type is internal*/
588 hw->bus.type = ixgbe_bus_type_internal;
589 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
592 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
593 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
594 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
595 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
596 mac->ops.get_supported_physical_layer =
597 ixgbe_get_supported_physical_layer_X550em;
599 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
600 mac->ops.setup_fc = ixgbe_setup_fc_generic;
602 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
604 switch (hw->device_id) {
605 case IXGBE_DEV_ID_X550EM_X_KR:
606 case IXGBE_DEV_ID_X550EM_A_KR:
607 case IXGBE_DEV_ID_X550EM_A_KR_L:
610 mac->ops.setup_eee = NULL;
614 phy->ops.init = ixgbe_init_phy_ops_X550em;
615 phy->ops.identify = ixgbe_identify_phy_x550em;
616 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
617 phy->ops.set_phy_power = NULL;
621 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
622 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
623 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
624 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
625 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
626 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
627 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
628 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
634 * ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
635 * @hw: pointer to hardware structure
637 * Initialize the function pointers and for MAC type X550EM_a.
638 * Does not touch the hardware.
640 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
642 struct ixgbe_mac_info *mac = &hw->mac;
645 DEBUGFUNC("ixgbe_init_ops_X550EM_a");
647 /* Start with generic X550EM init */
648 ret_val = ixgbe_init_ops_X550EM(hw);
650 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
651 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) {
652 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
653 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
655 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
656 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
658 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
659 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
661 switch (mac->ops.get_media_type(hw)) {
662 case ixgbe_media_type_fiber:
663 mac->ops.setup_fc = ixgbe_setup_fc_fiber_x550em_a;
664 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
666 case ixgbe_media_type_backplane:
667 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
668 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
674 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T) ||
675 (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)) {
676 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
677 mac->ops.setup_fc = ixgbe_setup_fc_sgmii_x550em_a;
684 * ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
685 * @hw: pointer to hardware structure
687 * Initialize the function pointers and for MAC type X550EM_x.
688 * Does not touch the hardware.
690 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
692 struct ixgbe_mac_info *mac = &hw->mac;
693 struct ixgbe_link_info *link = &hw->link;
696 DEBUGFUNC("ixgbe_init_ops_X550EM_x");
698 /* Start with generic X550EM init */
699 ret_val = ixgbe_init_ops_X550EM(hw);
701 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
702 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
703 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
704 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
705 link->ops.read_link = ixgbe_read_i2c_combined_generic;
706 link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
707 link->ops.write_link = ixgbe_write_i2c_combined_generic;
708 link->ops.write_link_unlocked =
709 ixgbe_write_i2c_combined_generic_unlocked;
710 link->addr = IXGBE_CS4227;
716 * ixgbe_dmac_config_X550
717 * @hw: pointer to hardware structure
719 * Configure DMA coalescing. If enabling dmac, dmac is activated.
720 * When disabling dmac, dmac enable dmac bit is cleared.
722 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
724 u32 reg, high_pri_tc;
726 DEBUGFUNC("ixgbe_dmac_config_X550");
728 /* Disable DMA coalescing before configuring */
729 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
730 reg &= ~IXGBE_DMACR_DMAC_EN;
731 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
733 /* Disable DMA Coalescing if the watchdog timer is 0 */
734 if (!hw->mac.dmac_config.watchdog_timer)
737 ixgbe_dmac_config_tcs_X550(hw);
739 /* Configure DMA Coalescing Control Register */
740 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
742 /* Set the watchdog timer in units of 40.96 usec */
743 reg &= ~IXGBE_DMACR_DMACWT_MASK;
744 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
746 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
747 /* If fcoe is enabled, set high priority traffic class */
748 if (hw->mac.dmac_config.fcoe_en) {
749 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
750 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
751 IXGBE_DMACR_HIGH_PRI_TC_MASK);
753 reg |= IXGBE_DMACR_EN_MNG_IND;
755 /* Enable DMA coalescing after configuration */
756 reg |= IXGBE_DMACR_DMAC_EN;
757 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
760 return IXGBE_SUCCESS;
764 * ixgbe_dmac_config_tcs_X550
765 * @hw: pointer to hardware structure
767 * Configure DMA coalescing threshold per TC. The dmac enable bit must
768 * be cleared before configuring.
770 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
772 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
774 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
776 /* Configure DMA coalescing enabled */
777 switch (hw->mac.dmac_config.link_speed) {
778 case IXGBE_LINK_SPEED_10_FULL:
779 case IXGBE_LINK_SPEED_100_FULL:
780 pb_headroom = IXGBE_DMACRXT_100M;
782 case IXGBE_LINK_SPEED_1GB_FULL:
783 pb_headroom = IXGBE_DMACRXT_1G;
786 pb_headroom = IXGBE_DMACRXT_10G;
790 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
791 IXGBE_MHADD_MFS_SHIFT) / 1024);
793 /* Set the per Rx packet buffer receive threshold */
794 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
795 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
796 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
798 if (tc < hw->mac.dmac_config.num_tcs) {
800 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
801 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
802 IXGBE_RXPBSIZE_SHIFT;
804 /* Calculate receive buffer threshold in kilobytes */
805 if (rx_pb_size > pb_headroom)
806 rx_pb_size = rx_pb_size - pb_headroom;
810 /* Minimum of MFS shall be set for DMCTH */
811 reg |= (rx_pb_size > maxframe_size_kb) ?
812 rx_pb_size : maxframe_size_kb;
814 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
816 return IXGBE_SUCCESS;
820 * ixgbe_dmac_update_tcs_X550
821 * @hw: pointer to hardware structure
823 * Disables dmac, updates per TC settings, and then enables dmac.
825 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
829 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
831 /* Disable DMA coalescing before configuring */
832 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
833 reg &= ~IXGBE_DMACR_DMAC_EN;
834 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
836 ixgbe_dmac_config_tcs_X550(hw);
838 /* Enable DMA coalescing after configuration */
839 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
840 reg |= IXGBE_DMACR_DMAC_EN;
841 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
843 return IXGBE_SUCCESS;
847 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
848 * @hw: pointer to hardware structure
850 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
851 * ixgbe_hw struct in order to set up EEPROM access.
853 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
855 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
859 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
861 if (eeprom->type == ixgbe_eeprom_uninitialized) {
862 eeprom->semaphore_delay = 10;
863 eeprom->type = ixgbe_flash;
865 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
866 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
867 IXGBE_EEC_SIZE_SHIFT);
868 eeprom->word_size = 1 << (eeprom_size +
869 IXGBE_EEPROM_WORD_SIZE_SHIFT);
871 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
872 eeprom->type, eeprom->word_size);
875 return IXGBE_SUCCESS;
879 * ixgbe_enable_eee_x550 - Enable EEE support
880 * @hw: pointer to hardware structure
882 STATIC s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
888 if (hw->mac.type == ixgbe_mac_X550) {
889 /* Advertise EEE capability */
890 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
891 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
894 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
895 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
896 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
898 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
899 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
901 return IXGBE_SUCCESS;
904 switch (hw->device_id) {
905 case IXGBE_DEV_ID_X550EM_X_KR:
906 case IXGBE_DEV_ID_X550EM_A_KR:
907 case IXGBE_DEV_ID_X550EM_A_KR_L:
908 status = hw->mac.ops.read_iosf_sb_reg(hw,
909 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
910 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
911 if (status != IXGBE_SUCCESS)
914 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
915 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
917 /* Don't advertise FEC capability when EEE enabled. */
918 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
920 status = hw->mac.ops.write_iosf_sb_reg(hw,
921 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
922 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
923 if (status != IXGBE_SUCCESS)
930 return IXGBE_SUCCESS;
934 * ixgbe_disable_eee_x550 - Disable EEE support
935 * @hw: pointer to hardware structure
937 STATIC s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
943 if (hw->mac.type == ixgbe_mac_X550) {
944 /* Disable advertised EEE capability */
945 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
946 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
949 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
950 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
951 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
953 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
954 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
956 return IXGBE_SUCCESS;
959 switch (hw->device_id) {
960 case IXGBE_DEV_ID_X550EM_X_KR:
961 case IXGBE_DEV_ID_X550EM_A_KR:
962 case IXGBE_DEV_ID_X550EM_A_KR_L:
963 status = hw->mac.ops.read_iosf_sb_reg(hw,
964 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
965 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
966 if (status != IXGBE_SUCCESS)
969 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
970 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
972 /* Advertise FEC capability when EEE is disabled. */
973 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
975 status = hw->mac.ops.write_iosf_sb_reg(hw,
976 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
977 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
978 if (status != IXGBE_SUCCESS)
985 return IXGBE_SUCCESS;
989 * ixgbe_setup_eee_X550 - Enable/disable EEE support
990 * @hw: pointer to the HW structure
991 * @enable_eee: boolean flag to enable EEE
993 * Enable/disable EEE based on enable_eee flag.
994 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
998 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
1003 DEBUGFUNC("ixgbe_setup_eee_X550");
1005 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
1006 /* Enable or disable EEE per flag */
1008 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1010 /* Not supported on first revision of X550EM_x. */
1011 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
1012 !(IXGBE_FUSES0_REV_MASK &
1013 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
1014 return IXGBE_SUCCESS;
1015 status = ixgbe_enable_eee_x550(hw);
1019 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1021 status = ixgbe_disable_eee_x550(hw);
1025 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
1027 return IXGBE_SUCCESS;
1031 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1032 * @hw: pointer to hardware structure
1033 * @enable: enable or disable source address pruning
1034 * @pool: Rx pool to set source address pruning for
1036 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1041 /* max rx pool is 63 */
1045 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1046 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1049 pfflp |= (1ULL << pool);
1051 pfflp &= ~(1ULL << pool);
1053 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1054 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1058 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1059 * @hw: pointer to hardware structure
1060 * @enable: enable or disable switch for Ethertype anti-spoofing
1061 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1064 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1065 bool enable, int vf)
1067 int vf_target_reg = vf >> 3;
1068 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1071 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1073 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1075 pfvfspoof |= (1 << vf_target_shift);
1077 pfvfspoof &= ~(1 << vf_target_shift);
1079 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1083 * ixgbe_iosf_wait - Wait for IOSF command completion
1084 * @hw: pointer to hardware structure
1085 * @ctrl: pointer to location to receive final IOSF control value
1087 * Returns failing status on timeout
1089 * Note: ctrl can be NULL if the IOSF control register value is not needed
1091 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1095 /* Check every 10 usec to see if the address cycle completed.
1096 * The SB IOSF BUSY bit will clear when the operation is
1099 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1100 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1101 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1107 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1108 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1109 return IXGBE_ERR_PHY;
1112 return IXGBE_SUCCESS;
1116 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register
1117 * of the IOSF device
1118 * @hw: pointer to hardware structure
1119 * @reg_addr: 32 bit PHY register to write
1120 * @device_type: 3 bit device type
1121 * @data: Data to write to the register
1123 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1124 u32 device_type, u32 data)
1126 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1130 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1131 if (ret != IXGBE_SUCCESS)
1134 ret = ixgbe_iosf_wait(hw, NULL);
1135 if (ret != IXGBE_SUCCESS)
1138 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1139 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1141 /* Write IOSF control register */
1142 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1144 /* Write IOSF data register */
1145 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1147 ret = ixgbe_iosf_wait(hw, &command);
1149 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1150 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1151 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1152 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1153 "Failed to write, error %x\n", error);
1154 ret = IXGBE_ERR_PHY;
1158 ixgbe_release_swfw_semaphore(hw, gssr);
1163 * ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device
1164 * @hw: pointer to hardware structure
1165 * @reg_addr: 32 bit PHY register to write
1166 * @device_type: 3 bit device type
1167 * @data: Pointer to read data from the register
1169 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1170 u32 device_type, u32 *data)
1172 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1176 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1177 if (ret != IXGBE_SUCCESS)
1180 ret = ixgbe_iosf_wait(hw, NULL);
1181 if (ret != IXGBE_SUCCESS)
1184 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1185 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1187 /* Write IOSF control register */
1188 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1190 ret = ixgbe_iosf_wait(hw, &command);
1192 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1193 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1194 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1195 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1196 "Failed to read, error %x\n", error);
1197 ret = IXGBE_ERR_PHY;
1200 if (ret == IXGBE_SUCCESS)
1201 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1204 ixgbe_release_swfw_semaphore(hw, gssr);
1209 * ixgbe_get_phy_token - Get the token for shared phy access
1210 * @hw: Pointer to hardware structure
1213 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1215 struct ixgbe_hic_phy_token_req token_cmd;
1218 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1219 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1220 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1221 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1222 token_cmd.port_number = hw->bus.lan_id;
1223 token_cmd.command_type = FW_PHY_TOKEN_REQ;
1225 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1227 IXGBE_HI_COMMAND_TIMEOUT,
1231 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1232 return IXGBE_SUCCESS;
1233 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1234 return IXGBE_ERR_FW_RESP_INVALID;
1236 return IXGBE_ERR_TOKEN_RETRY;
1240 * ixgbe_put_phy_token - Put the token for shared phy access
1241 * @hw: Pointer to hardware structure
1244 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1246 struct ixgbe_hic_phy_token_req token_cmd;
1249 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1250 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1251 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1252 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1253 token_cmd.port_number = hw->bus.lan_id;
1254 token_cmd.command_type = FW_PHY_TOKEN_REL;
1256 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1258 IXGBE_HI_COMMAND_TIMEOUT,
1262 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1263 return IXGBE_SUCCESS;
1265 DEBUGOUT("Put PHY Token host interface command failed");
1266 return IXGBE_ERR_FW_RESP_INVALID;
1270 * ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1271 * of the IOSF device
1272 * @hw: pointer to hardware structure
1273 * @reg_addr: 32 bit PHY register to write
1274 * @device_type: 3 bit device type
1275 * @data: Data to write to the register
1277 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1278 u32 device_type, u32 data)
1280 struct ixgbe_hic_internal_phy_req write_cmd;
1282 UNREFERENCED_1PARAMETER(device_type);
1284 memset(&write_cmd, 0, sizeof(write_cmd));
1285 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1286 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1287 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1288 write_cmd.port_number = hw->bus.lan_id;
1289 write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1290 write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1291 write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1293 status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1295 IXGBE_HI_COMMAND_TIMEOUT, false);
1301 * ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device
1302 * @hw: pointer to hardware structure
1303 * @reg_addr: 32 bit PHY register to write
1304 * @device_type: 3 bit device type
1305 * @data: Pointer to read data from the register
1307 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1308 u32 device_type, u32 *data)
1311 struct ixgbe_hic_internal_phy_req cmd;
1312 struct ixgbe_hic_internal_phy_resp rsp;
1315 UNREFERENCED_1PARAMETER(device_type);
1317 memset(&hic, 0, sizeof(hic));
1318 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1319 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1320 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1321 hic.cmd.port_number = hw->bus.lan_id;
1322 hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1323 hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1325 status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1327 IXGBE_HI_COMMAND_TIMEOUT, true);
1329 /* Extract the register value from the response. */
1330 *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1336 * ixgbe_disable_mdd_X550
1337 * @hw: pointer to hardware structure
1339 * Disable malicious driver detection
1341 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1345 DEBUGFUNC("ixgbe_disable_mdd_X550");
1347 /* Disable MDD for TX DMA and interrupt */
1348 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1349 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1350 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1352 /* Disable MDD for RX and interrupt */
1353 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1354 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1355 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1359 * ixgbe_enable_mdd_X550
1360 * @hw: pointer to hardware structure
1362 * Enable malicious driver detection
1364 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1368 DEBUGFUNC("ixgbe_enable_mdd_X550");
1370 /* Enable MDD for TX DMA and interrupt */
1371 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1372 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1373 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1375 /* Enable MDD for RX and interrupt */
1376 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1377 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1378 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1382 * ixgbe_restore_mdd_vf_X550
1383 * @hw: pointer to hardware structure
1386 * Restore VF that was disabled during malicious driver detection event
1388 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1390 u32 idx, reg, num_qs, start_q, bitmask;
1392 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1394 /* Map VF to queues */
1395 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1396 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1397 case IXGBE_MRQC_VMDQRT8TCEN:
1398 num_qs = 8; /* 16 VFs / pools */
1399 bitmask = 0x000000FF;
1401 case IXGBE_MRQC_VMDQRSS32EN:
1402 case IXGBE_MRQC_VMDQRT4TCEN:
1403 num_qs = 4; /* 32 VFs / pools */
1404 bitmask = 0x0000000F;
1406 default: /* 64 VFs / pools */
1408 bitmask = 0x00000003;
1411 start_q = vf * num_qs;
1413 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1416 reg |= (bitmask << (start_q % 32));
1417 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1418 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1422 * ixgbe_mdd_event_X550
1423 * @hw: pointer to hardware structure
1424 * @vf_bitmap: vf bitmap of malicious vfs
1426 * Handle malicious driver detection event.
1428 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1431 u32 i, j, reg, q, shift, vf, idx;
1433 DEBUGFUNC("ixgbe_mdd_event_X550");
1435 /* figure out pool size for mapping to vf's */
1436 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1437 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1438 case IXGBE_MRQC_VMDQRT8TCEN:
1439 shift = 3; /* 16 VFs / pools */
1441 case IXGBE_MRQC_VMDQRSS32EN:
1442 case IXGBE_MRQC_VMDQRT4TCEN:
1443 shift = 2; /* 32 VFs / pools */
1446 shift = 1; /* 64 VFs / pools */
1450 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1451 for (i = 0; i < 4; i++) {
1452 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1453 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1458 /* Get malicious queue */
1459 for (j = 0; j < 32 && wqbr; j++) {
1461 if (!(wqbr & (1 << j)))
1464 /* Get queue from bitmask */
1467 /* Map queue to vf */
1470 /* Set vf bit in vf_bitmap */
1472 vf_bitmap[idx] |= (1 << (vf % 32));
1479 * ixgbe_get_media_type_X550em - Get media type
1480 * @hw: pointer to hardware structure
1482 * Returns the media type (fiber, copper, backplane)
1484 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1486 enum ixgbe_media_type media_type;
1488 DEBUGFUNC("ixgbe_get_media_type_X550em");
1490 /* Detect if there is a copper PHY attached. */
1491 switch (hw->device_id) {
1492 case IXGBE_DEV_ID_X550EM_X_KR:
1493 case IXGBE_DEV_ID_X550EM_X_KX4:
1494 case IXGBE_DEV_ID_X550EM_A_KR:
1495 case IXGBE_DEV_ID_X550EM_A_KR_L:
1496 media_type = ixgbe_media_type_backplane;
1498 case IXGBE_DEV_ID_X550EM_X_SFP:
1499 case IXGBE_DEV_ID_X550EM_A_SFP:
1500 case IXGBE_DEV_ID_X550EM_A_SFP_N:
1501 case IXGBE_DEV_ID_X550EM_A_QSFP:
1502 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1503 media_type = ixgbe_media_type_fiber;
1505 case IXGBE_DEV_ID_X550EM_X_1G_T:
1506 case IXGBE_DEV_ID_X550EM_X_10G_T:
1507 case IXGBE_DEV_ID_X550EM_A_10G_T:
1508 media_type = ixgbe_media_type_copper;
1510 case IXGBE_DEV_ID_X550EM_A_SGMII:
1511 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1512 media_type = ixgbe_media_type_backplane;
1513 hw->phy.type = ixgbe_phy_sgmii;
1515 case IXGBE_DEV_ID_X550EM_A_1G_T:
1516 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1517 media_type = ixgbe_media_type_copper;
1520 media_type = ixgbe_media_type_unknown;
1527 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1528 * @hw: pointer to hardware structure
1529 * @linear: true if SFP module is linear
1531 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1533 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1535 switch (hw->phy.sfp_type) {
1536 case ixgbe_sfp_type_not_present:
1537 return IXGBE_ERR_SFP_NOT_PRESENT;
1538 case ixgbe_sfp_type_da_cu_core0:
1539 case ixgbe_sfp_type_da_cu_core1:
1542 case ixgbe_sfp_type_srlr_core0:
1543 case ixgbe_sfp_type_srlr_core1:
1544 case ixgbe_sfp_type_da_act_lmt_core0:
1545 case ixgbe_sfp_type_da_act_lmt_core1:
1546 case ixgbe_sfp_type_1g_sx_core0:
1547 case ixgbe_sfp_type_1g_sx_core1:
1548 case ixgbe_sfp_type_1g_lx_core0:
1549 case ixgbe_sfp_type_1g_lx_core1:
1552 case ixgbe_sfp_type_unknown:
1553 case ixgbe_sfp_type_1g_cu_core0:
1554 case ixgbe_sfp_type_1g_cu_core1:
1556 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1559 return IXGBE_SUCCESS;
1563 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1564 * @hw: pointer to hardware structure
1566 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1568 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1573 DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1575 status = ixgbe_identify_module_generic(hw);
1577 if (status != IXGBE_SUCCESS)
1580 /* Check if SFP module is supported */
1581 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1587 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1588 * @hw: pointer to hardware structure
1590 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1595 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1597 /* Check if SFP module is supported */
1598 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1600 if (status != IXGBE_SUCCESS)
1603 ixgbe_init_mac_link_ops_X550em(hw);
1604 hw->phy.ops.reset = NULL;
1606 return IXGBE_SUCCESS;
1610 * ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1612 * @hw: pointer to hardware structure
1614 STATIC s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1619 /* Restart auto-negotiation. */
1620 status = hw->mac.ops.read_iosf_sb_reg(hw,
1621 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1622 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1625 DEBUGOUT("Auto-negotiation did not complete\n");
1629 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1630 status = hw->mac.ops.write_iosf_sb_reg(hw,
1631 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1632 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1634 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1637 /* Indicate to FW that AN restart has been asserted */
1638 status = hw->mac.ops.read_iosf_sb_reg(hw,
1639 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1640 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1643 DEBUGOUT("Auto-negotiation did not complete\n");
1647 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1648 status = hw->mac.ops.write_iosf_sb_reg(hw,
1649 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1650 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1657 * ixgbe_setup_sgmii - Set up link for sgmii
1658 * @hw: pointer to hardware structure
1660 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1663 struct ixgbe_mac_info *mac = &hw->mac;
1664 u32 lval, sval, flx_val;
1667 rc = mac->ops.read_iosf_sb_reg(hw,
1668 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1669 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1673 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1674 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1675 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1676 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1677 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1678 rc = mac->ops.write_iosf_sb_reg(hw,
1679 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1680 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1684 rc = mac->ops.read_iosf_sb_reg(hw,
1685 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1686 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1690 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1691 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1692 rc = mac->ops.write_iosf_sb_reg(hw,
1693 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1694 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1698 rc = mac->ops.read_iosf_sb_reg(hw,
1699 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1700 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1704 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1705 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1706 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1707 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1708 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1710 rc = mac->ops.write_iosf_sb_reg(hw,
1711 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1712 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1716 rc = ixgbe_restart_an_internal_phy_x550em(hw);
1720 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1724 * ixgbe_setup_sgmii_m88 - Set up link for sgmii with Marvell PHYs
1725 * @hw: pointer to hardware structure
1727 STATIC s32 ixgbe_setup_sgmii_m88(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1730 struct ixgbe_mac_info *mac = &hw->mac;
1731 u32 lval, sval, flx_val;
1734 rc = mac->ops.read_iosf_sb_reg(hw,
1735 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1736 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1740 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1741 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1742 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1743 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1744 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1745 rc = mac->ops.write_iosf_sb_reg(hw,
1746 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1747 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1751 rc = mac->ops.read_iosf_sb_reg(hw,
1752 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1753 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1757 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1758 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1759 rc = mac->ops.write_iosf_sb_reg(hw,
1760 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1761 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1765 rc = mac->ops.write_iosf_sb_reg(hw,
1766 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1767 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1771 rc = mac->ops.read_iosf_sb_reg(hw,
1772 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1773 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1777 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1778 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1779 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1780 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1781 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1783 rc = mac->ops.write_iosf_sb_reg(hw,
1784 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1785 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1789 rc = ixgbe_restart_an_internal_phy_x550em(hw);
1791 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1795 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1796 * @hw: pointer to hardware structure
1798 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1800 struct ixgbe_mac_info *mac = &hw->mac;
1802 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1804 switch (hw->mac.ops.get_media_type(hw)) {
1805 case ixgbe_media_type_fiber:
1806 /* CS4227 does not support autoneg, so disable the laser control
1807 * functions for SFP+ fiber
1809 mac->ops.disable_tx_laser = NULL;
1810 mac->ops.enable_tx_laser = NULL;
1811 mac->ops.flap_tx_laser = NULL;
1812 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1813 mac->ops.set_rate_select_speed =
1814 ixgbe_set_soft_rate_select_speed;
1815 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1816 (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1817 mac->ops.setup_mac_link =
1818 ixgbe_setup_mac_link_sfp_x550a;
1820 mac->ops.setup_mac_link =
1821 ixgbe_setup_mac_link_sfp_x550em;
1823 case ixgbe_media_type_copper:
1824 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1825 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
1826 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
1827 mac->ops.setup_link = ixgbe_setup_sgmii_m88;
1829 mac->ops.setup_link =
1830 ixgbe_setup_mac_link_t_X550em;
1833 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1834 mac->ops.check_link = ixgbe_check_link_t_X550em;
1837 case ixgbe_media_type_backplane:
1838 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1839 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1840 mac->ops.setup_link = ixgbe_setup_sgmii;
1848 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1849 * @hw: pointer to hardware structure
1850 * @speed: pointer to link speed
1851 * @autoneg: true when autoneg or autotry is enabled
1853 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1854 ixgbe_link_speed *speed,
1857 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1860 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1862 /* CS4227 SFP must not enable auto-negotiation */
1865 /* Check if 1G SFP module. */
1866 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1867 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1868 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1869 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1870 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1871 return IXGBE_SUCCESS;
1874 /* Link capabilities are based on SFP */
1875 if (hw->phy.multispeed_fiber)
1876 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1877 IXGBE_LINK_SPEED_1GB_FULL;
1879 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1881 switch (hw->phy.type) {
1883 *speed = IXGBE_LINK_SPEED_1GB_FULL |
1884 IXGBE_LINK_SPEED_100_FULL |
1885 IXGBE_LINK_SPEED_10_FULL;
1887 case ixgbe_phy_sgmii:
1888 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1891 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1892 IXGBE_LINK_SPEED_1GB_FULL;
1898 return IXGBE_SUCCESS;
1902 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1903 * @hw: pointer to hardware structure
1904 * @lsc: pointer to boolean flag which indicates whether external Base T
1905 * PHY interrupt is lsc
1907 * Determime if external Base T PHY interrupt cause is high temperature
1908 * failure alarm or link status change.
1910 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1911 * failure alarm, else return PHY access status.
1913 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1920 /* Vendor alarm triggered */
1921 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1922 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1925 if (status != IXGBE_SUCCESS ||
1926 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1929 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1930 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1931 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1934 if (status != IXGBE_SUCCESS ||
1935 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1936 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1939 /* Global alarm triggered */
1940 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1941 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1944 if (status != IXGBE_SUCCESS)
1947 /* If high temperature failure, then return over temp error and exit */
1948 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1949 /* power down the PHY in case the PHY FW didn't already */
1950 ixgbe_set_copper_phy_power(hw, false);
1951 return IXGBE_ERR_OVERTEMP;
1952 } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1953 /* device fault alarm triggered */
1954 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1955 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1958 if (status != IXGBE_SUCCESS)
1961 /* if device fault was due to high temp alarm handle and exit */
1962 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1963 /* power down the PHY in case the PHY FW didn't */
1964 ixgbe_set_copper_phy_power(hw, false);
1965 return IXGBE_ERR_OVERTEMP;
1969 /* Vendor alarm 2 triggered */
1970 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1971 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1973 if (status != IXGBE_SUCCESS ||
1974 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1977 /* link connect/disconnect event occurred */
1978 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1979 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1981 if (status != IXGBE_SUCCESS)
1985 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1988 return IXGBE_SUCCESS;
1992 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1993 * @hw: pointer to hardware structure
1995 * Enable link status change and temperature failure alarm for the external
1998 * Returns PHY access status
2000 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2006 /* Clear interrupt flags */
2007 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2009 /* Enable link status change alarm */
2010 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2011 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
2013 if (status != IXGBE_SUCCESS)
2016 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2018 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2019 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
2021 if (status != IXGBE_SUCCESS)
2024 /* Enable high temperature failure and global fault alarms */
2025 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2026 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2029 if (status != IXGBE_SUCCESS)
2032 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2033 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2035 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2036 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2039 if (status != IXGBE_SUCCESS)
2042 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2043 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2044 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2047 if (status != IXGBE_SUCCESS)
2050 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2051 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2053 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2054 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2057 if (status != IXGBE_SUCCESS)
2060 /* Enable chip-wide vendor alarm */
2061 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2062 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2065 if (status != IXGBE_SUCCESS)
2068 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2070 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2071 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2078 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2079 * @hw: pointer to hardware structure
2080 * @speed: link speed
2082 * Configures the integrated KR PHY.
2084 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2085 ixgbe_link_speed speed)
2090 status = hw->mac.ops.read_iosf_sb_reg(hw,
2091 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2092 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2096 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2097 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2098 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2100 /* Advertise 10G support. */
2101 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2102 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2104 /* Advertise 1G support. */
2105 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2106 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2108 status = hw->mac.ops.write_iosf_sb_reg(hw,
2109 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2110 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2115 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2116 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2117 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2118 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2119 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2121 status = hw->mac.ops.write_iosf_sb_reg(hw,
2122 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2123 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2125 return ixgbe_restart_an_internal_phy_x550em(hw);
2129 * ixgbe_setup_m88 - setup m88 PHY
2130 * @hw: pointer to hardware structure
2132 STATIC s32 ixgbe_setup_m88(struct ixgbe_hw *hw)
2134 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2138 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2139 return IXGBE_SUCCESS;
2141 rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2145 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2148 if (reg & IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN) {
2149 reg &= ~IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN;
2150 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2154 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, ®);
2157 if (reg & IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN) {
2158 reg &= ~IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN;
2159 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0,
2163 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 2);
2167 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2171 if (reg & IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN) {
2172 reg &= ~IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN;
2173 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2175 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2179 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2183 reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2184 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2188 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2194 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2198 if (!(reg & IXGBE_M88E1500_COPPER_CTRL_AN_EN)) {
2199 reg |= IXGBE_M88E1500_COPPER_CTRL_AN_EN;
2200 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2204 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, ®);
2207 reg &= ~IXGBE_M88E1500_1000T_CTRL_HALF_DUPLEX;
2208 reg &= ~IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2209 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
2210 reg |= IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2211 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, reg);
2213 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, ®);
2216 reg &= ~IXGBE_M88E1500_COPPER_AN_T4;
2217 reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_FD;
2218 reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_HD;
2219 reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_FD;
2220 reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_HD;
2222 /* Flow control auto negotiation configuration was moved from here to
2223 * the function ixgbe_setup_fc_sgmii_x550em_a()
2226 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
2227 reg |= IXGBE_M88E1500_COPPER_AN_100TX_FD;
2228 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL)
2229 reg |= IXGBE_M88E1500_COPPER_AN_10TX_FD;
2230 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, reg);
2232 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2235 reg |= IXGBE_M88E1500_COPPER_CTRL_RESTART_AN;
2236 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2239 hw->mac.ops.release_swfw_sync(hw, mask);
2243 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2244 hw->mac.ops.release_swfw_sync(hw, mask);
2249 * ixgbe_reset_phy_m88e1500 - Reset m88e1500 PHY
2250 * @hw: pointer to hardware structure
2252 * The PHY token must be held when calling this function.
2254 static s32 ixgbe_reset_phy_m88e1500(struct ixgbe_hw *hw)
2259 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2263 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2267 reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2268 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2276 * ixgbe_reset_phy_m88e1543 - Reset m88e1543 PHY
2277 * @hw: pointer to hardware structure
2279 * The PHY token must be held when calling this function.
2281 static s32 ixgbe_reset_phy_m88e1543(struct ixgbe_hw *hw)
2283 return hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2287 * ixgbe_reset_phy_m88 - Reset m88 PHY
2288 * @hw: pointer to hardware structure
2290 STATIC s32 ixgbe_reset_phy_m88(struct ixgbe_hw *hw)
2292 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2296 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2297 return IXGBE_SUCCESS;
2299 rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2303 switch (hw->phy.id) {
2304 case IXGBE_M88E1500_E_PHY_ID:
2305 rc = ixgbe_reset_phy_m88e1500(hw);
2307 case IXGBE_M88E1543_E_PHY_ID:
2308 rc = ixgbe_reset_phy_m88e1543(hw);
2315 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2319 reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2320 IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2321 IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2322 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2326 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 18);
2330 reg = IXGBE_M88E1500_GEN_CTRL_RESET |
2331 IXGBE_M88E1500_GEN_CTRL_MODE_SGMII_COPPER;
2332 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_GEN_CTRL, 0, reg);
2336 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2340 reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2341 IXGBE_M88E1500_FIBER_CTRL_AN_EN |
2342 IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2343 IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2344 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2348 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2352 reg = (IXGBE_M88E1500_MAC_CTRL_1_DWN_4X <<
2353 IXGBE_M88E1500_MAC_CTRL_1_DWN_SHIFT) |
2354 (IXGBE_M88E1500_MAC_CTRL_1_ED_TM <<
2355 IXGBE_M88E1500_MAC_CTRL_1_ED_SHIFT) |
2356 (IXGBE_M88E1500_MAC_CTRL_1_MDIX_AUTO <<
2357 IXGBE_M88E1500_MAC_CTRL_1_MDIX_SHIFT);
2358 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, reg);
2362 reg = IXGBE_M88E1500_COPPER_CTRL_RESET |
2363 IXGBE_M88E1500_COPPER_CTRL_AN_EN |
2364 IXGBE_M88E1500_COPPER_CTRL_RESTART_AN |
2365 IXGBE_M88E1500_COPPER_CTRL_FULL_DUPLEX |
2366 IXGBE_M88E1500_COPPER_CTRL_SPEED_MSB;
2367 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2371 hw->mac.ops.release_swfw_sync(hw, mask);
2373 /* In case of first reset set advertised speeds to default value */
2374 if (!hw->phy.autoneg_advertised)
2375 hw->phy.autoneg_advertised = IXGBE_LINK_SPEED_1GB_FULL |
2376 IXGBE_LINK_SPEED_100_FULL |
2377 IXGBE_LINK_SPEED_10_FULL;
2379 return ixgbe_setup_m88(hw);
2382 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2383 hw->mac.ops.release_swfw_sync(hw, mask);
2388 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2389 * @hw: pointer to hardware structure
2391 * Read NW_MNG_IF_SEL register and save field values, and check for valid field
2394 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2396 /* Save NW management interface connected on board. This is used
2397 * to determine internal PHY mode.
2399 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2401 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2402 * PHY address. This register field was has only been used for X552.
2404 if (hw->mac.type == ixgbe_mac_X550EM_a &&
2405 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2406 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2407 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2408 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2411 return IXGBE_SUCCESS;
2415 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2416 * @hw: pointer to hardware structure
2418 * Initialize any function pointers that were not able to be
2419 * set during init_shared_code because the PHY/SFP type was
2420 * not known. Perform the SFP init if necessary.
2422 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2424 struct ixgbe_phy_info *phy = &hw->phy;
2427 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2429 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2430 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2431 ixgbe_setup_mux_ctl(hw);
2432 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2435 switch (hw->device_id) {
2436 case IXGBE_DEV_ID_X550EM_A_1G_T:
2437 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2438 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2439 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2440 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2441 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2443 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2445 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2448 case IXGBE_DEV_ID_X550EM_A_10G_T:
2449 case IXGBE_DEV_ID_X550EM_A_SFP:
2450 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2451 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2453 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2455 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2457 case IXGBE_DEV_ID_X550EM_X_SFP:
2458 /* set up for CS4227 usage */
2459 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2465 /* Identify the PHY or SFP module */
2466 ret_val = phy->ops.identify(hw);
2467 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
2470 /* Setup function pointers based on detected hardware */
2471 ixgbe_init_mac_link_ops_X550em(hw);
2472 if (phy->sfp_type != ixgbe_sfp_type_unknown)
2473 phy->ops.reset = NULL;
2475 /* Set functions pointers based on phy type */
2476 switch (hw->phy.type) {
2477 case ixgbe_phy_x550em_kx4:
2478 phy->ops.setup_link = NULL;
2479 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2480 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2482 case ixgbe_phy_x550em_kr:
2483 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2484 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2485 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2487 case ixgbe_phy_x550em_ext_t:
2488 /* If internal link mode is XFI, then setup iXFI internal link,
2489 * else setup KR now.
2491 phy->ops.setup_internal_link =
2492 ixgbe_setup_internal_phy_t_x550em;
2494 /* setup SW LPLU only for first revision of X550EM_x */
2495 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2496 !(IXGBE_FUSES0_REV_MASK &
2497 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2498 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2500 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2501 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2503 case ixgbe_phy_sgmii:
2504 phy->ops.setup_link = NULL;
2507 phy->ops.setup_link = ixgbe_setup_m88;
2508 phy->ops.reset = ixgbe_reset_phy_m88;
2517 * ixgbe_set_mdio_speed - Set MDIO clock speed
2518 * @hw: pointer to hardware structure
2520 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2524 switch (hw->device_id) {
2525 case IXGBE_DEV_ID_X550EM_X_10G_T:
2526 case IXGBE_DEV_ID_X550EM_A_SGMII:
2527 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2528 case IXGBE_DEV_ID_X550EM_A_1G_T:
2529 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2530 case IXGBE_DEV_ID_X550EM_A_10G_T:
2531 case IXGBE_DEV_ID_X550EM_A_SFP:
2532 case IXGBE_DEV_ID_X550EM_A_QSFP:
2533 /* Config MDIO clock speed before the first MDIO PHY access */
2534 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2535 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2536 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2544 * ixgbe_reset_hw_X550em - Perform hardware reset
2545 * @hw: pointer to hardware structure
2547 * Resets the hardware by resetting the transmit and receive units, masks
2548 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2551 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2553 ixgbe_link_speed link_speed;
2557 bool link_up = false;
2559 DEBUGFUNC("ixgbe_reset_hw_X550em");
2561 /* Call adapter stop to disable Tx/Rx and clear interrupts */
2562 status = hw->mac.ops.stop_adapter(hw);
2563 if (status != IXGBE_SUCCESS)
2566 /* flush pending Tx transactions */
2567 ixgbe_clear_tx_pending(hw);
2569 ixgbe_set_mdio_speed(hw);
2571 /* PHY ops must be identified and initialized prior to reset */
2572 status = hw->phy.ops.init(hw);
2574 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2577 /* start the external PHY */
2578 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2579 status = ixgbe_init_ext_t_x550em(hw);
2584 /* Setup SFP module if there is one present. */
2585 if (hw->phy.sfp_setup_needed) {
2586 status = hw->mac.ops.setup_sfp(hw);
2587 hw->phy.sfp_setup_needed = false;
2590 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2594 if (!hw->phy.reset_disable && hw->phy.ops.reset)
2595 hw->phy.ops.reset(hw);
2598 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
2599 * If link reset is used when link is up, it might reset the PHY when
2600 * mng is using it. If link is down or the flag to force full link
2601 * reset is set, then perform link reset.
2603 ctrl = IXGBE_CTRL_LNK_RST;
2604 if (!hw->force_full_reset) {
2605 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2607 ctrl = IXGBE_CTRL_RST;
2610 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2611 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2612 IXGBE_WRITE_FLUSH(hw);
2614 /* Poll for reset bit to self-clear meaning reset is complete */
2615 for (i = 0; i < 10; i++) {
2617 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2618 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2622 if (ctrl & IXGBE_CTRL_RST_MASK) {
2623 status = IXGBE_ERR_RESET_FAILED;
2624 DEBUGOUT("Reset polling failed to complete.\n");
2629 /* Double resets are required for recovery from certain error
2630 * conditions. Between resets, it is necessary to stall to
2631 * allow time for any pending HW events to complete.
2633 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2634 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2638 /* Store the permanent mac address */
2639 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2641 /* Store MAC address from RAR0, clear receive address registers, and
2642 * clear the multicast table. Also reset num_rar_entries to 128,
2643 * since we modify this value when programming the SAN MAC address.
2645 hw->mac.num_rar_entries = 128;
2646 hw->mac.ops.init_rx_addrs(hw);
2648 ixgbe_set_mdio_speed(hw);
2650 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2651 ixgbe_setup_mux_ctl(hw);
2657 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2658 * @hw: pointer to hardware structure
2660 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2665 status = hw->phy.ops.read_reg(hw,
2666 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2667 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2670 if (status != IXGBE_SUCCESS)
2673 /* If PHY FW reset completed bit is set then this is the first
2674 * SW instance after a power on so the PHY FW must be un-stalled.
2676 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2677 status = hw->phy.ops.read_reg(hw,
2678 IXGBE_MDIO_GLOBAL_RES_PR_10,
2679 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2682 if (status != IXGBE_SUCCESS)
2685 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2687 status = hw->phy.ops.write_reg(hw,
2688 IXGBE_MDIO_GLOBAL_RES_PR_10,
2689 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2692 if (status != IXGBE_SUCCESS)
2700 * ixgbe_setup_kr_x550em - Configure the KR PHY.
2701 * @hw: pointer to hardware structure
2703 * Configures the integrated KR PHY for X550EM_x.
2705 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2707 if (hw->mac.type != ixgbe_mac_X550EM_x)
2708 return IXGBE_SUCCESS;
2710 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2714 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2715 * @hw: pointer to hardware structure
2717 * Configure the external PHY and the integrated KR PHY for SFP support.
2719 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2720 ixgbe_link_speed speed,
2721 bool autoneg_wait_to_complete)
2724 u16 reg_slice, reg_val;
2725 bool setup_linear = false;
2726 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2728 /* Check if SFP module is supported and linear */
2729 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2731 /* If no SFP module present, then return success. Return success since
2732 * there is no reason to configure CS4227 and SFP not present error is
2733 * not excepted in the setup MAC link flow.
2735 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2736 return IXGBE_SUCCESS;
2738 if (ret_val != IXGBE_SUCCESS)
2741 /* Configure internal PHY for KR/KX. */
2742 ixgbe_setup_kr_speed_x550em(hw, speed);
2744 /* Configure CS4227 LINE side to proper mode. */
2745 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2746 (hw->bus.lan_id << 12);
2748 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2750 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2751 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2757 * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
2758 * @hw: pointer to hardware structure
2759 * @speed: the link speed to force
2761 * Configures the integrated PHY for native SFI mode. Used to connect the
2762 * internal PHY directly to an SFP cage, without autonegotiation.
2764 STATIC s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2766 struct ixgbe_mac_info *mac = &hw->mac;
2770 /* Disable all AN and force speed to 10G Serial. */
2771 status = mac->ops.read_iosf_sb_reg(hw,
2772 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2773 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2774 if (status != IXGBE_SUCCESS)
2777 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2778 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2779 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2780 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2782 /* Select forced link speed for internal PHY. */
2784 case IXGBE_LINK_SPEED_10GB_FULL:
2785 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
2787 case IXGBE_LINK_SPEED_1GB_FULL:
2788 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2791 /* Other link speeds are not supported by internal PHY. */
2792 return IXGBE_ERR_LINK_SETUP;
2795 status = mac->ops.write_iosf_sb_reg(hw,
2796 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2797 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2799 /* Toggle port SW reset by AN reset. */
2800 status = ixgbe_restart_an_internal_phy_x550em(hw);
2806 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2807 * @hw: pointer to hardware structure
2809 * Configure the the integrated PHY for SFP support.
2811 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2812 ixgbe_link_speed speed,
2813 bool autoneg_wait_to_complete)
2817 bool setup_linear = false;
2818 u32 reg_slice, reg_phy_int, slice_offset;
2820 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2822 /* Check if SFP module is supported and linear */
2823 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2825 /* If no SFP module present, then return success. Return success since
2826 * SFP not present error is not excepted in the setup MAC link flow.
2828 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2829 return IXGBE_SUCCESS;
2831 if (ret_val != IXGBE_SUCCESS)
2834 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2835 /* Configure internal PHY for native SFI based on module type */
2836 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2837 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2838 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int);
2840 if (ret_val != IXGBE_SUCCESS)
2843 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
2845 reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
2847 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2848 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2849 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2851 if (ret_val != IXGBE_SUCCESS)
2854 /* Setup SFI internal link. */
2855 ret_val = ixgbe_setup_sfi_x550a(hw, &speed);
2857 /* Configure internal PHY for KR/KX. */
2858 ixgbe_setup_kr_speed_x550em(hw, speed);
2860 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2862 DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2863 return IXGBE_ERR_PHY_ADDR_INVALID;
2866 /* Get external PHY device id */
2867 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_GLOBAL_ID_MSB,
2868 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
2870 if (ret_val != IXGBE_SUCCESS)
2873 /* When configuring quad port CS4223, the MAC instance is part
2874 * of the slice offset.
2876 if (reg_phy_ext == IXGBE_CS4223_PHY_ID)
2877 slice_offset = (hw->bus.lan_id +
2878 (hw->bus.instance_id << 1)) << 12;
2880 slice_offset = hw->bus.lan_id << 12;
2882 /* Configure CS4227/CS4223 LINE side to proper mode. */
2883 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2885 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2887 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2888 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2889 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2895 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2896 * @hw: pointer to hardware structure
2898 * iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2900 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2902 struct ixgbe_mac_info *mac = &hw->mac;
2906 /* Disable training protocol FSM. */
2907 status = mac->ops.read_iosf_sb_reg(hw,
2908 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2909 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2910 if (status != IXGBE_SUCCESS)
2912 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2913 status = mac->ops.write_iosf_sb_reg(hw,
2914 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2915 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2916 if (status != IXGBE_SUCCESS)
2919 /* Disable Flex from training TXFFE. */
2920 status = mac->ops.read_iosf_sb_reg(hw,
2921 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2922 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2923 if (status != IXGBE_SUCCESS)
2925 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2926 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2927 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2928 status = mac->ops.write_iosf_sb_reg(hw,
2929 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2930 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2931 if (status != IXGBE_SUCCESS)
2933 status = mac->ops.read_iosf_sb_reg(hw,
2934 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2935 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2936 if (status != IXGBE_SUCCESS)
2938 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2939 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2940 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2941 status = mac->ops.write_iosf_sb_reg(hw,
2942 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2943 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2944 if (status != IXGBE_SUCCESS)
2947 /* Enable override for coefficients. */
2948 status = mac->ops.read_iosf_sb_reg(hw,
2949 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2950 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2951 if (status != IXGBE_SUCCESS)
2953 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2954 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2955 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2956 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2957 status = mac->ops.write_iosf_sb_reg(hw,
2958 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2959 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2964 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2965 * @hw: pointer to hardware structure
2966 * @speed: the link speed to force
2968 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
2969 * internal and external PHY at a specific speed, without autonegotiation.
2971 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2973 struct ixgbe_mac_info *mac = &hw->mac;
2977 /* Disable AN and force speed to 10G Serial. */
2978 status = mac->ops.read_iosf_sb_reg(hw,
2979 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2980 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2981 if (status != IXGBE_SUCCESS)
2984 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2985 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2987 /* Select forced link speed for internal PHY. */
2989 case IXGBE_LINK_SPEED_10GB_FULL:
2990 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2992 case IXGBE_LINK_SPEED_1GB_FULL:
2993 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2996 /* Other link speeds are not supported by internal KR PHY. */
2997 return IXGBE_ERR_LINK_SETUP;
3000 status = mac->ops.write_iosf_sb_reg(hw,
3001 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3002 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3003 if (status != IXGBE_SUCCESS)
3006 /* Additional configuration needed for x550em_x */
3007 if (hw->mac.type == ixgbe_mac_X550EM_x) {
3008 status = ixgbe_setup_ixfi_x550em_x(hw);
3009 if (status != IXGBE_SUCCESS)
3013 /* Toggle port SW reset by AN reset. */
3014 status = ixgbe_restart_an_internal_phy_x550em(hw);
3020 * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
3021 * @hw: address of hardware structure
3022 * @link_up: address of boolean to indicate link status
3024 * Returns error code if unable to get link status.
3026 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
3033 /* read this twice back to back to indicate current status */
3034 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3035 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3037 if (ret != IXGBE_SUCCESS)
3040 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3041 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3043 if (ret != IXGBE_SUCCESS)
3046 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
3048 return IXGBE_SUCCESS;
3052 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
3053 * @hw: point to hardware structure
3055 * Configures the link between the integrated KR PHY and the external X557 PHY
3056 * The driver will call this function when it gets a link status change
3057 * interrupt from the X557 PHY. This function configures the link speed
3058 * between the PHYs to match the link speed of the BASE-T link.
3060 * A return of a non-zero value indicates an error, and the base driver should
3061 * not report link up.
3063 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
3065 ixgbe_link_speed force_speed;
3070 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3071 return IXGBE_ERR_CONFIG;
3073 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3074 /* If link is down, there is no setup necessary so return */
3075 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3076 if (status != IXGBE_SUCCESS)
3080 return IXGBE_SUCCESS;
3082 status = hw->phy.ops.read_reg(hw,
3083 IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3084 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3086 if (status != IXGBE_SUCCESS)
3089 /* If link is still down - no setup is required so return */
3090 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3091 if (status != IXGBE_SUCCESS)
3094 return IXGBE_SUCCESS;
3096 /* clear everything but the speed and duplex bits */
3097 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
3100 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
3101 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3103 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
3104 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3107 /* Internal PHY does not support anything else */
3108 return IXGBE_ERR_INVALID_LINK_SETTINGS;
3111 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
3113 speed = IXGBE_LINK_SPEED_10GB_FULL |
3114 IXGBE_LINK_SPEED_1GB_FULL;
3115 return ixgbe_setup_kr_speed_x550em(hw, speed);
3120 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
3121 * @hw: pointer to hardware structure
3123 * Configures the integrated KR PHY to use internal loopback mode.
3125 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
3130 /* Disable AN and force speed to 10G Serial. */
3131 status = hw->mac.ops.read_iosf_sb_reg(hw,
3132 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3133 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3134 if (status != IXGBE_SUCCESS)
3136 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3137 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3138 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3139 status = hw->mac.ops.write_iosf_sb_reg(hw,
3140 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3141 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3142 if (status != IXGBE_SUCCESS)
3145 /* Set near-end loopback clocks. */
3146 status = hw->mac.ops.read_iosf_sb_reg(hw,
3147 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3148 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3149 if (status != IXGBE_SUCCESS)
3151 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3152 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3153 status = hw->mac.ops.write_iosf_sb_reg(hw,
3154 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3155 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3156 if (status != IXGBE_SUCCESS)
3159 /* Set loopback enable. */
3160 status = hw->mac.ops.read_iosf_sb_reg(hw,
3161 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3162 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3163 if (status != IXGBE_SUCCESS)
3165 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3166 status = hw->mac.ops.write_iosf_sb_reg(hw,
3167 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3168 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3169 if (status != IXGBE_SUCCESS)
3172 /* Training bypass. */
3173 status = hw->mac.ops.read_iosf_sb_reg(hw,
3174 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3175 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3176 if (status != IXGBE_SUCCESS)
3178 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3179 status = hw->mac.ops.write_iosf_sb_reg(hw,
3180 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3181 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3187 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3188 * assuming that the semaphore is already obtained.
3189 * @hw: pointer to hardware structure
3190 * @offset: offset of word in the EEPROM to read
3191 * @data: word read from the EEPROM
3193 * Reads a 16 bit word from the EEPROM using the hostif.
3195 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
3197 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3198 struct ixgbe_hic_read_shadow_ram buffer;
3201 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3202 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3203 buffer.hdr.req.buf_lenh = 0;
3204 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3205 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3207 /* convert offset from words to bytes */
3208 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3210 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3212 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3216 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3217 IXGBE_HI_COMMAND_TIMEOUT);
3219 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3220 FW_NVM_DATA_OFFSET);
3223 hw->mac.ops.release_swfw_sync(hw, mask);
3228 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3229 * @hw: pointer to hardware structure
3230 * @offset: offset of word in the EEPROM to read
3231 * @words: number of words
3232 * @data: word(s) read from the EEPROM
3234 * Reads a 16 bit word(s) from the EEPROM using the hostif.
3236 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3237 u16 offset, u16 words, u16 *data)
3239 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3240 struct ixgbe_hic_read_shadow_ram buffer;
3241 u32 current_word = 0;
3246 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3248 /* Take semaphore for the entire operation. */
3249 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3251 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3255 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3256 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3258 words_to_read = words;
3260 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3261 buffer.hdr.req.buf_lenh = 0;
3262 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3263 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3265 /* convert offset from words to bytes */
3266 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3267 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3269 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3270 IXGBE_HI_COMMAND_TIMEOUT);
3273 DEBUGOUT("Host interface command failed\n");
3277 for (i = 0; i < words_to_read; i++) {
3278 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3280 u32 value = IXGBE_READ_REG(hw, reg);
3282 data[current_word] = (u16)(value & 0xffff);
3285 if (i < words_to_read) {
3287 data[current_word] = (u16)(value & 0xffff);
3291 words -= words_to_read;
3295 hw->mac.ops.release_swfw_sync(hw, mask);
3300 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3301 * @hw: pointer to hardware structure
3302 * @offset: offset of word in the EEPROM to write
3303 * @data: word write to the EEPROM
3305 * Write a 16 bit word to the EEPROM using the hostif.
3307 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3311 struct ixgbe_hic_write_shadow_ram buffer;
3313 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3315 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3316 buffer.hdr.req.buf_lenh = 0;
3317 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3318 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3321 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3323 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3325 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3327 IXGBE_HI_COMMAND_TIMEOUT, false);
3333 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3334 * @hw: pointer to hardware structure
3335 * @offset: offset of word in the EEPROM to write
3336 * @data: word write to the EEPROM
3338 * Write a 16 bit word to the EEPROM using the hostif.
3340 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3343 s32 status = IXGBE_SUCCESS;
3345 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3347 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3349 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3350 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3352 DEBUGOUT("write ee hostif failed to get semaphore");
3353 status = IXGBE_ERR_SWFW_SYNC;
3360 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3361 * @hw: pointer to hardware structure
3362 * @offset: offset of word in the EEPROM to write
3363 * @words: number of words
3364 * @data: word(s) write to the EEPROM
3366 * Write a 16 bit word(s) to the EEPROM using the hostif.
3368 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3369 u16 offset, u16 words, u16 *data)
3371 s32 status = IXGBE_SUCCESS;
3374 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3376 /* Take semaphore for the entire operation. */
3377 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3378 if (status != IXGBE_SUCCESS) {
3379 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3383 for (i = 0; i < words; i++) {
3384 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3387 if (status != IXGBE_SUCCESS) {
3388 DEBUGOUT("Eeprom buffered write failed\n");
3393 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3400 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3401 * @hw: pointer to hardware structure
3402 * @ptr: pointer offset in eeprom
3403 * @size: size of section pointed by ptr, if 0 first word will be used as size
3404 * @csum: address of checksum to update
3406 * Returns error status for any failure
3408 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3409 u16 size, u16 *csum, u16 *buffer,
3414 u16 length, bufsz, i, start;
3417 bufsz = sizeof(buf) / sizeof(buf[0]);
3419 /* Read a chunk at the pointer location */
3421 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3423 DEBUGOUT("Failed to read EEPROM image\n");
3428 if (buffer_size < ptr)
3429 return IXGBE_ERR_PARAM;
3430 local_buffer = &buffer[ptr];
3438 length = local_buffer[0];
3440 /* Skip pointer section if length is invalid. */
3441 if (length == 0xFFFF || length == 0 ||
3442 (ptr + length) >= hw->eeprom.word_size)
3443 return IXGBE_SUCCESS;
3446 if (buffer && ((u32)start + (u32)length > buffer_size))
3447 return IXGBE_ERR_PARAM;
3449 for (i = start; length; i++, length--) {
3450 if (i == bufsz && !buffer) {
3456 /* Read a chunk at the pointer location */
3457 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3460 DEBUGOUT("Failed to read EEPROM image\n");
3464 *csum += local_buffer[i];
3466 return IXGBE_SUCCESS;
3470 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3471 * @hw: pointer to hardware structure
3472 * @buffer: pointer to buffer containing calculated checksum
3473 * @buffer_size: size of buffer
3475 * Returns a negative error code on error, or the 16-bit checksum
3477 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3479 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3483 u16 pointer, i, size;
3485 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3487 hw->eeprom.ops.init_params(hw);
3490 /* Read pointer area */
3491 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3492 IXGBE_EEPROM_LAST_WORD + 1,
3495 DEBUGOUT("Failed to read EEPROM image\n");
3498 local_buffer = eeprom_ptrs;
3500 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3501 return IXGBE_ERR_PARAM;
3502 local_buffer = buffer;
3506 * For X550 hardware include 0x0-0x41 in the checksum, skip the
3507 * checksum word itself
3509 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3510 if (i != IXGBE_EEPROM_CHECKSUM)
3511 checksum += local_buffer[i];
3514 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
3515 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3517 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3518 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3521 pointer = local_buffer[i];
3523 /* Skip pointer section if the pointer is invalid. */
3524 if (pointer == 0xFFFF || pointer == 0 ||
3525 pointer >= hw->eeprom.word_size)
3529 case IXGBE_PCIE_GENERAL_PTR:
3530 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3532 case IXGBE_PCIE_CONFIG0_PTR:
3533 case IXGBE_PCIE_CONFIG1_PTR:
3534 size = IXGBE_PCIE_CONFIG_SIZE;
3541 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3542 buffer, buffer_size);
3547 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3549 return (s32)checksum;
3553 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3554 * @hw: pointer to hardware structure
3556 * Returns a negative error code on error, or the 16-bit checksum
3558 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3560 return ixgbe_calc_checksum_X550(hw, NULL, 0);
3564 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3565 * @hw: pointer to hardware structure
3566 * @checksum_val: calculated checksum
3568 * Performs checksum calculation and validates the EEPROM checksum. If the
3569 * caller does not need checksum_val, the value can be NULL.
3571 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3575 u16 read_checksum = 0;
3577 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3579 /* Read the first word from the EEPROM. If this times out or fails, do
3580 * not continue or we could be in for a very long wait while every
3583 status = hw->eeprom.ops.read(hw, 0, &checksum);
3585 DEBUGOUT("EEPROM read failed\n");
3589 status = hw->eeprom.ops.calc_checksum(hw);
3593 checksum = (u16)(status & 0xffff);
3595 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3600 /* Verify read checksum from EEPROM is the same as
3601 * calculated checksum
3603 if (read_checksum != checksum) {
3604 status = IXGBE_ERR_EEPROM_CHECKSUM;
3605 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3606 "Invalid EEPROM checksum");
3609 /* If the user cares, return the calculated checksum */
3611 *checksum_val = checksum;
3617 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3618 * @hw: pointer to hardware structure
3620 * After writing EEPROM to shadow RAM using EEWR register, software calculates
3621 * checksum and updates the EEPROM and instructs the hardware to update
3624 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3629 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3631 /* Read the first word from the EEPROM. If this times out or fails, do
3632 * not continue or we could be in for a very long wait while every
3635 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3637 DEBUGOUT("EEPROM read failed\n");
3641 status = ixgbe_calc_eeprom_checksum_X550(hw);
3645 checksum = (u16)(status & 0xffff);
3647 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3652 status = ixgbe_update_flash_X550(hw);
3658 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3659 * @hw: pointer to hardware structure
3661 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3663 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3665 s32 status = IXGBE_SUCCESS;
3666 union ixgbe_hic_hdr2 buffer;
3668 DEBUGFUNC("ixgbe_update_flash_X550");
3670 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3671 buffer.req.buf_lenh = 0;
3672 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3673 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3675 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3677 IXGBE_HI_COMMAND_TIMEOUT, false);
3683 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3684 * @hw: pointer to hardware structure
3686 * Determines physical layer capabilities of the current configuration.
3688 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3690 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3691 u16 ext_ability = 0;
3693 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3695 hw->phy.ops.identify(hw);
3697 switch (hw->phy.type) {
3698 case ixgbe_phy_x550em_kr:
3699 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3700 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3702 case ixgbe_phy_x550em_kx4:
3703 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3704 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3706 case ixgbe_phy_x550em_ext_t:
3707 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3708 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3710 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3711 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3712 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3713 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3719 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3720 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3722 return physical_layer;
3726 * ixgbe_get_bus_info_x550em - Set PCI bus info
3727 * @hw: pointer to hardware structure
3729 * Sets bus link width and speed to unknown because X550em is
3732 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3735 DEBUGFUNC("ixgbe_get_bus_info_x550em");
3737 hw->bus.width = ixgbe_bus_width_unknown;
3738 hw->bus.speed = ixgbe_bus_speed_unknown;
3740 hw->mac.ops.set_lan_id(hw);
3742 return IXGBE_SUCCESS;
3746 * ixgbe_disable_rx_x550 - Disable RX unit
3748 * Enables the Rx DMA unit for x550
3750 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3752 u32 rxctrl, pfdtxgswc;
3754 struct ixgbe_hic_disable_rxen fw_cmd;
3756 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3758 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3759 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3760 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3761 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3762 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3763 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3764 hw->mac.set_lben = true;
3766 hw->mac.set_lben = false;
3769 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3770 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3771 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3772 fw_cmd.port_number = (u8)hw->bus.lan_id;
3774 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3775 sizeof(struct ixgbe_hic_disable_rxen),
3776 IXGBE_HI_COMMAND_TIMEOUT, true);
3778 /* If we fail - disable RX using register write */
3780 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3781 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3782 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3783 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3790 * ixgbe_enter_lplu_x550em - Transition to low power states
3791 * @hw: pointer to hardware structure
3793 * Configures Low Power Link Up on transition to low power states
3794 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3795 * X557 PHY immediately prior to entering LPLU.
3797 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3799 u16 an_10g_cntl_reg, autoneg_reg, speed;
3801 ixgbe_link_speed lcd_speed;
3805 /* SW LPLU not required on later HW revisions. */
3806 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3807 (IXGBE_FUSES0_REV_MASK &
3808 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3809 return IXGBE_SUCCESS;
3811 /* If blocked by MNG FW, then don't restart AN */
3812 if (ixgbe_check_reset_blocked(hw))
3813 return IXGBE_SUCCESS;
3815 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3816 if (status != IXGBE_SUCCESS)
3819 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3821 if (status != IXGBE_SUCCESS)
3824 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3825 * disabled, then force link down by entering low power mode.
3827 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3828 !(hw->wol_enabled || ixgbe_mng_present(hw)))
3829 return ixgbe_set_copper_phy_power(hw, FALSE);
3832 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3834 if (status != IXGBE_SUCCESS)
3837 /* If no valid LCD link speed, then force link down and exit. */
3838 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3839 return ixgbe_set_copper_phy_power(hw, FALSE);
3841 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3842 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3845 if (status != IXGBE_SUCCESS)
3848 /* If no link now, speed is invalid so take link down */
3849 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3850 if (status != IXGBE_SUCCESS)
3851 return ixgbe_set_copper_phy_power(hw, false);
3853 /* clear everything but the speed bits */
3854 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3856 /* If current speed is already LCD, then exit. */
3857 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3858 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3859 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3860 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3863 /* Clear AN completed indication */
3864 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3865 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3868 if (status != IXGBE_SUCCESS)
3871 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3872 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3875 if (status != IXGBE_SUCCESS)
3878 status = hw->phy.ops.read_reg(hw,
3879 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3880 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3883 if (status != IXGBE_SUCCESS)
3886 save_autoneg = hw->phy.autoneg_advertised;
3888 /* Setup link at least common link speed */
3889 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3891 /* restore autoneg from before setting lplu speed */
3892 hw->phy.autoneg_advertised = save_autoneg;
3898 * ixgbe_get_lcd_x550em - Determine lowest common denominator
3899 * @hw: pointer to hardware structure
3900 * @lcd_speed: pointer to lowest common link speed
3902 * Determine lowest common link speed with link partner.
3904 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3908 u16 word = hw->eeprom.ctrl_word_3;
3910 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3912 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3913 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3916 if (status != IXGBE_SUCCESS)
3919 /* If link partner advertised 1G, return 1G */
3920 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3921 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3925 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3926 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3927 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3930 /* Link partner not capable of lower speeds, return 10G */
3931 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3936 * ixgbe_setup_fc_X550em - Set up flow control
3937 * @hw: pointer to hardware structure
3939 * Called at init time to set up flow control.
3941 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3943 s32 ret_val = IXGBE_SUCCESS;
3944 u32 pause, asm_dir, reg_val;
3946 DEBUGFUNC("ixgbe_setup_fc_X550em");
3948 /* Validate the requested mode */
3949 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3950 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3951 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3952 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3956 /* 10gig parts do not have a word in the EEPROM to determine the
3957 * default flow control setting, so we explicitly set it to full.
3959 if (hw->fc.requested_mode == ixgbe_fc_default)
3960 hw->fc.requested_mode = ixgbe_fc_full;
3962 /* Determine PAUSE and ASM_DIR bits. */
3963 switch (hw->fc.requested_mode) {
3968 case ixgbe_fc_tx_pause:
3972 case ixgbe_fc_rx_pause:
3973 /* Rx Flow control is enabled and Tx Flow control is
3974 * disabled by software override. Since there really
3975 * isn't a way to advertise that we are capable of RX
3976 * Pause ONLY, we will advertise that we support both
3977 * symmetric and asymmetric Rx PAUSE, as such we fall
3978 * through to the fc_full statement. Later, we will
3979 * disable the adapter's ability to send PAUSE frames.
3986 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3987 "Flow control param set incorrectly\n");
3988 ret_val = IXGBE_ERR_CONFIG;
3992 switch (hw->device_id) {
3993 case IXGBE_DEV_ID_X550EM_X_KR:
3994 case IXGBE_DEV_ID_X550EM_A_KR:
3995 case IXGBE_DEV_ID_X550EM_A_KR_L:
3996 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
3997 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3998 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3999 if (ret_val != IXGBE_SUCCESS)
4001 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4002 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4004 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4006 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4007 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
4008 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4009 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
4011 /* This device does not fully support AN. */
4012 hw->fc.disable_fc_autoneg = true;
4023 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
4024 * @hw: pointer to hardware structure
4026 * Enable flow control according to IEEE clause 37.
4028 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
4030 u32 link_s1, lp_an_page_low, an_cntl_1;
4031 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4032 ixgbe_link_speed speed;
4035 /* AN should have completed when the cable was plugged in.
4036 * Look for reasons to bail out. Bail out if:
4037 * - FC autoneg is disabled, or if
4040 if (hw->fc.disable_fc_autoneg) {
4041 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4042 "Flow control autoneg is disabled");
4046 hw->mac.ops.check_link(hw, &speed, &link_up, false);
4048 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4052 /* Check at auto-negotiation has completed */
4053 status = hw->mac.ops.read_iosf_sb_reg(hw,
4054 IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4055 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4057 if (status != IXGBE_SUCCESS ||
4058 (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4059 DEBUGOUT("Auto-Negotiation did not complete\n");
4060 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4064 /* Read the 10g AN autoc and LP ability registers and resolve
4065 * local flow control settings accordingly
4067 status = hw->mac.ops.read_iosf_sb_reg(hw,
4068 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4069 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
4071 if (status != IXGBE_SUCCESS) {
4072 DEBUGOUT("Auto-Negotiation did not complete\n");
4076 status = hw->mac.ops.read_iosf_sb_reg(hw,
4077 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
4078 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
4080 if (status != IXGBE_SUCCESS) {
4081 DEBUGOUT("Auto-Negotiation did not complete\n");
4085 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
4086 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
4087 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
4088 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
4089 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
4092 if (status == IXGBE_SUCCESS) {
4093 hw->fc.fc_was_autonegged = true;
4095 hw->fc.fc_was_autonegged = false;
4096 hw->fc.current_mode = hw->fc.requested_mode;
4101 * ixgbe_fc_autoneg_fiber_x550em_a - Enable flow control IEEE clause 37
4102 * @hw: pointer to hardware structure
4104 * Enable flow control according to IEEE clause 37.
4106 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
4108 u32 link_s1, pcs_an_lp, pcs_an;
4109 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4110 ixgbe_link_speed speed;
4113 /* AN should have completed when the cable was plugged in.
4114 * Look for reasons to bail out. Bail out if:
4115 * - FC autoneg is disabled, or if
4118 if (hw->fc.disable_fc_autoneg) {
4119 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4120 "Flow control autoneg is disabled");
4124 hw->mac.ops.check_link(hw, &speed, &link_up, false);
4126 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4130 /* Check if auto-negotiation has completed */
4131 status = hw->mac.ops.read_iosf_sb_reg(hw,
4132 IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4133 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4135 if (status != IXGBE_SUCCESS ||
4136 (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4137 DEBUGOUT("Auto-Negotiation did not complete\n");
4138 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4142 /* Determine advertised flow control */
4143 status = hw->mac.ops.read_iosf_sb_reg(hw,
4144 IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id),
4145 IXGBE_SB_IOSF_TARGET_KR_PHY, &pcs_an);
4147 if (status != IXGBE_SUCCESS) {
4148 DEBUGOUT("Auto-Negotiation did not complete\n");
4152 /* Determine link parter flow control */
4153 status = hw->mac.ops.read_iosf_sb_reg(hw,
4154 IXGBE_KRM_PCS_KX_AN_LP(hw->bus.lan_id),
4155 IXGBE_SB_IOSF_TARGET_KR_PHY, &pcs_an_lp);
4157 if (status != IXGBE_SUCCESS) {
4158 DEBUGOUT("Auto-Negotiation did not complete\n");
4162 status = ixgbe_negotiate_fc(hw, pcs_an, pcs_an_lp,
4163 IXGBE_KRM_PCS_KX_AN_SYM_PAUSE,
4164 IXGBE_KRM_PCS_KX_AN_ASM_PAUSE,
4165 IXGBE_KRM_PCS_KX_AN_LP_SYM_PAUSE,
4166 IXGBE_KRM_PCS_KX_AN_LP_ASM_PAUSE);
4169 if (status == IXGBE_SUCCESS) {
4170 hw->fc.fc_was_autonegged = true;
4172 hw->fc.fc_was_autonegged = false;
4173 hw->fc.current_mode = hw->fc.requested_mode;
4178 * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
4179 * @hw: pointer to hardware structure
4181 * Enable flow control according to IEEE clause 37.
4183 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
4185 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4186 u16 reg, pcs_an_lp, pcs_an;
4187 ixgbe_link_speed speed;
4190 /* AN should have completed when the cable was plugged in.
4191 * Look for reasons to bail out. Bail out if:
4192 * - FC autoneg is disabled, or if
4195 if (hw->fc.disable_fc_autoneg) {
4196 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4197 "Flow control autoneg is disabled");
4201 hw->mac.ops.check_link(hw, &speed, &link_up, false);
4203 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4207 /* Check if auto-negotiation has completed */
4208 status = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_STATUS,
4209 IXGBE_MDIO_ZERO_DEV_TYPE, ®);
4210 if (status != IXGBE_SUCCESS ||
4211 (reg & IXGBE_M88E1500_COPPER_STATUS_AN_DONE) == 0) {
4212 DEBUGOUT("Auto-Negotiation did not complete\n");
4213 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4217 /* Get the advertized flow control */
4218 status = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_AN,
4219 IXGBE_MDIO_ZERO_DEV_TYPE, &pcs_an);
4220 if (status != IXGBE_SUCCESS)
4223 /* Get link partner's flow control */
4224 status = hw->phy.ops.read_reg(hw,
4225 IXGBE_M88E1500_COPPER_AN_LP_ABILITY,
4226 IXGBE_MDIO_ZERO_DEV_TYPE, &pcs_an_lp);
4227 if (status != IXGBE_SUCCESS)
4230 /* Negotiate the flow control */
4231 status = ixgbe_negotiate_fc(hw, (u32)pcs_an, (u32)pcs_an_lp,
4232 IXGBE_M88E1500_COPPER_AN_PAUSE,
4233 IXGBE_M88E1500_COPPER_AN_AS_PAUSE,
4234 IXGBE_M88E1500_COPPER_AN_LP_PAUSE,
4235 IXGBE_M88E1500_COPPER_AN_LP_AS_PAUSE);
4238 if (status == IXGBE_SUCCESS) {
4239 hw->fc.fc_was_autonegged = true;
4241 hw->fc.fc_was_autonegged = false;
4242 hw->fc.current_mode = hw->fc.requested_mode;
4247 * ixgbe_setup_fc_sgmii_x550em_a - Set up flow control
4248 * @hw: pointer to hardware structure
4250 * Called at init time to set up flow control.
4252 s32 ixgbe_setup_fc_sgmii_x550em_a(struct ixgbe_hw *hw)
4257 /* Validate the requested mode */
4258 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4259 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4260 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4261 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4264 if (hw->fc.requested_mode == ixgbe_fc_default)
4265 hw->fc.requested_mode = ixgbe_fc_full;
4267 /* Read contents of the Auto-Negotiation register, page 0 reg 4 */
4268 rc = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_AN,
4269 IXGBE_MDIO_ZERO_DEV_TYPE, ®);
4273 /* Disable all the settings related to Flow control Auto-negotiation */
4274 reg &= ~IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4275 reg &= ~IXGBE_M88E1500_COPPER_AN_PAUSE;
4277 /* Configure the Asymmetric and symmetric pause according to the user
4280 switch (hw->fc.requested_mode) {
4282 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
4283 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4285 case ixgbe_fc_rx_pause:
4286 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
4287 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4289 case ixgbe_fc_tx_pause:
4290 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4296 /* Write back to the Auto-Negotiation register with newly configured
4299 hw->phy.ops.write_reg(hw, IXGBE_M88E1500_COPPER_AN,
4300 IXGBE_MDIO_ZERO_DEV_TYPE, reg);
4302 /* In this section of the code we restart Auto-negotiation */
4304 /* Read the CONTROL register, Page 0 reg 0 */
4305 rc = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_CTRL,
4306 IXGBE_MDIO_ZERO_DEV_TYPE, ®);
4310 /* Set the bit to restart Auto-Neg. The bit to enable Auto-neg is ON
4313 reg |= IXGBE_M88E1500_COPPER_CTRL_RESTART_AN;
4315 /* write the new values to the register to restart Auto-Negotiation */
4316 hw->phy.ops.write_reg(hw, IXGBE_M88E1500_COPPER_CTRL,
4317 IXGBE_MDIO_ZERO_DEV_TYPE, reg);
4324 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4325 * @hw: pointer to hardware structure
4327 * Called at init time to set up flow control.
4329 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4331 s32 status = IXGBE_SUCCESS;
4334 DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4336 /* Validate the requested mode */
4337 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4338 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4339 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4340 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4343 if (hw->fc.requested_mode == ixgbe_fc_default)
4344 hw->fc.requested_mode = ixgbe_fc_full;
4346 /* Set up the 1G and 10G flow control advertisement registers so the
4347 * HW will be able to do FC autoneg once the cable is plugged in. If
4348 * we link at 10G, the 1G advertisement is harmless and vice versa.
4350 status = hw->mac.ops.read_iosf_sb_reg(hw,
4351 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4352 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4354 if (status != IXGBE_SUCCESS) {
4355 DEBUGOUT("Auto-Negotiation did not complete\n");
4359 /* The possible values of fc.requested_mode are:
4360 * 0: Flow control is completely disabled
4361 * 1: Rx flow control is enabled (we can receive pause frames,
4362 * but not send pause frames).
4363 * 2: Tx flow control is enabled (we can send pause frames but
4364 * we do not support receiving pause frames).
4365 * 3: Both Rx and Tx flow control (symmetric) are enabled.
4368 switch (hw->fc.requested_mode) {
4370 /* Flow control completely disabled by software override. */
4371 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4372 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4374 case ixgbe_fc_tx_pause:
4375 /* Tx Flow control is enabled, and Rx Flow control is
4376 * disabled by software override.
4378 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4379 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4381 case ixgbe_fc_rx_pause:
4382 /* Rx Flow control is enabled and Tx Flow control is
4383 * disabled by software override. Since there really
4384 * isn't a way to advertise that we are capable of RX
4385 * Pause ONLY, we will advertise that we support both
4386 * symmetric and asymmetric Rx PAUSE, as such we fall
4387 * through to the fc_full statement. Later, we will
4388 * disable the adapter's ability to send PAUSE frames.
4391 /* Flow control (both Rx and Tx) is enabled by SW override. */
4392 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4393 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4396 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4397 "Flow control param set incorrectly\n");
4398 return IXGBE_ERR_CONFIG;
4401 status = hw->mac.ops.write_iosf_sb_reg(hw,
4402 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4403 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4405 /* Restart auto-negotiation. */
4406 status = ixgbe_restart_an_internal_phy_x550em(hw);
4412 * ixgbe_setup_fc_fiber_x550em_a - Set up flow control
4413 * @hw: pointer to hardware structure
4415 * Called at init time to set up flow control.
4417 s32 ixgbe_setup_fc_fiber_x550em_a(struct ixgbe_hw *hw)
4419 struct ixgbe_mac_info *mac = &hw->mac;
4420 s32 rc = IXGBE_SUCCESS;
4421 u32 an_cntl4, lctrl, pcs_an;
4423 DEBUGFUNC("ixgbe_setup_fc_fiber_x550em_a");
4425 /* Validate the requested mode */
4426 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4427 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4428 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4429 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4432 /* Enable clause 37 auto-negotiation in KRM_LINK_CTRL_1 */
4433 if (hw->fc.requested_mode == ixgbe_fc_default)
4434 hw->fc.requested_mode = ixgbe_fc_full;
4436 rc = mac->ops.read_iosf_sb_reg(hw,
4437 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4438 IXGBE_SB_IOSF_TARGET_KR_PHY, &lctrl);
4442 lctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
4443 lctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
4445 rc = mac->ops.write_iosf_sb_reg(hw,
4446 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4447 IXGBE_SB_IOSF_TARGET_KR_PHY, lctrl);
4451 /* Enable clause 37 over 73 in KRM_AN_CNTL_4 */
4452 rc = mac->ops.read_iosf_sb_reg(hw,
4453 IXGBE_KRM_AN_CNTL_4(hw->bus.lan_id),
4454 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl4);
4458 an_cntl4 |= IXGBE_KRM_AN_CNTL_4_ECSR_AN37_OVER_73;
4460 rc = mac->ops.write_iosf_sb_reg(hw,
4461 IXGBE_KRM_AN_CNTL_4(hw->bus.lan_id),
4462 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl4);
4466 rc = hw->mac.ops.read_iosf_sb_reg(hw,
4467 IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id),
4468 IXGBE_SB_IOSF_TARGET_KR_PHY, &pcs_an);
4473 /* The possible values of fc.requested_mode are:
4474 * 0: Flow control is completely disabled
4475 * 1: Rx flow control is enabled (we can receive pause frames,
4476 * but not send pause frames).
4477 * 2: Tx flow control is enabled (we can send pause frames but
4478 * we do not support receiving pause frames).
4479 * 3: Both Rx and Tx flow control (symmetric) are enabled.
4482 switch (hw->fc.requested_mode) {
4484 /* Flow control completely disabled by software override. */
4485 pcs_an &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4486 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4488 case ixgbe_fc_tx_pause:
4489 /* Tx Flow control is enabled, and Rx Flow control is
4490 * disabled by software override.
4492 pcs_an |= IXGBE_KRM_PCS_KX_AN_ASM_PAUSE;
4493 pcs_an &= ~IXGBE_KRM_PCS_KX_AN_SYM_PAUSE;
4495 case ixgbe_fc_rx_pause:
4496 /* Rx Flow control is enabled and Tx Flow control is
4497 * disabled by software override. Since there really
4498 * isn't a way to advertise that we are capable of RX
4499 * Pause ONLY, we will advertise that we support both
4500 * symmetric and asymmetric Rx PAUSE, as such we fall
4501 * through to the fc_full statement. Later, we will
4502 * disable the adapter's ability to send PAUSE frames.
4505 /* Flow control (both Rx and Tx) is enabled by SW override. */
4506 pcs_an |= IXGBE_KRM_PCS_KX_AN_SYM_PAUSE |
4507 IXGBE_KRM_PCS_KX_AN_ASM_PAUSE;
4510 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4511 "Flow control param set incorrectly\n");
4512 return IXGBE_ERR_CONFIG;
4515 rc = hw->mac.ops.write_iosf_sb_reg(hw,
4516 IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id),
4517 IXGBE_SB_IOSF_TARGET_KR_PHY, pcs_an);
4519 /* Restart auto-negotiation. */
4520 rc = ixgbe_restart_an_internal_phy_x550em(hw);
4526 * ixgbe_set_mux - Set mux for port 1 access with CS4227
4527 * @hw: pointer to hardware structure
4528 * @state: set mux if 1, clear if 0
4530 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4534 if (!hw->bus.lan_id)
4536 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4538 esdp |= IXGBE_ESDP_SDP1;
4540 esdp &= ~IXGBE_ESDP_SDP1;
4541 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4542 IXGBE_WRITE_FLUSH(hw);
4546 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4547 * @hw: pointer to hardware structure
4548 * @mask: Mask to specify which semaphore to acquire
4550 * Acquires the SWFW semaphore and sets the I2C MUX
4552 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4556 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4558 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4562 if (mask & IXGBE_GSSR_I2C_MASK)
4563 ixgbe_set_mux(hw, 1);
4565 return IXGBE_SUCCESS;
4569 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4570 * @hw: pointer to hardware structure
4571 * @mask: Mask to specify which semaphore to release
4573 * Releases the SWFW semaphore and sets the I2C MUX
4575 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4577 DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4579 if (mask & IXGBE_GSSR_I2C_MASK)
4580 ixgbe_set_mux(hw, 0);
4582 ixgbe_release_swfw_sync_X540(hw, mask);
4586 * ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4587 * @hw: pointer to hardware structure
4588 * @mask: Mask to specify which semaphore to acquire
4590 * Acquires the SWFW semaphore and get the shared phy token as needed
4592 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4594 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4595 int retries = FW_PHY_TOKEN_RETRIES;
4596 s32 status = IXGBE_SUCCESS;
4598 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4601 status = IXGBE_SUCCESS;
4603 status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4606 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4607 return IXGBE_SUCCESS;
4609 status = ixgbe_get_phy_token(hw);
4610 if (status == IXGBE_SUCCESS)
4611 return IXGBE_SUCCESS;
4614 ixgbe_release_swfw_sync_X540(hw, hmask);
4615 if (status != IXGBE_ERR_TOKEN_RETRY)
4623 * ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4624 * @hw: pointer to hardware structure
4625 * @mask: Mask to specify which semaphore to release
4627 * Releases the SWFW semaphore and puts the shared phy token as needed
4629 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4631 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4633 DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4635 if (mask & IXGBE_GSSR_TOKEN_SM)
4636 ixgbe_put_phy_token(hw);
4639 ixgbe_release_swfw_sync_X540(hw, hmask);
4643 * ixgbe_read_phy_reg_x550a - Reads specified PHY register
4644 * @hw: pointer to hardware structure
4645 * @reg_addr: 32 bit address of PHY register to read
4646 * @phy_data: Pointer to read data from PHY register
4648 * Reads a value from a specified PHY register using the SWFW lock and PHY
4649 * Token. The PHY Token is needed since the MDIO is shared between to MAC
4652 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4653 u32 device_type, u16 *phy_data)
4656 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4658 DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4660 if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4661 return IXGBE_ERR_SWFW_SYNC;
4663 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4665 hw->mac.ops.release_swfw_sync(hw, mask);
4671 * ixgbe_write_phy_reg_x550a - Writes specified PHY register
4672 * @hw: pointer to hardware structure
4673 * @reg_addr: 32 bit PHY register to write
4674 * @device_type: 5 bit device type
4675 * @phy_data: Data to write to the PHY register
4677 * Writes a value to specified PHY register using the SWFW lock and PHY Token.
4678 * The PHY Token is needed since the MDIO is shared between to MAC instances.
4680 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4681 u32 device_type, u16 phy_data)
4684 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4686 DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4688 if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4689 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
4691 hw->mac.ops.release_swfw_sync(hw, mask);
4693 status = IXGBE_ERR_SWFW_SYNC;
4700 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4701 * @hw: pointer to hardware structure
4703 * Handle external Base T PHY interrupt. If high temperature
4704 * failure alarm then return error, else if link status change
4705 * then setup internal/external PHY link
4707 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4708 * failure alarm, else return PHY access status.
4710 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4715 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4717 if (status != IXGBE_SUCCESS)
4721 return ixgbe_setup_internal_phy(hw);
4723 return IXGBE_SUCCESS;
4727 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4728 * @hw: pointer to hardware structure
4729 * @speed: new link speed
4730 * @autoneg_wait_to_complete: true when waiting for completion is needed
4732 * Setup internal/external PHY link speed based on link speed, then set
4733 * external PHY auto advertised link speed.
4735 * Returns error status for any failure
4737 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4738 ixgbe_link_speed speed,
4739 bool autoneg_wait_to_complete)
4742 ixgbe_link_speed force_speed;
4744 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4746 /* Setup internal/external PHY link speed to iXFI (10G), unless
4747 * only 1G is auto advertised then setup KX link.
4749 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4750 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4752 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4754 /* If internal link mode is XFI, then setup XFI internal link. */
4755 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4756 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4758 if (status != IXGBE_SUCCESS)
4762 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4766 * ixgbe_check_link_t_X550em - Determine link and speed status
4767 * @hw: pointer to hardware structure
4768 * @speed: pointer to link speed
4769 * @link_up: true when link is up
4770 * @link_up_wait_to_complete: bool used to wait for link up or not
4772 * Check that both the MAC and X557 external PHY have link.
4774 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4775 bool *link_up, bool link_up_wait_to_complete)
4780 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4781 return IXGBE_ERR_CONFIG;
4783 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4784 link_up_wait_to_complete);
4786 /* If check link fails or MAC link is not up, then return */
4787 if (status != IXGBE_SUCCESS || !(*link_up))
4790 /* MAC link is up, so check external PHY link.
4791 * Read this twice back to back to indicate current status.
4793 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4794 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4797 if (status != IXGBE_SUCCESS)
4800 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4801 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4804 if (status != IXGBE_SUCCESS)
4807 /* If external PHY link is not up, then indicate link not up */
4808 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4811 return IXGBE_SUCCESS;
4815 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4816 * @hw: pointer to hardware structure
4818 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4822 status = ixgbe_reset_phy_generic(hw);
4824 if (status != IXGBE_SUCCESS)
4827 /* Configure Link Status Alarm and Temperature Threshold interrupts */
4828 return ixgbe_enable_lasi_ext_t_x550em(hw);
4832 * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4833 * @hw: pointer to hardware structure
4834 * @led_idx: led number to turn on
4836 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4840 DEBUGFUNC("ixgbe_led_on_t_X550em");
4842 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4843 return IXGBE_ERR_PARAM;
4845 /* To turn on the LED, set mode to ON. */
4846 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4847 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4848 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4849 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4850 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4852 return IXGBE_SUCCESS;
4856 * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4857 * @hw: pointer to hardware structure
4858 * @led_idx: led number to turn off
4860 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4864 DEBUGFUNC("ixgbe_led_off_t_X550em");
4866 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4867 return IXGBE_ERR_PARAM;
4869 /* To turn on the LED, set mode to ON. */
4870 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4871 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4872 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4873 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4874 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4876 return IXGBE_SUCCESS;