drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42 static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  43 static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  44
  45 /**
  46  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  47  *  @hw: pointer to hardware structure
  48  *
  49  *  Initialize the function pointers and assign the MAC type for X550.
  50  *  Does not touch the hardware.
  51  **/
  52 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  53 {
  54         struct ixgbe_mac_info *mac = &hw->mac;
  55         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  56         s32 ret_val;
  57
  58         DEBUGFUNC("ixgbe_init_ops_X550");
  59
  60         ret_val = ixgbe_init_ops_X540(hw);
  61         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  62         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  63         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  64         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  65         mac->ops.set_source_address_pruning =
  66                         ixgbe_set_source_address_pruning_X550;
  67         mac->ops.set_ethertype_anti_spoofing =
  68                         ixgbe_set_ethertype_anti_spoofing_X550;
  69
  70         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  71         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  72         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  73         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  74         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  75         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  76         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  77         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  78         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  79
  80         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  81         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  82         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  83         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  84         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  85         switch (hw->device_id) {
  86         case IXGBE_DEV_ID_X550EM_X_10G_T:
  87         case IXGBE_DEV_ID_X550EM_A_10G_T:
  88                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  89                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  90                 break;
  91         default:
  92                 break;
  93         }
  94         return ret_val;
  95 }
  96
  97 /**
  98  * ixgbe_read_cs4227 - Read CS4227 register
  99  * @hw: pointer to hardware structure
 100  * @reg: register number to write
 101  * @value: pointer to receive value read
 102  *
 103  * Returns status code
 104  **/
 105 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
 106 {
 107         return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 108 }
 109
 110 /**
 111  * ixgbe_write_cs4227 - Write CS4227 register
 112  * @hw: pointer to hardware structure
 113  * @reg: register number to write
 114  * @value: value to write to register
 115  *
 116  * Returns status code
 117  **/
 118 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 119 {
 120         return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 121 }
 122
 123 /**
 124  * ixgbe_read_pe - Read register from port expander
 125  * @hw: pointer to hardware structure
 126  * @reg: register number to read
 127  * @value: pointer to receive read value
 128  *
 129  * Returns status code
 130  **/
 131 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 132 {
 133         s32 status;
 134
 135         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 136         if (status != IXGBE_SUCCESS)
 137                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 138                               "port expander access failed with %d\n", status);
 139         return status;
 140 }
 141
 142 /**
 143  * ixgbe_write_pe - Write register to port expander
 144  * @hw: pointer to hardware structure
 145  * @reg: register number to write
 146  * @value: value to write
 147  *
 148  * Returns status code
 149  **/
 150 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 151 {
 152         s32 status;
 153
 154         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 155         if (status != IXGBE_SUCCESS)
 156                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 157                               "port expander access failed with %d\n", status);
 158         return status;
 159 }
 160
 161 /**
 162  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 163  * @hw: pointer to hardware structure
 164  *
 165  * This function assumes that the caller has acquired the proper semaphore.
 166  * Returns error code
 167  **/
 168 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 169 {
 170         s32 status;
 171         u32 retry;
 172         u16 value;
 173         u8 reg;
 174
 175         /* Trigger hard reset. */
 176         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 177         if (status != IXGBE_SUCCESS)
 178                 return status;
 179         reg |= IXGBE_PE_BIT1;
 180         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 181         if (status != IXGBE_SUCCESS)
 182                 return status;
 183
 184         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 185         if (status != IXGBE_SUCCESS)
 186                 return status;
 187         reg &= ~IXGBE_PE_BIT1;
 188         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 189         if (status != IXGBE_SUCCESS)
 190                 return status;
 191
 192         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 193         if (status != IXGBE_SUCCESS)
 194                 return status;
 195         reg &= ~IXGBE_PE_BIT1;
 196         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 197         if (status != IXGBE_SUCCESS)
 198                 return status;
 199
 200         usec_delay(IXGBE_CS4227_RESET_HOLD);
 201
 202         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 203         if (status != IXGBE_SUCCESS)
 204                 return status;
 205         reg |= IXGBE_PE_BIT1;
 206         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 207         if (status != IXGBE_SUCCESS)
 208                 return status;
 209
 210         /* Wait for the reset to complete. */
 211         msec_delay(IXGBE_CS4227_RESET_DELAY);
 212         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 213                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 214                                            &value);
 215                 if (status == IXGBE_SUCCESS &&
 216                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 217                         break;
 218                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 219         }
 220         if (retry == IXGBE_CS4227_RETRIES) {
 221                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 222                         "CS4227 reset did not complete.");
 223                 return IXGBE_ERR_PHY;
 224         }
 225
 226         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 227         if (status != IXGBE_SUCCESS ||
 228             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 229                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 230                         "CS4227 EEPROM did not load successfully.");
 231                 return IXGBE_ERR_PHY;
 232         }
 233
 234         return IXGBE_SUCCESS;
 235 }
 236
 237 /**
 238  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 239  * @hw: pointer to hardware structure
 240  **/
 241 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 242 {
 243         s32 status = IXGBE_SUCCESS;
 244         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 245         u16 value = 0;
 246         u8 retry;
 247
 248         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 249                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 250                 if (status != IXGBE_SUCCESS) {
 251                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 252                                 "semaphore failed with %d", status);
 253                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 254                         continue;
 255                 }
 256
 257                 /* Get status of reset flow. */
 258                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 259
 260                 if (status == IXGBE_SUCCESS &&
 261                     value == IXGBE_CS4227_RESET_COMPLETE)
 262                         goto out;
 263
 264                 if (status != IXGBE_SUCCESS ||
 265                     value != IXGBE_CS4227_RESET_PENDING)
 266                         break;
 267
 268                 /* Reset is pending. Wait and check again. */
 269                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 270                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 271         }
 272
 273         /* If still pending, assume other instance failed. */
 274         if (retry == IXGBE_CS4227_RETRIES) {
 275                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 276                 if (status != IXGBE_SUCCESS) {
 277                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 278                                       "semaphore failed with %d", status);
 279                         return;
 280                 }
 281         }
 282
 283         /* Reset the CS4227. */
 284         status = ixgbe_reset_cs4227(hw);
 285         if (status != IXGBE_SUCCESS) {
 286                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 287                         "CS4227 reset failed: %d", status);
 288                 goto out;
 289         }
 290
 291         /* Reset takes so long, temporarily release semaphore in case the
 292          * other driver instance is waiting for the reset indication.
 293          */
 294         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 295                            IXGBE_CS4227_RESET_PENDING);
 296         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 297         msec_delay(10);
 298         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 299         if (status != IXGBE_SUCCESS) {
 300                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 301                         "semaphore failed with %d", status);
 302                 return;
 303         }
 304
 305         /* Record completion for next time. */
 306         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 307                 IXGBE_CS4227_RESET_COMPLETE);
 308
 309 out:
 310         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 311         msec_delay(hw->eeprom.semaphore_delay);
 312 }
 313
 314 /**
 315  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 316  * @hw: pointer to hardware structure
 317  **/
 318 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 319 {
 320         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 321
 322         if (hw->bus.lan_id) {
 323                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 324                 esdp |= IXGBE_ESDP_SDP1_DIR;
 325         }
 326         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 327         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 328         IXGBE_WRITE_FLUSH(hw);
 329 }
 330
 331 /**
 332  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 333  * @hw: pointer to hardware structure
 334  *
 335  * Returns error code
 336  */
 337 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 338 {
 339         switch (hw->device_id) {
 340         case IXGBE_DEV_ID_X550EM_A_SFP:
 341                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_TOKEN_SM;
 342                 if (hw->bus.lan_id)
 343                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 344                 else
 345                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 346                 return ixgbe_identify_module_generic(hw);
 347         case IXGBE_DEV_ID_X550EM_X_SFP:
 348                 /* set up for CS4227 usage */
 349                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 350                 ixgbe_setup_mux_ctl(hw);
 351                 ixgbe_check_cs4227(hw);
 352                 /* Fallthrough */
 353
 354         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 355                 return ixgbe_identify_module_generic(hw);
 356                 break;
 357         case IXGBE_DEV_ID_X550EM_X_KX4:
 358                 hw->phy.type = ixgbe_phy_x550em_kx4;
 359                 break;
 360         case IXGBE_DEV_ID_X550EM_X_KR:
 361         case IXGBE_DEV_ID_X550EM_A_KR:
 362         case IXGBE_DEV_ID_X550EM_A_KR_L:
 363                 hw->phy.type = ixgbe_phy_x550em_kr;
 364                 break;
 365         case IXGBE_DEV_ID_X550EM_X_1G_T:
 366         case IXGBE_DEV_ID_X550EM_X_10G_T:
 367         case IXGBE_DEV_ID_X550EM_A_1G_T:
 368         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 369         case IXGBE_DEV_ID_X550EM_A_10G_T:
 370                 return ixgbe_identify_phy_generic(hw);
 371         default:
 372                 break;
 373         }
 374         return IXGBE_SUCCESS;
 375 }
 376
 377 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 378                                      u32 device_type, u16 *phy_data)
 379 {
 380         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 381         return IXGBE_NOT_IMPLEMENTED;
 382 }
 383
 384 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 385                                       u32 device_type, u16 phy_data)
 386 {
 387         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 388         return IXGBE_NOT_IMPLEMENTED;
 389 }
 390
 391 /**
 392 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 393 *  @hw: pointer to hardware structure
 394 *
 395 *  Initialize the function pointers and for MAC type X550EM.
 396 *  Does not touch the hardware.
 397 **/
 398 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 399 {
 400         struct ixgbe_mac_info *mac = &hw->mac;
 401         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 402         struct ixgbe_phy_info *phy = &hw->phy;
 403         s32 ret_val;
 404
 405         DEBUGFUNC("ixgbe_init_ops_X550EM");
 406
 407         /* Similar to X550 so start there. */
 408         ret_val = ixgbe_init_ops_X550(hw);
 409
 410         /* Since this function eventually calls
 411          * ixgbe_init_ops_540 by design, we are setting
 412          * the pointers to NULL explicitly here to overwrite
 413          * the values being set in the x540 function.
 414          */
 415         /* Thermal sensor not supported in x550EM */
 416         mac->ops.get_thermal_sensor_data = NULL;
 417         mac->ops.init_thermal_sensor_thresh = NULL;
 418         mac->thermal_sensor_enabled = false;
 419
 420         /* FCOE not supported in x550EM */
 421         mac->ops.get_san_mac_addr = NULL;
 422         mac->ops.set_san_mac_addr = NULL;
 423         mac->ops.get_wwn_prefix = NULL;
 424         mac->ops.get_fcoe_boot_status = NULL;
 425
 426         /* IPsec not supported in x550EM */
 427         mac->ops.disable_sec_rx_path = NULL;
 428         mac->ops.enable_sec_rx_path = NULL;
 429
 430         /* AUTOC register is not present in x550EM. */
 431         mac->ops.prot_autoc_read = NULL;
 432         mac->ops.prot_autoc_write = NULL;
 433
 434         /* X550EM bus type is internal*/
 435         hw->bus.type = ixgbe_bus_type_internal;
 436         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 437
 438         if (hw->mac.type == ixgbe_mac_X550EM_x) {
 439                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 440                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 441                 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 442                 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 443         }
 444         if (hw->mac.type == ixgbe_mac_X550EM_a) {
 445                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
 446                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
 447                 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
 448                 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
 449         }
 450
 451         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 452         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 453         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 454         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 455         mac->ops.get_supported_physical_layer =
 456                                     ixgbe_get_supported_physical_layer_X550em;
 457
 458         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 459                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 460         else
 461                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 462
 463
 464         if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
 465                 mac->ops.setup_eee = NULL;
 466
 467         /* PHY */
 468         phy->ops.init = ixgbe_init_phy_ops_X550em;
 469         phy->ops.identify = ixgbe_identify_phy_x550em;
 470         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 471                 phy->ops.set_phy_power = NULL;
 472
 473
 474         /* EEPROM */
 475         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 476         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 477         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 478         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 479         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 480         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 481         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 482         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 483
 484         return ret_val;
 485 }
 486
 487 /**
 488  *  ixgbe_dmac_config_X550
 489  *  @hw: pointer to hardware structure
 490  *
 491  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 492  *  When disabling dmac, dmac enable dmac bit is cleared.
 493  **/
 494 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 495 {
 496         u32 reg, high_pri_tc;
 497
 498         DEBUGFUNC("ixgbe_dmac_config_X550");
 499
 500         /* Disable DMA coalescing before configuring */
 501         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 502         reg &= ~IXGBE_DMACR_DMAC_EN;
 503         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 504
 505         /* Disable DMA Coalescing if the watchdog timer is 0 */
 506         if (!hw->mac.dmac_config.watchdog_timer)
 507                 goto out;
 508
 509         ixgbe_dmac_config_tcs_X550(hw);
 510
 511         /* Configure DMA Coalescing Control Register */
 512         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 513
 514         /* Set the watchdog timer in units of 40.96 usec */
 515         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 516         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 517
 518         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 519         /* If fcoe is enabled, set high priority traffic class */
 520         if (hw->mac.dmac_config.fcoe_en) {
 521                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 522                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 523                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 524         }
 525         reg |= IXGBE_DMACR_EN_MNG_IND;
 526
 527         /* Enable DMA coalescing after configuration */
 528         reg |= IXGBE_DMACR_DMAC_EN;
 529         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 530
 531 out:
 532         return IXGBE_SUCCESS;
 533 }
 534
 535 /**
 536  *  ixgbe_dmac_config_tcs_X550
 537  *  @hw: pointer to hardware structure
 538  *
 539  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 540  *  be cleared before configuring.
 541  **/
 542 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 543 {
 544         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 545
 546         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 547
 548         /* Configure DMA coalescing enabled */
 549         switch (hw->mac.dmac_config.link_speed) {
 550         case IXGBE_LINK_SPEED_100_FULL:
 551                 pb_headroom = IXGBE_DMACRXT_100M;
 552                 break;
 553         case IXGBE_LINK_SPEED_1GB_FULL:
 554                 pb_headroom = IXGBE_DMACRXT_1G;
 555                 break;
 556         default:
 557                 pb_headroom = IXGBE_DMACRXT_10G;
 558                 break;
 559         }
 560
 561         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 562                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 563
 564         /* Set the per Rx packet buffer receive threshold */
 565         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 566                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 567                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 568
 569                 if (tc < hw->mac.dmac_config.num_tcs) {
 570                         /* Get Rx PB size */
 571                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 572                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 573                                 IXGBE_RXPBSIZE_SHIFT;
 574
 575                         /* Calculate receive buffer threshold in kilobytes */
 576                         if (rx_pb_size > pb_headroom)
 577                                 rx_pb_size = rx_pb_size - pb_headroom;
 578                         else
 579                                 rx_pb_size = 0;
 580
 581                         /* Minimum of MFS shall be set for DMCTH */
 582                         reg |= (rx_pb_size > maxframe_size_kb) ?
 583                                 rx_pb_size : maxframe_size_kb;
 584                 }
 585                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 586         }
 587         return IXGBE_SUCCESS;
 588 }
 589
 590 /**
 591  *  ixgbe_dmac_update_tcs_X550
 592  *  @hw: pointer to hardware structure
 593  *
 594  *  Disables dmac, updates per TC settings, and then enables dmac.
 595  **/
 596 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 597 {
 598         u32 reg;
 599
 600         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 601
 602         /* Disable DMA coalescing before configuring */
 603         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 604         reg &= ~IXGBE_DMACR_DMAC_EN;
 605         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 606
 607         ixgbe_dmac_config_tcs_X550(hw);
 608
 609         /* Enable DMA coalescing after configuration */
 610         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 611         reg |= IXGBE_DMACR_DMAC_EN;
 612         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 613
 614         return IXGBE_SUCCESS;
 615 }
 616
 617 /**
 618  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 619  *  @hw: pointer to hardware structure
 620  *
 621  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 622  *  ixgbe_hw struct in order to set up EEPROM access.
 623  **/
 624 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 625 {
 626         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 627         u32 eec;
 628         u16 eeprom_size;
 629
 630         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 631
 632         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 633                 eeprom->semaphore_delay = 10;
 634                 eeprom->type = ixgbe_flash;
 635
 636                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 637                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 638                                     IXGBE_EEC_SIZE_SHIFT);
 639                 eeprom->word_size = 1 << (eeprom_size +
 640                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 641
 642                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 643                           eeprom->type, eeprom->word_size);
 644         }
 645
 646         return IXGBE_SUCCESS;
 647 }
 648
 649 /**
 650  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 651  *  @hw: pointer to the HW structure
 652  *  @enable_eee: boolean flag to enable EEE
 653  *
 654  *  Enable/disable EEE based on enable_eee flag.
 655  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 656  *  are modified.
 657  *
 658  **/
 659 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 660 {
 661         u32 eeer;
 662         u16 autoneg_eee_reg;
 663         u32 link_reg;
 664         s32 status;
 665
 666         DEBUGFUNC("ixgbe_setup_eee_X550");
 667
 668         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 669         /* Enable or disable EEE per flag */
 670         if (enable_eee) {
 671                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 672
 673                 if (hw->mac.type == ixgbe_mac_X550) {
 674                         /* Advertise EEE capability */
 675                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 676                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 677
 678                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 679                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 680                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 681
 682                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 683                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 684                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 685                         /* Not supported on first revision of X550EM_x. */
 686                         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
 687                             !(IXGBE_FUSES0_REV_MASK &
 688                               IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
 689                                 return IXGBE_SUCCESS;
 690
 691                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 692                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 693                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 694                         if (status != IXGBE_SUCCESS)
 695                                 return status;
 696
 697                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 698                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 699
 700                         /* Don't advertise FEC capability when EEE enabled. */
 701                         link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 702
 703                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 704                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 705                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 706                         if (status != IXGBE_SUCCESS)
 707                                 return status;
 708                 }
 709         } else {
 710                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 711
 712                 if (hw->mac.type == ixgbe_mac_X550) {
 713                         /* Disable advertised EEE capability */
 714                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 715                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 716
 717                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 718                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 719                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 720
 721                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 722                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 723                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 724                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 725                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 726                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 727                         if (status != IXGBE_SUCCESS)
 728                                 return status;
 729
 730                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 731                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 732
 733                         /* Advertise FEC capability when EEE is disabled. */
 734                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 735
 736                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 737                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 738                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 739                         if (status != IXGBE_SUCCESS)
 740                                 return status;
 741                 }
 742         }
 743         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 744
 745         return IXGBE_SUCCESS;
 746 }
 747
 748 /**
 749  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 750  * @hw: pointer to hardware structure
 751  * @enable: enable or disable source address pruning
 752  * @pool: Rx pool to set source address pruning for
 753  **/
 754 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 755                                            unsigned int pool)
 756 {
 757         u64 pfflp;
 758
 759         /* max rx pool is 63 */
 760         if (pool > 63)
 761                 return;
 762
 763         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 764         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 765
 766         if (enable)
 767                 pfflp |= (1ULL << pool);
 768         else
 769                 pfflp &= ~(1ULL << pool);
 770
 771         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 772         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 773 }
 774
 775 /**
 776  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 777  *  @hw: pointer to hardware structure
 778  *  @enable: enable or disable switch for Ethertype anti-spoofing
 779  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 780  *
 781  **/
 782 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 783                 bool enable, int vf)
 784 {
 785         int vf_target_reg = vf >> 3;
 786         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 787         u32 pfvfspoof;
 788
 789         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 790
 791         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 792         if (enable)
 793                 pfvfspoof |= (1 << vf_target_shift);
 794         else
 795                 pfvfspoof &= ~(1 << vf_target_shift);
 796
 797         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 798 }
 799
 800 /**
 801  * ixgbe_iosf_wait - Wait for IOSF command completion
 802  * @hw: pointer to hardware structure
 803  * @ctrl: pointer to location to receive final IOSF control value
 804  *
 805  * Returns failing status on timeout
 806  *
 807  * Note: ctrl can be NULL if the IOSF control register value is not needed
 808  **/
 809 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
 810 {
 811         u32 i, command = 0;
 812
 813         /* Check every 10 usec to see if the address cycle completed.
 814          * The SB IOSF BUSY bit will clear when the operation is
 815          * complete
 816          */
 817         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 818                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 819                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 820                         break;
 821                 usec_delay(10);
 822         }
 823         if (ctrl)
 824                 *ctrl = command;
 825         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 826                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
 827                 return IXGBE_ERR_PHY;
 828         }
 829
 830         return IXGBE_SUCCESS;
 831 }
 832
 833 /**
 834  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 835  *  device
 836  *  @hw: pointer to hardware structure
 837  *  @reg_addr: 32 bit PHY register to write
 838  *  @device_type: 3 bit device type
 839  *  @data: Data to write to the register
 840  **/
 841 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 842                             u32 device_type, u32 data)
 843 {
 844         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 845         u32 command, error;
 846         s32 ret;
 847
 848         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
 849         if (ret != IXGBE_SUCCESS)
 850                 return ret;
 851
 852         ret = ixgbe_iosf_wait(hw, NULL);
 853         if (ret != IXGBE_SUCCESS)
 854                 goto out;
 855
 856         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 857                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 858
 859         /* Write IOSF control register */
 860         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 861
 862         /* Write IOSF data register */
 863         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 864
 865         ret = ixgbe_iosf_wait(hw, &command);
 866
 867         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 868                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 869                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 870                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 871                               "Failed to write, error %x\n", error);
 872                 ret = IXGBE_ERR_PHY;
 873         }
 874
 875 out:
 876         ixgbe_release_swfw_semaphore(hw, gssr);
 877         return ret;
 878 }
 879
 880 /**
 881  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 882  *  device
 883  *  @hw: pointer to hardware structure
 884  *  @reg_addr: 32 bit PHY register to write
 885  *  @device_type: 3 bit device type
 886  *  @phy_data: Pointer to read data from the register
 887  **/
 888 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 889                            u32 device_type, u32 *data)
 890 {
 891         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 892         u32 command, error;
 893         s32 ret;
 894
 895         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
 896         if (ret != IXGBE_SUCCESS)
 897                 return ret;
 898
 899         ret = ixgbe_iosf_wait(hw, NULL);
 900         if (ret != IXGBE_SUCCESS)
 901                 goto out;
 902
 903         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 904                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 905
 906         /* Write IOSF control register */
 907         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 908
 909         ret = ixgbe_iosf_wait(hw, &command);
 910
 911         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 912                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 913                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 914                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 915                                 "Failed to read, error %x\n", error);
 916                 ret = IXGBE_ERR_PHY;
 917         }
 918
 919         if (ret == IXGBE_SUCCESS)
 920                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 921
 922 out:
 923         ixgbe_release_swfw_semaphore(hw, gssr);
 924         return ret;
 925 }
 926
 927 /**
 928  * ixgbe_get_phy_token - Get the token for shared phy access
 929  * @hw: Pointer to hardware structure
 930  */
 931
 932 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
 933 {
 934         struct ixgbe_hic_phy_token_req token_cmd;
 935         s32 status;
 936
 937         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
 938         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
 939         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
 940         token_cmd.port_number = hw->bus.lan_id;
 941         token_cmd.command_type = FW_PHY_TOKEN_REQ;
 942         token_cmd.pad = 0;
 943         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
 944                                               sizeof(token_cmd),
 945                                               IXGBE_HI_COMMAND_TIMEOUT,
 946                                               true);
 947         if (status)
 948                 return status;
 949         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
 950                 return IXGBE_SUCCESS;
 951         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
 952                 return IXGBE_ERR_FW_RESP_INVALID;
 953
 954         return IXGBE_ERR_TOKEN_RETRY;
 955 }
 956
 957 /**
 958  * ixgbe_put_phy_token - Put the token for shared phy access
 959  * @hw: Pointer to hardware structure
 960  */
 961
 962 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
 963 {
 964         struct ixgbe_hic_phy_token_req token_cmd;
 965         s32 status;
 966
 967         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
 968         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
 969         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
 970         token_cmd.port_number = hw->bus.lan_id;
 971         token_cmd.command_type = FW_PHY_TOKEN_REL;
 972         token_cmd.pad = 0;
 973         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
 974                                               sizeof(token_cmd),
 975                                               IXGBE_HI_COMMAND_TIMEOUT,
 976                                               true);
 977         if (status)
 978                 return status;
 979         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
 980                 return IXGBE_SUCCESS;
 981         return IXGBE_ERR_FW_RESP_INVALID;
 982 }
 983
 984 /**
 985  *  ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
 986  *  of the IOSF device
 987  *  @hw: pointer to hardware structure
 988  *  @reg_addr: 32 bit PHY register to write
 989  *  @device_type: 3 bit device type
 990  *  @data: Data to write to the register
 991  **/
 992 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
 993         u32 device_type, u32 data)
 994 {
 995         struct ixgbe_hic_internal_phy_req write_cmd;
 996         s32 status;
 997         UNREFERENCED_1PARAMETER(device_type);
 998
 999         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1000         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1001         write_cmd.port_number = hw->bus.lan_id;
1002         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1003         write_cmd.address = (u16)reg_addr;
1004         write_cmd.rsv1 = 0;
1005         write_cmd.write_data = data;
1006         write_cmd.pad = 0;
1007
1008         status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1009                 sizeof(write_cmd), IXGBE_HI_COMMAND_TIMEOUT, false);
1010
1011         return status;
1012 }
1013
1014 /**
1015  *  ixgbe_read_iosf_sb_reg_x550a - Writes a value to specified register
1016  *  of the IOSF device.
1017  *  @hw: pointer to hardware structure
1018  *  @reg_addr: 32 bit PHY register to write
1019  *  @device_type: 3 bit device type
1020  *  @data: Pointer to read data from the register
1021  **/
1022 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1023         u32 device_type, u32 *data)
1024 {
1025         struct ixgbe_hic_internal_phy_req read_cmd;
1026         s32 status;
1027         UNREFERENCED_1PARAMETER(device_type);
1028
1029         read_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1030         read_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1031         read_cmd.port_number = hw->bus.lan_id;
1032         read_cmd.command_type = FW_INT_PHY_REQ_READ;
1033         read_cmd.address = (u16)reg_addr;
1034         read_cmd.rsv1 = 0;
1035         read_cmd.write_data = 0;
1036         read_cmd.pad = 0;
1037
1038         status = ixgbe_host_interface_command(hw, (u32 *)&read_cmd,
1039                 sizeof(read_cmd), IXGBE_HI_COMMAND_TIMEOUT, true);
1040
1041         /* Extract the register value from the response. */
1042         *data = ((struct ixgbe_hic_internal_phy_resp *)&read_cmd)->read_data;
1043
1044         return status;
1045 }
1046
1047 /**
1048  *  ixgbe_disable_mdd_X550
1049  *  @hw: pointer to hardware structure
1050  *
1051  *  Disable malicious driver detection
1052  **/
1053 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1054 {
1055         u32 reg;
1056
1057         DEBUGFUNC("ixgbe_disable_mdd_X550");
1058
1059         /* Disable MDD for TX DMA and interrupt */
1060         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1061         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1062         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1063
1064         /* Disable MDD for RX and interrupt */
1065         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1066         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1067         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1068 }
1069
1070 /**
1071  *  ixgbe_enable_mdd_X550
1072  *  @hw: pointer to hardware structure
1073  *
1074  *  Enable malicious driver detection
1075  **/
1076 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1077 {
1078         u32 reg;
1079
1080         DEBUGFUNC("ixgbe_enable_mdd_X550");
1081
1082         /* Enable MDD for TX DMA and interrupt */
1083         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1084         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1085         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1086
1087         /* Enable MDD for RX and interrupt */
1088         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1089         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1090         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1091 }
1092
1093 /**
1094  *  ixgbe_restore_mdd_vf_X550
1095  *  @hw: pointer to hardware structure
1096  *  @vf: vf index
1097  *
1098  *  Restore VF that was disabled during malicious driver detection event
1099  **/
1100 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1101 {
1102         u32 idx, reg, num_qs, start_q, bitmask;
1103
1104         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1105
1106         /* Map VF to queues */
1107         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1108         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1109         case IXGBE_MRQC_VMDQRT8TCEN:
1110                 num_qs = 8;  /* 16 VFs / pools */
1111                 bitmask = 0x000000FF;
1112                 break;
1113         case IXGBE_MRQC_VMDQRSS32EN:
1114         case IXGBE_MRQC_VMDQRT4TCEN:
1115                 num_qs = 4;  /* 32 VFs / pools */
1116                 bitmask = 0x0000000F;
1117                 break;
1118         default:            /* 64 VFs / pools */
1119                 num_qs = 2;
1120                 bitmask = 0x00000003;
1121                 break;
1122         }
1123         start_q = vf * num_qs;
1124
1125         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1126         idx = start_q / 32;
1127         reg = 0;
1128         reg |= (bitmask << (start_q % 32));
1129         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1130         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1131 }
1132
1133 /**
1134  *  ixgbe_mdd_event_X550
1135  *  @hw: pointer to hardware structure
1136  *  @vf_bitmap: vf bitmap of malicious vfs
1137  *
1138  *  Handle malicious driver detection event.
1139  **/
1140 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1141 {
1142         u32 wqbr;
1143         u32 i, j, reg, q, shift, vf, idx;
1144
1145         DEBUGFUNC("ixgbe_mdd_event_X550");
1146
1147         /* figure out pool size for mapping to vf's */
1148         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1149         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1150         case IXGBE_MRQC_VMDQRT8TCEN:
1151                 shift = 3;  /* 16 VFs / pools */
1152                 break;
1153         case IXGBE_MRQC_VMDQRSS32EN:
1154         case IXGBE_MRQC_VMDQRT4TCEN:
1155                 shift = 2;  /* 32 VFs / pools */
1156                 break;
1157         default:
1158                 shift = 1;  /* 64 VFs / pools */
1159                 break;
1160         }
1161
1162         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1163         for (i = 0; i < 4; i++) {
1164                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1165                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1166
1167                 if (!wqbr)
1168                         continue;
1169
1170                 /* Get malicious queue */
1171                 for (j = 0; j < 32 && wqbr; j++) {
1172
1173                         if (!(wqbr & (1 << j)))
1174                                 continue;
1175
1176                         /* Get queue from bitmask */
1177                         q = j + (i * 32);
1178
1179                         /* Map queue to vf */
1180                         vf = (q >> shift);
1181
1182                         /* Set vf bit in vf_bitmap */
1183                         idx = vf / 32;
1184                         vf_bitmap[idx] |= (1 << (vf % 32));
1185                         wqbr &= ~(1 << j);
1186                 }
1187         }
1188 }
1189
1190 /**
1191  *  ixgbe_get_media_type_X550em - Get media type
1192  *  @hw: pointer to hardware structure
1193  *
1194  *  Returns the media type (fiber, copper, backplane)
1195  */
1196 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1197 {
1198         enum ixgbe_media_type media_type;
1199
1200         DEBUGFUNC("ixgbe_get_media_type_X550em");
1201
1202         /* Detect if there is a copper PHY attached. */
1203         switch (hw->device_id) {
1204         case IXGBE_DEV_ID_X550EM_X_KR:
1205         case IXGBE_DEV_ID_X550EM_X_KX4:
1206         case IXGBE_DEV_ID_X550EM_A_KR:
1207         case IXGBE_DEV_ID_X550EM_A_KR_L:
1208                 media_type = ixgbe_media_type_backplane;
1209                 break;
1210         case IXGBE_DEV_ID_X550EM_X_SFP:
1211         case IXGBE_DEV_ID_X550EM_A_SFP:
1212         case IXGBE_DEV_ID_X550EM_A_SFP_N:
1213         case IXGBE_DEV_ID_X550EM_A_QSFP:
1214         case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1215                 media_type = ixgbe_media_type_fiber;
1216                 break;
1217         case IXGBE_DEV_ID_X550EM_X_1G_T:
1218         case IXGBE_DEV_ID_X550EM_X_10G_T:
1219         case IXGBE_DEV_ID_X550EM_A_1G_T:
1220         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1221         case IXGBE_DEV_ID_X550EM_A_10G_T:
1222                 media_type = ixgbe_media_type_copper;
1223                 break;
1224         default:
1225                 media_type = ixgbe_media_type_unknown;
1226                 break;
1227         }
1228         return media_type;
1229 }
1230
1231 /**
1232  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1233  *  @hw: pointer to hardware structure
1234  *  @linear: true if SFP module is linear
1235  */
1236 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1237 {
1238         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1239
1240         switch (hw->phy.sfp_type) {
1241         case ixgbe_sfp_type_not_present:
1242                 return IXGBE_ERR_SFP_NOT_PRESENT;
1243         case ixgbe_sfp_type_da_cu_core0:
1244         case ixgbe_sfp_type_da_cu_core1:
1245                 *linear = true;
1246                 break;
1247         case ixgbe_sfp_type_srlr_core0:
1248         case ixgbe_sfp_type_srlr_core1:
1249         case ixgbe_sfp_type_da_act_lmt_core0:
1250         case ixgbe_sfp_type_da_act_lmt_core1:
1251         case ixgbe_sfp_type_1g_sx_core0:
1252         case ixgbe_sfp_type_1g_sx_core1:
1253         case ixgbe_sfp_type_1g_lx_core0:
1254         case ixgbe_sfp_type_1g_lx_core1:
1255                 *linear = false;
1256                 break;
1257         case ixgbe_sfp_type_unknown:
1258         case ixgbe_sfp_type_1g_cu_core0:
1259         case ixgbe_sfp_type_1g_cu_core1:
1260         default:
1261                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1262         }
1263
1264         return IXGBE_SUCCESS;
1265 }
1266
1267 /**
1268  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1269  *  @hw: pointer to hardware structure
1270  *
1271  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1272  **/
1273 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1274 {
1275         s32 status;
1276         bool linear;
1277
1278         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1279
1280         status = ixgbe_identify_module_generic(hw);
1281
1282         if (status != IXGBE_SUCCESS)
1283                 return status;
1284
1285         /* Check if SFP module is supported */
1286         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1287
1288         return status;
1289 }
1290
1291 /**
1292  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1293  *  @hw: pointer to hardware structure
1294  */
1295 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1296 {
1297         s32 status;
1298         bool linear;
1299
1300         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1301
1302         /* Check if SFP module is supported */
1303         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1304
1305         if (status != IXGBE_SUCCESS)
1306                 return status;
1307
1308         ixgbe_init_mac_link_ops_X550em(hw);
1309         hw->phy.ops.reset = NULL;
1310
1311         return IXGBE_SUCCESS;
1312 }
1313
1314 /**
1315  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1316  *  @hw: pointer to hardware structure
1317  */
1318 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1319 {
1320         struct ixgbe_mac_info *mac = &hw->mac;
1321
1322         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1323
1324          switch (hw->mac.ops.get_media_type(hw)) {
1325          case ixgbe_media_type_fiber:
1326                 /* CS4227 does not support autoneg, so disable the laser control
1327                  * functions for SFP+ fiber
1328                  */
1329                 mac->ops.disable_tx_laser = NULL;
1330                 mac->ops.enable_tx_laser = NULL;
1331                 mac->ops.flap_tx_laser = NULL;
1332                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1333                 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1334                 mac->ops.set_rate_select_speed =
1335                                         ixgbe_set_soft_rate_select_speed;
1336                 break;
1337         case ixgbe_media_type_copper:
1338                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1339                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1340                 break;
1341         default:
1342                 break;
1343          }
1344 }
1345
1346 /**
1347  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1348  *  @hw: pointer to hardware structure
1349  *  @speed: pointer to link speed
1350  *  @autoneg: true when autoneg or autotry is enabled
1351  */
1352 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1353                                        ixgbe_link_speed *speed,
1354                                        bool *autoneg)
1355 {
1356         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1357
1358         /* SFP */
1359         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1360
1361                 /* CS4227 SFP must not enable auto-negotiation */
1362                 *autoneg = false;
1363
1364                 /* Check if 1G SFP module. */
1365                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1366                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1367                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1368                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1369                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1370                         return IXGBE_SUCCESS;
1371                 }
1372
1373                 /* Link capabilities are based on SFP */
1374                 if (hw->phy.multispeed_fiber)
1375                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1376                                  IXGBE_LINK_SPEED_1GB_FULL;
1377                 else
1378                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1379         } else {
1380                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1381                          IXGBE_LINK_SPEED_1GB_FULL;
1382                 *autoneg = true;
1383         }
1384
1385         return IXGBE_SUCCESS;
1386 }
1387
1388 /**
1389  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1390  * @hw: pointer to hardware structure
1391  * @lsc: pointer to boolean flag which indicates whether external Base T
1392  *       PHY interrupt is lsc
1393  *
1394  * Determime if external Base T PHY interrupt cause is high temperature
1395  * failure alarm or link status change.
1396  *
1397  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1398  * failure alarm, else return PHY access status.
1399  */
1400 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1401 {
1402         u32 status;
1403         u16 reg;
1404
1405         *lsc = false;
1406
1407         /* Vendor alarm triggered */
1408         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1409                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1410                                       &reg);
1411
1412         if (status != IXGBE_SUCCESS ||
1413             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1414                 return status;
1415
1416         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1417         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1418                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1419                                       &reg);
1420
1421         if (status != IXGBE_SUCCESS ||
1422             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1423             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1424                 return status;
1425
1426         /* Global alarm triggered */
1427         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1428                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1429                                       &reg);
1430
1431         if (status != IXGBE_SUCCESS)
1432                 return status;
1433
1434         /* If high temperature failure, then return over temp error and exit */
1435         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1436                 /* power down the PHY in case the PHY FW didn't already */
1437                 ixgbe_set_copper_phy_power(hw, false);
1438                 return IXGBE_ERR_OVERTEMP;
1439         } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1440                 /*  device fault alarm triggered */
1441                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1442                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1443                                           &reg);
1444
1445                 if (status != IXGBE_SUCCESS)
1446                         return status;
1447
1448                 /* if device fault was due to high temp alarm handle and exit */
1449                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1450                         /* power down the PHY in case the PHY FW didn't */
1451                         ixgbe_set_copper_phy_power(hw, false);
1452                         return IXGBE_ERR_OVERTEMP;
1453                 }
1454         }
1455
1456         /* Vendor alarm 2 triggered */
1457         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1458                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1459
1460         if (status != IXGBE_SUCCESS ||
1461             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1462                 return status;
1463
1464         /* link connect/disconnect event occurred */
1465         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1466                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1467
1468         if (status != IXGBE_SUCCESS)
1469                 return status;
1470
1471         /* Indicate LSC */
1472         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1473                 *lsc = true;
1474
1475         return IXGBE_SUCCESS;
1476 }
1477
1478 /**
1479  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1480  * @hw: pointer to hardware structure
1481  *
1482  * Enable link status change and temperature failure alarm for the external
1483  * Base T PHY
1484  *
1485  * Returns PHY access status
1486  */
1487 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1488 {
1489         u32 status;
1490         u16 reg;
1491         bool lsc;
1492
1493         /* Clear interrupt flags */
1494         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1495
1496         /* Enable link status change alarm */
1497         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1498                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1499
1500         if (status != IXGBE_SUCCESS)
1501                 return status;
1502
1503         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1504
1505         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1506                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1507
1508         if (status != IXGBE_SUCCESS)
1509                 return status;
1510
1511         /* Enable high temperature failure and global fault alarms */
1512         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1513                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1514                                       &reg);
1515
1516         if (status != IXGBE_SUCCESS)
1517                 return status;
1518
1519         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
1520                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
1521
1522         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1523                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1524                                        reg);
1525
1526         if (status != IXGBE_SUCCESS)
1527                 return status;
1528
1529         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1530         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1531                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1532                                       &reg);
1533
1534         if (status != IXGBE_SUCCESS)
1535                 return status;
1536
1537         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1538                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1539
1540         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1541                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1542                                        reg);
1543
1544         if (status != IXGBE_SUCCESS)
1545                 return status;
1546
1547         /* Enable chip-wide vendor alarm */
1548         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1549                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1550                                       &reg);
1551
1552         if (status != IXGBE_SUCCESS)
1553                 return status;
1554
1555         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1556
1557         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1558                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1559                                        reg);
1560
1561         return status;
1562 }
1563
1564 /**
1565  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1566  *  @hw: pointer to hardware structure
1567  *  @speed: link speed
1568  *
1569  *  Configures the integrated KR PHY.
1570  **/
1571 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1572                                        ixgbe_link_speed speed)
1573 {
1574         s32 status;
1575         u32 reg_val;
1576
1577         status = ixgbe_read_iosf_sb_reg_x550(hw,
1578                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1579                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1580         if (status)
1581                 return status;
1582
1583         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1584         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1585                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1586
1587         /* Advertise 10G support. */
1588         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1589                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1590
1591         /* Advertise 1G support. */
1592         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1593                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1594
1595         /* Restart auto-negotiation. */
1596         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1597         status = ixgbe_write_iosf_sb_reg_x550(hw,
1598                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1599                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1600
1601         return status;
1602 }
1603
1604 /**
1605  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1606  *  @hw: pointer to hardware structure
1607  *
1608  *  Initialize any function pointers that were not able to be
1609  *  set during init_shared_code because the PHY/SFP type was
1610  *  not known.  Perform the SFP init if necessary.
1611  */
1612 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1613 {
1614         struct ixgbe_phy_info *phy = &hw->phy;
1615         s32 ret_val;
1616
1617         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1618
1619         hw->mac.ops.set_lan_id(hw);
1620
1621         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1622                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1623                 ixgbe_setup_mux_ctl(hw);
1624
1625                 /* Save NW management interface connected on board. This is used
1626                  * to determine internal PHY mode.
1627                  */
1628                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1629                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
1630         }
1631
1632         /* Identify the PHY or SFP module */
1633         ret_val = phy->ops.identify(hw);
1634         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1635                 return ret_val;
1636
1637         /* Setup function pointers based on detected hardware */
1638         ixgbe_init_mac_link_ops_X550em(hw);
1639         if (phy->sfp_type != ixgbe_sfp_type_unknown)
1640                 phy->ops.reset = NULL;
1641
1642         /* Set functions pointers based on phy type */
1643         switch (hw->phy.type) {
1644         case ixgbe_phy_x550em_kx4:
1645                 phy->ops.setup_link = NULL;
1646                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1647                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1648                 break;
1649         case ixgbe_phy_x550em_kr:
1650                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1651                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1652                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1653                 break;
1654         case ixgbe_phy_x550em_ext_t:
1655                 /* Save NW management interface connected on board. This is used
1656                  * to determine internal PHY mode
1657                  */
1658                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1659
1660                 /* If internal link mode is XFI, then setup iXFI internal link,
1661                  * else setup KR now.
1662                  */
1663                 phy->ops.setup_internal_link =
1664                                               ixgbe_setup_internal_phy_t_x550em;
1665
1666                 /* setup SW LPLU only for first revision of X550EM_x */
1667                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
1668                     !(IXGBE_FUSES0_REV_MASK &
1669                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
1670                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1671
1672                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1673                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1674                 break;
1675         default:
1676                 break;
1677         }
1678         return ret_val;
1679 }
1680
1681 /**
1682  *  ixgbe_reset_hw_X550em - Perform hardware reset
1683  *  @hw: pointer to hardware structure
1684  *
1685  *  Resets the hardware by resetting the transmit and receive units, masks
1686  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1687  *  reset.
1688  */
1689 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1690 {
1691         ixgbe_link_speed link_speed;
1692         s32 status;
1693         u32 ctrl = 0;
1694         u32 i;
1695         u32 hlreg0;
1696         bool link_up = false;
1697
1698         DEBUGFUNC("ixgbe_reset_hw_X550em");
1699
1700         /* Call adapter stop to disable Tx/Rx and clear interrupts */
1701         status = hw->mac.ops.stop_adapter(hw);
1702         if (status != IXGBE_SUCCESS)
1703                 return status;
1704
1705         /* flush pending Tx transactions */
1706         ixgbe_clear_tx_pending(hw);
1707
1708         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
1709                 /* Config MDIO clock speed before the first MDIO PHY access */
1710                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1711                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
1712                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1713         }
1714
1715         /* PHY ops must be identified and initialized prior to reset */
1716         status = hw->phy.ops.init(hw);
1717
1718         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1719                 return status;
1720
1721         /* start the external PHY */
1722         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1723                 status = ixgbe_init_ext_t_x550em(hw);
1724                 if (status)
1725                         return status;
1726         }
1727
1728         /* Setup SFP module if there is one present. */
1729         if (hw->phy.sfp_setup_needed) {
1730                 status = hw->mac.ops.setup_sfp(hw);
1731                 hw->phy.sfp_setup_needed = false;
1732         }
1733
1734         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1735                 return status;
1736
1737         /* Reset PHY */
1738         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1739                 hw->phy.ops.reset(hw);
1740
1741 mac_reset_top:
1742         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1743          * If link reset is used when link is up, it might reset the PHY when
1744          * mng is using it.  If link is down or the flag to force full link
1745          * reset is set, then perform link reset.
1746          */
1747         ctrl = IXGBE_CTRL_LNK_RST;
1748         if (!hw->force_full_reset) {
1749                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1750                 if (link_up)
1751                         ctrl = IXGBE_CTRL_RST;
1752         }
1753
1754         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1755         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1756         IXGBE_WRITE_FLUSH(hw);
1757
1758         /* Poll for reset bit to self-clear meaning reset is complete */
1759         for (i = 0; i < 10; i++) {
1760                 usec_delay(1);
1761                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1762                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1763                         break;
1764         }
1765
1766         if (ctrl & IXGBE_CTRL_RST_MASK) {
1767                 status = IXGBE_ERR_RESET_FAILED;
1768                 DEBUGOUT("Reset polling failed to complete.\n");
1769         }
1770
1771         msec_delay(50);
1772
1773         /* Double resets are required for recovery from certain error
1774          * conditions.  Between resets, it is necessary to stall to
1775          * allow time for any pending HW events to complete.
1776          */
1777         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1778                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1779                 goto mac_reset_top;
1780         }
1781
1782         /* Store the permanent mac address */
1783         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1784
1785         /* Store MAC address from RAR0, clear receive address registers, and
1786          * clear the multicast table.  Also reset num_rar_entries to 128,
1787          * since we modify this value when programming the SAN MAC address.
1788          */
1789         hw->mac.num_rar_entries = 128;
1790         hw->mac.ops.init_rx_addrs(hw);
1791
1792         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1793                 ixgbe_setup_mux_ctl(hw);
1794
1795         return status;
1796 }
1797
1798 /**
1799  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1800  * @hw: pointer to hardware structure
1801  */
1802 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1803 {
1804         u32 status;
1805         u16 reg;
1806
1807         status = hw->phy.ops.read_reg(hw,
1808                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1809                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1810                                       &reg);
1811
1812         if (status != IXGBE_SUCCESS)
1813                 return status;
1814
1815         /* If PHY FW reset completed bit is set then this is the first
1816          * SW instance after a power on so the PHY FW must be un-stalled.
1817          */
1818         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1819                 status = hw->phy.ops.read_reg(hw,
1820                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1821                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1822                                         &reg);
1823
1824                 if (status != IXGBE_SUCCESS)
1825                         return status;
1826
1827                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1828
1829                 status = hw->phy.ops.write_reg(hw,
1830                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1831                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1832                                         reg);
1833
1834                 if (status != IXGBE_SUCCESS)
1835                         return status;
1836         }
1837
1838         return status;
1839 }
1840
1841 /**
1842  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1843  *  @hw: pointer to hardware structure
1844  *
1845  *  Configures the integrated KR PHY.
1846  **/
1847 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1848 {
1849         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
1850 }
1851
1852 /**
1853  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
1854  *  @hw: pointer to hardware structure
1855  *
1856  *  Configure the external PHY and the integrated KR PHY for SFP support.
1857  **/
1858 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1859                                     ixgbe_link_speed speed,
1860                                     bool autoneg_wait_to_complete)
1861 {
1862         s32 ret_val;
1863         u16 reg_slice, reg_val;
1864         bool setup_linear = false;
1865         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1866
1867         /* Check if SFP module is supported and linear */
1868         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1869
1870         /* If no SFP module present, then return success. Return success since
1871          * there is no reason to configure CS4227 and SFP not present error is
1872          * not excepted in the setup MAC link flow.
1873          */
1874         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1875                 return IXGBE_SUCCESS;
1876
1877         if (ret_val != IXGBE_SUCCESS)
1878                 return ret_val;
1879
1880         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1881                 /* Configure CS4227 LINE side to 10G SR. */
1882                 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
1883                             (hw->bus.lan_id << 12);
1884                 reg_val = IXGBE_CS4227_SPEED_10G;
1885                 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1886                                                    reg_val);
1887
1888                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
1889                             (hw->bus.lan_id << 12);
1890                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1891                 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1892                                                    reg_val);
1893
1894                 /* Configure CS4227 for HOST connection rate then type. */
1895                 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
1896                             (hw->bus.lan_id << 12);
1897                 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
1898                 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
1899                 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1900                                                    reg_val);
1901
1902                 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
1903                             (hw->bus.lan_id << 12);
1904                 if (setup_linear)
1905                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1906                 else
1907                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1908                 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1909                                                    reg_val);
1910
1911                 /* Setup XFI internal link. */
1912                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
1913         } else {
1914                 /* Configure internal PHY for KR/KX. */
1915                 ixgbe_setup_kr_speed_x550em(hw, speed);
1916
1917                 /* Configure CS4227 LINE side to proper mode. */
1918                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
1919                             (hw->bus.lan_id << 12);
1920                 if (setup_linear)
1921                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1922                 else
1923                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1924                 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1925                                                    reg_val);
1926         }
1927         return ret_val;
1928 }
1929
1930 /**
1931  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
1932  *  @hw: pointer to hardware structure
1933  *
1934  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
1935  **/
1936 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
1937 {
1938         s32 status;
1939         u32 reg_val;
1940
1941         /* Disable training protocol FSM. */
1942         status = ixgbe_read_iosf_sb_reg_x550(hw,
1943                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1944                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1945         if (status != IXGBE_SUCCESS)
1946                 return status;
1947         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1948         status = ixgbe_write_iosf_sb_reg_x550(hw,
1949                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1950                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1951         if (status != IXGBE_SUCCESS)
1952                 return status;
1953
1954         /* Disable Flex from training TXFFE. */
1955         status = ixgbe_read_iosf_sb_reg_x550(hw,
1956                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1957                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1958         if (status != IXGBE_SUCCESS)
1959                 return status;
1960         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1961         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1962         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1963         status = ixgbe_write_iosf_sb_reg_x550(hw,
1964                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1965                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1966         if (status != IXGBE_SUCCESS)
1967                 return status;
1968         status = ixgbe_read_iosf_sb_reg_x550(hw,
1969                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1970                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1971         if (status != IXGBE_SUCCESS)
1972                 return status;
1973         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1974         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1975         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1976         status = ixgbe_write_iosf_sb_reg_x550(hw,
1977                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1978                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1979         if (status != IXGBE_SUCCESS)
1980                 return status;
1981
1982         /* Enable override for coefficients. */
1983         status = ixgbe_read_iosf_sb_reg_x550(hw,
1984                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1985                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1986         if (status != IXGBE_SUCCESS)
1987                 return status;
1988         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1989         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1990         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1991         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1992         status = ixgbe_write_iosf_sb_reg_x550(hw,
1993                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1994                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1995         return status;
1996 }
1997
1998 /**
1999  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2000  *  @hw: pointer to hardware structure
2001  *  @speed: the link speed to force
2002  *
2003  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
2004  *  internal and external PHY at a specific speed, without autonegotiation.
2005  **/
2006 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2007 {
2008         s32 status;
2009         u32 reg_val;
2010
2011         /* Disable AN and force speed to 10G Serial. */
2012         status = ixgbe_read_iosf_sb_reg_x550(hw,
2013                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2014                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2015         if (status != IXGBE_SUCCESS)
2016                 return status;
2017
2018         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2019         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2020
2021         /* Select forced link speed for internal PHY. */
2022         switch (*speed) {
2023         case IXGBE_LINK_SPEED_10GB_FULL:
2024                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2025                 break;
2026         case IXGBE_LINK_SPEED_1GB_FULL:
2027                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2028                 break;
2029         default:
2030                 /* Other link speeds are not supported by internal KR PHY. */
2031                 return IXGBE_ERR_LINK_SETUP;
2032         }
2033
2034         status = ixgbe_write_iosf_sb_reg_x550(hw,
2035                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2036                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2037         if (status != IXGBE_SUCCESS)
2038                 return status;
2039
2040         /* Additional configuration needed for x550em_x */
2041         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2042                 status = ixgbe_setup_ixfi_x550em_x(hw);
2043                 if (status != IXGBE_SUCCESS)
2044                         return status;
2045         }
2046
2047         /* Toggle port SW reset by AN reset. */
2048         status = ixgbe_read_iosf_sb_reg_x550(hw,
2049                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2050                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2051         if (status != IXGBE_SUCCESS)
2052                 return status;
2053         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2054         status = ixgbe_write_iosf_sb_reg_x550(hw,
2055                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2056                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2057
2058         return status;
2059 }
2060
2061 /**
2062  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2063  * @hw: address of hardware structure
2064  * @link_up: address of boolean to indicate link status
2065  *
2066  * Returns error code if unable to get link status.
2067  */
2068 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2069 {
2070         u32 ret;
2071         u16 autoneg_status;
2072
2073         *link_up = false;
2074
2075         /* read this twice back to back to indicate current status */
2076         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2077                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2078                                    &autoneg_status);
2079         if (ret != IXGBE_SUCCESS)
2080                 return ret;
2081
2082         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2083                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2084                                    &autoneg_status);
2085         if (ret != IXGBE_SUCCESS)
2086                 return ret;
2087
2088         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2089
2090         return IXGBE_SUCCESS;
2091 }
2092
2093 /**
2094  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2095  * @hw: point to hardware structure
2096  *
2097  * Configures the link between the integrated KR PHY and the external X557 PHY
2098  * The driver will call this function when it gets a link status change
2099  * interrupt from the X557 PHY. This function configures the link speed
2100  * between the PHYs to match the link speed of the BASE-T link.
2101  *
2102  * A return of a non-zero value indicates an error, and the base driver should
2103  * not report link up.
2104  */
2105 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2106 {
2107         ixgbe_link_speed force_speed;
2108         bool link_up;
2109         u32 status;
2110         u16 speed;
2111
2112         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2113                 return IXGBE_ERR_CONFIG;
2114
2115         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2116                 /* If link is down, there is no setup necessary so return  */
2117                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2118                 if (status != IXGBE_SUCCESS)
2119                         return status;
2120
2121                 if (!link_up)
2122                         return IXGBE_SUCCESS;
2123
2124                 status = hw->phy.ops.read_reg(hw,
2125                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2126                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2127                                               &speed);
2128                 if (status != IXGBE_SUCCESS)
2129                         return status;
2130
2131                 /* If link is still down - no setup is required so return */
2132                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2133                 if (status != IXGBE_SUCCESS)
2134                         return status;
2135                 if (!link_up)
2136                         return IXGBE_SUCCESS;
2137
2138                 /* clear everything but the speed and duplex bits */
2139                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2140
2141                 switch (speed) {
2142                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2143                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2144                         break;
2145                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2146                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2147                         break;
2148                 default:
2149                         /* Internal PHY does not support anything else */
2150                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
2151                 }
2152
2153                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2154         } else {
2155                 speed = IXGBE_LINK_SPEED_10GB_FULL |
2156                         IXGBE_LINK_SPEED_1GB_FULL;
2157                 return ixgbe_setup_kr_speed_x550em(hw, speed);
2158         }
2159 }
2160
2161 /**
2162  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
2163  *  @hw: pointer to hardware structure
2164  *
2165  *  Configures the integrated KR PHY to use internal loopback mode.
2166  **/
2167 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
2168 {
2169         s32 status;
2170         u32 reg_val;
2171
2172         /* Disable AN and force speed to 10G Serial. */
2173         status = ixgbe_read_iosf_sb_reg_x550(hw,
2174                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2175                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2176         if (status != IXGBE_SUCCESS)
2177                 return status;
2178         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2179         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2180         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2181         status = ixgbe_write_iosf_sb_reg_x550(hw,
2182                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2183                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2184         if (status != IXGBE_SUCCESS)
2185                 return status;
2186
2187         /* Set near-end loopback clocks. */
2188         status = ixgbe_read_iosf_sb_reg_x550(hw,
2189                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2190                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2191         if (status != IXGBE_SUCCESS)
2192                 return status;
2193         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2194         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2195         status = ixgbe_write_iosf_sb_reg_x550(hw,
2196                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2197                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2198         if (status != IXGBE_SUCCESS)
2199                 return status;
2200
2201         /* Set loopback enable. */
2202         status = ixgbe_read_iosf_sb_reg_x550(hw,
2203                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2204                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2205         if (status != IXGBE_SUCCESS)
2206                 return status;
2207         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2208         status = ixgbe_write_iosf_sb_reg_x550(hw,
2209                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2210                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2211         if (status != IXGBE_SUCCESS)
2212                 return status;
2213
2214         /* Training bypass. */
2215         status = ixgbe_read_iosf_sb_reg_x550(hw,
2216                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2217                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2218         if (status != IXGBE_SUCCESS)
2219                 return status;
2220         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2221         status = ixgbe_write_iosf_sb_reg_x550(hw,
2222                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2223                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2224
2225         return status;
2226 }
2227
2228 /**
2229  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2230  *  assuming that the semaphore is already obtained.
2231  *  @hw: pointer to hardware structure
2232  *  @offset: offset of  word in the EEPROM to read
2233  *  @data: word read from the EEPROM
2234  *
2235  *  Reads a 16 bit word from the EEPROM using the hostif.
2236  **/
2237 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2238                                    u16 *data)
2239 {
2240         s32 status;
2241         struct ixgbe_hic_read_shadow_ram buffer;
2242
2243         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2244         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2245         buffer.hdr.req.buf_lenh = 0;
2246         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2247         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2248
2249         /* convert offset from words to bytes */
2250         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2251         /* one word */
2252         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2253
2254         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2255                                               sizeof(buffer),
2256                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2257
2258         if (status)
2259                 return status;
2260
2261         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2262                                           FW_NVM_DATA_OFFSET);
2263
2264         return 0;
2265 }
2266
2267 /**
2268  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2269  *  @hw: pointer to hardware structure
2270  *  @offset: offset of  word in the EEPROM to read
2271  *  @data: word read from the EEPROM
2272  *
2273  *  Reads a 16 bit word from the EEPROM using the hostif.
2274  **/
2275 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2276                               u16 *data)
2277 {
2278         s32 status = IXGBE_SUCCESS;
2279
2280         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2281
2282         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2283             IXGBE_SUCCESS) {
2284                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2285                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2286         } else {
2287                 status = IXGBE_ERR_SWFW_SYNC;
2288         }
2289
2290         return status;
2291 }
2292
2293 /**
2294  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2295  *  @hw: pointer to hardware structure
2296  *  @offset: offset of  word in the EEPROM to read
2297  *  @words: number of words
2298  *  @data: word(s) read from the EEPROM
2299  *
2300  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
2301  **/
2302 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2303                                      u16 offset, u16 words, u16 *data)
2304 {
2305         struct ixgbe_hic_read_shadow_ram buffer;
2306         u32 current_word = 0;
2307         u16 words_to_read;
2308         s32 status;
2309         u32 i;
2310
2311         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2312
2313         /* Take semaphore for the entire operation. */
2314         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2315         if (status) {
2316                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2317                 return status;
2318         }
2319         while (words) {
2320                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2321                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2322                 else
2323                         words_to_read = words;
2324
2325                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2326                 buffer.hdr.req.buf_lenh = 0;
2327                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2328                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2329
2330                 /* convert offset from words to bytes */
2331                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2332                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2333
2334                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2335                                                       sizeof(buffer),
2336                                                       IXGBE_HI_COMMAND_TIMEOUT,
2337                                                       false);
2338
2339                 if (status) {
2340                         DEBUGOUT("Host interface command failed\n");
2341                         goto out;
2342                 }
2343
2344                 for (i = 0; i < words_to_read; i++) {
2345                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
2346                                   2 * i;
2347                         u32 value = IXGBE_READ_REG(hw, reg);
2348
2349                         data[current_word] = (u16)(value & 0xffff);
2350                         current_word++;
2351                         i++;
2352                         if (i < words_to_read) {
2353                                 value >>= 16;
2354                                 data[current_word] = (u16)(value & 0xffff);
2355                                 current_word++;
2356                         }
2357                 }
2358                 words -= words_to_read;
2359         }
2360
2361 out:
2362         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2363         return status;
2364 }
2365
2366 /**
2367  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2368  *  @hw: pointer to hardware structure
2369  *  @offset: offset of  word in the EEPROM to write
2370  *  @data: word write to the EEPROM
2371  *
2372  *  Write a 16 bit word to the EEPROM using the hostif.
2373  **/
2374 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2375                                     u16 data)
2376 {
2377         s32 status;
2378         struct ixgbe_hic_write_shadow_ram buffer;
2379
2380         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
2381
2382         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
2383         buffer.hdr.req.buf_lenh = 0;
2384         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
2385         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2386
2387          /* one word */
2388         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2389         buffer.data = data;
2390         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2391
2392         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2393                                               sizeof(buffer),
2394                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2395
2396         return status;
2397 }
2398
2399 /**
2400  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2401  *  @hw: pointer to hardware structure
2402  *  @offset: offset of  word in the EEPROM to write
2403  *  @data: word write to the EEPROM
2404  *
2405  *  Write a 16 bit word to the EEPROM using the hostif.
2406  **/
2407 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2408                                u16 data)
2409 {
2410         s32 status = IXGBE_SUCCESS;
2411
2412         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2413
2414         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2415             IXGBE_SUCCESS) {
2416                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2417                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2418         } else {
2419                 DEBUGOUT("write ee hostif failed to get semaphore");
2420                 status = IXGBE_ERR_SWFW_SYNC;
2421         }
2422
2423         return status;
2424 }
2425
2426 /**
2427  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2428  *  @hw: pointer to hardware structure
2429  *  @offset: offset of  word in the EEPROM to write
2430  *  @words: number of words
2431  *  @data: word(s) write to the EEPROM
2432  *
2433  *  Write a 16 bit word(s) to the EEPROM using the hostif.
2434  **/
2435 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2436                                       u16 offset, u16 words, u16 *data)
2437 {
2438         s32 status = IXGBE_SUCCESS;
2439         u32 i = 0;
2440
2441         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2442
2443         /* Take semaphore for the entire operation. */
2444         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2445         if (status != IXGBE_SUCCESS) {
2446                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2447                 goto out;
2448         }
2449
2450         for (i = 0; i < words; i++) {
2451                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2452                                                          data[i]);
2453
2454                 if (status != IXGBE_SUCCESS) {
2455                         DEBUGOUT("Eeprom buffered write failed\n");
2456                         break;
2457                 }
2458         }
2459
2460         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2461 out:
2462
2463         return status;
2464 }
2465
2466 /**
2467  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2468  * @hw: pointer to hardware structure
2469  * @ptr: pointer offset in eeprom
2470  * @size: size of section pointed by ptr, if 0 first word will be used as size
2471  * @csum: address of checksum to update
2472  *
2473  * Returns error status for any failure
2474  */
2475 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2476                                    u16 size, u16 *csum, u16 *buffer,
2477                                    u32 buffer_size)
2478 {
2479         u16 buf[256];
2480         s32 status;
2481         u16 length, bufsz, i, start;
2482         u16 *local_buffer;
2483
2484         bufsz = sizeof(buf) / sizeof(buf[0]);
2485
2486         /* Read a chunk at the pointer location */
2487         if (!buffer) {
2488                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2489                 if (status) {
2490                         DEBUGOUT("Failed to read EEPROM image\n");
2491                         return status;
2492                 }
2493                 local_buffer = buf;
2494         } else {
2495                 if (buffer_size < ptr)
2496                         return  IXGBE_ERR_PARAM;
2497                 local_buffer = &buffer[ptr];
2498         }
2499
2500         if (size) {
2501                 start = 0;
2502                 length = size;
2503         } else {
2504                 start = 1;
2505                 length = local_buffer[0];
2506
2507                 /* Skip pointer section if length is invalid. */
2508                 if (length == 0xFFFF || length == 0 ||
2509                     (ptr + length) >= hw->eeprom.word_size)
2510                         return IXGBE_SUCCESS;
2511         }
2512
2513         if (buffer && ((u32)start + (u32)length > buffer_size))
2514                 return IXGBE_ERR_PARAM;
2515
2516         for (i = start; length; i++, length--) {
2517                 if (i == bufsz && !buffer) {
2518                         ptr += bufsz;
2519                         i = 0;
2520                         if (length < bufsz)
2521                                 bufsz = length;
2522
2523                         /* Read a chunk at the pointer location */
2524                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2525                                                                   bufsz, buf);
2526                         if (status) {
2527                                 DEBUGOUT("Failed to read EEPROM image\n");
2528                                 return status;
2529                         }
2530                 }
2531                 *csum += local_buffer[i];
2532         }
2533         return IXGBE_SUCCESS;
2534 }
2535
2536 /**
2537  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2538  *  @hw: pointer to hardware structure
2539  *  @buffer: pointer to buffer containing calculated checksum
2540  *  @buffer_size: size of buffer
2541  *
2542  *  Returns a negative error code on error, or the 16-bit checksum
2543  **/
2544 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2545 {
2546         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2547         u16 *local_buffer;
2548         s32 status;
2549         u16 checksum = 0;
2550         u16 pointer, i, size;
2551
2552         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2553
2554         hw->eeprom.ops.init_params(hw);
2555
2556         if (!buffer) {
2557                 /* Read pointer area */
2558                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2559                                                      IXGBE_EEPROM_LAST_WORD + 1,
2560                                                      eeprom_ptrs);
2561                 if (status) {
2562                         DEBUGOUT("Failed to read EEPROM image\n");
2563                         return status;
2564                 }
2565                 local_buffer = eeprom_ptrs;
2566         } else {
2567                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2568                         return IXGBE_ERR_PARAM;
2569                 local_buffer = buffer;
2570         }
2571
2572         /*
2573          * For X550 hardware include 0x0-0x41 in the checksum, skip the
2574          * checksum word itself
2575          */
2576         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2577                 if (i != IXGBE_EEPROM_CHECKSUM)
2578                         checksum += local_buffer[i];
2579
2580         /*
2581          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
2582          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2583          */
2584         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2585                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2586                         continue;
2587
2588                 pointer = local_buffer[i];
2589
2590                 /* Skip pointer section if the pointer is invalid. */
2591                 if (pointer == 0xFFFF || pointer == 0 ||
2592                     pointer >= hw->eeprom.word_size)
2593                         continue;
2594
2595                 switch (i) {
2596                 case IXGBE_PCIE_GENERAL_PTR:
2597                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2598                         break;
2599                 case IXGBE_PCIE_CONFIG0_PTR:
2600                 case IXGBE_PCIE_CONFIG1_PTR:
2601                         size = IXGBE_PCIE_CONFIG_SIZE;
2602                         break;
2603                 default:
2604                         size = 0;
2605                         break;
2606                 }
2607
2608                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2609                                                 buffer, buffer_size);
2610                 if (status)
2611                         return status;
2612         }
2613
2614         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2615
2616         return (s32)checksum;
2617 }
2618
2619 /**
2620  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2621  *  @hw: pointer to hardware structure
2622  *
2623  *  Returns a negative error code on error, or the 16-bit checksum
2624  **/
2625 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2626 {
2627         return ixgbe_calc_checksum_X550(hw, NULL, 0);
2628 }
2629
2630 /**
2631  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2632  *  @hw: pointer to hardware structure
2633  *  @checksum_val: calculated checksum
2634  *
2635  *  Performs checksum calculation and validates the EEPROM checksum.  If the
2636  *  caller does not need checksum_val, the value can be NULL.
2637  **/
2638 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2639 {
2640         s32 status;
2641         u16 checksum;
2642         u16 read_checksum = 0;
2643
2644         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2645
2646         /* Read the first word from the EEPROM. If this times out or fails, do
2647          * not continue or we could be in for a very long wait while every
2648          * EEPROM read fails
2649          */
2650         status = hw->eeprom.ops.read(hw, 0, &checksum);
2651         if (status) {
2652                 DEBUGOUT("EEPROM read failed\n");
2653                 return status;
2654         }
2655
2656         status = hw->eeprom.ops.calc_checksum(hw);
2657         if (status < 0)
2658                 return status;
2659
2660         checksum = (u16)(status & 0xffff);
2661
2662         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2663                                            &read_checksum);
2664         if (status)
2665                 return status;
2666
2667         /* Verify read checksum from EEPROM is the same as
2668          * calculated checksum
2669          */
2670         if (read_checksum != checksum) {
2671                 status = IXGBE_ERR_EEPROM_CHECKSUM;
2672                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2673                              "Invalid EEPROM checksum");
2674         }
2675
2676         /* If the user cares, return the calculated checksum */
2677         if (checksum_val)
2678                 *checksum_val = checksum;
2679
2680         return status;
2681 }
2682
2683 /**
2684  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2685  * @hw: pointer to hardware structure
2686  *
2687  * After writing EEPROM to shadow RAM using EEWR register, software calculates
2688  * checksum and updates the EEPROM and instructs the hardware to update
2689  * the flash.
2690  **/
2691 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2692 {
2693         s32 status;
2694         u16 checksum = 0;
2695
2696         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2697
2698         /* Read the first word from the EEPROM. If this times out or fails, do
2699          * not continue or we could be in for a very long wait while every
2700          * EEPROM read fails
2701          */
2702         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2703         if (status) {
2704                 DEBUGOUT("EEPROM read failed\n");
2705                 return status;
2706         }
2707
2708         status = ixgbe_calc_eeprom_checksum_X550(hw);
2709         if (status < 0)
2710                 return status;
2711
2712         checksum = (u16)(status & 0xffff);
2713
2714         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2715                                             checksum);
2716         if (status)
2717                 return status;
2718
2719         status = ixgbe_update_flash_X550(hw);
2720
2721         return status;
2722 }
2723
2724 /**
2725  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2726  *  @hw: pointer to hardware structure
2727  *
2728  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2729  **/
2730 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2731 {
2732         s32 status = IXGBE_SUCCESS;
2733         union ixgbe_hic_hdr2 buffer;
2734
2735         DEBUGFUNC("ixgbe_update_flash_X550");
2736
2737         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2738         buffer.req.buf_lenh = 0;
2739         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2740         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2741
2742         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2743                                               sizeof(buffer),
2744                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2745
2746         return status;
2747 }
2748
2749 /**
2750  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2751  *  @hw: pointer to hardware structure
2752  *
2753  *  Determines physical layer capabilities of the current configuration.
2754  **/
2755 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2756 {
2757         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2758         u16 ext_ability = 0;
2759
2760         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2761
2762         hw->phy.ops.identify(hw);
2763
2764         switch (hw->phy.type) {
2765         case ixgbe_phy_x550em_kr:
2766                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2767                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2768                 break;
2769         case ixgbe_phy_x550em_kx4:
2770                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2771                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2772                 break;
2773         case ixgbe_phy_x550em_ext_t:
2774                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2775                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2776                                      &ext_ability);
2777                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2778                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2779                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2780                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2781                 break;
2782         default:
2783                 break;
2784         }
2785
2786         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2787                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2788
2789         return physical_layer;
2790 }
2791
2792 /**
2793  * ixgbe_get_bus_info_x550em - Set PCI bus info
2794  * @hw: pointer to hardware structure
2795  *
2796  * Sets bus link width and speed to unknown because X550em is
2797  * not a PCI device.
2798  **/
2799 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2800 {
2801
2802         DEBUGFUNC("ixgbe_get_bus_info_x550em");
2803
2804         hw->bus.width = ixgbe_bus_width_unknown;
2805         hw->bus.speed = ixgbe_bus_speed_unknown;
2806
2807         hw->mac.ops.set_lan_id(hw);
2808
2809         return IXGBE_SUCCESS;
2810 }
2811
2812 /**
2813  * ixgbe_disable_rx_x550 - Disable RX unit
2814  *
2815  * Enables the Rx DMA unit for x550
2816  **/
2817 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2818 {
2819         u32 rxctrl, pfdtxgswc;
2820         s32 status;
2821         struct ixgbe_hic_disable_rxen fw_cmd;
2822
2823         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2824
2825         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2826         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2827                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2828                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2829                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2830                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2831                         hw->mac.set_lben = true;
2832                 } else {
2833                         hw->mac.set_lben = false;
2834                 }
2835
2836                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2837                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2838                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2839                 fw_cmd.port_number = (u8)hw->bus.lan_id;
2840
2841                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2842                                         sizeof(struct ixgbe_hic_disable_rxen),
2843                                         IXGBE_HI_COMMAND_TIMEOUT, true);
2844
2845                 /* If we fail - disable RX using register write */
2846                 if (status) {
2847                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2848                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2849                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2850                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2851                         }
2852                 }
2853         }
2854 }
2855
2856 /**
2857  * ixgbe_enter_lplu_x550em - Transition to low power states
2858  *  @hw: pointer to hardware structure
2859  *
2860  * Configures Low Power Link Up on transition to low power states
2861  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2862  * X557 PHY immediately prior to entering LPLU.
2863  **/
2864 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2865 {
2866         u16 an_10g_cntl_reg, autoneg_reg, speed;
2867         s32 status;
2868         ixgbe_link_speed lcd_speed;
2869         u32 save_autoneg;
2870         bool link_up;
2871
2872         /* SW LPLU not required on later HW revisions. */
2873         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2874             (IXGBE_FUSES0_REV_MASK &
2875              IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2876                 return IXGBE_SUCCESS;
2877
2878         /* If blocked by MNG FW, then don't restart AN */
2879         if (ixgbe_check_reset_blocked(hw))
2880                 return IXGBE_SUCCESS;
2881
2882         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2883         if (status != IXGBE_SUCCESS)
2884                 return status;
2885
2886         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2887
2888         if (status != IXGBE_SUCCESS)
2889                 return status;
2890
2891         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2892          * disabled, then force link down by entering low power mode.
2893          */
2894         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2895             !(hw->wol_enabled || ixgbe_mng_present(hw)))
2896                 return ixgbe_set_copper_phy_power(hw, FALSE);
2897
2898         /* Determine LCD */
2899         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2900
2901         if (status != IXGBE_SUCCESS)
2902                 return status;
2903
2904         /* If no valid LCD link speed, then force link down and exit. */
2905         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2906                 return ixgbe_set_copper_phy_power(hw, FALSE);
2907
2908         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2909                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2910                                       &speed);
2911
2912         if (status != IXGBE_SUCCESS)
2913                 return status;
2914
2915         /* If no link now, speed is invalid so take link down */
2916         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2917         if (status != IXGBE_SUCCESS)
2918                 return ixgbe_set_copper_phy_power(hw, false);
2919
2920         /* clear everything but the speed bits */
2921         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2922
2923         /* If current speed is already LCD, then exit. */
2924         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2925              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2926             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2927              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2928                 return status;
2929
2930         /* Clear AN completed indication */
2931         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2932                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2933                                       &autoneg_reg);
2934
2935         if (status != IXGBE_SUCCESS)
2936                 return status;
2937
2938         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2939                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2940                              &an_10g_cntl_reg);
2941
2942         if (status != IXGBE_SUCCESS)
2943                 return status;
2944
2945         status = hw->phy.ops.read_reg(hw,
2946                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2947                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2948                              &autoneg_reg);
2949
2950         if (status != IXGBE_SUCCESS)
2951                 return status;
2952
2953         save_autoneg = hw->phy.autoneg_advertised;
2954
2955         /* Setup link at least common link speed */
2956         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
2957
2958         /* restore autoneg from before setting lplu speed */
2959         hw->phy.autoneg_advertised = save_autoneg;
2960
2961         return status;
2962 }
2963
2964 /**
2965  * ixgbe_get_lcd_x550em - Determine lowest common denominator
2966  *  @hw: pointer to hardware structure
2967  *  @lcd_speed: pointer to lowest common link speed
2968  *
2969  * Determine lowest common link speed with link partner.
2970  **/
2971 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2972 {
2973         u16 an_lp_status;
2974         s32 status;
2975         u16 word = hw->eeprom.ctrl_word_3;
2976
2977         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2978
2979         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2980                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2981                                       &an_lp_status);
2982
2983         if (status != IXGBE_SUCCESS)
2984                 return status;
2985
2986         /* If link partner advertised 1G, return 1G */
2987         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2988                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2989                 return status;
2990         }
2991
2992         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2993         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2994             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2995                 return status;
2996
2997         /* Link partner not capable of lower speeds, return 10G */
2998         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2999         return status;
3000 }
3001
3002 /**
3003  *  ixgbe_setup_fc_X550em - Set up flow control
3004  *  @hw: pointer to hardware structure
3005  *
3006  *  Called at init time to set up flow control.
3007  **/
3008 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3009 {
3010         s32 ret_val = IXGBE_SUCCESS;
3011         u32 pause, asm_dir, reg_val;
3012
3013         DEBUGFUNC("ixgbe_setup_fc_X550em");
3014
3015         /* Validate the requested mode */
3016         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3017                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3018                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3019                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3020                 goto out;
3021         }
3022
3023         /* 10gig parts do not have a word in the EEPROM to determine the
3024          * default flow control setting, so we explicitly set it to full.
3025          */
3026         if (hw->fc.requested_mode == ixgbe_fc_default)
3027                 hw->fc.requested_mode = ixgbe_fc_full;
3028
3029         /* Determine PAUSE and ASM_DIR bits. */
3030         switch (hw->fc.requested_mode) {
3031         case ixgbe_fc_none:
3032                 pause = 0;
3033                 asm_dir = 0;
3034                 break;
3035         case ixgbe_fc_tx_pause:
3036                 pause = 0;
3037                 asm_dir = 1;
3038                 break;
3039         case ixgbe_fc_rx_pause:
3040                 /* Rx Flow control is enabled and Tx Flow control is
3041                  * disabled by software override. Since there really
3042                  * isn't a way to advertise that we are capable of RX
3043                  * Pause ONLY, we will advertise that we support both
3044                  * symmetric and asymmetric Rx PAUSE, as such we fall
3045                  * through to the fc_full statement.  Later, we will
3046                  * disable the adapter's ability to send PAUSE frames.
3047                  */
3048         case ixgbe_fc_full:
3049                 pause = 1;
3050                 asm_dir = 1;
3051                 break;
3052         default:
3053                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3054                         "Flow control param set incorrectly\n");
3055                 ret_val = IXGBE_ERR_CONFIG;
3056                 goto out;
3057         }
3058
3059         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
3060                 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
3061                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3062                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3063                 if (ret_val != IXGBE_SUCCESS)
3064                         goto out;
3065                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3066                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3067                 if (pause)
3068                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3069                 if (asm_dir)
3070                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3071                 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
3072                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3073                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3074
3075                 /* This device does not fully support AN. */
3076                 hw->fc.disable_fc_autoneg = true;
3077         }
3078
3079 out:
3080         return ret_val;
3081 }
3082
3083 /**
3084  * ixgbe_set_mux - Set mux for port 1 access with CS4227
3085  * @hw: pointer to hardware structure
3086  * @state: set mux if 1, clear if 0
3087  */
3088 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
3089 {
3090         u32 esdp;
3091
3092         if (!hw->bus.lan_id)
3093                 return;
3094         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3095         if (state)
3096                 esdp |= IXGBE_ESDP_SDP1;
3097         else
3098                 esdp &= ~IXGBE_ESDP_SDP1;
3099         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
3100         IXGBE_WRITE_FLUSH(hw);
3101 }
3102
3103 /**
3104  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
3105  *  @hw: pointer to hardware structure
3106  *  @mask: Mask to specify which semaphore to acquire
3107  *
3108  *  Acquires the SWFW semaphore and sets the I2C MUX
3109  **/
3110 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3111 {
3112         s32 status;
3113
3114         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
3115
3116         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
3117         if (status)
3118                 return status;
3119
3120         if (mask & IXGBE_GSSR_I2C_MASK)
3121                 ixgbe_set_mux(hw, 1);
3122
3123         return IXGBE_SUCCESS;
3124 }
3125
3126 /**
3127  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
3128  *  @hw: pointer to hardware structure
3129  *  @mask: Mask to specify which semaphore to release
3130  *
3131  *  Releases the SWFW semaphore and sets the I2C MUX
3132  **/
3133 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3134 {
3135         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
3136
3137         if (mask & IXGBE_GSSR_I2C_MASK)
3138                 ixgbe_set_mux(hw, 0);
3139
3140         ixgbe_release_swfw_sync_X540(hw, mask);
3141 }
3142
3143 /**
3144  *  ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
3145  *  @hw: pointer to hardware structure
3146  *  @mask: Mask to specify which semaphore to acquire
3147  *
3148  *  Acquires the SWFW semaphore and get the shared phy token as needed
3149  */
3150 static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
3151 {
3152         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3153         int retries = FW_PHY_TOKEN_RETRIES;
3154         s32 status = IXGBE_SUCCESS;
3155
3156         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
3157
3158         while (--retries) {
3159                 if (hmask)
3160                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
3161                 if (status)
3162                         break;
3163                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
3164                         break;
3165                 status = ixgbe_get_phy_token(hw);
3166                 if (status != IXGBE_ERR_TOKEN_RETRY)
3167                         break;
3168                 if (hmask)
3169                         ixgbe_release_swfw_sync_X540(hw, hmask);
3170                 msec_delay(FW_PHY_TOKEN_DELAY);
3171         }
3172
3173         return status;
3174 }
3175
3176 /**
3177  *  ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
3178  *  @hw: pointer to hardware structure
3179  *  @mask: Mask to specify which semaphore to release
3180  *
3181  *  Releases the SWFW semaphore and puts the shared phy token as needed
3182  */
3183 static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
3184 {
3185         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3186
3187         DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
3188
3189         if (mask & IXGBE_GSSR_TOKEN_SM)
3190                 ixgbe_put_phy_token(hw);
3191
3192         if (hmask)
3193                 ixgbe_release_swfw_sync_X540(hw, hmask);
3194 }
3195
3196 /**
3197  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
3198  * @hw: pointer to hardware structure
3199  *
3200  * Handle external Base T PHY interrupt. If high temperature
3201  * failure alarm then return error, else if link status change
3202  * then setup internal/external PHY link
3203  *
3204  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
3205  * failure alarm, else return PHY access status.
3206  */
3207 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
3208 {
3209         bool lsc;
3210         u32 status;
3211
3212         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
3213
3214         if (status != IXGBE_SUCCESS)
3215                 return status;
3216
3217         if (lsc)
3218                 return ixgbe_setup_internal_phy(hw);
3219
3220         return IXGBE_SUCCESS;
3221 }
3222
3223 /**
3224  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
3225  * @hw: pointer to hardware structure
3226  * @speed: new link speed
3227  * @autoneg_wait_to_complete: true when waiting for completion is needed
3228  *
3229  * Setup internal/external PHY link speed based on link speed, then set
3230  * external PHY auto advertised link speed.
3231  *
3232  * Returns error status for any failure
3233  **/
3234 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
3235                                   ixgbe_link_speed speed,
3236                                   bool autoneg_wait_to_complete)
3237 {
3238         s32 status;
3239         ixgbe_link_speed force_speed;
3240
3241         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
3242
3243         /* Setup internal/external PHY link speed to iXFI (10G), unless
3244          * only 1G is auto advertised then setup KX link.
3245          */
3246         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
3247                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3248         else
3249                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3250
3251         /* If internal link mode is XFI, then setup XFI internal link. */
3252         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3253                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
3254
3255                 if (status != IXGBE_SUCCESS)
3256                         return status;
3257         }
3258
3259         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
3260 }
3261
3262 /**
3263  * ixgbe_check_link_t_X550em - Determine link and speed status
3264  * @hw: pointer to hardware structure
3265  * @speed: pointer to link speed
3266  * @link_up: true when link is up
3267  * @link_up_wait_to_complete: bool used to wait for link up or not
3268  *
3269  * Check that both the MAC and X557 external PHY have link.
3270  **/
3271 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3272                               bool *link_up, bool link_up_wait_to_complete)
3273 {
3274         u32 status;
3275         u16 autoneg_status;
3276
3277         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3278                 return IXGBE_ERR_CONFIG;
3279
3280         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
3281                                               link_up_wait_to_complete);
3282
3283         /* If check link fails or MAC link is not up, then return */
3284         if (status != IXGBE_SUCCESS || !(*link_up))
3285                 return status;
3286
3287         /* MAC link is up, so check external PHY link.
3288          * Read this twice back to back to indicate current status.
3289          */
3290         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3291                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3292                                       &autoneg_status);
3293
3294         if (status != IXGBE_SUCCESS)
3295                 return status;
3296
3297         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3298                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3299                                       &autoneg_status);
3300
3301         if (status != IXGBE_SUCCESS)
3302                 return status;
3303
3304         /* If external PHY link is not up, then indicate link not up */
3305         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
3306                 *link_up = false;
3307
3308         return IXGBE_SUCCESS;
3309 }
3310
3311 /**
3312  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
3313  *  @hw: pointer to hardware structure
3314  **/
3315 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
3316 {
3317         s32 status;
3318
3319         status = ixgbe_reset_phy_generic(hw);
3320
3321         if (status != IXGBE_SUCCESS)
3322                 return status;
3323
3324         /* Configure Link Status Alarm and Temperature Threshold interrupts */
3325         return ixgbe_enable_lasi_ext_t_x550em(hw);
3326 }
3327
3328 /**
3329  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
3330  *  @hw: pointer to hardware structure
3331  *  @led_idx: led number to turn on
3332  **/
3333 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3334 {
3335         u16 phy_data;
3336
3337         DEBUGFUNC("ixgbe_led_on_t_X550em");
3338
3339         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3340                 return IXGBE_ERR_PARAM;
3341
3342         /* To turn on the LED, set mode to ON. */
3343         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3344                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3345         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
3346         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3347                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3348
3349         return IXGBE_SUCCESS;
3350 }
3351
3352 /**
3353  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
3354  *  @hw: pointer to hardware structure
3355  *  @led_idx: led number to turn off
3356  **/
3357 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3358 {
3359         u16 phy_data;
3360
3361         DEBUGFUNC("ixgbe_led_off_t_X550em");
3362
3363         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3364                 return IXGBE_ERR_PARAM;
3365
3366         /* To turn on the LED, set mode to ON. */
3367         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3368                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3369         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
3370         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3371                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3372
3373         return IXGBE_SUCCESS;
3374 }
3375