drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41
  42 /**
  43  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  44  *  @hw: pointer to hardware structure
  45  *
  46  *  Initialize the function pointers and assign the MAC type for X550.
  47  *  Does not touch the hardware.
  48  **/
  49 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  50 {
  51         struct ixgbe_mac_info *mac = &hw->mac;
  52         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  53         s32 ret_val;
  54
  55         DEBUGFUNC("ixgbe_init_ops_X550");
  56
  57         ret_val = ixgbe_init_ops_X540(hw);
  58         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  59         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  60         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  61         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  62         mac->ops.set_source_address_pruning =
  63                         ixgbe_set_source_address_pruning_X550;
  64         mac->ops.set_ethertype_anti_spoofing =
  65                         ixgbe_set_ethertype_anti_spoofing_X550;
  66
  67         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  68         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  69         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  70         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  71         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  72         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  73         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  74         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  75         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  76
  77         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  78         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  79         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  80         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  81         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  82         return ret_val;
  83 }
  84
  85 /**
  86  * ixgbe_read_cs4227 - Read CS4227 register
  87  * @hw: pointer to hardware structure
  88  * @reg: register number to write
  89  * @value: pointer to receive value read
  90  *
  91  * Returns status code
  92  **/
  93 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  94 {
  95         return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
  96 }
  97
  98 /**
  99  * ixgbe_write_cs4227 - Write CS4227 register
 100  * @hw: pointer to hardware structure
 101  * @reg: register number to write
 102  * @value: value to write to register
 103  *
 104  * Returns status code
 105  **/
 106 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 107 {
 108         return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 109 }
 110
 111 /**
 112  * ixgbe_get_cs4227_status - Return CS4227 status
 113  * @hw: pointer to hardware structure
 114  *
 115  * Returns error if CS4227 not successfully initialized
 116  **/
 117 STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
 118 {
 119         s32 status;
 120         u16 value = 0;
 121         u16 reg_slice, reg_val;
 122         u8 retry;
 123
 124         for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) {
 125                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB,
 126                                            &value);
 127                 if (status != IXGBE_SUCCESS)
 128                         return status;
 129                 if (value == IXGBE_CS4227_GLOBAL_ID_VALUE)
 130                         break;
 131                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 132         }
 133         if (value != IXGBE_CS4227_GLOBAL_ID_VALUE)
 134                 return IXGBE_ERR_PHY;
 135
 136         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 137         if (status != IXGBE_SUCCESS)
 138                 return status;
 139
 140         /* If this is the first time after power-on, check the ucode.
 141          * Otherwise, this will disrupt link on all ports. Because we
 142          * can only do this the first time, we must check all ports,
 143          * not just our own.
 144          */
 145         if (value != IXGBE_CS4227_SCRATCH_VALUE) {
 146                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB;
 147                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
 148                 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
 149                 if (status != IXGBE_SUCCESS)
 150                         return status;
 151
 152                 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB;
 153                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
 154                 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
 155                 if (status != IXGBE_SUCCESS)
 156                         return status;
 157
 158                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (1 << 12);
 159                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
 160                 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
 161                 if (status != IXGBE_SUCCESS)
 162                         return status;
 163
 164                 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (1 << 12);
 165                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
 166                 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
 167                 if (status != IXGBE_SUCCESS)
 168                         return status;
 169
 170                 msec_delay(10);
 171         }
 172
 173         /* Verify that the ucode is operational on all ports. */
 174         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB;
 175         reg_val = 0xFFFF;
 176         status = ixgbe_read_cs4227(hw, reg_slice, &reg_val);
 177         if (status != IXGBE_SUCCESS)
 178                 return status;
 179         if (reg_val != 0)
 180                 return IXGBE_ERR_PHY;
 181
 182         reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB;
 183         reg_val = 0xFFFF;
 184         status = ixgbe_read_cs4227(hw, reg_slice, &reg_val);
 185         if (status != IXGBE_SUCCESS)
 186                 return status;
 187         if (reg_val != 0)
 188                 return IXGBE_ERR_PHY;
 189
 190         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (1 << 12);
 191         reg_val = 0xFFFF;
 192         status = ixgbe_read_cs4227(hw, reg_slice, &reg_val);
 193         if (status != IXGBE_SUCCESS)
 194                 return status;
 195         if (reg_val != 0)
 196                 return IXGBE_ERR_PHY;
 197
 198         reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (1 << 12);
 199         reg_val = 0xFFFF;
 200         status = ixgbe_read_cs4227(hw, reg_slice, &reg_val);
 201         if (status != IXGBE_SUCCESS)
 202                 return status;
 203         if (reg_val != 0)
 204                 return IXGBE_ERR_PHY;
 205
 206         /* Set scratch indicating that the diagnostic was successful. */
 207         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 208                                     IXGBE_CS4227_SCRATCH_VALUE);
 209         if (status != IXGBE_SUCCESS)
 210                 return status;
 211         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 212         if (status != IXGBE_SUCCESS)
 213                 return status;
 214         if (value != IXGBE_CS4227_SCRATCH_VALUE)
 215                 return IXGBE_ERR_PHY;
 216
 217         return IXGBE_SUCCESS;
 218 }
 219
 220 /**
 221  * ixgbe_read_pe - Read register from port expander
 222  * @hw: pointer to hardware structure
 223  * @reg: register number to read
 224  * @value: pointer to receive read value
 225  *
 226  * Returns status code
 227  **/
 228 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 229 {
 230         s32 status;
 231
 232         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 233         if (status != IXGBE_SUCCESS)
 234                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 235                               "port expander access failed with %d\n", status);
 236         return status;
 237 }
 238
 239 /**
 240  * ixgbe_write_pe - Write register to port expander
 241  * @hw: pointer to hardware structure
 242  * @reg: register number to write
 243  * @value: value to write
 244  *
 245  * Returns status code
 246  **/
 247 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 248 {
 249         s32 status;
 250
 251         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 252         if (status != IXGBE_SUCCESS)
 253                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 254                               "port expander access failed with %d\n", status);
 255         return status;
 256 }
 257
 258 /**
 259  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 260  * @hw: pointer to hardware structure
 261  *
 262  * Returns error code
 263  **/
 264 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 265 {
 266         s32 status;
 267         u8 reg;
 268
 269         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 270         if (status != IXGBE_SUCCESS)
 271                 return status;
 272         reg |= IXGBE_PE_BIT1;
 273         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 274         if (status != IXGBE_SUCCESS)
 275                 return status;
 276
 277         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 278         if (status != IXGBE_SUCCESS)
 279                 return status;
 280         reg &= ~IXGBE_PE_BIT1;
 281         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 282         if (status != IXGBE_SUCCESS)
 283                 return status;
 284
 285         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 286         if (status != IXGBE_SUCCESS)
 287                 return status;
 288         reg &= ~IXGBE_PE_BIT1;
 289         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 290         if (status != IXGBE_SUCCESS)
 291                 return status;
 292
 293         usec_delay(IXGBE_CS4227_RESET_HOLD);
 294
 295         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 296         if (status != IXGBE_SUCCESS)
 297                 return status;
 298         reg |= IXGBE_PE_BIT1;
 299         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 300         if (status != IXGBE_SUCCESS)
 301                 return status;
 302
 303         msec_delay(IXGBE_CS4227_RESET_DELAY);
 304
 305         return IXGBE_SUCCESS;
 306 }
 307
 308 /**
 309  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 310  * @hw: pointer to hardware structure
 311  **/
 312 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 313 {
 314         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 315         s32 status;
 316         u8 retry;
 317
 318         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 319                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 320                 if (status != IXGBE_SUCCESS) {
 321                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 322                                       "semaphore failed with %d\n", status);
 323                         return;
 324                 }
 325                 status = ixgbe_get_cs4227_status(hw);
 326                 if (status == IXGBE_SUCCESS) {
 327                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 328                         msec_delay(hw->eeprom.semaphore_delay);
 329                         return;
 330                 }
 331                 ixgbe_reset_cs4227(hw);
 332                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 333                 msec_delay(hw->eeprom.semaphore_delay);
 334         }
 335         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 336                       "Unable to initialize CS4227, err=%d\n", status);
 337 }
 338
 339 /**
 340  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 341  * @hw: pointer to hardware structure
 342  **/
 343 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 344 {
 345         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 346
 347         if (hw->bus.lan_id) {
 348                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 349                 esdp |= IXGBE_ESDP_SDP1_DIR;
 350         }
 351         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 352         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 353         IXGBE_WRITE_FLUSH(hw);
 354 }
 355
 356 /**
 357  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 358  * @hw: pointer to hardware structure
 359  *
 360  * Returns error code
 361  */
 362 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 363 {
 364         switch (hw->device_id) {
 365         case IXGBE_DEV_ID_X550EM_X_SFP:
 366                 /* set up for CS4227 usage */
 367                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 368                 ixgbe_setup_mux_ctl(hw);
 369                 ixgbe_check_cs4227(hw);
 370
 371                 return ixgbe_identify_module_generic(hw);
 372                 break;
 373         case IXGBE_DEV_ID_X550EM_X_KX4:
 374                 hw->phy.type = ixgbe_phy_x550em_kx4;
 375                 break;
 376         case IXGBE_DEV_ID_X550EM_X_KR:
 377                 hw->phy.type = ixgbe_phy_x550em_kr;
 378                 break;
 379         case IXGBE_DEV_ID_X550EM_X_1G_T:
 380         case IXGBE_DEV_ID_X550EM_X_10G_T:
 381                 return ixgbe_identify_phy_generic(hw);
 382         default:
 383                 break;
 384         }
 385         return IXGBE_SUCCESS;
 386 }
 387
 388 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 389                                      u32 device_type, u16 *phy_data)
 390 {
 391         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 392         return IXGBE_NOT_IMPLEMENTED;
 393 }
 394
 395 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 396                                       u32 device_type, u16 phy_data)
 397 {
 398         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 399         return IXGBE_NOT_IMPLEMENTED;
 400 }
 401
 402 /**
 403 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 404 *  @hw: pointer to hardware structure
 405 *
 406 *  Initialize the function pointers and for MAC type X550EM.
 407 *  Does not touch the hardware.
 408 **/
 409 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 410 {
 411         struct ixgbe_mac_info *mac = &hw->mac;
 412         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 413         struct ixgbe_phy_info *phy = &hw->phy;
 414         s32 ret_val;
 415
 416         DEBUGFUNC("ixgbe_init_ops_X550EM");
 417
 418         /* Similar to X550 so start there. */
 419         ret_val = ixgbe_init_ops_X550(hw);
 420
 421         /* Since this function eventually calls
 422          * ixgbe_init_ops_540 by design, we are setting
 423          * the pointers to NULL explicitly here to overwrite
 424          * the values being set in the x540 function.
 425          */
 426         /* Thermal sensor not supported in x550EM */
 427         mac->ops.get_thermal_sensor_data = NULL;
 428         mac->ops.init_thermal_sensor_thresh = NULL;
 429         mac->thermal_sensor_enabled = false;
 430
 431         /* FCOE not supported in x550EM */
 432         mac->ops.get_san_mac_addr = NULL;
 433         mac->ops.set_san_mac_addr = NULL;
 434         mac->ops.get_wwn_prefix = NULL;
 435         mac->ops.get_fcoe_boot_status = NULL;
 436
 437         /* IPsec not supported in x550EM */
 438         mac->ops.disable_sec_rx_path = NULL;
 439         mac->ops.enable_sec_rx_path = NULL;
 440
 441         /* AUTOC register is not present in x550EM. */
 442         mac->ops.prot_autoc_read = NULL;
 443         mac->ops.prot_autoc_write = NULL;
 444
 445         /* X550EM bus type is internal*/
 446         hw->bus.type = ixgbe_bus_type_internal;
 447         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 448
 449         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 450         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 451         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 452         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 453         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 454         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 455         mac->ops.get_supported_physical_layer =
 456                                     ixgbe_get_supported_physical_layer_X550em;
 457
 458         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 459                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 460         else
 461                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 462
 463         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 464         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 465
 466         if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
 467                 mac->ops.setup_eee = NULL;
 468
 469         /* PHY */
 470         phy->ops.init = ixgbe_init_phy_ops_X550em;
 471         phy->ops.identify = ixgbe_identify_phy_x550em;
 472         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 473                 phy->ops.set_phy_power = NULL;
 474
 475
 476         /* EEPROM */
 477         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 478         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 479         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 480         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 481         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 482         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 483         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 484         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 485
 486         return ret_val;
 487 }
 488
 489 /**
 490  *  ixgbe_dmac_config_X550
 491  *  @hw: pointer to hardware structure
 492  *
 493  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 494  *  When disabling dmac, dmac enable dmac bit is cleared.
 495  **/
 496 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 497 {
 498         u32 reg, high_pri_tc;
 499
 500         DEBUGFUNC("ixgbe_dmac_config_X550");
 501
 502         /* Disable DMA coalescing before configuring */
 503         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 504         reg &= ~IXGBE_DMACR_DMAC_EN;
 505         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 506
 507         /* Disable DMA Coalescing if the watchdog timer is 0 */
 508         if (!hw->mac.dmac_config.watchdog_timer)
 509                 goto out;
 510
 511         ixgbe_dmac_config_tcs_X550(hw);
 512
 513         /* Configure DMA Coalescing Control Register */
 514         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 515
 516         /* Set the watchdog timer in units of 40.96 usec */
 517         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 518         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 519
 520         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 521         /* If fcoe is enabled, set high priority traffic class */
 522         if (hw->mac.dmac_config.fcoe_en) {
 523                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 524                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 525                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 526         }
 527         reg |= IXGBE_DMACR_EN_MNG_IND;
 528
 529         /* Enable DMA coalescing after configuration */
 530         reg |= IXGBE_DMACR_DMAC_EN;
 531         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 532
 533 out:
 534         return IXGBE_SUCCESS;
 535 }
 536
 537 /**
 538  *  ixgbe_dmac_config_tcs_X550
 539  *  @hw: pointer to hardware structure
 540  *
 541  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 542  *  be cleared before configuring.
 543  **/
 544 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 545 {
 546         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 547
 548         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 549
 550         /* Configure DMA coalescing enabled */
 551         switch (hw->mac.dmac_config.link_speed) {
 552         case IXGBE_LINK_SPEED_100_FULL:
 553                 pb_headroom = IXGBE_DMACRXT_100M;
 554                 break;
 555         case IXGBE_LINK_SPEED_1GB_FULL:
 556                 pb_headroom = IXGBE_DMACRXT_1G;
 557                 break;
 558         default:
 559                 pb_headroom = IXGBE_DMACRXT_10G;
 560                 break;
 561         }
 562
 563         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 564                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 565
 566         /* Set the per Rx packet buffer receive threshold */
 567         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 568                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 569                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 570
 571                 if (tc < hw->mac.dmac_config.num_tcs) {
 572                         /* Get Rx PB size */
 573                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 574                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 575                                 IXGBE_RXPBSIZE_SHIFT;
 576
 577                         /* Calculate receive buffer threshold in kilobytes */
 578                         if (rx_pb_size > pb_headroom)
 579                                 rx_pb_size = rx_pb_size - pb_headroom;
 580                         else
 581                                 rx_pb_size = 0;
 582
 583                         /* Minimum of MFS shall be set for DMCTH */
 584                         reg |= (rx_pb_size > maxframe_size_kb) ?
 585                                 rx_pb_size : maxframe_size_kb;
 586                 }
 587                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 588         }
 589         return IXGBE_SUCCESS;
 590 }
 591
 592 /**
 593  *  ixgbe_dmac_update_tcs_X550
 594  *  @hw: pointer to hardware structure
 595  *
 596  *  Disables dmac, updates per TC settings, and then enables dmac.
 597  **/
 598 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 599 {
 600         u32 reg;
 601
 602         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 603
 604         /* Disable DMA coalescing before configuring */
 605         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 606         reg &= ~IXGBE_DMACR_DMAC_EN;
 607         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 608
 609         ixgbe_dmac_config_tcs_X550(hw);
 610
 611         /* Enable DMA coalescing after configuration */
 612         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 613         reg |= IXGBE_DMACR_DMAC_EN;
 614         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 615
 616         return IXGBE_SUCCESS;
 617 }
 618
 619 /**
 620  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 621  *  @hw: pointer to hardware structure
 622  *
 623  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 624  *  ixgbe_hw struct in order to set up EEPROM access.
 625  **/
 626 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 627 {
 628         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 629         u32 eec;
 630         u16 eeprom_size;
 631
 632         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 633
 634         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 635                 eeprom->semaphore_delay = 10;
 636                 eeprom->type = ixgbe_flash;
 637
 638                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 639                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 640                                     IXGBE_EEC_SIZE_SHIFT);
 641                 eeprom->word_size = 1 << (eeprom_size +
 642                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 643
 644                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 645                           eeprom->type, eeprom->word_size);
 646         }
 647
 648         return IXGBE_SUCCESS;
 649 }
 650
 651 /**
 652  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 653  *  @hw: pointer to the HW structure
 654  *  @enable_eee: boolean flag to enable EEE
 655  *
 656  *  Enable/disable EEE based on enable_eee flag.
 657  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 658  *  are modified.
 659  *
 660  **/
 661 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 662 {
 663         u32 eeer;
 664         u16 autoneg_eee_reg;
 665         u32 link_reg;
 666         s32 status;
 667         u32 fuse;
 668
 669         DEBUGFUNC("ixgbe_setup_eee_X550");
 670
 671         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 672         /* Enable or disable EEE per flag */
 673         if (enable_eee) {
 674                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 675
 676                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 677                         /* Advertise EEE capability */
 678                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 679                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 680
 681                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 682                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 683                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 684
 685                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 686                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 687                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 688                         /* Not supported on first revision. */
 689                         fuse = IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0));
 690                         if (!(fuse & IXGBE_FUSES0_REV1))
 691                                 return IXGBE_SUCCESS;
 692
 693                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 694                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 695                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 696                         if (status != IXGBE_SUCCESS)
 697                                 return status;
 698
 699                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 700                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 701
 702                         /* Don't advertise FEC capability when EEE enabled. */
 703                         link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 704
 705                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 706                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 707                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 708                         if (status != IXGBE_SUCCESS)
 709                                 return status;
 710                 }
 711         } else {
 712                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 713
 714                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 715                         /* Disable advertised EEE capability */
 716                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 717                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 718
 719                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 720                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 721                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 722
 723                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 724                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 725                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 726                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 727                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 728                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 729                         if (status != IXGBE_SUCCESS)
 730                                 return status;
 731
 732                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 733                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 734
 735                         /* Advertise FEC capability when EEE is disabled. */
 736                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 737
 738                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 739                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 740                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 741                         if (status != IXGBE_SUCCESS)
 742                                 return status;
 743                 }
 744         }
 745         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 746
 747         return IXGBE_SUCCESS;
 748 }
 749
 750 /**
 751  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 752  * @hw: pointer to hardware structure
 753  * @enable: enable or disable source address pruning
 754  * @pool: Rx pool to set source address pruning for
 755  **/
 756 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 757                                            unsigned int pool)
 758 {
 759         u64 pfflp;
 760
 761         /* max rx pool is 63 */
 762         if (pool > 63)
 763                 return;
 764
 765         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 766         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 767
 768         if (enable)
 769                 pfflp |= (1ULL << pool);
 770         else
 771                 pfflp &= ~(1ULL << pool);
 772
 773         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 774         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 775 }
 776
 777 /**
 778  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 779  *  @hw: pointer to hardware structure
 780  *  @enable: enable or disable switch for Ethertype anti-spoofing
 781  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 782  *
 783  **/
 784 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 785                 bool enable, int vf)
 786 {
 787         int vf_target_reg = vf >> 3;
 788         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 789         u32 pfvfspoof;
 790
 791         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 792
 793         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 794         if (enable)
 795                 pfvfspoof |= (1 << vf_target_shift);
 796         else
 797                 pfvfspoof &= ~(1 << vf_target_shift);
 798
 799         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 800 }
 801
 802 /**
 803  * ixgbe_iosf_wait - Wait for IOSF command completion
 804  * @hw: pointer to hardware structure
 805  * @ctrl: pointer to location to receive final IOSF control value
 806  *
 807  * Returns failing status on timeout
 808  *
 809  * Note: ctrl can be NULL if the IOSF control register value is not needed
 810  **/
 811 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
 812 {
 813         u32 i, command = 0;
 814
 815         /* Check every 10 usec to see if the address cycle completed.
 816          * The SB IOSF BUSY bit will clear when the operation is
 817          * complete
 818          */
 819         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 820                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 821                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 822                         break;
 823                 usec_delay(10);
 824         }
 825         if (ctrl)
 826                 *ctrl = command;
 827         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 828                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
 829                 return IXGBE_ERR_PHY;
 830         }
 831
 832         return IXGBE_SUCCESS;
 833 }
 834
 835 /**
 836  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 837  *  device
 838  *  @hw: pointer to hardware structure
 839  *  @reg_addr: 32 bit PHY register to write
 840  *  @device_type: 3 bit device type
 841  *  @data: Data to write to the register
 842  **/
 843 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 844                             u32 device_type, u32 data)
 845 {
 846         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 847         u32 command, error;
 848         s32 ret;
 849
 850         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
 851         if (ret != IXGBE_SUCCESS)
 852                 return ret;
 853
 854         ret = ixgbe_iosf_wait(hw, NULL);
 855         if (ret != IXGBE_SUCCESS)
 856                 goto out;
 857
 858         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 859                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 860
 861         /* Write IOSF control register */
 862         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 863
 864         /* Write IOSF data register */
 865         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 866
 867         ret = ixgbe_iosf_wait(hw, &command);
 868
 869         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 870                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 871                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 872                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 873                               "Failed to write, error %x\n", error);
 874                 ret = IXGBE_ERR_PHY;
 875         }
 876
 877 out:
 878         ixgbe_release_swfw_semaphore(hw, gssr);
 879         return ret;
 880 }
 881
 882 /**
 883  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 884  *  device
 885  *  @hw: pointer to hardware structure
 886  *  @reg_addr: 32 bit PHY register to write
 887  *  @device_type: 3 bit device type
 888  *  @phy_data: Pointer to read data from the register
 889  **/
 890 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 891                            u32 device_type, u32 *data)
 892 {
 893         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 894         u32 command, error;
 895         s32 ret;
 896
 897         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
 898         if (ret != IXGBE_SUCCESS)
 899                 return ret;
 900
 901         ret = ixgbe_iosf_wait(hw, NULL);
 902         if (ret != IXGBE_SUCCESS)
 903                 goto out;
 904
 905         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 906                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 907
 908         /* Write IOSF control register */
 909         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 910
 911         ret = ixgbe_iosf_wait(hw, &command);
 912
 913         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 914                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 915                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 916                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 917                                 "Failed to read, error %x\n", error);
 918                 ret = IXGBE_ERR_PHY;
 919         }
 920
 921         if (ret == IXGBE_SUCCESS)
 922                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 923
 924 out:
 925         ixgbe_release_swfw_semaphore(hw, gssr);
 926         return ret;
 927 }
 928
 929 /**
 930  *  ixgbe_disable_mdd_X550
 931  *  @hw: pointer to hardware structure
 932  *
 933  *  Disable malicious driver detection
 934  **/
 935 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
 936 {
 937         u32 reg;
 938
 939         DEBUGFUNC("ixgbe_disable_mdd_X550");
 940
 941         /* Disable MDD for TX DMA and interrupt */
 942         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 943         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 944         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 945
 946         /* Disable MDD for RX and interrupt */
 947         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 948         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 949         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 950 }
 951
 952 /**
 953  *  ixgbe_enable_mdd_X550
 954  *  @hw: pointer to hardware structure
 955  *
 956  *  Enable malicious driver detection
 957  **/
 958 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
 959 {
 960         u32 reg;
 961
 962         DEBUGFUNC("ixgbe_enable_mdd_X550");
 963
 964         /* Enable MDD for TX DMA and interrupt */
 965         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 966         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 967         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 968
 969         /* Enable MDD for RX and interrupt */
 970         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 971         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 972         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 973 }
 974
 975 /**
 976  *  ixgbe_restore_mdd_vf_X550
 977  *  @hw: pointer to hardware structure
 978  *  @vf: vf index
 979  *
 980  *  Restore VF that was disabled during malicious driver detection event
 981  **/
 982 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
 983 {
 984         u32 idx, reg, num_qs, start_q, bitmask;
 985
 986         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
 987
 988         /* Map VF to queues */
 989         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 990         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 991         case IXGBE_MRQC_VMDQRT8TCEN:
 992                 num_qs = 8;  /* 16 VFs / pools */
 993                 bitmask = 0x000000FF;
 994                 break;
 995         case IXGBE_MRQC_VMDQRSS32EN:
 996         case IXGBE_MRQC_VMDQRT4TCEN:
 997                 num_qs = 4;  /* 32 VFs / pools */
 998                 bitmask = 0x0000000F;
 999                 break;
1000         default:            /* 64 VFs / pools */
1001                 num_qs = 2;
1002                 bitmask = 0x00000003;
1003                 break;
1004         }
1005         start_q = vf * num_qs;
1006
1007         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1008         idx = start_q / 32;
1009         reg = 0;
1010         reg |= (bitmask << (start_q % 32));
1011         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1012         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1013 }
1014
1015 /**
1016  *  ixgbe_mdd_event_X550
1017  *  @hw: pointer to hardware structure
1018  *  @vf_bitmap: vf bitmap of malicious vfs
1019  *
1020  *  Handle malicious driver detection event.
1021  **/
1022 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1023 {
1024         u32 wqbr;
1025         u32 i, j, reg, q, shift, vf, idx;
1026
1027         DEBUGFUNC("ixgbe_mdd_event_X550");
1028
1029         /* figure out pool size for mapping to vf's */
1030         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1031         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1032         case IXGBE_MRQC_VMDQRT8TCEN:
1033                 shift = 3;  /* 16 VFs / pools */
1034                 break;
1035         case IXGBE_MRQC_VMDQRSS32EN:
1036         case IXGBE_MRQC_VMDQRT4TCEN:
1037                 shift = 2;  /* 32 VFs / pools */
1038                 break;
1039         default:
1040                 shift = 1;  /* 64 VFs / pools */
1041                 break;
1042         }
1043
1044         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1045         for (i = 0; i < 4; i++) {
1046                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1047                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1048
1049                 if (!wqbr)
1050                         continue;
1051
1052                 /* Get malicious queue */
1053                 for (j = 0; j < 32 && wqbr; j++) {
1054
1055                         if (!(wqbr & (1 << j)))
1056                                 continue;
1057
1058                         /* Get queue from bitmask */
1059                         q = j + (i * 32);
1060
1061                         /* Map queue to vf */
1062                         vf = (q >> shift);
1063
1064                         /* Set vf bit in vf_bitmap */
1065                         idx = vf / 32;
1066                         vf_bitmap[idx] |= (1 << (vf % 32));
1067                         wqbr &= ~(1 << j);
1068                 }
1069         }
1070 }
1071
1072 /**
1073  *  ixgbe_get_media_type_X550em - Get media type
1074  *  @hw: pointer to hardware structure
1075  *
1076  *  Returns the media type (fiber, copper, backplane)
1077  */
1078 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1079 {
1080         enum ixgbe_media_type media_type;
1081
1082         DEBUGFUNC("ixgbe_get_media_type_X550em");
1083
1084         /* Detect if there is a copper PHY attached. */
1085         switch (hw->device_id) {
1086         case IXGBE_DEV_ID_X550EM_X_KR:
1087         case IXGBE_DEV_ID_X550EM_X_KX4:
1088                 media_type = ixgbe_media_type_backplane;
1089                 break;
1090         case IXGBE_DEV_ID_X550EM_X_SFP:
1091                 media_type = ixgbe_media_type_fiber;
1092                 break;
1093         case IXGBE_DEV_ID_X550EM_X_1G_T:
1094         case IXGBE_DEV_ID_X550EM_X_10G_T:
1095                 media_type = ixgbe_media_type_copper;
1096                 break;
1097         default:
1098                 media_type = ixgbe_media_type_unknown;
1099                 break;
1100         }
1101         return media_type;
1102 }
1103
1104 /**
1105  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1106  *  @hw: pointer to hardware structure
1107  *  @linear: true if SFP module is linear
1108  */
1109 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1110 {
1111         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1112
1113         switch (hw->phy.sfp_type) {
1114         case ixgbe_sfp_type_not_present:
1115                 return IXGBE_ERR_SFP_NOT_PRESENT;
1116         case ixgbe_sfp_type_da_cu_core0:
1117         case ixgbe_sfp_type_da_cu_core1:
1118                 *linear = true;
1119                 break;
1120         case ixgbe_sfp_type_srlr_core0:
1121         case ixgbe_sfp_type_srlr_core1:
1122         case ixgbe_sfp_type_da_act_lmt_core0:
1123         case ixgbe_sfp_type_da_act_lmt_core1:
1124         case ixgbe_sfp_type_1g_sx_core0:
1125         case ixgbe_sfp_type_1g_sx_core1:
1126         case ixgbe_sfp_type_1g_lx_core0:
1127         case ixgbe_sfp_type_1g_lx_core1:
1128                 *linear = false;
1129                 break;
1130         case ixgbe_sfp_type_unknown:
1131         case ixgbe_sfp_type_1g_cu_core0:
1132         case ixgbe_sfp_type_1g_cu_core1:
1133         default:
1134                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1135         }
1136
1137         return IXGBE_SUCCESS;
1138 }
1139
1140 /**
1141  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1142  *  @hw: pointer to hardware structure
1143  *
1144  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1145  **/
1146 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1147 {
1148         s32 status;
1149         bool linear;
1150
1151         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1152
1153         status = ixgbe_identify_module_generic(hw);
1154
1155         if (status != IXGBE_SUCCESS)
1156                 return status;
1157
1158         /* Check if SFP module is supported */
1159         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1160
1161         return status;
1162 }
1163
1164 /**
1165  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1166  *  @hw: pointer to hardware structure
1167  */
1168 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1169 {
1170         s32 status;
1171         bool linear;
1172
1173         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1174
1175         /* Check if SFP module is supported */
1176         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1177
1178         if (status != IXGBE_SUCCESS)
1179                 return status;
1180
1181         ixgbe_init_mac_link_ops_X550em(hw);
1182         hw->phy.ops.reset = NULL;
1183
1184         return IXGBE_SUCCESS;
1185 }
1186
1187 /**
1188  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1189  *  @hw: pointer to hardware structure
1190  */
1191 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1192 {
1193         struct ixgbe_mac_info *mac = &hw->mac;
1194
1195         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1196
1197          switch (hw->mac.ops.get_media_type(hw)) {
1198          case ixgbe_media_type_fiber:
1199                 /* CS4227 does not support autoneg, so disable the laser control
1200                  * functions for SFP+ fiber
1201                  */
1202                 mac->ops.disable_tx_laser = NULL;
1203                 mac->ops.enable_tx_laser = NULL;
1204                 mac->ops.flap_tx_laser = NULL;
1205                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1206                 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1207                 mac->ops.set_rate_select_speed =
1208                                         ixgbe_set_soft_rate_select_speed;
1209                 break;
1210         case ixgbe_media_type_copper:
1211                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1212                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1213                 break;
1214         default:
1215                 break;
1216          }
1217 }
1218
1219 /**
1220  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1221  *  @hw: pointer to hardware structure
1222  *  @speed: pointer to link speed
1223  *  @autoneg: true when autoneg or autotry is enabled
1224  */
1225 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1226                                        ixgbe_link_speed *speed,
1227                                        bool *autoneg)
1228 {
1229         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1230
1231         /* SFP */
1232         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1233
1234                 /* CS4227 SFP must not enable auto-negotiation */
1235                 *autoneg = false;
1236
1237                 /* Check if 1G SFP module. */
1238                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1239                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1240                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1241                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1242                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1243                         return IXGBE_SUCCESS;
1244                 }
1245
1246                 /* Link capabilities are based on SFP */
1247                 if (hw->phy.multispeed_fiber)
1248                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1249                                  IXGBE_LINK_SPEED_1GB_FULL;
1250                 else
1251                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1252         } else {
1253                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1254                          IXGBE_LINK_SPEED_1GB_FULL;
1255                 *autoneg = true;
1256         }
1257
1258         return IXGBE_SUCCESS;
1259 }
1260
1261 /**
1262  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1263  * @hw: pointer to hardware structure
1264  * @lsc: pointer to boolean flag which indicates whether external Base T
1265  *       PHY interrupt is lsc
1266  *
1267  * Determime if external Base T PHY interrupt cause is high temperature
1268  * failure alarm or link status change.
1269  *
1270  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1271  * failure alarm, else return PHY access status.
1272  */
1273 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1274 {
1275         u32 status;
1276         u16 reg;
1277
1278         *lsc = false;
1279
1280         /* Vendor alarm triggered */
1281         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1282                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1283                                       &reg);
1284
1285         if (status != IXGBE_SUCCESS ||
1286             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1287                 return status;
1288
1289         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1290         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1291                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1292                                       &reg);
1293
1294         if (status != IXGBE_SUCCESS ||
1295             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1296             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1297                 return status;
1298
1299         /* High temperature failure alarm triggered */
1300         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1301                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1302                                       &reg);
1303
1304         if (status != IXGBE_SUCCESS)
1305                 return status;
1306
1307         /* If high temperature failure, then return over temp error and exit */
1308         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1309                 /* power down the PHY in case the PHY FW didn't already */
1310                 ixgbe_set_copper_phy_power(hw, false);
1311                 return IXGBE_ERR_OVERTEMP;
1312         }
1313
1314         /* Vendor alarm 2 triggered */
1315         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1316                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1317
1318         if (status != IXGBE_SUCCESS ||
1319             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1320                 return status;
1321
1322         /* link connect/disconnect event occurred */
1323         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1324                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1325
1326         if (status != IXGBE_SUCCESS)
1327                 return status;
1328
1329         /* Indicate LSC */
1330         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1331                 *lsc = true;
1332
1333         return IXGBE_SUCCESS;
1334 }
1335
1336 /**
1337  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1338  * @hw: pointer to hardware structure
1339  *
1340  * Enable link status change and temperature failure alarm for the external
1341  * Base T PHY
1342  *
1343  * Returns PHY access status
1344  */
1345 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1346 {
1347         u32 status;
1348         u16 reg;
1349         bool lsc;
1350
1351         /* Clear interrupt flags */
1352         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1353
1354         /* Enable link status change alarm */
1355         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1356                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1357
1358         if (status != IXGBE_SUCCESS)
1359                 return status;
1360
1361         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1362
1363         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1364                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1365
1366         if (status != IXGBE_SUCCESS)
1367                 return status;
1368
1369         /* Enables high temperature failure alarm */
1370         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1371                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1372                                       &reg);
1373
1374         if (status != IXGBE_SUCCESS)
1375                 return status;
1376
1377         reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;
1378
1379         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1380                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1381                                        reg);
1382
1383         if (status != IXGBE_SUCCESS)
1384                 return status;
1385
1386         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1387         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1388                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1389                                       &reg);
1390
1391         if (status != IXGBE_SUCCESS)
1392                 return status;
1393
1394         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1395                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1396
1397         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1398                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1399                                        reg);
1400
1401         if (status != IXGBE_SUCCESS)
1402                 return status;
1403
1404         /* Enable chip-wide vendor alarm */
1405         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1406                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1407                                       &reg);
1408
1409         if (status != IXGBE_SUCCESS)
1410                 return status;
1411
1412         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1413
1414         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1415                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1416                                        reg);
1417
1418         return status;
1419 }
1420
1421 /**
1422  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1423  *  @hw: pointer to hardware structure
1424  *  @speed: link speed
1425  *
1426  *  Configures the integrated KR PHY.
1427  **/
1428 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1429                                        ixgbe_link_speed speed)
1430 {
1431         s32 status;
1432         u32 reg_val;
1433
1434         status = ixgbe_read_iosf_sb_reg_x550(hw,
1435                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1436                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1437         if (status)
1438                 return status;
1439
1440         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1441         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1442                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1443
1444         /* Advertise 10G support. */
1445         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1446                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1447
1448         /* Advertise 1G support. */
1449         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1450                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1451
1452         /* Restart auto-negotiation. */
1453         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1454         status = ixgbe_write_iosf_sb_reg_x550(hw,
1455                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1456                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1457
1458         return status;
1459 }
1460
1461 /**
1462  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1463  *  @hw: pointer to hardware structure
1464  *
1465  *  Initialize any function pointers that were not able to be
1466  *  set during init_shared_code because the PHY/SFP type was
1467  *  not known.  Perform the SFP init if necessary.
1468  */
1469 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1470 {
1471         struct ixgbe_phy_info *phy = &hw->phy;
1472         ixgbe_link_speed speed;
1473         s32 ret_val;
1474
1475         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1476
1477         hw->mac.ops.set_lan_id(hw);
1478
1479         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1480                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1481                 ixgbe_setup_mux_ctl(hw);
1482
1483                 /* Save NW management interface connected on board. This is used
1484                  * to determine internal PHY mode.
1485                  */
1486                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1487
1488                 /* If internal PHY mode is KR, then initialize KR link */
1489                 if (phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) {
1490                         speed = IXGBE_LINK_SPEED_10GB_FULL |
1491                                 IXGBE_LINK_SPEED_1GB_FULL;
1492                         ret_val = ixgbe_setup_kr_speed_x550em(hw, speed);
1493                 }
1494
1495                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
1496         }
1497
1498         /* Identify the PHY or SFP module */
1499         ret_val = phy->ops.identify(hw);
1500         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1501                 return ret_val;
1502
1503         /* Setup function pointers based on detected hardware */
1504         ixgbe_init_mac_link_ops_X550em(hw);
1505         if (phy->sfp_type != ixgbe_sfp_type_unknown)
1506                 phy->ops.reset = NULL;
1507
1508         /* Set functions pointers based on phy type */
1509         switch (hw->phy.type) {
1510         case ixgbe_phy_x550em_kx4:
1511                 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
1512                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1513                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1514                 break;
1515         case ixgbe_phy_x550em_kr:
1516                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1517                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1518                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1519                 break;
1520         case ixgbe_phy_x550em_ext_t:
1521                 /* Save NW management interface connected on board. This is used
1522                  * to determine internal PHY mode
1523                  */
1524                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1525
1526                 /* If internal link mode is XFI, then setup iXFI internal link,
1527                  * else setup KR now.
1528                  */
1529                 if (!(phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1530                         phy->ops.setup_internal_link =
1531                                               ixgbe_setup_internal_phy_t_x550em;
1532                 } else {
1533                         speed = IXGBE_LINK_SPEED_10GB_FULL |
1534                                 IXGBE_LINK_SPEED_1GB_FULL;
1535                         ret_val = ixgbe_setup_kr_speed_x550em(hw, speed);
1536                 }
1537
1538                 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1539                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1540                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1541                 break;
1542         default:
1543                 break;
1544         }
1545         return ret_val;
1546 }
1547
1548 /**
1549  *  ixgbe_reset_hw_X550em - Perform hardware reset
1550  *  @hw: pointer to hardware structure
1551  *
1552  *  Resets the hardware by resetting the transmit and receive units, masks
1553  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1554  *  reset.
1555  */
1556 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1557 {
1558         ixgbe_link_speed link_speed;
1559         s32 status;
1560         u32 ctrl = 0;
1561         u32 i;
1562         bool link_up = false;
1563
1564         DEBUGFUNC("ixgbe_reset_hw_X550em");
1565
1566         /* Call adapter stop to disable Tx/Rx and clear interrupts */
1567         status = hw->mac.ops.stop_adapter(hw);
1568         if (status != IXGBE_SUCCESS)
1569                 return status;
1570
1571         /* flush pending Tx transactions */
1572         ixgbe_clear_tx_pending(hw);
1573
1574         /* PHY ops must be identified and initialized prior to reset */
1575
1576         /* Identify PHY and related function pointers */
1577         status = hw->phy.ops.init(hw);
1578
1579         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1580                 return status;
1581
1582         /* start the external PHY */
1583         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1584                 status = ixgbe_init_ext_t_x550em(hw);
1585                 if (status)
1586                         return status;
1587         }
1588
1589         /* Setup SFP module if there is one present. */
1590         if (hw->phy.sfp_setup_needed) {
1591                 status = hw->mac.ops.setup_sfp(hw);
1592                 hw->phy.sfp_setup_needed = false;
1593         }
1594
1595         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1596                 return status;
1597
1598         /* Reset PHY */
1599         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1600                 hw->phy.ops.reset(hw);
1601
1602 mac_reset_top:
1603         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1604          * If link reset is used when link is up, it might reset the PHY when
1605          * mng is using it.  If link is down or the flag to force full link
1606          * reset is set, then perform link reset.
1607          */
1608         ctrl = IXGBE_CTRL_LNK_RST;
1609         if (!hw->force_full_reset) {
1610                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1611                 if (link_up)
1612                         ctrl = IXGBE_CTRL_RST;
1613         }
1614
1615         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1616         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1617         IXGBE_WRITE_FLUSH(hw);
1618
1619         /* Poll for reset bit to self-clear meaning reset is complete */
1620         for (i = 0; i < 10; i++) {
1621                 usec_delay(1);
1622                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1623                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1624                         break;
1625         }
1626
1627         if (ctrl & IXGBE_CTRL_RST_MASK) {
1628                 status = IXGBE_ERR_RESET_FAILED;
1629                 DEBUGOUT("Reset polling failed to complete.\n");
1630         }
1631
1632         msec_delay(50);
1633
1634         /* Double resets are required for recovery from certain error
1635          * conditions.  Between resets, it is necessary to stall to
1636          * allow time for any pending HW events to complete.
1637          */
1638         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1639                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1640                 goto mac_reset_top;
1641         }
1642
1643         /* Store the permanent mac address */
1644         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1645
1646         /* Store MAC address from RAR0, clear receive address registers, and
1647          * clear the multicast table.  Also reset num_rar_entries to 128,
1648          * since we modify this value when programming the SAN MAC address.
1649          */
1650         hw->mac.num_rar_entries = 128;
1651         hw->mac.ops.init_rx_addrs(hw);
1652
1653
1654         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1655                 ixgbe_setup_mux_ctl(hw);
1656
1657         return status;
1658 }
1659
1660 /**
1661  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1662  * @hw: pointer to hardware structure
1663  */
1664 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1665 {
1666         u32 status;
1667         u16 reg;
1668
1669         status = hw->phy.ops.read_reg(hw,
1670                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1671                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1672                                       &reg);
1673
1674         if (status != IXGBE_SUCCESS)
1675                 return status;
1676
1677         /* If PHY FW reset completed bit is set then this is the first
1678          * SW instance after a power on so the PHY FW must be un-stalled.
1679          */
1680         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1681                 status = hw->phy.ops.read_reg(hw,
1682                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1683                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1684                                         &reg);
1685
1686                 if (status != IXGBE_SUCCESS)
1687                         return status;
1688
1689                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1690
1691                 status = hw->phy.ops.write_reg(hw,
1692                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1693                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1694                                         reg);
1695
1696                 if (status != IXGBE_SUCCESS)
1697                         return status;
1698         }
1699
1700         return status;
1701 }
1702
1703 /**
1704  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1705  *  @hw: pointer to hardware structure
1706  *
1707  *  Configures the integrated KR PHY.
1708  **/
1709 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1710 {
1711         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
1712 }
1713
1714 /**
1715  *  ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1716  *  @hw: pointer to hardware structure
1717  *
1718  *  Configures the integrated KX4 PHY.
1719  **/
1720 s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1721 {
1722         s32 status;
1723         u32 reg_val;
1724
1725         status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1726                 IXGBE_SB_IOSF_TARGET_KX4_PCS, &reg_val);
1727         if (status)
1728                 return status;
1729
1730         reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1731                         IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1732
1733         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1734
1735         /* Advertise 10G support. */
1736         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1737                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1738
1739         /* Advertise 1G support. */
1740         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1741                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1742
1743         /* Restart auto-negotiation. */
1744         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1745         status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1746                 IXGBE_SB_IOSF_TARGET_KX4_PCS, reg_val);
1747
1748         return status;
1749 }
1750
1751 /**
1752  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1753  *  @hw: pointer to hardware structure
1754  *  @speed: the link speed to force
1755  *
1756  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1757  *  internal and external PHY at a specific speed, without autonegotiation.
1758  **/
1759 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1760 {
1761         s32 status;
1762         u32 reg_val;
1763
1764         /* Disable AN and force speed to 10G Serial. */
1765         status = ixgbe_read_iosf_sb_reg_x550(hw,
1766                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1767                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1768         if (status != IXGBE_SUCCESS)
1769                 return status;
1770
1771         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1772         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1773
1774         /* Select forced link speed for internal PHY. */
1775         switch (*speed) {
1776         case IXGBE_LINK_SPEED_10GB_FULL:
1777                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1778                 break;
1779         case IXGBE_LINK_SPEED_1GB_FULL:
1780                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1781                 break;
1782         default:
1783                 /* Other link speeds are not supported by internal KR PHY. */
1784                 return IXGBE_ERR_LINK_SETUP;
1785         }
1786
1787         status = ixgbe_write_iosf_sb_reg_x550(hw,
1788                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1789                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1790         if (status != IXGBE_SUCCESS)
1791                 return status;
1792
1793         /* Disable training protocol FSM. */
1794         status = ixgbe_read_iosf_sb_reg_x550(hw,
1795                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1796                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1797         if (status != IXGBE_SUCCESS)
1798                 return status;
1799         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1800         status = ixgbe_write_iosf_sb_reg_x550(hw,
1801                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1802                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1803         if (status != IXGBE_SUCCESS)
1804                 return status;
1805
1806         /* Disable Flex from training TXFFE. */
1807         status = ixgbe_read_iosf_sb_reg_x550(hw,
1808                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1809                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1810         if (status != IXGBE_SUCCESS)
1811                 return status;
1812         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1813         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1814         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1815         status = ixgbe_write_iosf_sb_reg_x550(hw,
1816                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1817                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1818         if (status != IXGBE_SUCCESS)
1819                 return status;
1820         status = ixgbe_read_iosf_sb_reg_x550(hw,
1821                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1822                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1823         if (status != IXGBE_SUCCESS)
1824                 return status;
1825         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1826         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1827         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1828         status = ixgbe_write_iosf_sb_reg_x550(hw,
1829                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1830                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1831         if (status != IXGBE_SUCCESS)
1832                 return status;
1833
1834         /* Enable override for coefficients. */
1835         status = ixgbe_read_iosf_sb_reg_x550(hw,
1836                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1837                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1838         if (status != IXGBE_SUCCESS)
1839                 return status;
1840         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1841         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1842         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1843         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1844         status = ixgbe_write_iosf_sb_reg_x550(hw,
1845                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1846                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1847         if (status != IXGBE_SUCCESS)
1848                 return status;
1849
1850         /* Toggle port SW reset by AN reset. */
1851         status = ixgbe_read_iosf_sb_reg_x550(hw,
1852                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1853                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1854         if (status != IXGBE_SUCCESS)
1855                 return status;
1856         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1857         status = ixgbe_write_iosf_sb_reg_x550(hw,
1858                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1859                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1860
1861         return status;
1862 }
1863
1864 /**
1865  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
1866  *  @hw: pointer to hardware structure
1867  *
1868  *  Configure the external PHY and the integrated KR PHY for SFP support.
1869  **/
1870 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1871                                     ixgbe_link_speed speed,
1872                                     bool autoneg_wait_to_complete)
1873 {
1874         s32 ret_val;
1875         u16 reg_slice, reg_val;
1876         bool setup_linear = false;
1877         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1878
1879         /* Check if SFP module is supported and linear */
1880         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1881
1882         /* If no SFP module present, then return success. Return success since
1883          * there is no reason to configure CS4227 and SFP not present error is
1884          * not excepted in the setup MAC link flow.
1885          */
1886         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1887                 return IXGBE_SUCCESS;
1888
1889         if (ret_val != IXGBE_SUCCESS)
1890                 return ret_val;
1891
1892         /* Configure CS4227 for LINE connection rate then type. */
1893         reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB + (hw->bus.lan_id << 12);
1894         reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000;
1895         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1896                                            reg_val);
1897
1898         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1899         if (setup_linear)
1900                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1901         else
1902                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1903         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1904                                            reg_val);
1905
1906         /* Configure CS4227 for HOST connection rate then type. */
1907         reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB + (hw->bus.lan_id << 12);
1908         reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000;
1909         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1910                                            reg_val);
1911
1912         reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (hw->bus.lan_id << 12);
1913         if (setup_linear)
1914                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1915         else
1916                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1917         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1918                                            reg_val);
1919
1920         /* If internal link mode is XFI, then setup XFI internal link. */
1921         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE))
1922                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
1923
1924         return ret_val;
1925 }
1926
1927 /**
1928  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1929  * @hw: point to hardware structure
1930  *
1931  * Configures the link between the integrated KR PHY and the external X557 PHY
1932  * The driver will call this function when it gets a link status change
1933  * interrupt from the X557 PHY. This function configures the link speed
1934  * between the PHYs to match the link speed of the BASE-T link.
1935  *
1936  * A return of a non-zero value indicates an error, and the base driver should
1937  * not report link up.
1938  */
1939 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
1940 {
1941         u32 status;
1942         u16 autoneg_status, speed;
1943         ixgbe_link_speed force_speed;
1944
1945         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1946                 return IXGBE_ERR_CONFIG;
1947
1948         /* read this twice back to back to indicate current status */
1949         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1950                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1951                                       &autoneg_status);
1952         if (status != IXGBE_SUCCESS)
1953                 return status;
1954
1955         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1956                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1957                                       &autoneg_status);
1958         if (status != IXGBE_SUCCESS)
1959                 return status;
1960
1961         /* If link is not up, then there is no setup necessary so return  */
1962         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1963                 return IXGBE_SUCCESS;
1964
1965         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1966                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1967                                       &speed);
1968
1969         /* clear everything but the speed and duplex bits */
1970         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1971
1972         switch (speed) {
1973         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1974                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1975                 break;
1976         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1977                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1978                 break;
1979         default:
1980                 /* Internal PHY does not support anything else */
1981                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1982         }
1983
1984         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1985 }
1986
1987 /**
1988  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1989  *  @hw: pointer to hardware structure
1990  *
1991  *  Configures the integrated KR PHY to use internal loopback mode.
1992  **/
1993 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1994 {
1995         s32 status;
1996         u32 reg_val;
1997
1998         /* Disable AN and force speed to 10G Serial. */
1999         status = ixgbe_read_iosf_sb_reg_x550(hw,
2000                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2001                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2002         if (status != IXGBE_SUCCESS)
2003                 return status;
2004         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2005         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2006         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2007         status = ixgbe_write_iosf_sb_reg_x550(hw,
2008                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2009                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2010         if (status != IXGBE_SUCCESS)
2011                 return status;
2012
2013         /* Set near-end loopback clocks. */
2014         status = ixgbe_read_iosf_sb_reg_x550(hw,
2015                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2016                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2017         if (status != IXGBE_SUCCESS)
2018                 return status;
2019         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2020         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2021         status = ixgbe_write_iosf_sb_reg_x550(hw,
2022                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2023                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2024         if (status != IXGBE_SUCCESS)
2025                 return status;
2026
2027         /* Set loopback enable. */
2028         status = ixgbe_read_iosf_sb_reg_x550(hw,
2029                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2030                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2031         if (status != IXGBE_SUCCESS)
2032                 return status;
2033         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2034         status = ixgbe_write_iosf_sb_reg_x550(hw,
2035                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2036                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2037         if (status != IXGBE_SUCCESS)
2038                 return status;
2039
2040         /* Training bypass. */
2041         status = ixgbe_read_iosf_sb_reg_x550(hw,
2042                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2043                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2044         if (status != IXGBE_SUCCESS)
2045                 return status;
2046         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2047         status = ixgbe_write_iosf_sb_reg_x550(hw,
2048                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2049                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2050
2051         return status;
2052 }
2053
2054 /**
2055  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2056  *  assuming that the semaphore is already obtained.
2057  *  @hw: pointer to hardware structure
2058  *  @offset: offset of  word in the EEPROM to read
2059  *  @data: word read from the EEPROM
2060  *
2061  *  Reads a 16 bit word from the EEPROM using the hostif.
2062  **/
2063 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2064                                    u16 *data)
2065 {
2066         s32 status;
2067         struct ixgbe_hic_read_shadow_ram buffer;
2068
2069         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2070         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2071         buffer.hdr.req.buf_lenh = 0;
2072         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2073         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2074
2075         /* convert offset from words to bytes */
2076         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2077         /* one word */
2078         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2079
2080         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2081                                               sizeof(buffer),
2082                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2083
2084         if (status)
2085                 return status;
2086
2087         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2088                                           FW_NVM_DATA_OFFSET);
2089
2090         return 0;
2091 }
2092
2093 /**
2094  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2095  *  @hw: pointer to hardware structure
2096  *  @offset: offset of  word in the EEPROM to read
2097  *  @data: word read from the EEPROM
2098  *
2099  *  Reads a 16 bit word from the EEPROM using the hostif.
2100  **/
2101 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2102                               u16 *data)
2103 {
2104         s32 status = IXGBE_SUCCESS;
2105
2106         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2107
2108         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2109             IXGBE_SUCCESS) {
2110                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2111                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2112         } else {
2113                 status = IXGBE_ERR_SWFW_SYNC;
2114         }
2115
2116         return status;
2117 }
2118
2119 /**
2120  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2121  *  @hw: pointer to hardware structure
2122  *  @offset: offset of  word in the EEPROM to read
2123  *  @words: number of words
2124  *  @data: word(s) read from the EEPROM
2125  *
2126  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
2127  **/
2128 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2129                                      u16 offset, u16 words, u16 *data)
2130 {
2131         struct ixgbe_hic_read_shadow_ram buffer;
2132         u32 current_word = 0;
2133         u16 words_to_read;
2134         s32 status;
2135         u32 i;
2136
2137         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2138
2139         /* Take semaphore for the entire operation. */
2140         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2141         if (status) {
2142                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2143                 return status;
2144         }
2145         while (words) {
2146                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2147                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2148                 else
2149                         words_to_read = words;
2150
2151                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2152                 buffer.hdr.req.buf_lenh = 0;
2153                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2154                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2155
2156                 /* convert offset from words to bytes */
2157                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2158                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2159
2160                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2161                                                       sizeof(buffer),
2162                                                       IXGBE_HI_COMMAND_TIMEOUT,
2163                                                       false);
2164
2165                 if (status) {
2166                         DEBUGOUT("Host interface command failed\n");
2167                         goto out;
2168                 }
2169
2170                 for (i = 0; i < words_to_read; i++) {
2171                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
2172                                   2 * i;
2173                         u32 value = IXGBE_READ_REG(hw, reg);
2174
2175                         data[current_word] = (u16)(value & 0xffff);
2176                         current_word++;
2177                         i++;
2178                         if (i < words_to_read) {
2179                                 value >>= 16;
2180                                 data[current_word] = (u16)(value & 0xffff);
2181                                 current_word++;
2182                         }
2183                 }
2184                 words -= words_to_read;
2185         }
2186
2187 out:
2188         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2189         return status;
2190 }
2191
2192 /**
2193  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2194  *  @hw: pointer to hardware structure
2195  *  @offset: offset of  word in the EEPROM to write
2196  *  @data: word write to the EEPROM
2197  *
2198  *  Write a 16 bit word to the EEPROM using the hostif.
2199  **/
2200 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2201                                     u16 data)
2202 {
2203         s32 status;
2204         struct ixgbe_hic_write_shadow_ram buffer;
2205
2206         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
2207
2208         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
2209         buffer.hdr.req.buf_lenh = 0;
2210         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
2211         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2212
2213          /* one word */
2214         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2215         buffer.data = data;
2216         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2217
2218         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2219                                               sizeof(buffer),
2220                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2221
2222         return status;
2223 }
2224
2225 /**
2226  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2227  *  @hw: pointer to hardware structure
2228  *  @offset: offset of  word in the EEPROM to write
2229  *  @data: word write to the EEPROM
2230  *
2231  *  Write a 16 bit word to the EEPROM using the hostif.
2232  **/
2233 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2234                                u16 data)
2235 {
2236         s32 status = IXGBE_SUCCESS;
2237
2238         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2239
2240         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2241             IXGBE_SUCCESS) {
2242                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2243                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2244         } else {
2245                 DEBUGOUT("write ee hostif failed to get semaphore");
2246                 status = IXGBE_ERR_SWFW_SYNC;
2247         }
2248
2249         return status;
2250 }
2251
2252 /**
2253  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2254  *  @hw: pointer to hardware structure
2255  *  @offset: offset of  word in the EEPROM to write
2256  *  @words: number of words
2257  *  @data: word(s) write to the EEPROM
2258  *
2259  *  Write a 16 bit word(s) to the EEPROM using the hostif.
2260  **/
2261 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2262                                       u16 offset, u16 words, u16 *data)
2263 {
2264         s32 status = IXGBE_SUCCESS;
2265         u32 i = 0;
2266
2267         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2268
2269         /* Take semaphore for the entire operation. */
2270         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2271         if (status != IXGBE_SUCCESS) {
2272                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2273                 goto out;
2274         }
2275
2276         for (i = 0; i < words; i++) {
2277                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2278                                                          data[i]);
2279
2280                 if (status != IXGBE_SUCCESS) {
2281                         DEBUGOUT("Eeprom buffered write failed\n");
2282                         break;
2283                 }
2284         }
2285
2286         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2287 out:
2288
2289         return status;
2290 }
2291
2292 /**
2293  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2294  * @hw: pointer to hardware structure
2295  * @ptr: pointer offset in eeprom
2296  * @size: size of section pointed by ptr, if 0 first word will be used as size
2297  * @csum: address of checksum to update
2298  *
2299  * Returns error status for any failure
2300  */
2301 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2302                                    u16 size, u16 *csum, u16 *buffer,
2303                                    u32 buffer_size)
2304 {
2305         u16 buf[256];
2306         s32 status;
2307         u16 length, bufsz, i, start;
2308         u16 *local_buffer;
2309
2310         bufsz = sizeof(buf) / sizeof(buf[0]);
2311
2312         /* Read a chunk at the pointer location */
2313         if (!buffer) {
2314                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2315                 if (status) {
2316                         DEBUGOUT("Failed to read EEPROM image\n");
2317                         return status;
2318                 }
2319                 local_buffer = buf;
2320         } else {
2321                 if (buffer_size < ptr)
2322                         return  IXGBE_ERR_PARAM;
2323                 local_buffer = &buffer[ptr];
2324         }
2325
2326         if (size) {
2327                 start = 0;
2328                 length = size;
2329         } else {
2330                 start = 1;
2331                 length = local_buffer[0];
2332
2333                 /* Skip pointer section if length is invalid. */
2334                 if (length == 0xFFFF || length == 0 ||
2335                     (ptr + length) >= hw->eeprom.word_size)
2336                         return IXGBE_SUCCESS;
2337         }
2338
2339         if (buffer && ((u32)start + (u32)length > buffer_size))
2340                 return IXGBE_ERR_PARAM;
2341
2342         for (i = start; length; i++, length--) {
2343                 if (i == bufsz && !buffer) {
2344                         ptr += bufsz;
2345                         i = 0;
2346                         if (length < bufsz)
2347                                 bufsz = length;
2348
2349                         /* Read a chunk at the pointer location */
2350                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2351                                                                   bufsz, buf);
2352                         if (status) {
2353                                 DEBUGOUT("Failed to read EEPROM image\n");
2354                                 return status;
2355                         }
2356                 }
2357                 *csum += local_buffer[i];
2358         }
2359         return IXGBE_SUCCESS;
2360 }
2361
2362 /**
2363  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2364  *  @hw: pointer to hardware structure
2365  *  @buffer: pointer to buffer containing calculated checksum
2366  *  @buffer_size: size of buffer
2367  *
2368  *  Returns a negative error code on error, or the 16-bit checksum
2369  **/
2370 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2371 {
2372         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2373         u16 *local_buffer;
2374         s32 status;
2375         u16 checksum = 0;
2376         u16 pointer, i, size;
2377
2378         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2379
2380         hw->eeprom.ops.init_params(hw);
2381
2382         if (!buffer) {
2383                 /* Read pointer area */
2384                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2385                                                      IXGBE_EEPROM_LAST_WORD + 1,
2386                                                      eeprom_ptrs);
2387                 if (status) {
2388                         DEBUGOUT("Failed to read EEPROM image\n");
2389                         return status;
2390                 }
2391                 local_buffer = eeprom_ptrs;
2392         } else {
2393                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2394                         return IXGBE_ERR_PARAM;
2395                 local_buffer = buffer;
2396         }
2397
2398         /*
2399          * For X550 hardware include 0x0-0x41 in the checksum, skip the
2400          * checksum word itself
2401          */
2402         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2403                 if (i != IXGBE_EEPROM_CHECKSUM)
2404                         checksum += local_buffer[i];
2405
2406         /*
2407          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
2408          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2409          */
2410         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2411                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2412                         continue;
2413
2414                 pointer = local_buffer[i];
2415
2416                 /* Skip pointer section if the pointer is invalid. */
2417                 if (pointer == 0xFFFF || pointer == 0 ||
2418                     pointer >= hw->eeprom.word_size)
2419                         continue;
2420
2421                 switch (i) {
2422                 case IXGBE_PCIE_GENERAL_PTR:
2423                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2424                         break;
2425                 case IXGBE_PCIE_CONFIG0_PTR:
2426                 case IXGBE_PCIE_CONFIG1_PTR:
2427                         size = IXGBE_PCIE_CONFIG_SIZE;
2428                         break;
2429                 default:
2430                         size = 0;
2431                         break;
2432                 }
2433
2434                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2435                                                 buffer, buffer_size);
2436                 if (status)
2437                         return status;
2438         }
2439
2440         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2441
2442         return (s32)checksum;
2443 }
2444
2445 /**
2446  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2447  *  @hw: pointer to hardware structure
2448  *
2449  *  Returns a negative error code on error, or the 16-bit checksum
2450  **/
2451 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2452 {
2453         return ixgbe_calc_checksum_X550(hw, NULL, 0);
2454 }
2455
2456 /**
2457  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2458  *  @hw: pointer to hardware structure
2459  *  @checksum_val: calculated checksum
2460  *
2461  *  Performs checksum calculation and validates the EEPROM checksum.  If the
2462  *  caller does not need checksum_val, the value can be NULL.
2463  **/
2464 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2465 {
2466         s32 status;
2467         u16 checksum;
2468         u16 read_checksum = 0;
2469
2470         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2471
2472         /* Read the first word from the EEPROM. If this times out or fails, do
2473          * not continue or we could be in for a very long wait while every
2474          * EEPROM read fails
2475          */
2476         status = hw->eeprom.ops.read(hw, 0, &checksum);
2477         if (status) {
2478                 DEBUGOUT("EEPROM read failed\n");
2479                 return status;
2480         }
2481
2482         status = hw->eeprom.ops.calc_checksum(hw);
2483         if (status < 0)
2484                 return status;
2485
2486         checksum = (u16)(status & 0xffff);
2487
2488         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2489                                            &read_checksum);
2490         if (status)
2491                 return status;
2492
2493         /* Verify read checksum from EEPROM is the same as
2494          * calculated checksum
2495          */
2496         if (read_checksum != checksum) {
2497                 status = IXGBE_ERR_EEPROM_CHECKSUM;
2498                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2499                              "Invalid EEPROM checksum");
2500         }
2501
2502         /* If the user cares, return the calculated checksum */
2503         if (checksum_val)
2504                 *checksum_val = checksum;
2505
2506         return status;
2507 }
2508
2509 /**
2510  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2511  * @hw: pointer to hardware structure
2512  *
2513  * After writing EEPROM to shadow RAM using EEWR register, software calculates
2514  * checksum and updates the EEPROM and instructs the hardware to update
2515  * the flash.
2516  **/
2517 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2518 {
2519         s32 status;
2520         u16 checksum = 0;
2521
2522         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2523
2524         /* Read the first word from the EEPROM. If this times out or fails, do
2525          * not continue or we could be in for a very long wait while every
2526          * EEPROM read fails
2527          */
2528         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2529         if (status) {
2530                 DEBUGOUT("EEPROM read failed\n");
2531                 return status;
2532         }
2533
2534         status = ixgbe_calc_eeprom_checksum_X550(hw);
2535         if (status < 0)
2536                 return status;
2537
2538         checksum = (u16)(status & 0xffff);
2539
2540         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2541                                             checksum);
2542         if (status)
2543                 return status;
2544
2545         status = ixgbe_update_flash_X550(hw);
2546
2547         return status;
2548 }
2549
2550 /**
2551  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2552  *  @hw: pointer to hardware structure
2553  *
2554  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2555  **/
2556 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2557 {
2558         s32 status = IXGBE_SUCCESS;
2559         union ixgbe_hic_hdr2 buffer;
2560
2561         DEBUGFUNC("ixgbe_update_flash_X550");
2562
2563         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2564         buffer.req.buf_lenh = 0;
2565         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2566         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2567
2568         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2569                                               sizeof(buffer),
2570                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2571
2572         return status;
2573 }
2574
2575 /**
2576  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2577  *  @hw: pointer to hardware structure
2578  *
2579  *  Determines physical layer capabilities of the current configuration.
2580  **/
2581 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2582 {
2583         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2584         u16 ext_ability = 0;
2585
2586         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2587
2588         hw->phy.ops.identify(hw);
2589
2590         switch (hw->phy.type) {
2591         case ixgbe_phy_x550em_kr:
2592                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2593                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2594                 break;
2595         case ixgbe_phy_x550em_kx4:
2596                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2597                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2598                 break;
2599         case ixgbe_phy_x550em_ext_t:
2600                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2601                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2602                                      &ext_ability);
2603                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2604                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2605                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2606                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2607                 break;
2608         default:
2609                 break;
2610         }
2611
2612         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2613                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2614
2615         return physical_layer;
2616 }
2617
2618 /**
2619  * ixgbe_get_bus_info_x550em - Set PCI bus info
2620  * @hw: pointer to hardware structure
2621  *
2622  * Sets bus link width and speed to unknown because X550em is
2623  * not a PCI device.
2624  **/
2625 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2626 {
2627
2628         DEBUGFUNC("ixgbe_get_bus_info_x550em");
2629
2630         hw->bus.width = ixgbe_bus_width_unknown;
2631         hw->bus.speed = ixgbe_bus_speed_unknown;
2632
2633         hw->mac.ops.set_lan_id(hw);
2634
2635         return IXGBE_SUCCESS;
2636 }
2637
2638 /**
2639  * ixgbe_disable_rx_x550 - Disable RX unit
2640  *
2641  * Enables the Rx DMA unit for x550
2642  **/
2643 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2644 {
2645         u32 rxctrl, pfdtxgswc;
2646         s32 status;
2647         struct ixgbe_hic_disable_rxen fw_cmd;
2648
2649         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2650
2651         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2652         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2653                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2654                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2655                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2656                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2657                         hw->mac.set_lben = true;
2658                 } else {
2659                         hw->mac.set_lben = false;
2660                 }
2661
2662                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2663                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2664                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2665                 fw_cmd.port_number = (u8)hw->bus.lan_id;
2666
2667                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2668                                         sizeof(struct ixgbe_hic_disable_rxen),
2669                                         IXGBE_HI_COMMAND_TIMEOUT, true);
2670
2671                 /* If we fail - disable RX using register write */
2672                 if (status) {
2673                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2674                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2675                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2676                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2677                         }
2678                 }
2679         }
2680 }
2681
2682 /**
2683  * ixgbe_enter_lplu_x550em - Transition to low power states
2684  *  @hw: pointer to hardware structure
2685  *
2686  * Configures Low Power Link Up on transition to low power states
2687  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2688  * X557 PHY immediately prior to entering LPLU.
2689  **/
2690 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2691 {
2692         u16 autoneg_status, an_10g_cntl_reg, autoneg_reg, speed;
2693         s32 status;
2694         ixgbe_link_speed lcd_speed;
2695         u32 save_autoneg;
2696
2697         /* If blocked by MNG FW, then don't restart AN */
2698         if (ixgbe_check_reset_blocked(hw))
2699                 return IXGBE_SUCCESS;
2700
2701         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2702                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2703                                       &autoneg_status);
2704
2705         if (status != IXGBE_SUCCESS)
2706                 return status;
2707
2708         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2709
2710         if (status != IXGBE_SUCCESS)
2711                 return status;
2712
2713         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2714          * disabled, then force link down by entering low power mode.
2715          */
2716         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS) ||
2717             !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2718             !(hw->wol_enabled || ixgbe_mng_present(hw)))
2719                 return ixgbe_set_copper_phy_power(hw, FALSE);
2720
2721         /* Determine LCD */
2722         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2723
2724         if (status != IXGBE_SUCCESS)
2725                 return status;
2726
2727         /* If no valid LCD link speed, then force link down and exit. */
2728         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2729                 return ixgbe_set_copper_phy_power(hw, FALSE);
2730
2731         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2732                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2733                                       &speed);
2734
2735         if (status != IXGBE_SUCCESS)
2736                 return status;
2737
2738         /* clear everything but the speed bits */
2739         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2740
2741         /* If current speed is already LCD, then exit. */
2742         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2743              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2744             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2745              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2746                 return status;
2747
2748         /* Clear AN completed indication */
2749         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2750                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2751                                       &autoneg_status);
2752
2753         if (status != IXGBE_SUCCESS)
2754                 return status;
2755
2756         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2757                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2758                              &an_10g_cntl_reg);
2759
2760         if (status != IXGBE_SUCCESS)
2761                 return status;
2762
2763         status = hw->phy.ops.read_reg(hw,
2764                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2765                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2766                              &autoneg_reg);
2767
2768         if (status != IXGBE_SUCCESS)
2769                 return status;
2770
2771         save_autoneg = hw->phy.autoneg_advertised;
2772
2773         /* Setup link at least common link speed */
2774         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
2775
2776         /* restore autoneg from before setting lplu speed */
2777         hw->phy.autoneg_advertised = save_autoneg;
2778
2779         return status;
2780 }
2781
2782 /**
2783  * ixgbe_get_lcd_x550em - Determine lowest common denominator
2784  *  @hw: pointer to hardware structure
2785  *  @lcd_speed: pointer to lowest common link speed
2786  *
2787  * Determine lowest common link speed with link partner.
2788  **/
2789 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2790 {
2791         u16 an_lp_status;
2792         s32 status;
2793         u16 word = hw->eeprom.ctrl_word_3;
2794
2795         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2796
2797         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2798                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2799                                       &an_lp_status);
2800
2801         if (status != IXGBE_SUCCESS)
2802                 return status;
2803
2804         /* If link partner advertised 1G, return 1G */
2805         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2806                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2807                 return status;
2808         }
2809
2810         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2811         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2812             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2813                 return status;
2814
2815         /* Link partner not capable of lower speeds, return 10G */
2816         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2817         return status;
2818 }
2819
2820 /**
2821  *  ixgbe_setup_fc_X550em - Set up flow control
2822  *  @hw: pointer to hardware structure
2823  *
2824  *  Called at init time to set up flow control.
2825  **/
2826 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
2827 {
2828         s32 ret_val = IXGBE_SUCCESS;
2829         u32 pause, asm_dir, reg_val;
2830
2831         DEBUGFUNC("ixgbe_setup_fc_X550em");
2832
2833         /* Validate the requested mode */
2834         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2835                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2836                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2837                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2838                 goto out;
2839         }
2840
2841         /* 10gig parts do not have a word in the EEPROM to determine the
2842          * default flow control setting, so we explicitly set it to full.
2843          */
2844         if (hw->fc.requested_mode == ixgbe_fc_default)
2845                 hw->fc.requested_mode = ixgbe_fc_full;
2846
2847         /* Determine PAUSE and ASM_DIR bits. */
2848         switch (hw->fc.requested_mode) {
2849         case ixgbe_fc_none:
2850                 pause = 0;
2851                 asm_dir = 0;
2852                 break;
2853         case ixgbe_fc_tx_pause:
2854                 pause = 0;
2855                 asm_dir = 1;
2856                 break;
2857         case ixgbe_fc_rx_pause:
2858                 /* Rx Flow control is enabled and Tx Flow control is
2859                  * disabled by software override. Since there really
2860                  * isn't a way to advertise that we are capable of RX
2861                  * Pause ONLY, we will advertise that we support both
2862                  * symmetric and asymmetric Rx PAUSE, as such we fall
2863                  * through to the fc_full statement.  Later, we will
2864                  * disable the adapter's ability to send PAUSE frames.
2865                  */
2866         case ixgbe_fc_full:
2867                 pause = 1;
2868                 asm_dir = 1;
2869                 break;
2870         default:
2871                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2872                         "Flow control param set incorrectly\n");
2873                 ret_val = IXGBE_ERR_CONFIG;
2874                 goto out;
2875         }
2876
2877         if (hw->phy.media_type == ixgbe_media_type_backplane) {
2878                 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
2879                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2880                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2881                 if (ret_val != IXGBE_SUCCESS)
2882                         goto out;
2883                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2884                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2885                 if (pause)
2886                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2887                 if (asm_dir)
2888                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2889                 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
2890                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2891                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2892
2893                 /* Not all devices fully support AN. */
2894                 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR)
2895                         hw->fc.disable_fc_autoneg = true;
2896         }
2897
2898 out:
2899         return ret_val;
2900 }
2901
2902 /**
2903  * ixgbe_set_mux - Set mux for port 1 access with CS4227
2904  * @hw: pointer to hardware structure
2905  * @state: set mux if 1, clear if 0
2906  */
2907 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2908 {
2909         u32 esdp;
2910
2911         if (!hw->bus.lan_id)
2912                 return;
2913         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2914         if (state)
2915                 esdp |= IXGBE_ESDP_SDP1;
2916         else
2917                 esdp &= ~IXGBE_ESDP_SDP1;
2918         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2919         IXGBE_WRITE_FLUSH(hw);
2920 }
2921
2922 /**
2923  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2924  *  @hw: pointer to hardware structure
2925  *  @mask: Mask to specify which semaphore to acquire
2926  *
2927  *  Acquires the SWFW semaphore and sets the I2C MUX
2928  **/
2929 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2930 {
2931         s32 status;
2932
2933         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
2934
2935         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2936         if (status)
2937                 return status;
2938
2939         if (mask & IXGBE_GSSR_I2C_MASK)
2940                 ixgbe_set_mux(hw, 1);
2941
2942         return IXGBE_SUCCESS;
2943 }
2944
2945 /**
2946  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2947  *  @hw: pointer to hardware structure
2948  *  @mask: Mask to specify which semaphore to release
2949  *
2950  *  Releases the SWFW semaphore and sets the I2C MUX
2951  **/
2952 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2953 {
2954         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
2955
2956         if (mask & IXGBE_GSSR_I2C_MASK)
2957                 ixgbe_set_mux(hw, 0);
2958
2959         ixgbe_release_swfw_sync_X540(hw, mask);
2960 }
2961
2962 /**
2963  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2964  * @hw: pointer to hardware structure
2965  *
2966  * Handle external Base T PHY interrupt. If high temperature
2967  * failure alarm then return error, else if link status change
2968  * then setup internal/external PHY link
2969  *
2970  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2971  * failure alarm, else return PHY access status.
2972  */
2973 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2974 {
2975         bool lsc;
2976         u32 status;
2977
2978         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2979
2980         if (status != IXGBE_SUCCESS)
2981                 return status;
2982
2983         if (lsc)
2984                 return ixgbe_setup_internal_phy(hw);
2985
2986         return IXGBE_SUCCESS;
2987 }
2988
2989 /**
2990  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
2991  * @hw: pointer to hardware structure
2992  * @speed: new link speed
2993  * @autoneg_wait_to_complete: true when waiting for completion is needed
2994  *
2995  * Setup internal/external PHY link speed based on link speed, then set
2996  * external PHY auto advertised link speed.
2997  *
2998  * Returns error status for any failure
2999  **/
3000 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
3001                                   ixgbe_link_speed speed,
3002                                   bool autoneg_wait_to_complete)
3003 {
3004         s32 status;
3005         ixgbe_link_speed force_speed;
3006
3007         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
3008
3009         /* Setup internal/external PHY link speed to iXFI (10G), unless
3010          * only 1G is auto advertised then setup KX link.
3011          */
3012         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
3013                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3014         else
3015                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3016
3017         /* If internal link mode is XFI, then setup XFI internal link. */
3018         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3019                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
3020
3021                 if (status != IXGBE_SUCCESS)
3022                         return status;
3023         }
3024
3025         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
3026 }
3027
3028 /**
3029  * ixgbe_check_link_t_X550em - Determine link and speed status
3030  * @hw: pointer to hardware structure
3031  * @speed: pointer to link speed
3032  * @link_up: true when link is up
3033  * @link_up_wait_to_complete: bool used to wait for link up or not
3034  *
3035  * Check that both the MAC and X557 external PHY have link.
3036  **/
3037 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3038                               bool *link_up, bool link_up_wait_to_complete)
3039 {
3040         u32 status;
3041         u16 autoneg_status;
3042
3043         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3044                 return IXGBE_ERR_CONFIG;
3045
3046         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
3047                                               link_up_wait_to_complete);
3048
3049         /* If check link fails or MAC link is not up, then return */
3050         if (status != IXGBE_SUCCESS || !(*link_up))
3051                 return status;
3052
3053         /* MAC link is up, so check external PHY link.
3054          * Read this twice back to back to indicate current status.
3055          */
3056         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3057                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3058                                       &autoneg_status);
3059
3060         if (status != IXGBE_SUCCESS)
3061                 return status;
3062
3063         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3064                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3065                                       &autoneg_status);
3066
3067         if (status != IXGBE_SUCCESS)
3068                 return status;
3069
3070         /* If external PHY link is not up, then indicate link not up */
3071         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
3072                 *link_up = false;
3073
3074         return IXGBE_SUCCESS;
3075 }
3076
3077 /**
3078  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
3079  *  @hw: pointer to hardware structure
3080  **/
3081 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
3082 {
3083         s32 status;
3084
3085         status = ixgbe_reset_phy_generic(hw);
3086
3087         if (status != IXGBE_SUCCESS)
3088                 return status;
3089
3090         /* Configure Link Status Alarm and Temperature Threshold interrupts */
3091         return ixgbe_enable_lasi_ext_t_x550em(hw);
3092 }