drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  44 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw);
  45
  46 /**
  47  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  48  *  @hw: pointer to hardware structure
  49  *
  50  *  Initialize the function pointers and assign the MAC type for X550.
  51  *  Does not touch the hardware.
  52  **/
  53 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  54 {
  55         struct ixgbe_mac_info *mac = &hw->mac;
  56         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  57         s32 ret_val;
  58
  59         DEBUGFUNC("ixgbe_init_ops_X550");
  60
  61         ret_val = ixgbe_init_ops_X540(hw);
  62         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  63         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  64         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  65         mac->ops.setup_eee = NULL;
  66         mac->ops.set_source_address_pruning =
  67                         ixgbe_set_source_address_pruning_X550;
  68         mac->ops.set_ethertype_anti_spoofing =
  69                         ixgbe_set_ethertype_anti_spoofing_X550;
  70
  71         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  72         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  73         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  74         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  75         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  76         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  77         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  78         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  79         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  80
  81         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  82         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  83         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  84         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  85         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  86         /* Manageability interface */
  87         mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_x550;
  88         switch (hw->device_id) {
  89         case IXGBE_DEV_ID_X550EM_X_1G_T:
  90                 hw->mac.ops.led_on = NULL;
  91                 hw->mac.ops.led_off = NULL;
  92                 break;
  93         case IXGBE_DEV_ID_X550EM_X_10G_T:
  94         case IXGBE_DEV_ID_X550EM_A_10G_T:
  95                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  96                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  97                 break;
  98         default:
  99                 break;
 100         }
 101         return ret_val;
 102 }
 103
 104 /**
 105  * ixgbe_read_cs4227 - Read CS4227 register
 106  * @hw: pointer to hardware structure
 107  * @reg: register number to write
 108  * @value: pointer to receive value read
 109  *
 110  * Returns status code
 111  **/
 112 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
 113 {
 114         return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
 115 }
 116
 117 /**
 118  * ixgbe_write_cs4227 - Write CS4227 register
 119  * @hw: pointer to hardware structure
 120  * @reg: register number to write
 121  * @value: value to write to register
 122  *
 123  * Returns status code
 124  **/
 125 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 126 {
 127         return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
 128 }
 129
 130 /**
 131  * ixgbe_read_pe - Read register from port expander
 132  * @hw: pointer to hardware structure
 133  * @reg: register number to read
 134  * @value: pointer to receive read value
 135  *
 136  * Returns status code
 137  **/
 138 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 139 {
 140         s32 status;
 141
 142         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 143         if (status != IXGBE_SUCCESS)
 144                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 145                               "port expander access failed with %d\n", status);
 146         return status;
 147 }
 148
 149 /**
 150  * ixgbe_write_pe - Write register to port expander
 151  * @hw: pointer to hardware structure
 152  * @reg: register number to write
 153  * @value: value to write
 154  *
 155  * Returns status code
 156  **/
 157 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 158 {
 159         s32 status;
 160
 161         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 162         if (status != IXGBE_SUCCESS)
 163                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 164                               "port expander access failed with %d\n", status);
 165         return status;
 166 }
 167
 168 /**
 169  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 170  * @hw: pointer to hardware structure
 171  *
 172  * This function assumes that the caller has acquired the proper semaphore.
 173  * Returns error code
 174  **/
 175 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 176 {
 177         s32 status;
 178         u32 retry;
 179         u16 value;
 180         u8 reg;
 181
 182         /* Trigger hard reset. */
 183         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 184         if (status != IXGBE_SUCCESS)
 185                 return status;
 186         reg |= IXGBE_PE_BIT1;
 187         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 188         if (status != IXGBE_SUCCESS)
 189                 return status;
 190
 191         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 192         if (status != IXGBE_SUCCESS)
 193                 return status;
 194         reg &= ~IXGBE_PE_BIT1;
 195         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 196         if (status != IXGBE_SUCCESS)
 197                 return status;
 198
 199         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 200         if (status != IXGBE_SUCCESS)
 201                 return status;
 202         reg &= ~IXGBE_PE_BIT1;
 203         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 204         if (status != IXGBE_SUCCESS)
 205                 return status;
 206
 207         usec_delay(IXGBE_CS4227_RESET_HOLD);
 208
 209         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 210         if (status != IXGBE_SUCCESS)
 211                 return status;
 212         reg |= IXGBE_PE_BIT1;
 213         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 214         if (status != IXGBE_SUCCESS)
 215                 return status;
 216
 217         /* Wait for the reset to complete. */
 218         msec_delay(IXGBE_CS4227_RESET_DELAY);
 219         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 220                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 221                                            &value);
 222                 if (status == IXGBE_SUCCESS &&
 223                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 224                         break;
 225                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 226         }
 227         if (retry == IXGBE_CS4227_RETRIES) {
 228                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 229                         "CS4227 reset did not complete.");
 230                 return IXGBE_ERR_PHY;
 231         }
 232
 233         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 234         if (status != IXGBE_SUCCESS ||
 235             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 236                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 237                         "CS4227 EEPROM did not load successfully.");
 238                 return IXGBE_ERR_PHY;
 239         }
 240
 241         return IXGBE_SUCCESS;
 242 }
 243
 244 /**
 245  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 246  * @hw: pointer to hardware structure
 247  **/
 248 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 249 {
 250         s32 status = IXGBE_SUCCESS;
 251         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 252         u16 value = 0;
 253         u8 retry;
 254
 255         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 256                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 257                 if (status != IXGBE_SUCCESS) {
 258                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 259                                 "semaphore failed with %d", status);
 260                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 261                         continue;
 262                 }
 263
 264                 /* Get status of reset flow. */
 265                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 266
 267                 if (status == IXGBE_SUCCESS &&
 268                     value == IXGBE_CS4227_RESET_COMPLETE)
 269                         goto out;
 270
 271                 if (status != IXGBE_SUCCESS ||
 272                     value != IXGBE_CS4227_RESET_PENDING)
 273                         break;
 274
 275                 /* Reset is pending. Wait and check again. */
 276                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 277                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 278         }
 279
 280         /* If still pending, assume other instance failed. */
 281         if (retry == IXGBE_CS4227_RETRIES) {
 282                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 283                 if (status != IXGBE_SUCCESS) {
 284                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 285                                       "semaphore failed with %d", status);
 286                         return;
 287                 }
 288         }
 289
 290         /* Reset the CS4227. */
 291         status = ixgbe_reset_cs4227(hw);
 292         if (status != IXGBE_SUCCESS) {
 293                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 294                         "CS4227 reset failed: %d", status);
 295                 goto out;
 296         }
 297
 298         /* Reset takes so long, temporarily release semaphore in case the
 299          * other driver instance is waiting for the reset indication.
 300          */
 301         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 302                            IXGBE_CS4227_RESET_PENDING);
 303         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 304         msec_delay(10);
 305         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 306         if (status != IXGBE_SUCCESS) {
 307                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 308                         "semaphore failed with %d", status);
 309                 return;
 310         }
 311
 312         /* Record completion for next time. */
 313         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 314                 IXGBE_CS4227_RESET_COMPLETE);
 315
 316 out:
 317         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 318         msec_delay(hw->eeprom.semaphore_delay);
 319 }
 320
 321 /**
 322  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 323  * @hw: pointer to hardware structure
 324  **/
 325 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 326 {
 327         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 328
 329         if (hw->bus.lan_id) {
 330                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 331                 esdp |= IXGBE_ESDP_SDP1_DIR;
 332         }
 333         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 334         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 335         IXGBE_WRITE_FLUSH(hw);
 336 }
 337
 338 /**
 339  * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
 340  * @hw: pointer to hardware structure
 341  * @reg_addr: 32 bit address of PHY register to read
 342  * @dev_type: always unused
 343  * @phy_data: Pointer to read data from PHY register
 344  */
 345 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 346                                      u32 dev_type, u16 *phy_data)
 347 {
 348         u32 i, data, command;
 349         UNREFERENCED_1PARAMETER(dev_type);
 350
 351         /* Setup and write the read command */
 352         command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 353                   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 354                   IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
 355                   IXGBE_MSCA_MDI_COMMAND;
 356
 357         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 358
 359         /* Check every 10 usec to see if the access completed.
 360          * The MDI Command bit will clear when the operation is
 361          * complete
 362          */
 363         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 364                 usec_delay(10);
 365
 366                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 367                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 368                         break;
 369         }
 370
 371         if (command & IXGBE_MSCA_MDI_COMMAND) {
 372                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 373                               "PHY read command did not complete.\n");
 374                 return IXGBE_ERR_PHY;
 375         }
 376
 377         /* Read operation is complete.  Get the data from MSRWD */
 378         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 379         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 380         *phy_data = (u16)data;
 381
 382         return IXGBE_SUCCESS;
 383 }
 384
 385 /**
 386  * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
 387  * @hw: pointer to hardware structure
 388  * @reg_addr: 32 bit PHY register to write
 389  * @dev_type: always unused
 390  * @phy_data: Data to write to the PHY register
 391  */
 392 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 393                                       u32 dev_type, u16 phy_data)
 394 {
 395         u32 i, command;
 396         UNREFERENCED_1PARAMETER(dev_type);
 397
 398         /* Put the data in the MDI single read and write data register*/
 399         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 400
 401         /* Setup and write the write command */
 402         command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 403                   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 404                   IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
 405                   IXGBE_MSCA_MDI_COMMAND;
 406
 407         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 408
 409         /* Check every 10 usec to see if the access completed.
 410          * The MDI Command bit will clear when the operation is
 411          * complete
 412          */
 413         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 414                 usec_delay(10);
 415
 416                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 417                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 418                         break;
 419         }
 420
 421         if (command & IXGBE_MSCA_MDI_COMMAND) {
 422                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 423                               "PHY write cmd didn't complete\n");
 424                 return IXGBE_ERR_PHY;
 425         }
 426
 427         return IXGBE_SUCCESS;
 428 }
 429
 430 /**
 431  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 432  * @hw: pointer to hardware structure
 433  *
 434  * Returns error code
 435  */
 436 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 437 {
 438         hw->mac.ops.set_lan_id(hw);
 439
 440         ixgbe_read_mng_if_sel_x550em(hw);
 441
 442         switch (hw->device_id) {
 443         case IXGBE_DEV_ID_X550EM_A_SFP:
 444                 return ixgbe_identify_module_generic(hw);
 445         case IXGBE_DEV_ID_X550EM_X_SFP:
 446                 /* set up for CS4227 usage */
 447                 ixgbe_setup_mux_ctl(hw);
 448                 ixgbe_check_cs4227(hw);
 449                 /* Fallthrough */
 450
 451         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 452                 return ixgbe_identify_module_generic(hw);
 453                 break;
 454         case IXGBE_DEV_ID_X550EM_X_KX4:
 455                 hw->phy.type = ixgbe_phy_x550em_kx4;
 456                 break;
 457         case IXGBE_DEV_ID_X550EM_X_XFI:
 458                 hw->phy.type = ixgbe_phy_x550em_xfi;
 459                 break;
 460         case IXGBE_DEV_ID_X550EM_X_KR:
 461         case IXGBE_DEV_ID_X550EM_A_KR:
 462         case IXGBE_DEV_ID_X550EM_A_KR_L:
 463                 hw->phy.type = ixgbe_phy_x550em_kr;
 464                 break;
 465         case IXGBE_DEV_ID_X550EM_A_10G_T:
 466         case IXGBE_DEV_ID_X550EM_X_10G_T:
 467                 return ixgbe_identify_phy_generic(hw);
 468         case IXGBE_DEV_ID_X550EM_X_1G_T:
 469                 hw->phy.type = ixgbe_phy_ext_1g_t;
 470                 hw->phy.ops.read_reg = NULL;
 471                 hw->phy.ops.write_reg = NULL;
 472                 break;
 473         case IXGBE_DEV_ID_X550EM_A_1G_T:
 474         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 475                 hw->phy.type = ixgbe_phy_fw;
 476                 hw->phy.ops.read_reg = NULL;
 477                 hw->phy.ops.write_reg = NULL;
 478                 if (hw->bus.lan_id)
 479                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 480                 else
 481                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 482                 break;
 483         default:
 484                 break;
 485         }
 486         return IXGBE_SUCCESS;
 487 }
 488
 489 /**
 490  * ixgbe_fw_phy_activity - Perform an activity on a PHY
 491  * @hw: pointer to hardware structure
 492  * @activity: activity to perform
 493  * @data: Pointer to 4 32-bit words of data
 494  */
 495 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,
 496                           u32 (*data)[FW_PHY_ACT_DATA_COUNT])
 497 {
 498         union {
 499                 struct ixgbe_hic_phy_activity_req cmd;
 500                 struct ixgbe_hic_phy_activity_resp rsp;
 501         } hic;
 502         u16 retries = FW_PHY_ACT_RETRIES;
 503         s32 rc;
 504         u16 i;
 505
 506         do {
 507                 memset(&hic, 0, sizeof(hic));
 508                 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD;
 509                 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN;
 510                 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 511                 hic.cmd.port_number = hw->bus.lan_id;
 512                 hic.cmd.activity_id = IXGBE_CPU_TO_LE16(activity);
 513                 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
 514                         hic.cmd.data[i] = IXGBE_CPU_TO_BE32((*data)[i]);
 515
 516                 rc = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
 517                                                   sizeof(hic.cmd),
 518                                                   IXGBE_HI_COMMAND_TIMEOUT,
 519                                                   true);
 520                 if (rc != IXGBE_SUCCESS)
 521                         return rc;
 522                 if (hic.rsp.hdr.cmd_or_resp.ret_status ==
 523                     FW_CEM_RESP_STATUS_SUCCESS) {
 524                         for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
 525                                 (*data)[i] = IXGBE_BE32_TO_CPU(hic.rsp.data[i]);
 526                         return IXGBE_SUCCESS;
 527                 }
 528                 usec_delay(20);
 529                 --retries;
 530         } while (retries > 0);
 531
 532         return IXGBE_ERR_HOST_INTERFACE_COMMAND;
 533 }
 534
 535 static const struct {
 536         u16 fw_speed;
 537         ixgbe_link_speed phy_speed;
 538 } ixgbe_fw_map[] = {
 539         { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL },
 540         { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL },
 541         { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL },
 542         { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL },
 543         { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL },
 544         { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL },
 545 };
 546
 547 /**
 548  * ixgbe_get_phy_id_fw - Get the phy ID via firmware command
 549  * @hw: pointer to hardware structure
 550  *
 551  * Returns error code
 552  */
 553 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw)
 554 {
 555         u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
 556         u16 phy_speeds;
 557         u16 phy_id_lo;
 558         s32 rc;
 559         u16 i;
 560
 561         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info);
 562         if (rc)
 563                 return rc;
 564
 565         hw->phy.speeds_supported = 0;
 566         phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK;
 567         for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
 568                 if (phy_speeds & ixgbe_fw_map[i].fw_speed)
 569                         hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed;
 570         }
 571         if (!hw->phy.autoneg_advertised)
 572                 hw->phy.autoneg_advertised = hw->phy.speeds_supported;
 573
 574         hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK;
 575         phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK;
 576         hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK;
 577         hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK;
 578         if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK)
 579                 return IXGBE_ERR_PHY_ADDR_INVALID;
 580         return IXGBE_SUCCESS;
 581 }
 582
 583 /**
 584  * ixgbe_identify_phy_fw - Get PHY type based on firmware command
 585  * @hw: pointer to hardware structure
 586  *
 587  * Returns error code
 588  */
 589 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw)
 590 {
 591         if (hw->bus.lan_id)
 592                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 593         else
 594                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 595
 596         hw->phy.type = ixgbe_phy_fw;
 597         hw->phy.ops.read_reg = NULL;
 598         hw->phy.ops.write_reg = NULL;
 599         return ixgbe_get_phy_id_fw(hw);
 600 }
 601
 602 /**
 603  * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY
 604  * @hw: pointer to hardware structure
 605  *
 606  * Returns error code
 607  */
 608 s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw)
 609 {
 610         u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
 611
 612         setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF;
 613         return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup);
 614 }
 615
 616 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 617                                      u32 device_type, u16 *phy_data)
 618 {
 619         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 620         return IXGBE_NOT_IMPLEMENTED;
 621 }
 622
 623 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 624                                       u32 device_type, u16 phy_data)
 625 {
 626         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 627         return IXGBE_NOT_IMPLEMENTED;
 628 }
 629
 630 /**
 631  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 632  * @hw: pointer to the hardware structure
 633  * @addr: I2C bus address to read from
 634  * @reg: I2C device register to read from
 635  * @val: pointer to location to receive read value
 636  *
 637  * Returns an error code on error.
 638  **/
 639 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 640                                            u16 reg, u16 *val)
 641 {
 642         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 643 }
 644
 645 /**
 646  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 647  * @hw: pointer to the hardware structure
 648  * @addr: I2C bus address to read from
 649  * @reg: I2C device register to read from
 650  * @val: pointer to location to receive read value
 651  *
 652  * Returns an error code on error.
 653  **/
 654 STATIC s32
 655 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 656                                          u16 reg, u16 *val)
 657 {
 658         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 659 }
 660
 661 /**
 662  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 663  * @hw: pointer to the hardware structure
 664  * @addr: I2C bus address to write to
 665  * @reg: I2C device register to write to
 666  * @val: value to write
 667  *
 668  * Returns an error code on error.
 669  **/
 670 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 671                                             u8 addr, u16 reg, u16 val)
 672 {
 673         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 674 }
 675
 676 /**
 677  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 678  * @hw: pointer to the hardware structure
 679  * @addr: I2C bus address to write to
 680  * @reg: I2C device register to write to
 681  * @val: value to write
 682  *
 683  * Returns an error code on error.
 684  **/
 685 STATIC s32
 686 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 687                                           u8 addr, u16 reg, u16 val)
 688 {
 689         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 690 }
 691
 692 /**
 693 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 694 *  @hw: pointer to hardware structure
 695 *
 696 *  Initialize the function pointers and for MAC type X550EM.
 697 *  Does not touch the hardware.
 698 **/
 699 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 700 {
 701         struct ixgbe_mac_info *mac = &hw->mac;
 702         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 703         struct ixgbe_phy_info *phy = &hw->phy;
 704         s32 ret_val;
 705
 706         DEBUGFUNC("ixgbe_init_ops_X550EM");
 707
 708         /* Similar to X550 so start there. */
 709         ret_val = ixgbe_init_ops_X550(hw);
 710
 711         /* Since this function eventually calls
 712          * ixgbe_init_ops_540 by design, we are setting
 713          * the pointers to NULL explicitly here to overwrite
 714          * the values being set in the x540 function.
 715          */
 716         /* Thermal sensor not supported in x550EM */
 717         mac->ops.get_thermal_sensor_data = NULL;
 718         mac->ops.init_thermal_sensor_thresh = NULL;
 719         mac->thermal_sensor_enabled = false;
 720
 721         /* FCOE not supported in x550EM */
 722         mac->ops.get_san_mac_addr = NULL;
 723         mac->ops.set_san_mac_addr = NULL;
 724         mac->ops.get_wwn_prefix = NULL;
 725         mac->ops.get_fcoe_boot_status = NULL;
 726
 727         /* IPsec not supported in x550EM */
 728         mac->ops.disable_sec_rx_path = NULL;
 729         mac->ops.enable_sec_rx_path = NULL;
 730
 731         /* AUTOC register is not present in x550EM. */
 732         mac->ops.prot_autoc_read = NULL;
 733         mac->ops.prot_autoc_write = NULL;
 734
 735         /* X550EM bus type is internal*/
 736         hw->bus.type = ixgbe_bus_type_internal;
 737         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 738
 739
 740         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 741         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 742         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 743         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 744         mac->ops.get_supported_physical_layer =
 745                                     ixgbe_get_supported_physical_layer_X550em;
 746
 747         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 748                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 749         else
 750                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 751
 752         /* PHY */
 753         phy->ops.init = ixgbe_init_phy_ops_X550em;
 754         switch (hw->device_id) {
 755         case IXGBE_DEV_ID_X550EM_A_1G_T:
 756         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 757                 mac->ops.setup_fc = NULL;
 758                 phy->ops.identify = ixgbe_identify_phy_fw;
 759                 phy->ops.set_phy_power = NULL;
 760                 phy->ops.get_firmware_version = NULL;
 761                 break;
 762         case IXGBE_DEV_ID_X550EM_X_1G_T:
 763                 mac->ops.setup_fc = NULL;
 764                 phy->ops.identify = ixgbe_identify_phy_x550em;
 765                 phy->ops.set_phy_power = NULL;
 766                 break;
 767         default:
 768                 phy->ops.identify = ixgbe_identify_phy_x550em;
 769         }
 770
 771         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 772                 phy->ops.set_phy_power = NULL;
 773
 774
 775         /* EEPROM */
 776         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 777         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 778         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 779         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 780         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 781         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 782         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 783         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 784
 785         return ret_val;
 786 }
 787
 788 /**
 789  * ixgbe_setup_fw_link - Setup firmware-controlled PHYs
 790  * @hw: pointer to hardware structure
 791  */
 792 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw)
 793 {
 794         u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
 795         s32 rc;
 796         u16 i;
 797
 798         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
 799                 return 0;
 800
 801         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
 802                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
 803                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
 804                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
 805         }
 806
 807         switch (hw->fc.requested_mode) {
 808         case ixgbe_fc_full:
 809                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX <<
 810                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 811                 break;
 812         case ixgbe_fc_rx_pause:
 813                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX <<
 814                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 815                 break;
 816         case ixgbe_fc_tx_pause:
 817                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX <<
 818                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 819                 break;
 820         default:
 821                 break;
 822         }
 823
 824         for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
 825                 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)
 826                         setup[0] |= ixgbe_fw_map[i].fw_speed;
 827         }
 828         setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN;
 829
 830         if (hw->phy.eee_speeds_advertised)
 831                 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE;
 832
 833         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup);
 834         if (rc)
 835                 return rc;
 836         if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN)
 837                 return IXGBE_ERR_OVERTEMP;
 838         return IXGBE_SUCCESS;
 839 }
 840
 841 /**
 842  * ixgbe_fc_autoneg_fw _ Set up flow control for FW-controlled PHYs
 843  * @hw: pointer to hardware structure
 844  *
 845  *  Called at init time to set up flow control.
 846  */
 847 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw)
 848 {
 849         if (hw->fc.requested_mode == ixgbe_fc_default)
 850                 hw->fc.requested_mode = ixgbe_fc_full;
 851
 852         return ixgbe_setup_fw_link(hw);
 853 }
 854
 855 /**
 856  * ixgbe_setup_eee_fw - Enable/disable EEE support
 857  * @hw: pointer to the HW structure
 858  * @enable_eee: boolean flag to enable EEE
 859  *
 860  * Enable/disable EEE based on enable_eee flag.
 861  * This function controls EEE for firmware-based PHY implementations.
 862  */
 863 static s32 ixgbe_setup_eee_fw(struct ixgbe_hw *hw, bool enable_eee)
 864 {
 865         if (!!hw->phy.eee_speeds_advertised == enable_eee)
 866                 return IXGBE_SUCCESS;
 867         if (enable_eee)
 868                 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
 869         else
 870                 hw->phy.eee_speeds_advertised = 0;
 871         return hw->phy.ops.setup_link(hw);
 872 }
 873
 874 /**
 875 *  ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
 876 *  @hw: pointer to hardware structure
 877 *
 878 *  Initialize the function pointers and for MAC type X550EM_a.
 879 *  Does not touch the hardware.
 880 **/
 881 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
 882 {
 883         struct ixgbe_mac_info *mac = &hw->mac;
 884         s32 ret_val;
 885
 886         DEBUGFUNC("ixgbe_init_ops_X550EM_a");
 887
 888         /* Start with generic X550EM init */
 889         ret_val = ixgbe_init_ops_X550EM(hw);
 890
 891         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
 892             hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) {
 893                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 894                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 895         } else {
 896                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
 897                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
 898         }
 899         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
 900         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
 901
 902         switch (mac->ops.get_media_type(hw)) {
 903         case ixgbe_media_type_fiber:
 904                 mac->ops.setup_fc = NULL;
 905                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
 906                 break;
 907         case ixgbe_media_type_backplane:
 908                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
 909                 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
 910                 break;
 911         default:
 912                 break;
 913         }
 914
 915         switch (hw->device_id) {
 916         case IXGBE_DEV_ID_X550EM_A_1G_T:
 917         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 918                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
 919                 mac->ops.setup_fc = ixgbe_fc_autoneg_fw;
 920                 mac->ops.setup_eee = ixgbe_setup_eee_fw;
 921                 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL |
 922                                                IXGBE_LINK_SPEED_1GB_FULL;
 923                 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
 924                 break;
 925         default:
 926                 break;
 927         }
 928
 929         return ret_val;
 930 }
 931
 932 /**
 933 *  ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
 934 *  @hw: pointer to hardware structure
 935 *
 936 *  Initialize the function pointers and for MAC type X550EM_x.
 937 *  Does not touch the hardware.
 938 **/
 939 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
 940 {
 941         struct ixgbe_mac_info *mac = &hw->mac;
 942         struct ixgbe_link_info *link = &hw->link;
 943         s32 ret_val;
 944
 945         DEBUGFUNC("ixgbe_init_ops_X550EM_x");
 946
 947         /* Start with generic X550EM init */
 948         ret_val = ixgbe_init_ops_X550EM(hw);
 949
 950         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 951         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 952         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 953         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 954         link->ops.read_link = ixgbe_read_i2c_combined_generic;
 955         link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
 956         link->ops.write_link = ixgbe_write_i2c_combined_generic;
 957         link->ops.write_link_unlocked =
 958                                       ixgbe_write_i2c_combined_generic_unlocked;
 959         link->addr = IXGBE_CS4227;
 960
 961         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T) {
 962                 mac->ops.setup_fc = NULL;
 963                 mac->ops.setup_eee = NULL;
 964                 mac->ops.init_led_link_act = NULL;
 965         }
 966
 967         return ret_val;
 968 }
 969
 970 /**
 971  *  ixgbe_dmac_config_X550
 972  *  @hw: pointer to hardware structure
 973  *
 974  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 975  *  When disabling dmac, dmac enable dmac bit is cleared.
 976  **/
 977 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 978 {
 979         u32 reg, high_pri_tc;
 980
 981         DEBUGFUNC("ixgbe_dmac_config_X550");
 982
 983         /* Disable DMA coalescing before configuring */
 984         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 985         reg &= ~IXGBE_DMACR_DMAC_EN;
 986         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 987
 988         /* Disable DMA Coalescing if the watchdog timer is 0 */
 989         if (!hw->mac.dmac_config.watchdog_timer)
 990                 goto out;
 991
 992         ixgbe_dmac_config_tcs_X550(hw);
 993
 994         /* Configure DMA Coalescing Control Register */
 995         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 996
 997         /* Set the watchdog timer in units of 40.96 usec */
 998         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 999         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
1000
1001         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
1002         /* If fcoe is enabled, set high priority traffic class */
1003         if (hw->mac.dmac_config.fcoe_en) {
1004                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
1005                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
1006                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
1007         }
1008         reg |= IXGBE_DMACR_EN_MNG_IND;
1009
1010         /* Enable DMA coalescing after configuration */
1011         reg |= IXGBE_DMACR_DMAC_EN;
1012         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
1013
1014 out:
1015         return IXGBE_SUCCESS;
1016 }
1017
1018 /**
1019  *  ixgbe_dmac_config_tcs_X550
1020  *  @hw: pointer to hardware structure
1021  *
1022  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
1023  *  be cleared before configuring.
1024  **/
1025 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
1026 {
1027         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
1028
1029         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
1030
1031         /* Configure DMA coalescing enabled */
1032         switch (hw->mac.dmac_config.link_speed) {
1033         case IXGBE_LINK_SPEED_10_FULL:
1034         case IXGBE_LINK_SPEED_100_FULL:
1035                 pb_headroom = IXGBE_DMACRXT_100M;
1036                 break;
1037         case IXGBE_LINK_SPEED_1GB_FULL:
1038                 pb_headroom = IXGBE_DMACRXT_1G;
1039                 break;
1040         default:
1041                 pb_headroom = IXGBE_DMACRXT_10G;
1042                 break;
1043         }
1044
1045         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
1046                              IXGBE_MHADD_MFS_SHIFT) / 1024);
1047
1048         /* Set the per Rx packet buffer receive threshold */
1049         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
1050                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
1051                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
1052
1053                 if (tc < hw->mac.dmac_config.num_tcs) {
1054                         /* Get Rx PB size */
1055                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
1056                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
1057                                 IXGBE_RXPBSIZE_SHIFT;
1058
1059                         /* Calculate receive buffer threshold in kilobytes */
1060                         if (rx_pb_size > pb_headroom)
1061                                 rx_pb_size = rx_pb_size - pb_headroom;
1062                         else
1063                                 rx_pb_size = 0;
1064
1065                         /* Minimum of MFS shall be set for DMCTH */
1066                         reg |= (rx_pb_size > maxframe_size_kb) ?
1067                                 rx_pb_size : maxframe_size_kb;
1068                 }
1069                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
1070         }
1071         return IXGBE_SUCCESS;
1072 }
1073
1074 /**
1075  *  ixgbe_dmac_update_tcs_X550
1076  *  @hw: pointer to hardware structure
1077  *
1078  *  Disables dmac, updates per TC settings, and then enables dmac.
1079  **/
1080 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
1081 {
1082         u32 reg;
1083
1084         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
1085
1086         /* Disable DMA coalescing before configuring */
1087         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
1088         reg &= ~IXGBE_DMACR_DMAC_EN;
1089         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
1090
1091         ixgbe_dmac_config_tcs_X550(hw);
1092
1093         /* Enable DMA coalescing after configuration */
1094         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
1095         reg |= IXGBE_DMACR_DMAC_EN;
1096         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
1097
1098         return IXGBE_SUCCESS;
1099 }
1100
1101 /**
1102  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
1103  *  @hw: pointer to hardware structure
1104  *
1105  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
1106  *  ixgbe_hw struct in order to set up EEPROM access.
1107  **/
1108 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
1109 {
1110         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1111         u32 eec;
1112         u16 eeprom_size;
1113
1114         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
1115
1116         if (eeprom->type == ixgbe_eeprom_uninitialized) {
1117                 eeprom->semaphore_delay = 10;
1118                 eeprom->type = ixgbe_flash;
1119
1120                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1121                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1122                                     IXGBE_EEC_SIZE_SHIFT);
1123                 eeprom->word_size = 1 << (eeprom_size +
1124                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
1125
1126                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
1127                           eeprom->type, eeprom->word_size);
1128         }
1129
1130         return IXGBE_SUCCESS;
1131 }
1132
1133 /**
1134  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1135  * @hw: pointer to hardware structure
1136  * @enable: enable or disable source address pruning
1137  * @pool: Rx pool to set source address pruning for
1138  **/
1139 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1140                                            unsigned int pool)
1141 {
1142         u64 pfflp;
1143
1144         /* max rx pool is 63 */
1145         if (pool > 63)
1146                 return;
1147
1148         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1149         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1150
1151         if (enable)
1152                 pfflp |= (1ULL << pool);
1153         else
1154                 pfflp &= ~(1ULL << pool);
1155
1156         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1157         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1158 }
1159
1160 /**
1161  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1162  *  @hw: pointer to hardware structure
1163  *  @enable: enable or disable switch for Ethertype anti-spoofing
1164  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1165  *
1166  **/
1167 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1168                 bool enable, int vf)
1169 {
1170         int vf_target_reg = vf >> 3;
1171         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1172         u32 pfvfspoof;
1173
1174         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1175
1176         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1177         if (enable)
1178                 pfvfspoof |= (1 << vf_target_shift);
1179         else
1180                 pfvfspoof &= ~(1 << vf_target_shift);
1181
1182         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1183 }
1184
1185 /**
1186  * ixgbe_iosf_wait - Wait for IOSF command completion
1187  * @hw: pointer to hardware structure
1188  * @ctrl: pointer to location to receive final IOSF control value
1189  *
1190  * Returns failing status on timeout
1191  *
1192  * Note: ctrl can be NULL if the IOSF control register value is not needed
1193  **/
1194 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1195 {
1196         u32 i, command = 0;
1197
1198         /* Check every 10 usec to see if the address cycle completed.
1199          * The SB IOSF BUSY bit will clear when the operation is
1200          * complete
1201          */
1202         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1203                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1204                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1205                         break;
1206                 usec_delay(10);
1207         }
1208         if (ctrl)
1209                 *ctrl = command;
1210         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1211                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1212                 return IXGBE_ERR_PHY;
1213         }
1214
1215         return IXGBE_SUCCESS;
1216 }
1217
1218 /**
1219  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register
1220  *  of the IOSF device
1221  *  @hw: pointer to hardware structure
1222  *  @reg_addr: 32 bit PHY register to write
1223  *  @device_type: 3 bit device type
1224  *  @data: Data to write to the register
1225  **/
1226 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1227                             u32 device_type, u32 data)
1228 {
1229         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1230         u32 command, error;
1231         s32 ret;
1232
1233         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1234         if (ret != IXGBE_SUCCESS)
1235                 return ret;
1236
1237         ret = ixgbe_iosf_wait(hw, NULL);
1238         if (ret != IXGBE_SUCCESS)
1239                 goto out;
1240
1241         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1242                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1243
1244         /* Write IOSF control register */
1245         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1246
1247         /* Write IOSF data register */
1248         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1249
1250         ret = ixgbe_iosf_wait(hw, &command);
1251
1252         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1253                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1254                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1255                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1256                               "Failed to write, error %x\n", error);
1257                 ret = IXGBE_ERR_PHY;
1258         }
1259
1260 out:
1261         ixgbe_release_swfw_semaphore(hw, gssr);
1262         return ret;
1263 }
1264
1265 /**
1266  *  ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device
1267  *  @hw: pointer to hardware structure
1268  *  @reg_addr: 32 bit PHY register to write
1269  *  @device_type: 3 bit device type
1270  *  @data: Pointer to read data from the register
1271  **/
1272 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1273                            u32 device_type, u32 *data)
1274 {
1275         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1276         u32 command, error;
1277         s32 ret;
1278
1279         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1280         if (ret != IXGBE_SUCCESS)
1281                 return ret;
1282
1283         ret = ixgbe_iosf_wait(hw, NULL);
1284         if (ret != IXGBE_SUCCESS)
1285                 goto out;
1286
1287         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1288                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1289
1290         /* Write IOSF control register */
1291         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1292
1293         ret = ixgbe_iosf_wait(hw, &command);
1294
1295         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1296                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1297                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1298                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1299                                 "Failed to read, error %x\n", error);
1300                 ret = IXGBE_ERR_PHY;
1301         }
1302
1303         if (ret == IXGBE_SUCCESS)
1304                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1305
1306 out:
1307         ixgbe_release_swfw_semaphore(hw, gssr);
1308         return ret;
1309 }
1310
1311 /**
1312  * ixgbe_get_phy_token - Get the token for shared phy access
1313  * @hw: Pointer to hardware structure
1314  */
1315
1316 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1317 {
1318         struct ixgbe_hic_phy_token_req token_cmd;
1319         s32 status;
1320
1321         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1322         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1323         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1324         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1325         token_cmd.port_number = hw->bus.lan_id;
1326         token_cmd.command_type = FW_PHY_TOKEN_REQ;
1327         token_cmd.pad = 0;
1328         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1329                                               sizeof(token_cmd),
1330                                               IXGBE_HI_COMMAND_TIMEOUT,
1331                                               true);
1332         if (status) {
1333                 DEBUGOUT1("Issuing host interface command failed with Status = %d\n",
1334                           status);
1335                 return status;
1336         }
1337         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1338                 return IXGBE_SUCCESS;
1339         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY) {
1340                 DEBUGOUT1("Host interface command returned 0x%08x , returning IXGBE_ERR_FW_RESP_INVALID\n",
1341                           token_cmd.hdr.cmd_or_resp.ret_status);
1342                 return IXGBE_ERR_FW_RESP_INVALID;
1343         }
1344
1345         DEBUGOUT("Returning  IXGBE_ERR_TOKEN_RETRY\n");
1346         return IXGBE_ERR_TOKEN_RETRY;
1347 }
1348
1349 /**
1350  * ixgbe_put_phy_token - Put the token for shared phy access
1351  * @hw: Pointer to hardware structure
1352  */
1353
1354 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1355 {
1356         struct ixgbe_hic_phy_token_req token_cmd;
1357         s32 status;
1358
1359         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1360         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1361         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1362         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1363         token_cmd.port_number = hw->bus.lan_id;
1364         token_cmd.command_type = FW_PHY_TOKEN_REL;
1365         token_cmd.pad = 0;
1366         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1367                                               sizeof(token_cmd),
1368                                               IXGBE_HI_COMMAND_TIMEOUT,
1369                                               true);
1370         if (status)
1371                 return status;
1372         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1373                 return IXGBE_SUCCESS;
1374
1375         DEBUGOUT("Put PHY Token host interface command failed");
1376         return IXGBE_ERR_FW_RESP_INVALID;
1377 }
1378
1379 /**
1380  *  ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1381  *  of the IOSF device
1382  *  @hw: pointer to hardware structure
1383  *  @reg_addr: 32 bit PHY register to write
1384  *  @device_type: 3 bit device type
1385  *  @data: Data to write to the register
1386  **/
1387 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1388                                   u32 device_type, u32 data)
1389 {
1390         struct ixgbe_hic_internal_phy_req write_cmd;
1391         s32 status;
1392         UNREFERENCED_1PARAMETER(device_type);
1393
1394         memset(&write_cmd, 0, sizeof(write_cmd));
1395         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1396         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1397         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1398         write_cmd.port_number = hw->bus.lan_id;
1399         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1400         write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1401         write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1402
1403         status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1404                                               sizeof(write_cmd),
1405                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1406
1407         return status;
1408 }
1409
1410 /**
1411  *  ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device
1412  *  @hw: pointer to hardware structure
1413  *  @reg_addr: 32 bit PHY register to write
1414  *  @device_type: 3 bit device type
1415  *  @data: Pointer to read data from the register
1416  **/
1417 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1418                                  u32 device_type, u32 *data)
1419 {
1420         union {
1421                 struct ixgbe_hic_internal_phy_req cmd;
1422                 struct ixgbe_hic_internal_phy_resp rsp;
1423         } hic;
1424         s32 status;
1425         UNREFERENCED_1PARAMETER(device_type);
1426
1427         memset(&hic, 0, sizeof(hic));
1428         hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1429         hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1430         hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1431         hic.cmd.port_number = hw->bus.lan_id;
1432         hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1433         hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1434
1435         status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1436                                               sizeof(hic.cmd),
1437                                               IXGBE_HI_COMMAND_TIMEOUT, true);
1438
1439         /* Extract the register value from the response. */
1440         *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1441
1442         return status;
1443 }
1444
1445 /**
1446  *  ixgbe_disable_mdd_X550
1447  *  @hw: pointer to hardware structure
1448  *
1449  *  Disable malicious driver detection
1450  **/
1451 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1452 {
1453         u32 reg;
1454
1455         DEBUGFUNC("ixgbe_disable_mdd_X550");
1456
1457         /* Disable MDD for TX DMA and interrupt */
1458         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1459         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1460         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1461
1462         /* Disable MDD for RX and interrupt */
1463         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1464         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1465         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1466 }
1467
1468 /**
1469  *  ixgbe_enable_mdd_X550
1470  *  @hw: pointer to hardware structure
1471  *
1472  *  Enable malicious driver detection
1473  **/
1474 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1475 {
1476         u32 reg;
1477
1478         DEBUGFUNC("ixgbe_enable_mdd_X550");
1479
1480         /* Enable MDD for TX DMA and interrupt */
1481         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1482         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1483         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1484
1485         /* Enable MDD for RX and interrupt */
1486         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1487         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1488         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1489 }
1490
1491 /**
1492  *  ixgbe_restore_mdd_vf_X550
1493  *  @hw: pointer to hardware structure
1494  *  @vf: vf index
1495  *
1496  *  Restore VF that was disabled during malicious driver detection event
1497  **/
1498 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1499 {
1500         u32 idx, reg, num_qs, start_q, bitmask;
1501
1502         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1503
1504         /* Map VF to queues */
1505         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1506         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1507         case IXGBE_MRQC_VMDQRT8TCEN:
1508                 num_qs = 8;  /* 16 VFs / pools */
1509                 bitmask = 0x000000FF;
1510                 break;
1511         case IXGBE_MRQC_VMDQRSS32EN:
1512         case IXGBE_MRQC_VMDQRT4TCEN:
1513                 num_qs = 4;  /* 32 VFs / pools */
1514                 bitmask = 0x0000000F;
1515                 break;
1516         default:            /* 64 VFs / pools */
1517                 num_qs = 2;
1518                 bitmask = 0x00000003;
1519                 break;
1520         }
1521         start_q = vf * num_qs;
1522
1523         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1524         idx = start_q / 32;
1525         reg = 0;
1526         reg |= (bitmask << (start_q % 32));
1527         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1528         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1529 }
1530
1531 /**
1532  *  ixgbe_mdd_event_X550
1533  *  @hw: pointer to hardware structure
1534  *  @vf_bitmap: vf bitmap of malicious vfs
1535  *
1536  *  Handle malicious driver detection event.
1537  **/
1538 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1539 {
1540         u32 wqbr;
1541         u32 i, j, reg, q, shift, vf, idx;
1542
1543         DEBUGFUNC("ixgbe_mdd_event_X550");
1544
1545         /* figure out pool size for mapping to vf's */
1546         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1547         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1548         case IXGBE_MRQC_VMDQRT8TCEN:
1549                 shift = 3;  /* 16 VFs / pools */
1550                 break;
1551         case IXGBE_MRQC_VMDQRSS32EN:
1552         case IXGBE_MRQC_VMDQRT4TCEN:
1553                 shift = 2;  /* 32 VFs / pools */
1554                 break;
1555         default:
1556                 shift = 1;  /* 64 VFs / pools */
1557                 break;
1558         }
1559
1560         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1561         for (i = 0; i < 4; i++) {
1562                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1563                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1564
1565                 if (!wqbr)
1566                         continue;
1567
1568                 /* Get malicious queue */
1569                 for (j = 0; j < 32 && wqbr; j++) {
1570
1571                         if (!(wqbr & (1 << j)))
1572                                 continue;
1573
1574                         /* Get queue from bitmask */
1575                         q = j + (i * 32);
1576
1577                         /* Map queue to vf */
1578                         vf = (q >> shift);
1579
1580                         /* Set vf bit in vf_bitmap */
1581                         idx = vf / 32;
1582                         vf_bitmap[idx] |= (1 << (vf % 32));
1583                         wqbr &= ~(1 << j);
1584                 }
1585         }
1586 }
1587
1588 /**
1589  *  ixgbe_get_media_type_X550em - Get media type
1590  *  @hw: pointer to hardware structure
1591  *
1592  *  Returns the media type (fiber, copper, backplane)
1593  */
1594 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1595 {
1596         enum ixgbe_media_type media_type;
1597
1598         DEBUGFUNC("ixgbe_get_media_type_X550em");
1599
1600         /* Detect if there is a copper PHY attached. */
1601         switch (hw->device_id) {
1602         case IXGBE_DEV_ID_X550EM_X_KR:
1603         case IXGBE_DEV_ID_X550EM_X_KX4:
1604         case IXGBE_DEV_ID_X550EM_X_XFI:
1605         case IXGBE_DEV_ID_X550EM_A_KR:
1606         case IXGBE_DEV_ID_X550EM_A_KR_L:
1607                 media_type = ixgbe_media_type_backplane;
1608                 break;
1609         case IXGBE_DEV_ID_X550EM_X_SFP:
1610         case IXGBE_DEV_ID_X550EM_A_SFP:
1611         case IXGBE_DEV_ID_X550EM_A_SFP_N:
1612         case IXGBE_DEV_ID_X550EM_A_QSFP:
1613         case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1614                 media_type = ixgbe_media_type_fiber;
1615                 break;
1616         case IXGBE_DEV_ID_X550EM_X_1G_T:
1617         case IXGBE_DEV_ID_X550EM_X_10G_T:
1618         case IXGBE_DEV_ID_X550EM_A_10G_T:
1619                 media_type = ixgbe_media_type_copper;
1620                 break;
1621         case IXGBE_DEV_ID_X550EM_A_SGMII:
1622         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1623                 media_type = ixgbe_media_type_backplane;
1624                 hw->phy.type = ixgbe_phy_sgmii;
1625                 break;
1626         case IXGBE_DEV_ID_X550EM_A_1G_T:
1627         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1628                 media_type = ixgbe_media_type_copper;
1629                 break;
1630         default:
1631                 media_type = ixgbe_media_type_unknown;
1632                 break;
1633         }
1634         return media_type;
1635 }
1636
1637 /**
1638  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1639  *  @hw: pointer to hardware structure
1640  *  @linear: true if SFP module is linear
1641  */
1642 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1643 {
1644         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1645
1646         switch (hw->phy.sfp_type) {
1647         case ixgbe_sfp_type_not_present:
1648                 return IXGBE_ERR_SFP_NOT_PRESENT;
1649         case ixgbe_sfp_type_da_cu_core0:
1650         case ixgbe_sfp_type_da_cu_core1:
1651                 *linear = true;
1652                 break;
1653         case ixgbe_sfp_type_srlr_core0:
1654         case ixgbe_sfp_type_srlr_core1:
1655         case ixgbe_sfp_type_da_act_lmt_core0:
1656         case ixgbe_sfp_type_da_act_lmt_core1:
1657         case ixgbe_sfp_type_1g_sx_core0:
1658         case ixgbe_sfp_type_1g_sx_core1:
1659         case ixgbe_sfp_type_1g_lx_core0:
1660         case ixgbe_sfp_type_1g_lx_core1:
1661                 *linear = false;
1662                 break;
1663         case ixgbe_sfp_type_unknown:
1664         case ixgbe_sfp_type_1g_cu_core0:
1665         case ixgbe_sfp_type_1g_cu_core1:
1666         default:
1667                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1668         }
1669
1670         return IXGBE_SUCCESS;
1671 }
1672
1673 /**
1674  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1675  *  @hw: pointer to hardware structure
1676  *
1677  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1678  **/
1679 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1680 {
1681         s32 status;
1682         bool linear;
1683
1684         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1685
1686         status = ixgbe_identify_module_generic(hw);
1687
1688         if (status != IXGBE_SUCCESS)
1689                 return status;
1690
1691         /* Check if SFP module is supported */
1692         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1693
1694         return status;
1695 }
1696
1697 /**
1698  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1699  *  @hw: pointer to hardware structure
1700  */
1701 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1702 {
1703         s32 status;
1704         bool linear;
1705
1706         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1707
1708         /* Check if SFP module is supported */
1709         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1710
1711         if (status != IXGBE_SUCCESS)
1712                 return status;
1713
1714         ixgbe_init_mac_link_ops_X550em(hw);
1715         hw->phy.ops.reset = NULL;
1716
1717         return IXGBE_SUCCESS;
1718 }
1719
1720 /**
1721 *  ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1722 *  internal PHY
1723 *  @hw: pointer to hardware structure
1724 **/
1725 STATIC s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1726 {
1727         s32 status;
1728         u32 link_ctrl;
1729
1730         /* Restart auto-negotiation. */
1731         status = hw->mac.ops.read_iosf_sb_reg(hw,
1732                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1733                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1734
1735         if (status) {
1736                 DEBUGOUT("Auto-negotiation did not complete\n");
1737                 return status;
1738         }
1739
1740         link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1741         status = hw->mac.ops.write_iosf_sb_reg(hw,
1742                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1743                                         IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1744
1745         if (hw->mac.type == ixgbe_mac_X550EM_a) {
1746                 u32 flx_mask_st20;
1747
1748                 /* Indicate to FW that AN restart has been asserted */
1749                 status = hw->mac.ops.read_iosf_sb_reg(hw,
1750                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1751                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1752
1753                 if (status) {
1754                         DEBUGOUT("Auto-negotiation did not complete\n");
1755                         return status;
1756                 }
1757
1758                 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1759                 status = hw->mac.ops.write_iosf_sb_reg(hw,
1760                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1761                                 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1762         }
1763
1764         return status;
1765 }
1766
1767 /**
1768  * ixgbe_setup_sgmii - Set up link for sgmii
1769  * @hw: pointer to hardware structure
1770  */
1771 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1772                              bool autoneg_wait)
1773 {
1774         struct ixgbe_mac_info *mac = &hw->mac;
1775         u32 lval, sval, flx_val;
1776         s32 rc;
1777
1778         rc = mac->ops.read_iosf_sb_reg(hw,
1779                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1780                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1781         if (rc)
1782                 return rc;
1783
1784         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1785         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1786         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1787         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1788         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1789         rc = mac->ops.write_iosf_sb_reg(hw,
1790                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1791                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1792         if (rc)
1793                 return rc;
1794
1795         rc = mac->ops.read_iosf_sb_reg(hw,
1796                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1797                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1798         if (rc)
1799                 return rc;
1800
1801         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1802         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1803         rc = mac->ops.write_iosf_sb_reg(hw,
1804                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1805                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1806         if (rc)
1807                 return rc;
1808
1809         rc = mac->ops.read_iosf_sb_reg(hw,
1810                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1811                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1812         if (rc)
1813                 return rc;
1814
1815         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1816         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1817         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1818         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1819         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1820
1821         rc = mac->ops.write_iosf_sb_reg(hw,
1822                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1823                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1824         if (rc)
1825                 return rc;
1826
1827         rc = ixgbe_restart_an_internal_phy_x550em(hw);
1828         if (rc)
1829                 return rc;
1830
1831         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1832 }
1833
1834 /**
1835  * ixgbe_setup_sgmii_fw - Set up link for sgmii with firmware-controlled PHYs
1836  * @hw: pointer to hardware structure
1837  */
1838 STATIC s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1839                                 bool autoneg_wait)
1840 {
1841         struct ixgbe_mac_info *mac = &hw->mac;
1842         u32 lval, sval, flx_val;
1843         s32 rc;
1844
1845         rc = mac->ops.read_iosf_sb_reg(hw,
1846                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1847                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1848         if (rc)
1849                 return rc;
1850
1851         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1852         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1853         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1854         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1855         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1856         rc = mac->ops.write_iosf_sb_reg(hw,
1857                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1858                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1859         if (rc)
1860                 return rc;
1861
1862         rc = mac->ops.read_iosf_sb_reg(hw,
1863                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1864                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1865         if (rc)
1866                 return rc;
1867
1868         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1869         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1870         rc = mac->ops.write_iosf_sb_reg(hw,
1871                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1872                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1873         if (rc)
1874                 return rc;
1875
1876         rc = mac->ops.write_iosf_sb_reg(hw,
1877                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1878                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1879         if (rc)
1880                 return rc;
1881
1882         rc = mac->ops.read_iosf_sb_reg(hw,
1883                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1884                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1885         if (rc)
1886                 return rc;
1887
1888         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1889         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
1890         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1891         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1892         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1893
1894         rc = mac->ops.write_iosf_sb_reg(hw,
1895                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1896                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1897         if (rc)
1898                 return rc;
1899
1900         rc = ixgbe_restart_an_internal_phy_x550em(hw);
1901
1902         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1903 }
1904
1905 /**
1906  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1907  *  @hw: pointer to hardware structure
1908  */
1909 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1910 {
1911         struct ixgbe_mac_info *mac = &hw->mac;
1912
1913         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1914
1915         switch (hw->mac.ops.get_media_type(hw)) {
1916         case ixgbe_media_type_fiber:
1917                 /* CS4227 does not support autoneg, so disable the laser control
1918                  * functions for SFP+ fiber
1919                  */
1920                 mac->ops.disable_tx_laser = NULL;
1921                 mac->ops.enable_tx_laser = NULL;
1922                 mac->ops.flap_tx_laser = NULL;
1923                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1924                 mac->ops.set_rate_select_speed =
1925                                         ixgbe_set_soft_rate_select_speed;
1926
1927                 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1928                     (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1929                         mac->ops.setup_mac_link =
1930                                                 ixgbe_setup_mac_link_sfp_x550a;
1931                 else
1932                         mac->ops.setup_mac_link =
1933                                                 ixgbe_setup_mac_link_sfp_x550em;
1934                 break;
1935         case ixgbe_media_type_copper:
1936                 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T)
1937                         break;
1938                 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1939                         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
1940                             hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
1941                                 mac->ops.setup_link = ixgbe_setup_sgmii_fw;
1942                                 mac->ops.check_link =
1943                                                    ixgbe_check_mac_link_generic;
1944                         } else {
1945                                 mac->ops.setup_link =
1946                                                   ixgbe_setup_mac_link_t_X550em;
1947                         }
1948                 } else {
1949                         mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1950                         mac->ops.check_link = ixgbe_check_link_t_X550em;
1951                 }
1952                 break;
1953         case ixgbe_media_type_backplane:
1954                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1955                     hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1956                         mac->ops.setup_link = ixgbe_setup_sgmii;
1957                 break;
1958         default:
1959                 break;
1960         }
1961 }
1962
1963 /**
1964  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1965  *  @hw: pointer to hardware structure
1966  *  @speed: pointer to link speed
1967  *  @autoneg: true when autoneg or autotry is enabled
1968  */
1969 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1970                                        ixgbe_link_speed *speed,
1971                                        bool *autoneg)
1972 {
1973         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1974
1975
1976         if (hw->phy.type == ixgbe_phy_fw) {
1977                 *autoneg = true;
1978                 *speed = hw->phy.speeds_supported;
1979                 return 0;
1980         }
1981
1982         /* SFP */
1983         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1984
1985                 /* CS4227 SFP must not enable auto-negotiation */
1986                 *autoneg = false;
1987
1988                 /* Check if 1G SFP module. */
1989                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1990                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1991                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1992                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1993                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1994                         return IXGBE_SUCCESS;
1995                 }
1996
1997                 /* Link capabilities are based on SFP */
1998                 if (hw->phy.multispeed_fiber)
1999                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
2000                                  IXGBE_LINK_SPEED_1GB_FULL;
2001                 else
2002                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
2003         } else {
2004                 switch (hw->phy.type) {
2005                 case ixgbe_phy_ext_1g_t:
2006                 case ixgbe_phy_sgmii:
2007                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
2008                         break;
2009                 case ixgbe_phy_x550em_kr:
2010                         if (hw->mac.type == ixgbe_mac_X550EM_a) {
2011                                 /* check different backplane modes */
2012                                 if (hw->phy.nw_mng_if_sel &
2013                                            IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
2014                                         *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
2015                                         break;
2016                                 } else if (hw->device_id ==
2017                                                    IXGBE_DEV_ID_X550EM_A_KR_L) {
2018                                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
2019                                         break;
2020                                 }
2021                         }
2022                         /* fall through */
2023                 default:
2024                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
2025                                  IXGBE_LINK_SPEED_1GB_FULL;
2026                         break;
2027                 }
2028                 *autoneg = true;
2029         }
2030
2031         return IXGBE_SUCCESS;
2032 }
2033
2034 /**
2035  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
2036  * @hw: pointer to hardware structure
2037  * @lsc: pointer to boolean flag which indicates whether external Base T
2038  *       PHY interrupt is lsc
2039  *
2040  * Determime if external Base T PHY interrupt cause is high temperature
2041  * failure alarm or link status change.
2042  *
2043  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2044  * failure alarm, else return PHY access status.
2045  */
2046 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
2047 {
2048         u32 status;
2049         u16 reg;
2050
2051         *lsc = false;
2052
2053         /* Vendor alarm triggered */
2054         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2055                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2056                                       &reg);
2057
2058         if (status != IXGBE_SUCCESS ||
2059             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
2060                 return status;
2061
2062         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
2063         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
2064                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2065                                       &reg);
2066
2067         if (status != IXGBE_SUCCESS ||
2068             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2069             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
2070                 return status;
2071
2072         /* Global alarm triggered */
2073         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
2074                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2075                                       &reg);
2076
2077         if (status != IXGBE_SUCCESS)
2078                 return status;
2079
2080         /* If high temperature failure, then return over temp error and exit */
2081         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
2082                 /* power down the PHY in case the PHY FW didn't already */
2083                 ixgbe_set_copper_phy_power(hw, false);
2084                 return IXGBE_ERR_OVERTEMP;
2085         } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
2086                 /*  device fault alarm triggered */
2087                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
2088                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2089                                           &reg);
2090
2091                 if (status != IXGBE_SUCCESS)
2092                         return status;
2093
2094                 /* if device fault was due to high temp alarm handle and exit */
2095                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
2096                         /* power down the PHY in case the PHY FW didn't */
2097                         ixgbe_set_copper_phy_power(hw, false);
2098                         return IXGBE_ERR_OVERTEMP;
2099                 }
2100         }
2101
2102         /* Vendor alarm 2 triggered */
2103         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2104                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2105
2106         if (status != IXGBE_SUCCESS ||
2107             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
2108                 return status;
2109
2110         /* link connect/disconnect event occurred */
2111         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
2112                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2113
2114         if (status != IXGBE_SUCCESS)
2115                 return status;
2116
2117         /* Indicate LSC */
2118         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2119                 *lsc = true;
2120
2121         return IXGBE_SUCCESS;
2122 }
2123
2124 /**
2125  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2126  * @hw: pointer to hardware structure
2127  *
2128  * Enable link status change and temperature failure alarm for the external
2129  * Base T PHY
2130  *
2131  * Returns PHY access status
2132  */
2133 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2134 {
2135         u32 status;
2136         u16 reg;
2137         bool lsc;
2138
2139         /* Clear interrupt flags */
2140         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2141
2142         /* Enable link status change alarm */
2143
2144         /* Enable the LASI interrupts on X552 devices to receive notifications
2145          * of the link configurations of the external PHY and correspondingly
2146          * support the configuration of the internal iXFI link, since iXFI does
2147          * not support auto-negotiation. This is not required for X553 devices
2148          * having KR support, which performs auto-negotiations and which is used
2149          * as the internal link to the external PHY. Hence adding a check here
2150          * to avoid enabling LASI interrupts for X553 devices.
2151          */
2152         if (hw->mac.type != ixgbe_mac_X550EM_a) {
2153                 status = hw->phy.ops.read_reg(hw,
2154                                         IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2155                                         IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2156
2157                 if (status != IXGBE_SUCCESS)
2158                         return status;
2159
2160                 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2161
2162                 status = hw->phy.ops.write_reg(hw,
2163                                         IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2164                                         IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
2165
2166                 if (status != IXGBE_SUCCESS)
2167                         return status;
2168         }
2169
2170         /* Enable high temperature failure and global fault alarms */
2171         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2172                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2173                                       &reg);
2174
2175         if (status != IXGBE_SUCCESS)
2176                 return status;
2177
2178         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2179                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2180
2181         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2182                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2183                                        reg);
2184
2185         if (status != IXGBE_SUCCESS)
2186                 return status;
2187
2188         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2189         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2190                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2191                                       &reg);
2192
2193         if (status != IXGBE_SUCCESS)
2194                 return status;
2195
2196         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2197                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2198
2199         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2200                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2201                                        reg);
2202
2203         if (status != IXGBE_SUCCESS)
2204                 return status;
2205
2206         /* Enable chip-wide vendor alarm */
2207         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2208                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2209                                       &reg);
2210
2211         if (status != IXGBE_SUCCESS)
2212                 return status;
2213
2214         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2215
2216         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2217                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2218                                        reg);
2219
2220         return status;
2221 }
2222
2223 /**
2224  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2225  *  @hw: pointer to hardware structure
2226  *  @speed: link speed
2227  *
2228  *  Configures the integrated KR PHY.
2229  **/
2230 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2231                                        ixgbe_link_speed speed)
2232 {
2233         s32 status;
2234         u32 reg_val;
2235
2236         status = hw->mac.ops.read_iosf_sb_reg(hw,
2237                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2238                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2239         if (status)
2240                 return status;
2241
2242         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2243         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2244                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2245
2246         /* Advertise 10G support. */
2247         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2248                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2249
2250         /* Advertise 1G support. */
2251         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2252                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2253
2254         status = hw->mac.ops.write_iosf_sb_reg(hw,
2255                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2256                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2257
2258         if (hw->mac.type == ixgbe_mac_X550EM_a) {
2259                 /* Set lane mode  to KR auto negotiation */
2260                 status = hw->mac.ops.read_iosf_sb_reg(hw,
2261                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2262                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2263
2264                 if (status)
2265                         return status;
2266
2267                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2268                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2269                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2270                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2271                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2272
2273                 status = hw->mac.ops.write_iosf_sb_reg(hw,
2274                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2275                                     IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2276         }
2277
2278         return ixgbe_restart_an_internal_phy_x550em(hw);
2279 }
2280
2281 /**
2282  * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs
2283  * @hw: pointer to hardware structure
2284  */
2285 static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw)
2286 {
2287         u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
2288         s32 rc;
2289
2290         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2291                 return IXGBE_SUCCESS;
2292
2293         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store);
2294         if (rc)
2295                 return rc;
2296         memset(store, 0, sizeof(store));
2297
2298         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store);
2299         if (rc)
2300                 return rc;
2301
2302         return ixgbe_setup_fw_link(hw);
2303 }
2304
2305 /**
2306  * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp
2307  * @hw: pointer to hardware structure
2308  */
2309 static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw)
2310 {
2311         u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
2312         s32 rc;
2313
2314         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store);
2315         if (rc)
2316                 return rc;
2317
2318         if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) {
2319                 ixgbe_shutdown_fw_phy(hw);
2320                 return IXGBE_ERR_OVERTEMP;
2321         }
2322         return IXGBE_SUCCESS;
2323 }
2324
2325 /**
2326  *  ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2327  *  @hw: pointer to hardware structure
2328  *
2329  *  Read NW_MNG_IF_SEL register and save field values, and check for valid field
2330  *  values.
2331  **/
2332 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2333 {
2334         /* Save NW management interface connected on board. This is used
2335          * to determine internal PHY mode.
2336          */
2337         hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2338
2339         /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2340          * PHY address. This register field was has only been used for X552.
2341          */
2342         if (hw->mac.type == ixgbe_mac_X550EM_a &&
2343             hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2344                 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2345                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2346                                IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2347         }
2348
2349         return IXGBE_SUCCESS;
2350 }
2351
2352 /**
2353  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2354  *  @hw: pointer to hardware structure
2355  *
2356  *  Initialize any function pointers that were not able to be
2357  *  set during init_shared_code because the PHY/SFP type was
2358  *  not known.  Perform the SFP init if necessary.
2359  */
2360 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2361 {
2362         struct ixgbe_phy_info *phy = &hw->phy;
2363         s32 ret_val;
2364
2365         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2366
2367         hw->mac.ops.set_lan_id(hw);
2368         ixgbe_read_mng_if_sel_x550em(hw);
2369
2370         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2371                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2372                 ixgbe_setup_mux_ctl(hw);
2373                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2374         }
2375
2376         switch (hw->device_id) {
2377         case IXGBE_DEV_ID_X550EM_A_1G_T:
2378         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2379                 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2380                 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2381                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2382                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2383                 phy->ops.check_overtemp = ixgbe_check_overtemp_fw;
2384                 if (hw->bus.lan_id)
2385                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2386                 else
2387                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2388
2389                 break;
2390         case IXGBE_DEV_ID_X550EM_A_10G_T:
2391         case IXGBE_DEV_ID_X550EM_A_SFP:
2392                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2393                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2394                 if (hw->bus.lan_id)
2395                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2396                 else
2397                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2398                 break;
2399         case IXGBE_DEV_ID_X550EM_X_SFP:
2400                 /* set up for CS4227 usage */
2401                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2402                 break;
2403         default:
2404                 break;
2405         }
2406
2407         /* Identify the PHY or SFP module */
2408         ret_val = phy->ops.identify(hw);
2409         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED ||
2410             ret_val == IXGBE_ERR_PHY_ADDR_INVALID)
2411                 return ret_val;
2412
2413         /* Setup function pointers based on detected hardware */
2414         ixgbe_init_mac_link_ops_X550em(hw);
2415         if (phy->sfp_type != ixgbe_sfp_type_unknown)
2416                 phy->ops.reset = NULL;
2417
2418         /* Set functions pointers based on phy type */
2419         switch (hw->phy.type) {
2420         case ixgbe_phy_x550em_kx4:
2421                 phy->ops.setup_link = NULL;
2422                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2423                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2424                 break;
2425         case ixgbe_phy_x550em_kr:
2426                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2427                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2428                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2429                 break;
2430         case ixgbe_phy_ext_1g_t:
2431                 /* link is managed by FW */
2432                 phy->ops.setup_link = NULL;
2433                 phy->ops.reset = NULL;
2434                 break;
2435         case ixgbe_phy_x550em_xfi:
2436                 /* link is managed by HW */
2437                 phy->ops.setup_link = NULL;
2438                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2439                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2440                 break;
2441         case ixgbe_phy_x550em_ext_t:
2442                 /* If internal link mode is XFI, then setup iXFI internal link,
2443                  * else setup KR now.
2444                  */
2445                 phy->ops.setup_internal_link =
2446                                               ixgbe_setup_internal_phy_t_x550em;
2447
2448                 /* setup SW LPLU only for first revision of X550EM_x */
2449                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2450                     !(IXGBE_FUSES0_REV_MASK &
2451                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2452                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2453
2454                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2455                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2456                 break;
2457         case ixgbe_phy_sgmii:
2458                 phy->ops.setup_link = NULL;
2459                 break;
2460         case ixgbe_phy_fw:
2461                 phy->ops.setup_link = ixgbe_setup_fw_link;
2462                 phy->ops.reset = ixgbe_reset_phy_fw;
2463                 break;
2464         default:
2465                 break;
2466         }
2467         return ret_val;
2468 }
2469
2470 /**
2471  * ixgbe_set_mdio_speed - Set MDIO clock speed
2472  *  @hw: pointer to hardware structure
2473  */
2474 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2475 {
2476         u32 hlreg0;
2477
2478         switch (hw->device_id) {
2479         case IXGBE_DEV_ID_X550EM_X_10G_T:
2480         case IXGBE_DEV_ID_X550EM_A_SGMII:
2481         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2482         case IXGBE_DEV_ID_X550EM_A_10G_T:
2483         case IXGBE_DEV_ID_X550EM_A_SFP:
2484         case IXGBE_DEV_ID_X550EM_A_QSFP:
2485                 /* Config MDIO clock speed before the first MDIO PHY access */
2486                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2487                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2488                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2489                 break;
2490         case IXGBE_DEV_ID_X550EM_A_1G_T:
2491         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2492                 /* Select fast MDIO clock speed for these devices */
2493                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2494                 hlreg0 |= IXGBE_HLREG0_MDCSPD;
2495                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2496                 break;
2497         default:
2498                 break;
2499         }
2500 }
2501
2502 /**
2503  *  ixgbe_reset_hw_X550em - Perform hardware reset
2504  *  @hw: pointer to hardware structure
2505  *
2506  *  Resets the hardware by resetting the transmit and receive units, masks
2507  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2508  *  reset.
2509  */
2510 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2511 {
2512         ixgbe_link_speed link_speed;
2513         s32 status;
2514         u32 ctrl = 0;
2515         u32 i;
2516         bool link_up = false;
2517         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2518
2519         DEBUGFUNC("ixgbe_reset_hw_X550em");
2520
2521         /* Call adapter stop to disable Tx/Rx and clear interrupts */
2522         status = hw->mac.ops.stop_adapter(hw);
2523         if (status != IXGBE_SUCCESS) {
2524                 DEBUGOUT1("Failed to stop adapter, STATUS = %d\n", status);
2525                 return status;
2526         }
2527         /* flush pending Tx transactions */
2528         ixgbe_clear_tx_pending(hw);
2529
2530         ixgbe_set_mdio_speed(hw);
2531
2532         /* PHY ops must be identified and initialized prior to reset */
2533         status = hw->phy.ops.init(hw);
2534
2535         if (status)
2536                 DEBUGOUT1("Failed to initialize PHY ops, STATUS = %d\n",
2537                           status);
2538
2539         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2540                 DEBUGOUT("Returning from reset HW due to PHY init failure\n");
2541                 return status;
2542         }
2543
2544         /* start the external PHY */
2545         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2546                 status = ixgbe_init_ext_t_x550em(hw);
2547                 if (status) {
2548                         DEBUGOUT1("Failed to start the external PHY, STATUS = %d\n",
2549                                   status);
2550                         return status;
2551                 }
2552         }
2553
2554         /* Setup SFP module if there is one present. */
2555         if (hw->phy.sfp_setup_needed) {
2556                 status = hw->mac.ops.setup_sfp(hw);
2557                 hw->phy.sfp_setup_needed = false;
2558         }
2559
2560         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2561                 return status;
2562
2563         /* Reset PHY */
2564         if (!hw->phy.reset_disable && hw->phy.ops.reset) {
2565                 if (hw->phy.ops.reset(hw) == IXGBE_ERR_OVERTEMP)
2566                         return IXGBE_ERR_OVERTEMP;
2567         }
2568
2569 mac_reset_top:
2570         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2571          * If link reset is used when link is up, it might reset the PHY when
2572          * mng is using it.  If link is down or the flag to force full link
2573          * reset is set, then perform link reset.
2574          */
2575         ctrl = IXGBE_CTRL_LNK_RST;
2576         if (!hw->force_full_reset) {
2577                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2578                 if (link_up)
2579                         ctrl = IXGBE_CTRL_RST;
2580         }
2581
2582         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
2583         if (status != IXGBE_SUCCESS) {
2584                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
2585                         "semaphore failed with %d", status);
2586                 return IXGBE_ERR_SWFW_SYNC;
2587         }
2588         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2589         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2590         IXGBE_WRITE_FLUSH(hw);
2591         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2592
2593         /* Poll for reset bit to self-clear meaning reset is complete */
2594         for (i = 0; i < 10; i++) {
2595                 usec_delay(1);
2596                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2597                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2598                         break;
2599         }
2600
2601         if (ctrl & IXGBE_CTRL_RST_MASK) {
2602                 status = IXGBE_ERR_RESET_FAILED;
2603                 DEBUGOUT("Reset polling failed to complete.\n");
2604         }
2605
2606         msec_delay(50);
2607
2608         /* Double resets are required for recovery from certain error
2609          * conditions.  Between resets, it is necessary to stall to
2610          * allow time for any pending HW events to complete.
2611          */
2612         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2613                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2614                 goto mac_reset_top;
2615         }
2616
2617         /* Store the permanent mac address */
2618         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2619
2620         /* Store MAC address from RAR0, clear receive address registers, and
2621          * clear the multicast table.  Also reset num_rar_entries to 128,
2622          * since we modify this value when programming the SAN MAC address.
2623          */
2624         hw->mac.num_rar_entries = 128;
2625         hw->mac.ops.init_rx_addrs(hw);
2626
2627         ixgbe_set_mdio_speed(hw);
2628
2629         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2630                 ixgbe_setup_mux_ctl(hw);
2631
2632         if (status != IXGBE_SUCCESS)
2633                 DEBUGOUT1("Reset HW failed, STATUS = %d\n", status);
2634
2635         return status;
2636 }
2637
2638 /**
2639  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2640  * @hw: pointer to hardware structure
2641  */
2642 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2643 {
2644         u32 status;
2645         u16 reg;
2646
2647         status = hw->phy.ops.read_reg(hw,
2648                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2649                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2650                                       &reg);
2651
2652         if (status != IXGBE_SUCCESS)
2653                 return status;
2654
2655         /* If PHY FW reset completed bit is set then this is the first
2656          * SW instance after a power on so the PHY FW must be un-stalled.
2657          */
2658         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2659                 status = hw->phy.ops.read_reg(hw,
2660                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2661                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2662                                         &reg);
2663
2664                 if (status != IXGBE_SUCCESS)
2665                         return status;
2666
2667                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2668
2669                 status = hw->phy.ops.write_reg(hw,
2670                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2671                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2672                                         reg);
2673
2674                 if (status != IXGBE_SUCCESS)
2675                         return status;
2676         }
2677
2678         return status;
2679 }
2680
2681 /**
2682  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
2683  *  @hw: pointer to hardware structure
2684  **/
2685 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2686 {
2687         /* leave link alone for 2.5G */
2688         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL)
2689                 return IXGBE_SUCCESS;
2690
2691         if (ixgbe_check_reset_blocked(hw))
2692                 return 0;
2693
2694         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2695 }
2696
2697 /**
2698  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2699  *  @hw: pointer to hardware structure
2700  *
2701  *  Configure the external PHY and the integrated KR PHY for SFP support.
2702  **/
2703 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2704                                     ixgbe_link_speed speed,
2705                                     bool autoneg_wait_to_complete)
2706 {
2707         s32 ret_val;
2708         u16 reg_slice, reg_val;
2709         bool setup_linear = false;
2710         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2711
2712         /* Check if SFP module is supported and linear */
2713         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2714
2715         /* If no SFP module present, then return success. Return success since
2716          * there is no reason to configure CS4227 and SFP not present error is
2717          * not excepted in the setup MAC link flow.
2718          */
2719         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2720                 return IXGBE_SUCCESS;
2721
2722         if (ret_val != IXGBE_SUCCESS)
2723                 return ret_val;
2724
2725         /* Configure internal PHY for KR/KX. */
2726         ixgbe_setup_kr_speed_x550em(hw, speed);
2727
2728         /* Configure CS4227 LINE side to proper mode. */
2729         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2730                     (hw->bus.lan_id << 12);
2731         if (setup_linear)
2732                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2733         else
2734                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2735         ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2736                                           reg_val);
2737         return ret_val;
2738 }
2739
2740 /**
2741  *  ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
2742  *  @hw: pointer to hardware structure
2743  *  @speed: the link speed to force
2744  *
2745  *  Configures the integrated PHY for native SFI mode. Used to connect the
2746  *  internal PHY directly to an SFP cage, without autonegotiation.
2747  **/
2748 STATIC s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2749 {
2750         struct ixgbe_mac_info *mac = &hw->mac;
2751         s32 status;
2752         u32 reg_val;
2753
2754         /* Disable all AN and force speed to 10G Serial. */
2755         status = mac->ops.read_iosf_sb_reg(hw,
2756                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2757                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2758         if (status != IXGBE_SUCCESS)
2759                 return status;
2760
2761         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2762         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2763         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2764         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2765
2766         /* Select forced link speed for internal PHY. */
2767         switch (*speed) {
2768         case IXGBE_LINK_SPEED_10GB_FULL:
2769                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
2770                 break;
2771         case IXGBE_LINK_SPEED_1GB_FULL:
2772                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2773                 break;
2774         default:
2775                 /* Other link speeds are not supported by internal PHY. */
2776                 return IXGBE_ERR_LINK_SETUP;
2777         }
2778
2779         status = mac->ops.write_iosf_sb_reg(hw,
2780                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2781                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2782
2783         /* Toggle port SW reset by AN reset. */
2784         status = ixgbe_restart_an_internal_phy_x550em(hw);
2785
2786         return status;
2787 }
2788
2789 /**
2790  *  ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2791  *  @hw: pointer to hardware structure
2792  *
2793  *  Configure the the integrated PHY for SFP support.
2794  **/
2795 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2796                                     ixgbe_link_speed speed,
2797                                     bool autoneg_wait_to_complete)
2798 {
2799         s32 ret_val;
2800         u16 reg_phy_ext;
2801         bool setup_linear = false;
2802         u32 reg_slice, reg_phy_int, slice_offset;
2803
2804         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2805
2806         /* Check if SFP module is supported and linear */
2807         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2808
2809         /* If no SFP module present, then return success. Return success since
2810          * SFP not present error is not excepted in the setup MAC link flow.
2811          */
2812         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2813                 return IXGBE_SUCCESS;
2814
2815         if (ret_val != IXGBE_SUCCESS)
2816                 return ret_val;
2817
2818         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2819                 /* Configure internal PHY for native SFI based on module type */
2820                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2821                                    IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2822                                    IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_phy_int);
2823
2824                 if (ret_val != IXGBE_SUCCESS)
2825                         return ret_val;
2826
2827                 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
2828                 if (!setup_linear)
2829                         reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
2830
2831                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2832                                    IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2833                                    IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2834
2835                 if (ret_val != IXGBE_SUCCESS)
2836                         return ret_val;
2837
2838                 /* Setup SFI internal link. */
2839                 ret_val = ixgbe_setup_sfi_x550a(hw, &speed);
2840         } else {
2841                 /* Configure internal PHY for KR/KX. */
2842                 ixgbe_setup_kr_speed_x550em(hw, speed);
2843
2844                 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2845                         /* Find Address */
2846                         DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2847                         return IXGBE_ERR_PHY_ADDR_INVALID;
2848                 }
2849
2850                 /* Get external PHY SKU id */
2851                 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,
2852                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2853
2854                 if (ret_val != IXGBE_SUCCESS)
2855                         return ret_val;
2856
2857                 /* When configuring quad port CS4223, the MAC instance is part
2858                  * of the slice offset.
2859                  */
2860                 if (reg_phy_ext == IXGBE_CS4223_SKU_ID)
2861                         slice_offset = (hw->bus.lan_id +
2862                                         (hw->bus.instance_id << 1)) << 12;
2863                 else
2864                         slice_offset = hw->bus.lan_id << 12;
2865
2866                 /* Configure CS4227/CS4223 LINE side to proper mode. */
2867                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2868
2869                 ret_val = hw->phy.ops.read_reg(hw, reg_slice,
2870                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2871
2872                 if (ret_val != IXGBE_SUCCESS)
2873                         return ret_val;
2874
2875                 reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) |
2876                                  (IXGBE_CS4227_EDC_MODE_SR << 1));
2877
2878                 if (setup_linear)
2879                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2880                 else
2881                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2882                 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2883                                          IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2884
2885                 /* Flush previous write with a read */
2886                 ret_val = hw->phy.ops.read_reg(hw, reg_slice,
2887                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2888         }
2889         return ret_val;
2890 }
2891
2892 /**
2893  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2894  *  @hw: pointer to hardware structure
2895  *
2896  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2897  **/
2898 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2899 {
2900         struct ixgbe_mac_info *mac = &hw->mac;
2901         s32 status;
2902         u32 reg_val;
2903
2904         /* Disable training protocol FSM. */
2905         status = mac->ops.read_iosf_sb_reg(hw,
2906                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2907                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2908         if (status != IXGBE_SUCCESS)
2909                 return status;
2910         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2911         status = mac->ops.write_iosf_sb_reg(hw,
2912                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2913                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2914         if (status != IXGBE_SUCCESS)
2915                 return status;
2916
2917         /* Disable Flex from training TXFFE. */
2918         status = mac->ops.read_iosf_sb_reg(hw,
2919                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2920                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2921         if (status != IXGBE_SUCCESS)
2922                 return status;
2923         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2924         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2925         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2926         status = mac->ops.write_iosf_sb_reg(hw,
2927                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2928                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2929         if (status != IXGBE_SUCCESS)
2930                 return status;
2931         status = mac->ops.read_iosf_sb_reg(hw,
2932                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2933                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2934         if (status != IXGBE_SUCCESS)
2935                 return status;
2936         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2937         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2938         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2939         status = mac->ops.write_iosf_sb_reg(hw,
2940                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2941                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2942         if (status != IXGBE_SUCCESS)
2943                 return status;
2944
2945         /* Enable override for coefficients. */
2946         status = mac->ops.read_iosf_sb_reg(hw,
2947                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2948                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2949         if (status != IXGBE_SUCCESS)
2950                 return status;
2951         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2952         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2953         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2954         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2955         status = mac->ops.write_iosf_sb_reg(hw,
2956                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2957                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2958         return status;
2959 }
2960
2961 /**
2962  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2963  *  @hw: pointer to hardware structure
2964  *  @speed: the link speed to force
2965  *
2966  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
2967  *  internal and external PHY at a specific speed, without autonegotiation.
2968  **/
2969 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2970 {
2971         struct ixgbe_mac_info *mac = &hw->mac;
2972         s32 status;
2973         u32 reg_val;
2974
2975         /* iXFI is only supported with X552 */
2976         if (mac->type != ixgbe_mac_X550EM_x)
2977                 return IXGBE_ERR_LINK_SETUP;
2978
2979         /* Disable AN and force speed to 10G Serial. */
2980         status = mac->ops.read_iosf_sb_reg(hw,
2981                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2982                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2983         if (status != IXGBE_SUCCESS)
2984                 return status;
2985
2986         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2987         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2988
2989         /* Select forced link speed for internal PHY. */
2990         switch (*speed) {
2991         case IXGBE_LINK_SPEED_10GB_FULL:
2992                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2993                 break;
2994         case IXGBE_LINK_SPEED_1GB_FULL:
2995                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2996                 break;
2997         default:
2998                 /* Other link speeds are not supported by internal KR PHY. */
2999                 return IXGBE_ERR_LINK_SETUP;
3000         }
3001
3002         status = mac->ops.write_iosf_sb_reg(hw,
3003                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3004                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3005         if (status != IXGBE_SUCCESS)
3006                 return status;
3007
3008         /* Additional configuration needed for x550em_x */
3009         if (hw->mac.type == ixgbe_mac_X550EM_x) {
3010                 status = ixgbe_setup_ixfi_x550em_x(hw);
3011                 if (status != IXGBE_SUCCESS)
3012                         return status;
3013         }
3014
3015         /* Toggle port SW reset by AN reset. */
3016         status = ixgbe_restart_an_internal_phy_x550em(hw);
3017
3018         return status;
3019 }
3020
3021 /**
3022  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
3023  * @hw: address of hardware structure
3024  * @link_up: address of boolean to indicate link status
3025  *
3026  * Returns error code if unable to get link status.
3027  */
3028 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
3029 {
3030         u32 ret;
3031         u16 autoneg_status;
3032
3033         *link_up = false;
3034
3035         /* read this twice back to back to indicate current status */
3036         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3037                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3038                                    &autoneg_status);
3039         if (ret != IXGBE_SUCCESS)
3040                 return ret;
3041
3042         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3043                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3044                                    &autoneg_status);
3045         if (ret != IXGBE_SUCCESS)
3046                 return ret;
3047
3048         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
3049
3050         return IXGBE_SUCCESS;
3051 }
3052
3053 /**
3054  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
3055  * @hw: point to hardware structure
3056  *
3057  * Configures the link between the integrated KR PHY and the external X557 PHY
3058  * The driver will call this function when it gets a link status change
3059  * interrupt from the X557 PHY. This function configures the link speed
3060  * between the PHYs to match the link speed of the BASE-T link.
3061  *
3062  * A return of a non-zero value indicates an error, and the base driver should
3063  * not report link up.
3064  */
3065 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
3066 {
3067         ixgbe_link_speed force_speed;
3068         bool link_up;
3069         u32 status;
3070         u16 speed;
3071
3072         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3073                 return IXGBE_ERR_CONFIG;
3074
3075         if (hw->mac.type == ixgbe_mac_X550EM_x &&
3076             !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3077                 /* If link is down, there is no setup necessary so return  */
3078                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3079                 if (status != IXGBE_SUCCESS)
3080                         return status;
3081
3082                 if (!link_up)
3083                         return IXGBE_SUCCESS;
3084
3085                 status = hw->phy.ops.read_reg(hw,
3086                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3087                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3088                                               &speed);
3089                 if (status != IXGBE_SUCCESS)
3090                         return status;
3091
3092                 /* If link is still down - no setup is required so return */
3093                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3094                 if (status != IXGBE_SUCCESS)
3095                         return status;
3096                 if (!link_up)
3097                         return IXGBE_SUCCESS;
3098
3099                 /* clear everything but the speed and duplex bits */
3100                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
3101
3102                 switch (speed) {
3103                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
3104                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3105                         break;
3106                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
3107                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3108                         break;
3109                 default:
3110                         /* Internal PHY does not support anything else */
3111                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
3112                 }
3113
3114                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
3115         } else {
3116                 speed = IXGBE_LINK_SPEED_10GB_FULL |
3117                         IXGBE_LINK_SPEED_1GB_FULL;
3118                 return ixgbe_setup_kr_speed_x550em(hw, speed);
3119         }
3120 }
3121
3122 /**
3123  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
3124  *  @hw: pointer to hardware structure
3125  *
3126  *  Configures the integrated KR PHY to use internal loopback mode.
3127  **/
3128 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
3129 {
3130         s32 status;
3131         u32 reg_val;
3132
3133         /* Disable AN and force speed to 10G Serial. */
3134         status = hw->mac.ops.read_iosf_sb_reg(hw,
3135                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3136                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3137         if (status != IXGBE_SUCCESS)
3138                 return status;
3139         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3140         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3141         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3142         status = hw->mac.ops.write_iosf_sb_reg(hw,
3143                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3144                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3145         if (status != IXGBE_SUCCESS)
3146                 return status;
3147
3148         /* Set near-end loopback clocks. */
3149         status = hw->mac.ops.read_iosf_sb_reg(hw,
3150                                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3151                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3152         if (status != IXGBE_SUCCESS)
3153                 return status;
3154         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3155         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3156         status = hw->mac.ops.write_iosf_sb_reg(hw,
3157                                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3158                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3159         if (status != IXGBE_SUCCESS)
3160                 return status;
3161
3162         /* Set loopback enable. */
3163         status = hw->mac.ops.read_iosf_sb_reg(hw,
3164                                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3165                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3166         if (status != IXGBE_SUCCESS)
3167                 return status;
3168         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3169         status = hw->mac.ops.write_iosf_sb_reg(hw,
3170                                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3171                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3172         if (status != IXGBE_SUCCESS)
3173                 return status;
3174
3175         /* Training bypass. */
3176         status = hw->mac.ops.read_iosf_sb_reg(hw,
3177                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3178                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3179         if (status != IXGBE_SUCCESS)
3180                 return status;
3181         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3182         status = hw->mac.ops.write_iosf_sb_reg(hw,
3183                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3184                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3185
3186         return status;
3187 }
3188
3189 /**
3190  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3191  *  assuming that the semaphore is already obtained.
3192  *  @hw: pointer to hardware structure
3193  *  @offset: offset of  word in the EEPROM to read
3194  *  @data: word read from the EEPROM
3195  *
3196  *  Reads a 16 bit word from the EEPROM using the hostif.
3197  **/
3198 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
3199 {
3200         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3201         struct ixgbe_hic_read_shadow_ram buffer;
3202         s32 status;
3203
3204         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3205         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3206         buffer.hdr.req.buf_lenh = 0;
3207         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3208         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3209
3210         /* convert offset from words to bytes */
3211         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3212         /* one word */
3213         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3214
3215         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3216         if (status)
3217                 return status;
3218
3219         status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3220                                     IXGBE_HI_COMMAND_TIMEOUT);
3221         if (!status) {
3222                 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3223                                                   FW_NVM_DATA_OFFSET);
3224         }
3225
3226         hw->mac.ops.release_swfw_sync(hw, mask);
3227         return status;
3228 }
3229
3230 /**
3231  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3232  *  @hw: pointer to hardware structure
3233  *  @offset: offset of  word in the EEPROM to read
3234  *  @words: number of words
3235  *  @data: word(s) read from the EEPROM
3236  *
3237  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
3238  **/
3239 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3240                                      u16 offset, u16 words, u16 *data)
3241 {
3242         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3243         struct ixgbe_hic_read_shadow_ram buffer;
3244         u32 current_word = 0;
3245         u16 words_to_read;
3246         s32 status;
3247         u32 i;
3248
3249         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3250
3251         /* Take semaphore for the entire operation. */
3252         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3253         if (status) {
3254                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3255                 return status;
3256         }
3257
3258         while (words) {
3259                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3260                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3261                 else
3262                         words_to_read = words;
3263
3264                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3265                 buffer.hdr.req.buf_lenh = 0;
3266                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3267                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3268
3269                 /* convert offset from words to bytes */
3270                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3271                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3272
3273                 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3274                                             IXGBE_HI_COMMAND_TIMEOUT);
3275
3276                 if (status) {
3277                         DEBUGOUT("Host interface command failed\n");
3278                         goto out;
3279                 }
3280
3281                 for (i = 0; i < words_to_read; i++) {
3282                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3283                                   2 * i;
3284                         u32 value = IXGBE_READ_REG(hw, reg);
3285
3286                         data[current_word] = (u16)(value & 0xffff);
3287                         current_word++;
3288                         i++;
3289                         if (i < words_to_read) {
3290                                 value >>= 16;
3291                                 data[current_word] = (u16)(value & 0xffff);
3292                                 current_word++;
3293                         }
3294                 }
3295                 words -= words_to_read;
3296         }
3297
3298 out:
3299         hw->mac.ops.release_swfw_sync(hw, mask);
3300         return status;
3301 }
3302
3303 /**
3304  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3305  *  @hw: pointer to hardware structure
3306  *  @offset: offset of  word in the EEPROM to write
3307  *  @data: word write to the EEPROM
3308  *
3309  *  Write a 16 bit word to the EEPROM using the hostif.
3310  **/
3311 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3312                                     u16 data)
3313 {
3314         s32 status;
3315         struct ixgbe_hic_write_shadow_ram buffer;
3316
3317         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3318
3319         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3320         buffer.hdr.req.buf_lenh = 0;
3321         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3322         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3323
3324          /* one word */
3325         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3326         buffer.data = data;
3327         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3328
3329         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3330                                               sizeof(buffer),
3331                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3332
3333         return status;
3334 }
3335
3336 /**
3337  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3338  *  @hw: pointer to hardware structure
3339  *  @offset: offset of  word in the EEPROM to write
3340  *  @data: word write to the EEPROM
3341  *
3342  *  Write a 16 bit word to the EEPROM using the hostif.
3343  **/
3344 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3345                                u16 data)
3346 {
3347         s32 status = IXGBE_SUCCESS;
3348
3349         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3350
3351         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3352             IXGBE_SUCCESS) {
3353                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3354                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3355         } else {
3356                 DEBUGOUT("write ee hostif failed to get semaphore");
3357                 status = IXGBE_ERR_SWFW_SYNC;
3358         }
3359
3360         return status;
3361 }
3362
3363 /**
3364  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3365  *  @hw: pointer to hardware structure
3366  *  @offset: offset of  word in the EEPROM to write
3367  *  @words: number of words
3368  *  @data: word(s) write to the EEPROM
3369  *
3370  *  Write a 16 bit word(s) to the EEPROM using the hostif.
3371  **/
3372 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3373                                       u16 offset, u16 words, u16 *data)
3374 {
3375         s32 status = IXGBE_SUCCESS;
3376         u32 i = 0;
3377
3378         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3379
3380         /* Take semaphore for the entire operation. */
3381         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3382         if (status != IXGBE_SUCCESS) {
3383                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3384                 goto out;
3385         }
3386
3387         for (i = 0; i < words; i++) {
3388                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3389                                                          data[i]);
3390
3391                 if (status != IXGBE_SUCCESS) {
3392                         DEBUGOUT("Eeprom buffered write failed\n");
3393                         break;
3394                 }
3395         }
3396
3397         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3398 out:
3399
3400         return status;
3401 }
3402
3403 /**
3404  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3405  * @hw: pointer to hardware structure
3406  * @ptr: pointer offset in eeprom
3407  * @size: size of section pointed by ptr, if 0 first word will be used as size
3408  * @csum: address of checksum to update
3409  *
3410  * Returns error status for any failure
3411  */
3412 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3413                                    u16 size, u16 *csum, u16 *buffer,
3414                                    u32 buffer_size)
3415 {
3416         u16 buf[256];
3417         s32 status;
3418         u16 length, bufsz, i, start;
3419         u16 *local_buffer;
3420
3421         bufsz = sizeof(buf) / sizeof(buf[0]);
3422
3423         /* Read a chunk at the pointer location */
3424         if (!buffer) {
3425                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3426                 if (status) {
3427                         DEBUGOUT("Failed to read EEPROM image\n");
3428                         return status;
3429                 }
3430                 local_buffer = buf;
3431         } else {
3432                 if (buffer_size < ptr)
3433                         return  IXGBE_ERR_PARAM;
3434                 local_buffer = &buffer[ptr];
3435         }
3436
3437         if (size) {
3438                 start = 0;
3439                 length = size;
3440         } else {
3441                 start = 1;
3442                 length = local_buffer[0];
3443
3444                 /* Skip pointer section if length is invalid. */
3445                 if (length == 0xFFFF || length == 0 ||
3446                     (ptr + length) >= hw->eeprom.word_size)
3447                         return IXGBE_SUCCESS;
3448         }
3449
3450         if (buffer && ((u32)start + (u32)length > buffer_size))
3451                 return IXGBE_ERR_PARAM;
3452
3453         for (i = start; length; i++, length--) {
3454                 if (i == bufsz && !buffer) {
3455                         ptr += bufsz;
3456                         i = 0;
3457                         if (length < bufsz)
3458                                 bufsz = length;
3459
3460                         /* Read a chunk at the pointer location */
3461                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3462                                                                   bufsz, buf);
3463                         if (status) {
3464                                 DEBUGOUT("Failed to read EEPROM image\n");
3465                                 return status;
3466                         }
3467                 }
3468                 *csum += local_buffer[i];
3469         }
3470         return IXGBE_SUCCESS;
3471 }
3472
3473 /**
3474  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3475  *  @hw: pointer to hardware structure
3476  *  @buffer: pointer to buffer containing calculated checksum
3477  *  @buffer_size: size of buffer
3478  *
3479  *  Returns a negative error code on error, or the 16-bit checksum
3480  **/
3481 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3482 {
3483         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3484         u16 *local_buffer;
3485         s32 status;
3486         u16 checksum = 0;
3487         u16 pointer, i, size;
3488
3489         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3490
3491         hw->eeprom.ops.init_params(hw);
3492
3493         if (!buffer) {
3494                 /* Read pointer area */
3495                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3496                                                      IXGBE_EEPROM_LAST_WORD + 1,
3497                                                      eeprom_ptrs);
3498                 if (status) {
3499                         DEBUGOUT("Failed to read EEPROM image\n");
3500                         return status;
3501                 }
3502                 local_buffer = eeprom_ptrs;
3503         } else {
3504                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3505                         return IXGBE_ERR_PARAM;
3506                 local_buffer = buffer;
3507         }
3508
3509         /*
3510          * For X550 hardware include 0x0-0x41 in the checksum, skip the
3511          * checksum word itself
3512          */
3513         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3514                 if (i != IXGBE_EEPROM_CHECKSUM)
3515                         checksum += local_buffer[i];
3516
3517         /*
3518          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
3519          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3520          */
3521         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3522                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3523                         continue;
3524
3525                 pointer = local_buffer[i];
3526
3527                 /* Skip pointer section if the pointer is invalid. */
3528                 if (pointer == 0xFFFF || pointer == 0 ||
3529                     pointer >= hw->eeprom.word_size)
3530                         continue;
3531
3532                 switch (i) {
3533                 case IXGBE_PCIE_GENERAL_PTR:
3534                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3535                         break;
3536                 case IXGBE_PCIE_CONFIG0_PTR:
3537                 case IXGBE_PCIE_CONFIG1_PTR:
3538                         size = IXGBE_PCIE_CONFIG_SIZE;
3539                         break;
3540                 default:
3541                         size = 0;
3542                         break;
3543                 }
3544
3545                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3546                                                 buffer, buffer_size);
3547                 if (status)
3548                         return status;
3549         }
3550
3551         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3552
3553         return (s32)checksum;
3554 }
3555
3556 /**
3557  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3558  *  @hw: pointer to hardware structure
3559  *
3560  *  Returns a negative error code on error, or the 16-bit checksum
3561  **/
3562 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3563 {
3564         return ixgbe_calc_checksum_X550(hw, NULL, 0);
3565 }
3566
3567 /**
3568  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3569  *  @hw: pointer to hardware structure
3570  *  @checksum_val: calculated checksum
3571  *
3572  *  Performs checksum calculation and validates the EEPROM checksum.  If the
3573  *  caller does not need checksum_val, the value can be NULL.
3574  **/
3575 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3576 {
3577         s32 status;
3578         u16 checksum;
3579         u16 read_checksum = 0;
3580
3581         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3582
3583         /* Read the first word from the EEPROM. If this times out or fails, do
3584          * not continue or we could be in for a very long wait while every
3585          * EEPROM read fails
3586          */
3587         status = hw->eeprom.ops.read(hw, 0, &checksum);
3588         if (status) {
3589                 DEBUGOUT("EEPROM read failed\n");
3590                 return status;
3591         }
3592
3593         status = hw->eeprom.ops.calc_checksum(hw);
3594         if (status < 0)
3595                 return status;
3596
3597         checksum = (u16)(status & 0xffff);
3598
3599         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3600                                            &read_checksum);
3601         if (status)
3602                 return status;
3603
3604         /* Verify read checksum from EEPROM is the same as
3605          * calculated checksum
3606          */
3607         if (read_checksum != checksum) {
3608                 status = IXGBE_ERR_EEPROM_CHECKSUM;
3609                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3610                              "Invalid EEPROM checksum");
3611         }
3612
3613         /* If the user cares, return the calculated checksum */
3614         if (checksum_val)
3615                 *checksum_val = checksum;
3616
3617         return status;
3618 }
3619
3620 /**
3621  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3622  * @hw: pointer to hardware structure
3623  *
3624  * After writing EEPROM to shadow RAM using EEWR register, software calculates
3625  * checksum and updates the EEPROM and instructs the hardware to update
3626  * the flash.
3627  **/
3628 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3629 {
3630         s32 status;
3631         u16 checksum = 0;
3632
3633         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3634
3635         /* Read the first word from the EEPROM. If this times out or fails, do
3636          * not continue or we could be in for a very long wait while every
3637          * EEPROM read fails
3638          */
3639         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3640         if (status) {
3641                 DEBUGOUT("EEPROM read failed\n");
3642                 return status;
3643         }
3644
3645         status = ixgbe_calc_eeprom_checksum_X550(hw);
3646         if (status < 0)
3647                 return status;
3648
3649         checksum = (u16)(status & 0xffff);
3650
3651         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3652                                             checksum);
3653         if (status)
3654                 return status;
3655
3656         status = ixgbe_update_flash_X550(hw);
3657
3658         return status;
3659 }
3660
3661 /**
3662  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3663  *  @hw: pointer to hardware structure
3664  *
3665  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3666  **/
3667 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3668 {
3669         s32 status = IXGBE_SUCCESS;
3670         union ixgbe_hic_hdr2 buffer;
3671
3672         DEBUGFUNC("ixgbe_update_flash_X550");
3673
3674         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3675         buffer.req.buf_lenh = 0;
3676         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3677         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3678
3679         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3680                                               sizeof(buffer),
3681                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3682
3683         return status;
3684 }
3685
3686 /**
3687  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3688  *  @hw: pointer to hardware structure
3689  *
3690  *  Determines physical layer capabilities of the current configuration.
3691  **/
3692 u64 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3693 {
3694         u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3695         u16 ext_ability = 0;
3696
3697         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3698
3699         hw->phy.ops.identify(hw);
3700
3701         switch (hw->phy.type) {
3702         case ixgbe_phy_x550em_kr:
3703                 if (hw->mac.type == ixgbe_mac_X550EM_a) {
3704                         if (hw->phy.nw_mng_if_sel &
3705                             IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
3706                                 physical_layer =
3707                                         IXGBE_PHYSICAL_LAYER_2500BASE_KX;
3708                                 break;
3709                         } else if (hw->device_id ==
3710                                    IXGBE_DEV_ID_X550EM_A_KR_L) {
3711                                 physical_layer =
3712                                         IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3713                                 break;
3714                         }
3715                 }
3716                 /* fall through */
3717         case ixgbe_phy_x550em_xfi:
3718                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3719                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3720                 break;
3721         case ixgbe_phy_x550em_kx4:
3722                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3723                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3724                 break;
3725         case ixgbe_phy_x550em_ext_t:
3726                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3727                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3728                                      &ext_ability);
3729                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3730                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3731                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3732                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3733                 break;
3734         case ixgbe_phy_fw:
3735                 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_1GB_FULL)
3736                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3737                 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_100_FULL)
3738                         physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
3739                 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_10_FULL)
3740                         physical_layer |= IXGBE_PHYSICAL_LAYER_10BASE_T;
3741                 break;
3742         case ixgbe_phy_sgmii:
3743                 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3744                 break;
3745         case ixgbe_phy_ext_1g_t:
3746                 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3747                 break;
3748         default:
3749                 break;
3750         }
3751
3752         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3753                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3754
3755         return physical_layer;
3756 }
3757
3758 /**
3759  * ixgbe_get_bus_info_x550em - Set PCI bus info
3760  * @hw: pointer to hardware structure
3761  *
3762  * Sets bus link width and speed to unknown because X550em is
3763  * not a PCI device.
3764  **/
3765 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3766 {
3767
3768         DEBUGFUNC("ixgbe_get_bus_info_x550em");
3769
3770         hw->bus.width = ixgbe_bus_width_unknown;
3771         hw->bus.speed = ixgbe_bus_speed_unknown;
3772
3773         hw->mac.ops.set_lan_id(hw);
3774
3775         return IXGBE_SUCCESS;
3776 }
3777
3778 /**
3779  * ixgbe_disable_rx_x550 - Disable RX unit
3780  *
3781  * Enables the Rx DMA unit for x550
3782  **/
3783 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3784 {
3785         u32 rxctrl, pfdtxgswc;
3786         s32 status;
3787         struct ixgbe_hic_disable_rxen fw_cmd;
3788
3789         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3790
3791         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3792         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3793                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3794                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3795                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3796                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3797                         hw->mac.set_lben = true;
3798                 } else {
3799                         hw->mac.set_lben = false;
3800                 }
3801
3802                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3803                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3804                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3805                 fw_cmd.port_number = (u8)hw->bus.lan_id;
3806
3807                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3808                                         sizeof(struct ixgbe_hic_disable_rxen),
3809                                         IXGBE_HI_COMMAND_TIMEOUT, true);
3810
3811                 /* If we fail - disable RX using register write */
3812                 if (status) {
3813                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3814                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3815                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3816                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3817                         }
3818                 }
3819         }
3820 }
3821
3822 /**
3823  * ixgbe_enter_lplu_x550em - Transition to low power states
3824  *  @hw: pointer to hardware structure
3825  *
3826  * Configures Low Power Link Up on transition to low power states
3827  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3828  * X557 PHY immediately prior to entering LPLU.
3829  **/
3830 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3831 {
3832         u16 an_10g_cntl_reg, autoneg_reg, speed;
3833         s32 status;
3834         ixgbe_link_speed lcd_speed;
3835         u32 save_autoneg;
3836         bool link_up;
3837
3838         /* SW LPLU not required on later HW revisions. */
3839         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3840             (IXGBE_FUSES0_REV_MASK &
3841              IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3842                 return IXGBE_SUCCESS;
3843
3844         /* If blocked by MNG FW, then don't restart AN */
3845         if (ixgbe_check_reset_blocked(hw))
3846                 return IXGBE_SUCCESS;
3847
3848         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3849         if (status != IXGBE_SUCCESS)
3850                 return status;
3851
3852         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3853
3854         if (status != IXGBE_SUCCESS)
3855                 return status;
3856
3857         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3858          * disabled, then force link down by entering low power mode.
3859          */
3860         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3861             !(hw->wol_enabled || ixgbe_mng_present(hw)))
3862                 return ixgbe_set_copper_phy_power(hw, FALSE);
3863
3864         /* Determine LCD */
3865         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3866
3867         if (status != IXGBE_SUCCESS)
3868                 return status;
3869
3870         /* If no valid LCD link speed, then force link down and exit. */
3871         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3872                 return ixgbe_set_copper_phy_power(hw, FALSE);
3873
3874         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3875                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3876                                       &speed);
3877
3878         if (status != IXGBE_SUCCESS)
3879                 return status;
3880
3881         /* If no link now, speed is invalid so take link down */
3882         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3883         if (status != IXGBE_SUCCESS)
3884                 return ixgbe_set_copper_phy_power(hw, false);
3885
3886         /* clear everything but the speed bits */
3887         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3888
3889         /* If current speed is already LCD, then exit. */
3890         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3891              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3892             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3893              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3894                 return status;
3895
3896         /* Clear AN completed indication */
3897         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3898                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3899                                       &autoneg_reg);
3900
3901         if (status != IXGBE_SUCCESS)
3902                 return status;
3903
3904         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3905                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3906                              &an_10g_cntl_reg);
3907
3908         if (status != IXGBE_SUCCESS)
3909                 return status;
3910
3911         status = hw->phy.ops.read_reg(hw,
3912                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3913                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3914                              &autoneg_reg);
3915
3916         if (status != IXGBE_SUCCESS)
3917                 return status;
3918
3919         save_autoneg = hw->phy.autoneg_advertised;
3920
3921         /* Setup link at least common link speed */
3922         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3923
3924         /* restore autoneg from before setting lplu speed */
3925         hw->phy.autoneg_advertised = save_autoneg;
3926
3927         return status;
3928 }
3929
3930 /**
3931  * ixgbe_get_lcd_x550em - Determine lowest common denominator
3932  *  @hw: pointer to hardware structure
3933  *  @lcd_speed: pointer to lowest common link speed
3934  *
3935  * Determine lowest common link speed with link partner.
3936  **/
3937 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3938 {
3939         u16 an_lp_status;
3940         s32 status;
3941         u16 word = hw->eeprom.ctrl_word_3;
3942
3943         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3944
3945         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3946                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3947                                       &an_lp_status);
3948
3949         if (status != IXGBE_SUCCESS)
3950                 return status;
3951
3952         /* If link partner advertised 1G, return 1G */
3953         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3954                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3955                 return status;
3956         }
3957
3958         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3959         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3960             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3961                 return status;
3962
3963         /* Link partner not capable of lower speeds, return 10G */
3964         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3965         return status;
3966 }
3967
3968 /**
3969  *  ixgbe_setup_fc_X550em - Set up flow control
3970  *  @hw: pointer to hardware structure
3971  *
3972  *  Called at init time to set up flow control.
3973  **/
3974 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3975 {
3976         s32 ret_val = IXGBE_SUCCESS;
3977         u32 pause, asm_dir, reg_val;
3978
3979         DEBUGFUNC("ixgbe_setup_fc_X550em");
3980
3981         /* Validate the requested mode */
3982         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3983                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3984                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3985                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3986                 goto out;
3987         }
3988
3989         /* 10gig parts do not have a word in the EEPROM to determine the
3990          * default flow control setting, so we explicitly set it to full.
3991          */
3992         if (hw->fc.requested_mode == ixgbe_fc_default)
3993                 hw->fc.requested_mode = ixgbe_fc_full;
3994
3995         /* Determine PAUSE and ASM_DIR bits. */
3996         switch (hw->fc.requested_mode) {
3997         case ixgbe_fc_none:
3998                 pause = 0;
3999                 asm_dir = 0;
4000                 break;
4001         case ixgbe_fc_tx_pause:
4002                 pause = 0;
4003                 asm_dir = 1;
4004                 break;
4005         case ixgbe_fc_rx_pause:
4006                 /* Rx Flow control is enabled and Tx Flow control is
4007                  * disabled by software override. Since there really
4008                  * isn't a way to advertise that we are capable of RX
4009                  * Pause ONLY, we will advertise that we support both
4010                  * symmetric and asymmetric Rx PAUSE, as such we fall
4011                  * through to the fc_full statement.  Later, we will
4012                  * disable the adapter's ability to send PAUSE frames.
4013                  */
4014         case ixgbe_fc_full:
4015                 pause = 1;
4016                 asm_dir = 1;
4017                 break;
4018         default:
4019                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4020                         "Flow control param set incorrectly\n");
4021                 ret_val = IXGBE_ERR_CONFIG;
4022                 goto out;
4023         }
4024
4025         switch (hw->device_id) {
4026         case IXGBE_DEV_ID_X550EM_X_KR:
4027         case IXGBE_DEV_ID_X550EM_A_KR:
4028         case IXGBE_DEV_ID_X550EM_A_KR_L:
4029                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
4030                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4031                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
4032                 if (ret_val != IXGBE_SUCCESS)
4033                         goto out;
4034                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4035                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4036                 if (pause)
4037                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4038                 if (asm_dir)
4039                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4040                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
4041                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4042                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
4043
4044                 /* This device does not fully support AN. */
4045                 hw->fc.disable_fc_autoneg = true;
4046                 break;
4047         case IXGBE_DEV_ID_X550EM_X_XFI:
4048                 hw->fc.disable_fc_autoneg = true;
4049                 break;
4050         default:
4051                 break;
4052         }
4053
4054 out:
4055         return ret_val;
4056 }
4057
4058 /**
4059  *  ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
4060  *  @hw: pointer to hardware structure
4061  *
4062  *  Enable flow control according to IEEE clause 37.
4063  **/
4064 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
4065 {
4066         u32 link_s1, lp_an_page_low, an_cntl_1;
4067         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4068         ixgbe_link_speed speed;
4069         bool link_up;
4070
4071         /* AN should have completed when the cable was plugged in.
4072          * Look for reasons to bail out.  Bail out if:
4073          * - FC autoneg is disabled, or if
4074          * - link is not up.
4075          */
4076         if (hw->fc.disable_fc_autoneg) {
4077                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4078                              "Flow control autoneg is disabled");
4079                 goto out;
4080         }
4081
4082         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4083         if (!link_up) {
4084                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4085                 goto out;
4086         }
4087
4088         /* Check at auto-negotiation has completed */
4089         status = hw->mac.ops.read_iosf_sb_reg(hw,
4090                                         IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4091                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4092
4093         if (status != IXGBE_SUCCESS ||
4094             (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4095                 DEBUGOUT("Auto-Negotiation did not complete\n");
4096                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4097                 goto out;
4098         }
4099
4100         /* Read the 10g AN autoc and LP ability registers and resolve
4101          * local flow control settings accordingly
4102          */
4103         status = hw->mac.ops.read_iosf_sb_reg(hw,
4104                                 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4105                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
4106
4107         if (status != IXGBE_SUCCESS) {
4108                 DEBUGOUT("Auto-Negotiation did not complete\n");
4109                 goto out;
4110         }
4111
4112         status = hw->mac.ops.read_iosf_sb_reg(hw,
4113                                 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
4114                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
4115
4116         if (status != IXGBE_SUCCESS) {
4117                 DEBUGOUT("Auto-Negotiation did not complete\n");
4118                 goto out;
4119         }
4120
4121         status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
4122                                     IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
4123                                     IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
4124                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
4125                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
4126
4127 out:
4128         if (status == IXGBE_SUCCESS) {
4129                 hw->fc.fc_was_autonegged = true;
4130         } else {
4131                 hw->fc.fc_was_autonegged = false;
4132                 hw->fc.current_mode = hw->fc.requested_mode;
4133         }
4134 }
4135
4136 /**
4137  *  ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
4138  *  @hw: pointer to hardware structure
4139  *
4140  **/
4141 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
4142 {
4143         hw->fc.fc_was_autonegged = false;
4144         hw->fc.current_mode = hw->fc.requested_mode;
4145 }
4146
4147 /**
4148  *  ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
4149  *  @hw: pointer to hardware structure
4150  *
4151  *  Enable flow control according to IEEE clause 37.
4152  **/
4153 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
4154 {
4155         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4156         u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
4157         ixgbe_link_speed speed;
4158         bool link_up;
4159
4160         /* AN should have completed when the cable was plugged in.
4161          * Look for reasons to bail out.  Bail out if:
4162          * - FC autoneg is disabled, or if
4163          * - link is not up.
4164          */
4165         if (hw->fc.disable_fc_autoneg) {
4166                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4167                              "Flow control autoneg is disabled");
4168                 goto out;
4169         }
4170
4171         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4172         if (!link_up) {
4173                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4174                 goto out;
4175         }
4176
4177         /* Check if auto-negotiation has completed */
4178         status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info);
4179         if (status != IXGBE_SUCCESS ||
4180             !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) {
4181                 DEBUGOUT("Auto-Negotiation did not complete\n");
4182                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4183                 goto out;
4184         }
4185
4186         /* Negotiate the flow control */
4187         status = ixgbe_negotiate_fc(hw, info[0], info[0],
4188                                     FW_PHY_ACT_GET_LINK_INFO_FC_RX,
4189                                     FW_PHY_ACT_GET_LINK_INFO_FC_TX,
4190                                     FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX,
4191                                     FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX);
4192
4193 out:
4194         if (status == IXGBE_SUCCESS) {
4195                 hw->fc.fc_was_autonegged = true;
4196         } else {
4197                 hw->fc.fc_was_autonegged = false;
4198                 hw->fc.current_mode = hw->fc.requested_mode;
4199         }
4200 }
4201
4202 /**
4203  *  ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4204  *  @hw: pointer to hardware structure
4205  *
4206  *  Called at init time to set up flow control.
4207  **/
4208 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4209 {
4210         s32 status = IXGBE_SUCCESS;
4211         u32 an_cntl = 0;
4212
4213         DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4214
4215         /* Validate the requested mode */
4216         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4217                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4218                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4219                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4220         }
4221
4222         if (hw->fc.requested_mode == ixgbe_fc_default)
4223                 hw->fc.requested_mode = ixgbe_fc_full;
4224
4225         /* Set up the 1G and 10G flow control advertisement registers so the
4226          * HW will be able to do FC autoneg once the cable is plugged in.  If
4227          * we link at 10G, the 1G advertisement is harmless and vice versa.
4228          */
4229         status = hw->mac.ops.read_iosf_sb_reg(hw,
4230                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4231                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4232
4233         if (status != IXGBE_SUCCESS) {
4234                 DEBUGOUT("Auto-Negotiation did not complete\n");
4235                 return status;
4236         }
4237
4238         /* The possible values of fc.requested_mode are:
4239          * 0: Flow control is completely disabled
4240          * 1: Rx flow control is enabled (we can receive pause frames,
4241          *    but not send pause frames).
4242          * 2: Tx flow control is enabled (we can send pause frames but
4243          *    we do not support receiving pause frames).
4244          * 3: Both Rx and Tx flow control (symmetric) are enabled.
4245          * other: Invalid.
4246          */
4247         switch (hw->fc.requested_mode) {
4248         case ixgbe_fc_none:
4249                 /* Flow control completely disabled by software override. */
4250                 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4251                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4252                 break;
4253         case ixgbe_fc_tx_pause:
4254                 /* Tx Flow control is enabled, and Rx Flow control is
4255                  * disabled by software override.
4256                  */
4257                 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4258                 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4259                 break;
4260         case ixgbe_fc_rx_pause:
4261                 /* Rx Flow control is enabled and Tx Flow control is
4262                  * disabled by software override. Since there really
4263                  * isn't a way to advertise that we are capable of RX
4264                  * Pause ONLY, we will advertise that we support both
4265                  * symmetric and asymmetric Rx PAUSE, as such we fall
4266                  * through to the fc_full statement.  Later, we will
4267                  * disable the adapter's ability to send PAUSE frames.
4268                  */
4269         case ixgbe_fc_full:
4270                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4271                 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4272                            IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4273                 break;
4274         default:
4275                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4276                               "Flow control param set incorrectly\n");
4277                 return IXGBE_ERR_CONFIG;
4278         }
4279
4280         status = hw->mac.ops.write_iosf_sb_reg(hw,
4281                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4282                                         IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4283
4284         /* Restart auto-negotiation. */
4285         status = ixgbe_restart_an_internal_phy_x550em(hw);
4286
4287         return status;
4288 }
4289
4290 /**
4291  * ixgbe_set_mux - Set mux for port 1 access with CS4227
4292  * @hw: pointer to hardware structure
4293  * @state: set mux if 1, clear if 0
4294  */
4295 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4296 {
4297         u32 esdp;
4298
4299         if (!hw->bus.lan_id)
4300                 return;
4301         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4302         if (state)
4303                 esdp |= IXGBE_ESDP_SDP1;
4304         else
4305                 esdp &= ~IXGBE_ESDP_SDP1;
4306         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4307         IXGBE_WRITE_FLUSH(hw);
4308 }
4309
4310 /**
4311  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4312  *  @hw: pointer to hardware structure
4313  *  @mask: Mask to specify which semaphore to acquire
4314  *
4315  *  Acquires the SWFW semaphore and sets the I2C MUX
4316  **/
4317 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4318 {
4319         s32 status;
4320
4321         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4322
4323         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4324         if (status)
4325                 return status;
4326
4327         if (mask & IXGBE_GSSR_I2C_MASK)
4328                 ixgbe_set_mux(hw, 1);
4329
4330         return IXGBE_SUCCESS;
4331 }
4332
4333 /**
4334  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4335  *  @hw: pointer to hardware structure
4336  *  @mask: Mask to specify which semaphore to release
4337  *
4338  *  Releases the SWFW semaphore and sets the I2C MUX
4339  **/
4340 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4341 {
4342         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4343
4344         if (mask & IXGBE_GSSR_I2C_MASK)
4345                 ixgbe_set_mux(hw, 0);
4346
4347         ixgbe_release_swfw_sync_X540(hw, mask);
4348 }
4349
4350 /**
4351  *  ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4352  *  @hw: pointer to hardware structure
4353  *  @mask: Mask to specify which semaphore to acquire
4354  *
4355  *  Acquires the SWFW semaphore and get the shared phy token as needed
4356  */
4357 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4358 {
4359         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4360         int retries = FW_PHY_TOKEN_RETRIES;
4361         s32 status = IXGBE_SUCCESS;
4362
4363         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4364
4365         while (--retries) {
4366                 status = IXGBE_SUCCESS;
4367                 if (hmask)
4368                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4369                 if (status) {
4370                         DEBUGOUT1("Could not acquire SWFW semaphore, Status = %d\n",
4371                                   status);
4372                         return status;
4373                 }
4374                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4375                         return IXGBE_SUCCESS;
4376
4377                 status = ixgbe_get_phy_token(hw);
4378                 if (status == IXGBE_ERR_TOKEN_RETRY)
4379                         DEBUGOUT1("Could not acquire PHY token, Status = %d\n",
4380                                   status);
4381
4382                 if (status == IXGBE_SUCCESS)
4383                         return IXGBE_SUCCESS;
4384
4385                 if (hmask)
4386                         ixgbe_release_swfw_sync_X540(hw, hmask);
4387
4388                 if (status != IXGBE_ERR_TOKEN_RETRY) {
4389                         DEBUGOUT1("Unable to retry acquiring the PHY token, Status = %d\n",
4390                                   status);
4391                         return status;
4392                 }
4393         }
4394
4395         DEBUGOUT1("Semaphore acquisition retries failed!: PHY ID = 0x%08X\n",
4396                   hw->phy.id);
4397         return status;
4398 }
4399
4400 /**
4401  *  ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4402  *  @hw: pointer to hardware structure
4403  *  @mask: Mask to specify which semaphore to release
4404  *
4405  *  Releases the SWFW semaphore and puts the shared phy token as needed
4406  */
4407 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4408 {
4409         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4410
4411         DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4412
4413         if (mask & IXGBE_GSSR_TOKEN_SM)
4414                 ixgbe_put_phy_token(hw);
4415
4416         if (hmask)
4417                 ixgbe_release_swfw_sync_X540(hw, hmask);
4418 }
4419
4420 /**
4421  *  ixgbe_read_phy_reg_x550a  - Reads specified PHY register
4422  *  @hw: pointer to hardware structure
4423  *  @reg_addr: 32 bit address of PHY register to read
4424  *  @phy_data: Pointer to read data from PHY register
4425  *
4426  *  Reads a value from a specified PHY register using the SWFW lock and PHY
4427  *  Token. The PHY Token is needed since the MDIO is shared between to MAC
4428  *  instances.
4429  **/
4430 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4431                                u32 device_type, u16 *phy_data)
4432 {
4433         s32 status;
4434         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4435
4436         DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4437
4438         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4439                 return IXGBE_ERR_SWFW_SYNC;
4440
4441         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4442
4443         hw->mac.ops.release_swfw_sync(hw, mask);
4444
4445         return status;
4446 }
4447
4448 /**
4449  *  ixgbe_write_phy_reg_x550a - Writes specified PHY register
4450  *  @hw: pointer to hardware structure
4451  *  @reg_addr: 32 bit PHY register to write
4452  *  @device_type: 5 bit device type
4453  *  @phy_data: Data to write to the PHY register
4454  *
4455  *  Writes a value to specified PHY register using the SWFW lock and PHY Token.
4456  *  The PHY Token is needed since the MDIO is shared between to MAC instances.
4457  **/
4458 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4459                                 u32 device_type, u16 phy_data)
4460 {
4461         s32 status;
4462         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4463
4464         DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4465
4466         if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4467                 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
4468                                                  phy_data);
4469                 hw->mac.ops.release_swfw_sync(hw, mask);
4470         } else {
4471                 status = IXGBE_ERR_SWFW_SYNC;
4472         }
4473
4474         return status;
4475 }
4476
4477 /**
4478  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4479  * @hw: pointer to hardware structure
4480  *
4481  * Handle external Base T PHY interrupt. If high temperature
4482  * failure alarm then return error, else if link status change
4483  * then setup internal/external PHY link
4484  *
4485  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4486  * failure alarm, else return PHY access status.
4487  */
4488 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4489 {
4490         bool lsc;
4491         u32 status;
4492
4493         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4494
4495         if (status != IXGBE_SUCCESS)
4496                 return status;
4497
4498         if (lsc)
4499                 return ixgbe_setup_internal_phy(hw);
4500
4501         return IXGBE_SUCCESS;
4502 }
4503
4504 /**
4505  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4506  * @hw: pointer to hardware structure
4507  * @speed: new link speed
4508  * @autoneg_wait_to_complete: true when waiting for completion is needed
4509  *
4510  * Setup internal/external PHY link speed based on link speed, then set
4511  * external PHY auto advertised link speed.
4512  *
4513  * Returns error status for any failure
4514  **/
4515 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4516                                   ixgbe_link_speed speed,
4517                                   bool autoneg_wait_to_complete)
4518 {
4519         s32 status;
4520         ixgbe_link_speed force_speed;
4521
4522         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4523
4524         /* Setup internal/external PHY link speed to iXFI (10G), unless
4525          * only 1G is auto advertised then setup KX link.
4526          */
4527         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4528                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4529         else
4530                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4531
4532         /* If X552 and internal link mode is XFI, then setup XFI internal link.
4533          */
4534         if (hw->mac.type == ixgbe_mac_X550EM_x &&
4535             !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4536                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4537
4538                 if (status != IXGBE_SUCCESS)
4539                         return status;
4540         }
4541
4542         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4543 }
4544
4545 /**
4546  * ixgbe_check_link_t_X550em - Determine link and speed status
4547  * @hw: pointer to hardware structure
4548  * @speed: pointer to link speed
4549  * @link_up: true when link is up
4550  * @link_up_wait_to_complete: bool used to wait for link up or not
4551  *
4552  * Check that both the MAC and X557 external PHY have link.
4553  **/
4554 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4555                               bool *link_up, bool link_up_wait_to_complete)
4556 {
4557         u32 status;
4558         u16 i, autoneg_status = 0;
4559
4560         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4561                 return IXGBE_ERR_CONFIG;
4562
4563         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4564                                               link_up_wait_to_complete);
4565
4566         /* If check link fails or MAC link is not up, then return */
4567         if (status != IXGBE_SUCCESS || !(*link_up))
4568                 return status;
4569
4570         /* MAC link is up, so check external PHY link.
4571          * X557 PHY. Link status is latching low, and can only be used to detect
4572          * link drop, and not the current status of the link without performing
4573          * back-to-back reads.
4574          */
4575         for (i = 0; i < 2; i++) {
4576                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4577                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4578                                               &autoneg_status);
4579
4580                 if (status != IXGBE_SUCCESS)
4581                         return status;
4582         }
4583
4584         /* If external PHY link is not up, then indicate link not up */
4585         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4586                 *link_up = false;
4587
4588         return IXGBE_SUCCESS;
4589 }
4590
4591 /**
4592  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4593  *  @hw: pointer to hardware structure
4594  **/
4595 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4596 {
4597         s32 status;
4598
4599         status = ixgbe_reset_phy_generic(hw);
4600
4601         if (status != IXGBE_SUCCESS)
4602                 return status;
4603
4604         /* Configure Link Status Alarm and Temperature Threshold interrupts */
4605         return ixgbe_enable_lasi_ext_t_x550em(hw);
4606 }
4607
4608 /**
4609  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4610  *  @hw: pointer to hardware structure
4611  *  @led_idx: led number to turn on
4612  **/
4613 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4614 {
4615         u16 phy_data;
4616
4617         DEBUGFUNC("ixgbe_led_on_t_X550em");
4618
4619         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4620                 return IXGBE_ERR_PARAM;
4621
4622         /* To turn on the LED, set mode to ON. */
4623         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4624                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4625         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4626         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4627                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4628
4629         /* Some designs have the LEDs wired to the MAC */
4630         return ixgbe_led_on_generic(hw, led_idx);
4631 }
4632
4633 /**
4634  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4635  *  @hw: pointer to hardware structure
4636  *  @led_idx: led number to turn off
4637  **/
4638 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4639 {
4640         u16 phy_data;
4641
4642         DEBUGFUNC("ixgbe_led_off_t_X550em");
4643
4644         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4645                 return IXGBE_ERR_PARAM;
4646
4647         /* To turn on the LED, set mode to ON. */
4648         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4649                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4650         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4651         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4652                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4653
4654         /* Some designs have the LEDs wired to the MAC */
4655         return ixgbe_led_off_generic(hw, led_idx);
4656 }
4657
4658 /**
4659  *  ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware
4660  *  @hw: pointer to the HW structure
4661  *  @maj: driver version major number
4662  *  @min: driver version minor number
4663  *  @build: driver version build number
4664  *  @sub: driver version sub build number
4665  *  @len: length of driver_ver string
4666  *  @driver_ver: driver string
4667  *
4668  *  Sends driver version number to firmware through the manageability
4669  *  block.  On success return IXGBE_SUCCESS
4670  *  else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4671  *  semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4672  **/
4673 s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,
4674                               u8 build, u8 sub, u16 len, const char *driver_ver)
4675 {
4676         struct ixgbe_hic_drv_info2 fw_cmd;
4677         s32 ret_val = IXGBE_SUCCESS;
4678         int i;
4679
4680         DEBUGFUNC("ixgbe_set_fw_drv_ver_x550");
4681
4682         if ((len == 0) || (driver_ver == NULL) ||
4683            (len > sizeof(fw_cmd.driver_string)))
4684                 return IXGBE_ERR_INVALID_ARGUMENT;
4685
4686         fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4687         fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len;
4688         fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4689         fw_cmd.port_num = (u8)hw->bus.func;
4690         fw_cmd.ver_maj = maj;
4691         fw_cmd.ver_min = min;
4692         fw_cmd.ver_build = build;
4693         fw_cmd.ver_sub = sub;
4694         fw_cmd.hdr.checksum = 0;
4695         memcpy(fw_cmd.driver_string, driver_ver, len);
4696         fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4697                                 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4698
4699         for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4700                 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4701                                                        sizeof(fw_cmd),
4702                                                        IXGBE_HI_COMMAND_TIMEOUT,
4703                                                        true);
4704                 if (ret_val != IXGBE_SUCCESS)
4705                         continue;
4706
4707                 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4708                     FW_CEM_RESP_STATUS_SUCCESS)
4709                         ret_val = IXGBE_SUCCESS;
4710                 else
4711                         ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4712
4713                 break;
4714         }
4715
4716         return ret_val;
4717 }