1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
42 static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
43 static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
46 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
47 * @hw: pointer to hardware structure
49 * Initialize the function pointers and assign the MAC type for X550.
50 * Does not touch the hardware.
52 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
54 struct ixgbe_mac_info *mac = &hw->mac;
55 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
58 DEBUGFUNC("ixgbe_init_ops_X550");
60 ret_val = ixgbe_init_ops_X540(hw);
61 mac->ops.dmac_config = ixgbe_dmac_config_X550;
62 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
63 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
64 mac->ops.setup_eee = ixgbe_setup_eee_X550;
65 mac->ops.set_source_address_pruning =
66 ixgbe_set_source_address_pruning_X550;
67 mac->ops.set_ethertype_anti_spoofing =
68 ixgbe_set_ethertype_anti_spoofing_X550;
70 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
71 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
72 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
73 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
74 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
75 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
76 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
77 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
78 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
80 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
81 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
82 mac->ops.mdd_event = ixgbe_mdd_event_X550;
83 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
84 mac->ops.disable_rx = ixgbe_disable_rx_x550;
85 switch (hw->device_id) {
86 case IXGBE_DEV_ID_X550EM_X_10G_T:
87 case IXGBE_DEV_ID_X550EM_A_10G_T:
88 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
89 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
98 * ixgbe_read_cs4227 - Read CS4227 register
99 * @hw: pointer to hardware structure
100 * @reg: register number to write
101 * @value: pointer to receive value read
103 * Returns status code
105 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
107 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
111 * ixgbe_write_cs4227 - Write CS4227 register
112 * @hw: pointer to hardware structure
113 * @reg: register number to write
114 * @value: value to write to register
116 * Returns status code
118 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
120 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
124 * ixgbe_read_pe - Read register from port expander
125 * @hw: pointer to hardware structure
126 * @reg: register number to read
127 * @value: pointer to receive read value
129 * Returns status code
131 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
135 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
136 if (status != IXGBE_SUCCESS)
137 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
138 "port expander access failed with %d\n", status);
143 * ixgbe_write_pe - Write register to port expander
144 * @hw: pointer to hardware structure
145 * @reg: register number to write
146 * @value: value to write
148 * Returns status code
150 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
154 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
155 if (status != IXGBE_SUCCESS)
156 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
157 "port expander access failed with %d\n", status);
162 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
163 * @hw: pointer to hardware structure
165 * This function assumes that the caller has acquired the proper semaphore.
168 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
175 /* Trigger hard reset. */
176 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
177 if (status != IXGBE_SUCCESS)
179 reg |= IXGBE_PE_BIT1;
180 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
181 if (status != IXGBE_SUCCESS)
184 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
185 if (status != IXGBE_SUCCESS)
187 reg &= ~IXGBE_PE_BIT1;
188 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
189 if (status != IXGBE_SUCCESS)
192 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
193 if (status != IXGBE_SUCCESS)
195 reg &= ~IXGBE_PE_BIT1;
196 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
197 if (status != IXGBE_SUCCESS)
200 usec_delay(IXGBE_CS4227_RESET_HOLD);
202 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
203 if (status != IXGBE_SUCCESS)
205 reg |= IXGBE_PE_BIT1;
206 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
207 if (status != IXGBE_SUCCESS)
210 /* Wait for the reset to complete. */
211 msec_delay(IXGBE_CS4227_RESET_DELAY);
212 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
213 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
215 if (status == IXGBE_SUCCESS &&
216 value == IXGBE_CS4227_EEPROM_LOAD_OK)
218 msec_delay(IXGBE_CS4227_CHECK_DELAY);
220 if (retry == IXGBE_CS4227_RETRIES) {
221 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
222 "CS4227 reset did not complete.");
223 return IXGBE_ERR_PHY;
226 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
227 if (status != IXGBE_SUCCESS ||
228 !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
229 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
230 "CS4227 EEPROM did not load successfully.");
231 return IXGBE_ERR_PHY;
234 return IXGBE_SUCCESS;
238 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
239 * @hw: pointer to hardware structure
241 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
243 s32 status = IXGBE_SUCCESS;
244 u32 swfw_mask = hw->phy.phy_semaphore_mask;
248 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
249 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
250 if (status != IXGBE_SUCCESS) {
251 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
252 "semaphore failed with %d", status);
253 msec_delay(IXGBE_CS4227_CHECK_DELAY);
257 /* Get status of reset flow. */
258 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
260 if (status == IXGBE_SUCCESS &&
261 value == IXGBE_CS4227_RESET_COMPLETE)
264 if (status != IXGBE_SUCCESS ||
265 value != IXGBE_CS4227_RESET_PENDING)
268 /* Reset is pending. Wait and check again. */
269 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
270 msec_delay(IXGBE_CS4227_CHECK_DELAY);
273 /* If still pending, assume other instance failed. */
274 if (retry == IXGBE_CS4227_RETRIES) {
275 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
276 if (status != IXGBE_SUCCESS) {
277 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
278 "semaphore failed with %d", status);
283 /* Reset the CS4227. */
284 status = ixgbe_reset_cs4227(hw);
285 if (status != IXGBE_SUCCESS) {
286 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
287 "CS4227 reset failed: %d", status);
291 /* Reset takes so long, temporarily release semaphore in case the
292 * other driver instance is waiting for the reset indication.
294 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
295 IXGBE_CS4227_RESET_PENDING);
296 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
298 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
299 if (status != IXGBE_SUCCESS) {
300 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
301 "semaphore failed with %d", status);
305 /* Record completion for next time. */
306 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
307 IXGBE_CS4227_RESET_COMPLETE);
310 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
311 msec_delay(hw->eeprom.semaphore_delay);
315 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
316 * @hw: pointer to hardware structure
318 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
320 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
322 if (hw->bus.lan_id) {
323 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
324 esdp |= IXGBE_ESDP_SDP1_DIR;
326 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
327 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
328 IXGBE_WRITE_FLUSH(hw);
332 * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
333 * @hw: pointer to hardware structure
334 * @reg_addr: 32 bit address of PHY register to read
335 * @dev_type: always unused
336 * @phy_data: Pointer to read data from PHY register
338 static s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
339 u32 dev_type, u16 *phy_data)
341 u32 i, data, command;
342 UNREFERENCED_1PARAMETER(dev_type);
344 /* Setup and write the read command */
345 command = (reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
346 (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
347 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
348 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ |
349 IXGBE_MSCA_MDI_COMMAND;
351 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
353 /* Check every 10 usec to see if the access completed.
354 * The MDI Command bit will clear when the operation is
357 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
360 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
361 if (!(command & IXGBE_MSCA_MDI_COMMAND))
365 if (command & IXGBE_MSCA_MDI_COMMAND) {
366 ERROR_REPORT1(IXGBE_ERROR_POLLING,
367 "PHY read command did not complete.\n");
368 return IXGBE_ERR_PHY;
371 /* Read operation is complete. Get the data from MSRWD */
372 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
373 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
374 *phy_data = (u16)data;
376 return IXGBE_SUCCESS;
380 * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
381 * @hw: pointer to hardware structure
382 * @reg_addr: 32 bit PHY register to write
383 * @dev_type: always unused
384 * @phy_data: Data to write to the PHY register
386 static s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
387 u32 dev_type, u16 phy_data)
390 UNREFERENCED_1PARAMETER(dev_type);
392 /* Put the data in the MDI single read and write data register*/
393 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
395 /* Setup and write the write command */
396 command = (reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
397 (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
398 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
399 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
400 IXGBE_MSCA_MDI_COMMAND;
402 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
404 /* Check every 10 usec to see if the access completed.
405 * The MDI Command bit will clear when the operation is
408 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
411 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
412 if (!(command & IXGBE_MSCA_MDI_COMMAND))
416 if (command & IXGBE_MSCA_MDI_COMMAND) {
417 ERROR_REPORT1(IXGBE_ERROR_POLLING,
418 "PHY write cmd didn't complete\n");
419 return IXGBE_ERR_PHY;
422 return IXGBE_SUCCESS;
426 * ixgbe_identify_phy_1g - Get 1g PHY type based on device id
427 * @hw: pointer to hardware structure
431 static s32 ixgbe_identify_phy_1g(struct ixgbe_hw *hw)
433 u32 swfw_mask = hw->phy.phy_semaphore_mask;
438 rc = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
442 rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_MDIO_PHY_ID_HIGH, 0,
447 rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_MDIO_PHY_ID_LOW, 0,
452 hw->phy.id = (u32)phy_id_high << 16;
453 hw->phy.id |= phy_id_low & IXGBE_PHY_REVISION_MASK;
454 hw->phy.revision = (u32)phy_id_low & ~IXGBE_PHY_REVISION_MASK;
457 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
463 * ixgbe_identify_phy_x550em - Get PHY type based on device id
464 * @hw: pointer to hardware structure
468 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
470 switch (hw->device_id) {
471 case IXGBE_DEV_ID_X550EM_A_SFP:
472 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
473 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
475 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
477 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
478 return ixgbe_identify_module_generic(hw);
479 case IXGBE_DEV_ID_X550EM_X_SFP:
480 /* set up for CS4227 usage */
481 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
482 ixgbe_setup_mux_ctl(hw);
483 ixgbe_check_cs4227(hw);
486 case IXGBE_DEV_ID_X550EM_A_SFP_N:
487 return ixgbe_identify_module_generic(hw);
489 case IXGBE_DEV_ID_X550EM_X_KX4:
490 hw->phy.type = ixgbe_phy_x550em_kx4;
492 case IXGBE_DEV_ID_X550EM_X_KR:
493 case IXGBE_DEV_ID_X550EM_A_KR:
494 case IXGBE_DEV_ID_X550EM_A_KR_L:
495 hw->phy.type = ixgbe_phy_x550em_kr;
497 case IXGBE_DEV_ID_X550EM_X_1G_T:
498 case IXGBE_DEV_ID_X550EM_X_10G_T:
499 case IXGBE_DEV_ID_X550EM_A_10G_T:
500 return ixgbe_identify_phy_generic(hw);
501 case IXGBE_DEV_ID_X550EM_A_1G_T:
502 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
503 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
504 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
506 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
508 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
509 return ixgbe_identify_phy_1g(hw);
513 return IXGBE_SUCCESS;
516 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
517 u32 device_type, u16 *phy_data)
519 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
520 return IXGBE_NOT_IMPLEMENTED;
523 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
524 u32 device_type, u16 phy_data)
526 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
527 return IXGBE_NOT_IMPLEMENTED;
531 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
532 * @hw: pointer to the hardware structure
533 * @addr: I2C bus address to read from
534 * @reg: I2C device register to read from
535 * @val: pointer to location to receive read value
537 * Returns an error code on error.
539 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
542 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
546 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
547 * @hw: pointer to the hardware structure
548 * @addr: I2C bus address to read from
549 * @reg: I2C device register to read from
550 * @val: pointer to location to receive read value
552 * Returns an error code on error.
555 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
558 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
562 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
563 * @hw: pointer to the hardware structure
564 * @addr: I2C bus address to write to
565 * @reg: I2C device register to write to
566 * @val: value to write
568 * Returns an error code on error.
570 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
571 u8 addr, u16 reg, u16 val)
573 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
577 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
578 * @hw: pointer to the hardware structure
579 * @addr: I2C bus address to write to
580 * @reg: I2C device register to write to
581 * @val: value to write
583 * Returns an error code on error.
586 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
587 u8 addr, u16 reg, u16 val)
589 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
593 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
594 * @hw: pointer to hardware structure
596 * Initialize the function pointers and for MAC type X550EM.
597 * Does not touch the hardware.
599 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
601 struct ixgbe_mac_info *mac = &hw->mac;
602 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
603 struct ixgbe_phy_info *phy = &hw->phy;
604 struct ixgbe_link_info *link = &hw->link;
607 DEBUGFUNC("ixgbe_init_ops_X550EM");
609 /* Similar to X550 so start there. */
610 ret_val = ixgbe_init_ops_X550(hw);
612 /* Since this function eventually calls
613 * ixgbe_init_ops_540 by design, we are setting
614 * the pointers to NULL explicitly here to overwrite
615 * the values being set in the x540 function.
617 /* Thermal sensor not supported in x550EM */
618 mac->ops.get_thermal_sensor_data = NULL;
619 mac->ops.init_thermal_sensor_thresh = NULL;
620 mac->thermal_sensor_enabled = false;
622 /* FCOE not supported in x550EM */
623 mac->ops.get_san_mac_addr = NULL;
624 mac->ops.set_san_mac_addr = NULL;
625 mac->ops.get_wwn_prefix = NULL;
626 mac->ops.get_fcoe_boot_status = NULL;
628 /* IPsec not supported in x550EM */
629 mac->ops.disable_sec_rx_path = NULL;
630 mac->ops.enable_sec_rx_path = NULL;
632 /* AUTOC register is not present in x550EM. */
633 mac->ops.prot_autoc_read = NULL;
634 mac->ops.prot_autoc_write = NULL;
636 /* X550EM bus type is internal*/
637 hw->bus.type = ixgbe_bus_type_internal;
638 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
640 if (hw->mac.type == ixgbe_mac_X550EM_x) {
641 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
642 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
643 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
644 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
645 link->ops.read_link = ixgbe_read_i2c_combined_generic;
646 link->ops.read_link_unlocked =
647 ixgbe_read_i2c_combined_generic_unlocked;
648 link->ops.write_link = ixgbe_write_i2c_combined_generic;
649 link->ops.write_link_unlocked =
650 ixgbe_write_i2c_combined_generic_unlocked;
651 link->addr = IXGBE_CS4227;
653 if (hw->mac.type == ixgbe_mac_X550EM_a) {
654 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
655 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
656 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
657 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
660 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
661 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
662 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
663 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
664 mac->ops.get_supported_physical_layer =
665 ixgbe_get_supported_physical_layer_X550em;
667 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
668 mac->ops.setup_fc = ixgbe_setup_fc_generic;
670 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
672 switch (hw->device_id) {
673 case IXGBE_DEV_ID_X550EM_X_KR:
674 case IXGBE_DEV_ID_X550EM_A_KR:
675 case IXGBE_DEV_ID_X550EM_A_KR_L:
678 mac->ops.setup_eee = NULL;
682 phy->ops.init = ixgbe_init_phy_ops_X550em;
683 phy->ops.identify = ixgbe_identify_phy_x550em;
684 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
685 phy->ops.set_phy_power = NULL;
689 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
690 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
691 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
692 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
693 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
694 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
695 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
696 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
702 * ixgbe_dmac_config_X550
703 * @hw: pointer to hardware structure
705 * Configure DMA coalescing. If enabling dmac, dmac is activated.
706 * When disabling dmac, dmac enable dmac bit is cleared.
708 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
710 u32 reg, high_pri_tc;
712 DEBUGFUNC("ixgbe_dmac_config_X550");
714 /* Disable DMA coalescing before configuring */
715 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
716 reg &= ~IXGBE_DMACR_DMAC_EN;
717 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
719 /* Disable DMA Coalescing if the watchdog timer is 0 */
720 if (!hw->mac.dmac_config.watchdog_timer)
723 ixgbe_dmac_config_tcs_X550(hw);
725 /* Configure DMA Coalescing Control Register */
726 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
728 /* Set the watchdog timer in units of 40.96 usec */
729 reg &= ~IXGBE_DMACR_DMACWT_MASK;
730 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
732 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
733 /* If fcoe is enabled, set high priority traffic class */
734 if (hw->mac.dmac_config.fcoe_en) {
735 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
736 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
737 IXGBE_DMACR_HIGH_PRI_TC_MASK);
739 reg |= IXGBE_DMACR_EN_MNG_IND;
741 /* Enable DMA coalescing after configuration */
742 reg |= IXGBE_DMACR_DMAC_EN;
743 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
746 return IXGBE_SUCCESS;
750 * ixgbe_dmac_config_tcs_X550
751 * @hw: pointer to hardware structure
753 * Configure DMA coalescing threshold per TC. The dmac enable bit must
754 * be cleared before configuring.
756 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
758 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
760 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
762 /* Configure DMA coalescing enabled */
763 switch (hw->mac.dmac_config.link_speed) {
764 case IXGBE_LINK_SPEED_100_FULL:
765 pb_headroom = IXGBE_DMACRXT_100M;
767 case IXGBE_LINK_SPEED_1GB_FULL:
768 pb_headroom = IXGBE_DMACRXT_1G;
771 pb_headroom = IXGBE_DMACRXT_10G;
775 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
776 IXGBE_MHADD_MFS_SHIFT) / 1024);
778 /* Set the per Rx packet buffer receive threshold */
779 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
780 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
781 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
783 if (tc < hw->mac.dmac_config.num_tcs) {
785 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
786 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
787 IXGBE_RXPBSIZE_SHIFT;
789 /* Calculate receive buffer threshold in kilobytes */
790 if (rx_pb_size > pb_headroom)
791 rx_pb_size = rx_pb_size - pb_headroom;
795 /* Minimum of MFS shall be set for DMCTH */
796 reg |= (rx_pb_size > maxframe_size_kb) ?
797 rx_pb_size : maxframe_size_kb;
799 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
801 return IXGBE_SUCCESS;
805 * ixgbe_dmac_update_tcs_X550
806 * @hw: pointer to hardware structure
808 * Disables dmac, updates per TC settings, and then enables dmac.
810 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
814 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
816 /* Disable DMA coalescing before configuring */
817 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
818 reg &= ~IXGBE_DMACR_DMAC_EN;
819 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
821 ixgbe_dmac_config_tcs_X550(hw);
823 /* Enable DMA coalescing after configuration */
824 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
825 reg |= IXGBE_DMACR_DMAC_EN;
826 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
828 return IXGBE_SUCCESS;
832 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
833 * @hw: pointer to hardware structure
835 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
836 * ixgbe_hw struct in order to set up EEPROM access.
838 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
840 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
844 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
846 if (eeprom->type == ixgbe_eeprom_uninitialized) {
847 eeprom->semaphore_delay = 10;
848 eeprom->type = ixgbe_flash;
850 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
851 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
852 IXGBE_EEC_SIZE_SHIFT);
853 eeprom->word_size = 1 << (eeprom_size +
854 IXGBE_EEPROM_WORD_SIZE_SHIFT);
856 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
857 eeprom->type, eeprom->word_size);
860 return IXGBE_SUCCESS;
864 * ixgbe_enable_eee_x550 - Enable EEE support
865 * @hw: pointer to hardware structure
867 static s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
873 if (hw->mac.type == ixgbe_mac_X550) {
874 /* Advertise EEE capability */
875 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
876 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
879 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
880 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
881 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
883 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
884 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
886 return IXGBE_SUCCESS;
889 switch (hw->device_id) {
890 case IXGBE_DEV_ID_X550EM_X_KR:
891 case IXGBE_DEV_ID_X550EM_A_KR:
892 case IXGBE_DEV_ID_X550EM_A_KR_L:
893 status = hw->mac.ops.read_iosf_sb_reg(hw,
894 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
895 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
896 if (status != IXGBE_SUCCESS)
899 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
900 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
902 /* Don't advertise FEC capability when EEE enabled. */
903 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
905 status = hw->mac.ops.write_iosf_sb_reg(hw,
906 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
907 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
908 if (status != IXGBE_SUCCESS)
915 return IXGBE_SUCCESS;
919 * ixgbe_disable_eee_x550 - Disable EEE support
920 * @hw: pointer to hardware structure
922 static s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
928 if (hw->mac.type == ixgbe_mac_X550) {
929 /* Disable advertised EEE capability */
930 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
931 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
934 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
935 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
936 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
938 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
939 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
941 return IXGBE_SUCCESS;
944 switch (hw->device_id) {
945 case IXGBE_DEV_ID_X550EM_X_KR:
946 case IXGBE_DEV_ID_X550EM_A_KR:
947 case IXGBE_DEV_ID_X550EM_A_KR_L:
948 status = hw->mac.ops.read_iosf_sb_reg(hw,
949 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
950 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
951 if (status != IXGBE_SUCCESS)
954 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
955 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
957 /* Advertise FEC capability when EEE is disabled. */
958 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
960 status = hw->mac.ops.write_iosf_sb_reg(hw,
961 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
962 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
963 if (status != IXGBE_SUCCESS)
970 return IXGBE_SUCCESS;
974 * ixgbe_setup_eee_X550 - Enable/disable EEE support
975 * @hw: pointer to the HW structure
976 * @enable_eee: boolean flag to enable EEE
978 * Enable/disable EEE based on enable_eee flag.
979 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
983 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
988 DEBUGFUNC("ixgbe_setup_eee_X550");
990 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
991 /* Enable or disable EEE per flag */
993 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
995 /* Not supported on first revision of X550EM_x. */
996 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
997 !(IXGBE_FUSES0_REV_MASK &
998 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
999 return IXGBE_SUCCESS;
1000 status = ixgbe_enable_eee_x550(hw);
1004 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1006 status = ixgbe_disable_eee_x550(hw);
1010 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
1012 return IXGBE_SUCCESS;
1016 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1017 * @hw: pointer to hardware structure
1018 * @enable: enable or disable source address pruning
1019 * @pool: Rx pool to set source address pruning for
1021 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1026 /* max rx pool is 63 */
1030 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1031 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1034 pfflp |= (1ULL << pool);
1036 pfflp &= ~(1ULL << pool);
1038 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1039 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1043 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1044 * @hw: pointer to hardware structure
1045 * @enable: enable or disable switch for Ethertype anti-spoofing
1046 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1049 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1050 bool enable, int vf)
1052 int vf_target_reg = vf >> 3;
1053 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1056 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1058 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1060 pfvfspoof |= (1 << vf_target_shift);
1062 pfvfspoof &= ~(1 << vf_target_shift);
1064 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1068 * ixgbe_iosf_wait - Wait for IOSF command completion
1069 * @hw: pointer to hardware structure
1070 * @ctrl: pointer to location to receive final IOSF control value
1072 * Returns failing status on timeout
1074 * Note: ctrl can be NULL if the IOSF control register value is not needed
1076 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1080 /* Check every 10 usec to see if the address cycle completed.
1081 * The SB IOSF BUSY bit will clear when the operation is
1084 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1085 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1086 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1092 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1093 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1094 return IXGBE_ERR_PHY;
1097 return IXGBE_SUCCESS;
1101 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
1103 * @hw: pointer to hardware structure
1104 * @reg_addr: 32 bit PHY register to write
1105 * @device_type: 3 bit device type
1106 * @data: Data to write to the register
1108 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1109 u32 device_type, u32 data)
1111 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1115 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1116 if (ret != IXGBE_SUCCESS)
1119 ret = ixgbe_iosf_wait(hw, NULL);
1120 if (ret != IXGBE_SUCCESS)
1123 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1124 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1126 /* Write IOSF control register */
1127 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1129 /* Write IOSF data register */
1130 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1132 ret = ixgbe_iosf_wait(hw, &command);
1134 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1135 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1136 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1137 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1138 "Failed to write, error %x\n", error);
1139 ret = IXGBE_ERR_PHY;
1143 ixgbe_release_swfw_semaphore(hw, gssr);
1148 * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
1150 * @hw: pointer to hardware structure
1151 * @reg_addr: 32 bit PHY register to write
1152 * @device_type: 3 bit device type
1153 * @phy_data: Pointer to read data from the register
1155 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1156 u32 device_type, u32 *data)
1158 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1162 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1163 if (ret != IXGBE_SUCCESS)
1166 ret = ixgbe_iosf_wait(hw, NULL);
1167 if (ret != IXGBE_SUCCESS)
1170 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1171 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1173 /* Write IOSF control register */
1174 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1176 ret = ixgbe_iosf_wait(hw, &command);
1178 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1179 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1180 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1181 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1182 "Failed to read, error %x\n", error);
1183 ret = IXGBE_ERR_PHY;
1186 if (ret == IXGBE_SUCCESS)
1187 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1190 ixgbe_release_swfw_semaphore(hw, gssr);
1195 * ixgbe_get_phy_token - Get the token for shared phy access
1196 * @hw: Pointer to hardware structure
1199 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1201 struct ixgbe_hic_phy_token_req token_cmd;
1204 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1205 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1206 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1207 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1208 token_cmd.port_number = hw->bus.lan_id;
1209 token_cmd.command_type = FW_PHY_TOKEN_REQ;
1211 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1213 IXGBE_HI_COMMAND_TIMEOUT,
1217 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1218 return IXGBE_SUCCESS;
1219 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1220 return IXGBE_ERR_FW_RESP_INVALID;
1222 return IXGBE_ERR_TOKEN_RETRY;
1226 * ixgbe_put_phy_token - Put the token for shared phy access
1227 * @hw: Pointer to hardware structure
1230 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1232 struct ixgbe_hic_phy_token_req token_cmd;
1235 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1236 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1237 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1238 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1239 token_cmd.port_number = hw->bus.lan_id;
1240 token_cmd.command_type = FW_PHY_TOKEN_REL;
1242 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1244 IXGBE_HI_COMMAND_TIMEOUT,
1248 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1249 return IXGBE_SUCCESS;
1251 DEBUGOUT("Put PHY Token host interface command failed");
1252 return IXGBE_ERR_FW_RESP_INVALID;
1256 * ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1257 * of the IOSF device
1258 * @hw: pointer to hardware structure
1259 * @reg_addr: 32 bit PHY register to write
1260 * @device_type: 3 bit device type
1261 * @data: Data to write to the register
1263 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1264 u32 device_type, u32 data)
1266 struct ixgbe_hic_internal_phy_req write_cmd;
1268 UNREFERENCED_1PARAMETER(device_type);
1270 memset(&write_cmd, 0, sizeof(write_cmd));
1271 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1272 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1273 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1274 write_cmd.port_number = hw->bus.lan_id;
1275 write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1276 write_cmd.address = (u16)reg_addr;
1277 write_cmd.write_data = data;
1279 status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1281 IXGBE_HI_COMMAND_TIMEOUT, false);
1287 * ixgbe_read_iosf_sb_reg_x550a - Writes a value to specified register
1288 * of the IOSF device.
1289 * @hw: pointer to hardware structure
1290 * @reg_addr: 32 bit PHY register to write
1291 * @device_type: 3 bit device type
1292 * @data: Pointer to read data from the register
1294 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1295 u32 device_type, u32 *data)
1297 struct ixgbe_hic_internal_phy_req read_cmd;
1299 UNREFERENCED_1PARAMETER(device_type);
1301 memset(&read_cmd, 0, sizeof(read_cmd));
1302 read_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1303 read_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1304 read_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1305 read_cmd.port_number = hw->bus.lan_id;
1306 read_cmd.command_type = FW_INT_PHY_REQ_READ;
1307 read_cmd.address = (u16)reg_addr;
1309 status = ixgbe_host_interface_command(hw, (u32 *)&read_cmd,
1311 IXGBE_HI_COMMAND_TIMEOUT, true);
1313 /* Extract the register value from the response. */
1314 *data = ((struct ixgbe_hic_internal_phy_resp *)&read_cmd)->read_data;
1320 * ixgbe_disable_mdd_X550
1321 * @hw: pointer to hardware structure
1323 * Disable malicious driver detection
1325 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1329 DEBUGFUNC("ixgbe_disable_mdd_X550");
1331 /* Disable MDD for TX DMA and interrupt */
1332 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1333 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1334 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1336 /* Disable MDD for RX and interrupt */
1337 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1338 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1339 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1343 * ixgbe_enable_mdd_X550
1344 * @hw: pointer to hardware structure
1346 * Enable malicious driver detection
1348 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1352 DEBUGFUNC("ixgbe_enable_mdd_X550");
1354 /* Enable MDD for TX DMA and interrupt */
1355 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1356 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1357 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1359 /* Enable MDD for RX and interrupt */
1360 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1361 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1362 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1366 * ixgbe_restore_mdd_vf_X550
1367 * @hw: pointer to hardware structure
1370 * Restore VF that was disabled during malicious driver detection event
1372 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1374 u32 idx, reg, num_qs, start_q, bitmask;
1376 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1378 /* Map VF to queues */
1379 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1380 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1381 case IXGBE_MRQC_VMDQRT8TCEN:
1382 num_qs = 8; /* 16 VFs / pools */
1383 bitmask = 0x000000FF;
1385 case IXGBE_MRQC_VMDQRSS32EN:
1386 case IXGBE_MRQC_VMDQRT4TCEN:
1387 num_qs = 4; /* 32 VFs / pools */
1388 bitmask = 0x0000000F;
1390 default: /* 64 VFs / pools */
1392 bitmask = 0x00000003;
1395 start_q = vf * num_qs;
1397 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1400 reg |= (bitmask << (start_q % 32));
1401 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1402 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1406 * ixgbe_mdd_event_X550
1407 * @hw: pointer to hardware structure
1408 * @vf_bitmap: vf bitmap of malicious vfs
1410 * Handle malicious driver detection event.
1412 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1415 u32 i, j, reg, q, shift, vf, idx;
1417 DEBUGFUNC("ixgbe_mdd_event_X550");
1419 /* figure out pool size for mapping to vf's */
1420 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1421 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1422 case IXGBE_MRQC_VMDQRT8TCEN:
1423 shift = 3; /* 16 VFs / pools */
1425 case IXGBE_MRQC_VMDQRSS32EN:
1426 case IXGBE_MRQC_VMDQRT4TCEN:
1427 shift = 2; /* 32 VFs / pools */
1430 shift = 1; /* 64 VFs / pools */
1434 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1435 for (i = 0; i < 4; i++) {
1436 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1437 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1442 /* Get malicious queue */
1443 for (j = 0; j < 32 && wqbr; j++) {
1445 if (!(wqbr & (1 << j)))
1448 /* Get queue from bitmask */
1451 /* Map queue to vf */
1454 /* Set vf bit in vf_bitmap */
1456 vf_bitmap[idx] |= (1 << (vf % 32));
1463 * ixgbe_get_media_type_X550em - Get media type
1464 * @hw: pointer to hardware structure
1466 * Returns the media type (fiber, copper, backplane)
1468 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1470 enum ixgbe_media_type media_type;
1472 DEBUGFUNC("ixgbe_get_media_type_X550em");
1474 /* Detect if there is a copper PHY attached. */
1475 switch (hw->device_id) {
1476 case IXGBE_DEV_ID_X550EM_X_KR:
1477 case IXGBE_DEV_ID_X550EM_X_KX4:
1478 case IXGBE_DEV_ID_X550EM_A_KR:
1479 case IXGBE_DEV_ID_X550EM_A_KR_L:
1480 media_type = ixgbe_media_type_backplane;
1482 case IXGBE_DEV_ID_X550EM_X_SFP:
1483 case IXGBE_DEV_ID_X550EM_A_SFP:
1484 case IXGBE_DEV_ID_X550EM_A_SFP_N:
1485 case IXGBE_DEV_ID_X550EM_A_QSFP:
1486 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1487 media_type = ixgbe_media_type_fiber;
1489 case IXGBE_DEV_ID_X550EM_X_1G_T:
1490 case IXGBE_DEV_ID_X550EM_X_10G_T:
1491 case IXGBE_DEV_ID_X550EM_A_10G_T:
1492 media_type = ixgbe_media_type_copper;
1494 case IXGBE_DEV_ID_X550EM_A_SGMII:
1495 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1496 media_type = ixgbe_media_type_backplane;
1497 hw->phy.type = ixgbe_phy_sgmii;
1499 case IXGBE_DEV_ID_X550EM_A_1G_T:
1500 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1501 media_type = ixgbe_media_type_copper;
1502 hw->phy.type = ixgbe_phy_m88;
1505 media_type = ixgbe_media_type_unknown;
1512 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1513 * @hw: pointer to hardware structure
1514 * @linear: true if SFP module is linear
1516 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1518 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1520 switch (hw->phy.sfp_type) {
1521 case ixgbe_sfp_type_not_present:
1522 return IXGBE_ERR_SFP_NOT_PRESENT;
1523 case ixgbe_sfp_type_da_cu_core0:
1524 case ixgbe_sfp_type_da_cu_core1:
1527 case ixgbe_sfp_type_srlr_core0:
1528 case ixgbe_sfp_type_srlr_core1:
1529 case ixgbe_sfp_type_da_act_lmt_core0:
1530 case ixgbe_sfp_type_da_act_lmt_core1:
1531 case ixgbe_sfp_type_1g_sx_core0:
1532 case ixgbe_sfp_type_1g_sx_core1:
1533 case ixgbe_sfp_type_1g_lx_core0:
1534 case ixgbe_sfp_type_1g_lx_core1:
1537 case ixgbe_sfp_type_unknown:
1538 case ixgbe_sfp_type_1g_cu_core0:
1539 case ixgbe_sfp_type_1g_cu_core1:
1541 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1544 return IXGBE_SUCCESS;
1548 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1549 * @hw: pointer to hardware structure
1551 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1553 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1558 DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1560 status = ixgbe_identify_module_generic(hw);
1562 if (status != IXGBE_SUCCESS)
1565 /* Check if SFP module is supported */
1566 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1572 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1573 * @hw: pointer to hardware structure
1575 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1580 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1582 /* Check if SFP module is supported */
1583 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1585 if (status != IXGBE_SUCCESS)
1588 ixgbe_init_mac_link_ops_X550em(hw);
1589 hw->phy.ops.reset = NULL;
1591 return IXGBE_SUCCESS;
1595 * ixgbe_setup_sgmii - Set up link for sgmii
1596 * @hw: pointer to hardware structure
1598 static s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1599 bool autoneg_wait_to_complete)
1601 struct ixgbe_mac_info *mac = &hw->mac;
1604 UNREFERENCED_2PARAMETER(speed, autoneg_wait_to_complete);
1606 rc = mac->ops.read_iosf_sb_reg(hw,
1607 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1608 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1612 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1613 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1614 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1615 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1616 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1617 rc = mac->ops.write_iosf_sb_reg(hw,
1618 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1619 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1623 rc = mac->ops.read_iosf_sb_reg(hw,
1624 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1625 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1629 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1630 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1631 rc = mac->ops.write_iosf_sb_reg(hw,
1632 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1633 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1637 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1638 rc = mac->ops.write_iosf_sb_reg(hw,
1639 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1640 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1646 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1647 * @hw: pointer to hardware structure
1649 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1651 struct ixgbe_mac_info *mac = &hw->mac;
1653 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1655 switch (hw->mac.ops.get_media_type(hw)) {
1656 case ixgbe_media_type_fiber:
1657 /* CS4227 does not support autoneg, so disable the laser control
1658 * functions for SFP+ fiber
1660 mac->ops.disable_tx_laser = NULL;
1661 mac->ops.enable_tx_laser = NULL;
1662 mac->ops.flap_tx_laser = NULL;
1663 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1664 mac->ops.set_rate_select_speed =
1665 ixgbe_set_soft_rate_select_speed;
1666 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1667 (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1668 mac->ops.setup_mac_link =
1669 ixgbe_setup_mac_link_sfp_x550a;
1671 mac->ops.setup_mac_link =
1672 ixgbe_setup_mac_link_sfp_x550em;
1674 case ixgbe_media_type_copper:
1675 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1676 mac->ops.check_link = ixgbe_check_link_t_X550em;
1678 case ixgbe_media_type_backplane:
1679 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1680 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1681 mac->ops.setup_link = ixgbe_setup_sgmii;
1689 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1690 * @hw: pointer to hardware structure
1691 * @speed: pointer to link speed
1692 * @autoneg: true when autoneg or autotry is enabled
1694 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1695 ixgbe_link_speed *speed,
1698 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1701 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1703 /* CS4227 SFP must not enable auto-negotiation */
1706 /* Check if 1G SFP module. */
1707 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1708 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1709 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1710 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1711 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1712 return IXGBE_SUCCESS;
1715 /* Link capabilities are based on SFP */
1716 if (hw->phy.multispeed_fiber)
1717 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1718 IXGBE_LINK_SPEED_1GB_FULL;
1720 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1722 switch (hw->phy.type) {
1724 *speed = IXGBE_LINK_SPEED_100_FULL |
1725 IXGBE_LINK_SPEED_1GB_FULL;
1727 case ixgbe_phy_sgmii:
1728 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1731 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1732 IXGBE_LINK_SPEED_1GB_FULL;
1738 return IXGBE_SUCCESS;
1742 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1743 * @hw: pointer to hardware structure
1744 * @lsc: pointer to boolean flag which indicates whether external Base T
1745 * PHY interrupt is lsc
1747 * Determime if external Base T PHY interrupt cause is high temperature
1748 * failure alarm or link status change.
1750 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1751 * failure alarm, else return PHY access status.
1753 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1760 /* Vendor alarm triggered */
1761 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1762 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1765 if (status != IXGBE_SUCCESS ||
1766 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1769 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1770 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1771 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1774 if (status != IXGBE_SUCCESS ||
1775 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1776 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1779 /* Global alarm triggered */
1780 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1781 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1784 if (status != IXGBE_SUCCESS)
1787 /* If high temperature failure, then return over temp error and exit */
1788 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1789 /* power down the PHY in case the PHY FW didn't already */
1790 ixgbe_set_copper_phy_power(hw, false);
1791 return IXGBE_ERR_OVERTEMP;
1792 } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1793 /* device fault alarm triggered */
1794 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1795 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1798 if (status != IXGBE_SUCCESS)
1801 /* if device fault was due to high temp alarm handle and exit */
1802 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1803 /* power down the PHY in case the PHY FW didn't */
1804 ixgbe_set_copper_phy_power(hw, false);
1805 return IXGBE_ERR_OVERTEMP;
1809 /* Vendor alarm 2 triggered */
1810 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1811 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1813 if (status != IXGBE_SUCCESS ||
1814 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1817 /* link connect/disconnect event occurred */
1818 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1819 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1821 if (status != IXGBE_SUCCESS)
1825 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1828 return IXGBE_SUCCESS;
1832 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1833 * @hw: pointer to hardware structure
1835 * Enable link status change and temperature failure alarm for the external
1838 * Returns PHY access status
1840 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1846 /* Clear interrupt flags */
1847 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1849 /* Enable link status change alarm */
1850 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1851 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1853 if (status != IXGBE_SUCCESS)
1856 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1858 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1859 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1861 if (status != IXGBE_SUCCESS)
1864 /* Enable high temperature failure and global fault alarms */
1865 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1866 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1869 if (status != IXGBE_SUCCESS)
1872 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
1873 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
1875 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1876 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1879 if (status != IXGBE_SUCCESS)
1882 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1883 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1884 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1887 if (status != IXGBE_SUCCESS)
1890 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1891 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1893 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1894 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1897 if (status != IXGBE_SUCCESS)
1900 /* Enable chip-wide vendor alarm */
1901 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1902 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1905 if (status != IXGBE_SUCCESS)
1908 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1910 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1911 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1918 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1919 * @hw: pointer to hardware structure
1920 * @speed: link speed
1922 * Configures the integrated KR PHY.
1924 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1925 ixgbe_link_speed speed)
1930 status = hw->mac.ops.read_iosf_sb_reg(hw,
1931 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1932 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1936 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1937 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1938 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1940 /* Advertise 10G support. */
1941 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1942 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1944 /* Advertise 1G support. */
1945 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1946 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1948 /* Restart auto-negotiation. */
1949 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1950 status = hw->mac.ops.write_iosf_sb_reg(hw,
1951 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1952 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1958 * ixgbe_set_master_slave_mode - Set up PHY for master/slave mode
1959 * @hw: pointer to hardware structure
1961 * Must be called while holding the PHY semaphore and token
1963 static s32 ixgbe_set_master_slave_mode(struct ixgbe_hw *hw)
1968 /* Resolve master/slave mode */
1969 rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_M88E1500_1000T_CTRL, 0,
1974 /* load defaults for future use */
1975 if (phy_data & IXGBE_M88E1500_1000T_CTRL_MS_ENABLE) {
1976 if (phy_data & IXGBE_M88E1500_1000T_CTRL_MS_VALUE)
1977 hw->phy.original_ms_type = ixgbe_ms_force_master;
1979 hw->phy.original_ms_type = ixgbe_ms_force_slave;
1981 hw->phy.original_ms_type = ixgbe_ms_auto;
1984 switch (hw->phy.ms_type) {
1985 case ixgbe_ms_force_master:
1986 phy_data |= IXGBE_M88E1500_1000T_CTRL_MS_ENABLE;
1987 phy_data |= IXGBE_M88E1500_1000T_CTRL_MS_VALUE;
1989 case ixgbe_ms_force_slave:
1990 phy_data |= IXGBE_M88E1500_1000T_CTRL_MS_ENABLE;
1991 phy_data &= ~IXGBE_M88E1500_1000T_CTRL_MS_VALUE;
1994 phy_data &= ~IXGBE_M88E1500_1000T_CTRL_MS_ENABLE;
2000 return ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_1000T_CTRL, 0,
2005 * ixgbe_reset_phy_m88_nolock - Reset m88 PHY without locking
2006 * @hw: pointer to hardware structure
2008 * Must be called while holding the PHY semaphore and token
2010 static s32 ixgbe_reset_phy_m88_nolock(struct ixgbe_hw *hw)
2014 rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2018 rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_FIBER_CTRL, 0,
2019 IXGBE_M88E1500_FIBER_CTRL_RESET |
2020 IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2021 IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB);
2025 rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 18);
2029 rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_GEN_CTRL, 0,
2030 IXGBE_M88E1500_GEN_CTRL_RESET |
2031 IXGBE_M88E1500_GEN_CTRL_SGMII_COPPER);
2035 rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2039 rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2040 IXGBE_M88E1500_COPPER_CTRL_RESET |
2041 IXGBE_M88E1500_COPPER_CTRL_AN_EN |
2042 IXGBE_M88E1500_COPPER_CTRL_RESTART_AN |
2043 IXGBE_M88E1500_COPPER_CTRL_FULL_DUPLEX |
2044 IXGBE_M88E1500_COPPER_CTRL_SPEED_MSB);
2047 ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2052 * ixgbe_reset_phy_m88 - Reset m88 PHY
2053 * @hw: pointer to hardware structure
2055 static s32 ixgbe_reset_phy_m88(struct ixgbe_hw *hw)
2057 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2060 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2061 return IXGBE_SUCCESS;
2063 rc = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
2067 rc = ixgbe_reset_phy_m88_nolock(hw);
2069 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2074 * ixgbe_setup_m88 - setup m88 PHY
2075 * @hw: pointer to hardware structure
2077 static s32 ixgbe_setup_m88(struct ixgbe_hw *hw)
2079 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2080 struct ixgbe_phy_info *phy = &hw->phy;
2084 if (phy->reset_disable || ixgbe_check_reset_blocked(hw))
2085 return IXGBE_SUCCESS;
2087 rc = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
2091 rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_M88E1500_PHY_SPEC_CTRL, 0,
2096 /* Enable downshift and setting it to X6 */
2097 phy_data &= ~IXGBE_M88E1500_PSCR_DOWNSHIFT_ENABLE;
2098 phy_data |= IXGBE_M88E1500_PSCR_DOWNSHIFT_6X;
2099 phy_data |= IXGBE_M88E1500_PSCR_DOWNSHIFT_ENABLE;
2100 rc = ixgbe_write_phy_reg_mdi_22(hw,
2101 IXGBE_M88E1500_PHY_SPEC_CTRL, 0,
2106 ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2108 /* Commit the changes */
2109 rc = ixgbe_reset_phy_m88_nolock(hw);
2111 DEBUGOUT("Error committing the PHY changes\n");
2115 rc = ixgbe_set_master_slave_mode(hw);
2117 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2121 ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2122 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2127 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2128 * @hw: pointer to hardware structure
2130 * Read NW_MNG_IF_SEL register and save field values, and check for valid field
2133 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2135 /* Save NW management interface connected on board. This is used
2136 * to determine internal PHY mode.
2138 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2140 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2141 * PHY address. This register field was has only been used for X552.
2143 if (hw->mac.type == ixgbe_mac_X550EM_a &&
2144 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2145 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2146 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2147 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2150 return IXGBE_SUCCESS;
2154 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2155 * @hw: pointer to hardware structure
2157 * Initialize any function pointers that were not able to be
2158 * set during init_shared_code because the PHY/SFP type was
2159 * not known. Perform the SFP init if necessary.
2161 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2163 struct ixgbe_phy_info *phy = &hw->phy;
2166 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2168 hw->mac.ops.set_lan_id(hw);
2170 ixgbe_read_mng_if_sel_x550em(hw);
2172 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2173 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2174 ixgbe_setup_mux_ctl(hw);
2175 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2178 /* Identify the PHY or SFP module */
2179 ret_val = phy->ops.identify(hw);
2180 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
2183 /* Setup function pointers based on detected hardware */
2184 ixgbe_init_mac_link_ops_X550em(hw);
2185 if (phy->sfp_type != ixgbe_sfp_type_unknown)
2186 phy->ops.reset = NULL;
2188 /* Set functions pointers based on phy type */
2189 switch (hw->phy.type) {
2190 case ixgbe_phy_x550em_kx4:
2191 phy->ops.setup_link = NULL;
2192 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2193 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2195 case ixgbe_phy_x550em_kr:
2196 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2197 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2198 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2200 case ixgbe_phy_x550em_ext_t:
2201 /* If internal link mode is XFI, then setup iXFI internal link,
2202 * else setup KR now.
2204 phy->ops.setup_internal_link =
2205 ixgbe_setup_internal_phy_t_x550em;
2207 /* setup SW LPLU only for first revision of X550EM_x */
2208 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2209 !(IXGBE_FUSES0_REV_MASK &
2210 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2211 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2213 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2214 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2216 case ixgbe_phy_sgmii:
2217 phy->ops.setup_link = NULL;
2220 phy->ops.setup_link = ixgbe_setup_m88;
2221 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2222 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2223 phy->ops.reset = ixgbe_reset_phy_m88;
2232 * ixgbe_set_mdio_speed - Set MDIO clock speed
2233 * @hw: pointer to hardware structure
2235 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2239 switch (hw->device_id) {
2240 case IXGBE_DEV_ID_X550EM_X_10G_T:
2241 case IXGBE_DEV_ID_X550EM_A_SGMII:
2242 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2243 case IXGBE_DEV_ID_X550EM_A_1G_T:
2244 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2245 case IXGBE_DEV_ID_X550EM_A_10G_T:
2246 case IXGBE_DEV_ID_X550EM_A_SFP:
2247 case IXGBE_DEV_ID_X550EM_A_QSFP:
2248 /* Config MDIO clock speed before the first MDIO PHY access */
2249 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2250 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2251 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2259 * ixgbe_reset_hw_X550em - Perform hardware reset
2260 * @hw: pointer to hardware structure
2262 * Resets the hardware by resetting the transmit and receive units, masks
2263 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2266 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2268 ixgbe_link_speed link_speed;
2272 bool link_up = false;
2274 DEBUGFUNC("ixgbe_reset_hw_X550em");
2276 /* Call adapter stop to disable Tx/Rx and clear interrupts */
2277 status = hw->mac.ops.stop_adapter(hw);
2278 if (status != IXGBE_SUCCESS)
2281 /* flush pending Tx transactions */
2282 ixgbe_clear_tx_pending(hw);
2284 ixgbe_set_mdio_speed(hw);
2286 /* PHY ops must be identified and initialized prior to reset */
2287 status = hw->phy.ops.init(hw);
2289 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2292 /* start the external PHY */
2293 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2294 status = ixgbe_init_ext_t_x550em(hw);
2299 /* Setup SFP module if there is one present. */
2300 if (hw->phy.sfp_setup_needed) {
2301 status = hw->mac.ops.setup_sfp(hw);
2302 hw->phy.sfp_setup_needed = false;
2305 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2309 if (!hw->phy.reset_disable && hw->phy.ops.reset)
2310 hw->phy.ops.reset(hw);
2313 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
2314 * If link reset is used when link is up, it might reset the PHY when
2315 * mng is using it. If link is down or the flag to force full link
2316 * reset is set, then perform link reset.
2318 ctrl = IXGBE_CTRL_LNK_RST;
2319 if (!hw->force_full_reset) {
2320 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2322 ctrl = IXGBE_CTRL_RST;
2325 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2326 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2327 IXGBE_WRITE_FLUSH(hw);
2329 /* Poll for reset bit to self-clear meaning reset is complete */
2330 for (i = 0; i < 10; i++) {
2332 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2333 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2337 if (ctrl & IXGBE_CTRL_RST_MASK) {
2338 status = IXGBE_ERR_RESET_FAILED;
2339 DEBUGOUT("Reset polling failed to complete.\n");
2344 /* Double resets are required for recovery from certain error
2345 * conditions. Between resets, it is necessary to stall to
2346 * allow time for any pending HW events to complete.
2348 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2349 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2353 /* Store the permanent mac address */
2354 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2356 /* Store MAC address from RAR0, clear receive address registers, and
2357 * clear the multicast table. Also reset num_rar_entries to 128,
2358 * since we modify this value when programming the SAN MAC address.
2360 hw->mac.num_rar_entries = 128;
2361 hw->mac.ops.init_rx_addrs(hw);
2363 ixgbe_set_mdio_speed(hw);
2365 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2366 ixgbe_setup_mux_ctl(hw);
2372 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2373 * @hw: pointer to hardware structure
2375 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2380 status = hw->phy.ops.read_reg(hw,
2381 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2382 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2385 if (status != IXGBE_SUCCESS)
2388 /* If PHY FW reset completed bit is set then this is the first
2389 * SW instance after a power on so the PHY FW must be un-stalled.
2391 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2392 status = hw->phy.ops.read_reg(hw,
2393 IXGBE_MDIO_GLOBAL_RES_PR_10,
2394 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2397 if (status != IXGBE_SUCCESS)
2400 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2402 status = hw->phy.ops.write_reg(hw,
2403 IXGBE_MDIO_GLOBAL_RES_PR_10,
2404 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2407 if (status != IXGBE_SUCCESS)
2415 * ixgbe_setup_kr_x550em - Configure the KR PHY.
2416 * @hw: pointer to hardware structure
2418 * Configures the integrated KR PHY for X550EM_x.
2420 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2422 if (hw->mac.type != ixgbe_mac_X550EM_x)
2423 return IXGBE_SUCCESS;
2425 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2429 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2430 * @hw: pointer to hardware structure
2432 * Configure the external PHY and the integrated KR PHY for SFP support.
2434 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2435 ixgbe_link_speed speed,
2436 bool autoneg_wait_to_complete)
2439 u16 reg_slice, reg_val;
2440 bool setup_linear = false;
2441 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2443 /* Check if SFP module is supported and linear */
2444 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2446 /* If no SFP module present, then return success. Return success since
2447 * there is no reason to configure CS4227 and SFP not present error is
2448 * not excepted in the setup MAC link flow.
2450 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2451 return IXGBE_SUCCESS;
2453 if (ret_val != IXGBE_SUCCESS)
2456 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2457 /* Configure CS4227 LINE side to 10G SR. */
2458 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
2459 (hw->bus.lan_id << 12);
2460 reg_val = IXGBE_CS4227_SPEED_10G;
2461 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2464 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2465 (hw->bus.lan_id << 12);
2466 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2467 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2470 /* Configure CS4227 for HOST connection rate then type. */
2471 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
2472 (hw->bus.lan_id << 12);
2473 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
2474 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
2475 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2478 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
2479 (hw->bus.lan_id << 12);
2481 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2483 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2484 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2487 /* Setup XFI internal link. */
2488 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2490 /* Configure internal PHY for KR/KX. */
2491 ixgbe_setup_kr_speed_x550em(hw, speed);
2493 /* Configure CS4227 LINE side to proper mode. */
2494 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2495 (hw->bus.lan_id << 12);
2497 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2499 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2500 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2507 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2508 * @hw: pointer to hardware structure
2510 * Configure the the integrated PHY for SFP support.
2512 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2513 ixgbe_link_speed speed,
2514 bool autoneg_wait_to_complete)
2518 bool setup_linear = false;
2519 u32 reg_slice, reg_phy_int, slice_offset;
2521 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2523 /* Check if SFP module is supported and linear */
2524 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2526 /* If no SFP module present, then return success. Return success since
2527 * SFP not present error is not excepted in the setup MAC link flow.
2529 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2530 return IXGBE_SUCCESS;
2532 if (ret_val != IXGBE_SUCCESS)
2535 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2536 /* Configure internal PHY for native SFI */
2537 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2538 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2539 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int);
2541 if (ret_val != IXGBE_SUCCESS)
2545 reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LIMITING;
2546 reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LINEAR;
2548 reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LIMITING;
2549 reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LINEAR;
2552 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2553 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2554 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2556 if (ret_val != IXGBE_SUCCESS)
2559 /* Setup XFI/SFI internal link. */
2560 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2562 /* Configure internal PHY for KR/KX. */
2563 ixgbe_setup_kr_speed_x550em(hw, speed);
2565 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2567 DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2568 return IXGBE_ERR_PHY_ADDR_INVALID;
2571 /* Get external PHY device id */
2572 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_GLOBAL_ID_MSB,
2573 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
2575 if (ret_val != IXGBE_SUCCESS)
2578 /* When configuring quad port CS4223, the MAC instance is part
2579 * of the slice offset.
2581 if (reg_phy_ext == IXGBE_CS4223_PHY_ID)
2582 slice_offset = (hw->bus.lan_id +
2583 (hw->bus.instance_id << 1)) << 12;
2585 slice_offset = hw->bus.lan_id << 12;
2587 /* Configure CS4227/CS4223 LINE side to proper mode. */
2588 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2590 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2592 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2593 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2594 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2600 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2601 * @hw: pointer to hardware structure
2603 * iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2605 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2610 /* Disable training protocol FSM. */
2611 status = ixgbe_read_iosf_sb_reg_x550(hw,
2612 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2613 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2614 if (status != IXGBE_SUCCESS)
2616 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2617 status = ixgbe_write_iosf_sb_reg_x550(hw,
2618 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2619 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2620 if (status != IXGBE_SUCCESS)
2623 /* Disable Flex from training TXFFE. */
2624 status = ixgbe_read_iosf_sb_reg_x550(hw,
2625 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2626 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2627 if (status != IXGBE_SUCCESS)
2629 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2630 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2631 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2632 status = ixgbe_write_iosf_sb_reg_x550(hw,
2633 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2634 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2635 if (status != IXGBE_SUCCESS)
2637 status = ixgbe_read_iosf_sb_reg_x550(hw,
2638 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2639 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2640 if (status != IXGBE_SUCCESS)
2642 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2643 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2644 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2645 status = ixgbe_write_iosf_sb_reg_x550(hw,
2646 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2647 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2648 if (status != IXGBE_SUCCESS)
2651 /* Enable override for coefficients. */
2652 status = ixgbe_read_iosf_sb_reg_x550(hw,
2653 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2654 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2655 if (status != IXGBE_SUCCESS)
2657 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2658 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2659 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2660 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2661 status = ixgbe_write_iosf_sb_reg_x550(hw,
2662 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2663 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2668 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2669 * @hw: pointer to hardware structure
2670 * @speed: the link speed to force
2672 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
2673 * internal and external PHY at a specific speed, without autonegotiation.
2675 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2680 /* Disable AN and force speed to 10G Serial. */
2681 status = ixgbe_read_iosf_sb_reg_x550(hw,
2682 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2683 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2684 if (status != IXGBE_SUCCESS)
2687 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2688 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2690 /* Select forced link speed for internal PHY. */
2692 case IXGBE_LINK_SPEED_10GB_FULL:
2693 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2695 case IXGBE_LINK_SPEED_1GB_FULL:
2696 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2699 /* Other link speeds are not supported by internal KR PHY. */
2700 return IXGBE_ERR_LINK_SETUP;
2703 status = ixgbe_write_iosf_sb_reg_x550(hw,
2704 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2705 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2706 if (status != IXGBE_SUCCESS)
2709 /* Additional configuration needed for x550em_x */
2710 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2711 status = ixgbe_setup_ixfi_x550em_x(hw);
2712 if (status != IXGBE_SUCCESS)
2716 /* Toggle port SW reset by AN reset. */
2717 status = ixgbe_read_iosf_sb_reg_x550(hw,
2718 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2719 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2720 if (status != IXGBE_SUCCESS)
2722 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2723 status = ixgbe_write_iosf_sb_reg_x550(hw,
2724 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2725 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2731 * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2732 * @hw: address of hardware structure
2733 * @link_up: address of boolean to indicate link status
2735 * Returns error code if unable to get link status.
2737 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2744 /* read this twice back to back to indicate current status */
2745 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2746 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2748 if (ret != IXGBE_SUCCESS)
2751 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2752 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2754 if (ret != IXGBE_SUCCESS)
2757 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2759 return IXGBE_SUCCESS;
2763 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2764 * @hw: point to hardware structure
2766 * Configures the link between the integrated KR PHY and the external X557 PHY
2767 * The driver will call this function when it gets a link status change
2768 * interrupt from the X557 PHY. This function configures the link speed
2769 * between the PHYs to match the link speed of the BASE-T link.
2771 * A return of a non-zero value indicates an error, and the base driver should
2772 * not report link up.
2774 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2776 ixgbe_link_speed force_speed;
2781 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2782 return IXGBE_ERR_CONFIG;
2784 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2785 /* If link is down, there is no setup necessary so return */
2786 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2787 if (status != IXGBE_SUCCESS)
2791 return IXGBE_SUCCESS;
2793 status = hw->phy.ops.read_reg(hw,
2794 IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2795 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2797 if (status != IXGBE_SUCCESS)
2800 /* If link is still down - no setup is required so return */
2801 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2802 if (status != IXGBE_SUCCESS)
2805 return IXGBE_SUCCESS;
2807 /* clear everything but the speed and duplex bits */
2808 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2811 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2812 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2814 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2815 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2818 /* Internal PHY does not support anything else */
2819 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2822 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2824 speed = IXGBE_LINK_SPEED_10GB_FULL |
2825 IXGBE_LINK_SPEED_1GB_FULL;
2826 return ixgbe_setup_kr_speed_x550em(hw, speed);
2831 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
2832 * @hw: pointer to hardware structure
2834 * Configures the integrated KR PHY to use internal loopback mode.
2836 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
2841 /* Disable AN and force speed to 10G Serial. */
2842 status = hw->mac.ops.read_iosf_sb_reg(hw,
2843 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2844 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2845 if (status != IXGBE_SUCCESS)
2847 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2848 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2849 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2850 status = hw->mac.ops.write_iosf_sb_reg(hw,
2851 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2852 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2853 if (status != IXGBE_SUCCESS)
2856 /* Set near-end loopback clocks. */
2857 status = hw->mac.ops.read_iosf_sb_reg(hw,
2858 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2859 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2860 if (status != IXGBE_SUCCESS)
2862 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2863 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2864 status = hw->mac.ops.write_iosf_sb_reg(hw,
2865 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2866 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2867 if (status != IXGBE_SUCCESS)
2870 /* Set loopback enable. */
2871 status = hw->mac.ops.read_iosf_sb_reg(hw,
2872 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2873 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2874 if (status != IXGBE_SUCCESS)
2876 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2877 status = hw->mac.ops.write_iosf_sb_reg(hw,
2878 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2879 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2880 if (status != IXGBE_SUCCESS)
2883 /* Training bypass. */
2884 status = hw->mac.ops.read_iosf_sb_reg(hw,
2885 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2886 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2887 if (status != IXGBE_SUCCESS)
2889 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2890 status = hw->mac.ops.write_iosf_sb_reg(hw,
2891 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2892 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2898 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2899 * assuming that the semaphore is already obtained.
2900 * @hw: pointer to hardware structure
2901 * @offset: offset of word in the EEPROM to read
2902 * @data: word read from the EEPROM
2904 * Reads a 16 bit word from the EEPROM using the hostif.
2906 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2910 struct ixgbe_hic_read_shadow_ram buffer;
2912 DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2913 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2914 buffer.hdr.req.buf_lenh = 0;
2915 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2916 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2918 /* convert offset from words to bytes */
2919 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2921 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2923 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2925 IXGBE_HI_COMMAND_TIMEOUT, false);
2930 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2931 FW_NVM_DATA_OFFSET);
2937 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2938 * @hw: pointer to hardware structure
2939 * @offset: offset of word in the EEPROM to read
2940 * @data: word read from the EEPROM
2942 * Reads a 16 bit word from the EEPROM using the hostif.
2944 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2947 s32 status = IXGBE_SUCCESS;
2949 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2951 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2953 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2954 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2956 status = IXGBE_ERR_SWFW_SYNC;
2963 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2964 * @hw: pointer to hardware structure
2965 * @offset: offset of word in the EEPROM to read
2966 * @words: number of words
2967 * @data: word(s) read from the EEPROM
2969 * Reads a 16 bit word(s) from the EEPROM using the hostif.
2971 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2972 u16 offset, u16 words, u16 *data)
2974 struct ixgbe_hic_read_shadow_ram buffer;
2975 u32 current_word = 0;
2980 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2982 /* Take semaphore for the entire operation. */
2983 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2985 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2989 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2990 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2992 words_to_read = words;
2994 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2995 buffer.hdr.req.buf_lenh = 0;
2996 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2997 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2999 /* convert offset from words to bytes */
3000 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3001 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3003 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3005 IXGBE_HI_COMMAND_TIMEOUT,
3009 DEBUGOUT("Host interface command failed\n");
3013 for (i = 0; i < words_to_read; i++) {
3014 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3016 u32 value = IXGBE_READ_REG(hw, reg);
3018 data[current_word] = (u16)(value & 0xffff);
3021 if (i < words_to_read) {
3023 data[current_word] = (u16)(value & 0xffff);
3027 words -= words_to_read;
3031 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3036 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3037 * @hw: pointer to hardware structure
3038 * @offset: offset of word in the EEPROM to write
3039 * @data: word write to the EEPROM
3041 * Write a 16 bit word to the EEPROM using the hostif.
3043 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3047 struct ixgbe_hic_write_shadow_ram buffer;
3049 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3051 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3052 buffer.hdr.req.buf_lenh = 0;
3053 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3054 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3057 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3059 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3061 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3063 IXGBE_HI_COMMAND_TIMEOUT, false);
3069 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3070 * @hw: pointer to hardware structure
3071 * @offset: offset of word in the EEPROM to write
3072 * @data: word write to the EEPROM
3074 * Write a 16 bit word to the EEPROM using the hostif.
3076 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3079 s32 status = IXGBE_SUCCESS;
3081 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3083 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3085 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3086 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3088 DEBUGOUT("write ee hostif failed to get semaphore");
3089 status = IXGBE_ERR_SWFW_SYNC;
3096 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3097 * @hw: pointer to hardware structure
3098 * @offset: offset of word in the EEPROM to write
3099 * @words: number of words
3100 * @data: word(s) write to the EEPROM
3102 * Write a 16 bit word(s) to the EEPROM using the hostif.
3104 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3105 u16 offset, u16 words, u16 *data)
3107 s32 status = IXGBE_SUCCESS;
3110 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3112 /* Take semaphore for the entire operation. */
3113 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3114 if (status != IXGBE_SUCCESS) {
3115 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3119 for (i = 0; i < words; i++) {
3120 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3123 if (status != IXGBE_SUCCESS) {
3124 DEBUGOUT("Eeprom buffered write failed\n");
3129 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3136 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3137 * @hw: pointer to hardware structure
3138 * @ptr: pointer offset in eeprom
3139 * @size: size of section pointed by ptr, if 0 first word will be used as size
3140 * @csum: address of checksum to update
3142 * Returns error status for any failure
3144 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3145 u16 size, u16 *csum, u16 *buffer,
3150 u16 length, bufsz, i, start;
3153 bufsz = sizeof(buf) / sizeof(buf[0]);
3155 /* Read a chunk at the pointer location */
3157 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3159 DEBUGOUT("Failed to read EEPROM image\n");
3164 if (buffer_size < ptr)
3165 return IXGBE_ERR_PARAM;
3166 local_buffer = &buffer[ptr];
3174 length = local_buffer[0];
3176 /* Skip pointer section if length is invalid. */
3177 if (length == 0xFFFF || length == 0 ||
3178 (ptr + length) >= hw->eeprom.word_size)
3179 return IXGBE_SUCCESS;
3182 if (buffer && ((u32)start + (u32)length > buffer_size))
3183 return IXGBE_ERR_PARAM;
3185 for (i = start; length; i++, length--) {
3186 if (i == bufsz && !buffer) {
3192 /* Read a chunk at the pointer location */
3193 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3196 DEBUGOUT("Failed to read EEPROM image\n");
3200 *csum += local_buffer[i];
3202 return IXGBE_SUCCESS;
3206 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3207 * @hw: pointer to hardware structure
3208 * @buffer: pointer to buffer containing calculated checksum
3209 * @buffer_size: size of buffer
3211 * Returns a negative error code on error, or the 16-bit checksum
3213 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3215 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3219 u16 pointer, i, size;
3221 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3223 hw->eeprom.ops.init_params(hw);
3226 /* Read pointer area */
3227 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3228 IXGBE_EEPROM_LAST_WORD + 1,
3231 DEBUGOUT("Failed to read EEPROM image\n");
3234 local_buffer = eeprom_ptrs;
3236 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3237 return IXGBE_ERR_PARAM;
3238 local_buffer = buffer;
3242 * For X550 hardware include 0x0-0x41 in the checksum, skip the
3243 * checksum word itself
3245 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3246 if (i != IXGBE_EEPROM_CHECKSUM)
3247 checksum += local_buffer[i];
3250 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
3251 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3253 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3254 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3257 pointer = local_buffer[i];
3259 /* Skip pointer section if the pointer is invalid. */
3260 if (pointer == 0xFFFF || pointer == 0 ||
3261 pointer >= hw->eeprom.word_size)
3265 case IXGBE_PCIE_GENERAL_PTR:
3266 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3268 case IXGBE_PCIE_CONFIG0_PTR:
3269 case IXGBE_PCIE_CONFIG1_PTR:
3270 size = IXGBE_PCIE_CONFIG_SIZE;
3277 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3278 buffer, buffer_size);
3283 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3285 return (s32)checksum;
3289 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3290 * @hw: pointer to hardware structure
3292 * Returns a negative error code on error, or the 16-bit checksum
3294 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3296 return ixgbe_calc_checksum_X550(hw, NULL, 0);
3300 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3301 * @hw: pointer to hardware structure
3302 * @checksum_val: calculated checksum
3304 * Performs checksum calculation and validates the EEPROM checksum. If the
3305 * caller does not need checksum_val, the value can be NULL.
3307 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3311 u16 read_checksum = 0;
3313 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3315 /* Read the first word from the EEPROM. If this times out or fails, do
3316 * not continue or we could be in for a very long wait while every
3319 status = hw->eeprom.ops.read(hw, 0, &checksum);
3321 DEBUGOUT("EEPROM read failed\n");
3325 status = hw->eeprom.ops.calc_checksum(hw);
3329 checksum = (u16)(status & 0xffff);
3331 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3336 /* Verify read checksum from EEPROM is the same as
3337 * calculated checksum
3339 if (read_checksum != checksum) {
3340 status = IXGBE_ERR_EEPROM_CHECKSUM;
3341 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3342 "Invalid EEPROM checksum");
3345 /* If the user cares, return the calculated checksum */
3347 *checksum_val = checksum;
3353 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3354 * @hw: pointer to hardware structure
3356 * After writing EEPROM to shadow RAM using EEWR register, software calculates
3357 * checksum and updates the EEPROM and instructs the hardware to update
3360 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3365 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3367 /* Read the first word from the EEPROM. If this times out or fails, do
3368 * not continue or we could be in for a very long wait while every
3371 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3373 DEBUGOUT("EEPROM read failed\n");
3377 status = ixgbe_calc_eeprom_checksum_X550(hw);
3381 checksum = (u16)(status & 0xffff);
3383 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3388 status = ixgbe_update_flash_X550(hw);
3394 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3395 * @hw: pointer to hardware structure
3397 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3399 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3401 s32 status = IXGBE_SUCCESS;
3402 union ixgbe_hic_hdr2 buffer;
3404 DEBUGFUNC("ixgbe_update_flash_X550");
3406 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3407 buffer.req.buf_lenh = 0;
3408 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3409 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3411 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3413 IXGBE_HI_COMMAND_TIMEOUT, false);
3419 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3420 * @hw: pointer to hardware structure
3422 * Determines physical layer capabilities of the current configuration.
3424 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3426 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3427 u16 ext_ability = 0;
3429 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3431 hw->phy.ops.identify(hw);
3433 switch (hw->phy.type) {
3434 case ixgbe_phy_x550em_kr:
3435 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3436 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3438 case ixgbe_phy_x550em_kx4:
3439 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3440 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3442 case ixgbe_phy_x550em_ext_t:
3443 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3444 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3446 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3447 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3448 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3449 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3455 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3456 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3458 return physical_layer;
3462 * ixgbe_get_bus_info_x550em - Set PCI bus info
3463 * @hw: pointer to hardware structure
3465 * Sets bus link width and speed to unknown because X550em is
3468 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3471 DEBUGFUNC("ixgbe_get_bus_info_x550em");
3473 hw->bus.width = ixgbe_bus_width_unknown;
3474 hw->bus.speed = ixgbe_bus_speed_unknown;
3476 hw->mac.ops.set_lan_id(hw);
3478 return IXGBE_SUCCESS;
3482 * ixgbe_disable_rx_x550 - Disable RX unit
3484 * Enables the Rx DMA unit for x550
3486 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3488 u32 rxctrl, pfdtxgswc;
3490 struct ixgbe_hic_disable_rxen fw_cmd;
3492 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3494 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3495 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3496 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3497 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3498 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3499 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3500 hw->mac.set_lben = true;
3502 hw->mac.set_lben = false;
3505 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3506 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3507 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3508 fw_cmd.port_number = (u8)hw->bus.lan_id;
3510 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3511 sizeof(struct ixgbe_hic_disable_rxen),
3512 IXGBE_HI_COMMAND_TIMEOUT, true);
3514 /* If we fail - disable RX using register write */
3516 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3517 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3518 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3519 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3526 * ixgbe_enter_lplu_x550em - Transition to low power states
3527 * @hw: pointer to hardware structure
3529 * Configures Low Power Link Up on transition to low power states
3530 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3531 * X557 PHY immediately prior to entering LPLU.
3533 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3535 u16 an_10g_cntl_reg, autoneg_reg, speed;
3537 ixgbe_link_speed lcd_speed;
3541 /* SW LPLU not required on later HW revisions. */
3542 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3543 (IXGBE_FUSES0_REV_MASK &
3544 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3545 return IXGBE_SUCCESS;
3547 /* If blocked by MNG FW, then don't restart AN */
3548 if (ixgbe_check_reset_blocked(hw))
3549 return IXGBE_SUCCESS;
3551 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3552 if (status != IXGBE_SUCCESS)
3555 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3557 if (status != IXGBE_SUCCESS)
3560 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3561 * disabled, then force link down by entering low power mode.
3563 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3564 !(hw->wol_enabled || ixgbe_mng_present(hw)))
3565 return ixgbe_set_copper_phy_power(hw, FALSE);
3568 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3570 if (status != IXGBE_SUCCESS)
3573 /* If no valid LCD link speed, then force link down and exit. */
3574 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3575 return ixgbe_set_copper_phy_power(hw, FALSE);
3577 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3578 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3581 if (status != IXGBE_SUCCESS)
3584 /* If no link now, speed is invalid so take link down */
3585 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3586 if (status != IXGBE_SUCCESS)
3587 return ixgbe_set_copper_phy_power(hw, false);
3589 /* clear everything but the speed bits */
3590 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3592 /* If current speed is already LCD, then exit. */
3593 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3594 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3595 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3596 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3599 /* Clear AN completed indication */
3600 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3601 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3604 if (status != IXGBE_SUCCESS)
3607 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3608 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3611 if (status != IXGBE_SUCCESS)
3614 status = hw->phy.ops.read_reg(hw,
3615 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3616 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3619 if (status != IXGBE_SUCCESS)
3622 save_autoneg = hw->phy.autoneg_advertised;
3624 /* Setup link at least common link speed */
3625 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3627 /* restore autoneg from before setting lplu speed */
3628 hw->phy.autoneg_advertised = save_autoneg;
3634 * ixgbe_get_lcd_x550em - Determine lowest common denominator
3635 * @hw: pointer to hardware structure
3636 * @lcd_speed: pointer to lowest common link speed
3638 * Determine lowest common link speed with link partner.
3640 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3644 u16 word = hw->eeprom.ctrl_word_3;
3646 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3648 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3649 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3652 if (status != IXGBE_SUCCESS)
3655 /* If link partner advertised 1G, return 1G */
3656 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3657 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3661 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3662 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3663 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3666 /* Link partner not capable of lower speeds, return 10G */
3667 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3672 * ixgbe_setup_fc_X550em - Set up flow control
3673 * @hw: pointer to hardware structure
3675 * Called at init time to set up flow control.
3677 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3679 s32 ret_val = IXGBE_SUCCESS;
3680 u32 pause, asm_dir, reg_val;
3682 DEBUGFUNC("ixgbe_setup_fc_X550em");
3684 /* Validate the requested mode */
3685 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3686 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3687 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3688 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3692 /* 10gig parts do not have a word in the EEPROM to determine the
3693 * default flow control setting, so we explicitly set it to full.
3695 if (hw->fc.requested_mode == ixgbe_fc_default)
3696 hw->fc.requested_mode = ixgbe_fc_full;
3698 /* Determine PAUSE and ASM_DIR bits. */
3699 switch (hw->fc.requested_mode) {
3704 case ixgbe_fc_tx_pause:
3708 case ixgbe_fc_rx_pause:
3709 /* Rx Flow control is enabled and Tx Flow control is
3710 * disabled by software override. Since there really
3711 * isn't a way to advertise that we are capable of RX
3712 * Pause ONLY, we will advertise that we support both
3713 * symmetric and asymmetric Rx PAUSE, as such we fall
3714 * through to the fc_full statement. Later, we will
3715 * disable the adapter's ability to send PAUSE frames.
3722 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3723 "Flow control param set incorrectly\n");
3724 ret_val = IXGBE_ERR_CONFIG;
3728 switch (hw->device_id) {
3729 case IXGBE_DEV_ID_X550EM_X_KR:
3730 case IXGBE_DEV_ID_X550EM_A_KR:
3731 case IXGBE_DEV_ID_X550EM_A_KR_L:
3732 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
3733 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3734 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3735 if (ret_val != IXGBE_SUCCESS)
3737 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3738 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3740 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3742 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3743 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
3744 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3745 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3747 /* This device does not fully support AN. */
3748 hw->fc.disable_fc_autoneg = true;
3759 * ixgbe_set_mux - Set mux for port 1 access with CS4227
3760 * @hw: pointer to hardware structure
3761 * @state: set mux if 1, clear if 0
3763 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
3767 if (!hw->bus.lan_id)
3769 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3771 esdp |= IXGBE_ESDP_SDP1;
3773 esdp &= ~IXGBE_ESDP_SDP1;
3774 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
3775 IXGBE_WRITE_FLUSH(hw);
3779 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
3780 * @hw: pointer to hardware structure
3781 * @mask: Mask to specify which semaphore to acquire
3783 * Acquires the SWFW semaphore and sets the I2C MUX
3785 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3789 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
3791 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
3795 if (mask & IXGBE_GSSR_I2C_MASK)
3796 ixgbe_set_mux(hw, 1);
3798 return IXGBE_SUCCESS;
3802 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
3803 * @hw: pointer to hardware structure
3804 * @mask: Mask to specify which semaphore to release
3806 * Releases the SWFW semaphore and sets the I2C MUX
3808 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3810 DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
3812 if (mask & IXGBE_GSSR_I2C_MASK)
3813 ixgbe_set_mux(hw, 0);
3815 ixgbe_release_swfw_sync_X540(hw, mask);
3819 * ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
3820 * @hw: pointer to hardware structure
3821 * @mask: Mask to specify which semaphore to acquire
3823 * Acquires the SWFW semaphore and get the shared phy token as needed
3825 static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
3827 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3828 int retries = FW_PHY_TOKEN_RETRIES;
3829 s32 status = IXGBE_SUCCESS;
3831 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
3834 status = IXGBE_SUCCESS;
3836 status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
3839 if (!(mask & IXGBE_GSSR_TOKEN_SM))
3840 return IXGBE_SUCCESS;
3842 status = ixgbe_get_phy_token(hw);
3843 if (status == IXGBE_SUCCESS)
3844 return IXGBE_SUCCESS;
3847 ixgbe_release_swfw_sync_X540(hw, hmask);
3848 if (status != IXGBE_ERR_TOKEN_RETRY)
3850 msec_delay(FW_PHY_TOKEN_DELAY);
3857 * ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
3858 * @hw: pointer to hardware structure
3859 * @mask: Mask to specify which semaphore to release
3861 * Releases the SWFW semaphore and puts the shared phy token as needed
3863 static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
3865 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3867 DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
3869 if (mask & IXGBE_GSSR_TOKEN_SM)
3870 ixgbe_put_phy_token(hw);
3873 ixgbe_release_swfw_sync_X540(hw, hmask);
3877 * ixgbe_read_phy_reg_x550a - Reads specified PHY register
3878 * @hw: pointer to hardware structure
3879 * @reg_addr: 32 bit address of PHY register to read
3880 * @phy_data: Pointer to read data from PHY register
3882 * Reads a value from a specified PHY register using the SWFW lock and PHY
3883 * Token. The PHY Token is needed since the MDIO is shared between to MAC
3886 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
3887 u32 device_type, u16 *phy_data)
3890 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
3892 DEBUGFUNC("ixgbe_read_phy_reg_x550a");
3894 if (hw->mac.ops.acquire_swfw_sync(hw, mask))
3895 return IXGBE_ERR_SWFW_SYNC;
3897 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
3899 hw->mac.ops.release_swfw_sync(hw, mask);
3905 * ixgbe_write_phy_reg_x550a - Writes specified PHY register
3906 * @hw: pointer to hardware structure
3907 * @reg_addr: 32 bit PHY register to write
3908 * @device_type: 5 bit device type
3909 * @phy_data: Data to write to the PHY register
3911 * Writes a value to specified PHY register using the SWFW lock and PHY Token.
3912 * The PHY Token is needed since the MDIO is shared between to MAC instances.
3914 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
3915 u32 device_type, u16 phy_data)
3918 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
3920 DEBUGFUNC("ixgbe_write_phy_reg_x550a");
3922 if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
3923 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
3925 hw->mac.ops.release_swfw_sync(hw, mask);
3927 status = IXGBE_ERR_SWFW_SYNC;
3934 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
3935 * @hw: pointer to hardware structure
3937 * Handle external Base T PHY interrupt. If high temperature
3938 * failure alarm then return error, else if link status change
3939 * then setup internal/external PHY link
3941 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
3942 * failure alarm, else return PHY access status.
3944 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
3949 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
3951 if (status != IXGBE_SUCCESS)
3955 return ixgbe_setup_internal_phy(hw);
3957 return IXGBE_SUCCESS;
3961 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
3962 * @hw: pointer to hardware structure
3963 * @speed: new link speed
3964 * @autoneg_wait_to_complete: true when waiting for completion is needed
3966 * Setup internal/external PHY link speed based on link speed, then set
3967 * external PHY auto advertised link speed.
3969 * Returns error status for any failure
3971 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
3972 ixgbe_link_speed speed,
3973 bool autoneg_wait_to_complete)
3976 ixgbe_link_speed force_speed;
3978 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
3980 /* Setup internal/external PHY link speed to iXFI (10G), unless
3981 * only 1G is auto advertised then setup KX link.
3983 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
3984 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3986 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3988 /* If internal link mode is XFI, then setup XFI internal link. */
3989 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3990 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
3992 if (status != IXGBE_SUCCESS)
3996 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4000 * ixgbe_check_link_t_X550em - Determine link and speed status
4001 * @hw: pointer to hardware structure
4002 * @speed: pointer to link speed
4003 * @link_up: true when link is up
4004 * @link_up_wait_to_complete: bool used to wait for link up or not
4006 * Check that both the MAC and X557 external PHY have link.
4008 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4009 bool *link_up, bool link_up_wait_to_complete)
4014 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4015 return IXGBE_ERR_CONFIG;
4017 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4018 link_up_wait_to_complete);
4020 /* If check link fails or MAC link is not up, then return */
4021 if (status != IXGBE_SUCCESS || !(*link_up))
4024 /* MAC link is up, so check external PHY link.
4025 * Read this twice back to back to indicate current status.
4027 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4028 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4031 if (status != IXGBE_SUCCESS)
4034 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4035 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4038 if (status != IXGBE_SUCCESS)
4041 /* If external PHY link is not up, then indicate link not up */
4042 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4045 return IXGBE_SUCCESS;
4049 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4050 * @hw: pointer to hardware structure
4052 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4056 status = ixgbe_reset_phy_generic(hw);
4058 if (status != IXGBE_SUCCESS)
4061 /* Configure Link Status Alarm and Temperature Threshold interrupts */
4062 return ixgbe_enable_lasi_ext_t_x550em(hw);
4066 * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4067 * @hw: pointer to hardware structure
4068 * @led_idx: led number to turn on
4070 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4074 DEBUGFUNC("ixgbe_led_on_t_X550em");
4076 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4077 return IXGBE_ERR_PARAM;
4079 /* To turn on the LED, set mode to ON. */
4080 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4081 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4082 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4083 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4084 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4086 return IXGBE_SUCCESS;
4090 * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4091 * @hw: pointer to hardware structure
4092 * @led_idx: led number to turn off
4094 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4098 DEBUGFUNC("ixgbe_led_off_t_X550em");
4100 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4101 return IXGBE_ERR_PARAM;
4103 /* To turn on the LED, set mode to ON. */
4104 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4105 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4106 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4107 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4108 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4110 return IXGBE_SUCCESS;