drivers/net/ixgbe/base/ixgbe_x550.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2018
   3  */
   4
   5 #include "ixgbe_x550.h"
   6 #include "ixgbe_x540.h"
   7 #include "ixgbe_type.h"
   8 #include "ixgbe_api.h"
   9 #include "ixgbe_common.h"
  10 #include "ixgbe_phy.h"
  11
  12 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  13 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  14 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  15 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw);
  16
  17 /**
  18  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  19  *  @hw: pointer to hardware structure
  20  *
  21  *  Initialize the function pointers and assign the MAC type for X550.
  22  *  Does not touch the hardware.
  23  **/
  24 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  25 {
  26         struct ixgbe_mac_info *mac = &hw->mac;
  27         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  28         s32 ret_val;
  29
  30         DEBUGFUNC("ixgbe_init_ops_X550");
  31
  32         ret_val = ixgbe_init_ops_X540(hw);
  33         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  34         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  35         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  36         mac->ops.setup_eee = NULL;
  37         mac->ops.set_source_address_pruning =
  38                         ixgbe_set_source_address_pruning_X550;
  39         mac->ops.set_ethertype_anti_spoofing =
  40                         ixgbe_set_ethertype_anti_spoofing_X550;
  41
  42         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  43         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  44         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  45         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  46         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  47         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  48         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  49         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  50         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  51
  52         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  53         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  54         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  55         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  56         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  57         /* Manageability interface */
  58         mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_x550;
  59         switch (hw->device_id) {
  60         case IXGBE_DEV_ID_X550EM_X_1G_T:
  61                 hw->mac.ops.led_on = NULL;
  62                 hw->mac.ops.led_off = NULL;
  63                 break;
  64         case IXGBE_DEV_ID_X550EM_X_10G_T:
  65         case IXGBE_DEV_ID_X550EM_A_10G_T:
  66                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  67                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  68                 break;
  69         default:
  70                 break;
  71         }
  72         return ret_val;
  73 }
  74
  75 /**
  76  * ixgbe_read_cs4227 - Read CS4227 register
  77  * @hw: pointer to hardware structure
  78  * @reg: register number to write
  79  * @value: pointer to receive value read
  80  *
  81  * Returns status code
  82  **/
  83 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  84 {
  85         return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
  86 }
  87
  88 /**
  89  * ixgbe_write_cs4227 - Write CS4227 register
  90  * @hw: pointer to hardware structure
  91  * @reg: register number to write
  92  * @value: value to write to register
  93  *
  94  * Returns status code
  95  **/
  96 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
  97 {
  98         return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
  99 }
 100
 101 /**
 102  * ixgbe_read_pe - Read register from port expander
 103  * @hw: pointer to hardware structure
 104  * @reg: register number to read
 105  * @value: pointer to receive read value
 106  *
 107  * Returns status code
 108  **/
 109 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 110 {
 111         s32 status;
 112
 113         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 114         if (status != IXGBE_SUCCESS)
 115                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 116                               "port expander access failed with %d\n", status);
 117         return status;
 118 }
 119
 120 /**
 121  * ixgbe_write_pe - Write register to port expander
 122  * @hw: pointer to hardware structure
 123  * @reg: register number to write
 124  * @value: value to write
 125  *
 126  * Returns status code
 127  **/
 128 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 129 {
 130         s32 status;
 131
 132         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 133         if (status != IXGBE_SUCCESS)
 134                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 135                               "port expander access failed with %d\n", status);
 136         return status;
 137 }
 138
 139 /**
 140  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 141  * @hw: pointer to hardware structure
 142  *
 143  * This function assumes that the caller has acquired the proper semaphore.
 144  * Returns error code
 145  **/
 146 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 147 {
 148         s32 status;
 149         u32 retry;
 150         u16 value;
 151         u8 reg;
 152
 153         /* Trigger hard reset. */
 154         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 155         if (status != IXGBE_SUCCESS)
 156                 return status;
 157         reg |= IXGBE_PE_BIT1;
 158         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 159         if (status != IXGBE_SUCCESS)
 160                 return status;
 161
 162         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 163         if (status != IXGBE_SUCCESS)
 164                 return status;
 165         reg &= ~IXGBE_PE_BIT1;
 166         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 167         if (status != IXGBE_SUCCESS)
 168                 return status;
 169
 170         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 171         if (status != IXGBE_SUCCESS)
 172                 return status;
 173         reg &= ~IXGBE_PE_BIT1;
 174         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 175         if (status != IXGBE_SUCCESS)
 176                 return status;
 177
 178         usec_delay(IXGBE_CS4227_RESET_HOLD);
 179
 180         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 181         if (status != IXGBE_SUCCESS)
 182                 return status;
 183         reg |= IXGBE_PE_BIT1;
 184         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 185         if (status != IXGBE_SUCCESS)
 186                 return status;
 187
 188         /* Wait for the reset to complete. */
 189         msec_delay(IXGBE_CS4227_RESET_DELAY);
 190         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 191                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 192                                            &value);
 193                 if (status == IXGBE_SUCCESS &&
 194                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 195                         break;
 196                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 197         }
 198         if (retry == IXGBE_CS4227_RETRIES) {
 199                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 200                         "CS4227 reset did not complete.");
 201                 return IXGBE_ERR_PHY;
 202         }
 203
 204         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 205         if (status != IXGBE_SUCCESS ||
 206             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 207                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 208                         "CS4227 EEPROM did not load successfully.");
 209                 return IXGBE_ERR_PHY;
 210         }
 211
 212         return IXGBE_SUCCESS;
 213 }
 214
 215 /**
 216  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 217  * @hw: pointer to hardware structure
 218  **/
 219 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 220 {
 221         s32 status = IXGBE_SUCCESS;
 222         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 223         u16 value = 0;
 224         u8 retry;
 225
 226         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 227                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 228                 if (status != IXGBE_SUCCESS) {
 229                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 230                                 "semaphore failed with %d", status);
 231                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 232                         continue;
 233                 }
 234
 235                 /* Get status of reset flow. */
 236                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 237
 238                 if (status == IXGBE_SUCCESS &&
 239                     value == IXGBE_CS4227_RESET_COMPLETE)
 240                         goto out;
 241
 242                 if (status != IXGBE_SUCCESS ||
 243                     value != IXGBE_CS4227_RESET_PENDING)
 244                         break;
 245
 246                 /* Reset is pending. Wait and check again. */
 247                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 248                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 249         }
 250
 251         /* If still pending, assume other instance failed. */
 252         if (retry == IXGBE_CS4227_RETRIES) {
 253                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 254                 if (status != IXGBE_SUCCESS) {
 255                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 256                                       "semaphore failed with %d", status);
 257                         return;
 258                 }
 259         }
 260
 261         /* Reset the CS4227. */
 262         status = ixgbe_reset_cs4227(hw);
 263         if (status != IXGBE_SUCCESS) {
 264                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 265                         "CS4227 reset failed: %d", status);
 266                 goto out;
 267         }
 268
 269         /* Reset takes so long, temporarily release semaphore in case the
 270          * other driver instance is waiting for the reset indication.
 271          */
 272         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 273                            IXGBE_CS4227_RESET_PENDING);
 274         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 275         msec_delay(10);
 276         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 277         if (status != IXGBE_SUCCESS) {
 278                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 279                         "semaphore failed with %d", status);
 280                 return;
 281         }
 282
 283         /* Record completion for next time. */
 284         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 285                 IXGBE_CS4227_RESET_COMPLETE);
 286
 287 out:
 288         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 289         msec_delay(hw->eeprom.semaphore_delay);
 290 }
 291
 292 /**
 293  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 294  * @hw: pointer to hardware structure
 295  **/
 296 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 297 {
 298         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 299
 300         if (hw->bus.lan_id) {
 301                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 302                 esdp |= IXGBE_ESDP_SDP1_DIR;
 303         }
 304         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 305         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 306         IXGBE_WRITE_FLUSH(hw);
 307 }
 308
 309 /**
 310  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 311  * @hw: pointer to hardware structure
 312  *
 313  * Returns error code
 314  */
 315 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 316 {
 317         hw->mac.ops.set_lan_id(hw);
 318
 319         ixgbe_read_mng_if_sel_x550em(hw);
 320
 321         switch (hw->device_id) {
 322         case IXGBE_DEV_ID_X550EM_A_SFP:
 323                 return ixgbe_identify_module_generic(hw);
 324         case IXGBE_DEV_ID_X550EM_X_SFP:
 325                 /* set up for CS4227 usage */
 326                 ixgbe_setup_mux_ctl(hw);
 327                 ixgbe_check_cs4227(hw);
 328                 /* Fallthrough */
 329
 330         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 331                 return ixgbe_identify_module_generic(hw);
 332                 break;
 333         case IXGBE_DEV_ID_X550EM_X_KX4:
 334                 hw->phy.type = ixgbe_phy_x550em_kx4;
 335                 break;
 336         case IXGBE_DEV_ID_X550EM_X_XFI:
 337                 hw->phy.type = ixgbe_phy_x550em_xfi;
 338                 break;
 339         case IXGBE_DEV_ID_X550EM_X_KR:
 340         case IXGBE_DEV_ID_X550EM_A_KR:
 341         case IXGBE_DEV_ID_X550EM_A_KR_L:
 342                 hw->phy.type = ixgbe_phy_x550em_kr;
 343                 break;
 344         case IXGBE_DEV_ID_X550EM_A_10G_T:
 345         case IXGBE_DEV_ID_X550EM_X_10G_T:
 346                 return ixgbe_identify_phy_generic(hw);
 347         case IXGBE_DEV_ID_X550EM_X_1G_T:
 348                 hw->phy.type = ixgbe_phy_ext_1g_t;
 349                 break;
 350         case IXGBE_DEV_ID_X550EM_A_1G_T:
 351         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 352                 hw->phy.type = ixgbe_phy_fw;
 353                 if (hw->bus.lan_id)
 354                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 355                 else
 356                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 357                 break;
 358         default:
 359                 break;
 360         }
 361         return IXGBE_SUCCESS;
 362 }
 363
 364 /**
 365  * ixgbe_fw_phy_activity - Perform an activity on a PHY
 366  * @hw: pointer to hardware structure
 367  * @activity: activity to perform
 368  * @data: Pointer to 4 32-bit words of data
 369  */
 370 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,
 371                           u32 (*data)[FW_PHY_ACT_DATA_COUNT])
 372 {
 373         union {
 374                 struct ixgbe_hic_phy_activity_req cmd;
 375                 struct ixgbe_hic_phy_activity_resp rsp;
 376         } hic;
 377         u16 retries = FW_PHY_ACT_RETRIES;
 378         s32 rc;
 379         u16 i;
 380
 381         do {
 382                 memset(&hic, 0, sizeof(hic));
 383                 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD;
 384                 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN;
 385                 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 386                 hic.cmd.port_number = hw->bus.lan_id;
 387                 hic.cmd.activity_id = IXGBE_CPU_TO_LE16(activity);
 388                 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
 389                         hic.cmd.data[i] = IXGBE_CPU_TO_BE32((*data)[i]);
 390
 391                 rc = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
 392                                                   sizeof(hic.cmd),
 393                                                   IXGBE_HI_COMMAND_TIMEOUT,
 394                                                   true);
 395                 if (rc != IXGBE_SUCCESS)
 396                         return rc;
 397                 if (hic.rsp.hdr.cmd_or_resp.ret_status ==
 398                     FW_CEM_RESP_STATUS_SUCCESS) {
 399                         for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
 400                                 (*data)[i] = IXGBE_BE32_TO_CPU(hic.rsp.data[i]);
 401                         return IXGBE_SUCCESS;
 402                 }
 403                 usec_delay(20);
 404                 --retries;
 405         } while (retries > 0);
 406
 407         return IXGBE_ERR_HOST_INTERFACE_COMMAND;
 408 }
 409
 410 static const struct {
 411         u16 fw_speed;
 412         ixgbe_link_speed phy_speed;
 413 } ixgbe_fw_map[] = {
 414         { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL },
 415         { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL },
 416         { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL },
 417         { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL },
 418         { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL },
 419         { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL },
 420 };
 421
 422 /**
 423  * ixgbe_get_phy_id_fw - Get the phy ID via firmware command
 424  * @hw: pointer to hardware structure
 425  *
 426  * Returns error code
 427  */
 428 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw)
 429 {
 430         u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
 431         u16 phy_speeds;
 432         u16 phy_id_lo;
 433         s32 rc;
 434         u16 i;
 435
 436         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info);
 437         if (rc)
 438                 return rc;
 439
 440         hw->phy.speeds_supported = 0;
 441         phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK;
 442         for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
 443                 if (phy_speeds & ixgbe_fw_map[i].fw_speed)
 444                         hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed;
 445         }
 446         if (!hw->phy.autoneg_advertised)
 447                 hw->phy.autoneg_advertised = hw->phy.speeds_supported;
 448
 449         hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK;
 450         phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK;
 451         hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK;
 452         hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK;
 453         if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK)
 454                 return IXGBE_ERR_PHY_ADDR_INVALID;
 455         return IXGBE_SUCCESS;
 456 }
 457
 458 /**
 459  * ixgbe_identify_phy_fw - Get PHY type based on firmware command
 460  * @hw: pointer to hardware structure
 461  *
 462  * Returns error code
 463  */
 464 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw)
 465 {
 466         if (hw->bus.lan_id)
 467                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 468         else
 469                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 470
 471         hw->phy.type = ixgbe_phy_fw;
 472         hw->phy.ops.read_reg = NULL;
 473         hw->phy.ops.write_reg = NULL;
 474         return ixgbe_get_phy_id_fw(hw);
 475 }
 476
 477 /**
 478  * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY
 479  * @hw: pointer to hardware structure
 480  *
 481  * Returns error code
 482  */
 483 s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw)
 484 {
 485         u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
 486
 487         setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF;
 488         return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup);
 489 }
 490
 491 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 492                                      u32 device_type, u16 *phy_data)
 493 {
 494         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 495         return IXGBE_NOT_IMPLEMENTED;
 496 }
 497
 498 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 499                                       u32 device_type, u16 phy_data)
 500 {
 501         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 502         return IXGBE_NOT_IMPLEMENTED;
 503 }
 504
 505 /**
 506  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 507  * @hw: pointer to the hardware structure
 508  * @addr: I2C bus address to read from
 509  * @reg: I2C device register to read from
 510  * @val: pointer to location to receive read value
 511  *
 512  * Returns an error code on error.
 513  **/
 514 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 515                                            u16 reg, u16 *val)
 516 {
 517         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 518 }
 519
 520 /**
 521  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 522  * @hw: pointer to the hardware structure
 523  * @addr: I2C bus address to read from
 524  * @reg: I2C device register to read from
 525  * @val: pointer to location to receive read value
 526  *
 527  * Returns an error code on error.
 528  **/
 529 STATIC s32
 530 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 531                                          u16 reg, u16 *val)
 532 {
 533         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 534 }
 535
 536 /**
 537  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 538  * @hw: pointer to the hardware structure
 539  * @addr: I2C bus address to write to
 540  * @reg: I2C device register to write to
 541  * @val: value to write
 542  *
 543  * Returns an error code on error.
 544  **/
 545 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 546                                             u8 addr, u16 reg, u16 val)
 547 {
 548         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 549 }
 550
 551 /**
 552  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 553  * @hw: pointer to the hardware structure
 554  * @addr: I2C bus address to write to
 555  * @reg: I2C device register to write to
 556  * @val: value to write
 557  *
 558  * Returns an error code on error.
 559  **/
 560 STATIC s32
 561 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 562                                           u8 addr, u16 reg, u16 val)
 563 {
 564         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 565 }
 566
 567 /**
 568 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 569 *  @hw: pointer to hardware structure
 570 *
 571 *  Initialize the function pointers and for MAC type X550EM.
 572 *  Does not touch the hardware.
 573 **/
 574 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 575 {
 576         struct ixgbe_mac_info *mac = &hw->mac;
 577         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 578         struct ixgbe_phy_info *phy = &hw->phy;
 579         s32 ret_val;
 580
 581         DEBUGFUNC("ixgbe_init_ops_X550EM");
 582
 583         /* Similar to X550 so start there. */
 584         ret_val = ixgbe_init_ops_X550(hw);
 585
 586         /* Since this function eventually calls
 587          * ixgbe_init_ops_540 by design, we are setting
 588          * the pointers to NULL explicitly here to overwrite
 589          * the values being set in the x540 function.
 590          */
 591         /* Thermal sensor not supported in x550EM */
 592         mac->ops.get_thermal_sensor_data = NULL;
 593         mac->ops.init_thermal_sensor_thresh = NULL;
 594         mac->thermal_sensor_enabled = false;
 595
 596         /* FCOE not supported in x550EM */
 597         mac->ops.get_san_mac_addr = NULL;
 598         mac->ops.set_san_mac_addr = NULL;
 599         mac->ops.get_wwn_prefix = NULL;
 600         mac->ops.get_fcoe_boot_status = NULL;
 601
 602         /* IPsec not supported in x550EM */
 603         mac->ops.disable_sec_rx_path = NULL;
 604         mac->ops.enable_sec_rx_path = NULL;
 605
 606         /* AUTOC register is not present in x550EM. */
 607         mac->ops.prot_autoc_read = NULL;
 608         mac->ops.prot_autoc_write = NULL;
 609
 610         /* X550EM bus type is internal*/
 611         hw->bus.type = ixgbe_bus_type_internal;
 612         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 613
 614
 615         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 616         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 617         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 618         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 619         mac->ops.get_supported_physical_layer =
 620                                     ixgbe_get_supported_physical_layer_X550em;
 621
 622         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 623                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 624         else
 625                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 626
 627         /* PHY */
 628         phy->ops.init = ixgbe_init_phy_ops_X550em;
 629         switch (hw->device_id) {
 630         case IXGBE_DEV_ID_X550EM_A_1G_T:
 631         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 632                 mac->ops.setup_fc = NULL;
 633                 phy->ops.identify = ixgbe_identify_phy_fw;
 634                 phy->ops.set_phy_power = NULL;
 635                 phy->ops.get_firmware_version = NULL;
 636                 break;
 637         case IXGBE_DEV_ID_X550EM_X_1G_T:
 638                 mac->ops.setup_fc = NULL;
 639                 phy->ops.identify = ixgbe_identify_phy_x550em;
 640                 phy->ops.set_phy_power = NULL;
 641                 break;
 642         default:
 643                 phy->ops.identify = ixgbe_identify_phy_x550em;
 644         }
 645
 646         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 647                 phy->ops.set_phy_power = NULL;
 648
 649
 650         /* EEPROM */
 651         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 652         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 653         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 654         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 655         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 656         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 657         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 658         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 659
 660         return ret_val;
 661 }
 662
 663 /**
 664  * ixgbe_setup_fw_link - Setup firmware-controlled PHYs
 665  * @hw: pointer to hardware structure
 666  */
 667 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw)
 668 {
 669         u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
 670         s32 rc;
 671         u16 i;
 672
 673         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
 674                 return 0;
 675
 676         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
 677                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
 678                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
 679                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
 680         }
 681
 682         switch (hw->fc.requested_mode) {
 683         case ixgbe_fc_full:
 684                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX <<
 685                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 686                 break;
 687         case ixgbe_fc_rx_pause:
 688                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX <<
 689                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 690                 break;
 691         case ixgbe_fc_tx_pause:
 692                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX <<
 693                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 694                 break;
 695         default:
 696                 break;
 697         }
 698
 699         for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
 700                 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)
 701                         setup[0] |= ixgbe_fw_map[i].fw_speed;
 702         }
 703         setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN;
 704
 705         if (hw->phy.eee_speeds_advertised)
 706                 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE;
 707
 708         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup);
 709         if (rc)
 710                 return rc;
 711         if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN)
 712                 return IXGBE_ERR_OVERTEMP;
 713         return IXGBE_SUCCESS;
 714 }
 715
 716 /**
 717  * ixgbe_fc_autoneg_fw _ Set up flow control for FW-controlled PHYs
 718  * @hw: pointer to hardware structure
 719  *
 720  *  Called at init time to set up flow control.
 721  */
 722 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw)
 723 {
 724         if (hw->fc.requested_mode == ixgbe_fc_default)
 725                 hw->fc.requested_mode = ixgbe_fc_full;
 726
 727         return ixgbe_setup_fw_link(hw);
 728 }
 729
 730 /**
 731  * ixgbe_setup_eee_fw - Enable/disable EEE support
 732  * @hw: pointer to the HW structure
 733  * @enable_eee: boolean flag to enable EEE
 734  *
 735  * Enable/disable EEE based on enable_eee flag.
 736  * This function controls EEE for firmware-based PHY implementations.
 737  */
 738 static s32 ixgbe_setup_eee_fw(struct ixgbe_hw *hw, bool enable_eee)
 739 {
 740         if (!!hw->phy.eee_speeds_advertised == enable_eee)
 741                 return IXGBE_SUCCESS;
 742         if (enable_eee)
 743                 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
 744         else
 745                 hw->phy.eee_speeds_advertised = 0;
 746         return hw->phy.ops.setup_link(hw);
 747 }
 748
 749 /**
 750 *  ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
 751 *  @hw: pointer to hardware structure
 752 *
 753 *  Initialize the function pointers and for MAC type X550EM_a.
 754 *  Does not touch the hardware.
 755 **/
 756 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
 757 {
 758         struct ixgbe_mac_info *mac = &hw->mac;
 759         s32 ret_val;
 760
 761         DEBUGFUNC("ixgbe_init_ops_X550EM_a");
 762
 763         /* Start with generic X550EM init */
 764         ret_val = ixgbe_init_ops_X550EM(hw);
 765
 766         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
 767             hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) {
 768                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 769                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 770         } else {
 771                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
 772                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
 773         }
 774         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
 775         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
 776
 777         switch (mac->ops.get_media_type(hw)) {
 778         case ixgbe_media_type_fiber:
 779                 mac->ops.setup_fc = NULL;
 780                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
 781                 break;
 782         case ixgbe_media_type_backplane:
 783                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
 784                 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
 785                 break;
 786         default:
 787                 break;
 788         }
 789
 790         switch (hw->device_id) {
 791         case IXGBE_DEV_ID_X550EM_A_1G_T:
 792         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 793                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
 794                 mac->ops.setup_fc = ixgbe_fc_autoneg_fw;
 795                 mac->ops.setup_eee = ixgbe_setup_eee_fw;
 796                 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL |
 797                                                IXGBE_LINK_SPEED_1GB_FULL;
 798                 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
 799                 break;
 800         default:
 801                 break;
 802         }
 803
 804         return ret_val;
 805 }
 806
 807 /**
 808 *  ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
 809 *  @hw: pointer to hardware structure
 810 *
 811 *  Initialize the function pointers and for MAC type X550EM_x.
 812 *  Does not touch the hardware.
 813 **/
 814 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
 815 {
 816         struct ixgbe_mac_info *mac = &hw->mac;
 817         struct ixgbe_link_info *link = &hw->link;
 818         s32 ret_val;
 819
 820         DEBUGFUNC("ixgbe_init_ops_X550EM_x");
 821
 822         /* Start with generic X550EM init */
 823         ret_val = ixgbe_init_ops_X550EM(hw);
 824
 825         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 826         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 827         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 828         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 829         link->ops.read_link = ixgbe_read_i2c_combined_generic;
 830         link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
 831         link->ops.write_link = ixgbe_write_i2c_combined_generic;
 832         link->ops.write_link_unlocked =
 833                                       ixgbe_write_i2c_combined_generic_unlocked;
 834         link->addr = IXGBE_CS4227;
 835
 836         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T) {
 837                 mac->ops.setup_fc = NULL;
 838                 mac->ops.setup_eee = NULL;
 839                 mac->ops.init_led_link_act = NULL;
 840         }
 841
 842         return ret_val;
 843 }
 844
 845 /**
 846  *  ixgbe_dmac_config_X550
 847  *  @hw: pointer to hardware structure
 848  *
 849  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 850  *  When disabling dmac, dmac enable dmac bit is cleared.
 851  **/
 852 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 853 {
 854         u32 reg, high_pri_tc;
 855
 856         DEBUGFUNC("ixgbe_dmac_config_X550");
 857
 858         /* Disable DMA coalescing before configuring */
 859         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 860         reg &= ~IXGBE_DMACR_DMAC_EN;
 861         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 862
 863         /* Disable DMA Coalescing if the watchdog timer is 0 */
 864         if (!hw->mac.dmac_config.watchdog_timer)
 865                 goto out;
 866
 867         ixgbe_dmac_config_tcs_X550(hw);
 868
 869         /* Configure DMA Coalescing Control Register */
 870         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 871
 872         /* Set the watchdog timer in units of 40.96 usec */
 873         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 874         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 875
 876         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 877         /* If fcoe is enabled, set high priority traffic class */
 878         if (hw->mac.dmac_config.fcoe_en) {
 879                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 880                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 881                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 882         }
 883         reg |= IXGBE_DMACR_EN_MNG_IND;
 884
 885         /* Enable DMA coalescing after configuration */
 886         reg |= IXGBE_DMACR_DMAC_EN;
 887         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 888
 889 out:
 890         return IXGBE_SUCCESS;
 891 }
 892
 893 /**
 894  *  ixgbe_dmac_config_tcs_X550
 895  *  @hw: pointer to hardware structure
 896  *
 897  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 898  *  be cleared before configuring.
 899  **/
 900 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 901 {
 902         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 903
 904         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 905
 906         /* Configure DMA coalescing enabled */
 907         switch (hw->mac.dmac_config.link_speed) {
 908         case IXGBE_LINK_SPEED_10_FULL:
 909         case IXGBE_LINK_SPEED_100_FULL:
 910                 pb_headroom = IXGBE_DMACRXT_100M;
 911                 break;
 912         case IXGBE_LINK_SPEED_1GB_FULL:
 913                 pb_headroom = IXGBE_DMACRXT_1G;
 914                 break;
 915         default:
 916                 pb_headroom = IXGBE_DMACRXT_10G;
 917                 break;
 918         }
 919
 920         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 921                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 922
 923         /* Set the per Rx packet buffer receive threshold */
 924         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 925                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 926                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 927
 928                 if (tc < hw->mac.dmac_config.num_tcs) {
 929                         /* Get Rx PB size */
 930                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 931                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 932                                 IXGBE_RXPBSIZE_SHIFT;
 933
 934                         /* Calculate receive buffer threshold in kilobytes */
 935                         if (rx_pb_size > pb_headroom)
 936                                 rx_pb_size = rx_pb_size - pb_headroom;
 937                         else
 938                                 rx_pb_size = 0;
 939
 940                         /* Minimum of MFS shall be set for DMCTH */
 941                         reg |= (rx_pb_size > maxframe_size_kb) ?
 942                                 rx_pb_size : maxframe_size_kb;
 943                 }
 944                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 945         }
 946         return IXGBE_SUCCESS;
 947 }
 948
 949 /**
 950  *  ixgbe_dmac_update_tcs_X550
 951  *  @hw: pointer to hardware structure
 952  *
 953  *  Disables dmac, updates per TC settings, and then enables dmac.
 954  **/
 955 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 956 {
 957         u32 reg;
 958
 959         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 960
 961         /* Disable DMA coalescing before configuring */
 962         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 963         reg &= ~IXGBE_DMACR_DMAC_EN;
 964         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 965
 966         ixgbe_dmac_config_tcs_X550(hw);
 967
 968         /* Enable DMA coalescing after configuration */
 969         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 970         reg |= IXGBE_DMACR_DMAC_EN;
 971         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 972
 973         return IXGBE_SUCCESS;
 974 }
 975
 976 /**
 977  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 978  *  @hw: pointer to hardware structure
 979  *
 980  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 981  *  ixgbe_hw struct in order to set up EEPROM access.
 982  **/
 983 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 984 {
 985         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 986         u32 eec;
 987         u16 eeprom_size;
 988
 989         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 990
 991         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 992                 eeprom->semaphore_delay = 10;
 993                 eeprom->type = ixgbe_flash;
 994
 995                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 996                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 997                                     IXGBE_EEC_SIZE_SHIFT);
 998                 eeprom->word_size = 1 << (eeprom_size +
 999                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
1000
1001                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
1002                           eeprom->type, eeprom->word_size);
1003         }
1004
1005         return IXGBE_SUCCESS;
1006 }
1007
1008 /**
1009  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1010  * @hw: pointer to hardware structure
1011  * @enable: enable or disable source address pruning
1012  * @pool: Rx pool to set source address pruning for
1013  **/
1014 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1015                                            unsigned int pool)
1016 {
1017         u64 pfflp;
1018
1019         /* max rx pool is 63 */
1020         if (pool > 63)
1021                 return;
1022
1023         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1024         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1025
1026         if (enable)
1027                 pfflp |= (1ULL << pool);
1028         else
1029                 pfflp &= ~(1ULL << pool);
1030
1031         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1032         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1033 }
1034
1035 /**
1036  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1037  *  @hw: pointer to hardware structure
1038  *  @enable: enable or disable switch for Ethertype anti-spoofing
1039  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1040  *
1041  **/
1042 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1043                 bool enable, int vf)
1044 {
1045         int vf_target_reg = vf >> 3;
1046         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1047         u32 pfvfspoof;
1048
1049         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1050
1051         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1052         if (enable)
1053                 pfvfspoof |= (1 << vf_target_shift);
1054         else
1055                 pfvfspoof &= ~(1 << vf_target_shift);
1056
1057         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1058 }
1059
1060 /**
1061  * ixgbe_iosf_wait - Wait for IOSF command completion
1062  * @hw: pointer to hardware structure
1063  * @ctrl: pointer to location to receive final IOSF control value
1064  *
1065  * Returns failing status on timeout
1066  *
1067  * Note: ctrl can be NULL if the IOSF control register value is not needed
1068  **/
1069 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1070 {
1071         u32 i, command = 0;
1072
1073         /* Check every 10 usec to see if the address cycle completed.
1074          * The SB IOSF BUSY bit will clear when the operation is
1075          * complete
1076          */
1077         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1078                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1079                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1080                         break;
1081                 usec_delay(10);
1082         }
1083         if (ctrl)
1084                 *ctrl = command;
1085         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1086                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1087                 return IXGBE_ERR_PHY;
1088         }
1089
1090         return IXGBE_SUCCESS;
1091 }
1092
1093 /**
1094  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register
1095  *  of the IOSF device
1096  *  @hw: pointer to hardware structure
1097  *  @reg_addr: 32 bit PHY register to write
1098  *  @device_type: 3 bit device type
1099  *  @data: Data to write to the register
1100  **/
1101 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1102                             u32 device_type, u32 data)
1103 {
1104         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1105         u32 command, error;
1106         s32 ret;
1107
1108         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1109         if (ret != IXGBE_SUCCESS)
1110                 return ret;
1111
1112         ret = ixgbe_iosf_wait(hw, NULL);
1113         if (ret != IXGBE_SUCCESS)
1114                 goto out;
1115
1116         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1117                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1118
1119         /* Write IOSF control register */
1120         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1121
1122         /* Write IOSF data register */
1123         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1124
1125         ret = ixgbe_iosf_wait(hw, &command);
1126
1127         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1128                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1129                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1130                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1131                               "Failed to write, error %x\n", error);
1132                 ret = IXGBE_ERR_PHY;
1133         }
1134
1135 out:
1136         ixgbe_release_swfw_semaphore(hw, gssr);
1137         return ret;
1138 }
1139
1140 /**
1141  *  ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device
1142  *  @hw: pointer to hardware structure
1143  *  @reg_addr: 32 bit PHY register to write
1144  *  @device_type: 3 bit device type
1145  *  @data: Pointer to read data from the register
1146  **/
1147 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1148                            u32 device_type, u32 *data)
1149 {
1150         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1151         u32 command, error;
1152         s32 ret;
1153
1154         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1155         if (ret != IXGBE_SUCCESS)
1156                 return ret;
1157
1158         ret = ixgbe_iosf_wait(hw, NULL);
1159         if (ret != IXGBE_SUCCESS)
1160                 goto out;
1161
1162         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1163                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1164
1165         /* Write IOSF control register */
1166         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1167
1168         ret = ixgbe_iosf_wait(hw, &command);
1169
1170         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1171                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1172                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1173                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1174                                 "Failed to read, error %x\n", error);
1175                 ret = IXGBE_ERR_PHY;
1176         }
1177
1178         if (ret == IXGBE_SUCCESS)
1179                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1180
1181 out:
1182         ixgbe_release_swfw_semaphore(hw, gssr);
1183         return ret;
1184 }
1185
1186 /**
1187  * ixgbe_get_phy_token - Get the token for shared phy access
1188  * @hw: Pointer to hardware structure
1189  */
1190
1191 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1192 {
1193         struct ixgbe_hic_phy_token_req token_cmd;
1194         s32 status;
1195
1196         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1197         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1198         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1199         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1200         token_cmd.port_number = hw->bus.lan_id;
1201         token_cmd.command_type = FW_PHY_TOKEN_REQ;
1202         token_cmd.pad = 0;
1203         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1204                                               sizeof(token_cmd),
1205                                               IXGBE_HI_COMMAND_TIMEOUT,
1206                                               true);
1207         if (status) {
1208                 DEBUGOUT1("Issuing host interface command failed with Status = %d\n",
1209                           status);
1210                 return status;
1211         }
1212         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1213                 return IXGBE_SUCCESS;
1214         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY) {
1215                 DEBUGOUT1("Host interface command returned 0x%08x , returning IXGBE_ERR_FW_RESP_INVALID\n",
1216                           token_cmd.hdr.cmd_or_resp.ret_status);
1217                 return IXGBE_ERR_FW_RESP_INVALID;
1218         }
1219
1220         DEBUGOUT("Returning  IXGBE_ERR_TOKEN_RETRY\n");
1221         return IXGBE_ERR_TOKEN_RETRY;
1222 }
1223
1224 /**
1225  * ixgbe_put_phy_token - Put the token for shared phy access
1226  * @hw: Pointer to hardware structure
1227  */
1228
1229 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1230 {
1231         struct ixgbe_hic_phy_token_req token_cmd;
1232         s32 status;
1233
1234         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1235         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1236         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1237         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1238         token_cmd.port_number = hw->bus.lan_id;
1239         token_cmd.command_type = FW_PHY_TOKEN_REL;
1240         token_cmd.pad = 0;
1241         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1242                                               sizeof(token_cmd),
1243                                               IXGBE_HI_COMMAND_TIMEOUT,
1244                                               true);
1245         if (status)
1246                 return status;
1247         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1248                 return IXGBE_SUCCESS;
1249
1250         DEBUGOUT("Put PHY Token host interface command failed");
1251         return IXGBE_ERR_FW_RESP_INVALID;
1252 }
1253
1254 /**
1255  *  ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1256  *  of the IOSF device
1257  *  @hw: pointer to hardware structure
1258  *  @reg_addr: 32 bit PHY register to write
1259  *  @device_type: 3 bit device type
1260  *  @data: Data to write to the register
1261  **/
1262 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1263                                   u32 device_type, u32 data)
1264 {
1265         struct ixgbe_hic_internal_phy_req write_cmd;
1266         s32 status;
1267         UNREFERENCED_1PARAMETER(device_type);
1268
1269         memset(&write_cmd, 0, sizeof(write_cmd));
1270         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1271         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1272         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1273         write_cmd.port_number = hw->bus.lan_id;
1274         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1275         write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1276         write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1277
1278         status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1279                                               sizeof(write_cmd),
1280                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1281
1282         return status;
1283 }
1284
1285 /**
1286  *  ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device
1287  *  @hw: pointer to hardware structure
1288  *  @reg_addr: 32 bit PHY register to write
1289  *  @device_type: 3 bit device type
1290  *  @data: Pointer to read data from the register
1291  **/
1292 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1293                                  u32 device_type, u32 *data)
1294 {
1295         union {
1296                 struct ixgbe_hic_internal_phy_req cmd;
1297                 struct ixgbe_hic_internal_phy_resp rsp;
1298         } hic;
1299         s32 status;
1300         UNREFERENCED_1PARAMETER(device_type);
1301
1302         memset(&hic, 0, sizeof(hic));
1303         hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1304         hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1305         hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1306         hic.cmd.port_number = hw->bus.lan_id;
1307         hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1308         hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1309
1310         status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1311                                               sizeof(hic.cmd),
1312                                               IXGBE_HI_COMMAND_TIMEOUT, true);
1313
1314         /* Extract the register value from the response. */
1315         *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1316
1317         return status;
1318 }
1319
1320 /**
1321  *  ixgbe_disable_mdd_X550
1322  *  @hw: pointer to hardware structure
1323  *
1324  *  Disable malicious driver detection
1325  **/
1326 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1327 {
1328         u32 reg;
1329
1330         DEBUGFUNC("ixgbe_disable_mdd_X550");
1331
1332         /* Disable MDD for TX DMA and interrupt */
1333         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1334         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1335         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1336
1337         /* Disable MDD for RX and interrupt */
1338         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1339         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1340         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1341 }
1342
1343 /**
1344  *  ixgbe_enable_mdd_X550
1345  *  @hw: pointer to hardware structure
1346  *
1347  *  Enable malicious driver detection
1348  **/
1349 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1350 {
1351         u32 reg;
1352
1353         DEBUGFUNC("ixgbe_enable_mdd_X550");
1354
1355         /* Enable MDD for TX DMA and interrupt */
1356         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1357         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1358         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1359
1360         /* Enable MDD for RX and interrupt */
1361         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1362         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1363         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1364 }
1365
1366 /**
1367  *  ixgbe_restore_mdd_vf_X550
1368  *  @hw: pointer to hardware structure
1369  *  @vf: vf index
1370  *
1371  *  Restore VF that was disabled during malicious driver detection event
1372  **/
1373 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1374 {
1375         u32 idx, reg, num_qs, start_q, bitmask;
1376
1377         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1378
1379         /* Map VF to queues */
1380         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1381         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1382         case IXGBE_MRQC_VMDQRT8TCEN:
1383                 num_qs = 8;  /* 16 VFs / pools */
1384                 bitmask = 0x000000FF;
1385                 break;
1386         case IXGBE_MRQC_VMDQRSS32EN:
1387         case IXGBE_MRQC_VMDQRT4TCEN:
1388                 num_qs = 4;  /* 32 VFs / pools */
1389                 bitmask = 0x0000000F;
1390                 break;
1391         default:            /* 64 VFs / pools */
1392                 num_qs = 2;
1393                 bitmask = 0x00000003;
1394                 break;
1395         }
1396         start_q = vf * num_qs;
1397
1398         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1399         idx = start_q / 32;
1400         reg = 0;
1401         reg |= (bitmask << (start_q % 32));
1402         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1403         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1404 }
1405
1406 /**
1407  *  ixgbe_mdd_event_X550
1408  *  @hw: pointer to hardware structure
1409  *  @vf_bitmap: vf bitmap of malicious vfs
1410  *
1411  *  Handle malicious driver detection event.
1412  **/
1413 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1414 {
1415         u32 wqbr;
1416         u32 i, j, reg, q, shift, vf, idx;
1417
1418         DEBUGFUNC("ixgbe_mdd_event_X550");
1419
1420         /* figure out pool size for mapping to vf's */
1421         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1422         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1423         case IXGBE_MRQC_VMDQRT8TCEN:
1424                 shift = 3;  /* 16 VFs / pools */
1425                 break;
1426         case IXGBE_MRQC_VMDQRSS32EN:
1427         case IXGBE_MRQC_VMDQRT4TCEN:
1428                 shift = 2;  /* 32 VFs / pools */
1429                 break;
1430         default:
1431                 shift = 1;  /* 64 VFs / pools */
1432                 break;
1433         }
1434
1435         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1436         for (i = 0; i < 4; i++) {
1437                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1438                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1439
1440                 if (!wqbr)
1441                         continue;
1442
1443                 /* Get malicious queue */
1444                 for (j = 0; j < 32 && wqbr; j++) {
1445
1446                         if (!(wqbr & (1 << j)))
1447                                 continue;
1448
1449                         /* Get queue from bitmask */
1450                         q = j + (i * 32);
1451
1452                         /* Map queue to vf */
1453                         vf = (q >> shift);
1454
1455                         /* Set vf bit in vf_bitmap */
1456                         idx = vf / 32;
1457                         vf_bitmap[idx] |= (1 << (vf % 32));
1458                         wqbr &= ~(1 << j);
1459                 }
1460         }
1461 }
1462
1463 /**
1464  *  ixgbe_get_media_type_X550em - Get media type
1465  *  @hw: pointer to hardware structure
1466  *
1467  *  Returns the media type (fiber, copper, backplane)
1468  */
1469 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1470 {
1471         enum ixgbe_media_type media_type;
1472
1473         DEBUGFUNC("ixgbe_get_media_type_X550em");
1474
1475         /* Detect if there is a copper PHY attached. */
1476         switch (hw->device_id) {
1477         case IXGBE_DEV_ID_X550EM_X_KR:
1478         case IXGBE_DEV_ID_X550EM_X_KX4:
1479         case IXGBE_DEV_ID_X550EM_X_XFI:
1480         case IXGBE_DEV_ID_X550EM_A_KR:
1481         case IXGBE_DEV_ID_X550EM_A_KR_L:
1482                 media_type = ixgbe_media_type_backplane;
1483                 break;
1484         case IXGBE_DEV_ID_X550EM_X_SFP:
1485         case IXGBE_DEV_ID_X550EM_A_SFP:
1486         case IXGBE_DEV_ID_X550EM_A_SFP_N:
1487         case IXGBE_DEV_ID_X550EM_A_QSFP:
1488         case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1489                 media_type = ixgbe_media_type_fiber;
1490                 break;
1491         case IXGBE_DEV_ID_X550EM_X_1G_T:
1492         case IXGBE_DEV_ID_X550EM_X_10G_T:
1493         case IXGBE_DEV_ID_X550EM_A_10G_T:
1494                 media_type = ixgbe_media_type_copper;
1495                 break;
1496         case IXGBE_DEV_ID_X550EM_A_SGMII:
1497         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1498                 media_type = ixgbe_media_type_backplane;
1499                 hw->phy.type = ixgbe_phy_sgmii;
1500                 break;
1501         case IXGBE_DEV_ID_X550EM_A_1G_T:
1502         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1503                 media_type = ixgbe_media_type_copper;
1504                 break;
1505         default:
1506                 media_type = ixgbe_media_type_unknown;
1507                 break;
1508         }
1509         return media_type;
1510 }
1511
1512 /**
1513  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1514  *  @hw: pointer to hardware structure
1515  *  @linear: true if SFP module is linear
1516  */
1517 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1518 {
1519         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1520
1521         switch (hw->phy.sfp_type) {
1522         case ixgbe_sfp_type_not_present:
1523                 return IXGBE_ERR_SFP_NOT_PRESENT;
1524         case ixgbe_sfp_type_da_cu_core0:
1525         case ixgbe_sfp_type_da_cu_core1:
1526                 *linear = true;
1527                 break;
1528         case ixgbe_sfp_type_srlr_core0:
1529         case ixgbe_sfp_type_srlr_core1:
1530         case ixgbe_sfp_type_da_act_lmt_core0:
1531         case ixgbe_sfp_type_da_act_lmt_core1:
1532         case ixgbe_sfp_type_1g_sx_core0:
1533         case ixgbe_sfp_type_1g_sx_core1:
1534         case ixgbe_sfp_type_1g_lx_core0:
1535         case ixgbe_sfp_type_1g_lx_core1:
1536                 *linear = false;
1537                 break;
1538         case ixgbe_sfp_type_unknown:
1539         case ixgbe_sfp_type_1g_cu_core0:
1540         case ixgbe_sfp_type_1g_cu_core1:
1541         default:
1542                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1543         }
1544
1545         return IXGBE_SUCCESS;
1546 }
1547
1548 /**
1549  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1550  *  @hw: pointer to hardware structure
1551  *
1552  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1553  **/
1554 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1555 {
1556         s32 status;
1557         bool linear;
1558
1559         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1560
1561         status = ixgbe_identify_module_generic(hw);
1562
1563         if (status != IXGBE_SUCCESS)
1564                 return status;
1565
1566         /* Check if SFP module is supported */
1567         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1568
1569         return status;
1570 }
1571
1572 /**
1573  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1574  *  @hw: pointer to hardware structure
1575  */
1576 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1577 {
1578         s32 status;
1579         bool linear;
1580
1581         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1582
1583         /* Check if SFP module is supported */
1584         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1585
1586         if (status != IXGBE_SUCCESS)
1587                 return status;
1588
1589         ixgbe_init_mac_link_ops_X550em(hw);
1590         hw->phy.ops.reset = NULL;
1591
1592         return IXGBE_SUCCESS;
1593 }
1594
1595 /**
1596 *  ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1597 *  internal PHY
1598 *  @hw: pointer to hardware structure
1599 **/
1600 STATIC s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1601 {
1602         s32 status;
1603         u32 link_ctrl;
1604
1605         /* Restart auto-negotiation. */
1606         status = hw->mac.ops.read_iosf_sb_reg(hw,
1607                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1608                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1609
1610         if (status) {
1611                 DEBUGOUT("Auto-negotiation did not complete\n");
1612                 return status;
1613         }
1614
1615         link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1616         status = hw->mac.ops.write_iosf_sb_reg(hw,
1617                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1618                                         IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1619
1620         if (hw->mac.type == ixgbe_mac_X550EM_a) {
1621                 u32 flx_mask_st20;
1622
1623                 /* Indicate to FW that AN restart has been asserted */
1624                 status = hw->mac.ops.read_iosf_sb_reg(hw,
1625                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1626                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1627
1628                 if (status) {
1629                         DEBUGOUT("Auto-negotiation did not complete\n");
1630                         return status;
1631                 }
1632
1633                 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1634                 status = hw->mac.ops.write_iosf_sb_reg(hw,
1635                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1636                                 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1637         }
1638
1639         return status;
1640 }
1641
1642 #ifndef PREBOOT_SUPPORT
1643 /**
1644  * ixgbe_setup_sgmii - Set up link for sgmii
1645  * @hw: pointer to hardware structure
1646  * @speed: new link speed
1647  * @autoneg_wait: true when waiting for completion is needed
1648  */
1649 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1650                              bool autoneg_wait)
1651 {
1652         struct ixgbe_mac_info *mac = &hw->mac;
1653         u32 lval, sval, flx_val;
1654         s32 rc;
1655
1656         rc = mac->ops.read_iosf_sb_reg(hw,
1657                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1658                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1659         if (rc)
1660                 return rc;
1661
1662         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1663         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1664         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1665         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1666         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1667         rc = mac->ops.write_iosf_sb_reg(hw,
1668                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1669                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1670         if (rc)
1671                 return rc;
1672
1673         rc = mac->ops.read_iosf_sb_reg(hw,
1674                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1675                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1676         if (rc)
1677                 return rc;
1678
1679         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1680         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1681         rc = mac->ops.write_iosf_sb_reg(hw,
1682                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1683                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1684         if (rc)
1685                 return rc;
1686
1687         rc = mac->ops.read_iosf_sb_reg(hw,
1688                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1689                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1690         if (rc)
1691                 return rc;
1692
1693         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1694         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1695         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1696         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1697         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1698
1699         rc = mac->ops.write_iosf_sb_reg(hw,
1700                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1701                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1702         if (rc)
1703                 return rc;
1704
1705         rc = ixgbe_restart_an_internal_phy_x550em(hw);
1706         if (rc)
1707                 return rc;
1708
1709         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1710 }
1711
1712 #endif /* PREBOOT_SUPPORT */
1713 /**
1714  * ixgbe_setup_sgmii_fw - Set up link for internal PHY SGMII auto-negotiation
1715  * @hw: pointer to hardware structure
1716  * @speed: new link speed
1717  * @autoneg_wait: true when waiting for completion is needed
1718  */
1719 STATIC s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1720                                 bool autoneg_wait)
1721 {
1722         struct ixgbe_mac_info *mac = &hw->mac;
1723         u32 lval, sval, flx_val;
1724         s32 rc;
1725
1726         rc = mac->ops.read_iosf_sb_reg(hw,
1727                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1728                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1729         if (rc)
1730                 return rc;
1731
1732         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1733         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1734         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1735         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1736         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1737         rc = mac->ops.write_iosf_sb_reg(hw,
1738                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1739                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1740         if (rc)
1741                 return rc;
1742
1743         rc = mac->ops.read_iosf_sb_reg(hw,
1744                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1745                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1746         if (rc)
1747                 return rc;
1748
1749         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1750         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1751         rc = mac->ops.write_iosf_sb_reg(hw,
1752                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1753                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1754         if (rc)
1755                 return rc;
1756
1757         rc = mac->ops.write_iosf_sb_reg(hw,
1758                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1759                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1760         if (rc)
1761                 return rc;
1762
1763         rc = mac->ops.read_iosf_sb_reg(hw,
1764                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1765                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1766         if (rc)
1767                 return rc;
1768
1769         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1770         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
1771         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1772         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1773         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1774
1775         rc = mac->ops.write_iosf_sb_reg(hw,
1776                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1777                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1778         if (rc)
1779                 return rc;
1780
1781         rc = ixgbe_restart_an_internal_phy_x550em(hw);
1782
1783         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1784 }
1785
1786 /**
1787  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1788  *  @hw: pointer to hardware structure
1789  */
1790 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1791 {
1792         struct ixgbe_mac_info *mac = &hw->mac;
1793
1794         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1795
1796         switch (hw->mac.ops.get_media_type(hw)) {
1797         case ixgbe_media_type_fiber:
1798                 /* CS4227 does not support autoneg, so disable the laser control
1799                  * functions for SFP+ fiber
1800                  */
1801                 mac->ops.disable_tx_laser = NULL;
1802                 mac->ops.enable_tx_laser = NULL;
1803                 mac->ops.flap_tx_laser = NULL;
1804                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1805                 mac->ops.set_rate_select_speed =
1806                                         ixgbe_set_soft_rate_select_speed;
1807
1808                 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1809                     (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1810                         mac->ops.setup_mac_link =
1811                                                 ixgbe_setup_mac_link_sfp_x550a;
1812                 else
1813                         mac->ops.setup_mac_link =
1814                                                 ixgbe_setup_mac_link_sfp_x550em;
1815                 break;
1816         case ixgbe_media_type_copper:
1817                 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T)
1818                         break;
1819                 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1820                         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
1821                             hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
1822                                 mac->ops.setup_link = ixgbe_setup_sgmii_fw;
1823                                 mac->ops.check_link =
1824                                                    ixgbe_check_mac_link_generic;
1825                         } else {
1826                                 mac->ops.setup_link =
1827                                                   ixgbe_setup_mac_link_t_X550em;
1828                         }
1829                 } else {
1830                         mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1831                         mac->ops.check_link = ixgbe_check_link_t_X550em;
1832                 }
1833                 break;
1834         case ixgbe_media_type_backplane:
1835                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1836                     hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1837 #ifdef PREBOOT_SUPPORT
1838                         mac->ops.setup_link = ixgbe_setup_sgmii_fw;
1839 #else
1840                         mac->ops.setup_link = ixgbe_setup_sgmii;
1841 #endif /* PREBOOT_SUPPORT */
1842                 break;
1843         default:
1844                 break;
1845         }
1846 }
1847
1848 /**
1849  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1850  *  @hw: pointer to hardware structure
1851  *  @speed: pointer to link speed
1852  *  @autoneg: true when autoneg or autotry is enabled
1853  */
1854 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1855                                        ixgbe_link_speed *speed,
1856                                        bool *autoneg)
1857 {
1858         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1859
1860
1861         if (hw->phy.type == ixgbe_phy_fw) {
1862                 *autoneg = true;
1863                 *speed = hw->phy.speeds_supported;
1864                 return 0;
1865         }
1866
1867         /* SFP */
1868         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1869
1870                 /* CS4227 SFP must not enable auto-negotiation */
1871                 *autoneg = false;
1872
1873                 /* Check if 1G SFP module. */
1874                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1875                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1876                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1877                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1878                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1879                         return IXGBE_SUCCESS;
1880                 }
1881
1882                 /* Link capabilities are based on SFP */
1883                 if (hw->phy.multispeed_fiber)
1884                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1885                                  IXGBE_LINK_SPEED_1GB_FULL;
1886                 else
1887                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1888         } else {
1889                 switch (hw->phy.type) {
1890                 case ixgbe_phy_ext_1g_t:
1891 #ifdef PREBOOT_SUPPORT
1892                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1893                         break;
1894 #endif /* PREBOOT_SUPPORT */
1895                 case ixgbe_phy_sgmii:
1896 #ifdef PREBOOT_SUPPORT
1897                         *speed = IXGBE_LINK_SPEED_1GB_FULL |
1898                                  IXGBE_LINK_SPEED_100_FULL |
1899                                  IXGBE_LINK_SPEED_10_FULL;
1900 #else
1901                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1902 #endif /* PREBOOT_SUPPORT */
1903                         break;
1904                 case ixgbe_phy_x550em_kr:
1905                         if (hw->mac.type == ixgbe_mac_X550EM_a) {
1906                                 /* check different backplane modes */
1907                                 if (hw->phy.nw_mng_if_sel &
1908                                            IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
1909                                         *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
1910                                         break;
1911                                 } else if (hw->device_id ==
1912                                                    IXGBE_DEV_ID_X550EM_A_KR_L) {
1913                                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1914                                         break;
1915                                 }
1916                         }
1917                         /* fall through */
1918                 default:
1919                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1920                                  IXGBE_LINK_SPEED_1GB_FULL;
1921                         break;
1922                 }
1923                 *autoneg = true;
1924         }
1925
1926         return IXGBE_SUCCESS;
1927 }
1928
1929 /**
1930  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1931  * @hw: pointer to hardware structure
1932  * @lsc: pointer to boolean flag which indicates whether external Base T
1933  *       PHY interrupt is lsc
1934  *
1935  * Determime if external Base T PHY interrupt cause is high temperature
1936  * failure alarm or link status change.
1937  *
1938  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1939  * failure alarm, else return PHY access status.
1940  */
1941 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1942 {
1943         u32 status;
1944         u16 reg;
1945
1946         *lsc = false;
1947
1948         /* Vendor alarm triggered */
1949         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1950                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1951                                       &reg);
1952
1953         if (status != IXGBE_SUCCESS ||
1954             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1955                 return status;
1956
1957         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1958         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1959                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1960                                       &reg);
1961
1962         if (status != IXGBE_SUCCESS ||
1963             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1964             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1965                 return status;
1966
1967         /* Global alarm triggered */
1968         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1969                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1970                                       &reg);
1971
1972         if (status != IXGBE_SUCCESS)
1973                 return status;
1974
1975         /* If high temperature failure, then return over temp error and exit */
1976         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1977                 /* power down the PHY in case the PHY FW didn't already */
1978                 ixgbe_set_copper_phy_power(hw, false);
1979                 return IXGBE_ERR_OVERTEMP;
1980         } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1981                 /*  device fault alarm triggered */
1982                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1983                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1984                                           &reg);
1985
1986                 if (status != IXGBE_SUCCESS)
1987                         return status;
1988
1989                 /* if device fault was due to high temp alarm handle and exit */
1990                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1991                         /* power down the PHY in case the PHY FW didn't */
1992                         ixgbe_set_copper_phy_power(hw, false);
1993                         return IXGBE_ERR_OVERTEMP;
1994                 }
1995         }
1996
1997         /* Vendor alarm 2 triggered */
1998         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1999                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2000
2001         if (status != IXGBE_SUCCESS ||
2002             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
2003                 return status;
2004
2005         /* link connect/disconnect event occurred */
2006         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
2007                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2008
2009         if (status != IXGBE_SUCCESS)
2010                 return status;
2011
2012         /* Indicate LSC */
2013         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2014                 *lsc = true;
2015
2016         return IXGBE_SUCCESS;
2017 }
2018
2019 /**
2020  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2021  * @hw: pointer to hardware structure
2022  *
2023  * Enable link status change and temperature failure alarm for the external
2024  * Base T PHY
2025  *
2026  * Returns PHY access status
2027  */
2028 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2029 {
2030         u32 status;
2031         u16 reg;
2032         bool lsc;
2033
2034         /* Clear interrupt flags */
2035         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2036
2037         /* Enable link status change alarm */
2038
2039         /* Enable the LASI interrupts on X552 devices to receive notifications
2040          * of the link configurations of the external PHY and correspondingly
2041          * support the configuration of the internal iXFI link, since iXFI does
2042          * not support auto-negotiation. This is not required for X553 devices
2043          * having KR support, which performs auto-negotiations and which is used
2044          * as the internal link to the external PHY. Hence adding a check here
2045          * to avoid enabling LASI interrupts for X553 devices.
2046          */
2047         if (hw->mac.type != ixgbe_mac_X550EM_a) {
2048                 status = hw->phy.ops.read_reg(hw,
2049                                         IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2050                                         IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2051
2052                 if (status != IXGBE_SUCCESS)
2053                         return status;
2054
2055                 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2056
2057                 status = hw->phy.ops.write_reg(hw,
2058                                         IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2059                                         IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
2060
2061                 if (status != IXGBE_SUCCESS)
2062                         return status;
2063         }
2064
2065         /* Enable high temperature failure and global fault alarms */
2066         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2067                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2068                                       &reg);
2069
2070         if (status != IXGBE_SUCCESS)
2071                 return status;
2072
2073         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2074                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2075
2076         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2077                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2078                                        reg);
2079
2080         if (status != IXGBE_SUCCESS)
2081                 return status;
2082
2083         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2084         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2085                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2086                                       &reg);
2087
2088         if (status != IXGBE_SUCCESS)
2089                 return status;
2090
2091         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2092                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2093
2094         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2095                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2096                                        reg);
2097
2098         if (status != IXGBE_SUCCESS)
2099                 return status;
2100
2101         /* Enable chip-wide vendor alarm */
2102         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2103                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2104                                       &reg);
2105
2106         if (status != IXGBE_SUCCESS)
2107                 return status;
2108
2109         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2110
2111         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2112                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2113                                        reg);
2114
2115         return status;
2116 }
2117
2118 /**
2119  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2120  *  @hw: pointer to hardware structure
2121  *  @speed: link speed
2122  *
2123  *  Configures the integrated KR PHY.
2124  **/
2125 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2126                                        ixgbe_link_speed speed)
2127 {
2128         s32 status;
2129         u32 reg_val;
2130
2131         status = hw->mac.ops.read_iosf_sb_reg(hw,
2132                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2133                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2134         if (status)
2135                 return status;
2136
2137         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2138         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2139                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2140
2141         /* Advertise 10G support. */
2142         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2143                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2144
2145         /* Advertise 1G support. */
2146         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2147                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2148
2149         status = hw->mac.ops.write_iosf_sb_reg(hw,
2150                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2151                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2152
2153         if (hw->mac.type == ixgbe_mac_X550EM_a) {
2154                 /* Set lane mode  to KR auto negotiation */
2155                 status = hw->mac.ops.read_iosf_sb_reg(hw,
2156                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2157                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2158
2159                 if (status)
2160                         return status;
2161
2162                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2163                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2164                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2165                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2166                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2167
2168                 status = hw->mac.ops.write_iosf_sb_reg(hw,
2169                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2170                                     IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2171         }
2172
2173         return ixgbe_restart_an_internal_phy_x550em(hw);
2174 }
2175
2176 /**
2177  * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs
2178  * @hw: pointer to hardware structure
2179  */
2180 static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw)
2181 {
2182         u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
2183         s32 rc;
2184
2185         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2186                 return IXGBE_SUCCESS;
2187
2188         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store);
2189         if (rc)
2190                 return rc;
2191         memset(store, 0, sizeof(store));
2192
2193         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store);
2194         if (rc)
2195                 return rc;
2196
2197         return ixgbe_setup_fw_link(hw);
2198 }
2199
2200 /**
2201  * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp
2202  * @hw: pointer to hardware structure
2203  */
2204 static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw)
2205 {
2206         u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
2207         s32 rc;
2208
2209         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store);
2210         if (rc)
2211                 return rc;
2212
2213         if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) {
2214                 ixgbe_shutdown_fw_phy(hw);
2215                 return IXGBE_ERR_OVERTEMP;
2216         }
2217         return IXGBE_SUCCESS;
2218 }
2219
2220 /**
2221  *  ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2222  *  @hw: pointer to hardware structure
2223  *
2224  *  Read NW_MNG_IF_SEL register and save field values, and check for valid field
2225  *  values.
2226  **/
2227 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2228 {
2229         /* Save NW management interface connected on board. This is used
2230          * to determine internal PHY mode.
2231          */
2232         hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2233
2234         /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2235          * PHY address. This register field was has only been used for X552.
2236          */
2237         if (hw->mac.type == ixgbe_mac_X550EM_a &&
2238             hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2239                 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2240                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2241                                IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2242         }
2243
2244         return IXGBE_SUCCESS;
2245 }
2246
2247 /**
2248  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2249  *  @hw: pointer to hardware structure
2250  *
2251  *  Initialize any function pointers that were not able to be
2252  *  set during init_shared_code because the PHY/SFP type was
2253  *  not known.  Perform the SFP init if necessary.
2254  */
2255 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2256 {
2257         struct ixgbe_phy_info *phy = &hw->phy;
2258         s32 ret_val;
2259
2260         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2261
2262         hw->mac.ops.set_lan_id(hw);
2263         ixgbe_read_mng_if_sel_x550em(hw);
2264
2265         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2266                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2267                 ixgbe_setup_mux_ctl(hw);
2268                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2269         }
2270
2271         switch (hw->device_id) {
2272         case IXGBE_DEV_ID_X550EM_A_1G_T:
2273         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2274                 phy->ops.read_reg_mdi = NULL;
2275                 phy->ops.write_reg_mdi = NULL;
2276                 hw->phy.ops.read_reg = NULL;
2277                 hw->phy.ops.write_reg = NULL;
2278                 phy->ops.check_overtemp = ixgbe_check_overtemp_fw;
2279                 if (hw->bus.lan_id)
2280                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2281                 else
2282                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2283
2284                 break;
2285         case IXGBE_DEV_ID_X550EM_A_10G_T:
2286         case IXGBE_DEV_ID_X550EM_A_SFP:
2287                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2288                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2289                 if (hw->bus.lan_id)
2290                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2291                 else
2292                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2293                 break;
2294         case IXGBE_DEV_ID_X550EM_X_SFP:
2295                 /* set up for CS4227 usage */
2296                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2297                 break;
2298         case IXGBE_DEV_ID_X550EM_X_1G_T:
2299                 phy->ops.read_reg_mdi = NULL;
2300                 phy->ops.write_reg_mdi = NULL;
2301         default:
2302                 break;
2303         }
2304
2305         /* Identify the PHY or SFP module */
2306         ret_val = phy->ops.identify(hw);
2307         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED ||
2308             ret_val == IXGBE_ERR_PHY_ADDR_INVALID)
2309                 return ret_val;
2310
2311         /* Setup function pointers based on detected hardware */
2312         ixgbe_init_mac_link_ops_X550em(hw);
2313         if (phy->sfp_type != ixgbe_sfp_type_unknown)
2314                 phy->ops.reset = NULL;
2315
2316         /* Set functions pointers based on phy type */
2317         switch (hw->phy.type) {
2318         case ixgbe_phy_x550em_kx4:
2319                 phy->ops.setup_link = NULL;
2320                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2321                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2322                 break;
2323         case ixgbe_phy_x550em_kr:
2324                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2325                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2326                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2327                 break;
2328         case ixgbe_phy_ext_1g_t:
2329                 /* link is managed by FW */
2330                 phy->ops.setup_link = NULL;
2331                 phy->ops.reset = NULL;
2332                 break;
2333         case ixgbe_phy_x550em_xfi:
2334                 /* link is managed by HW */
2335                 phy->ops.setup_link = NULL;
2336                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2337                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2338                 break;
2339         case ixgbe_phy_x550em_ext_t:
2340                 /* If internal link mode is XFI, then setup iXFI internal link,
2341                  * else setup KR now.
2342                  */
2343                 phy->ops.setup_internal_link =
2344                                               ixgbe_setup_internal_phy_t_x550em;
2345
2346                 /* setup SW LPLU only for first revision of X550EM_x */
2347                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2348                     !(IXGBE_FUSES0_REV_MASK &
2349                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2350                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2351
2352                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2353                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2354                 break;
2355         case ixgbe_phy_sgmii:
2356                 phy->ops.setup_link = NULL;
2357                 break;
2358         case ixgbe_phy_fw:
2359                 phy->ops.setup_link = ixgbe_setup_fw_link;
2360                 phy->ops.reset = ixgbe_reset_phy_fw;
2361                 break;
2362         default:
2363                 break;
2364         }
2365         return ret_val;
2366 }
2367
2368 /**
2369  * ixgbe_set_mdio_speed - Set MDIO clock speed
2370  *  @hw: pointer to hardware structure
2371  */
2372 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2373 {
2374         u32 hlreg0;
2375
2376         switch (hw->device_id) {
2377         case IXGBE_DEV_ID_X550EM_X_10G_T:
2378         case IXGBE_DEV_ID_X550EM_A_SGMII:
2379         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2380         case IXGBE_DEV_ID_X550EM_A_10G_T:
2381         case IXGBE_DEV_ID_X550EM_A_SFP:
2382         case IXGBE_DEV_ID_X550EM_A_QSFP:
2383                 /* Config MDIO clock speed before the first MDIO PHY access */
2384                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2385                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2386                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2387                 break;
2388         case IXGBE_DEV_ID_X550EM_A_1G_T:
2389         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2390                 /* Select fast MDIO clock speed for these devices */
2391                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2392                 hlreg0 |= IXGBE_HLREG0_MDCSPD;
2393                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2394                 break;
2395         default:
2396                 break;
2397         }
2398 }
2399
2400 /**
2401  *  ixgbe_reset_hw_X550em - Perform hardware reset
2402  *  @hw: pointer to hardware structure
2403  *
2404  *  Resets the hardware by resetting the transmit and receive units, masks
2405  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2406  *  reset.
2407  */
2408 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2409 {
2410         ixgbe_link_speed link_speed;
2411         s32 status;
2412         u32 ctrl = 0;
2413         u32 i;
2414         bool link_up = false;
2415         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2416
2417         DEBUGFUNC("ixgbe_reset_hw_X550em");
2418
2419         /* Call adapter stop to disable Tx/Rx and clear interrupts */
2420         status = hw->mac.ops.stop_adapter(hw);
2421         if (status != IXGBE_SUCCESS) {
2422                 DEBUGOUT1("Failed to stop adapter, STATUS = %d\n", status);
2423                 return status;
2424         }
2425         /* flush pending Tx transactions */
2426         ixgbe_clear_tx_pending(hw);
2427
2428         ixgbe_set_mdio_speed(hw);
2429
2430         /* PHY ops must be identified and initialized prior to reset */
2431         status = hw->phy.ops.init(hw);
2432
2433         if (status)
2434                 DEBUGOUT1("Failed to initialize PHY ops, STATUS = %d\n",
2435                           status);
2436
2437         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED ||
2438             status == IXGBE_ERR_PHY_ADDR_INVALID) {
2439                 DEBUGOUT("Returning from reset HW due to PHY init failure\n");
2440                 return status;
2441         }
2442
2443         /* start the external PHY */
2444         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2445                 status = ixgbe_init_ext_t_x550em(hw);
2446                 if (status) {
2447                         DEBUGOUT1("Failed to start the external PHY, STATUS = %d\n",
2448                                   status);
2449                         return status;
2450                 }
2451         }
2452
2453         /* Setup SFP module if there is one present. */
2454         if (hw->phy.sfp_setup_needed) {
2455                 status = hw->mac.ops.setup_sfp(hw);
2456                 hw->phy.sfp_setup_needed = false;
2457         }
2458
2459         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2460                 return status;
2461
2462         /* Reset PHY */
2463         if (!hw->phy.reset_disable && hw->phy.ops.reset) {
2464                 if (hw->phy.ops.reset(hw) == IXGBE_ERR_OVERTEMP)
2465                         return IXGBE_ERR_OVERTEMP;
2466         }
2467
2468 mac_reset_top:
2469         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2470          * If link reset is used when link is up, it might reset the PHY when
2471          * mng is using it.  If link is down or the flag to force full link
2472          * reset is set, then perform link reset.
2473          */
2474         ctrl = IXGBE_CTRL_LNK_RST;
2475         if (!hw->force_full_reset) {
2476                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2477                 if (link_up)
2478                         ctrl = IXGBE_CTRL_RST;
2479         }
2480
2481         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
2482         if (status != IXGBE_SUCCESS) {
2483                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
2484                         "semaphore failed with %d", status);
2485                 return IXGBE_ERR_SWFW_SYNC;
2486         }
2487         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2488         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2489         IXGBE_WRITE_FLUSH(hw);
2490         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2491
2492         /* Poll for reset bit to self-clear meaning reset is complete */
2493         for (i = 0; i < 10; i++) {
2494                 usec_delay(1);
2495                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2496                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2497                         break;
2498         }
2499
2500         if (ctrl & IXGBE_CTRL_RST_MASK) {
2501                 status = IXGBE_ERR_RESET_FAILED;
2502                 DEBUGOUT("Reset polling failed to complete.\n");
2503         }
2504
2505         msec_delay(50);
2506
2507         /* Double resets are required for recovery from certain error
2508          * conditions.  Between resets, it is necessary to stall to
2509          * allow time for any pending HW events to complete.
2510          */
2511         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2512                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2513                 goto mac_reset_top;
2514         }
2515
2516         /* Store the permanent mac address */
2517         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2518
2519         /* Store MAC address from RAR0, clear receive address registers, and
2520          * clear the multicast table.  Also reset num_rar_entries to 128,
2521          * since we modify this value when programming the SAN MAC address.
2522          */
2523         hw->mac.num_rar_entries = 128;
2524         hw->mac.ops.init_rx_addrs(hw);
2525
2526         ixgbe_set_mdio_speed(hw);
2527
2528         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2529                 ixgbe_setup_mux_ctl(hw);
2530
2531         if (status != IXGBE_SUCCESS)
2532                 DEBUGOUT1("Reset HW failed, STATUS = %d\n", status);
2533
2534         return status;
2535 }
2536
2537 /**
2538  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2539  * @hw: pointer to hardware structure
2540  */
2541 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2542 {
2543         u32 status;
2544         u16 reg;
2545
2546         status = hw->phy.ops.read_reg(hw,
2547                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2548                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2549                                       &reg);
2550
2551         if (status != IXGBE_SUCCESS)
2552                 return status;
2553
2554         /* If PHY FW reset completed bit is set then this is the first
2555          * SW instance after a power on so the PHY FW must be un-stalled.
2556          */
2557         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2558                 status = hw->phy.ops.read_reg(hw,
2559                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2560                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2561                                         &reg);
2562
2563                 if (status != IXGBE_SUCCESS)
2564                         return status;
2565
2566                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2567
2568                 status = hw->phy.ops.write_reg(hw,
2569                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2570                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2571                                         reg);
2572
2573                 if (status != IXGBE_SUCCESS)
2574                         return status;
2575         }
2576
2577         return status;
2578 }
2579
2580 /**
2581  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
2582  *  @hw: pointer to hardware structure
2583  **/
2584 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2585 {
2586         /* leave link alone for 2.5G */
2587         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL)
2588                 return IXGBE_SUCCESS;
2589
2590         if (ixgbe_check_reset_blocked(hw))
2591                 return 0;
2592
2593         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2594 }
2595
2596 /**
2597  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2598  *  @hw: pointer to hardware structure
2599  *  @speed: new link speed
2600  *  @autoneg_wait_to_complete: unused
2601  *
2602  *  Configure the external PHY and the integrated KR PHY for SFP support.
2603  **/
2604 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2605                                     ixgbe_link_speed speed,
2606                                     bool autoneg_wait_to_complete)
2607 {
2608         s32 ret_val;
2609         u16 reg_slice, reg_val;
2610         bool setup_linear = false;
2611         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2612
2613         /* Check if SFP module is supported and linear */
2614         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2615
2616         /* If no SFP module present, then return success. Return success since
2617          * there is no reason to configure CS4227 and SFP not present error is
2618          * not excepted in the setup MAC link flow.
2619          */
2620         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2621                 return IXGBE_SUCCESS;
2622
2623         if (ret_val != IXGBE_SUCCESS)
2624                 return ret_val;
2625
2626         /* Configure internal PHY for KR/KX. */
2627         ixgbe_setup_kr_speed_x550em(hw, speed);
2628
2629         /* Configure CS4227 LINE side to proper mode. */
2630         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2631                     (hw->bus.lan_id << 12);
2632         if (setup_linear)
2633                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2634         else
2635                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2636         ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2637                                           reg_val);
2638         return ret_val;
2639 }
2640
2641 /**
2642  *  ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
2643  *  @hw: pointer to hardware structure
2644  *  @speed: the link speed to force
2645  *
2646  *  Configures the integrated PHY for native SFI mode. Used to connect the
2647  *  internal PHY directly to an SFP cage, without autonegotiation.
2648  **/
2649 STATIC s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2650 {
2651         struct ixgbe_mac_info *mac = &hw->mac;
2652         s32 status;
2653         u32 reg_val;
2654
2655         /* Disable all AN and force speed to 10G Serial. */
2656         status = mac->ops.read_iosf_sb_reg(hw,
2657                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2658                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2659         if (status != IXGBE_SUCCESS)
2660                 return status;
2661
2662         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2663         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2664         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2665         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2666
2667         /* Select forced link speed for internal PHY. */
2668         switch (*speed) {
2669         case IXGBE_LINK_SPEED_10GB_FULL:
2670                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
2671                 break;
2672         case IXGBE_LINK_SPEED_1GB_FULL:
2673                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2674                 break;
2675         default:
2676                 /* Other link speeds are not supported by internal PHY. */
2677                 return IXGBE_ERR_LINK_SETUP;
2678         }
2679
2680         status = mac->ops.write_iosf_sb_reg(hw,
2681                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2682                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2683
2684         /* Toggle port SW reset by AN reset. */
2685         status = ixgbe_restart_an_internal_phy_x550em(hw);
2686
2687         return status;
2688 }
2689
2690 /**
2691  *  ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2692  *  @hw: pointer to hardware structure
2693  *  @speed: new link speed
2694  *  @autoneg_wait_to_complete: unused
2695  *
2696  *  Configure the integrated PHY for SFP support.
2697  **/
2698 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2699                                     ixgbe_link_speed speed,
2700                                     bool autoneg_wait_to_complete)
2701 {
2702         s32 ret_val;
2703         u16 reg_phy_ext;
2704         bool setup_linear = false;
2705         u32 reg_slice, reg_phy_int, slice_offset;
2706
2707         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2708
2709         /* Check if SFP module is supported and linear */
2710         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2711
2712         /* If no SFP module present, then return success. Return success since
2713          * SFP not present error is not excepted in the setup MAC link flow.
2714          */
2715         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2716                 return IXGBE_SUCCESS;
2717
2718         if (ret_val != IXGBE_SUCCESS)
2719                 return ret_val;
2720
2721         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2722                 /* Configure internal PHY for native SFI based on module type */
2723                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2724                                    IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2725                                    IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_phy_int);
2726
2727                 if (ret_val != IXGBE_SUCCESS)
2728                         return ret_val;
2729
2730                 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
2731                 if (!setup_linear)
2732                         reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
2733
2734                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2735                                    IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2736                                    IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2737
2738                 if (ret_val != IXGBE_SUCCESS)
2739                         return ret_val;
2740
2741                 /* Setup SFI internal link. */
2742                 ret_val = ixgbe_setup_sfi_x550a(hw, &speed);
2743         } else {
2744                 /* Configure internal PHY for KR/KX. */
2745                 ixgbe_setup_kr_speed_x550em(hw, speed);
2746
2747                 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2748                         /* Find Address */
2749                         DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2750                         return IXGBE_ERR_PHY_ADDR_INVALID;
2751                 }
2752
2753                 /* Get external PHY SKU id */
2754                 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,
2755                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2756
2757                 if (ret_val != IXGBE_SUCCESS)
2758                         return ret_val;
2759
2760                 /* When configuring quad port CS4223, the MAC instance is part
2761                  * of the slice offset.
2762                  */
2763                 if (reg_phy_ext == IXGBE_CS4223_SKU_ID)
2764                         slice_offset = (hw->bus.lan_id +
2765                                         (hw->bus.instance_id << 1)) << 12;
2766                 else
2767                         slice_offset = hw->bus.lan_id << 12;
2768
2769                 /* Configure CS4227/CS4223 LINE side to proper mode. */
2770                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2771
2772                 ret_val = hw->phy.ops.read_reg(hw, reg_slice,
2773                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2774
2775                 if (ret_val != IXGBE_SUCCESS)
2776                         return ret_val;
2777
2778                 reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) |
2779                                  (IXGBE_CS4227_EDC_MODE_SR << 1));
2780
2781                 if (setup_linear)
2782                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2783                 else
2784                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2785                 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2786                                          IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2787
2788                 /* Flush previous write with a read */
2789                 ret_val = hw->phy.ops.read_reg(hw, reg_slice,
2790                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2791         }
2792         return ret_val;
2793 }
2794
2795 /**
2796  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2797  *  @hw: pointer to hardware structure
2798  *
2799  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2800  **/
2801 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2802 {
2803         struct ixgbe_mac_info *mac = &hw->mac;
2804         s32 status;
2805         u32 reg_val;
2806
2807         /* Disable training protocol FSM. */
2808         status = mac->ops.read_iosf_sb_reg(hw,
2809                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2810                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2811         if (status != IXGBE_SUCCESS)
2812                 return status;
2813         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2814         status = mac->ops.write_iosf_sb_reg(hw,
2815                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2816                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2817         if (status != IXGBE_SUCCESS)
2818                 return status;
2819
2820         /* Disable Flex from training TXFFE. */
2821         status = mac->ops.read_iosf_sb_reg(hw,
2822                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2823                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2824         if (status != IXGBE_SUCCESS)
2825                 return status;
2826         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2827         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2828         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2829         status = mac->ops.write_iosf_sb_reg(hw,
2830                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2831                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2832         if (status != IXGBE_SUCCESS)
2833                 return status;
2834         status = mac->ops.read_iosf_sb_reg(hw,
2835                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2836                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2837         if (status != IXGBE_SUCCESS)
2838                 return status;
2839         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2840         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2841         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2842         status = mac->ops.write_iosf_sb_reg(hw,
2843                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2844                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2845         if (status != IXGBE_SUCCESS)
2846                 return status;
2847
2848         /* Enable override for coefficients. */
2849         status = mac->ops.read_iosf_sb_reg(hw,
2850                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2851                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2852         if (status != IXGBE_SUCCESS)
2853                 return status;
2854         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2855         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2856         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2857         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2858         status = mac->ops.write_iosf_sb_reg(hw,
2859                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2860                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2861         return status;
2862 }
2863
2864 /**
2865  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2866  *  @hw: pointer to hardware structure
2867  *  @speed: the link speed to force
2868  *
2869  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
2870  *  internal and external PHY at a specific speed, without autonegotiation.
2871  **/
2872 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2873 {
2874         struct ixgbe_mac_info *mac = &hw->mac;
2875         s32 status;
2876         u32 reg_val;
2877
2878         /* iXFI is only supported with X552 */
2879         if (mac->type != ixgbe_mac_X550EM_x)
2880                 return IXGBE_ERR_LINK_SETUP;
2881
2882         /* Disable AN and force speed to 10G Serial. */
2883         status = mac->ops.read_iosf_sb_reg(hw,
2884                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2885                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2886         if (status != IXGBE_SUCCESS)
2887                 return status;
2888
2889         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2890         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2891
2892         /* Select forced link speed for internal PHY. */
2893         switch (*speed) {
2894         case IXGBE_LINK_SPEED_10GB_FULL:
2895                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2896                 break;
2897         case IXGBE_LINK_SPEED_1GB_FULL:
2898                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2899                 break;
2900         default:
2901                 /* Other link speeds are not supported by internal KR PHY. */
2902                 return IXGBE_ERR_LINK_SETUP;
2903         }
2904
2905         status = mac->ops.write_iosf_sb_reg(hw,
2906                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2907                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2908         if (status != IXGBE_SUCCESS)
2909                 return status;
2910
2911         /* Additional configuration needed for x550em_x */
2912         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2913                 status = ixgbe_setup_ixfi_x550em_x(hw);
2914                 if (status != IXGBE_SUCCESS)
2915                         return status;
2916         }
2917
2918         /* Toggle port SW reset by AN reset. */
2919         status = ixgbe_restart_an_internal_phy_x550em(hw);
2920
2921         return status;
2922 }
2923
2924 /**
2925  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2926  * @hw: address of hardware structure
2927  * @link_up: address of boolean to indicate link status
2928  *
2929  * Returns error code if unable to get link status.
2930  */
2931 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2932 {
2933         u32 ret;
2934         u16 autoneg_status;
2935
2936         *link_up = false;
2937
2938         /* read this twice back to back to indicate current status */
2939         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2940                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2941                                    &autoneg_status);
2942         if (ret != IXGBE_SUCCESS)
2943                 return ret;
2944
2945         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2946                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2947                                    &autoneg_status);
2948         if (ret != IXGBE_SUCCESS)
2949                 return ret;
2950
2951         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2952
2953         return IXGBE_SUCCESS;
2954 }
2955
2956 /**
2957  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2958  * @hw: point to hardware structure
2959  *
2960  * Configures the link between the integrated KR PHY and the external X557 PHY
2961  * The driver will call this function when it gets a link status change
2962  * interrupt from the X557 PHY. This function configures the link speed
2963  * between the PHYs to match the link speed of the BASE-T link.
2964  *
2965  * A return of a non-zero value indicates an error, and the base driver should
2966  * not report link up.
2967  */
2968 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2969 {
2970         ixgbe_link_speed force_speed;
2971         bool link_up;
2972         u32 status;
2973         u16 speed;
2974
2975         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2976                 return IXGBE_ERR_CONFIG;
2977
2978         if (hw->mac.type == ixgbe_mac_X550EM_x &&
2979             !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2980                 /* If link is down, there is no setup necessary so return  */
2981                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2982                 if (status != IXGBE_SUCCESS)
2983                         return status;
2984
2985                 if (!link_up)
2986                         return IXGBE_SUCCESS;
2987
2988                 status = hw->phy.ops.read_reg(hw,
2989                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2990                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2991                                               &speed);
2992                 if (status != IXGBE_SUCCESS)
2993                         return status;
2994
2995                 /* If link is still down - no setup is required so return */
2996                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2997                 if (status != IXGBE_SUCCESS)
2998                         return status;
2999                 if (!link_up)
3000                         return IXGBE_SUCCESS;
3001
3002                 /* clear everything but the speed and duplex bits */
3003                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
3004
3005                 switch (speed) {
3006                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
3007                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3008                         break;
3009                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
3010                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3011                         break;
3012                 default:
3013                         /* Internal PHY does not support anything else */
3014                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
3015                 }
3016
3017                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
3018         } else {
3019                 speed = IXGBE_LINK_SPEED_10GB_FULL |
3020                         IXGBE_LINK_SPEED_1GB_FULL;
3021                 return ixgbe_setup_kr_speed_x550em(hw, speed);
3022         }
3023 }
3024
3025 /**
3026  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
3027  *  @hw: pointer to hardware structure
3028  *
3029  *  Configures the integrated KR PHY to use internal loopback mode.
3030  **/
3031 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
3032 {
3033         s32 status;
3034         u32 reg_val;
3035
3036         /* Disable AN and force speed to 10G Serial. */
3037         status = hw->mac.ops.read_iosf_sb_reg(hw,
3038                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3039                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3040         if (status != IXGBE_SUCCESS)
3041                 return status;
3042         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3043         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3044         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3045         status = hw->mac.ops.write_iosf_sb_reg(hw,
3046                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3047                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3048         if (status != IXGBE_SUCCESS)
3049                 return status;
3050
3051         /* Set near-end loopback clocks. */
3052         status = hw->mac.ops.read_iosf_sb_reg(hw,
3053                                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3054                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3055         if (status != IXGBE_SUCCESS)
3056                 return status;
3057         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3058         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3059         status = hw->mac.ops.write_iosf_sb_reg(hw,
3060                                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3061                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3062         if (status != IXGBE_SUCCESS)
3063                 return status;
3064
3065         /* Set loopback enable. */
3066         status = hw->mac.ops.read_iosf_sb_reg(hw,
3067                                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3068                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3069         if (status != IXGBE_SUCCESS)
3070                 return status;
3071         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3072         status = hw->mac.ops.write_iosf_sb_reg(hw,
3073                                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3074                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3075         if (status != IXGBE_SUCCESS)
3076                 return status;
3077
3078         /* Training bypass. */
3079         status = hw->mac.ops.read_iosf_sb_reg(hw,
3080                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3081                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3082         if (status != IXGBE_SUCCESS)
3083                 return status;
3084         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3085         status = hw->mac.ops.write_iosf_sb_reg(hw,
3086                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3087                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3088
3089         return status;
3090 }
3091
3092 /**
3093  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3094  *  assuming that the semaphore is already obtained.
3095  *  @hw: pointer to hardware structure
3096  *  @offset: offset of  word in the EEPROM to read
3097  *  @data: word read from the EEPROM
3098  *
3099  *  Reads a 16 bit word from the EEPROM using the hostif.
3100  **/
3101 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
3102 {
3103         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3104         struct ixgbe_hic_read_shadow_ram buffer;
3105         s32 status;
3106
3107         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3108         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3109         buffer.hdr.req.buf_lenh = 0;
3110         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3111         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3112
3113         /* convert offset from words to bytes */
3114         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3115         /* one word */
3116         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3117         buffer.pad2 = 0;
3118         buffer.pad3 = 0;
3119
3120         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3121         if (status)
3122                 return status;
3123
3124         status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3125                                     IXGBE_HI_COMMAND_TIMEOUT);
3126         if (!status) {
3127                 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3128                                                   FW_NVM_DATA_OFFSET);
3129         }
3130
3131         hw->mac.ops.release_swfw_sync(hw, mask);
3132         return status;
3133 }
3134
3135 /**
3136  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3137  *  @hw: pointer to hardware structure
3138  *  @offset: offset of  word in the EEPROM to read
3139  *  @words: number of words
3140  *  @data: word(s) read from the EEPROM
3141  *
3142  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
3143  **/
3144 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3145                                      u16 offset, u16 words, u16 *data)
3146 {
3147         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3148         struct ixgbe_hic_read_shadow_ram buffer;
3149         u32 current_word = 0;
3150         u16 words_to_read;
3151         s32 status;
3152         u32 i;
3153
3154         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3155
3156         /* Take semaphore for the entire operation. */
3157         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3158         if (status) {
3159                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3160                 return status;
3161         }
3162
3163         while (words) {
3164                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3165                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3166                 else
3167                         words_to_read = words;
3168
3169                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3170                 buffer.hdr.req.buf_lenh = 0;
3171                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3172                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3173
3174                 /* convert offset from words to bytes */
3175                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3176                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3177                 buffer.pad2 = 0;
3178                 buffer.pad3 = 0;
3179
3180                 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3181                                             IXGBE_HI_COMMAND_TIMEOUT);
3182
3183                 if (status) {
3184                         DEBUGOUT("Host interface command failed\n");
3185                         goto out;
3186                 }
3187
3188                 for (i = 0; i < words_to_read; i++) {
3189                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3190                                   2 * i;
3191                         u32 value = IXGBE_READ_REG(hw, reg);
3192
3193                         data[current_word] = (u16)(value & 0xffff);
3194                         current_word++;
3195                         i++;
3196                         if (i < words_to_read) {
3197                                 value >>= 16;
3198                                 data[current_word] = (u16)(value & 0xffff);
3199                                 current_word++;
3200                         }
3201                 }
3202                 words -= words_to_read;
3203         }
3204
3205 out:
3206         hw->mac.ops.release_swfw_sync(hw, mask);
3207         return status;
3208 }
3209
3210 /**
3211  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3212  *  @hw: pointer to hardware structure
3213  *  @offset: offset of  word in the EEPROM to write
3214  *  @data: word write to the EEPROM
3215  *
3216  *  Write a 16 bit word to the EEPROM using the hostif.
3217  **/
3218 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3219                                     u16 data)
3220 {
3221         s32 status;
3222         struct ixgbe_hic_write_shadow_ram buffer;
3223
3224         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3225
3226         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3227         buffer.hdr.req.buf_lenh = 0;
3228         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3229         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3230
3231          /* one word */
3232         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3233         buffer.data = data;
3234         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3235
3236         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3237                                               sizeof(buffer),
3238                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3239
3240         return status;
3241 }
3242
3243 /**
3244  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3245  *  @hw: pointer to hardware structure
3246  *  @offset: offset of  word in the EEPROM to write
3247  *  @data: word write to the EEPROM
3248  *
3249  *  Write a 16 bit word to the EEPROM using the hostif.
3250  **/
3251 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3252                                u16 data)
3253 {
3254         s32 status = IXGBE_SUCCESS;
3255
3256         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3257
3258         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3259             IXGBE_SUCCESS) {
3260                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3261                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3262         } else {
3263                 DEBUGOUT("write ee hostif failed to get semaphore");
3264                 status = IXGBE_ERR_SWFW_SYNC;
3265         }
3266
3267         return status;
3268 }
3269
3270 /**
3271  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3272  *  @hw: pointer to hardware structure
3273  *  @offset: offset of  word in the EEPROM to write
3274  *  @words: number of words
3275  *  @data: word(s) write to the EEPROM
3276  *
3277  *  Write a 16 bit word(s) to the EEPROM using the hostif.
3278  **/
3279 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3280                                       u16 offset, u16 words, u16 *data)
3281 {
3282         s32 status = IXGBE_SUCCESS;
3283         u32 i = 0;
3284
3285         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3286
3287         /* Take semaphore for the entire operation. */
3288         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3289         if (status != IXGBE_SUCCESS) {
3290                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3291                 goto out;
3292         }
3293
3294         for (i = 0; i < words; i++) {
3295                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3296                                                          data[i]);
3297
3298                 if (status != IXGBE_SUCCESS) {
3299                         DEBUGOUT("Eeprom buffered write failed\n");
3300                         break;
3301                 }
3302         }
3303
3304         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3305 out:
3306
3307         return status;
3308 }
3309
3310 /**
3311  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3312  * @hw: pointer to hardware structure
3313  * @ptr: pointer offset in eeprom
3314  * @size: size of section pointed by ptr, if 0 first word will be used as size
3315  * @csum: address of checksum to update
3316  * @buffer: pointer to buffer containing calculated checksum
3317  * @buffer_size: size of buffer
3318  *
3319  * Returns error status for any failure
3320  */
3321 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3322                                    u16 size, u16 *csum, u16 *buffer,
3323                                    u32 buffer_size)
3324 {
3325         u16 buf[256];
3326         s32 status;
3327         u16 length, bufsz, i, start;
3328         u16 *local_buffer;
3329
3330         bufsz = sizeof(buf) / sizeof(buf[0]);
3331
3332         /* Read a chunk at the pointer location */
3333         if (!buffer) {
3334                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3335                 if (status) {
3336                         DEBUGOUT("Failed to read EEPROM image\n");
3337                         return status;
3338                 }
3339                 local_buffer = buf;
3340         } else {
3341                 if (buffer_size < ptr)
3342                         return  IXGBE_ERR_PARAM;
3343                 local_buffer = &buffer[ptr];
3344         }
3345
3346         if (size) {
3347                 start = 0;
3348                 length = size;
3349         } else {
3350                 start = 1;
3351                 length = local_buffer[0];
3352
3353                 /* Skip pointer section if length is invalid. */
3354                 if (length == 0xFFFF || length == 0 ||
3355                     (ptr + length) >= hw->eeprom.word_size)
3356                         return IXGBE_SUCCESS;
3357         }
3358
3359         if (buffer && ((u32)start + (u32)length > buffer_size))
3360                 return IXGBE_ERR_PARAM;
3361
3362         for (i = start; length; i++, length--) {
3363                 if (i == bufsz && !buffer) {
3364                         ptr += bufsz;
3365                         i = 0;
3366                         if (length < bufsz)
3367                                 bufsz = length;
3368
3369                         /* Read a chunk at the pointer location */
3370                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3371                                                                   bufsz, buf);
3372                         if (status) {
3373                                 DEBUGOUT("Failed to read EEPROM image\n");
3374                                 return status;
3375                         }
3376                 }
3377                 *csum += local_buffer[i];
3378         }
3379         return IXGBE_SUCCESS;
3380 }
3381
3382 /**
3383  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3384  *  @hw: pointer to hardware structure
3385  *  @buffer: pointer to buffer containing calculated checksum
3386  *  @buffer_size: size of buffer
3387  *
3388  *  Returns a negative error code on error, or the 16-bit checksum
3389  **/
3390 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3391 {
3392         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3393         u16 *local_buffer;
3394         s32 status;
3395         u16 checksum = 0;
3396         u16 pointer, i, size;
3397
3398         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3399
3400         hw->eeprom.ops.init_params(hw);
3401
3402         if (!buffer) {
3403                 /* Read pointer area */
3404                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3405                                                      IXGBE_EEPROM_LAST_WORD + 1,
3406                                                      eeprom_ptrs);
3407                 if (status) {
3408                         DEBUGOUT("Failed to read EEPROM image\n");
3409                         return status;
3410                 }
3411                 local_buffer = eeprom_ptrs;
3412         } else {
3413                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3414                         return IXGBE_ERR_PARAM;
3415                 local_buffer = buffer;
3416         }
3417
3418         /*
3419          * For X550 hardware include 0x0-0x41 in the checksum, skip the
3420          * checksum word itself
3421          */
3422         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3423                 if (i != IXGBE_EEPROM_CHECKSUM)
3424                         checksum += local_buffer[i];
3425
3426         /*
3427          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
3428          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3429          */
3430         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3431                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3432                         continue;
3433
3434                 pointer = local_buffer[i];
3435
3436                 /* Skip pointer section if the pointer is invalid. */
3437                 if (pointer == 0xFFFF || pointer == 0 ||
3438                     pointer >= hw->eeprom.word_size)
3439                         continue;
3440
3441                 switch (i) {
3442                 case IXGBE_PCIE_GENERAL_PTR:
3443                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3444                         break;
3445                 case IXGBE_PCIE_CONFIG0_PTR:
3446                 case IXGBE_PCIE_CONFIG1_PTR:
3447                         size = IXGBE_PCIE_CONFIG_SIZE;
3448                         break;
3449                 default:
3450                         size = 0;
3451                         break;
3452                 }
3453
3454                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3455                                                 buffer, buffer_size);
3456                 if (status)
3457                         return status;
3458         }
3459
3460         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3461
3462         return (s32)checksum;
3463 }
3464
3465 /**
3466  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3467  *  @hw: pointer to hardware structure
3468  *
3469  *  Returns a negative error code on error, or the 16-bit checksum
3470  **/
3471 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3472 {
3473         return ixgbe_calc_checksum_X550(hw, NULL, 0);
3474 }
3475
3476 /**
3477  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3478  *  @hw: pointer to hardware structure
3479  *  @checksum_val: calculated checksum
3480  *
3481  *  Performs checksum calculation and validates the EEPROM checksum.  If the
3482  *  caller does not need checksum_val, the value can be NULL.
3483  **/
3484 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3485 {
3486         s32 status;
3487         u16 checksum;
3488         u16 read_checksum = 0;
3489
3490         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3491
3492         /* Read the first word from the EEPROM. If this times out or fails, do
3493          * not continue or we could be in for a very long wait while every
3494          * EEPROM read fails
3495          */
3496         status = hw->eeprom.ops.read(hw, 0, &checksum);
3497         if (status) {
3498                 DEBUGOUT("EEPROM read failed\n");
3499                 return status;
3500         }
3501
3502         status = hw->eeprom.ops.calc_checksum(hw);
3503         if (status < 0)
3504                 return status;
3505
3506         checksum = (u16)(status & 0xffff);
3507
3508         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3509                                            &read_checksum);
3510         if (status)
3511                 return status;
3512
3513         /* Verify read checksum from EEPROM is the same as
3514          * calculated checksum
3515          */
3516         if (read_checksum != checksum) {
3517                 status = IXGBE_ERR_EEPROM_CHECKSUM;
3518                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3519                              "Invalid EEPROM checksum");
3520         }
3521
3522         /* If the user cares, return the calculated checksum */
3523         if (checksum_val)
3524                 *checksum_val = checksum;
3525
3526         return status;
3527 }
3528
3529 /**
3530  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3531  * @hw: pointer to hardware structure
3532  *
3533  * After writing EEPROM to shadow RAM using EEWR register, software calculates
3534  * checksum and updates the EEPROM and instructs the hardware to update
3535  * the flash.
3536  **/
3537 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3538 {
3539         s32 status;
3540         u16 checksum = 0;
3541
3542         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3543
3544         /* Read the first word from the EEPROM. If this times out or fails, do
3545          * not continue or we could be in for a very long wait while every
3546          * EEPROM read fails
3547          */
3548         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3549         if (status) {
3550                 DEBUGOUT("EEPROM read failed\n");
3551                 return status;
3552         }
3553
3554         status = ixgbe_calc_eeprom_checksum_X550(hw);
3555         if (status < 0)
3556                 return status;
3557
3558         checksum = (u16)(status & 0xffff);
3559
3560         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3561                                             checksum);
3562         if (status)
3563                 return status;
3564
3565         status = ixgbe_update_flash_X550(hw);
3566
3567         return status;
3568 }
3569
3570 /**
3571  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3572  *  @hw: pointer to hardware structure
3573  *
3574  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3575  **/
3576 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3577 {
3578         s32 status = IXGBE_SUCCESS;
3579         union ixgbe_hic_hdr2 buffer;
3580
3581         DEBUGFUNC("ixgbe_update_flash_X550");
3582
3583         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3584         buffer.req.buf_lenh = 0;
3585         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3586         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3587
3588         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3589                                               sizeof(buffer),
3590                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3591
3592         return status;
3593 }
3594
3595 /**
3596  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3597  *  @hw: pointer to hardware structure
3598  *
3599  *  Determines physical layer capabilities of the current configuration.
3600  **/
3601 u64 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3602 {
3603         u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3604         u16 ext_ability = 0;
3605
3606         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3607
3608         hw->phy.ops.identify(hw);
3609
3610         switch (hw->phy.type) {
3611         case ixgbe_phy_x550em_kr:
3612                 if (hw->mac.type == ixgbe_mac_X550EM_a) {
3613                         if (hw->phy.nw_mng_if_sel &
3614                             IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
3615                                 physical_layer =
3616                                         IXGBE_PHYSICAL_LAYER_2500BASE_KX;
3617                                 break;
3618                         } else if (hw->device_id ==
3619                                    IXGBE_DEV_ID_X550EM_A_KR_L) {
3620                                 physical_layer =
3621                                         IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3622                                 break;
3623                         }
3624                 }
3625                 /* fall through */
3626         case ixgbe_phy_x550em_xfi:
3627                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3628                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3629                 break;
3630         case ixgbe_phy_x550em_kx4:
3631                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3632                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3633                 break;
3634         case ixgbe_phy_x550em_ext_t:
3635                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3636                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3637                                      &ext_ability);
3638                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3639                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3640                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3641                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3642                 break;
3643         case ixgbe_phy_fw:
3644                 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_1GB_FULL)
3645                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3646                 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_100_FULL)
3647                         physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
3648                 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_10_FULL)
3649                         physical_layer |= IXGBE_PHYSICAL_LAYER_10BASE_T;
3650                 break;
3651         case ixgbe_phy_sgmii:
3652 #ifdef PREBOOT_SUPPORT
3653                 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
3654                                  IXGBE_PHYSICAL_LAYER_100BASE_TX |
3655                                  IXGBE_PHYSICAL_LAYER_10BASE_T;
3656 #else
3657                 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3658 #endif /* PREBOOT_SUPPORT */
3659                 break;
3660         case ixgbe_phy_ext_1g_t:
3661                 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3662                 break;
3663         default:
3664                 break;
3665         }
3666
3667         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3668                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3669
3670         return physical_layer;
3671 }
3672
3673 /**
3674  * ixgbe_get_bus_info_x550em - Set PCI bus info
3675  * @hw: pointer to hardware structure
3676  *
3677  * Sets bus link width and speed to unknown because X550em is
3678  * not a PCI device.
3679  **/
3680 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3681 {
3682
3683         DEBUGFUNC("ixgbe_get_bus_info_x550em");
3684
3685         hw->bus.width = ixgbe_bus_width_unknown;
3686         hw->bus.speed = ixgbe_bus_speed_unknown;
3687
3688         hw->mac.ops.set_lan_id(hw);
3689
3690         return IXGBE_SUCCESS;
3691 }
3692
3693 /**
3694  * ixgbe_disable_rx_x550 - Disable RX unit
3695  * @hw: pointer to hardware structure
3696  *
3697  * Enables the Rx DMA unit for x550
3698  **/
3699 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3700 {
3701         u32 rxctrl, pfdtxgswc;
3702         s32 status;
3703         struct ixgbe_hic_disable_rxen fw_cmd;
3704
3705         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3706
3707         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3708         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3709                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3710                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3711                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3712                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3713                         hw->mac.set_lben = true;
3714                 } else {
3715                         hw->mac.set_lben = false;
3716                 }
3717
3718                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3719                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3720                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3721                 fw_cmd.port_number = (u8)hw->bus.lan_id;
3722
3723                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3724                                         sizeof(struct ixgbe_hic_disable_rxen),
3725                                         IXGBE_HI_COMMAND_TIMEOUT, true);
3726
3727                 /* If we fail - disable RX using register write */
3728                 if (status) {
3729                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3730                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3731                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3732                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3733                         }
3734                 }
3735         }
3736 }
3737
3738 /**
3739  * ixgbe_enter_lplu_x550em - Transition to low power states
3740  *  @hw: pointer to hardware structure
3741  *
3742  * Configures Low Power Link Up on transition to low power states
3743  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3744  * X557 PHY immediately prior to entering LPLU.
3745  **/
3746 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3747 {
3748         u16 an_10g_cntl_reg, autoneg_reg, speed;
3749         s32 status;
3750         ixgbe_link_speed lcd_speed;
3751         u32 save_autoneg;
3752         bool link_up;
3753
3754         /* SW LPLU not required on later HW revisions. */
3755         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3756             (IXGBE_FUSES0_REV_MASK &
3757              IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3758                 return IXGBE_SUCCESS;
3759
3760         /* If blocked by MNG FW, then don't restart AN */
3761         if (ixgbe_check_reset_blocked(hw))
3762                 return IXGBE_SUCCESS;
3763
3764         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3765         if (status != IXGBE_SUCCESS)
3766                 return status;
3767
3768         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3769
3770         if (status != IXGBE_SUCCESS)
3771                 return status;
3772
3773         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3774          * disabled, then force link down by entering low power mode.
3775          */
3776         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3777             !(hw->wol_enabled || ixgbe_mng_present(hw)))
3778                 return ixgbe_set_copper_phy_power(hw, FALSE);
3779
3780         /* Determine LCD */
3781         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3782
3783         if (status != IXGBE_SUCCESS)
3784                 return status;
3785
3786         /* If no valid LCD link speed, then force link down and exit. */
3787         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3788                 return ixgbe_set_copper_phy_power(hw, FALSE);
3789
3790         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3791                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3792                                       &speed);
3793
3794         if (status != IXGBE_SUCCESS)
3795                 return status;
3796
3797         /* If no link now, speed is invalid so take link down */
3798         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3799         if (status != IXGBE_SUCCESS)
3800                 return ixgbe_set_copper_phy_power(hw, false);
3801
3802         /* clear everything but the speed bits */
3803         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3804
3805         /* If current speed is already LCD, then exit. */
3806         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3807              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3808             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3809              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3810                 return status;
3811
3812         /* Clear AN completed indication */
3813         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3814                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3815                                       &autoneg_reg);
3816
3817         if (status != IXGBE_SUCCESS)
3818                 return status;
3819
3820         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3821                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3822                              &an_10g_cntl_reg);
3823
3824         if (status != IXGBE_SUCCESS)
3825                 return status;
3826
3827         status = hw->phy.ops.read_reg(hw,
3828                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3829                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3830                              &autoneg_reg);
3831
3832         if (status != IXGBE_SUCCESS)
3833                 return status;
3834
3835         save_autoneg = hw->phy.autoneg_advertised;
3836
3837         /* Setup link at least common link speed */
3838         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3839
3840         /* restore autoneg from before setting lplu speed */
3841         hw->phy.autoneg_advertised = save_autoneg;
3842
3843         return status;
3844 }
3845
3846 /**
3847  * ixgbe_get_lcd_x550em - Determine lowest common denominator
3848  *  @hw: pointer to hardware structure
3849  *  @lcd_speed: pointer to lowest common link speed
3850  *
3851  * Determine lowest common link speed with link partner.
3852  **/
3853 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3854 {
3855         u16 an_lp_status;
3856         s32 status;
3857         u16 word = hw->eeprom.ctrl_word_3;
3858
3859         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3860
3861         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3862                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3863                                       &an_lp_status);
3864
3865         if (status != IXGBE_SUCCESS)
3866                 return status;
3867
3868         /* If link partner advertised 1G, return 1G */
3869         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3870                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3871                 return status;
3872         }
3873
3874         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3875         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3876             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3877                 return status;
3878
3879         /* Link partner not capable of lower speeds, return 10G */
3880         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3881         return status;
3882 }
3883
3884 /**
3885  *  ixgbe_setup_fc_X550em - Set up flow control
3886  *  @hw: pointer to hardware structure
3887  *
3888  *  Called at init time to set up flow control.
3889  **/
3890 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3891 {
3892         s32 ret_val = IXGBE_SUCCESS;
3893         u32 pause, asm_dir, reg_val;
3894
3895         DEBUGFUNC("ixgbe_setup_fc_X550em");
3896
3897         /* Validate the requested mode */
3898         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3899                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3900                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3901                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3902                 goto out;
3903         }
3904
3905         /* 10gig parts do not have a word in the EEPROM to determine the
3906          * default flow control setting, so we explicitly set it to full.
3907          */
3908         if (hw->fc.requested_mode == ixgbe_fc_default)
3909                 hw->fc.requested_mode = ixgbe_fc_full;
3910
3911         /* Determine PAUSE and ASM_DIR bits. */
3912         switch (hw->fc.requested_mode) {
3913         case ixgbe_fc_none:
3914                 pause = 0;
3915                 asm_dir = 0;
3916                 break;
3917         case ixgbe_fc_tx_pause:
3918                 pause = 0;
3919                 asm_dir = 1;
3920                 break;
3921         case ixgbe_fc_rx_pause:
3922                 /* Rx Flow control is enabled and Tx Flow control is
3923                  * disabled by software override. Since there really
3924                  * isn't a way to advertise that we are capable of RX
3925                  * Pause ONLY, we will advertise that we support both
3926                  * symmetric and asymmetric Rx PAUSE, as such we fall
3927                  * through to the fc_full statement.  Later, we will
3928                  * disable the adapter's ability to send PAUSE frames.
3929                  */
3930         case ixgbe_fc_full:
3931                 pause = 1;
3932                 asm_dir = 1;
3933                 break;
3934         default:
3935                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3936                         "Flow control param set incorrectly\n");
3937                 ret_val = IXGBE_ERR_CONFIG;
3938                 goto out;
3939         }
3940
3941         switch (hw->device_id) {
3942         case IXGBE_DEV_ID_X550EM_X_KR:
3943         case IXGBE_DEV_ID_X550EM_A_KR:
3944         case IXGBE_DEV_ID_X550EM_A_KR_L:
3945                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
3946                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3947                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3948                 if (ret_val != IXGBE_SUCCESS)
3949                         goto out;
3950                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3951                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3952                 if (pause)
3953                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3954                 if (asm_dir)
3955                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3956                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
3957                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3958                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3959
3960                 /* This device does not fully support AN. */
3961                 hw->fc.disable_fc_autoneg = true;
3962                 break;
3963         case IXGBE_DEV_ID_X550EM_X_XFI:
3964                 hw->fc.disable_fc_autoneg = true;
3965                 break;
3966         default:
3967                 break;
3968         }
3969
3970 out:
3971         return ret_val;
3972 }
3973
3974 /**
3975  *  ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
3976  *  @hw: pointer to hardware structure
3977  *
3978  *  Enable flow control according to IEEE clause 37.
3979  **/
3980 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
3981 {
3982         u32 link_s1, lp_an_page_low, an_cntl_1;
3983         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
3984         ixgbe_link_speed speed;
3985         bool link_up;
3986
3987         /* AN should have completed when the cable was plugged in.
3988          * Look for reasons to bail out.  Bail out if:
3989          * - FC autoneg is disabled, or if
3990          * - link is not up.
3991          */
3992         if (hw->fc.disable_fc_autoneg) {
3993                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3994                              "Flow control autoneg is disabled");
3995                 goto out;
3996         }
3997
3998         hw->mac.ops.check_link(hw, &speed, &link_up, false);
3999         if (!link_up) {
4000                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4001                 goto out;
4002         }
4003
4004         /* Check at auto-negotiation has completed */
4005         status = hw->mac.ops.read_iosf_sb_reg(hw,
4006                                         IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4007                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4008
4009         if (status != IXGBE_SUCCESS ||
4010             (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4011                 DEBUGOUT("Auto-Negotiation did not complete\n");
4012                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4013                 goto out;
4014         }
4015
4016         /* Read the 10g AN autoc and LP ability registers and resolve
4017          * local flow control settings accordingly
4018          */
4019         status = hw->mac.ops.read_iosf_sb_reg(hw,
4020                                 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4021                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
4022
4023         if (status != IXGBE_SUCCESS) {
4024                 DEBUGOUT("Auto-Negotiation did not complete\n");
4025                 goto out;
4026         }
4027
4028         status = hw->mac.ops.read_iosf_sb_reg(hw,
4029                                 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
4030                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
4031
4032         if (status != IXGBE_SUCCESS) {
4033                 DEBUGOUT("Auto-Negotiation did not complete\n");
4034                 goto out;
4035         }
4036
4037         status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
4038                                     IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
4039                                     IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
4040                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
4041                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
4042
4043 out:
4044         if (status == IXGBE_SUCCESS) {
4045                 hw->fc.fc_was_autonegged = true;
4046         } else {
4047                 hw->fc.fc_was_autonegged = false;
4048                 hw->fc.current_mode = hw->fc.requested_mode;
4049         }
4050 }
4051
4052 /**
4053  *  ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
4054  *  @hw: pointer to hardware structure
4055  *
4056  **/
4057 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
4058 {
4059         hw->fc.fc_was_autonegged = false;
4060         hw->fc.current_mode = hw->fc.requested_mode;
4061 }
4062
4063 /**
4064  *  ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
4065  *  @hw: pointer to hardware structure
4066  *
4067  *  Enable flow control according to IEEE clause 37.
4068  **/
4069 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
4070 {
4071         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4072         u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
4073         ixgbe_link_speed speed;
4074         bool link_up;
4075
4076         /* AN should have completed when the cable was plugged in.
4077          * Look for reasons to bail out.  Bail out if:
4078          * - FC autoneg is disabled, or if
4079          * - link is not up.
4080          */
4081         if (hw->fc.disable_fc_autoneg) {
4082                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4083                              "Flow control autoneg is disabled");
4084                 goto out;
4085         }
4086
4087         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4088         if (!link_up) {
4089                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4090                 goto out;
4091         }
4092
4093         /* Check if auto-negotiation has completed */
4094         status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info);
4095         if (status != IXGBE_SUCCESS ||
4096             !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) {
4097                 DEBUGOUT("Auto-Negotiation did not complete\n");
4098                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4099                 goto out;
4100         }
4101
4102         /* Negotiate the flow control */
4103         status = ixgbe_negotiate_fc(hw, info[0], info[0],
4104                                     FW_PHY_ACT_GET_LINK_INFO_FC_RX,
4105                                     FW_PHY_ACT_GET_LINK_INFO_FC_TX,
4106                                     FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX,
4107                                     FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX);
4108
4109 out:
4110         if (status == IXGBE_SUCCESS) {
4111                 hw->fc.fc_was_autonegged = true;
4112         } else {
4113                 hw->fc.fc_was_autonegged = false;
4114                 hw->fc.current_mode = hw->fc.requested_mode;
4115         }
4116 }
4117
4118 /**
4119  *  ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4120  *  @hw: pointer to hardware structure
4121  *
4122  *  Called at init time to set up flow control.
4123  **/
4124 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4125 {
4126         s32 status = IXGBE_SUCCESS;
4127         u32 an_cntl = 0;
4128
4129         DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4130
4131         /* Validate the requested mode */
4132         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4133                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4134                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4135                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4136         }
4137
4138         if (hw->fc.requested_mode == ixgbe_fc_default)
4139                 hw->fc.requested_mode = ixgbe_fc_full;
4140
4141         /* Set up the 1G and 10G flow control advertisement registers so the
4142          * HW will be able to do FC autoneg once the cable is plugged in.  If
4143          * we link at 10G, the 1G advertisement is harmless and vice versa.
4144          */
4145         status = hw->mac.ops.read_iosf_sb_reg(hw,
4146                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4147                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4148
4149         if (status != IXGBE_SUCCESS) {
4150                 DEBUGOUT("Auto-Negotiation did not complete\n");
4151                 return status;
4152         }
4153
4154         /* The possible values of fc.requested_mode are:
4155          * 0: Flow control is completely disabled
4156          * 1: Rx flow control is enabled (we can receive pause frames,
4157          *    but not send pause frames).
4158          * 2: Tx flow control is enabled (we can send pause frames but
4159          *    we do not support receiving pause frames).
4160          * 3: Both Rx and Tx flow control (symmetric) are enabled.
4161          * other: Invalid.
4162          */
4163         switch (hw->fc.requested_mode) {
4164         case ixgbe_fc_none:
4165                 /* Flow control completely disabled by software override. */
4166                 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4167                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4168                 break;
4169         case ixgbe_fc_tx_pause:
4170                 /* Tx Flow control is enabled, and Rx Flow control is
4171                  * disabled by software override.
4172                  */
4173                 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4174                 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4175                 break;
4176         case ixgbe_fc_rx_pause:
4177                 /* Rx Flow control is enabled and Tx Flow control is
4178                  * disabled by software override. Since there really
4179                  * isn't a way to advertise that we are capable of RX
4180                  * Pause ONLY, we will advertise that we support both
4181                  * symmetric and asymmetric Rx PAUSE, as such we fall
4182                  * through to the fc_full statement.  Later, we will
4183                  * disable the adapter's ability to send PAUSE frames.
4184                  */
4185         case ixgbe_fc_full:
4186                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4187                 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4188                            IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4189                 break;
4190         default:
4191                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4192                               "Flow control param set incorrectly\n");
4193                 return IXGBE_ERR_CONFIG;
4194         }
4195
4196         status = hw->mac.ops.write_iosf_sb_reg(hw,
4197                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4198                                         IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4199
4200         /* Restart auto-negotiation. */
4201         status = ixgbe_restart_an_internal_phy_x550em(hw);
4202
4203         return status;
4204 }
4205
4206 /**
4207  * ixgbe_set_mux - Set mux for port 1 access with CS4227
4208  * @hw: pointer to hardware structure
4209  * @state: set mux if 1, clear if 0
4210  */
4211 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4212 {
4213         u32 esdp;
4214
4215         if (!hw->bus.lan_id)
4216                 return;
4217         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4218         if (state)
4219                 esdp |= IXGBE_ESDP_SDP1;
4220         else
4221                 esdp &= ~IXGBE_ESDP_SDP1;
4222         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4223         IXGBE_WRITE_FLUSH(hw);
4224 }
4225
4226 /**
4227  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4228  *  @hw: pointer to hardware structure
4229  *  @mask: Mask to specify which semaphore to acquire
4230  *
4231  *  Acquires the SWFW semaphore and sets the I2C MUX
4232  **/
4233 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4234 {
4235         s32 status;
4236
4237         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4238
4239         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4240         if (status)
4241                 return status;
4242
4243         if (mask & IXGBE_GSSR_I2C_MASK)
4244                 ixgbe_set_mux(hw, 1);
4245
4246         return IXGBE_SUCCESS;
4247 }
4248
4249 /**
4250  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4251  *  @hw: pointer to hardware structure
4252  *  @mask: Mask to specify which semaphore to release
4253  *
4254  *  Releases the SWFW semaphore and sets the I2C MUX
4255  **/
4256 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4257 {
4258         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4259
4260         if (mask & IXGBE_GSSR_I2C_MASK)
4261                 ixgbe_set_mux(hw, 0);
4262
4263         ixgbe_release_swfw_sync_X540(hw, mask);
4264 }
4265
4266 /**
4267  *  ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4268  *  @hw: pointer to hardware structure
4269  *  @mask: Mask to specify which semaphore to acquire
4270  *
4271  *  Acquires the SWFW semaphore and get the shared phy token as needed
4272  */
4273 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4274 {
4275         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4276         int retries = FW_PHY_TOKEN_RETRIES;
4277         s32 status = IXGBE_SUCCESS;
4278
4279         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4280
4281         while (--retries) {
4282                 status = IXGBE_SUCCESS;
4283                 if (hmask)
4284                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4285                 if (status) {
4286                         DEBUGOUT1("Could not acquire SWFW semaphore, Status = %d\n",
4287                                   status);
4288                         return status;
4289                 }
4290                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4291                         return IXGBE_SUCCESS;
4292
4293                 status = ixgbe_get_phy_token(hw);
4294                 if (status == IXGBE_ERR_TOKEN_RETRY)
4295                         DEBUGOUT1("Could not acquire PHY token, Status = %d\n",
4296                                   status);
4297
4298                 if (status == IXGBE_SUCCESS)
4299                         return IXGBE_SUCCESS;
4300
4301                 if (hmask)
4302                         ixgbe_release_swfw_sync_X540(hw, hmask);
4303
4304                 if (status != IXGBE_ERR_TOKEN_RETRY) {
4305                         DEBUGOUT1("Unable to retry acquiring the PHY token, Status = %d\n",
4306                                   status);
4307                         return status;
4308                 }
4309         }
4310
4311         DEBUGOUT1("Semaphore acquisition retries failed!: PHY ID = 0x%08X\n",
4312                   hw->phy.id);
4313         return status;
4314 }
4315
4316 /**
4317  *  ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4318  *  @hw: pointer to hardware structure
4319  *  @mask: Mask to specify which semaphore to release
4320  *
4321  *  Releases the SWFW semaphore and puts the shared phy token as needed
4322  */
4323 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4324 {
4325         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4326
4327         DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4328
4329         if (mask & IXGBE_GSSR_TOKEN_SM)
4330                 ixgbe_put_phy_token(hw);
4331
4332         if (hmask)
4333                 ixgbe_release_swfw_sync_X540(hw, hmask);
4334 }
4335
4336 /**
4337  *  ixgbe_read_phy_reg_x550a  - Reads specified PHY register
4338  *  @hw: pointer to hardware structure
4339  *  @reg_addr: 32 bit address of PHY register to read
4340  *  @device_type: 5 bit device type
4341  *  @phy_data: Pointer to read data from PHY register
4342  *
4343  *  Reads a value from a specified PHY register using the SWFW lock and PHY
4344  *  Token. The PHY Token is needed since the MDIO is shared between to MAC
4345  *  instances.
4346  **/
4347 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4348                                u32 device_type, u16 *phy_data)
4349 {
4350         s32 status;
4351         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4352
4353         DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4354
4355         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4356                 return IXGBE_ERR_SWFW_SYNC;
4357
4358         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4359
4360         hw->mac.ops.release_swfw_sync(hw, mask);
4361
4362         return status;
4363 }
4364
4365 /**
4366  *  ixgbe_write_phy_reg_x550a - Writes specified PHY register
4367  *  @hw: pointer to hardware structure
4368  *  @reg_addr: 32 bit PHY register to write
4369  *  @device_type: 5 bit device type
4370  *  @phy_data: Data to write to the PHY register
4371  *
4372  *  Writes a value to specified PHY register using the SWFW lock and PHY Token.
4373  *  The PHY Token is needed since the MDIO is shared between to MAC instances.
4374  **/
4375 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4376                                 u32 device_type, u16 phy_data)
4377 {
4378         s32 status;
4379         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4380
4381         DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4382
4383         if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4384                 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
4385                                                  phy_data);
4386                 hw->mac.ops.release_swfw_sync(hw, mask);
4387         } else {
4388                 status = IXGBE_ERR_SWFW_SYNC;
4389         }
4390
4391         return status;
4392 }
4393
4394 /**
4395  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4396  * @hw: pointer to hardware structure
4397  *
4398  * Handle external Base T PHY interrupt. If high temperature
4399  * failure alarm then return error, else if link status change
4400  * then setup internal/external PHY link
4401  *
4402  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4403  * failure alarm, else return PHY access status.
4404  */
4405 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4406 {
4407         bool lsc;
4408         u32 status;
4409
4410         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4411
4412         if (status != IXGBE_SUCCESS)
4413                 return status;
4414
4415         if (lsc)
4416                 return ixgbe_setup_internal_phy(hw);
4417
4418         return IXGBE_SUCCESS;
4419 }
4420
4421 /**
4422  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4423  * @hw: pointer to hardware structure
4424  * @speed: new link speed
4425  * @autoneg_wait_to_complete: true when waiting for completion is needed
4426  *
4427  * Setup internal/external PHY link speed based on link speed, then set
4428  * external PHY auto advertised link speed.
4429  *
4430  * Returns error status for any failure
4431  **/
4432 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4433                                   ixgbe_link_speed speed,
4434                                   bool autoneg_wait_to_complete)
4435 {
4436         s32 status;
4437         ixgbe_link_speed force_speed;
4438
4439         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4440
4441         /* Setup internal/external PHY link speed to iXFI (10G), unless
4442          * only 1G is auto advertised then setup KX link.
4443          */
4444         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4445                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4446         else
4447                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4448
4449         /* If X552 and internal link mode is XFI, then setup XFI internal link.
4450          */
4451         if (hw->mac.type == ixgbe_mac_X550EM_x &&
4452             !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4453                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4454
4455                 if (status != IXGBE_SUCCESS)
4456                         return status;
4457         }
4458
4459         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4460 }
4461
4462 /**
4463  * ixgbe_check_link_t_X550em - Determine link and speed status
4464  * @hw: pointer to hardware structure
4465  * @speed: pointer to link speed
4466  * @link_up: true when link is up
4467  * @link_up_wait_to_complete: bool used to wait for link up or not
4468  *
4469  * Check that both the MAC and X557 external PHY have link.
4470  **/
4471 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4472                               bool *link_up, bool link_up_wait_to_complete)
4473 {
4474         u32 status;
4475         u16 i, autoneg_status = 0;
4476
4477         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4478                 return IXGBE_ERR_CONFIG;
4479
4480         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4481                                               link_up_wait_to_complete);
4482
4483         /* If check link fails or MAC link is not up, then return */
4484         if (status != IXGBE_SUCCESS || !(*link_up))
4485                 return status;
4486
4487         /* MAC link is up, so check external PHY link.
4488          * X557 PHY. Link status is latching low, and can only be used to detect
4489          * link drop, and not the current status of the link without performing
4490          * back-to-back reads.
4491          */
4492         for (i = 0; i < 2; i++) {
4493                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4494                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4495                                               &autoneg_status);
4496
4497                 if (status != IXGBE_SUCCESS)
4498                         return status;
4499         }
4500
4501         /* If external PHY link is not up, then indicate link not up */
4502         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4503                 *link_up = false;
4504
4505         return IXGBE_SUCCESS;
4506 }
4507
4508 /**
4509  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4510  *  @hw: pointer to hardware structure
4511  **/
4512 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4513 {
4514         s32 status;
4515
4516         status = ixgbe_reset_phy_generic(hw);
4517
4518         if (status != IXGBE_SUCCESS)
4519                 return status;
4520
4521         /* Configure Link Status Alarm and Temperature Threshold interrupts */
4522         return ixgbe_enable_lasi_ext_t_x550em(hw);
4523 }
4524
4525 /**
4526  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4527  *  @hw: pointer to hardware structure
4528  *  @led_idx: led number to turn on
4529  **/
4530 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4531 {
4532         u16 phy_data;
4533
4534         DEBUGFUNC("ixgbe_led_on_t_X550em");
4535
4536         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4537                 return IXGBE_ERR_PARAM;
4538
4539         /* To turn on the LED, set mode to ON. */
4540         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4541                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4542         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4543         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4544                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4545
4546         /* Some designs have the LEDs wired to the MAC */
4547         return ixgbe_led_on_generic(hw, led_idx);
4548 }
4549
4550 /**
4551  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4552  *  @hw: pointer to hardware structure
4553  *  @led_idx: led number to turn off
4554  **/
4555 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4556 {
4557         u16 phy_data;
4558
4559         DEBUGFUNC("ixgbe_led_off_t_X550em");
4560
4561         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4562                 return IXGBE_ERR_PARAM;
4563
4564         /* To turn on the LED, set mode to ON. */
4565         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4566                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4567         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4568         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4569                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4570
4571         /* Some designs have the LEDs wired to the MAC */
4572         return ixgbe_led_off_generic(hw, led_idx);
4573 }
4574
4575 /**
4576  *  ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware
4577  *  @hw: pointer to the HW structure
4578  *  @maj: driver version major number
4579  *  @min: driver version minor number
4580  *  @build: driver version build number
4581  *  @sub: driver version sub build number
4582  *  @len: length of driver_ver string
4583  *  @driver_ver: driver string
4584  *
4585  *  Sends driver version number to firmware through the manageability
4586  *  block.  On success return IXGBE_SUCCESS
4587  *  else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4588  *  semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4589  **/
4590 s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,
4591                               u8 build, u8 sub, u16 len, const char *driver_ver)
4592 {
4593         struct ixgbe_hic_drv_info2 fw_cmd;
4594         s32 ret_val = IXGBE_SUCCESS;
4595         int i;
4596
4597         DEBUGFUNC("ixgbe_set_fw_drv_ver_x550");
4598
4599         if ((len == 0) || (driver_ver == NULL) ||
4600            (len > sizeof(fw_cmd.driver_string)))
4601                 return IXGBE_ERR_INVALID_ARGUMENT;
4602
4603         fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4604         fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len;
4605         fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4606         fw_cmd.port_num = (u8)hw->bus.func;
4607         fw_cmd.ver_maj = maj;
4608         fw_cmd.ver_min = min;
4609         fw_cmd.ver_build = build;
4610         fw_cmd.ver_sub = sub;
4611         fw_cmd.hdr.checksum = 0;
4612         memcpy(fw_cmd.driver_string, driver_ver, len);
4613         fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4614                                 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4615
4616         for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4617                 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4618                                                        sizeof(fw_cmd),
4619                                                        IXGBE_HI_COMMAND_TIMEOUT,
4620                                                        true);
4621                 if (ret_val != IXGBE_SUCCESS)
4622                         continue;
4623
4624                 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4625                     FW_CEM_RESP_STATUS_SUCCESS)
4626                         ret_val = IXGBE_SUCCESS;
4627                 else
4628                         ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4629
4630                 break;
4631         }
4632
4633         return ret_val;
4634 }