1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
46 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
47 * @hw: pointer to hardware structure
49 * Initialize the function pointers and assign the MAC type for X550.
50 * Does not touch the hardware.
52 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
54 struct ixgbe_mac_info *mac = &hw->mac;
55 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
58 DEBUGFUNC("ixgbe_init_ops_X550");
60 ret_val = ixgbe_init_ops_X540(hw);
61 mac->ops.dmac_config = ixgbe_dmac_config_X550;
62 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
63 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
64 mac->ops.setup_eee = ixgbe_setup_eee_X550;
65 mac->ops.set_source_address_pruning =
66 ixgbe_set_source_address_pruning_X550;
67 mac->ops.set_ethertype_anti_spoofing =
68 ixgbe_set_ethertype_anti_spoofing_X550;
70 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
71 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
72 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
73 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
74 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
75 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
76 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
77 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
78 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
80 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
81 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
82 mac->ops.mdd_event = ixgbe_mdd_event_X550;
83 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
84 mac->ops.disable_rx = ixgbe_disable_rx_x550;
85 switch (hw->device_id) {
86 case IXGBE_DEV_ID_X550EM_X_10G_T:
87 case IXGBE_DEV_ID_X550EM_A_10G_T:
88 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
89 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
98 * ixgbe_read_cs4227 - Read CS4227 register
99 * @hw: pointer to hardware structure
100 * @reg: register number to write
101 * @value: pointer to receive value read
103 * Returns status code
105 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
107 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
111 * ixgbe_write_cs4227 - Write CS4227 register
112 * @hw: pointer to hardware structure
113 * @reg: register number to write
114 * @value: value to write to register
116 * Returns status code
118 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
120 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
124 * ixgbe_read_pe - Read register from port expander
125 * @hw: pointer to hardware structure
126 * @reg: register number to read
127 * @value: pointer to receive read value
129 * Returns status code
131 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
135 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
136 if (status != IXGBE_SUCCESS)
137 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
138 "port expander access failed with %d\n", status);
143 * ixgbe_write_pe - Write register to port expander
144 * @hw: pointer to hardware structure
145 * @reg: register number to write
146 * @value: value to write
148 * Returns status code
150 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
154 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
155 if (status != IXGBE_SUCCESS)
156 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
157 "port expander access failed with %d\n", status);
162 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
163 * @hw: pointer to hardware structure
165 * This function assumes that the caller has acquired the proper semaphore.
168 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
175 /* Trigger hard reset. */
176 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
177 if (status != IXGBE_SUCCESS)
179 reg |= IXGBE_PE_BIT1;
180 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
181 if (status != IXGBE_SUCCESS)
184 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
185 if (status != IXGBE_SUCCESS)
187 reg &= ~IXGBE_PE_BIT1;
188 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
189 if (status != IXGBE_SUCCESS)
192 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
193 if (status != IXGBE_SUCCESS)
195 reg &= ~IXGBE_PE_BIT1;
196 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
197 if (status != IXGBE_SUCCESS)
200 usec_delay(IXGBE_CS4227_RESET_HOLD);
202 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
203 if (status != IXGBE_SUCCESS)
205 reg |= IXGBE_PE_BIT1;
206 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
207 if (status != IXGBE_SUCCESS)
210 /* Wait for the reset to complete. */
211 msec_delay(IXGBE_CS4227_RESET_DELAY);
212 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
213 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
215 if (status == IXGBE_SUCCESS &&
216 value == IXGBE_CS4227_EEPROM_LOAD_OK)
218 msec_delay(IXGBE_CS4227_CHECK_DELAY);
220 if (retry == IXGBE_CS4227_RETRIES) {
221 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
222 "CS4227 reset did not complete.");
223 return IXGBE_ERR_PHY;
226 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
227 if (status != IXGBE_SUCCESS ||
228 !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
229 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
230 "CS4227 EEPROM did not load successfully.");
231 return IXGBE_ERR_PHY;
234 return IXGBE_SUCCESS;
238 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
239 * @hw: pointer to hardware structure
241 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
243 s32 status = IXGBE_SUCCESS;
244 u32 swfw_mask = hw->phy.phy_semaphore_mask;
248 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
249 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
250 if (status != IXGBE_SUCCESS) {
251 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
252 "semaphore failed with %d", status);
253 msec_delay(IXGBE_CS4227_CHECK_DELAY);
257 /* Get status of reset flow. */
258 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
260 if (status == IXGBE_SUCCESS &&
261 value == IXGBE_CS4227_RESET_COMPLETE)
264 if (status != IXGBE_SUCCESS ||
265 value != IXGBE_CS4227_RESET_PENDING)
268 /* Reset is pending. Wait and check again. */
269 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
270 msec_delay(IXGBE_CS4227_CHECK_DELAY);
273 /* If still pending, assume other instance failed. */
274 if (retry == IXGBE_CS4227_RETRIES) {
275 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
276 if (status != IXGBE_SUCCESS) {
277 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
278 "semaphore failed with %d", status);
283 /* Reset the CS4227. */
284 status = ixgbe_reset_cs4227(hw);
285 if (status != IXGBE_SUCCESS) {
286 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
287 "CS4227 reset failed: %d", status);
291 /* Reset takes so long, temporarily release semaphore in case the
292 * other driver instance is waiting for the reset indication.
294 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
295 IXGBE_CS4227_RESET_PENDING);
296 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
298 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
299 if (status != IXGBE_SUCCESS) {
300 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
301 "semaphore failed with %d", status);
305 /* Record completion for next time. */
306 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
307 IXGBE_CS4227_RESET_COMPLETE);
310 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
311 msec_delay(hw->eeprom.semaphore_delay);
315 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
316 * @hw: pointer to hardware structure
318 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
320 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
322 if (hw->bus.lan_id) {
323 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
324 esdp |= IXGBE_ESDP_SDP1_DIR;
326 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
327 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
328 IXGBE_WRITE_FLUSH(hw);
332 * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
333 * @hw: pointer to hardware structure
334 * @reg_addr: 32 bit address of PHY register to read
335 * @dev_type: always unused
336 * @phy_data: Pointer to read data from PHY register
338 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
339 u32 dev_type, u16 *phy_data)
341 u32 i, data, command;
342 UNREFERENCED_1PARAMETER(dev_type);
344 /* Setup and write the read command */
345 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
346 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
347 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
348 IXGBE_MSCA_MDI_COMMAND;
350 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
352 /* Check every 10 usec to see if the access completed.
353 * The MDI Command bit will clear when the operation is
356 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
359 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
360 if (!(command & IXGBE_MSCA_MDI_COMMAND))
364 if (command & IXGBE_MSCA_MDI_COMMAND) {
365 ERROR_REPORT1(IXGBE_ERROR_POLLING,
366 "PHY read command did not complete.\n");
367 return IXGBE_ERR_PHY;
370 /* Read operation is complete. Get the data from MSRWD */
371 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
372 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
373 *phy_data = (u16)data;
375 return IXGBE_SUCCESS;
379 * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
380 * @hw: pointer to hardware structure
381 * @reg_addr: 32 bit PHY register to write
382 * @dev_type: always unused
383 * @phy_data: Data to write to the PHY register
385 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
386 u32 dev_type, u16 phy_data)
389 UNREFERENCED_1PARAMETER(dev_type);
391 /* Put the data in the MDI single read and write data register*/
392 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
394 /* Setup and write the write command */
395 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
396 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
397 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
398 IXGBE_MSCA_MDI_COMMAND;
400 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
402 /* Check every 10 usec to see if the access completed.
403 * The MDI Command bit will clear when the operation is
406 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
409 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
410 if (!(command & IXGBE_MSCA_MDI_COMMAND))
414 if (command & IXGBE_MSCA_MDI_COMMAND) {
415 ERROR_REPORT1(IXGBE_ERROR_POLLING,
416 "PHY write cmd didn't complete\n");
417 return IXGBE_ERR_PHY;
420 return IXGBE_SUCCESS;
424 * ixgbe_identify_phy_x550em - Get PHY type based on device id
425 * @hw: pointer to hardware structure
429 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
431 switch (hw->device_id) {
432 case IXGBE_DEV_ID_X550EM_A_SFP:
433 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
434 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
436 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
438 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
439 return ixgbe_identify_module_generic(hw);
440 case IXGBE_DEV_ID_X550EM_X_SFP:
441 /* set up for CS4227 usage */
442 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
443 ixgbe_setup_mux_ctl(hw);
444 ixgbe_check_cs4227(hw);
447 case IXGBE_DEV_ID_X550EM_A_SFP_N:
448 return ixgbe_identify_module_generic(hw);
450 case IXGBE_DEV_ID_X550EM_X_KX4:
451 hw->phy.type = ixgbe_phy_x550em_kx4;
453 case IXGBE_DEV_ID_X550EM_X_KR:
454 case IXGBE_DEV_ID_X550EM_A_KR:
455 case IXGBE_DEV_ID_X550EM_A_KR_L:
456 hw->phy.type = ixgbe_phy_x550em_kr;
458 case IXGBE_DEV_ID_X550EM_A_10G_T:
459 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
460 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
461 /* Fallthrough to ixgbe_identify_phy_generic */
462 case IXGBE_DEV_ID_X550EM_A_1G_T:
463 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
464 case IXGBE_DEV_ID_X550EM_X_1G_T:
465 case IXGBE_DEV_ID_X550EM_X_10G_T:
466 return ixgbe_identify_phy_generic(hw);
470 return IXGBE_SUCCESS;
473 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
474 u32 device_type, u16 *phy_data)
476 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
477 return IXGBE_NOT_IMPLEMENTED;
480 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
481 u32 device_type, u16 phy_data)
483 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
484 return IXGBE_NOT_IMPLEMENTED;
488 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
489 * @hw: pointer to the hardware structure
490 * @addr: I2C bus address to read from
491 * @reg: I2C device register to read from
492 * @val: pointer to location to receive read value
494 * Returns an error code on error.
496 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
499 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
503 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
504 * @hw: pointer to the hardware structure
505 * @addr: I2C bus address to read from
506 * @reg: I2C device register to read from
507 * @val: pointer to location to receive read value
509 * Returns an error code on error.
512 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
515 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
519 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
520 * @hw: pointer to the hardware structure
521 * @addr: I2C bus address to write to
522 * @reg: I2C device register to write to
523 * @val: value to write
525 * Returns an error code on error.
527 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
528 u8 addr, u16 reg, u16 val)
530 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
534 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
535 * @hw: pointer to the hardware structure
536 * @addr: I2C bus address to write to
537 * @reg: I2C device register to write to
538 * @val: value to write
540 * Returns an error code on error.
543 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
544 u8 addr, u16 reg, u16 val)
546 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
550 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
551 * @hw: pointer to hardware structure
553 * Initialize the function pointers and for MAC type X550EM.
554 * Does not touch the hardware.
556 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
558 struct ixgbe_mac_info *mac = &hw->mac;
559 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
560 struct ixgbe_phy_info *phy = &hw->phy;
563 DEBUGFUNC("ixgbe_init_ops_X550EM");
565 /* Similar to X550 so start there. */
566 ret_val = ixgbe_init_ops_X550(hw);
568 /* Since this function eventually calls
569 * ixgbe_init_ops_540 by design, we are setting
570 * the pointers to NULL explicitly here to overwrite
571 * the values being set in the x540 function.
573 /* Thermal sensor not supported in x550EM */
574 mac->ops.get_thermal_sensor_data = NULL;
575 mac->ops.init_thermal_sensor_thresh = NULL;
576 mac->thermal_sensor_enabled = false;
578 /* FCOE not supported in x550EM */
579 mac->ops.get_san_mac_addr = NULL;
580 mac->ops.set_san_mac_addr = NULL;
581 mac->ops.get_wwn_prefix = NULL;
582 mac->ops.get_fcoe_boot_status = NULL;
584 /* IPsec not supported in x550EM */
585 mac->ops.disable_sec_rx_path = NULL;
586 mac->ops.enable_sec_rx_path = NULL;
588 /* AUTOC register is not present in x550EM. */
589 mac->ops.prot_autoc_read = NULL;
590 mac->ops.prot_autoc_write = NULL;
592 /* X550EM bus type is internal*/
593 hw->bus.type = ixgbe_bus_type_internal;
594 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
597 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
598 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
599 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
600 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
601 mac->ops.get_supported_physical_layer =
602 ixgbe_get_supported_physical_layer_X550em;
604 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
605 mac->ops.setup_fc = ixgbe_setup_fc_generic;
607 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
609 switch (hw->device_id) {
610 case IXGBE_DEV_ID_X550EM_X_KR:
611 case IXGBE_DEV_ID_X550EM_A_KR:
612 case IXGBE_DEV_ID_X550EM_A_KR_L:
615 mac->ops.setup_eee = NULL;
619 phy->ops.init = ixgbe_init_phy_ops_X550em;
620 phy->ops.identify = ixgbe_identify_phy_x550em;
621 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
622 phy->ops.set_phy_power = NULL;
626 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
627 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
628 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
629 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
630 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
631 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
632 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
633 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
639 * ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
640 * @hw: pointer to hardware structure
642 * Initialize the function pointers and for MAC type X550EM_a.
643 * Does not touch the hardware.
645 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
647 struct ixgbe_mac_info *mac = &hw->mac;
650 DEBUGFUNC("ixgbe_init_ops_X550EM_a");
652 /* Start with generic X550EM init */
653 ret_val = ixgbe_init_ops_X550EM(hw);
655 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
656 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) {
657 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
658 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
660 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
661 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
663 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
664 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
666 switch (mac->ops.get_media_type(hw)) {
667 case ixgbe_media_type_fiber:
668 mac->ops.setup_fc = ixgbe_setup_fc_fiber_x550em_a;
669 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
671 case ixgbe_media_type_backplane:
672 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
673 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
679 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T) ||
680 (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)) {
681 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
682 mac->ops.setup_fc = ixgbe_setup_fc_sgmii_x550em_a;
689 * ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
690 * @hw: pointer to hardware structure
692 * Initialize the function pointers and for MAC type X550EM_x.
693 * Does not touch the hardware.
695 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
697 struct ixgbe_mac_info *mac = &hw->mac;
698 struct ixgbe_link_info *link = &hw->link;
701 DEBUGFUNC("ixgbe_init_ops_X550EM_x");
703 /* Start with generic X550EM init */
704 ret_val = ixgbe_init_ops_X550EM(hw);
706 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
707 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
708 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
709 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
710 link->ops.read_link = ixgbe_read_i2c_combined_generic;
711 link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
712 link->ops.write_link = ixgbe_write_i2c_combined_generic;
713 link->ops.write_link_unlocked =
714 ixgbe_write_i2c_combined_generic_unlocked;
715 link->addr = IXGBE_CS4227;
721 * ixgbe_dmac_config_X550
722 * @hw: pointer to hardware structure
724 * Configure DMA coalescing. If enabling dmac, dmac is activated.
725 * When disabling dmac, dmac enable dmac bit is cleared.
727 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
729 u32 reg, high_pri_tc;
731 DEBUGFUNC("ixgbe_dmac_config_X550");
733 /* Disable DMA coalescing before configuring */
734 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
735 reg &= ~IXGBE_DMACR_DMAC_EN;
736 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
738 /* Disable DMA Coalescing if the watchdog timer is 0 */
739 if (!hw->mac.dmac_config.watchdog_timer)
742 ixgbe_dmac_config_tcs_X550(hw);
744 /* Configure DMA Coalescing Control Register */
745 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
747 /* Set the watchdog timer in units of 40.96 usec */
748 reg &= ~IXGBE_DMACR_DMACWT_MASK;
749 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
751 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
752 /* If fcoe is enabled, set high priority traffic class */
753 if (hw->mac.dmac_config.fcoe_en) {
754 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
755 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
756 IXGBE_DMACR_HIGH_PRI_TC_MASK);
758 reg |= IXGBE_DMACR_EN_MNG_IND;
760 /* Enable DMA coalescing after configuration */
761 reg |= IXGBE_DMACR_DMAC_EN;
762 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
765 return IXGBE_SUCCESS;
769 * ixgbe_dmac_config_tcs_X550
770 * @hw: pointer to hardware structure
772 * Configure DMA coalescing threshold per TC. The dmac enable bit must
773 * be cleared before configuring.
775 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
777 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
779 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
781 /* Configure DMA coalescing enabled */
782 switch (hw->mac.dmac_config.link_speed) {
783 case IXGBE_LINK_SPEED_10_FULL:
784 case IXGBE_LINK_SPEED_100_FULL:
785 pb_headroom = IXGBE_DMACRXT_100M;
787 case IXGBE_LINK_SPEED_1GB_FULL:
788 pb_headroom = IXGBE_DMACRXT_1G;
791 pb_headroom = IXGBE_DMACRXT_10G;
795 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
796 IXGBE_MHADD_MFS_SHIFT) / 1024);
798 /* Set the per Rx packet buffer receive threshold */
799 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
800 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
801 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
803 if (tc < hw->mac.dmac_config.num_tcs) {
805 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
806 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
807 IXGBE_RXPBSIZE_SHIFT;
809 /* Calculate receive buffer threshold in kilobytes */
810 if (rx_pb_size > pb_headroom)
811 rx_pb_size = rx_pb_size - pb_headroom;
815 /* Minimum of MFS shall be set for DMCTH */
816 reg |= (rx_pb_size > maxframe_size_kb) ?
817 rx_pb_size : maxframe_size_kb;
819 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
821 return IXGBE_SUCCESS;
825 * ixgbe_dmac_update_tcs_X550
826 * @hw: pointer to hardware structure
828 * Disables dmac, updates per TC settings, and then enables dmac.
830 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
834 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
836 /* Disable DMA coalescing before configuring */
837 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
838 reg &= ~IXGBE_DMACR_DMAC_EN;
839 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
841 ixgbe_dmac_config_tcs_X550(hw);
843 /* Enable DMA coalescing after configuration */
844 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
845 reg |= IXGBE_DMACR_DMAC_EN;
846 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
848 return IXGBE_SUCCESS;
852 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
853 * @hw: pointer to hardware structure
855 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
856 * ixgbe_hw struct in order to set up EEPROM access.
858 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
860 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
864 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
866 if (eeprom->type == ixgbe_eeprom_uninitialized) {
867 eeprom->semaphore_delay = 10;
868 eeprom->type = ixgbe_flash;
870 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
871 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
872 IXGBE_EEC_SIZE_SHIFT);
873 eeprom->word_size = 1 << (eeprom_size +
874 IXGBE_EEPROM_WORD_SIZE_SHIFT);
876 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
877 eeprom->type, eeprom->word_size);
880 return IXGBE_SUCCESS;
884 * ixgbe_enable_eee_x550 - Enable EEE support
885 * @hw: pointer to hardware structure
887 STATIC s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
893 if (hw->mac.type == ixgbe_mac_X550) {
894 /* Advertise EEE capability */
895 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
896 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
899 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
900 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
901 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
903 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
904 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
906 return IXGBE_SUCCESS;
909 switch (hw->device_id) {
910 case IXGBE_DEV_ID_X550EM_X_KR:
911 case IXGBE_DEV_ID_X550EM_A_KR:
912 case IXGBE_DEV_ID_X550EM_A_KR_L:
913 status = hw->mac.ops.read_iosf_sb_reg(hw,
914 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
915 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
916 if (status != IXGBE_SUCCESS)
919 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
920 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
922 /* Don't advertise FEC capability when EEE enabled. */
923 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
925 status = hw->mac.ops.write_iosf_sb_reg(hw,
926 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
927 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
928 if (status != IXGBE_SUCCESS)
935 return IXGBE_SUCCESS;
939 * ixgbe_disable_eee_x550 - Disable EEE support
940 * @hw: pointer to hardware structure
942 STATIC s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
948 if (hw->mac.type == ixgbe_mac_X550) {
949 /* Disable advertised EEE capability */
950 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
951 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
954 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
955 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
956 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
958 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
959 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
961 return IXGBE_SUCCESS;
964 switch (hw->device_id) {
965 case IXGBE_DEV_ID_X550EM_X_KR:
966 case IXGBE_DEV_ID_X550EM_A_KR:
967 case IXGBE_DEV_ID_X550EM_A_KR_L:
968 status = hw->mac.ops.read_iosf_sb_reg(hw,
969 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
970 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
971 if (status != IXGBE_SUCCESS)
974 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
975 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
977 /* Advertise FEC capability when EEE is disabled. */
978 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
980 status = hw->mac.ops.write_iosf_sb_reg(hw,
981 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
982 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
983 if (status != IXGBE_SUCCESS)
990 return IXGBE_SUCCESS;
994 * ixgbe_setup_eee_X550 - Enable/disable EEE support
995 * @hw: pointer to the HW structure
996 * @enable_eee: boolean flag to enable EEE
998 * Enable/disable EEE based on enable_eee flag.
999 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
1003 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
1008 DEBUGFUNC("ixgbe_setup_eee_X550");
1010 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
1011 /* Enable or disable EEE per flag */
1013 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1015 /* Not supported on first revision of X550EM_x. */
1016 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
1017 !(IXGBE_FUSES0_REV_MASK &
1018 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
1019 return IXGBE_SUCCESS;
1020 status = ixgbe_enable_eee_x550(hw);
1024 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1026 status = ixgbe_disable_eee_x550(hw);
1030 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
1032 return IXGBE_SUCCESS;
1036 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1037 * @hw: pointer to hardware structure
1038 * @enable: enable or disable source address pruning
1039 * @pool: Rx pool to set source address pruning for
1041 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1046 /* max rx pool is 63 */
1050 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1051 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1054 pfflp |= (1ULL << pool);
1056 pfflp &= ~(1ULL << pool);
1058 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1059 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1063 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1064 * @hw: pointer to hardware structure
1065 * @enable: enable or disable switch for Ethertype anti-spoofing
1066 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1069 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1070 bool enable, int vf)
1072 int vf_target_reg = vf >> 3;
1073 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1076 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1078 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1080 pfvfspoof |= (1 << vf_target_shift);
1082 pfvfspoof &= ~(1 << vf_target_shift);
1084 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1088 * ixgbe_iosf_wait - Wait for IOSF command completion
1089 * @hw: pointer to hardware structure
1090 * @ctrl: pointer to location to receive final IOSF control value
1092 * Returns failing status on timeout
1094 * Note: ctrl can be NULL if the IOSF control register value is not needed
1096 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1100 /* Check every 10 usec to see if the address cycle completed.
1101 * The SB IOSF BUSY bit will clear when the operation is
1104 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1105 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1106 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1112 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1113 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1114 return IXGBE_ERR_PHY;
1117 return IXGBE_SUCCESS;
1121 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register
1122 * of the IOSF device
1123 * @hw: pointer to hardware structure
1124 * @reg_addr: 32 bit PHY register to write
1125 * @device_type: 3 bit device type
1126 * @data: Data to write to the register
1128 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1129 u32 device_type, u32 data)
1131 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1135 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1136 if (ret != IXGBE_SUCCESS)
1139 ret = ixgbe_iosf_wait(hw, NULL);
1140 if (ret != IXGBE_SUCCESS)
1143 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1144 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1146 /* Write IOSF control register */
1147 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1149 /* Write IOSF data register */
1150 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1152 ret = ixgbe_iosf_wait(hw, &command);
1154 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1155 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1156 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1157 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1158 "Failed to write, error %x\n", error);
1159 ret = IXGBE_ERR_PHY;
1163 ixgbe_release_swfw_semaphore(hw, gssr);
1168 * ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device
1169 * @hw: pointer to hardware structure
1170 * @reg_addr: 32 bit PHY register to write
1171 * @device_type: 3 bit device type
1172 * @data: Pointer to read data from the register
1174 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1175 u32 device_type, u32 *data)
1177 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1181 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1182 if (ret != IXGBE_SUCCESS)
1185 ret = ixgbe_iosf_wait(hw, NULL);
1186 if (ret != IXGBE_SUCCESS)
1189 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1190 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1192 /* Write IOSF control register */
1193 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1195 ret = ixgbe_iosf_wait(hw, &command);
1197 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1198 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1199 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1200 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1201 "Failed to read, error %x\n", error);
1202 ret = IXGBE_ERR_PHY;
1205 if (ret == IXGBE_SUCCESS)
1206 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1209 ixgbe_release_swfw_semaphore(hw, gssr);
1214 * ixgbe_get_phy_token - Get the token for shared phy access
1215 * @hw: Pointer to hardware structure
1218 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1220 struct ixgbe_hic_phy_token_req token_cmd;
1223 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1224 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1225 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1226 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1227 token_cmd.port_number = hw->bus.lan_id;
1228 token_cmd.command_type = FW_PHY_TOKEN_REQ;
1230 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1232 IXGBE_HI_COMMAND_TIMEOUT,
1236 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1237 return IXGBE_SUCCESS;
1238 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1239 return IXGBE_ERR_FW_RESP_INVALID;
1241 return IXGBE_ERR_TOKEN_RETRY;
1245 * ixgbe_put_phy_token - Put the token for shared phy access
1246 * @hw: Pointer to hardware structure
1249 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1251 struct ixgbe_hic_phy_token_req token_cmd;
1254 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1255 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1256 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1257 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1258 token_cmd.port_number = hw->bus.lan_id;
1259 token_cmd.command_type = FW_PHY_TOKEN_REL;
1261 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1263 IXGBE_HI_COMMAND_TIMEOUT,
1267 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1268 return IXGBE_SUCCESS;
1270 DEBUGOUT("Put PHY Token host interface command failed");
1271 return IXGBE_ERR_FW_RESP_INVALID;
1275 * ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1276 * of the IOSF device
1277 * @hw: pointer to hardware structure
1278 * @reg_addr: 32 bit PHY register to write
1279 * @device_type: 3 bit device type
1280 * @data: Data to write to the register
1282 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1283 u32 device_type, u32 data)
1285 struct ixgbe_hic_internal_phy_req write_cmd;
1287 UNREFERENCED_1PARAMETER(device_type);
1289 memset(&write_cmd, 0, sizeof(write_cmd));
1290 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1291 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1292 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1293 write_cmd.port_number = hw->bus.lan_id;
1294 write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1295 write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1296 write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1298 status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1300 IXGBE_HI_COMMAND_TIMEOUT, false);
1306 * ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device
1307 * @hw: pointer to hardware structure
1308 * @reg_addr: 32 bit PHY register to write
1309 * @device_type: 3 bit device type
1310 * @data: Pointer to read data from the register
1312 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1313 u32 device_type, u32 *data)
1316 struct ixgbe_hic_internal_phy_req cmd;
1317 struct ixgbe_hic_internal_phy_resp rsp;
1320 UNREFERENCED_1PARAMETER(device_type);
1322 memset(&hic, 0, sizeof(hic));
1323 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1324 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1325 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1326 hic.cmd.port_number = hw->bus.lan_id;
1327 hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1328 hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1330 status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1332 IXGBE_HI_COMMAND_TIMEOUT, true);
1334 /* Extract the register value from the response. */
1335 *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1341 * ixgbe_disable_mdd_X550
1342 * @hw: pointer to hardware structure
1344 * Disable malicious driver detection
1346 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1350 DEBUGFUNC("ixgbe_disable_mdd_X550");
1352 /* Disable MDD for TX DMA and interrupt */
1353 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1354 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1355 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1357 /* Disable MDD for RX and interrupt */
1358 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1359 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1360 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1364 * ixgbe_enable_mdd_X550
1365 * @hw: pointer to hardware structure
1367 * Enable malicious driver detection
1369 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1373 DEBUGFUNC("ixgbe_enable_mdd_X550");
1375 /* Enable MDD for TX DMA and interrupt */
1376 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1377 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1378 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1380 /* Enable MDD for RX and interrupt */
1381 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1382 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1383 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1387 * ixgbe_restore_mdd_vf_X550
1388 * @hw: pointer to hardware structure
1391 * Restore VF that was disabled during malicious driver detection event
1393 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1395 u32 idx, reg, num_qs, start_q, bitmask;
1397 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1399 /* Map VF to queues */
1400 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1401 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1402 case IXGBE_MRQC_VMDQRT8TCEN:
1403 num_qs = 8; /* 16 VFs / pools */
1404 bitmask = 0x000000FF;
1406 case IXGBE_MRQC_VMDQRSS32EN:
1407 case IXGBE_MRQC_VMDQRT4TCEN:
1408 num_qs = 4; /* 32 VFs / pools */
1409 bitmask = 0x0000000F;
1411 default: /* 64 VFs / pools */
1413 bitmask = 0x00000003;
1416 start_q = vf * num_qs;
1418 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1421 reg |= (bitmask << (start_q % 32));
1422 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1423 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1427 * ixgbe_mdd_event_X550
1428 * @hw: pointer to hardware structure
1429 * @vf_bitmap: vf bitmap of malicious vfs
1431 * Handle malicious driver detection event.
1433 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1436 u32 i, j, reg, q, shift, vf, idx;
1438 DEBUGFUNC("ixgbe_mdd_event_X550");
1440 /* figure out pool size for mapping to vf's */
1441 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1442 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1443 case IXGBE_MRQC_VMDQRT8TCEN:
1444 shift = 3; /* 16 VFs / pools */
1446 case IXGBE_MRQC_VMDQRSS32EN:
1447 case IXGBE_MRQC_VMDQRT4TCEN:
1448 shift = 2; /* 32 VFs / pools */
1451 shift = 1; /* 64 VFs / pools */
1455 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1456 for (i = 0; i < 4; i++) {
1457 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1458 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1463 /* Get malicious queue */
1464 for (j = 0; j < 32 && wqbr; j++) {
1466 if (!(wqbr & (1 << j)))
1469 /* Get queue from bitmask */
1472 /* Map queue to vf */
1475 /* Set vf bit in vf_bitmap */
1477 vf_bitmap[idx] |= (1 << (vf % 32));
1484 * ixgbe_get_media_type_X550em - Get media type
1485 * @hw: pointer to hardware structure
1487 * Returns the media type (fiber, copper, backplane)
1489 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1491 enum ixgbe_media_type media_type;
1493 DEBUGFUNC("ixgbe_get_media_type_X550em");
1495 /* Detect if there is a copper PHY attached. */
1496 switch (hw->device_id) {
1497 case IXGBE_DEV_ID_X550EM_X_KR:
1498 case IXGBE_DEV_ID_X550EM_X_KX4:
1499 case IXGBE_DEV_ID_X550EM_A_KR:
1500 case IXGBE_DEV_ID_X550EM_A_KR_L:
1501 media_type = ixgbe_media_type_backplane;
1503 case IXGBE_DEV_ID_X550EM_X_SFP:
1504 case IXGBE_DEV_ID_X550EM_A_SFP:
1505 case IXGBE_DEV_ID_X550EM_A_SFP_N:
1506 case IXGBE_DEV_ID_X550EM_A_QSFP:
1507 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1508 media_type = ixgbe_media_type_fiber;
1510 case IXGBE_DEV_ID_X550EM_X_1G_T:
1511 case IXGBE_DEV_ID_X550EM_X_10G_T:
1512 case IXGBE_DEV_ID_X550EM_A_10G_T:
1513 media_type = ixgbe_media_type_copper;
1515 case IXGBE_DEV_ID_X550EM_A_SGMII:
1516 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1517 media_type = ixgbe_media_type_backplane;
1518 hw->phy.type = ixgbe_phy_sgmii;
1520 case IXGBE_DEV_ID_X550EM_A_1G_T:
1521 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1522 media_type = ixgbe_media_type_copper;
1525 media_type = ixgbe_media_type_unknown;
1532 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1533 * @hw: pointer to hardware structure
1534 * @linear: true if SFP module is linear
1536 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1538 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1540 switch (hw->phy.sfp_type) {
1541 case ixgbe_sfp_type_not_present:
1542 return IXGBE_ERR_SFP_NOT_PRESENT;
1543 case ixgbe_sfp_type_da_cu_core0:
1544 case ixgbe_sfp_type_da_cu_core1:
1547 case ixgbe_sfp_type_srlr_core0:
1548 case ixgbe_sfp_type_srlr_core1:
1549 case ixgbe_sfp_type_da_act_lmt_core0:
1550 case ixgbe_sfp_type_da_act_lmt_core1:
1551 case ixgbe_sfp_type_1g_sx_core0:
1552 case ixgbe_sfp_type_1g_sx_core1:
1553 case ixgbe_sfp_type_1g_lx_core0:
1554 case ixgbe_sfp_type_1g_lx_core1:
1557 case ixgbe_sfp_type_unknown:
1558 case ixgbe_sfp_type_1g_cu_core0:
1559 case ixgbe_sfp_type_1g_cu_core1:
1561 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1564 return IXGBE_SUCCESS;
1568 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1569 * @hw: pointer to hardware structure
1571 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1573 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1578 DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1580 status = ixgbe_identify_module_generic(hw);
1582 if (status != IXGBE_SUCCESS)
1585 /* Check if SFP module is supported */
1586 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1592 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1593 * @hw: pointer to hardware structure
1595 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1600 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1602 /* Check if SFP module is supported */
1603 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1605 if (status != IXGBE_SUCCESS)
1608 ixgbe_init_mac_link_ops_X550em(hw);
1609 hw->phy.ops.reset = NULL;
1611 return IXGBE_SUCCESS;
1615 * ixgbe_setup_sgmii - Set up link for sgmii
1616 * @hw: pointer to hardware structure
1618 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1621 struct ixgbe_mac_info *mac = &hw->mac;
1625 rc = mac->ops.read_iosf_sb_reg(hw,
1626 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1627 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1631 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1632 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1633 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1634 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1635 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1636 rc = mac->ops.write_iosf_sb_reg(hw,
1637 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1638 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1642 rc = mac->ops.read_iosf_sb_reg(hw,
1643 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1644 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1648 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1649 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1650 rc = mac->ops.write_iosf_sb_reg(hw,
1651 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1652 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1656 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1657 rc = mac->ops.write_iosf_sb_reg(hw,
1658 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1659 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1663 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1667 * ixgbe_setup_sgmii_m88 - Set up link for sgmii with Marvell PHYs
1668 * @hw: pointer to hardware structure
1670 STATIC s32 ixgbe_setup_sgmii_m88(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1673 struct ixgbe_mac_info *mac = &hw->mac;
1677 rc = mac->ops.read_iosf_sb_reg(hw,
1678 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1679 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1683 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1684 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1685 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1686 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1687 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1688 rc = mac->ops.write_iosf_sb_reg(hw,
1689 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1690 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1694 rc = mac->ops.read_iosf_sb_reg(hw,
1695 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1696 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1700 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1701 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1702 rc = mac->ops.write_iosf_sb_reg(hw,
1703 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1704 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1708 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1709 rc = mac->ops.write_iosf_sb_reg(hw,
1710 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1711 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1715 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1719 * ixgbe_check_link_m88 - Poll PHY for link
1720 * @hw: pointer to hardware structure
1721 * @speed: pointer to link speed
1722 * @link_up: true when link is up
1723 * @link_up_wait: bool indicating whether to wait for link
1725 * Check that both the MAC and PHY have link.
1728 ixgbe_check_link_m88(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1729 bool *link_up, bool link_up_wait)
1735 rc = ixgbe_check_mac_link_generic(hw, speed, link_up, link_up_wait);
1736 if (rc || !*link_up)
1739 rc = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_PHY_SPEC_STATUS, 0, ®);
1741 /* MAC link is up, so check external PHY link */
1742 *link_up = !!(reg & IXGBE_M88E1500_PHY_SPEC_STATUS_LINK);
1745 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
1747 (reg & IXGBE_M88E1500_PHY_SPEC_STATUS_LINK)) {
1753 rc = hw->phy.ops.read_reg(hw,
1754 IXGBE_M88E1500_PHY_SPEC_STATUS,
1759 #define M88_SPEED(x) (IXGBE_M88E1500_PHY_SPEC_STATUS_RESOLVED | \
1760 IXGBE_M88E1500_PHY_SPEC_STATUS_DUPLEX | \
1761 ((IXGBE_M88E1500_PHY_SPEC_STATUS_SPEED_##x) <<\
1762 IXGBE_M88E1500_PHY_SPEC_STATUS_SPEED_SHIFT))
1764 reg &= M88_SPEED(MASK);
1767 *speed = IXGBE_LINK_SPEED_10_FULL;
1769 case M88_SPEED(100):
1770 *speed = IXGBE_LINK_SPEED_100_FULL;
1772 case M88_SPEED(1000):
1773 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1776 *speed = IXGBE_LINK_SPEED_UNKNOWN;
1785 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1786 * @hw: pointer to hardware structure
1788 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1790 struct ixgbe_mac_info *mac = &hw->mac;
1792 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1794 switch (hw->mac.ops.get_media_type(hw)) {
1795 case ixgbe_media_type_fiber:
1796 /* CS4227 does not support autoneg, so disable the laser control
1797 * functions for SFP+ fiber
1799 mac->ops.disable_tx_laser = NULL;
1800 mac->ops.enable_tx_laser = NULL;
1801 mac->ops.flap_tx_laser = NULL;
1802 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1803 mac->ops.set_rate_select_speed =
1804 ixgbe_set_soft_rate_select_speed;
1805 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1806 (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1807 mac->ops.setup_mac_link =
1808 ixgbe_setup_mac_link_sfp_x550a;
1810 mac->ops.setup_mac_link =
1811 ixgbe_setup_mac_link_sfp_x550em;
1813 case ixgbe_media_type_copper:
1814 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
1815 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
1816 mac->ops.setup_link = ixgbe_setup_sgmii_m88;
1817 mac->ops.check_link = ixgbe_check_link_m88;
1819 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1820 mac->ops.check_link = ixgbe_check_link_t_X550em;
1823 case ixgbe_media_type_backplane:
1824 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1825 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1826 mac->ops.setup_link = ixgbe_setup_sgmii;
1834 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1835 * @hw: pointer to hardware structure
1836 * @speed: pointer to link speed
1837 * @autoneg: true when autoneg or autotry is enabled
1839 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1840 ixgbe_link_speed *speed,
1843 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1846 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1848 /* CS4227 SFP must not enable auto-negotiation */
1851 /* Check if 1G SFP module. */
1852 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1853 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1854 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1855 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1856 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1857 return IXGBE_SUCCESS;
1860 /* Link capabilities are based on SFP */
1861 if (hw->phy.multispeed_fiber)
1862 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1863 IXGBE_LINK_SPEED_1GB_FULL;
1865 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1867 switch (hw->phy.type) {
1869 *speed = IXGBE_LINK_SPEED_1GB_FULL |
1870 IXGBE_LINK_SPEED_100_FULL |
1871 IXGBE_LINK_SPEED_10_FULL;
1873 case ixgbe_phy_sgmii:
1874 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1877 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1878 IXGBE_LINK_SPEED_1GB_FULL;
1884 return IXGBE_SUCCESS;
1888 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1889 * @hw: pointer to hardware structure
1890 * @lsc: pointer to boolean flag which indicates whether external Base T
1891 * PHY interrupt is lsc
1893 * Determime if external Base T PHY interrupt cause is high temperature
1894 * failure alarm or link status change.
1896 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1897 * failure alarm, else return PHY access status.
1899 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1906 /* Vendor alarm triggered */
1907 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1908 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1911 if (status != IXGBE_SUCCESS ||
1912 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1915 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1916 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1917 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1920 if (status != IXGBE_SUCCESS ||
1921 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1922 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1925 /* Global alarm triggered */
1926 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1927 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1930 if (status != IXGBE_SUCCESS)
1933 /* If high temperature failure, then return over temp error and exit */
1934 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1935 /* power down the PHY in case the PHY FW didn't already */
1936 ixgbe_set_copper_phy_power(hw, false);
1937 return IXGBE_ERR_OVERTEMP;
1938 } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1939 /* device fault alarm triggered */
1940 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1941 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1944 if (status != IXGBE_SUCCESS)
1947 /* if device fault was due to high temp alarm handle and exit */
1948 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1949 /* power down the PHY in case the PHY FW didn't */
1950 ixgbe_set_copper_phy_power(hw, false);
1951 return IXGBE_ERR_OVERTEMP;
1955 /* Vendor alarm 2 triggered */
1956 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1957 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1959 if (status != IXGBE_SUCCESS ||
1960 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1963 /* link connect/disconnect event occurred */
1964 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1965 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1967 if (status != IXGBE_SUCCESS)
1971 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1974 return IXGBE_SUCCESS;
1978 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1979 * @hw: pointer to hardware structure
1981 * Enable link status change and temperature failure alarm for the external
1984 * Returns PHY access status
1986 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1992 /* Clear interrupt flags */
1993 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1995 /* Enable link status change alarm */
1996 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1997 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1999 if (status != IXGBE_SUCCESS)
2002 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2004 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2005 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
2007 if (status != IXGBE_SUCCESS)
2010 /* Enable high temperature failure and global fault alarms */
2011 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2012 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2015 if (status != IXGBE_SUCCESS)
2018 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2019 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2021 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2022 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2025 if (status != IXGBE_SUCCESS)
2028 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2029 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2030 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2033 if (status != IXGBE_SUCCESS)
2036 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2037 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2039 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2040 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2043 if (status != IXGBE_SUCCESS)
2046 /* Enable chip-wide vendor alarm */
2047 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2048 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2051 if (status != IXGBE_SUCCESS)
2054 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2056 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2057 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2064 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2065 * @hw: pointer to hardware structure
2066 * @speed: link speed
2068 * Configures the integrated KR PHY.
2070 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2071 ixgbe_link_speed speed)
2076 status = hw->mac.ops.read_iosf_sb_reg(hw,
2077 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2078 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2082 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2083 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2084 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2086 /* Advertise 10G support. */
2087 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2088 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2090 /* Advertise 1G support. */
2091 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2092 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2094 /* Restart auto-negotiation. */
2095 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2096 status = hw->mac.ops.write_iosf_sb_reg(hw,
2097 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2098 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2104 * ixgbe_setup_m88 - setup m88 PHY
2105 * @hw: pointer to hardware structure
2107 STATIC s32 ixgbe_setup_m88(struct ixgbe_hw *hw)
2109 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2113 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2114 return IXGBE_SUCCESS;
2116 rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2120 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2123 if (reg & IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN) {
2124 reg &= ~IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN;
2125 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2129 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, ®);
2132 if (reg & IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN) {
2133 reg &= ~IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN;
2134 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0,
2138 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 2);
2142 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2146 if (reg & IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN) {
2147 reg &= ~IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN;
2148 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2150 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2154 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2158 reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2159 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2163 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2169 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2173 if (!(reg & IXGBE_M88E1500_COPPER_CTRL_AN_EN)) {
2174 reg |= IXGBE_M88E1500_COPPER_CTRL_AN_EN;
2175 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2179 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, ®);
2182 reg &= ~IXGBE_M88E1500_1000T_CTRL_HALF_DUPLEX;
2183 reg &= ~IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2184 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
2185 reg |= IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2186 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, reg);
2188 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, ®);
2191 reg &= ~IXGBE_M88E1500_COPPER_AN_T4;
2192 reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_FD;
2193 reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_HD;
2194 reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_FD;
2195 reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_HD;
2197 /* Flow control auto negotiation configuration was moved from here to
2198 * the function ixgbe_setup_fc_sgmii_x550em_a()
2201 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
2202 reg |= IXGBE_M88E1500_COPPER_AN_100TX_FD;
2203 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL)
2204 reg |= IXGBE_M88E1500_COPPER_AN_10TX_FD;
2205 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, reg);
2207 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2210 reg |= IXGBE_M88E1500_COPPER_CTRL_RESTART_AN;
2211 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2214 hw->mac.ops.release_swfw_sync(hw, mask);
2218 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2219 hw->mac.ops.release_swfw_sync(hw, mask);
2224 * ixgbe_reset_phy_m88e1500 - Reset m88e1500 PHY
2225 * @hw: pointer to hardware structure
2227 * The PHY token must be held when calling this function.
2229 static s32 ixgbe_reset_phy_m88e1500(struct ixgbe_hw *hw)
2234 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2238 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2242 reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2243 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2251 * ixgbe_reset_phy_m88e1543 - Reset m88e1543 PHY
2252 * @hw: pointer to hardware structure
2254 * The PHY token must be held when calling this function.
2256 static s32 ixgbe_reset_phy_m88e1543(struct ixgbe_hw *hw)
2258 return hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2262 * ixgbe_reset_phy_m88 - Reset m88 PHY
2263 * @hw: pointer to hardware structure
2265 STATIC s32 ixgbe_reset_phy_m88(struct ixgbe_hw *hw)
2267 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2271 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2272 return IXGBE_SUCCESS;
2274 rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2278 switch (hw->phy.id) {
2279 case IXGBE_M88E1500_E_PHY_ID:
2280 rc = ixgbe_reset_phy_m88e1500(hw);
2282 case IXGBE_M88E1543_E_PHY_ID:
2283 rc = ixgbe_reset_phy_m88e1543(hw);
2290 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2294 reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2295 IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2296 IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2297 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2301 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 18);
2305 reg = IXGBE_M88E1500_GEN_CTRL_RESET |
2306 IXGBE_M88E1500_GEN_CTRL_MODE_SGMII_COPPER;
2307 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_GEN_CTRL, 0, reg);
2311 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2315 reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2316 IXGBE_M88E1500_FIBER_CTRL_AN_EN |
2317 IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2318 IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2319 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2323 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2327 reg = (IXGBE_M88E1500_MAC_CTRL_1_DWN_4X <<
2328 IXGBE_M88E1500_MAC_CTRL_1_DWN_SHIFT) |
2329 (IXGBE_M88E1500_MAC_CTRL_1_ED_TM <<
2330 IXGBE_M88E1500_MAC_CTRL_1_ED_SHIFT) |
2331 (IXGBE_M88E1500_MAC_CTRL_1_MDIX_AUTO <<
2332 IXGBE_M88E1500_MAC_CTRL_1_MDIX_SHIFT);
2333 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, reg);
2337 reg = IXGBE_M88E1500_COPPER_CTRL_RESET |
2338 IXGBE_M88E1500_COPPER_CTRL_AN_EN |
2339 IXGBE_M88E1500_COPPER_CTRL_RESTART_AN |
2340 IXGBE_M88E1500_COPPER_CTRL_FULL_DUPLEX |
2341 IXGBE_M88E1500_COPPER_CTRL_SPEED_MSB;
2342 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2346 hw->mac.ops.release_swfw_sync(hw, mask);
2348 return ixgbe_setup_m88(hw);
2351 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2352 hw->mac.ops.release_swfw_sync(hw, mask);
2357 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2358 * @hw: pointer to hardware structure
2360 * Read NW_MNG_IF_SEL register and save field values, and check for valid field
2363 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2365 /* Save NW management interface connected on board. This is used
2366 * to determine internal PHY mode.
2368 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2370 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2371 * PHY address. This register field was has only been used for X552.
2373 if (hw->mac.type == ixgbe_mac_X550EM_a &&
2374 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2375 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2376 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2377 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2380 return IXGBE_SUCCESS;
2384 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2385 * @hw: pointer to hardware structure
2387 * Initialize any function pointers that were not able to be
2388 * set during init_shared_code because the PHY/SFP type was
2389 * not known. Perform the SFP init if necessary.
2391 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2393 struct ixgbe_phy_info *phy = &hw->phy;
2396 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2398 hw->mac.ops.set_lan_id(hw);
2400 ixgbe_read_mng_if_sel_x550em(hw);
2402 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2403 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2404 ixgbe_setup_mux_ctl(hw);
2405 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2408 switch (hw->device_id) {
2409 case IXGBE_DEV_ID_X550EM_A_1G_T:
2410 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2411 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2412 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2418 /* Identify the PHY or SFP module */
2419 ret_val = phy->ops.identify(hw);
2420 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
2423 /* Setup function pointers based on detected hardware */
2424 ixgbe_init_mac_link_ops_X550em(hw);
2425 if (phy->sfp_type != ixgbe_sfp_type_unknown)
2426 phy->ops.reset = NULL;
2428 /* Set functions pointers based on phy type */
2429 switch (hw->phy.type) {
2430 case ixgbe_phy_x550em_kx4:
2431 phy->ops.setup_link = NULL;
2432 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2433 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2435 case ixgbe_phy_x550em_kr:
2436 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2437 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2438 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2440 case ixgbe_phy_x550em_ext_t:
2441 /* If internal link mode is XFI, then setup iXFI internal link,
2442 * else setup KR now.
2444 phy->ops.setup_internal_link =
2445 ixgbe_setup_internal_phy_t_x550em;
2447 /* setup SW LPLU only for first revision of X550EM_x */
2448 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2449 !(IXGBE_FUSES0_REV_MASK &
2450 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2451 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2453 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2454 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2456 case ixgbe_phy_sgmii:
2457 phy->ops.setup_link = NULL;
2460 phy->ops.setup_link = ixgbe_setup_m88;
2461 phy->ops.reset = ixgbe_reset_phy_m88;
2470 * ixgbe_set_mdio_speed - Set MDIO clock speed
2471 * @hw: pointer to hardware structure
2473 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2477 switch (hw->device_id) {
2478 case IXGBE_DEV_ID_X550EM_X_10G_T:
2479 case IXGBE_DEV_ID_X550EM_A_SGMII:
2480 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2481 case IXGBE_DEV_ID_X550EM_A_1G_T:
2482 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2483 case IXGBE_DEV_ID_X550EM_A_10G_T:
2484 case IXGBE_DEV_ID_X550EM_A_SFP:
2485 case IXGBE_DEV_ID_X550EM_A_QSFP:
2486 /* Config MDIO clock speed before the first MDIO PHY access */
2487 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2488 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2489 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2497 * ixgbe_reset_hw_X550em - Perform hardware reset
2498 * @hw: pointer to hardware structure
2500 * Resets the hardware by resetting the transmit and receive units, masks
2501 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2504 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2506 ixgbe_link_speed link_speed;
2510 bool link_up = false;
2512 DEBUGFUNC("ixgbe_reset_hw_X550em");
2514 /* Call adapter stop to disable Tx/Rx and clear interrupts */
2515 status = hw->mac.ops.stop_adapter(hw);
2516 if (status != IXGBE_SUCCESS)
2519 /* flush pending Tx transactions */
2520 ixgbe_clear_tx_pending(hw);
2522 ixgbe_set_mdio_speed(hw);
2524 /* PHY ops must be identified and initialized prior to reset */
2525 status = hw->phy.ops.init(hw);
2527 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2530 /* start the external PHY */
2531 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2532 status = ixgbe_init_ext_t_x550em(hw);
2537 /* Setup SFP module if there is one present. */
2538 if (hw->phy.sfp_setup_needed) {
2539 status = hw->mac.ops.setup_sfp(hw);
2540 hw->phy.sfp_setup_needed = false;
2543 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2547 if (!hw->phy.reset_disable && hw->phy.ops.reset)
2548 hw->phy.ops.reset(hw);
2551 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
2552 * If link reset is used when link is up, it might reset the PHY when
2553 * mng is using it. If link is down or the flag to force full link
2554 * reset is set, then perform link reset.
2556 ctrl = IXGBE_CTRL_LNK_RST;
2557 if (!hw->force_full_reset) {
2558 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2560 ctrl = IXGBE_CTRL_RST;
2563 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2564 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2565 IXGBE_WRITE_FLUSH(hw);
2567 /* Poll for reset bit to self-clear meaning reset is complete */
2568 for (i = 0; i < 10; i++) {
2570 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2571 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2575 if (ctrl & IXGBE_CTRL_RST_MASK) {
2576 status = IXGBE_ERR_RESET_FAILED;
2577 DEBUGOUT("Reset polling failed to complete.\n");
2582 /* Double resets are required for recovery from certain error
2583 * conditions. Between resets, it is necessary to stall to
2584 * allow time for any pending HW events to complete.
2586 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2587 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2591 /* Store the permanent mac address */
2592 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2594 /* Store MAC address from RAR0, clear receive address registers, and
2595 * clear the multicast table. Also reset num_rar_entries to 128,
2596 * since we modify this value when programming the SAN MAC address.
2598 hw->mac.num_rar_entries = 128;
2599 hw->mac.ops.init_rx_addrs(hw);
2601 ixgbe_set_mdio_speed(hw);
2603 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2604 ixgbe_setup_mux_ctl(hw);
2610 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2611 * @hw: pointer to hardware structure
2613 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2618 status = hw->phy.ops.read_reg(hw,
2619 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2620 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2623 if (status != IXGBE_SUCCESS)
2626 /* If PHY FW reset completed bit is set then this is the first
2627 * SW instance after a power on so the PHY FW must be un-stalled.
2629 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2630 status = hw->phy.ops.read_reg(hw,
2631 IXGBE_MDIO_GLOBAL_RES_PR_10,
2632 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2635 if (status != IXGBE_SUCCESS)
2638 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2640 status = hw->phy.ops.write_reg(hw,
2641 IXGBE_MDIO_GLOBAL_RES_PR_10,
2642 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2645 if (status != IXGBE_SUCCESS)
2653 * ixgbe_setup_kr_x550em - Configure the KR PHY.
2654 * @hw: pointer to hardware structure
2656 * Configures the integrated KR PHY for X550EM_x.
2658 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2660 if (hw->mac.type != ixgbe_mac_X550EM_x)
2661 return IXGBE_SUCCESS;
2663 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2667 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2668 * @hw: pointer to hardware structure
2670 * Configure the external PHY and the integrated KR PHY for SFP support.
2672 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2673 ixgbe_link_speed speed,
2674 bool autoneg_wait_to_complete)
2677 u16 reg_slice, reg_val;
2678 bool setup_linear = false;
2679 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2681 /* Check if SFP module is supported and linear */
2682 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2684 /* If no SFP module present, then return success. Return success since
2685 * there is no reason to configure CS4227 and SFP not present error is
2686 * not excepted in the setup MAC link flow.
2688 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2689 return IXGBE_SUCCESS;
2691 if (ret_val != IXGBE_SUCCESS)
2694 /* Configure internal PHY for KR/KX. */
2695 ixgbe_setup_kr_speed_x550em(hw, speed);
2697 /* Configure CS4227 LINE side to proper mode. */
2698 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2699 (hw->bus.lan_id << 12);
2701 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2703 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2704 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2710 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2711 * @hw: pointer to hardware structure
2713 * Configure the the integrated PHY for SFP support.
2715 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2716 ixgbe_link_speed speed,
2717 bool autoneg_wait_to_complete)
2721 bool setup_linear = false;
2722 u32 reg_slice, reg_phy_int, slice_offset;
2724 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2726 /* Check if SFP module is supported and linear */
2727 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2729 /* If no SFP module present, then return success. Return success since
2730 * SFP not present error is not excepted in the setup MAC link flow.
2732 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2733 return IXGBE_SUCCESS;
2735 if (ret_val != IXGBE_SUCCESS)
2738 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2739 /* Configure internal PHY for native SFI */
2740 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2741 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2742 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int);
2744 if (ret_val != IXGBE_SUCCESS)
2748 reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LIMITING;
2749 reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LINEAR;
2751 reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LIMITING;
2752 reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LINEAR;
2755 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2756 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2757 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2759 if (ret_val != IXGBE_SUCCESS)
2762 /* Setup XFI/SFI internal link. */
2763 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2765 /* Configure internal PHY for KR/KX. */
2766 ixgbe_setup_kr_speed_x550em(hw, speed);
2768 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2770 DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2771 return IXGBE_ERR_PHY_ADDR_INVALID;
2774 /* Get external PHY device id */
2775 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_GLOBAL_ID_MSB,
2776 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
2778 if (ret_val != IXGBE_SUCCESS)
2781 /* When configuring quad port CS4223, the MAC instance is part
2782 * of the slice offset.
2784 if (reg_phy_ext == IXGBE_CS4223_PHY_ID)
2785 slice_offset = (hw->bus.lan_id +
2786 (hw->bus.instance_id << 1)) << 12;
2788 slice_offset = hw->bus.lan_id << 12;
2790 /* Configure CS4227/CS4223 LINE side to proper mode. */
2791 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2793 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2795 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2796 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2797 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2803 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2804 * @hw: pointer to hardware structure
2806 * iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2808 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2810 struct ixgbe_mac_info *mac = &hw->mac;
2814 /* Disable training protocol FSM. */
2815 status = mac->ops.read_iosf_sb_reg(hw,
2816 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2817 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2818 if (status != IXGBE_SUCCESS)
2820 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2821 status = mac->ops.write_iosf_sb_reg(hw,
2822 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2823 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2824 if (status != IXGBE_SUCCESS)
2827 /* Disable Flex from training TXFFE. */
2828 status = mac->ops.read_iosf_sb_reg(hw,
2829 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2830 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2831 if (status != IXGBE_SUCCESS)
2833 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2834 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2835 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2836 status = mac->ops.write_iosf_sb_reg(hw,
2837 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2838 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2839 if (status != IXGBE_SUCCESS)
2841 status = mac->ops.read_iosf_sb_reg(hw,
2842 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2843 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2844 if (status != IXGBE_SUCCESS)
2846 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2847 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2848 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2849 status = mac->ops.write_iosf_sb_reg(hw,
2850 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2851 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2852 if (status != IXGBE_SUCCESS)
2855 /* Enable override for coefficients. */
2856 status = mac->ops.read_iosf_sb_reg(hw,
2857 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2858 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2859 if (status != IXGBE_SUCCESS)
2861 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2862 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2863 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2864 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2865 status = mac->ops.write_iosf_sb_reg(hw,
2866 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2867 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2872 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2873 * @hw: pointer to hardware structure
2874 * @speed: the link speed to force
2876 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
2877 * internal and external PHY at a specific speed, without autonegotiation.
2879 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2881 struct ixgbe_mac_info *mac = &hw->mac;
2885 /* Disable AN and force speed to 10G Serial. */
2886 status = mac->ops.read_iosf_sb_reg(hw,
2887 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2888 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2889 if (status != IXGBE_SUCCESS)
2892 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2893 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2895 /* Select forced link speed for internal PHY. */
2897 case IXGBE_LINK_SPEED_10GB_FULL:
2898 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2900 case IXGBE_LINK_SPEED_1GB_FULL:
2901 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2904 /* Other link speeds are not supported by internal KR PHY. */
2905 return IXGBE_ERR_LINK_SETUP;
2908 status = mac->ops.write_iosf_sb_reg(hw,
2909 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2910 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2911 if (status != IXGBE_SUCCESS)
2914 /* Additional configuration needed for x550em_x */
2915 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2916 status = ixgbe_setup_ixfi_x550em_x(hw);
2917 if (status != IXGBE_SUCCESS)
2921 /* Toggle port SW reset by AN reset. */
2922 status = mac->ops.read_iosf_sb_reg(hw,
2923 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2924 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2925 if (status != IXGBE_SUCCESS)
2927 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2928 status = mac->ops.write_iosf_sb_reg(hw,
2929 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2930 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2936 * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2937 * @hw: address of hardware structure
2938 * @link_up: address of boolean to indicate link status
2940 * Returns error code if unable to get link status.
2942 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2949 /* read this twice back to back to indicate current status */
2950 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2951 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2953 if (ret != IXGBE_SUCCESS)
2956 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2957 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2959 if (ret != IXGBE_SUCCESS)
2962 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2964 return IXGBE_SUCCESS;
2968 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2969 * @hw: point to hardware structure
2971 * Configures the link between the integrated KR PHY and the external X557 PHY
2972 * The driver will call this function when it gets a link status change
2973 * interrupt from the X557 PHY. This function configures the link speed
2974 * between the PHYs to match the link speed of the BASE-T link.
2976 * A return of a non-zero value indicates an error, and the base driver should
2977 * not report link up.
2979 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2981 ixgbe_link_speed force_speed;
2986 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2987 return IXGBE_ERR_CONFIG;
2989 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2990 /* If link is down, there is no setup necessary so return */
2991 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2992 if (status != IXGBE_SUCCESS)
2996 return IXGBE_SUCCESS;
2998 status = hw->phy.ops.read_reg(hw,
2999 IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3000 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3002 if (status != IXGBE_SUCCESS)
3005 /* If link is still down - no setup is required so return */
3006 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3007 if (status != IXGBE_SUCCESS)
3010 return IXGBE_SUCCESS;
3012 /* clear everything but the speed and duplex bits */
3013 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
3016 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
3017 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3019 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
3020 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3023 /* Internal PHY does not support anything else */
3024 return IXGBE_ERR_INVALID_LINK_SETTINGS;
3027 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
3029 speed = IXGBE_LINK_SPEED_10GB_FULL |
3030 IXGBE_LINK_SPEED_1GB_FULL;
3031 return ixgbe_setup_kr_speed_x550em(hw, speed);
3036 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
3037 * @hw: pointer to hardware structure
3039 * Configures the integrated KR PHY to use internal loopback mode.
3041 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
3046 /* Disable AN and force speed to 10G Serial. */
3047 status = hw->mac.ops.read_iosf_sb_reg(hw,
3048 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3049 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3050 if (status != IXGBE_SUCCESS)
3052 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3053 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3054 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3055 status = hw->mac.ops.write_iosf_sb_reg(hw,
3056 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3057 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3058 if (status != IXGBE_SUCCESS)
3061 /* Set near-end loopback clocks. */
3062 status = hw->mac.ops.read_iosf_sb_reg(hw,
3063 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3064 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3065 if (status != IXGBE_SUCCESS)
3067 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3068 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3069 status = hw->mac.ops.write_iosf_sb_reg(hw,
3070 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3071 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3072 if (status != IXGBE_SUCCESS)
3075 /* Set loopback enable. */
3076 status = hw->mac.ops.read_iosf_sb_reg(hw,
3077 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3078 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3079 if (status != IXGBE_SUCCESS)
3081 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3082 status = hw->mac.ops.write_iosf_sb_reg(hw,
3083 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3084 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3085 if (status != IXGBE_SUCCESS)
3088 /* Training bypass. */
3089 status = hw->mac.ops.read_iosf_sb_reg(hw,
3090 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3091 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3092 if (status != IXGBE_SUCCESS)
3094 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3095 status = hw->mac.ops.write_iosf_sb_reg(hw,
3096 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3097 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3103 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3104 * assuming that the semaphore is already obtained.
3105 * @hw: pointer to hardware structure
3106 * @offset: offset of word in the EEPROM to read
3107 * @data: word read from the EEPROM
3109 * Reads a 16 bit word from the EEPROM using the hostif.
3111 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3115 struct ixgbe_hic_read_shadow_ram buffer;
3117 DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
3118 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3119 buffer.hdr.req.buf_lenh = 0;
3120 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3121 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3123 /* convert offset from words to bytes */
3124 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3126 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3128 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3130 IXGBE_HI_COMMAND_TIMEOUT, false);
3135 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3136 FW_NVM_DATA_OFFSET);
3142 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3143 * @hw: pointer to hardware structure
3144 * @offset: offset of word in the EEPROM to read
3145 * @data: word read from the EEPROM
3147 * Reads a 16 bit word from the EEPROM using the hostif.
3149 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3152 s32 status = IXGBE_SUCCESS;
3154 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3156 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3158 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
3159 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3161 status = IXGBE_ERR_SWFW_SYNC;
3168 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3169 * @hw: pointer to hardware structure
3170 * @offset: offset of word in the EEPROM to read
3171 * @words: number of words
3172 * @data: word(s) read from the EEPROM
3174 * Reads a 16 bit word(s) from the EEPROM using the hostif.
3176 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3177 u16 offset, u16 words, u16 *data)
3179 struct ixgbe_hic_read_shadow_ram buffer;
3180 u32 current_word = 0;
3185 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3187 /* Take semaphore for the entire operation. */
3188 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3190 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3194 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3195 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3197 words_to_read = words;
3199 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3200 buffer.hdr.req.buf_lenh = 0;
3201 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3202 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3204 /* convert offset from words to bytes */
3205 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3206 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3208 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3210 IXGBE_HI_COMMAND_TIMEOUT,
3214 DEBUGOUT("Host interface command failed\n");
3218 for (i = 0; i < words_to_read; i++) {
3219 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3221 u32 value = IXGBE_READ_REG(hw, reg);
3223 data[current_word] = (u16)(value & 0xffff);
3226 if (i < words_to_read) {
3228 data[current_word] = (u16)(value & 0xffff);
3232 words -= words_to_read;
3236 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3241 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3242 * @hw: pointer to hardware structure
3243 * @offset: offset of word in the EEPROM to write
3244 * @data: word write to the EEPROM
3246 * Write a 16 bit word to the EEPROM using the hostif.
3248 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3252 struct ixgbe_hic_write_shadow_ram buffer;
3254 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3256 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3257 buffer.hdr.req.buf_lenh = 0;
3258 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3259 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3262 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3264 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3266 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3268 IXGBE_HI_COMMAND_TIMEOUT, false);
3274 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3275 * @hw: pointer to hardware structure
3276 * @offset: offset of word in the EEPROM to write
3277 * @data: word write to the EEPROM
3279 * Write a 16 bit word to the EEPROM using the hostif.
3281 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3284 s32 status = IXGBE_SUCCESS;
3286 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3288 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3290 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3291 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3293 DEBUGOUT("write ee hostif failed to get semaphore");
3294 status = IXGBE_ERR_SWFW_SYNC;
3301 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3302 * @hw: pointer to hardware structure
3303 * @offset: offset of word in the EEPROM to write
3304 * @words: number of words
3305 * @data: word(s) write to the EEPROM
3307 * Write a 16 bit word(s) to the EEPROM using the hostif.
3309 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3310 u16 offset, u16 words, u16 *data)
3312 s32 status = IXGBE_SUCCESS;
3315 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3317 /* Take semaphore for the entire operation. */
3318 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3319 if (status != IXGBE_SUCCESS) {
3320 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3324 for (i = 0; i < words; i++) {
3325 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3328 if (status != IXGBE_SUCCESS) {
3329 DEBUGOUT("Eeprom buffered write failed\n");
3334 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3341 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3342 * @hw: pointer to hardware structure
3343 * @ptr: pointer offset in eeprom
3344 * @size: size of section pointed by ptr, if 0 first word will be used as size
3345 * @csum: address of checksum to update
3347 * Returns error status for any failure
3349 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3350 u16 size, u16 *csum, u16 *buffer,
3355 u16 length, bufsz, i, start;
3358 bufsz = sizeof(buf) / sizeof(buf[0]);
3360 /* Read a chunk at the pointer location */
3362 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3364 DEBUGOUT("Failed to read EEPROM image\n");
3369 if (buffer_size < ptr)
3370 return IXGBE_ERR_PARAM;
3371 local_buffer = &buffer[ptr];
3379 length = local_buffer[0];
3381 /* Skip pointer section if length is invalid. */
3382 if (length == 0xFFFF || length == 0 ||
3383 (ptr + length) >= hw->eeprom.word_size)
3384 return IXGBE_SUCCESS;
3387 if (buffer && ((u32)start + (u32)length > buffer_size))
3388 return IXGBE_ERR_PARAM;
3390 for (i = start; length; i++, length--) {
3391 if (i == bufsz && !buffer) {
3397 /* Read a chunk at the pointer location */
3398 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3401 DEBUGOUT("Failed to read EEPROM image\n");
3405 *csum += local_buffer[i];
3407 return IXGBE_SUCCESS;
3411 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3412 * @hw: pointer to hardware structure
3413 * @buffer: pointer to buffer containing calculated checksum
3414 * @buffer_size: size of buffer
3416 * Returns a negative error code on error, or the 16-bit checksum
3418 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3420 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3424 u16 pointer, i, size;
3426 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3428 hw->eeprom.ops.init_params(hw);
3431 /* Read pointer area */
3432 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3433 IXGBE_EEPROM_LAST_WORD + 1,
3436 DEBUGOUT("Failed to read EEPROM image\n");
3439 local_buffer = eeprom_ptrs;
3441 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3442 return IXGBE_ERR_PARAM;
3443 local_buffer = buffer;
3447 * For X550 hardware include 0x0-0x41 in the checksum, skip the
3448 * checksum word itself
3450 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3451 if (i != IXGBE_EEPROM_CHECKSUM)
3452 checksum += local_buffer[i];
3455 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
3456 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3458 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3459 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3462 pointer = local_buffer[i];
3464 /* Skip pointer section if the pointer is invalid. */
3465 if (pointer == 0xFFFF || pointer == 0 ||
3466 pointer >= hw->eeprom.word_size)
3470 case IXGBE_PCIE_GENERAL_PTR:
3471 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3473 case IXGBE_PCIE_CONFIG0_PTR:
3474 case IXGBE_PCIE_CONFIG1_PTR:
3475 size = IXGBE_PCIE_CONFIG_SIZE;
3482 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3483 buffer, buffer_size);
3488 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3490 return (s32)checksum;
3494 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3495 * @hw: pointer to hardware structure
3497 * Returns a negative error code on error, or the 16-bit checksum
3499 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3501 return ixgbe_calc_checksum_X550(hw, NULL, 0);
3505 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3506 * @hw: pointer to hardware structure
3507 * @checksum_val: calculated checksum
3509 * Performs checksum calculation and validates the EEPROM checksum. If the
3510 * caller does not need checksum_val, the value can be NULL.
3512 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3516 u16 read_checksum = 0;
3518 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3520 /* Read the first word from the EEPROM. If this times out or fails, do
3521 * not continue or we could be in for a very long wait while every
3524 status = hw->eeprom.ops.read(hw, 0, &checksum);
3526 DEBUGOUT("EEPROM read failed\n");
3530 status = hw->eeprom.ops.calc_checksum(hw);
3534 checksum = (u16)(status & 0xffff);
3536 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3541 /* Verify read checksum from EEPROM is the same as
3542 * calculated checksum
3544 if (read_checksum != checksum) {
3545 status = IXGBE_ERR_EEPROM_CHECKSUM;
3546 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3547 "Invalid EEPROM checksum");
3550 /* If the user cares, return the calculated checksum */
3552 *checksum_val = checksum;
3558 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3559 * @hw: pointer to hardware structure
3561 * After writing EEPROM to shadow RAM using EEWR register, software calculates
3562 * checksum and updates the EEPROM and instructs the hardware to update
3565 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3570 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3572 /* Read the first word from the EEPROM. If this times out or fails, do
3573 * not continue or we could be in for a very long wait while every
3576 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3578 DEBUGOUT("EEPROM read failed\n");
3582 status = ixgbe_calc_eeprom_checksum_X550(hw);
3586 checksum = (u16)(status & 0xffff);
3588 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3593 status = ixgbe_update_flash_X550(hw);
3599 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3600 * @hw: pointer to hardware structure
3602 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3604 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3606 s32 status = IXGBE_SUCCESS;
3607 union ixgbe_hic_hdr2 buffer;
3609 DEBUGFUNC("ixgbe_update_flash_X550");
3611 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3612 buffer.req.buf_lenh = 0;
3613 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3614 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3616 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3618 IXGBE_HI_COMMAND_TIMEOUT, false);
3624 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3625 * @hw: pointer to hardware structure
3627 * Determines physical layer capabilities of the current configuration.
3629 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3631 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3632 u16 ext_ability = 0;
3634 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3636 hw->phy.ops.identify(hw);
3638 switch (hw->phy.type) {
3639 case ixgbe_phy_x550em_kr:
3640 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3641 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3643 case ixgbe_phy_x550em_kx4:
3644 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3645 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3647 case ixgbe_phy_x550em_ext_t:
3648 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3649 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3651 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3652 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3653 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3654 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3660 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3661 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3663 return physical_layer;
3667 * ixgbe_get_bus_info_x550em - Set PCI bus info
3668 * @hw: pointer to hardware structure
3670 * Sets bus link width and speed to unknown because X550em is
3673 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3676 DEBUGFUNC("ixgbe_get_bus_info_x550em");
3678 hw->bus.width = ixgbe_bus_width_unknown;
3679 hw->bus.speed = ixgbe_bus_speed_unknown;
3681 hw->mac.ops.set_lan_id(hw);
3683 return IXGBE_SUCCESS;
3687 * ixgbe_disable_rx_x550 - Disable RX unit
3689 * Enables the Rx DMA unit for x550
3691 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3693 u32 rxctrl, pfdtxgswc;
3695 struct ixgbe_hic_disable_rxen fw_cmd;
3697 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3699 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3700 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3701 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3702 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3703 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3704 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3705 hw->mac.set_lben = true;
3707 hw->mac.set_lben = false;
3710 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3711 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3712 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3713 fw_cmd.port_number = (u8)hw->bus.lan_id;
3715 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3716 sizeof(struct ixgbe_hic_disable_rxen),
3717 IXGBE_HI_COMMAND_TIMEOUT, true);
3719 /* If we fail - disable RX using register write */
3721 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3722 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3723 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3724 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3731 * ixgbe_enter_lplu_x550em - Transition to low power states
3732 * @hw: pointer to hardware structure
3734 * Configures Low Power Link Up on transition to low power states
3735 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3736 * X557 PHY immediately prior to entering LPLU.
3738 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3740 u16 an_10g_cntl_reg, autoneg_reg, speed;
3742 ixgbe_link_speed lcd_speed;
3746 /* SW LPLU not required on later HW revisions. */
3747 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3748 (IXGBE_FUSES0_REV_MASK &
3749 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3750 return IXGBE_SUCCESS;
3752 /* If blocked by MNG FW, then don't restart AN */
3753 if (ixgbe_check_reset_blocked(hw))
3754 return IXGBE_SUCCESS;
3756 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3757 if (status != IXGBE_SUCCESS)
3760 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3762 if (status != IXGBE_SUCCESS)
3765 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3766 * disabled, then force link down by entering low power mode.
3768 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3769 !(hw->wol_enabled || ixgbe_mng_present(hw)))
3770 return ixgbe_set_copper_phy_power(hw, FALSE);
3773 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3775 if (status != IXGBE_SUCCESS)
3778 /* If no valid LCD link speed, then force link down and exit. */
3779 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3780 return ixgbe_set_copper_phy_power(hw, FALSE);
3782 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3783 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3786 if (status != IXGBE_SUCCESS)
3789 /* If no link now, speed is invalid so take link down */
3790 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3791 if (status != IXGBE_SUCCESS)
3792 return ixgbe_set_copper_phy_power(hw, false);
3794 /* clear everything but the speed bits */
3795 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3797 /* If current speed is already LCD, then exit. */
3798 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3799 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3800 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3801 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3804 /* Clear AN completed indication */
3805 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3806 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3809 if (status != IXGBE_SUCCESS)
3812 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3813 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3816 if (status != IXGBE_SUCCESS)
3819 status = hw->phy.ops.read_reg(hw,
3820 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3821 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3824 if (status != IXGBE_SUCCESS)
3827 save_autoneg = hw->phy.autoneg_advertised;
3829 /* Setup link at least common link speed */
3830 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3832 /* restore autoneg from before setting lplu speed */
3833 hw->phy.autoneg_advertised = save_autoneg;
3839 * ixgbe_get_lcd_x550em - Determine lowest common denominator
3840 * @hw: pointer to hardware structure
3841 * @lcd_speed: pointer to lowest common link speed
3843 * Determine lowest common link speed with link partner.
3845 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3849 u16 word = hw->eeprom.ctrl_word_3;
3851 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3853 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3854 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3857 if (status != IXGBE_SUCCESS)
3860 /* If link partner advertised 1G, return 1G */
3861 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3862 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3866 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3867 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3868 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3871 /* Link partner not capable of lower speeds, return 10G */
3872 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3877 * ixgbe_setup_fc_X550em - Set up flow control
3878 * @hw: pointer to hardware structure
3880 * Called at init time to set up flow control.
3882 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3884 s32 ret_val = IXGBE_SUCCESS;
3885 u32 pause, asm_dir, reg_val;
3887 DEBUGFUNC("ixgbe_setup_fc_X550em");
3889 /* Validate the requested mode */
3890 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3891 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3892 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3893 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3897 /* 10gig parts do not have a word in the EEPROM to determine the
3898 * default flow control setting, so we explicitly set it to full.
3900 if (hw->fc.requested_mode == ixgbe_fc_default)
3901 hw->fc.requested_mode = ixgbe_fc_full;
3903 /* Determine PAUSE and ASM_DIR bits. */
3904 switch (hw->fc.requested_mode) {
3909 case ixgbe_fc_tx_pause:
3913 case ixgbe_fc_rx_pause:
3914 /* Rx Flow control is enabled and Tx Flow control is
3915 * disabled by software override. Since there really
3916 * isn't a way to advertise that we are capable of RX
3917 * Pause ONLY, we will advertise that we support both
3918 * symmetric and asymmetric Rx PAUSE, as such we fall
3919 * through to the fc_full statement. Later, we will
3920 * disable the adapter's ability to send PAUSE frames.
3927 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3928 "Flow control param set incorrectly\n");
3929 ret_val = IXGBE_ERR_CONFIG;
3933 switch (hw->device_id) {
3934 case IXGBE_DEV_ID_X550EM_X_KR:
3935 case IXGBE_DEV_ID_X550EM_A_KR:
3936 case IXGBE_DEV_ID_X550EM_A_KR_L:
3937 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
3938 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3939 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3940 if (ret_val != IXGBE_SUCCESS)
3942 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3943 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3945 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3947 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3948 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
3949 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3950 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3952 /* This device does not fully support AN. */
3953 hw->fc.disable_fc_autoneg = true;
3964 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
3965 * @hw: pointer to hardware structure
3967 * Enable flow control according to IEEE clause 37.
3969 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
3971 u32 link_s1, lp_an_page_low, an_cntl_1;
3972 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
3973 ixgbe_link_speed speed;
3976 /* AN should have completed when the cable was plugged in.
3977 * Look for reasons to bail out. Bail out if:
3978 * - FC autoneg is disabled, or if
3981 if (hw->fc.disable_fc_autoneg) {
3982 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3983 "Flow control autoneg is disabled");
3987 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3989 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3993 /* Check at auto-negotiation has completed */
3994 status = hw->mac.ops.read_iosf_sb_reg(hw,
3995 IXGBE_KRM_LINK_S1(hw->bus.lan_id),
3996 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
3998 if (status != IXGBE_SUCCESS ||
3999 (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4000 DEBUGOUT("Auto-Negotiation did not complete\n");
4001 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4005 /* Read the 10g AN autoc and LP ability registers and resolve
4006 * local flow control settings accordingly
4008 status = hw->mac.ops.read_iosf_sb_reg(hw,
4009 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4010 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
4012 if (status != IXGBE_SUCCESS) {
4013 DEBUGOUT("Auto-Negotiation did not complete\n");
4017 status = hw->mac.ops.read_iosf_sb_reg(hw,
4018 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
4019 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
4021 if (status != IXGBE_SUCCESS) {
4022 DEBUGOUT("Auto-Negotiation did not complete\n");
4026 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
4027 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
4028 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
4029 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
4030 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
4033 if (status == IXGBE_SUCCESS) {
4034 hw->fc.fc_was_autonegged = true;
4036 hw->fc.fc_was_autonegged = false;
4037 hw->fc.current_mode = hw->fc.requested_mode;
4042 * ixgbe_fc_autoneg_fiber_x550em_a - Enable flow control IEEE clause 37
4043 * @hw: pointer to hardware structure
4045 * Enable flow control according to IEEE clause 37.
4047 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
4049 u32 link_s1, pcs_an_lp, pcs_an;
4050 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4051 ixgbe_link_speed speed;
4054 /* AN should have completed when the cable was plugged in.
4055 * Look for reasons to bail out. Bail out if:
4056 * - FC autoneg is disabled, or if
4059 if (hw->fc.disable_fc_autoneg) {
4060 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4061 "Flow control autoneg is disabled");
4065 hw->mac.ops.check_link(hw, &speed, &link_up, false);
4067 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4071 /* Check if auto-negotiation has completed */
4072 status = hw->mac.ops.read_iosf_sb_reg(hw,
4073 IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4074 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4076 if (status != IXGBE_SUCCESS ||
4077 (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4078 DEBUGOUT("Auto-Negotiation did not complete\n");
4079 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4083 /* Determine advertised flow control */
4084 status = hw->mac.ops.read_iosf_sb_reg(hw,
4085 IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id),
4086 IXGBE_SB_IOSF_TARGET_KR_PHY, &pcs_an);
4088 if (status != IXGBE_SUCCESS) {
4089 DEBUGOUT("Auto-Negotiation did not complete\n");
4093 /* Determine link parter flow control */
4094 status = hw->mac.ops.read_iosf_sb_reg(hw,
4095 IXGBE_KRM_PCS_KX_AN_LP(hw->bus.lan_id),
4096 IXGBE_SB_IOSF_TARGET_KR_PHY, &pcs_an_lp);
4098 if (status != IXGBE_SUCCESS) {
4099 DEBUGOUT("Auto-Negotiation did not complete\n");
4103 status = ixgbe_negotiate_fc(hw, pcs_an, pcs_an_lp,
4104 IXGBE_KRM_PCS_KX_AN_SYM_PAUSE,
4105 IXGBE_KRM_PCS_KX_AN_ASM_PAUSE,
4106 IXGBE_KRM_PCS_KX_AN_LP_SYM_PAUSE,
4107 IXGBE_KRM_PCS_KX_AN_LP_ASM_PAUSE);
4110 if (status == IXGBE_SUCCESS) {
4111 hw->fc.fc_was_autonegged = true;
4113 hw->fc.fc_was_autonegged = false;
4114 hw->fc.current_mode = hw->fc.requested_mode;
4119 * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
4120 * @hw: pointer to hardware structure
4122 * Enable flow control according to IEEE clause 37.
4124 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
4126 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4127 u16 reg, pcs_an_lp, pcs_an;
4128 ixgbe_link_speed speed;
4131 /* AN should have completed when the cable was plugged in.
4132 * Look for reasons to bail out. Bail out if:
4133 * - FC autoneg is disabled, or if
4136 if (hw->fc.disable_fc_autoneg) {
4137 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4138 "Flow control autoneg is disabled");
4142 hw->mac.ops.check_link(hw, &speed, &link_up, false);
4144 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4148 /* Check if auto-negotiation has completed */
4149 status = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_STATUS,
4150 IXGBE_MDIO_ZERO_DEV_TYPE, ®);
4151 if (status != IXGBE_SUCCESS ||
4152 (reg & IXGBE_M88E1500_COPPER_STATUS_AN_DONE) == 0) {
4153 DEBUGOUT("Auto-Negotiation did not complete\n");
4154 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4158 /* Get the advertized flow control */
4159 status = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_AN,
4160 IXGBE_MDIO_ZERO_DEV_TYPE, &pcs_an);
4161 if (status != IXGBE_SUCCESS)
4164 /* Get link partner's flow control */
4165 status = hw->phy.ops.read_reg(hw,
4166 IXGBE_M88E1500_COPPER_AN_LP_ABILITY,
4167 IXGBE_MDIO_ZERO_DEV_TYPE, &pcs_an_lp);
4168 if (status != IXGBE_SUCCESS)
4171 /* Negotiate the flow control */
4172 status = ixgbe_negotiate_fc(hw, (u32)pcs_an, (u32)pcs_an_lp,
4173 IXGBE_M88E1500_COPPER_AN_PAUSE,
4174 IXGBE_M88E1500_COPPER_AN_AS_PAUSE,
4175 IXGBE_M88E1500_COPPER_AN_LP_PAUSE,
4176 IXGBE_M88E1500_COPPER_AN_LP_AS_PAUSE);
4179 if (status == IXGBE_SUCCESS) {
4180 hw->fc.fc_was_autonegged = true;
4182 hw->fc.fc_was_autonegged = false;
4183 hw->fc.current_mode = hw->fc.requested_mode;
4188 * ixgbe_setup_fc_sgmii_x550em_a - Set up flow control
4189 * @hw: pointer to hardware structure
4191 * Called at init time to set up flow control.
4193 s32 ixgbe_setup_fc_sgmii_x550em_a(struct ixgbe_hw *hw)
4198 /* Validate the requested mode */
4199 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4200 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4201 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4202 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4205 if (hw->fc.requested_mode == ixgbe_fc_default)
4206 hw->fc.requested_mode = ixgbe_fc_full;
4208 /* Read contents of the Auto-Negotiation register, page 0 reg 4 */
4209 rc = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_AN,
4210 IXGBE_MDIO_ZERO_DEV_TYPE, ®);
4214 /* Disable all the settings related to Flow control Auto-negotiation */
4215 reg &= ~IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4216 reg &= ~IXGBE_M88E1500_COPPER_AN_PAUSE;
4218 /* Configure the Asymmetric and symmetric pause according to the user
4221 switch (hw->fc.requested_mode) {
4223 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
4224 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4226 case ixgbe_fc_rx_pause:
4227 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
4228 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4230 case ixgbe_fc_tx_pause:
4231 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4237 /* Write back to the Auto-Negotiation register with newly configured
4240 hw->phy.ops.write_reg(hw, IXGBE_M88E1500_COPPER_AN,
4241 IXGBE_MDIO_ZERO_DEV_TYPE, reg);
4243 /* In this section of the code we restart Auto-negotiation */
4245 /* Read the CONTROL register, Page 0 reg 0 */
4246 rc = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_CTRL,
4247 IXGBE_MDIO_ZERO_DEV_TYPE, ®);
4251 /* Set the bit to restart Auto-Neg. The bit to enable Auto-neg is ON
4254 reg |= IXGBE_M88E1500_COPPER_CTRL_RESTART_AN;
4256 /* write the new values to the register to restart Auto-Negotiation */
4257 hw->phy.ops.write_reg(hw, IXGBE_M88E1500_COPPER_CTRL,
4258 IXGBE_MDIO_ZERO_DEV_TYPE, reg);
4265 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4266 * @hw: pointer to hardware structure
4268 * Called at init time to set up flow control.
4270 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4272 s32 status = IXGBE_SUCCESS;
4273 u32 an_cntl, link_ctrl = 0;
4275 DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4277 /* Validate the requested mode */
4278 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4279 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4280 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4281 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4284 if (hw->fc.requested_mode == ixgbe_fc_default)
4285 hw->fc.requested_mode = ixgbe_fc_full;
4287 /* Set up the 1G and 10G flow control advertisement registers so the
4288 * HW will be able to do FC autoneg once the cable is plugged in. If
4289 * we link at 10G, the 1G advertisement is harmless and vice versa.
4291 status = hw->mac.ops.read_iosf_sb_reg(hw,
4292 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4293 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4295 if (status != IXGBE_SUCCESS) {
4296 DEBUGOUT("Auto-Negotiation did not complete\n");
4300 /* The possible values of fc.requested_mode are:
4301 * 0: Flow control is completely disabled
4302 * 1: Rx flow control is enabled (we can receive pause frames,
4303 * but not send pause frames).
4304 * 2: Tx flow control is enabled (we can send pause frames but
4305 * we do not support receiving pause frames).
4306 * 3: Both Rx and Tx flow control (symmetric) are enabled.
4309 switch (hw->fc.requested_mode) {
4311 /* Flow control completely disabled by software override. */
4312 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4313 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4315 case ixgbe_fc_tx_pause:
4316 /* Tx Flow control is enabled, and Rx Flow control is
4317 * disabled by software override.
4319 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4320 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4322 case ixgbe_fc_rx_pause:
4323 /* Rx Flow control is enabled and Tx Flow control is
4324 * disabled by software override. Since there really
4325 * isn't a way to advertise that we are capable of RX
4326 * Pause ONLY, we will advertise that we support both
4327 * symmetric and asymmetric Rx PAUSE, as such we fall
4328 * through to the fc_full statement. Later, we will
4329 * disable the adapter's ability to send PAUSE frames.
4332 /* Flow control (both Rx and Tx) is enabled by SW override. */
4333 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4334 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4337 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4338 "Flow control param set incorrectly\n");
4339 return IXGBE_ERR_CONFIG;
4342 status = hw->mac.ops.write_iosf_sb_reg(hw,
4343 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4344 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4346 /* Restart auto-negotiation. */
4347 status = hw->mac.ops.read_iosf_sb_reg(hw,
4348 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4349 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
4351 if (status != IXGBE_SUCCESS) {
4352 DEBUGOUT("Auto-Negotiation did not complete\n");
4356 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
4357 status = hw->mac.ops.write_iosf_sb_reg(hw,
4358 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4359 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
4365 * ixgbe_setup_fc_fiber_x550em_a - Set up flow control
4366 * @hw: pointer to hardware structure
4368 * Called at init time to set up flow control.
4370 s32 ixgbe_setup_fc_fiber_x550em_a(struct ixgbe_hw *hw)
4372 struct ixgbe_mac_info *mac = &hw->mac;
4373 s32 rc = IXGBE_SUCCESS;
4374 u32 an_cntl4, lctrl, pcs_an;
4376 DEBUGFUNC("ixgbe_setup_fc_fiber_x550em_a");
4378 /* Validate the requested mode */
4379 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4380 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4381 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4382 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4385 /* Enable clause 37 auto-negotiation in KRM_LINK_CTRL_1 */
4386 if (hw->fc.requested_mode == ixgbe_fc_default)
4387 hw->fc.requested_mode = ixgbe_fc_full;
4389 rc = mac->ops.read_iosf_sb_reg(hw,
4390 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4391 IXGBE_SB_IOSF_TARGET_KR_PHY, &lctrl);
4395 lctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
4396 lctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
4398 rc = mac->ops.write_iosf_sb_reg(hw,
4399 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4400 IXGBE_SB_IOSF_TARGET_KR_PHY, lctrl);
4404 /* Enable clause 37 over 73 in KRM_AN_CNTL_4 */
4405 rc = mac->ops.read_iosf_sb_reg(hw,
4406 IXGBE_KRM_AN_CNTL_4(hw->bus.lan_id),
4407 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl4);
4411 an_cntl4 |= IXGBE_KRM_AN_CNTL_4_ECSR_AN37_OVER_73;
4413 rc = mac->ops.write_iosf_sb_reg(hw,
4414 IXGBE_KRM_AN_CNTL_4(hw->bus.lan_id),
4415 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl4);
4419 rc = hw->mac.ops.read_iosf_sb_reg(hw,
4420 IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id),
4421 IXGBE_SB_IOSF_TARGET_KR_PHY, &pcs_an);
4426 /* The possible values of fc.requested_mode are:
4427 * 0: Flow control is completely disabled
4428 * 1: Rx flow control is enabled (we can receive pause frames,
4429 * but not send pause frames).
4430 * 2: Tx flow control is enabled (we can send pause frames but
4431 * we do not support receiving pause frames).
4432 * 3: Both Rx and Tx flow control (symmetric) are enabled.
4435 switch (hw->fc.requested_mode) {
4437 /* Flow control completely disabled by software override. */
4438 pcs_an &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4439 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4441 case ixgbe_fc_tx_pause:
4442 /* Tx Flow control is enabled, and Rx Flow control is
4443 * disabled by software override.
4445 pcs_an |= IXGBE_KRM_PCS_KX_AN_ASM_PAUSE;
4446 pcs_an &= ~IXGBE_KRM_PCS_KX_AN_SYM_PAUSE;
4448 case ixgbe_fc_rx_pause:
4449 /* Rx Flow control is enabled and Tx Flow control is
4450 * disabled by software override. Since there really
4451 * isn't a way to advertise that we are capable of RX
4452 * Pause ONLY, we will advertise that we support both
4453 * symmetric and asymmetric Rx PAUSE, as such we fall
4454 * through to the fc_full statement. Later, we will
4455 * disable the adapter's ability to send PAUSE frames.
4458 /* Flow control (both Rx and Tx) is enabled by SW override. */
4459 pcs_an |= IXGBE_KRM_PCS_KX_AN_SYM_PAUSE |
4460 IXGBE_KRM_PCS_KX_AN_ASM_PAUSE;
4463 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4464 "Flow control param set incorrectly\n");
4465 return IXGBE_ERR_CONFIG;
4468 rc = hw->mac.ops.write_iosf_sb_reg(hw,
4469 IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id),
4470 IXGBE_SB_IOSF_TARGET_KR_PHY, pcs_an);
4472 /* Restart auto-negotiation. */
4473 rc = hw->mac.ops.read_iosf_sb_reg(hw,
4474 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4475 IXGBE_SB_IOSF_TARGET_KR_PHY, &lctrl);
4478 DEBUGOUT("Auto-Negotiation did not complete\n");
4482 lctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
4483 rc = hw->mac.ops.write_iosf_sb_reg(hw,
4484 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4485 IXGBE_SB_IOSF_TARGET_KR_PHY, lctrl);
4491 * ixgbe_set_mux - Set mux for port 1 access with CS4227
4492 * @hw: pointer to hardware structure
4493 * @state: set mux if 1, clear if 0
4495 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4499 if (!hw->bus.lan_id)
4501 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4503 esdp |= IXGBE_ESDP_SDP1;
4505 esdp &= ~IXGBE_ESDP_SDP1;
4506 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4507 IXGBE_WRITE_FLUSH(hw);
4511 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4512 * @hw: pointer to hardware structure
4513 * @mask: Mask to specify which semaphore to acquire
4515 * Acquires the SWFW semaphore and sets the I2C MUX
4517 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4521 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4523 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4527 if (mask & IXGBE_GSSR_I2C_MASK)
4528 ixgbe_set_mux(hw, 1);
4530 return IXGBE_SUCCESS;
4534 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4535 * @hw: pointer to hardware structure
4536 * @mask: Mask to specify which semaphore to release
4538 * Releases the SWFW semaphore and sets the I2C MUX
4540 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4542 DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4544 if (mask & IXGBE_GSSR_I2C_MASK)
4545 ixgbe_set_mux(hw, 0);
4547 ixgbe_release_swfw_sync_X540(hw, mask);
4551 * ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4552 * @hw: pointer to hardware structure
4553 * @mask: Mask to specify which semaphore to acquire
4555 * Acquires the SWFW semaphore and get the shared phy token as needed
4557 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4559 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4560 int retries = FW_PHY_TOKEN_RETRIES;
4561 s32 status = IXGBE_SUCCESS;
4563 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4566 status = IXGBE_SUCCESS;
4568 status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4571 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4572 return IXGBE_SUCCESS;
4574 status = ixgbe_get_phy_token(hw);
4575 if (status == IXGBE_SUCCESS)
4576 return IXGBE_SUCCESS;
4579 ixgbe_release_swfw_sync_X540(hw, hmask);
4580 if (status != IXGBE_ERR_TOKEN_RETRY)
4582 msec_delay(FW_PHY_TOKEN_DELAY);
4589 * ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4590 * @hw: pointer to hardware structure
4591 * @mask: Mask to specify which semaphore to release
4593 * Releases the SWFW semaphore and puts the shared phy token as needed
4595 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4597 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4599 DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4601 if (mask & IXGBE_GSSR_TOKEN_SM)
4602 ixgbe_put_phy_token(hw);
4605 ixgbe_release_swfw_sync_X540(hw, hmask);
4609 * ixgbe_read_phy_reg_x550a - Reads specified PHY register
4610 * @hw: pointer to hardware structure
4611 * @reg_addr: 32 bit address of PHY register to read
4612 * @phy_data: Pointer to read data from PHY register
4614 * Reads a value from a specified PHY register using the SWFW lock and PHY
4615 * Token. The PHY Token is needed since the MDIO is shared between to MAC
4618 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4619 u32 device_type, u16 *phy_data)
4622 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4624 DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4626 if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4627 return IXGBE_ERR_SWFW_SYNC;
4629 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4631 hw->mac.ops.release_swfw_sync(hw, mask);
4637 * ixgbe_write_phy_reg_x550a - Writes specified PHY register
4638 * @hw: pointer to hardware structure
4639 * @reg_addr: 32 bit PHY register to write
4640 * @device_type: 5 bit device type
4641 * @phy_data: Data to write to the PHY register
4643 * Writes a value to specified PHY register using the SWFW lock and PHY Token.
4644 * The PHY Token is needed since the MDIO is shared between to MAC instances.
4646 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4647 u32 device_type, u16 phy_data)
4650 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4652 DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4654 if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4655 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
4657 hw->mac.ops.release_swfw_sync(hw, mask);
4659 status = IXGBE_ERR_SWFW_SYNC;
4666 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4667 * @hw: pointer to hardware structure
4669 * Handle external Base T PHY interrupt. If high temperature
4670 * failure alarm then return error, else if link status change
4671 * then setup internal/external PHY link
4673 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4674 * failure alarm, else return PHY access status.
4676 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4681 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4683 if (status != IXGBE_SUCCESS)
4687 return ixgbe_setup_internal_phy(hw);
4689 return IXGBE_SUCCESS;
4693 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4694 * @hw: pointer to hardware structure
4695 * @speed: new link speed
4696 * @autoneg_wait_to_complete: true when waiting for completion is needed
4698 * Setup internal/external PHY link speed based on link speed, then set
4699 * external PHY auto advertised link speed.
4701 * Returns error status for any failure
4703 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4704 ixgbe_link_speed speed,
4705 bool autoneg_wait_to_complete)
4708 ixgbe_link_speed force_speed;
4710 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4712 /* Setup internal/external PHY link speed to iXFI (10G), unless
4713 * only 1G is auto advertised then setup KX link.
4715 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4716 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4718 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4720 /* If internal link mode is XFI, then setup XFI internal link. */
4721 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4722 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4724 if (status != IXGBE_SUCCESS)
4728 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4732 * ixgbe_check_link_t_X550em - Determine link and speed status
4733 * @hw: pointer to hardware structure
4734 * @speed: pointer to link speed
4735 * @link_up: true when link is up
4736 * @link_up_wait_to_complete: bool used to wait for link up or not
4738 * Check that both the MAC and X557 external PHY have link.
4740 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4741 bool *link_up, bool link_up_wait_to_complete)
4746 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4747 return IXGBE_ERR_CONFIG;
4749 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4750 link_up_wait_to_complete);
4752 /* If check link fails or MAC link is not up, then return */
4753 if (status != IXGBE_SUCCESS || !(*link_up))
4756 /* MAC link is up, so check external PHY link.
4757 * Read this twice back to back to indicate current status.
4759 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4760 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4763 if (status != IXGBE_SUCCESS)
4766 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4767 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4770 if (status != IXGBE_SUCCESS)
4773 /* If external PHY link is not up, then indicate link not up */
4774 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4777 return IXGBE_SUCCESS;
4781 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4782 * @hw: pointer to hardware structure
4784 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4788 status = ixgbe_reset_phy_generic(hw);
4790 if (status != IXGBE_SUCCESS)
4793 /* Configure Link Status Alarm and Temperature Threshold interrupts */
4794 return ixgbe_enable_lasi_ext_t_x550em(hw);
4798 * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4799 * @hw: pointer to hardware structure
4800 * @led_idx: led number to turn on
4802 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4806 DEBUGFUNC("ixgbe_led_on_t_X550em");
4808 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4809 return IXGBE_ERR_PARAM;
4811 /* To turn on the LED, set mode to ON. */
4812 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4813 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4814 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4815 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4816 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4818 return IXGBE_SUCCESS;
4822 * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4823 * @hw: pointer to hardware structure
4824 * @led_idx: led number to turn off
4826 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4830 DEBUGFUNC("ixgbe_led_off_t_X550em");
4832 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4833 return IXGBE_ERR_PARAM;
4835 /* To turn on the LED, set mode to ON. */
4836 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4837 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4838 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4839 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4840 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4842 return IXGBE_SUCCESS;