drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  44 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw);
  45
  46 /**
  47  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  48  *  @hw: pointer to hardware structure
  49  *
  50  *  Initialize the function pointers and assign the MAC type for X550.
  51  *  Does not touch the hardware.
  52  **/
  53 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  54 {
  55         struct ixgbe_mac_info *mac = &hw->mac;
  56         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  57         s32 ret_val;
  58
  59         DEBUGFUNC("ixgbe_init_ops_X550");
  60
  61         ret_val = ixgbe_init_ops_X540(hw);
  62         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  63         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  64         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  65         mac->ops.setup_eee = NULL;
  66         mac->ops.set_source_address_pruning =
  67                         ixgbe_set_source_address_pruning_X550;
  68         mac->ops.set_ethertype_anti_spoofing =
  69                         ixgbe_set_ethertype_anti_spoofing_X550;
  70
  71         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  72         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  73         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  74         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  75         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  76         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  77         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  78         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  79         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  80
  81         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  82         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  83         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  84         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  85         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  86         /* Manageability interface */
  87         mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_x550;
  88         switch (hw->device_id) {
  89         case IXGBE_DEV_ID_X550EM_X_10G_T:
  90         case IXGBE_DEV_ID_X550EM_A_10G_T:
  91                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  92                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  93                 break;
  94         default:
  95                 break;
  96         }
  97         return ret_val;
  98 }
  99
 100 /**
 101  * ixgbe_read_cs4227 - Read CS4227 register
 102  * @hw: pointer to hardware structure
 103  * @reg: register number to write
 104  * @value: pointer to receive value read
 105  *
 106  * Returns status code
 107  **/
 108 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
 109 {
 110         return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
 111 }
 112
 113 /**
 114  * ixgbe_write_cs4227 - Write CS4227 register
 115  * @hw: pointer to hardware structure
 116  * @reg: register number to write
 117  * @value: value to write to register
 118  *
 119  * Returns status code
 120  **/
 121 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 122 {
 123         return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
 124 }
 125
 126 /**
 127  * ixgbe_read_pe - Read register from port expander
 128  * @hw: pointer to hardware structure
 129  * @reg: register number to read
 130  * @value: pointer to receive read value
 131  *
 132  * Returns status code
 133  **/
 134 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 135 {
 136         s32 status;
 137
 138         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 139         if (status != IXGBE_SUCCESS)
 140                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 141                               "port expander access failed with %d\n", status);
 142         return status;
 143 }
 144
 145 /**
 146  * ixgbe_write_pe - Write register to port expander
 147  * @hw: pointer to hardware structure
 148  * @reg: register number to write
 149  * @value: value to write
 150  *
 151  * Returns status code
 152  **/
 153 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 154 {
 155         s32 status;
 156
 157         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 158         if (status != IXGBE_SUCCESS)
 159                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 160                               "port expander access failed with %d\n", status);
 161         return status;
 162 }
 163
 164 /**
 165  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 166  * @hw: pointer to hardware structure
 167  *
 168  * This function assumes that the caller has acquired the proper semaphore.
 169  * Returns error code
 170  **/
 171 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 172 {
 173         s32 status;
 174         u32 retry;
 175         u16 value;
 176         u8 reg;
 177
 178         /* Trigger hard reset. */
 179         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 180         if (status != IXGBE_SUCCESS)
 181                 return status;
 182         reg |= IXGBE_PE_BIT1;
 183         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 184         if (status != IXGBE_SUCCESS)
 185                 return status;
 186
 187         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 188         if (status != IXGBE_SUCCESS)
 189                 return status;
 190         reg &= ~IXGBE_PE_BIT1;
 191         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 192         if (status != IXGBE_SUCCESS)
 193                 return status;
 194
 195         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 196         if (status != IXGBE_SUCCESS)
 197                 return status;
 198         reg &= ~IXGBE_PE_BIT1;
 199         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 200         if (status != IXGBE_SUCCESS)
 201                 return status;
 202
 203         usec_delay(IXGBE_CS4227_RESET_HOLD);
 204
 205         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 206         if (status != IXGBE_SUCCESS)
 207                 return status;
 208         reg |= IXGBE_PE_BIT1;
 209         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 210         if (status != IXGBE_SUCCESS)
 211                 return status;
 212
 213         /* Wait for the reset to complete. */
 214         msec_delay(IXGBE_CS4227_RESET_DELAY);
 215         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 216                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 217                                            &value);
 218                 if (status == IXGBE_SUCCESS &&
 219                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 220                         break;
 221                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 222         }
 223         if (retry == IXGBE_CS4227_RETRIES) {
 224                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 225                         "CS4227 reset did not complete.");
 226                 return IXGBE_ERR_PHY;
 227         }
 228
 229         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 230         if (status != IXGBE_SUCCESS ||
 231             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 232                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 233                         "CS4227 EEPROM did not load successfully.");
 234                 return IXGBE_ERR_PHY;
 235         }
 236
 237         return IXGBE_SUCCESS;
 238 }
 239
 240 /**
 241  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 242  * @hw: pointer to hardware structure
 243  **/
 244 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 245 {
 246         s32 status = IXGBE_SUCCESS;
 247         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 248         u16 value = 0;
 249         u8 retry;
 250
 251         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 252                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 253                 if (status != IXGBE_SUCCESS) {
 254                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 255                                 "semaphore failed with %d", status);
 256                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 257                         continue;
 258                 }
 259
 260                 /* Get status of reset flow. */
 261                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 262
 263                 if (status == IXGBE_SUCCESS &&
 264                     value == IXGBE_CS4227_RESET_COMPLETE)
 265                         goto out;
 266
 267                 if (status != IXGBE_SUCCESS ||
 268                     value != IXGBE_CS4227_RESET_PENDING)
 269                         break;
 270
 271                 /* Reset is pending. Wait and check again. */
 272                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 273                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 274         }
 275
 276         /* If still pending, assume other instance failed. */
 277         if (retry == IXGBE_CS4227_RETRIES) {
 278                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 279                 if (status != IXGBE_SUCCESS) {
 280                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 281                                       "semaphore failed with %d", status);
 282                         return;
 283                 }
 284         }
 285
 286         /* Reset the CS4227. */
 287         status = ixgbe_reset_cs4227(hw);
 288         if (status != IXGBE_SUCCESS) {
 289                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 290                         "CS4227 reset failed: %d", status);
 291                 goto out;
 292         }
 293
 294         /* Reset takes so long, temporarily release semaphore in case the
 295          * other driver instance is waiting for the reset indication.
 296          */
 297         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 298                            IXGBE_CS4227_RESET_PENDING);
 299         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 300         msec_delay(10);
 301         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 302         if (status != IXGBE_SUCCESS) {
 303                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 304                         "semaphore failed with %d", status);
 305                 return;
 306         }
 307
 308         /* Record completion for next time. */
 309         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 310                 IXGBE_CS4227_RESET_COMPLETE);
 311
 312 out:
 313         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 314         msec_delay(hw->eeprom.semaphore_delay);
 315 }
 316
 317 /**
 318  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 319  * @hw: pointer to hardware structure
 320  **/
 321 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 322 {
 323         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 324
 325         if (hw->bus.lan_id) {
 326                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 327                 esdp |= IXGBE_ESDP_SDP1_DIR;
 328         }
 329         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 330         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 331         IXGBE_WRITE_FLUSH(hw);
 332 }
 333
 334 /**
 335  * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
 336  * @hw: pointer to hardware structure
 337  * @reg_addr: 32 bit address of PHY register to read
 338  * @dev_type: always unused
 339  * @phy_data: Pointer to read data from PHY register
 340  */
 341 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 342                                      u32 dev_type, u16 *phy_data)
 343 {
 344         u32 i, data, command;
 345         UNREFERENCED_1PARAMETER(dev_type);
 346
 347         /* Setup and write the read command */
 348         command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 349                   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 350                   IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
 351                   IXGBE_MSCA_MDI_COMMAND;
 352
 353         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 354
 355         /* Check every 10 usec to see if the access completed.
 356          * The MDI Command bit will clear when the operation is
 357          * complete
 358          */
 359         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 360                 usec_delay(10);
 361
 362                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 363                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 364                         break;
 365         }
 366
 367         if (command & IXGBE_MSCA_MDI_COMMAND) {
 368                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 369                               "PHY read command did not complete.\n");
 370                 return IXGBE_ERR_PHY;
 371         }
 372
 373         /* Read operation is complete.  Get the data from MSRWD */
 374         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 375         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 376         *phy_data = (u16)data;
 377
 378         return IXGBE_SUCCESS;
 379 }
 380
 381 /**
 382  * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
 383  * @hw: pointer to hardware structure
 384  * @reg_addr: 32 bit PHY register to write
 385  * @dev_type: always unused
 386  * @phy_data: Data to write to the PHY register
 387  */
 388 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 389                                       u32 dev_type, u16 phy_data)
 390 {
 391         u32 i, command;
 392         UNREFERENCED_1PARAMETER(dev_type);
 393
 394         /* Put the data in the MDI single read and write data register*/
 395         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 396
 397         /* Setup and write the write command */
 398         command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 399                   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 400                   IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
 401                   IXGBE_MSCA_MDI_COMMAND;
 402
 403         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 404
 405         /* Check every 10 usec to see if the access completed.
 406          * The MDI Command bit will clear when the operation is
 407          * complete
 408          */
 409         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 410                 usec_delay(10);
 411
 412                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 413                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 414                         break;
 415         }
 416
 417         if (command & IXGBE_MSCA_MDI_COMMAND) {
 418                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 419                               "PHY write cmd didn't complete\n");
 420                 return IXGBE_ERR_PHY;
 421         }
 422
 423         return IXGBE_SUCCESS;
 424 }
 425
 426 /**
 427  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 428  * @hw: pointer to hardware structure
 429  *
 430  * Returns error code
 431  */
 432 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 433 {
 434         hw->mac.ops.set_lan_id(hw);
 435
 436         ixgbe_read_mng_if_sel_x550em(hw);
 437
 438         switch (hw->device_id) {
 439         case IXGBE_DEV_ID_X550EM_A_SFP:
 440                 return ixgbe_identify_module_generic(hw);
 441         case IXGBE_DEV_ID_X550EM_X_SFP:
 442                 /* set up for CS4227 usage */
 443                 ixgbe_setup_mux_ctl(hw);
 444                 ixgbe_check_cs4227(hw);
 445                 /* Fallthrough */
 446
 447         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 448                 return ixgbe_identify_module_generic(hw);
 449                 break;
 450         case IXGBE_DEV_ID_X550EM_X_KX4:
 451                 hw->phy.type = ixgbe_phy_x550em_kx4;
 452                 break;
 453         case IXGBE_DEV_ID_X550EM_X_XFI:
 454                 hw->phy.type = ixgbe_phy_x550em_xfi;
 455                 break;
 456         case IXGBE_DEV_ID_X550EM_X_KR:
 457         case IXGBE_DEV_ID_X550EM_A_KR:
 458         case IXGBE_DEV_ID_X550EM_A_KR_L:
 459                 hw->phy.type = ixgbe_phy_x550em_kr;
 460                 break;
 461         case IXGBE_DEV_ID_X550EM_A_10G_T:
 462         case IXGBE_DEV_ID_X550EM_X_1G_T:
 463         case IXGBE_DEV_ID_X550EM_X_10G_T:
 464                 return ixgbe_identify_phy_generic(hw);
 465         case IXGBE_DEV_ID_X550EM_A_1G_T:
 466         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 467                 hw->phy.type = ixgbe_phy_fw;
 468                 hw->phy.ops.read_reg = NULL;
 469                 hw->phy.ops.write_reg = NULL;
 470                 if (hw->bus.lan_id)
 471                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 472                 else
 473                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 474                 break;
 475         default:
 476                 break;
 477         }
 478         return IXGBE_SUCCESS;
 479 }
 480
 481 /**
 482  * ixgbe_fw_phy_activity - Perform an activity on a PHY
 483  * @hw: pointer to hardware structure
 484  * @activity: activity to perform
 485  * @data: Pointer to 4 32-bit words of data
 486  */
 487 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,
 488                           u32 (*data)[FW_PHY_ACT_DATA_COUNT])
 489 {
 490         union {
 491                 struct ixgbe_hic_phy_activity_req cmd;
 492                 struct ixgbe_hic_phy_activity_resp rsp;
 493         } hic;
 494         u16 retries = FW_PHY_ACT_RETRIES;
 495         s32 rc;
 496         u16 i;
 497
 498         do {
 499                 memset(&hic, 0, sizeof(hic));
 500                 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD;
 501                 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN;
 502                 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 503                 hic.cmd.port_number = hw->bus.lan_id;
 504                 hic.cmd.activity_id = IXGBE_CPU_TO_LE16(activity);
 505                 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
 506                         hic.cmd.data[i] = IXGBE_CPU_TO_BE32((*data)[i]);
 507
 508                 rc = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
 509                                                   sizeof(hic.cmd),
 510                                                   IXGBE_HI_COMMAND_TIMEOUT,
 511                                                   true);
 512                 if (rc != IXGBE_SUCCESS)
 513                         return rc;
 514                 if (hic.rsp.hdr.cmd_or_resp.ret_status ==
 515                     FW_CEM_RESP_STATUS_SUCCESS) {
 516                         for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
 517                                 (*data)[i] = IXGBE_BE32_TO_CPU(hic.rsp.data[i]);
 518                         return IXGBE_SUCCESS;
 519                 }
 520                 usec_delay(20);
 521                 --retries;
 522         } while (retries > 0);
 523
 524         return IXGBE_ERR_HOST_INTERFACE_COMMAND;
 525 }
 526
 527 static const struct {
 528         u16 fw_speed;
 529         ixgbe_link_speed phy_speed;
 530 } ixgbe_fw_map[] = {
 531         { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL },
 532         { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL },
 533         { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL },
 534         { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL },
 535         { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL },
 536         { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL },
 537 };
 538
 539 /**
 540  * ixgbe_get_phy_id_fw - Get the phy ID via firmware command
 541  * @hw: pointer to hardware structure
 542  *
 543  * Returns error code
 544  */
 545 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw)
 546 {
 547         u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
 548         u16 phy_speeds;
 549         u16 phy_id_lo;
 550         s32 rc;
 551         u16 i;
 552
 553         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info);
 554         if (rc)
 555                 return rc;
 556
 557         hw->phy.speeds_supported = 0;
 558         phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK;
 559         for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
 560                 if (phy_speeds & ixgbe_fw_map[i].fw_speed)
 561                         hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed;
 562         }
 563         if (!hw->phy.autoneg_advertised)
 564                 hw->phy.autoneg_advertised = hw->phy.speeds_supported;
 565
 566         hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK;
 567         phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK;
 568         hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK;
 569         hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK;
 570         if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK)
 571                 return IXGBE_ERR_PHY_ADDR_INVALID;
 572         return IXGBE_SUCCESS;
 573 }
 574
 575 /**
 576  * ixgbe_identify_phy_fw - Get PHY type based on firmware command
 577  * @hw: pointer to hardware structure
 578  *
 579  * Returns error code
 580  */
 581 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw)
 582 {
 583         if (hw->bus.lan_id)
 584                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 585         else
 586                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 587
 588         hw->phy.type = ixgbe_phy_fw;
 589         hw->phy.ops.read_reg = NULL;
 590         hw->phy.ops.write_reg = NULL;
 591         return ixgbe_get_phy_id_fw(hw);
 592 }
 593
 594 /**
 595  * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY
 596  * @hw: pointer to hardware structure
 597  *
 598  * Returns error code
 599  */
 600 s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw)
 601 {
 602         u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
 603
 604         setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF;
 605         return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup);
 606 }
 607
 608 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 609                                      u32 device_type, u16 *phy_data)
 610 {
 611         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 612         return IXGBE_NOT_IMPLEMENTED;
 613 }
 614
 615 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 616                                       u32 device_type, u16 phy_data)
 617 {
 618         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 619         return IXGBE_NOT_IMPLEMENTED;
 620 }
 621
 622 /**
 623  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 624  * @hw: pointer to the hardware structure
 625  * @addr: I2C bus address to read from
 626  * @reg: I2C device register to read from
 627  * @val: pointer to location to receive read value
 628  *
 629  * Returns an error code on error.
 630  **/
 631 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 632                                            u16 reg, u16 *val)
 633 {
 634         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 635 }
 636
 637 /**
 638  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 639  * @hw: pointer to the hardware structure
 640  * @addr: I2C bus address to read from
 641  * @reg: I2C device register to read from
 642  * @val: pointer to location to receive read value
 643  *
 644  * Returns an error code on error.
 645  **/
 646 STATIC s32
 647 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 648                                          u16 reg, u16 *val)
 649 {
 650         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 651 }
 652
 653 /**
 654  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 655  * @hw: pointer to the hardware structure
 656  * @addr: I2C bus address to write to
 657  * @reg: I2C device register to write to
 658  * @val: value to write
 659  *
 660  * Returns an error code on error.
 661  **/
 662 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 663                                             u8 addr, u16 reg, u16 val)
 664 {
 665         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 666 }
 667
 668 /**
 669  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 670  * @hw: pointer to the hardware structure
 671  * @addr: I2C bus address to write to
 672  * @reg: I2C device register to write to
 673  * @val: value to write
 674  *
 675  * Returns an error code on error.
 676  **/
 677 STATIC s32
 678 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 679                                           u8 addr, u16 reg, u16 val)
 680 {
 681         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 682 }
 683
 684 /**
 685 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 686 *  @hw: pointer to hardware structure
 687 *
 688 *  Initialize the function pointers and for MAC type X550EM.
 689 *  Does not touch the hardware.
 690 **/
 691 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 692 {
 693         struct ixgbe_mac_info *mac = &hw->mac;
 694         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 695         struct ixgbe_phy_info *phy = &hw->phy;
 696         s32 ret_val;
 697
 698         DEBUGFUNC("ixgbe_init_ops_X550EM");
 699
 700         /* Similar to X550 so start there. */
 701         ret_val = ixgbe_init_ops_X550(hw);
 702
 703         /* Since this function eventually calls
 704          * ixgbe_init_ops_540 by design, we are setting
 705          * the pointers to NULL explicitly here to overwrite
 706          * the values being set in the x540 function.
 707          */
 708         /* Thermal sensor not supported in x550EM */
 709         mac->ops.get_thermal_sensor_data = NULL;
 710         mac->ops.init_thermal_sensor_thresh = NULL;
 711         mac->thermal_sensor_enabled = false;
 712
 713         /* FCOE not supported in x550EM */
 714         mac->ops.get_san_mac_addr = NULL;
 715         mac->ops.set_san_mac_addr = NULL;
 716         mac->ops.get_wwn_prefix = NULL;
 717         mac->ops.get_fcoe_boot_status = NULL;
 718
 719         /* IPsec not supported in x550EM */
 720         mac->ops.disable_sec_rx_path = NULL;
 721         mac->ops.enable_sec_rx_path = NULL;
 722
 723         /* AUTOC register is not present in x550EM. */
 724         mac->ops.prot_autoc_read = NULL;
 725         mac->ops.prot_autoc_write = NULL;
 726
 727         /* X550EM bus type is internal*/
 728         hw->bus.type = ixgbe_bus_type_internal;
 729         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 730
 731
 732         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 733         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 734         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 735         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 736         mac->ops.get_supported_physical_layer =
 737                                     ixgbe_get_supported_physical_layer_X550em;
 738
 739         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 740                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 741         else
 742                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 743
 744         /* PHY */
 745         phy->ops.init = ixgbe_init_phy_ops_X550em;
 746         switch (hw->device_id) {
 747         case IXGBE_DEV_ID_X550EM_A_1G_T:
 748         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 749                 mac->ops.setup_fc = NULL;
 750                 phy->ops.identify = ixgbe_identify_phy_fw;
 751                 phy->ops.set_phy_power = NULL;
 752                 phy->ops.get_firmware_version = NULL;
 753                 break;
 754         default:
 755                 phy->ops.identify = ixgbe_identify_phy_x550em;
 756         }
 757
 758         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 759                 phy->ops.set_phy_power = NULL;
 760
 761
 762         /* EEPROM */
 763         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 764         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 765         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 766         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 767         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 768         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 769         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 770         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 771
 772         return ret_val;
 773 }
 774
 775 /**
 776  * ixgbe_setup_fw_link - Setup firmware-controlled PHYs
 777  * @hw: pointer to hardware structure
 778  */
 779 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw)
 780 {
 781         u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
 782         s32 rc;
 783         u16 i;
 784
 785         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
 786                 return 0;
 787
 788         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
 789                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
 790                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
 791                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
 792         }
 793
 794         switch (hw->fc.requested_mode) {
 795         case ixgbe_fc_full:
 796                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX <<
 797                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 798                 break;
 799         case ixgbe_fc_rx_pause:
 800                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX <<
 801                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 802                 break;
 803         case ixgbe_fc_tx_pause:
 804                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX <<
 805                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 806                 break;
 807         default:
 808                 break;
 809         }
 810
 811         for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
 812                 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)
 813                         setup[0] |= ixgbe_fw_map[i].fw_speed;
 814         }
 815         setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN;
 816
 817         if (hw->phy.eee_speeds_advertised)
 818                 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE;
 819
 820         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup);
 821         if (rc)
 822                 return rc;
 823         if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN)
 824                 return IXGBE_ERR_OVERTEMP;
 825         return IXGBE_SUCCESS;
 826 }
 827
 828 /**
 829  * ixgbe_fc_autoneg_fw _ Set up flow control for FW-controlled PHYs
 830  * @hw: pointer to hardware structure
 831  *
 832  *  Called at init time to set up flow control.
 833  */
 834 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw)
 835 {
 836         if (hw->fc.requested_mode == ixgbe_fc_default)
 837                 hw->fc.requested_mode = ixgbe_fc_full;
 838
 839         return ixgbe_setup_fw_link(hw);
 840 }
 841
 842 /**
 843  * ixgbe_setup_eee_fw - Enable/disable EEE support
 844  * @hw: pointer to the HW structure
 845  * @enable_eee: boolean flag to enable EEE
 846  *
 847  * Enable/disable EEE based on enable_eee flag.
 848  * This function controls EEE for firmware-based PHY implementations.
 849  */
 850 static s32 ixgbe_setup_eee_fw(struct ixgbe_hw *hw, bool enable_eee)
 851 {
 852         if (!!hw->phy.eee_speeds_advertised == enable_eee)
 853                 return IXGBE_SUCCESS;
 854         if (enable_eee)
 855                 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
 856         else
 857                 hw->phy.eee_speeds_advertised = 0;
 858         return hw->phy.ops.setup_link(hw);
 859 }
 860
 861 /**
 862 *  ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
 863 *  @hw: pointer to hardware structure
 864 *
 865 *  Initialize the function pointers and for MAC type X550EM_a.
 866 *  Does not touch the hardware.
 867 **/
 868 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
 869 {
 870         struct ixgbe_mac_info *mac = &hw->mac;
 871         s32 ret_val;
 872
 873         DEBUGFUNC("ixgbe_init_ops_X550EM_a");
 874
 875         /* Start with generic X550EM init */
 876         ret_val = ixgbe_init_ops_X550EM(hw);
 877
 878         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
 879             hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) {
 880                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 881                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 882         } else {
 883                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
 884                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
 885         }
 886         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
 887         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
 888
 889         switch (mac->ops.get_media_type(hw)) {
 890         case ixgbe_media_type_fiber:
 891                 mac->ops.setup_fc = NULL;
 892                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
 893                 break;
 894         case ixgbe_media_type_backplane:
 895                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
 896                 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
 897                 break;
 898         default:
 899                 break;
 900         }
 901
 902         switch (hw->device_id) {
 903         case IXGBE_DEV_ID_X550EM_A_1G_T:
 904         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 905                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
 906                 mac->ops.setup_fc = ixgbe_fc_autoneg_fw;
 907                 mac->ops.setup_eee = ixgbe_setup_eee_fw;
 908                 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL |
 909                                                IXGBE_LINK_SPEED_1GB_FULL;
 910                 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
 911                 break;
 912         default:
 913                 break;
 914         }
 915
 916         return ret_val;
 917 }
 918
 919 /**
 920 *  ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
 921 *  @hw: pointer to hardware structure
 922 *
 923 *  Initialize the function pointers and for MAC type X550EM_x.
 924 *  Does not touch the hardware.
 925 **/
 926 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
 927 {
 928         struct ixgbe_mac_info *mac = &hw->mac;
 929         struct ixgbe_link_info *link = &hw->link;
 930         s32 ret_val;
 931
 932         DEBUGFUNC("ixgbe_init_ops_X550EM_x");
 933
 934         /* Start with generic X550EM init */
 935         ret_val = ixgbe_init_ops_X550EM(hw);
 936
 937         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 938         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 939         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 940         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 941         link->ops.read_link = ixgbe_read_i2c_combined_generic;
 942         link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
 943         link->ops.write_link = ixgbe_write_i2c_combined_generic;
 944         link->ops.write_link_unlocked =
 945                                       ixgbe_write_i2c_combined_generic_unlocked;
 946         link->addr = IXGBE_CS4227;
 947
 948
 949         return ret_val;
 950 }
 951
 952 /**
 953  *  ixgbe_dmac_config_X550
 954  *  @hw: pointer to hardware structure
 955  *
 956  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 957  *  When disabling dmac, dmac enable dmac bit is cleared.
 958  **/
 959 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 960 {
 961         u32 reg, high_pri_tc;
 962
 963         DEBUGFUNC("ixgbe_dmac_config_X550");
 964
 965         /* Disable DMA coalescing before configuring */
 966         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 967         reg &= ~IXGBE_DMACR_DMAC_EN;
 968         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 969
 970         /* Disable DMA Coalescing if the watchdog timer is 0 */
 971         if (!hw->mac.dmac_config.watchdog_timer)
 972                 goto out;
 973
 974         ixgbe_dmac_config_tcs_X550(hw);
 975
 976         /* Configure DMA Coalescing Control Register */
 977         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 978
 979         /* Set the watchdog timer in units of 40.96 usec */
 980         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 981         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 982
 983         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 984         /* If fcoe is enabled, set high priority traffic class */
 985         if (hw->mac.dmac_config.fcoe_en) {
 986                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 987                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 988                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 989         }
 990         reg |= IXGBE_DMACR_EN_MNG_IND;
 991
 992         /* Enable DMA coalescing after configuration */
 993         reg |= IXGBE_DMACR_DMAC_EN;
 994         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 995
 996 out:
 997         return IXGBE_SUCCESS;
 998 }
 999
1000 /**
1001  *  ixgbe_dmac_config_tcs_X550
1002  *  @hw: pointer to hardware structure
1003  *
1004  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
1005  *  be cleared before configuring.
1006  **/
1007 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
1008 {
1009         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
1010
1011         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
1012
1013         /* Configure DMA coalescing enabled */
1014         switch (hw->mac.dmac_config.link_speed) {
1015         case IXGBE_LINK_SPEED_10_FULL:
1016         case IXGBE_LINK_SPEED_100_FULL:
1017                 pb_headroom = IXGBE_DMACRXT_100M;
1018                 break;
1019         case IXGBE_LINK_SPEED_1GB_FULL:
1020                 pb_headroom = IXGBE_DMACRXT_1G;
1021                 break;
1022         default:
1023                 pb_headroom = IXGBE_DMACRXT_10G;
1024                 break;
1025         }
1026
1027         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
1028                              IXGBE_MHADD_MFS_SHIFT) / 1024);
1029
1030         /* Set the per Rx packet buffer receive threshold */
1031         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
1032                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
1033                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
1034
1035                 if (tc < hw->mac.dmac_config.num_tcs) {
1036                         /* Get Rx PB size */
1037                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
1038                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
1039                                 IXGBE_RXPBSIZE_SHIFT;
1040
1041                         /* Calculate receive buffer threshold in kilobytes */
1042                         if (rx_pb_size > pb_headroom)
1043                                 rx_pb_size = rx_pb_size - pb_headroom;
1044                         else
1045                                 rx_pb_size = 0;
1046
1047                         /* Minimum of MFS shall be set for DMCTH */
1048                         reg |= (rx_pb_size > maxframe_size_kb) ?
1049                                 rx_pb_size : maxframe_size_kb;
1050                 }
1051                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
1052         }
1053         return IXGBE_SUCCESS;
1054 }
1055
1056 /**
1057  *  ixgbe_dmac_update_tcs_X550
1058  *  @hw: pointer to hardware structure
1059  *
1060  *  Disables dmac, updates per TC settings, and then enables dmac.
1061  **/
1062 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
1063 {
1064         u32 reg;
1065
1066         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
1067
1068         /* Disable DMA coalescing before configuring */
1069         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
1070         reg &= ~IXGBE_DMACR_DMAC_EN;
1071         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
1072
1073         ixgbe_dmac_config_tcs_X550(hw);
1074
1075         /* Enable DMA coalescing after configuration */
1076         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
1077         reg |= IXGBE_DMACR_DMAC_EN;
1078         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
1079
1080         return IXGBE_SUCCESS;
1081 }
1082
1083 /**
1084  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
1085  *  @hw: pointer to hardware structure
1086  *
1087  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
1088  *  ixgbe_hw struct in order to set up EEPROM access.
1089  **/
1090 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
1091 {
1092         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1093         u32 eec;
1094         u16 eeprom_size;
1095
1096         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
1097
1098         if (eeprom->type == ixgbe_eeprom_uninitialized) {
1099                 eeprom->semaphore_delay = 10;
1100                 eeprom->type = ixgbe_flash;
1101
1102                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1103                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1104                                     IXGBE_EEC_SIZE_SHIFT);
1105                 eeprom->word_size = 1 << (eeprom_size +
1106                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
1107
1108                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
1109                           eeprom->type, eeprom->word_size);
1110         }
1111
1112         return IXGBE_SUCCESS;
1113 }
1114
1115 /**
1116  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1117  * @hw: pointer to hardware structure
1118  * @enable: enable or disable source address pruning
1119  * @pool: Rx pool to set source address pruning for
1120  **/
1121 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1122                                            unsigned int pool)
1123 {
1124         u64 pfflp;
1125
1126         /* max rx pool is 63 */
1127         if (pool > 63)
1128                 return;
1129
1130         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1131         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1132
1133         if (enable)
1134                 pfflp |= (1ULL << pool);
1135         else
1136                 pfflp &= ~(1ULL << pool);
1137
1138         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1139         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1140 }
1141
1142 /**
1143  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1144  *  @hw: pointer to hardware structure
1145  *  @enable: enable or disable switch for Ethertype anti-spoofing
1146  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1147  *
1148  **/
1149 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1150                 bool enable, int vf)
1151 {
1152         int vf_target_reg = vf >> 3;
1153         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1154         u32 pfvfspoof;
1155
1156         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1157
1158         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1159         if (enable)
1160                 pfvfspoof |= (1 << vf_target_shift);
1161         else
1162                 pfvfspoof &= ~(1 << vf_target_shift);
1163
1164         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1165 }
1166
1167 /**
1168  * ixgbe_iosf_wait - Wait for IOSF command completion
1169  * @hw: pointer to hardware structure
1170  * @ctrl: pointer to location to receive final IOSF control value
1171  *
1172  * Returns failing status on timeout
1173  *
1174  * Note: ctrl can be NULL if the IOSF control register value is not needed
1175  **/
1176 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1177 {
1178         u32 i, command = 0;
1179
1180         /* Check every 10 usec to see if the address cycle completed.
1181          * The SB IOSF BUSY bit will clear when the operation is
1182          * complete
1183          */
1184         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1185                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1186                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1187                         break;
1188                 usec_delay(10);
1189         }
1190         if (ctrl)
1191                 *ctrl = command;
1192         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1193                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1194                 return IXGBE_ERR_PHY;
1195         }
1196
1197         return IXGBE_SUCCESS;
1198 }
1199
1200 /**
1201  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register
1202  *  of the IOSF device
1203  *  @hw: pointer to hardware structure
1204  *  @reg_addr: 32 bit PHY register to write
1205  *  @device_type: 3 bit device type
1206  *  @data: Data to write to the register
1207  **/
1208 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1209                             u32 device_type, u32 data)
1210 {
1211         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1212         u32 command, error;
1213         s32 ret;
1214
1215         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1216         if (ret != IXGBE_SUCCESS)
1217                 return ret;
1218
1219         ret = ixgbe_iosf_wait(hw, NULL);
1220         if (ret != IXGBE_SUCCESS)
1221                 goto out;
1222
1223         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1224                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1225
1226         /* Write IOSF control register */
1227         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1228
1229         /* Write IOSF data register */
1230         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1231
1232         ret = ixgbe_iosf_wait(hw, &command);
1233
1234         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1235                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1236                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1237                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1238                               "Failed to write, error %x\n", error);
1239                 ret = IXGBE_ERR_PHY;
1240         }
1241
1242 out:
1243         ixgbe_release_swfw_semaphore(hw, gssr);
1244         return ret;
1245 }
1246
1247 /**
1248  *  ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device
1249  *  @hw: pointer to hardware structure
1250  *  @reg_addr: 32 bit PHY register to write
1251  *  @device_type: 3 bit device type
1252  *  @data: Pointer to read data from the register
1253  **/
1254 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1255                            u32 device_type, u32 *data)
1256 {
1257         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1258         u32 command, error;
1259         s32 ret;
1260
1261         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1262         if (ret != IXGBE_SUCCESS)
1263                 return ret;
1264
1265         ret = ixgbe_iosf_wait(hw, NULL);
1266         if (ret != IXGBE_SUCCESS)
1267                 goto out;
1268
1269         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1270                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1271
1272         /* Write IOSF control register */
1273         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1274
1275         ret = ixgbe_iosf_wait(hw, &command);
1276
1277         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1278                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1279                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1280                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1281                                 "Failed to read, error %x\n", error);
1282                 ret = IXGBE_ERR_PHY;
1283         }
1284
1285         if (ret == IXGBE_SUCCESS)
1286                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1287
1288 out:
1289         ixgbe_release_swfw_semaphore(hw, gssr);
1290         return ret;
1291 }
1292
1293 /**
1294  * ixgbe_get_phy_token - Get the token for shared phy access
1295  * @hw: Pointer to hardware structure
1296  */
1297
1298 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1299 {
1300         struct ixgbe_hic_phy_token_req token_cmd;
1301         s32 status;
1302
1303         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1304         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1305         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1306         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1307         token_cmd.port_number = hw->bus.lan_id;
1308         token_cmd.command_type = FW_PHY_TOKEN_REQ;
1309         token_cmd.pad = 0;
1310         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1311                                               sizeof(token_cmd),
1312                                               IXGBE_HI_COMMAND_TIMEOUT,
1313                                               true);
1314         if (status)
1315                 return status;
1316         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1317                 return IXGBE_SUCCESS;
1318         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1319                 return IXGBE_ERR_FW_RESP_INVALID;
1320
1321         return IXGBE_ERR_TOKEN_RETRY;
1322 }
1323
1324 /**
1325  * ixgbe_put_phy_token - Put the token for shared phy access
1326  * @hw: Pointer to hardware structure
1327  */
1328
1329 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1330 {
1331         struct ixgbe_hic_phy_token_req token_cmd;
1332         s32 status;
1333
1334         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1335         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1336         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1337         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1338         token_cmd.port_number = hw->bus.lan_id;
1339         token_cmd.command_type = FW_PHY_TOKEN_REL;
1340         token_cmd.pad = 0;
1341         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1342                                               sizeof(token_cmd),
1343                                               IXGBE_HI_COMMAND_TIMEOUT,
1344                                               true);
1345         if (status)
1346                 return status;
1347         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1348                 return IXGBE_SUCCESS;
1349
1350         DEBUGOUT("Put PHY Token host interface command failed");
1351         return IXGBE_ERR_FW_RESP_INVALID;
1352 }
1353
1354 /**
1355  *  ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1356  *  of the IOSF device
1357  *  @hw: pointer to hardware structure
1358  *  @reg_addr: 32 bit PHY register to write
1359  *  @device_type: 3 bit device type
1360  *  @data: Data to write to the register
1361  **/
1362 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1363                                   u32 device_type, u32 data)
1364 {
1365         struct ixgbe_hic_internal_phy_req write_cmd;
1366         s32 status;
1367         UNREFERENCED_1PARAMETER(device_type);
1368
1369         memset(&write_cmd, 0, sizeof(write_cmd));
1370         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1371         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1372         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1373         write_cmd.port_number = hw->bus.lan_id;
1374         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1375         write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1376         write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1377
1378         status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1379                                               sizeof(write_cmd),
1380                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1381
1382         return status;
1383 }
1384
1385 /**
1386  *  ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device
1387  *  @hw: pointer to hardware structure
1388  *  @reg_addr: 32 bit PHY register to write
1389  *  @device_type: 3 bit device type
1390  *  @data: Pointer to read data from the register
1391  **/
1392 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1393                                  u32 device_type, u32 *data)
1394 {
1395         union {
1396                 struct ixgbe_hic_internal_phy_req cmd;
1397                 struct ixgbe_hic_internal_phy_resp rsp;
1398         } hic;
1399         s32 status;
1400         UNREFERENCED_1PARAMETER(device_type);
1401
1402         memset(&hic, 0, sizeof(hic));
1403         hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1404         hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1405         hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1406         hic.cmd.port_number = hw->bus.lan_id;
1407         hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1408         hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1409
1410         status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1411                                               sizeof(hic.cmd),
1412                                               IXGBE_HI_COMMAND_TIMEOUT, true);
1413
1414         /* Extract the register value from the response. */
1415         *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1416
1417         return status;
1418 }
1419
1420 /**
1421  *  ixgbe_disable_mdd_X550
1422  *  @hw: pointer to hardware structure
1423  *
1424  *  Disable malicious driver detection
1425  **/
1426 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1427 {
1428         u32 reg;
1429
1430         DEBUGFUNC("ixgbe_disable_mdd_X550");
1431
1432         /* Disable MDD for TX DMA and interrupt */
1433         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1434         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1435         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1436
1437         /* Disable MDD for RX and interrupt */
1438         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1439         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1440         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1441 }
1442
1443 /**
1444  *  ixgbe_enable_mdd_X550
1445  *  @hw: pointer to hardware structure
1446  *
1447  *  Enable malicious driver detection
1448  **/
1449 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1450 {
1451         u32 reg;
1452
1453         DEBUGFUNC("ixgbe_enable_mdd_X550");
1454
1455         /* Enable MDD for TX DMA and interrupt */
1456         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1457         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1458         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1459
1460         /* Enable MDD for RX and interrupt */
1461         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1462         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1463         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1464 }
1465
1466 /**
1467  *  ixgbe_restore_mdd_vf_X550
1468  *  @hw: pointer to hardware structure
1469  *  @vf: vf index
1470  *
1471  *  Restore VF that was disabled during malicious driver detection event
1472  **/
1473 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1474 {
1475         u32 idx, reg, num_qs, start_q, bitmask;
1476
1477         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1478
1479         /* Map VF to queues */
1480         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1481         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1482         case IXGBE_MRQC_VMDQRT8TCEN:
1483                 num_qs = 8;  /* 16 VFs / pools */
1484                 bitmask = 0x000000FF;
1485                 break;
1486         case IXGBE_MRQC_VMDQRSS32EN:
1487         case IXGBE_MRQC_VMDQRT4TCEN:
1488                 num_qs = 4;  /* 32 VFs / pools */
1489                 bitmask = 0x0000000F;
1490                 break;
1491         default:            /* 64 VFs / pools */
1492                 num_qs = 2;
1493                 bitmask = 0x00000003;
1494                 break;
1495         }
1496         start_q = vf * num_qs;
1497
1498         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1499         idx = start_q / 32;
1500         reg = 0;
1501         reg |= (bitmask << (start_q % 32));
1502         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1503         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1504 }
1505
1506 /**
1507  *  ixgbe_mdd_event_X550
1508  *  @hw: pointer to hardware structure
1509  *  @vf_bitmap: vf bitmap of malicious vfs
1510  *
1511  *  Handle malicious driver detection event.
1512  **/
1513 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1514 {
1515         u32 wqbr;
1516         u32 i, j, reg, q, shift, vf, idx;
1517
1518         DEBUGFUNC("ixgbe_mdd_event_X550");
1519
1520         /* figure out pool size for mapping to vf's */
1521         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1522         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1523         case IXGBE_MRQC_VMDQRT8TCEN:
1524                 shift = 3;  /* 16 VFs / pools */
1525                 break;
1526         case IXGBE_MRQC_VMDQRSS32EN:
1527         case IXGBE_MRQC_VMDQRT4TCEN:
1528                 shift = 2;  /* 32 VFs / pools */
1529                 break;
1530         default:
1531                 shift = 1;  /* 64 VFs / pools */
1532                 break;
1533         }
1534
1535         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1536         for (i = 0; i < 4; i++) {
1537                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1538                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1539
1540                 if (!wqbr)
1541                         continue;
1542
1543                 /* Get malicious queue */
1544                 for (j = 0; j < 32 && wqbr; j++) {
1545
1546                         if (!(wqbr & (1 << j)))
1547                                 continue;
1548
1549                         /* Get queue from bitmask */
1550                         q = j + (i * 32);
1551
1552                         /* Map queue to vf */
1553                         vf = (q >> shift);
1554
1555                         /* Set vf bit in vf_bitmap */
1556                         idx = vf / 32;
1557                         vf_bitmap[idx] |= (1 << (vf % 32));
1558                         wqbr &= ~(1 << j);
1559                 }
1560         }
1561 }
1562
1563 /**
1564  *  ixgbe_get_media_type_X550em - Get media type
1565  *  @hw: pointer to hardware structure
1566  *
1567  *  Returns the media type (fiber, copper, backplane)
1568  */
1569 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1570 {
1571         enum ixgbe_media_type media_type;
1572
1573         DEBUGFUNC("ixgbe_get_media_type_X550em");
1574
1575         /* Detect if there is a copper PHY attached. */
1576         switch (hw->device_id) {
1577         case IXGBE_DEV_ID_X550EM_X_KR:
1578         case IXGBE_DEV_ID_X550EM_X_KX4:
1579         case IXGBE_DEV_ID_X550EM_X_XFI:
1580         case IXGBE_DEV_ID_X550EM_A_KR:
1581         case IXGBE_DEV_ID_X550EM_A_KR_L:
1582                 media_type = ixgbe_media_type_backplane;
1583                 break;
1584         case IXGBE_DEV_ID_X550EM_X_SFP:
1585         case IXGBE_DEV_ID_X550EM_A_SFP:
1586         case IXGBE_DEV_ID_X550EM_A_SFP_N:
1587         case IXGBE_DEV_ID_X550EM_A_QSFP:
1588         case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1589                 media_type = ixgbe_media_type_fiber;
1590                 break;
1591         case IXGBE_DEV_ID_X550EM_X_1G_T:
1592         case IXGBE_DEV_ID_X550EM_X_10G_T:
1593         case IXGBE_DEV_ID_X550EM_A_10G_T:
1594                 media_type = ixgbe_media_type_copper;
1595                 break;
1596         case IXGBE_DEV_ID_X550EM_A_SGMII:
1597         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1598                 media_type = ixgbe_media_type_backplane;
1599                 hw->phy.type = ixgbe_phy_sgmii;
1600                 break;
1601         case IXGBE_DEV_ID_X550EM_A_1G_T:
1602         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1603                 media_type = ixgbe_media_type_copper;
1604                 break;
1605         default:
1606                 media_type = ixgbe_media_type_unknown;
1607                 break;
1608         }
1609         return media_type;
1610 }
1611
1612 /**
1613  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1614  *  @hw: pointer to hardware structure
1615  *  @linear: true if SFP module is linear
1616  */
1617 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1618 {
1619         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1620
1621         switch (hw->phy.sfp_type) {
1622         case ixgbe_sfp_type_not_present:
1623                 return IXGBE_ERR_SFP_NOT_PRESENT;
1624         case ixgbe_sfp_type_da_cu_core0:
1625         case ixgbe_sfp_type_da_cu_core1:
1626                 *linear = true;
1627                 break;
1628         case ixgbe_sfp_type_srlr_core0:
1629         case ixgbe_sfp_type_srlr_core1:
1630         case ixgbe_sfp_type_da_act_lmt_core0:
1631         case ixgbe_sfp_type_da_act_lmt_core1:
1632         case ixgbe_sfp_type_1g_sx_core0:
1633         case ixgbe_sfp_type_1g_sx_core1:
1634         case ixgbe_sfp_type_1g_lx_core0:
1635         case ixgbe_sfp_type_1g_lx_core1:
1636                 *linear = false;
1637                 break;
1638         case ixgbe_sfp_type_unknown:
1639         case ixgbe_sfp_type_1g_cu_core0:
1640         case ixgbe_sfp_type_1g_cu_core1:
1641         default:
1642                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1643         }
1644
1645         return IXGBE_SUCCESS;
1646 }
1647
1648 /**
1649  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1650  *  @hw: pointer to hardware structure
1651  *
1652  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1653  **/
1654 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1655 {
1656         s32 status;
1657         bool linear;
1658
1659         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1660
1661         status = ixgbe_identify_module_generic(hw);
1662
1663         if (status != IXGBE_SUCCESS)
1664                 return status;
1665
1666         /* Check if SFP module is supported */
1667         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1668
1669         return status;
1670 }
1671
1672 /**
1673  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1674  *  @hw: pointer to hardware structure
1675  */
1676 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1677 {
1678         s32 status;
1679         bool linear;
1680
1681         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1682
1683         /* Check if SFP module is supported */
1684         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1685
1686         if (status != IXGBE_SUCCESS)
1687                 return status;
1688
1689         ixgbe_init_mac_link_ops_X550em(hw);
1690         hw->phy.ops.reset = NULL;
1691
1692         return IXGBE_SUCCESS;
1693 }
1694
1695 /**
1696 *  ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1697 *  internal PHY
1698 *  @hw: pointer to hardware structure
1699 **/
1700 STATIC s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1701 {
1702         s32 status;
1703         u32 link_ctrl;
1704
1705         /* Restart auto-negotiation. */
1706         status = hw->mac.ops.read_iosf_sb_reg(hw,
1707                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1708                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1709
1710         if (status) {
1711                 DEBUGOUT("Auto-negotiation did not complete\n");
1712                 return status;
1713         }
1714
1715         link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1716         status = hw->mac.ops.write_iosf_sb_reg(hw,
1717                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1718                                         IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1719
1720         if (hw->mac.type == ixgbe_mac_X550EM_a) {
1721                 u32 flx_mask_st20;
1722
1723                 /* Indicate to FW that AN restart has been asserted */
1724                 status = hw->mac.ops.read_iosf_sb_reg(hw,
1725                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1726                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1727
1728                 if (status) {
1729                         DEBUGOUT("Auto-negotiation did not complete\n");
1730                         return status;
1731                 }
1732
1733                 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1734                 status = hw->mac.ops.write_iosf_sb_reg(hw,
1735                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1736                                 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1737         }
1738
1739         return status;
1740 }
1741
1742 /**
1743  * ixgbe_setup_sgmii - Set up link for sgmii
1744  * @hw: pointer to hardware structure
1745  */
1746 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1747                              bool autoneg_wait)
1748 {
1749         struct ixgbe_mac_info *mac = &hw->mac;
1750         u32 lval, sval, flx_val;
1751         s32 rc;
1752
1753         rc = mac->ops.read_iosf_sb_reg(hw,
1754                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1755                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1756         if (rc)
1757                 return rc;
1758
1759         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1760         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1761         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1762         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1763         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1764         rc = mac->ops.write_iosf_sb_reg(hw,
1765                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1766                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1767         if (rc)
1768                 return rc;
1769
1770         rc = mac->ops.read_iosf_sb_reg(hw,
1771                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1772                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1773         if (rc)
1774                 return rc;
1775
1776         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1777         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1778         rc = mac->ops.write_iosf_sb_reg(hw,
1779                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1780                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1781         if (rc)
1782                 return rc;
1783
1784         rc = mac->ops.read_iosf_sb_reg(hw,
1785                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1786                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1787         if (rc)
1788                 return rc;
1789
1790         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1791         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1792         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1793         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1794         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1795
1796         rc = mac->ops.write_iosf_sb_reg(hw,
1797                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1798                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1799         if (rc)
1800                 return rc;
1801
1802         rc = ixgbe_restart_an_internal_phy_x550em(hw);
1803         if (rc)
1804                 return rc;
1805
1806         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1807 }
1808
1809 /**
1810  * ixgbe_setup_sgmii_fw - Set up link for sgmii with firmware-controlled PHYs
1811  * @hw: pointer to hardware structure
1812  */
1813 STATIC s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1814                                 bool autoneg_wait)
1815 {
1816         struct ixgbe_mac_info *mac = &hw->mac;
1817         u32 lval, sval, flx_val;
1818         s32 rc;
1819
1820         rc = mac->ops.read_iosf_sb_reg(hw,
1821                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1822                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1823         if (rc)
1824                 return rc;
1825
1826         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1827         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1828         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1829         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1830         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1831         rc = mac->ops.write_iosf_sb_reg(hw,
1832                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1833                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1834         if (rc)
1835                 return rc;
1836
1837         rc = mac->ops.read_iosf_sb_reg(hw,
1838                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1839                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1840         if (rc)
1841                 return rc;
1842
1843         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1844         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1845         rc = mac->ops.write_iosf_sb_reg(hw,
1846                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1847                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1848         if (rc)
1849                 return rc;
1850
1851         rc = mac->ops.write_iosf_sb_reg(hw,
1852                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1853                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1854         if (rc)
1855                 return rc;
1856
1857         rc = mac->ops.read_iosf_sb_reg(hw,
1858                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1859                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1860         if (rc)
1861                 return rc;
1862
1863         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1864         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
1865         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1866         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1867         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1868
1869         rc = mac->ops.write_iosf_sb_reg(hw,
1870                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1871                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1872         if (rc)
1873                 return rc;
1874
1875         rc = ixgbe_restart_an_internal_phy_x550em(hw);
1876
1877         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1878 }
1879
1880 /**
1881  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1882  *  @hw: pointer to hardware structure
1883  */
1884 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1885 {
1886         struct ixgbe_mac_info *mac = &hw->mac;
1887
1888         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1889
1890         switch (hw->mac.ops.get_media_type(hw)) {
1891         case ixgbe_media_type_fiber:
1892                 /* CS4227 does not support autoneg, so disable the laser control
1893                  * functions for SFP+ fiber
1894                  */
1895                 mac->ops.disable_tx_laser = NULL;
1896                 mac->ops.enable_tx_laser = NULL;
1897                 mac->ops.flap_tx_laser = NULL;
1898                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1899                 mac->ops.set_rate_select_speed =
1900                                         ixgbe_set_soft_rate_select_speed;
1901
1902                 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1903                     (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1904                         mac->ops.setup_mac_link =
1905                                                 ixgbe_setup_mac_link_sfp_x550a;
1906                 else
1907                         mac->ops.setup_mac_link =
1908                                                 ixgbe_setup_mac_link_sfp_x550em;
1909                 break;
1910         case ixgbe_media_type_copper:
1911                 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1912                         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
1913                             hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
1914                                 mac->ops.setup_link = ixgbe_setup_sgmii_fw;
1915                                 mac->ops.check_link =
1916                                                    ixgbe_check_mac_link_generic;
1917                         } else {
1918                                 mac->ops.setup_link =
1919                                                   ixgbe_setup_mac_link_t_X550em;
1920                         }
1921                 } else {
1922                         mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1923                         mac->ops.check_link = ixgbe_check_link_t_X550em;
1924                 }
1925                 break;
1926         case ixgbe_media_type_backplane:
1927                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1928                     hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1929                         mac->ops.setup_link = ixgbe_setup_sgmii;
1930                 break;
1931         default:
1932                 break;
1933         }
1934 }
1935
1936 /**
1937  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1938  *  @hw: pointer to hardware structure
1939  *  @speed: pointer to link speed
1940  *  @autoneg: true when autoneg or autotry is enabled
1941  */
1942 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1943                                        ixgbe_link_speed *speed,
1944                                        bool *autoneg)
1945 {
1946         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1947
1948
1949         if (hw->phy.type == ixgbe_phy_fw) {
1950                 *autoneg = true;
1951                 *speed = hw->phy.speeds_supported;
1952                 return 0;
1953         }
1954
1955         /* SFP */
1956         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1957
1958                 /* CS4227 SFP must not enable auto-negotiation */
1959                 *autoneg = false;
1960
1961                 /* Check if 1G SFP module. */
1962                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1963                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1964                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1965                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1966                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1967                         return IXGBE_SUCCESS;
1968                 }
1969
1970                 /* Link capabilities are based on SFP */
1971                 if (hw->phy.multispeed_fiber)
1972                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1973                                  IXGBE_LINK_SPEED_1GB_FULL;
1974                 else
1975                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1976         } else {
1977                 switch (hw->phy.type) {
1978                 case ixgbe_phy_sgmii:
1979                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1980                         break;
1981                 case ixgbe_phy_x550em_kr:
1982                         if (hw->mac.type == ixgbe_mac_X550EM_a) {
1983                                 /* check different backplane modes */
1984                                 if (hw->phy.nw_mng_if_sel &
1985                                            IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
1986                                         *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
1987                                         break;
1988                                 } else if (hw->device_id ==
1989                                                    IXGBE_DEV_ID_X550EM_A_KR_L) {
1990                                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1991                                         break;
1992                                 }
1993                         }
1994                         /* fall through */
1995                 default:
1996                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1997                                  IXGBE_LINK_SPEED_1GB_FULL;
1998                         break;
1999                 }
2000                 *autoneg = true;
2001         }
2002
2003         return IXGBE_SUCCESS;
2004 }
2005
2006 /**
2007  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
2008  * @hw: pointer to hardware structure
2009  * @lsc: pointer to boolean flag which indicates whether external Base T
2010  *       PHY interrupt is lsc
2011  *
2012  * Determime if external Base T PHY interrupt cause is high temperature
2013  * failure alarm or link status change.
2014  *
2015  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2016  * failure alarm, else return PHY access status.
2017  */
2018 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
2019 {
2020         u32 status;
2021         u16 reg;
2022
2023         *lsc = false;
2024
2025         /* Vendor alarm triggered */
2026         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2027                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2028                                       &reg);
2029
2030         if (status != IXGBE_SUCCESS ||
2031             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
2032                 return status;
2033
2034         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
2035         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
2036                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2037                                       &reg);
2038
2039         if (status != IXGBE_SUCCESS ||
2040             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2041             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
2042                 return status;
2043
2044         /* Global alarm triggered */
2045         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
2046                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2047                                       &reg);
2048
2049         if (status != IXGBE_SUCCESS)
2050                 return status;
2051
2052         /* If high temperature failure, then return over temp error and exit */
2053         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
2054                 /* power down the PHY in case the PHY FW didn't already */
2055                 ixgbe_set_copper_phy_power(hw, false);
2056                 return IXGBE_ERR_OVERTEMP;
2057         } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
2058                 /*  device fault alarm triggered */
2059                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
2060                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2061                                           &reg);
2062
2063                 if (status != IXGBE_SUCCESS)
2064                         return status;
2065
2066                 /* if device fault was due to high temp alarm handle and exit */
2067                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
2068                         /* power down the PHY in case the PHY FW didn't */
2069                         ixgbe_set_copper_phy_power(hw, false);
2070                         return IXGBE_ERR_OVERTEMP;
2071                 }
2072         }
2073
2074         /* Vendor alarm 2 triggered */
2075         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2076                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2077
2078         if (status != IXGBE_SUCCESS ||
2079             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
2080                 return status;
2081
2082         /* link connect/disconnect event occurred */
2083         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
2084                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2085
2086         if (status != IXGBE_SUCCESS)
2087                 return status;
2088
2089         /* Indicate LSC */
2090         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2091                 *lsc = true;
2092
2093         return IXGBE_SUCCESS;
2094 }
2095
2096 /**
2097  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2098  * @hw: pointer to hardware structure
2099  *
2100  * Enable link status change and temperature failure alarm for the external
2101  * Base T PHY
2102  *
2103  * Returns PHY access status
2104  */
2105 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2106 {
2107         u32 status;
2108         u16 reg;
2109         bool lsc;
2110
2111         /* Clear interrupt flags */
2112         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2113
2114         /* Enable link status change alarm */
2115
2116         /* Enable the LASI interrupts on X552 devices to receive notifications
2117          * of the link configurations of the external PHY and correspondingly
2118          * support the configuration of the internal iXFI link, since iXFI does
2119          * not support auto-negotiation. This is not required for X553 devices
2120          * having KR support, which performs auto-negotiations and which is used
2121          * as the internal link to the external PHY. Hence adding a check here
2122          * to avoid enabling LASI interrupts for X553 devices.
2123          */
2124         if (hw->mac.type != ixgbe_mac_X550EM_a) {
2125                 status = hw->phy.ops.read_reg(hw,
2126                                         IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2127                                         IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2128
2129                 if (status != IXGBE_SUCCESS)
2130                         return status;
2131
2132                 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2133
2134                 status = hw->phy.ops.write_reg(hw,
2135                                         IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2136                                         IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
2137
2138                 if (status != IXGBE_SUCCESS)
2139                         return status;
2140         }
2141
2142         /* Enable high temperature failure and global fault alarms */
2143         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2144                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2145                                       &reg);
2146
2147         if (status != IXGBE_SUCCESS)
2148                 return status;
2149
2150         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2151                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2152
2153         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2154                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2155                                        reg);
2156
2157         if (status != IXGBE_SUCCESS)
2158                 return status;
2159
2160         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2161         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2162                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2163                                       &reg);
2164
2165         if (status != IXGBE_SUCCESS)
2166                 return status;
2167
2168         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2169                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2170
2171         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2172                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2173                                        reg);
2174
2175         if (status != IXGBE_SUCCESS)
2176                 return status;
2177
2178         /* Enable chip-wide vendor alarm */
2179         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2180                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2181                                       &reg);
2182
2183         if (status != IXGBE_SUCCESS)
2184                 return status;
2185
2186         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2187
2188         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2189                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2190                                        reg);
2191
2192         return status;
2193 }
2194
2195 /**
2196  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2197  *  @hw: pointer to hardware structure
2198  *  @speed: link speed
2199  *
2200  *  Configures the integrated KR PHY.
2201  **/
2202 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2203                                        ixgbe_link_speed speed)
2204 {
2205         s32 status;
2206         u32 reg_val;
2207
2208         status = hw->mac.ops.read_iosf_sb_reg(hw,
2209                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2210                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2211         if (status)
2212                 return status;
2213
2214         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2215         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2216                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2217
2218         /* Advertise 10G support. */
2219         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2220                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2221
2222         /* Advertise 1G support. */
2223         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2224                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2225
2226         status = hw->mac.ops.write_iosf_sb_reg(hw,
2227                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2228                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2229
2230         if (hw->mac.type == ixgbe_mac_X550EM_a) {
2231                 /* Set lane mode  to KR auto negotiation */
2232                 status = hw->mac.ops.read_iosf_sb_reg(hw,
2233                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2234                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2235
2236                 if (status)
2237                         return status;
2238
2239                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2240                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2241                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2242                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2243                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2244
2245                 status = hw->mac.ops.write_iosf_sb_reg(hw,
2246                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2247                                     IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2248         }
2249
2250         return ixgbe_restart_an_internal_phy_x550em(hw);
2251 }
2252
2253 /**
2254  * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs
2255  * @hw: pointer to hardware structure
2256  */
2257 static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw)
2258 {
2259         u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
2260         s32 rc;
2261
2262         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2263                 return IXGBE_SUCCESS;
2264
2265         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store);
2266         if (rc)
2267                 return rc;
2268         memset(store, 0, sizeof(store));
2269
2270         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store);
2271         if (rc)
2272                 return rc;
2273
2274         return ixgbe_setup_fw_link(hw);
2275 }
2276
2277 /**
2278  * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp
2279  * @hw: pointer to hardware structure
2280  */
2281 static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw)
2282 {
2283         u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
2284         s32 rc;
2285
2286         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store);
2287         if (rc)
2288                 return rc;
2289
2290         if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) {
2291                 ixgbe_shutdown_fw_phy(hw);
2292                 return IXGBE_ERR_OVERTEMP;
2293         }
2294         return IXGBE_SUCCESS;
2295 }
2296
2297 /**
2298  *  ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2299  *  @hw: pointer to hardware structure
2300  *
2301  *  Read NW_MNG_IF_SEL register and save field values, and check for valid field
2302  *  values.
2303  **/
2304 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2305 {
2306         /* Save NW management interface connected on board. This is used
2307          * to determine internal PHY mode.
2308          */
2309         hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2310
2311         /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2312          * PHY address. This register field was has only been used for X552.
2313          */
2314         if (hw->mac.type == ixgbe_mac_X550EM_a &&
2315             hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2316                 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2317                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2318                                IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2319         }
2320
2321         return IXGBE_SUCCESS;
2322 }
2323
2324 /**
2325  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2326  *  @hw: pointer to hardware structure
2327  *
2328  *  Initialize any function pointers that were not able to be
2329  *  set during init_shared_code because the PHY/SFP type was
2330  *  not known.  Perform the SFP init if necessary.
2331  */
2332 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2333 {
2334         struct ixgbe_phy_info *phy = &hw->phy;
2335         s32 ret_val;
2336
2337         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2338
2339         hw->mac.ops.set_lan_id(hw);
2340         ixgbe_read_mng_if_sel_x550em(hw);
2341
2342         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2343                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2344                 ixgbe_setup_mux_ctl(hw);
2345                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2346         }
2347
2348         switch (hw->device_id) {
2349         case IXGBE_DEV_ID_X550EM_A_1G_T:
2350         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2351                 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2352                 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2353                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2354                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2355                 phy->ops.check_overtemp = ixgbe_check_overtemp_fw;
2356                 if (hw->bus.lan_id)
2357                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2358                 else
2359                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2360
2361                 break;
2362         case IXGBE_DEV_ID_X550EM_A_10G_T:
2363         case IXGBE_DEV_ID_X550EM_A_SFP:
2364                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2365                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2366                 if (hw->bus.lan_id)
2367                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2368                 else
2369                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2370                 break;
2371         case IXGBE_DEV_ID_X550EM_X_SFP:
2372                 /* set up for CS4227 usage */
2373                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2374                 break;
2375         default:
2376                 break;
2377         }
2378
2379         /* Identify the PHY or SFP module */
2380         ret_val = phy->ops.identify(hw);
2381         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED ||
2382             ret_val == IXGBE_ERR_PHY_ADDR_INVALID)
2383                 return ret_val;
2384
2385         /* Setup function pointers based on detected hardware */
2386         ixgbe_init_mac_link_ops_X550em(hw);
2387         if (phy->sfp_type != ixgbe_sfp_type_unknown)
2388                 phy->ops.reset = NULL;
2389
2390         /* Set functions pointers based on phy type */
2391         switch (hw->phy.type) {
2392         case ixgbe_phy_x550em_kx4:
2393                 phy->ops.setup_link = NULL;
2394                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2395                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2396                 break;
2397         case ixgbe_phy_x550em_kr:
2398                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2399                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2400                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2401                 break;
2402         case ixgbe_phy_x550em_xfi:
2403                 /* link is managed by HW */
2404                 phy->ops.setup_link = NULL;
2405                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2406                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2407                 break;
2408         case ixgbe_phy_x550em_ext_t:
2409                 /* If internal link mode is XFI, then setup iXFI internal link,
2410                  * else setup KR now.
2411                  */
2412                 phy->ops.setup_internal_link =
2413                                               ixgbe_setup_internal_phy_t_x550em;
2414
2415                 /* setup SW LPLU only for first revision of X550EM_x */
2416                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2417                     !(IXGBE_FUSES0_REV_MASK &
2418                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2419                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2420
2421                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2422                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2423                 break;
2424         case ixgbe_phy_sgmii:
2425                 phy->ops.setup_link = NULL;
2426                 break;
2427         case ixgbe_phy_fw:
2428                 phy->ops.setup_link = ixgbe_setup_fw_link;
2429                 phy->ops.reset = ixgbe_reset_phy_fw;
2430                 break;
2431         default:
2432                 break;
2433         }
2434         return ret_val;
2435 }
2436
2437 /**
2438  * ixgbe_set_mdio_speed - Set MDIO clock speed
2439  *  @hw: pointer to hardware structure
2440  */
2441 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2442 {
2443         u32 hlreg0;
2444
2445         switch (hw->device_id) {
2446         case IXGBE_DEV_ID_X550EM_X_10G_T:
2447         case IXGBE_DEV_ID_X550EM_A_SGMII:
2448         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2449         case IXGBE_DEV_ID_X550EM_A_10G_T:
2450         case IXGBE_DEV_ID_X550EM_A_SFP:
2451         case IXGBE_DEV_ID_X550EM_A_QSFP:
2452                 /* Config MDIO clock speed before the first MDIO PHY access */
2453                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2454                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2455                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2456                 break;
2457         case IXGBE_DEV_ID_X550EM_A_1G_T:
2458         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2459                 /* Select fast MDIO clock speed for these devices */
2460                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2461                 hlreg0 |= IXGBE_HLREG0_MDCSPD;
2462                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2463                 break;
2464         default:
2465                 break;
2466         }
2467 }
2468
2469 /**
2470  *  ixgbe_reset_hw_X550em - Perform hardware reset
2471  *  @hw: pointer to hardware structure
2472  *
2473  *  Resets the hardware by resetting the transmit and receive units, masks
2474  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2475  *  reset.
2476  */
2477 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2478 {
2479         ixgbe_link_speed link_speed;
2480         s32 status;
2481         u32 ctrl = 0;
2482         u32 i;
2483         bool link_up = false;
2484
2485         DEBUGFUNC("ixgbe_reset_hw_X550em");
2486
2487         /* Call adapter stop to disable Tx/Rx and clear interrupts */
2488         status = hw->mac.ops.stop_adapter(hw);
2489         if (status != IXGBE_SUCCESS)
2490                 return status;
2491
2492         /* flush pending Tx transactions */
2493         ixgbe_clear_tx_pending(hw);
2494
2495         ixgbe_set_mdio_speed(hw);
2496
2497         /* PHY ops must be identified and initialized prior to reset */
2498         status = hw->phy.ops.init(hw);
2499
2500         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2501                 return status;
2502
2503         /* start the external PHY */
2504         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2505                 status = ixgbe_init_ext_t_x550em(hw);
2506                 if (status)
2507                         return status;
2508         }
2509
2510         /* Setup SFP module if there is one present. */
2511         if (hw->phy.sfp_setup_needed) {
2512                 status = hw->mac.ops.setup_sfp(hw);
2513                 hw->phy.sfp_setup_needed = false;
2514         }
2515
2516         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2517                 return status;
2518
2519         /* Reset PHY */
2520         if (!hw->phy.reset_disable && hw->phy.ops.reset) {
2521                 if (hw->phy.ops.reset(hw) == IXGBE_ERR_OVERTEMP)
2522                         return IXGBE_ERR_OVERTEMP;
2523         }
2524
2525 mac_reset_top:
2526         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2527          * If link reset is used when link is up, it might reset the PHY when
2528          * mng is using it.  If link is down or the flag to force full link
2529          * reset is set, then perform link reset.
2530          */
2531         ctrl = IXGBE_CTRL_LNK_RST;
2532         if (!hw->force_full_reset) {
2533                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2534                 if (link_up)
2535                         ctrl = IXGBE_CTRL_RST;
2536         }
2537
2538         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2539         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2540         IXGBE_WRITE_FLUSH(hw);
2541
2542         /* Poll for reset bit to self-clear meaning reset is complete */
2543         for (i = 0; i < 10; i++) {
2544                 usec_delay(1);
2545                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2546                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2547                         break;
2548         }
2549
2550         if (ctrl & IXGBE_CTRL_RST_MASK) {
2551                 status = IXGBE_ERR_RESET_FAILED;
2552                 DEBUGOUT("Reset polling failed to complete.\n");
2553         }
2554
2555         msec_delay(50);
2556
2557         /* Double resets are required for recovery from certain error
2558          * conditions.  Between resets, it is necessary to stall to
2559          * allow time for any pending HW events to complete.
2560          */
2561         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2562                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2563                 goto mac_reset_top;
2564         }
2565
2566         /* Store the permanent mac address */
2567         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2568
2569         /* Store MAC address from RAR0, clear receive address registers, and
2570          * clear the multicast table.  Also reset num_rar_entries to 128,
2571          * since we modify this value when programming the SAN MAC address.
2572          */
2573         hw->mac.num_rar_entries = 128;
2574         hw->mac.ops.init_rx_addrs(hw);
2575
2576         ixgbe_set_mdio_speed(hw);
2577
2578         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2579                 ixgbe_setup_mux_ctl(hw);
2580
2581         return status;
2582 }
2583
2584 /**
2585  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2586  * @hw: pointer to hardware structure
2587  */
2588 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2589 {
2590         u32 status;
2591         u16 reg;
2592
2593         status = hw->phy.ops.read_reg(hw,
2594                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2595                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2596                                       &reg);
2597
2598         if (status != IXGBE_SUCCESS)
2599                 return status;
2600
2601         /* If PHY FW reset completed bit is set then this is the first
2602          * SW instance after a power on so the PHY FW must be un-stalled.
2603          */
2604         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2605                 status = hw->phy.ops.read_reg(hw,
2606                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2607                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2608                                         &reg);
2609
2610                 if (status != IXGBE_SUCCESS)
2611                         return status;
2612
2613                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2614
2615                 status = hw->phy.ops.write_reg(hw,
2616                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2617                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2618                                         reg);
2619
2620                 if (status != IXGBE_SUCCESS)
2621                         return status;
2622         }
2623
2624         return status;
2625 }
2626
2627 /**
2628  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
2629  *  @hw: pointer to hardware structure
2630  **/
2631 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2632 {
2633         /* leave link alone for 2.5G */
2634         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL)
2635                 return IXGBE_SUCCESS;
2636
2637         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2638 }
2639
2640 /**
2641  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2642  *  @hw: pointer to hardware structure
2643  *
2644  *  Configure the external PHY and the integrated KR PHY for SFP support.
2645  **/
2646 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2647                                     ixgbe_link_speed speed,
2648                                     bool autoneg_wait_to_complete)
2649 {
2650         s32 ret_val;
2651         u16 reg_slice, reg_val;
2652         bool setup_linear = false;
2653         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2654
2655         /* Check if SFP module is supported and linear */
2656         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2657
2658         /* If no SFP module present, then return success. Return success since
2659          * there is no reason to configure CS4227 and SFP not present error is
2660          * not excepted in the setup MAC link flow.
2661          */
2662         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2663                 return IXGBE_SUCCESS;
2664
2665         if (ret_val != IXGBE_SUCCESS)
2666                 return ret_val;
2667
2668         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2669                 /* Configure CS4227 LINE side to 10G SR. */
2670                 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
2671                             (hw->bus.lan_id << 12);
2672                 reg_val = IXGBE_CS4227_SPEED_10G;
2673                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2674                                                   reg_val);
2675
2676                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2677                             (hw->bus.lan_id << 12);
2678                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2679                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2680                                                   reg_val);
2681
2682                 /* Configure CS4227 for HOST connection rate then type. */
2683                 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
2684                             (hw->bus.lan_id << 12);
2685                 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
2686                 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
2687                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2688                                                   reg_val);
2689
2690                 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
2691                             (hw->bus.lan_id << 12);
2692                 if (setup_linear)
2693                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2694                 else
2695                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2696                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2697                                                   reg_val);
2698
2699                 /* Setup XFI internal link. */
2700                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2701         } else {
2702                 /* Configure internal PHY for KR/KX. */
2703                 ixgbe_setup_kr_speed_x550em(hw, speed);
2704
2705                 /* Configure CS4227 LINE side to proper mode. */
2706                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2707                             (hw->bus.lan_id << 12);
2708                 if (setup_linear)
2709                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2710                 else
2711                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2712                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2713                                                   reg_val);
2714         }
2715         return ret_val;
2716 }
2717
2718 /**
2719  *  ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
2720  *  @hw: pointer to hardware structure
2721  *  @speed: the link speed to force
2722  *
2723  *  Configures the integrated PHY for native SFI mode. Used to connect the
2724  *  internal PHY directly to an SFP cage, without autonegotiation.
2725  **/
2726 STATIC s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2727 {
2728         struct ixgbe_mac_info *mac = &hw->mac;
2729         s32 status;
2730         u32 reg_val;
2731
2732         /* Disable all AN and force speed to 10G Serial. */
2733         status = mac->ops.read_iosf_sb_reg(hw,
2734                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2735                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2736         if (status != IXGBE_SUCCESS)
2737                 return status;
2738
2739         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2740         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2741         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2742         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2743
2744         /* Select forced link speed for internal PHY. */
2745         switch (*speed) {
2746         case IXGBE_LINK_SPEED_10GB_FULL:
2747                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
2748                 break;
2749         case IXGBE_LINK_SPEED_1GB_FULL:
2750                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2751                 break;
2752         default:
2753                 /* Other link speeds are not supported by internal PHY. */
2754                 return IXGBE_ERR_LINK_SETUP;
2755         }
2756
2757         status = mac->ops.write_iosf_sb_reg(hw,
2758                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2759                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2760
2761         /* Toggle port SW reset by AN reset. */
2762         status = ixgbe_restart_an_internal_phy_x550em(hw);
2763
2764         return status;
2765 }
2766
2767 /**
2768  *  ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2769  *  @hw: pointer to hardware structure
2770  *
2771  *  Configure the the integrated PHY for SFP support.
2772  **/
2773 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2774                                     ixgbe_link_speed speed,
2775                                     bool autoneg_wait_to_complete)
2776 {
2777         s32 ret_val;
2778         u16 reg_phy_ext;
2779         bool setup_linear = false;
2780         u32 reg_slice, reg_phy_int, slice_offset;
2781
2782         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2783
2784         /* Check if SFP module is supported and linear */
2785         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2786
2787         /* If no SFP module present, then return success. Return success since
2788          * SFP not present error is not excepted in the setup MAC link flow.
2789          */
2790         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2791                 return IXGBE_SUCCESS;
2792
2793         if (ret_val != IXGBE_SUCCESS)
2794                 return ret_val;
2795
2796         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2797                 /* Configure internal PHY for native SFI based on module type */
2798                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2799                                    IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2800                                    IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_phy_int);
2801
2802                 if (ret_val != IXGBE_SUCCESS)
2803                         return ret_val;
2804
2805                 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
2806                 if (!setup_linear)
2807                         reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
2808
2809                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2810                                    IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2811                                    IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2812
2813                 if (ret_val != IXGBE_SUCCESS)
2814                         return ret_val;
2815
2816                 /* Setup SFI internal link. */
2817                 ret_val = ixgbe_setup_sfi_x550a(hw, &speed);
2818         } else {
2819                 /* Configure internal PHY for KR/KX. */
2820                 ixgbe_setup_kr_speed_x550em(hw, speed);
2821
2822                 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2823                         /* Find Address */
2824                         DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2825                         return IXGBE_ERR_PHY_ADDR_INVALID;
2826                 }
2827
2828                 /* Get external PHY SKU id */
2829                 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,
2830                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2831
2832                 if (ret_val != IXGBE_SUCCESS)
2833                         return ret_val;
2834
2835                 /* When configuring quad port CS4223, the MAC instance is part
2836                  * of the slice offset.
2837                  */
2838                 if (reg_phy_ext == IXGBE_CS4223_SKU_ID)
2839                         slice_offset = (hw->bus.lan_id +
2840                                         (hw->bus.instance_id << 1)) << 12;
2841                 else
2842                         slice_offset = hw->bus.lan_id << 12;
2843
2844                 /* Configure CS4227/CS4223 LINE side to proper mode. */
2845                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2846
2847                 ret_val = hw->phy.ops.read_reg(hw, reg_slice,
2848                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2849
2850                 if (ret_val != IXGBE_SUCCESS)
2851                         return ret_val;
2852
2853                 reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) |
2854                                  (IXGBE_CS4227_EDC_MODE_SR << 1));
2855
2856                 if (setup_linear)
2857                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2858                 else
2859                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2860                 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2861                                          IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2862
2863                 /* Flush previous write with a read */
2864                 ret_val = hw->phy.ops.read_reg(hw, reg_slice,
2865                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2866         }
2867         return ret_val;
2868 }
2869
2870 /**
2871  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2872  *  @hw: pointer to hardware structure
2873  *
2874  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2875  **/
2876 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2877 {
2878         struct ixgbe_mac_info *mac = &hw->mac;
2879         s32 status;
2880         u32 reg_val;
2881
2882         /* Disable training protocol FSM. */
2883         status = mac->ops.read_iosf_sb_reg(hw,
2884                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2885                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2886         if (status != IXGBE_SUCCESS)
2887                 return status;
2888         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2889         status = mac->ops.write_iosf_sb_reg(hw,
2890                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2891                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2892         if (status != IXGBE_SUCCESS)
2893                 return status;
2894
2895         /* Disable Flex from training TXFFE. */
2896         status = mac->ops.read_iosf_sb_reg(hw,
2897                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2898                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2899         if (status != IXGBE_SUCCESS)
2900                 return status;
2901         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2902         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2903         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2904         status = mac->ops.write_iosf_sb_reg(hw,
2905                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2906                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2907         if (status != IXGBE_SUCCESS)
2908                 return status;
2909         status = mac->ops.read_iosf_sb_reg(hw,
2910                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2911                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2912         if (status != IXGBE_SUCCESS)
2913                 return status;
2914         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2915         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2916         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2917         status = mac->ops.write_iosf_sb_reg(hw,
2918                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2919                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2920         if (status != IXGBE_SUCCESS)
2921                 return status;
2922
2923         /* Enable override for coefficients. */
2924         status = mac->ops.read_iosf_sb_reg(hw,
2925                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2926                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2927         if (status != IXGBE_SUCCESS)
2928                 return status;
2929         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2930         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2931         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2932         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2933         status = mac->ops.write_iosf_sb_reg(hw,
2934                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2935                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2936         return status;
2937 }
2938
2939 /**
2940  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2941  *  @hw: pointer to hardware structure
2942  *  @speed: the link speed to force
2943  *
2944  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
2945  *  internal and external PHY at a specific speed, without autonegotiation.
2946  **/
2947 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2948 {
2949         struct ixgbe_mac_info *mac = &hw->mac;
2950         s32 status;
2951         u32 reg_val;
2952
2953         /* iXFI is only supported with X552 */
2954         if (mac->type != ixgbe_mac_X550EM_x)
2955                 return IXGBE_ERR_LINK_SETUP;
2956
2957         /* Disable AN and force speed to 10G Serial. */
2958         status = mac->ops.read_iosf_sb_reg(hw,
2959                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2960                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2961         if (status != IXGBE_SUCCESS)
2962                 return status;
2963
2964         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2965         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2966
2967         /* Select forced link speed for internal PHY. */
2968         switch (*speed) {
2969         case IXGBE_LINK_SPEED_10GB_FULL:
2970                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2971                 break;
2972         case IXGBE_LINK_SPEED_1GB_FULL:
2973                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2974                 break;
2975         default:
2976                 /* Other link speeds are not supported by internal KR PHY. */
2977                 return IXGBE_ERR_LINK_SETUP;
2978         }
2979
2980         status = mac->ops.write_iosf_sb_reg(hw,
2981                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2982                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2983         if (status != IXGBE_SUCCESS)
2984                 return status;
2985
2986         /* Additional configuration needed for x550em_x */
2987         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2988                 status = ixgbe_setup_ixfi_x550em_x(hw);
2989                 if (status != IXGBE_SUCCESS)
2990                         return status;
2991         }
2992
2993         /* Toggle port SW reset by AN reset. */
2994         status = ixgbe_restart_an_internal_phy_x550em(hw);
2995
2996         return status;
2997 }
2998
2999 /**
3000  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
3001  * @hw: address of hardware structure
3002  * @link_up: address of boolean to indicate link status
3003  *
3004  * Returns error code if unable to get link status.
3005  */
3006 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
3007 {
3008         u32 ret;
3009         u16 autoneg_status;
3010
3011         *link_up = false;
3012
3013         /* read this twice back to back to indicate current status */
3014         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3015                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3016                                    &autoneg_status);
3017         if (ret != IXGBE_SUCCESS)
3018                 return ret;
3019
3020         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3021                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3022                                    &autoneg_status);
3023         if (ret != IXGBE_SUCCESS)
3024                 return ret;
3025
3026         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
3027
3028         return IXGBE_SUCCESS;
3029 }
3030
3031 /**
3032  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
3033  * @hw: point to hardware structure
3034  *
3035  * Configures the link between the integrated KR PHY and the external X557 PHY
3036  * The driver will call this function when it gets a link status change
3037  * interrupt from the X557 PHY. This function configures the link speed
3038  * between the PHYs to match the link speed of the BASE-T link.
3039  *
3040  * A return of a non-zero value indicates an error, and the base driver should
3041  * not report link up.
3042  */
3043 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
3044 {
3045         ixgbe_link_speed force_speed;
3046         bool link_up;
3047         u32 status;
3048         u16 speed;
3049
3050         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3051                 return IXGBE_ERR_CONFIG;
3052
3053         if (hw->mac.type == ixgbe_mac_X550EM_x &&
3054             !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3055                 /* If link is down, there is no setup necessary so return  */
3056                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3057                 if (status != IXGBE_SUCCESS)
3058                         return status;
3059
3060                 if (!link_up)
3061                         return IXGBE_SUCCESS;
3062
3063                 status = hw->phy.ops.read_reg(hw,
3064                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3065                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3066                                               &speed);
3067                 if (status != IXGBE_SUCCESS)
3068                         return status;
3069
3070                 /* If link is still down - no setup is required so return */
3071                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3072                 if (status != IXGBE_SUCCESS)
3073                         return status;
3074                 if (!link_up)
3075                         return IXGBE_SUCCESS;
3076
3077                 /* clear everything but the speed and duplex bits */
3078                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
3079
3080                 switch (speed) {
3081                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
3082                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3083                         break;
3084                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
3085                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3086                         break;
3087                 default:
3088                         /* Internal PHY does not support anything else */
3089                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
3090                 }
3091
3092                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
3093         } else {
3094                 speed = IXGBE_LINK_SPEED_10GB_FULL |
3095                         IXGBE_LINK_SPEED_1GB_FULL;
3096                 return ixgbe_setup_kr_speed_x550em(hw, speed);
3097         }
3098 }
3099
3100 /**
3101  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
3102  *  @hw: pointer to hardware structure
3103  *
3104  *  Configures the integrated KR PHY to use internal loopback mode.
3105  **/
3106 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
3107 {
3108         s32 status;
3109         u32 reg_val;
3110
3111         /* Disable AN and force speed to 10G Serial. */
3112         status = hw->mac.ops.read_iosf_sb_reg(hw,
3113                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3114                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3115         if (status != IXGBE_SUCCESS)
3116                 return status;
3117         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3118         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3119         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3120         status = hw->mac.ops.write_iosf_sb_reg(hw,
3121                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3122                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3123         if (status != IXGBE_SUCCESS)
3124                 return status;
3125
3126         /* Set near-end loopback clocks. */
3127         status = hw->mac.ops.read_iosf_sb_reg(hw,
3128                                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3129                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3130         if (status != IXGBE_SUCCESS)
3131                 return status;
3132         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3133         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3134         status = hw->mac.ops.write_iosf_sb_reg(hw,
3135                                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3136                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3137         if (status != IXGBE_SUCCESS)
3138                 return status;
3139
3140         /* Set loopback enable. */
3141         status = hw->mac.ops.read_iosf_sb_reg(hw,
3142                                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3143                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3144         if (status != IXGBE_SUCCESS)
3145                 return status;
3146         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3147         status = hw->mac.ops.write_iosf_sb_reg(hw,
3148                                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3149                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3150         if (status != IXGBE_SUCCESS)
3151                 return status;
3152
3153         /* Training bypass. */
3154         status = hw->mac.ops.read_iosf_sb_reg(hw,
3155                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3156                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3157         if (status != IXGBE_SUCCESS)
3158                 return status;
3159         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3160         status = hw->mac.ops.write_iosf_sb_reg(hw,
3161                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3162                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3163
3164         return status;
3165 }
3166
3167 /**
3168  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3169  *  assuming that the semaphore is already obtained.
3170  *  @hw: pointer to hardware structure
3171  *  @offset: offset of  word in the EEPROM to read
3172  *  @data: word read from the EEPROM
3173  *
3174  *  Reads a 16 bit word from the EEPROM using the hostif.
3175  **/
3176 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
3177 {
3178         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3179         struct ixgbe_hic_read_shadow_ram buffer;
3180         s32 status;
3181
3182         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3183         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3184         buffer.hdr.req.buf_lenh = 0;
3185         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3186         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3187
3188         /* convert offset from words to bytes */
3189         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3190         /* one word */
3191         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3192
3193         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3194         if (status)
3195                 return status;
3196
3197         status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3198                                     IXGBE_HI_COMMAND_TIMEOUT);
3199         if (!status) {
3200                 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3201                                                   FW_NVM_DATA_OFFSET);
3202         }
3203
3204         hw->mac.ops.release_swfw_sync(hw, mask);
3205         return status;
3206 }
3207
3208 /**
3209  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3210  *  @hw: pointer to hardware structure
3211  *  @offset: offset of  word in the EEPROM to read
3212  *  @words: number of words
3213  *  @data: word(s) read from the EEPROM
3214  *
3215  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
3216  **/
3217 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3218                                      u16 offset, u16 words, u16 *data)
3219 {
3220         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3221         struct ixgbe_hic_read_shadow_ram buffer;
3222         u32 current_word = 0;
3223         u16 words_to_read;
3224         s32 status;
3225         u32 i;
3226
3227         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3228
3229         /* Take semaphore for the entire operation. */
3230         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3231         if (status) {
3232                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3233                 return status;
3234         }
3235
3236         while (words) {
3237                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3238                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3239                 else
3240                         words_to_read = words;
3241
3242                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3243                 buffer.hdr.req.buf_lenh = 0;
3244                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3245                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3246
3247                 /* convert offset from words to bytes */
3248                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3249                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3250
3251                 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3252                                             IXGBE_HI_COMMAND_TIMEOUT);
3253
3254                 if (status) {
3255                         DEBUGOUT("Host interface command failed\n");
3256                         goto out;
3257                 }
3258
3259                 for (i = 0; i < words_to_read; i++) {
3260                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3261                                   2 * i;
3262                         u32 value = IXGBE_READ_REG(hw, reg);
3263
3264                         data[current_word] = (u16)(value & 0xffff);
3265                         current_word++;
3266                         i++;
3267                         if (i < words_to_read) {
3268                                 value >>= 16;
3269                                 data[current_word] = (u16)(value & 0xffff);
3270                                 current_word++;
3271                         }
3272                 }
3273                 words -= words_to_read;
3274         }
3275
3276 out:
3277         hw->mac.ops.release_swfw_sync(hw, mask);
3278         return status;
3279 }
3280
3281 /**
3282  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3283  *  @hw: pointer to hardware structure
3284  *  @offset: offset of  word in the EEPROM to write
3285  *  @data: word write to the EEPROM
3286  *
3287  *  Write a 16 bit word to the EEPROM using the hostif.
3288  **/
3289 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3290                                     u16 data)
3291 {
3292         s32 status;
3293         struct ixgbe_hic_write_shadow_ram buffer;
3294
3295         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3296
3297         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3298         buffer.hdr.req.buf_lenh = 0;
3299         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3300         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3301
3302          /* one word */
3303         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3304         buffer.data = data;
3305         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3306
3307         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3308                                               sizeof(buffer),
3309                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3310
3311         return status;
3312 }
3313
3314 /**
3315  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3316  *  @hw: pointer to hardware structure
3317  *  @offset: offset of  word in the EEPROM to write
3318  *  @data: word write to the EEPROM
3319  *
3320  *  Write a 16 bit word to the EEPROM using the hostif.
3321  **/
3322 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3323                                u16 data)
3324 {
3325         s32 status = IXGBE_SUCCESS;
3326
3327         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3328
3329         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3330             IXGBE_SUCCESS) {
3331                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3332                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3333         } else {
3334                 DEBUGOUT("write ee hostif failed to get semaphore");
3335                 status = IXGBE_ERR_SWFW_SYNC;
3336         }
3337
3338         return status;
3339 }
3340
3341 /**
3342  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3343  *  @hw: pointer to hardware structure
3344  *  @offset: offset of  word in the EEPROM to write
3345  *  @words: number of words
3346  *  @data: word(s) write to the EEPROM
3347  *
3348  *  Write a 16 bit word(s) to the EEPROM using the hostif.
3349  **/
3350 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3351                                       u16 offset, u16 words, u16 *data)
3352 {
3353         s32 status = IXGBE_SUCCESS;
3354         u32 i = 0;
3355
3356         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3357
3358         /* Take semaphore for the entire operation. */
3359         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3360         if (status != IXGBE_SUCCESS) {
3361                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3362                 goto out;
3363         }
3364
3365         for (i = 0; i < words; i++) {
3366                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3367                                                          data[i]);
3368
3369                 if (status != IXGBE_SUCCESS) {
3370                         DEBUGOUT("Eeprom buffered write failed\n");
3371                         break;
3372                 }
3373         }
3374
3375         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3376 out:
3377
3378         return status;
3379 }
3380
3381 /**
3382  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3383  * @hw: pointer to hardware structure
3384  * @ptr: pointer offset in eeprom
3385  * @size: size of section pointed by ptr, if 0 first word will be used as size
3386  * @csum: address of checksum to update
3387  *
3388  * Returns error status for any failure
3389  */
3390 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3391                                    u16 size, u16 *csum, u16 *buffer,
3392                                    u32 buffer_size)
3393 {
3394         u16 buf[256];
3395         s32 status;
3396         u16 length, bufsz, i, start;
3397         u16 *local_buffer;
3398
3399         bufsz = sizeof(buf) / sizeof(buf[0]);
3400
3401         /* Read a chunk at the pointer location */
3402         if (!buffer) {
3403                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3404                 if (status) {
3405                         DEBUGOUT("Failed to read EEPROM image\n");
3406                         return status;
3407                 }
3408                 local_buffer = buf;
3409         } else {
3410                 if (buffer_size < ptr)
3411                         return  IXGBE_ERR_PARAM;
3412                 local_buffer = &buffer[ptr];
3413         }
3414
3415         if (size) {
3416                 start = 0;
3417                 length = size;
3418         } else {
3419                 start = 1;
3420                 length = local_buffer[0];
3421
3422                 /* Skip pointer section if length is invalid. */
3423                 if (length == 0xFFFF || length == 0 ||
3424                     (ptr + length) >= hw->eeprom.word_size)
3425                         return IXGBE_SUCCESS;
3426         }
3427
3428         if (buffer && ((u32)start + (u32)length > buffer_size))
3429                 return IXGBE_ERR_PARAM;
3430
3431         for (i = start; length; i++, length--) {
3432                 if (i == bufsz && !buffer) {
3433                         ptr += bufsz;
3434                         i = 0;
3435                         if (length < bufsz)
3436                                 bufsz = length;
3437
3438                         /* Read a chunk at the pointer location */
3439                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3440                                                                   bufsz, buf);
3441                         if (status) {
3442                                 DEBUGOUT("Failed to read EEPROM image\n");
3443                                 return status;
3444                         }
3445                 }
3446                 *csum += local_buffer[i];
3447         }
3448         return IXGBE_SUCCESS;
3449 }
3450
3451 /**
3452  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3453  *  @hw: pointer to hardware structure
3454  *  @buffer: pointer to buffer containing calculated checksum
3455  *  @buffer_size: size of buffer
3456  *
3457  *  Returns a negative error code on error, or the 16-bit checksum
3458  **/
3459 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3460 {
3461         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3462         u16 *local_buffer;
3463         s32 status;
3464         u16 checksum = 0;
3465         u16 pointer, i, size;
3466
3467         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3468
3469         hw->eeprom.ops.init_params(hw);
3470
3471         if (!buffer) {
3472                 /* Read pointer area */
3473                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3474                                                      IXGBE_EEPROM_LAST_WORD + 1,
3475                                                      eeprom_ptrs);
3476                 if (status) {
3477                         DEBUGOUT("Failed to read EEPROM image\n");
3478                         return status;
3479                 }
3480                 local_buffer = eeprom_ptrs;
3481         } else {
3482                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3483                         return IXGBE_ERR_PARAM;
3484                 local_buffer = buffer;
3485         }
3486
3487         /*
3488          * For X550 hardware include 0x0-0x41 in the checksum, skip the
3489          * checksum word itself
3490          */
3491         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3492                 if (i != IXGBE_EEPROM_CHECKSUM)
3493                         checksum += local_buffer[i];
3494
3495         /*
3496          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
3497          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3498          */
3499         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3500                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3501                         continue;
3502
3503                 pointer = local_buffer[i];
3504
3505                 /* Skip pointer section if the pointer is invalid. */
3506                 if (pointer == 0xFFFF || pointer == 0 ||
3507                     pointer >= hw->eeprom.word_size)
3508                         continue;
3509
3510                 switch (i) {
3511                 case IXGBE_PCIE_GENERAL_PTR:
3512                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3513                         break;
3514                 case IXGBE_PCIE_CONFIG0_PTR:
3515                 case IXGBE_PCIE_CONFIG1_PTR:
3516                         size = IXGBE_PCIE_CONFIG_SIZE;
3517                         break;
3518                 default:
3519                         size = 0;
3520                         break;
3521                 }
3522
3523                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3524                                                 buffer, buffer_size);
3525                 if (status)
3526                         return status;
3527         }
3528
3529         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3530
3531         return (s32)checksum;
3532 }
3533
3534 /**
3535  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3536  *  @hw: pointer to hardware structure
3537  *
3538  *  Returns a negative error code on error, or the 16-bit checksum
3539  **/
3540 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3541 {
3542         return ixgbe_calc_checksum_X550(hw, NULL, 0);
3543 }
3544
3545 /**
3546  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3547  *  @hw: pointer to hardware structure
3548  *  @checksum_val: calculated checksum
3549  *
3550  *  Performs checksum calculation and validates the EEPROM checksum.  If the
3551  *  caller does not need checksum_val, the value can be NULL.
3552  **/
3553 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3554 {
3555         s32 status;
3556         u16 checksum;
3557         u16 read_checksum = 0;
3558
3559         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3560
3561         /* Read the first word from the EEPROM. If this times out or fails, do
3562          * not continue or we could be in for a very long wait while every
3563          * EEPROM read fails
3564          */
3565         status = hw->eeprom.ops.read(hw, 0, &checksum);
3566         if (status) {
3567                 DEBUGOUT("EEPROM read failed\n");
3568                 return status;
3569         }
3570
3571         status = hw->eeprom.ops.calc_checksum(hw);
3572         if (status < 0)
3573                 return status;
3574
3575         checksum = (u16)(status & 0xffff);
3576
3577         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3578                                            &read_checksum);
3579         if (status)
3580                 return status;
3581
3582         /* Verify read checksum from EEPROM is the same as
3583          * calculated checksum
3584          */
3585         if (read_checksum != checksum) {
3586                 status = IXGBE_ERR_EEPROM_CHECKSUM;
3587                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3588                              "Invalid EEPROM checksum");
3589         }
3590
3591         /* If the user cares, return the calculated checksum */
3592         if (checksum_val)
3593                 *checksum_val = checksum;
3594
3595         return status;
3596 }
3597
3598 /**
3599  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3600  * @hw: pointer to hardware structure
3601  *
3602  * After writing EEPROM to shadow RAM using EEWR register, software calculates
3603  * checksum and updates the EEPROM and instructs the hardware to update
3604  * the flash.
3605  **/
3606 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3607 {
3608         s32 status;
3609         u16 checksum = 0;
3610
3611         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3612
3613         /* Read the first word from the EEPROM. If this times out or fails, do
3614          * not continue or we could be in for a very long wait while every
3615          * EEPROM read fails
3616          */
3617         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3618         if (status) {
3619                 DEBUGOUT("EEPROM read failed\n");
3620                 return status;
3621         }
3622
3623         status = ixgbe_calc_eeprom_checksum_X550(hw);
3624         if (status < 0)
3625                 return status;
3626
3627         checksum = (u16)(status & 0xffff);
3628
3629         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3630                                             checksum);
3631         if (status)
3632                 return status;
3633
3634         status = ixgbe_update_flash_X550(hw);
3635
3636         return status;
3637 }
3638
3639 /**
3640  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3641  *  @hw: pointer to hardware structure
3642  *
3643  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3644  **/
3645 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3646 {
3647         s32 status = IXGBE_SUCCESS;
3648         union ixgbe_hic_hdr2 buffer;
3649
3650         DEBUGFUNC("ixgbe_update_flash_X550");
3651
3652         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3653         buffer.req.buf_lenh = 0;
3654         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3655         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3656
3657         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3658                                               sizeof(buffer),
3659                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3660
3661         return status;
3662 }
3663
3664 /**
3665  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3666  *  @hw: pointer to hardware structure
3667  *
3668  *  Determines physical layer capabilities of the current configuration.
3669  **/
3670 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3671 {
3672         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3673         u16 ext_ability = 0;
3674
3675         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3676
3677         hw->phy.ops.identify(hw);
3678
3679         switch (hw->phy.type) {
3680         case ixgbe_phy_x550em_kr:
3681         case ixgbe_phy_x550em_xfi:
3682                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3683                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3684                 break;
3685         case ixgbe_phy_x550em_kx4:
3686                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3687                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3688                 break;
3689         case ixgbe_phy_x550em_ext_t:
3690                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3691                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3692                                      &ext_ability);
3693                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3694                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3695                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3696                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3697                 break;
3698         case ixgbe_phy_fw:
3699                 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_1GB_FULL)
3700                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3701                 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_100_FULL)
3702                         physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
3703                 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_10_FULL)
3704                         physical_layer |= IXGBE_PHYSICAL_LAYER_10BASE_T;
3705                 break;
3706         case ixgbe_phy_sgmii:
3707                 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3708                 break;
3709         default:
3710                 break;
3711         }
3712
3713         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3714                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3715
3716         return physical_layer;
3717 }
3718
3719 /**
3720  * ixgbe_get_bus_info_x550em - Set PCI bus info
3721  * @hw: pointer to hardware structure
3722  *
3723  * Sets bus link width and speed to unknown because X550em is
3724  * not a PCI device.
3725  **/
3726 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3727 {
3728
3729         DEBUGFUNC("ixgbe_get_bus_info_x550em");
3730
3731         hw->bus.width = ixgbe_bus_width_unknown;
3732         hw->bus.speed = ixgbe_bus_speed_unknown;
3733
3734         hw->mac.ops.set_lan_id(hw);
3735
3736         return IXGBE_SUCCESS;
3737 }
3738
3739 /**
3740  * ixgbe_disable_rx_x550 - Disable RX unit
3741  *
3742  * Enables the Rx DMA unit for x550
3743  **/
3744 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3745 {
3746         u32 rxctrl, pfdtxgswc;
3747         s32 status;
3748         struct ixgbe_hic_disable_rxen fw_cmd;
3749
3750         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3751
3752         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3753         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3754                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3755                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3756                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3757                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3758                         hw->mac.set_lben = true;
3759                 } else {
3760                         hw->mac.set_lben = false;
3761                 }
3762
3763                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3764                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3765                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3766                 fw_cmd.port_number = (u8)hw->bus.lan_id;
3767
3768                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3769                                         sizeof(struct ixgbe_hic_disable_rxen),
3770                                         IXGBE_HI_COMMAND_TIMEOUT, true);
3771
3772                 /* If we fail - disable RX using register write */
3773                 if (status) {
3774                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3775                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3776                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3777                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3778                         }
3779                 }
3780         }
3781 }
3782
3783 /**
3784  * ixgbe_enter_lplu_x550em - Transition to low power states
3785  *  @hw: pointer to hardware structure
3786  *
3787  * Configures Low Power Link Up on transition to low power states
3788  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3789  * X557 PHY immediately prior to entering LPLU.
3790  **/
3791 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3792 {
3793         u16 an_10g_cntl_reg, autoneg_reg, speed;
3794         s32 status;
3795         ixgbe_link_speed lcd_speed;
3796         u32 save_autoneg;
3797         bool link_up;
3798
3799         /* SW LPLU not required on later HW revisions. */
3800         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3801             (IXGBE_FUSES0_REV_MASK &
3802              IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3803                 return IXGBE_SUCCESS;
3804
3805         /* If blocked by MNG FW, then don't restart AN */
3806         if (ixgbe_check_reset_blocked(hw))
3807                 return IXGBE_SUCCESS;
3808
3809         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3810         if (status != IXGBE_SUCCESS)
3811                 return status;
3812
3813         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3814
3815         if (status != IXGBE_SUCCESS)
3816                 return status;
3817
3818         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3819          * disabled, then force link down by entering low power mode.
3820          */
3821         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3822             !(hw->wol_enabled || ixgbe_mng_present(hw)))
3823                 return ixgbe_set_copper_phy_power(hw, FALSE);
3824
3825         /* Determine LCD */
3826         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3827
3828         if (status != IXGBE_SUCCESS)
3829                 return status;
3830
3831         /* If no valid LCD link speed, then force link down and exit. */
3832         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3833                 return ixgbe_set_copper_phy_power(hw, FALSE);
3834
3835         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3836                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3837                                       &speed);
3838
3839         if (status != IXGBE_SUCCESS)
3840                 return status;
3841
3842         /* If no link now, speed is invalid so take link down */
3843         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3844         if (status != IXGBE_SUCCESS)
3845                 return ixgbe_set_copper_phy_power(hw, false);
3846
3847         /* clear everything but the speed bits */
3848         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3849
3850         /* If current speed is already LCD, then exit. */
3851         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3852              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3853             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3854              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3855                 return status;
3856
3857         /* Clear AN completed indication */
3858         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3859                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3860                                       &autoneg_reg);
3861
3862         if (status != IXGBE_SUCCESS)
3863                 return status;
3864
3865         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3866                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3867                              &an_10g_cntl_reg);
3868
3869         if (status != IXGBE_SUCCESS)
3870                 return status;
3871
3872         status = hw->phy.ops.read_reg(hw,
3873                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3874                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3875                              &autoneg_reg);
3876
3877         if (status != IXGBE_SUCCESS)
3878                 return status;
3879
3880         save_autoneg = hw->phy.autoneg_advertised;
3881
3882         /* Setup link at least common link speed */
3883         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3884
3885         /* restore autoneg from before setting lplu speed */
3886         hw->phy.autoneg_advertised = save_autoneg;
3887
3888         return status;
3889 }
3890
3891 /**
3892  * ixgbe_get_lcd_x550em - Determine lowest common denominator
3893  *  @hw: pointer to hardware structure
3894  *  @lcd_speed: pointer to lowest common link speed
3895  *
3896  * Determine lowest common link speed with link partner.
3897  **/
3898 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3899 {
3900         u16 an_lp_status;
3901         s32 status;
3902         u16 word = hw->eeprom.ctrl_word_3;
3903
3904         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3905
3906         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3907                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3908                                       &an_lp_status);
3909
3910         if (status != IXGBE_SUCCESS)
3911                 return status;
3912
3913         /* If link partner advertised 1G, return 1G */
3914         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3915                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3916                 return status;
3917         }
3918
3919         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3920         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3921             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3922                 return status;
3923
3924         /* Link partner not capable of lower speeds, return 10G */
3925         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3926         return status;
3927 }
3928
3929 /**
3930  *  ixgbe_setup_fc_X550em - Set up flow control
3931  *  @hw: pointer to hardware structure
3932  *
3933  *  Called at init time to set up flow control.
3934  **/
3935 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3936 {
3937         s32 ret_val = IXGBE_SUCCESS;
3938         u32 pause, asm_dir, reg_val;
3939
3940         DEBUGFUNC("ixgbe_setup_fc_X550em");
3941
3942         /* Validate the requested mode */
3943         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3944                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3945                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3946                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3947                 goto out;
3948         }
3949
3950         /* 10gig parts do not have a word in the EEPROM to determine the
3951          * default flow control setting, so we explicitly set it to full.
3952          */
3953         if (hw->fc.requested_mode == ixgbe_fc_default)
3954                 hw->fc.requested_mode = ixgbe_fc_full;
3955
3956         /* Determine PAUSE and ASM_DIR bits. */
3957         switch (hw->fc.requested_mode) {
3958         case ixgbe_fc_none:
3959                 pause = 0;
3960                 asm_dir = 0;
3961                 break;
3962         case ixgbe_fc_tx_pause:
3963                 pause = 0;
3964                 asm_dir = 1;
3965                 break;
3966         case ixgbe_fc_rx_pause:
3967                 /* Rx Flow control is enabled and Tx Flow control is
3968                  * disabled by software override. Since there really
3969                  * isn't a way to advertise that we are capable of RX
3970                  * Pause ONLY, we will advertise that we support both
3971                  * symmetric and asymmetric Rx PAUSE, as such we fall
3972                  * through to the fc_full statement.  Later, we will
3973                  * disable the adapter's ability to send PAUSE frames.
3974                  */
3975         case ixgbe_fc_full:
3976                 pause = 1;
3977                 asm_dir = 1;
3978                 break;
3979         default:
3980                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3981                         "Flow control param set incorrectly\n");
3982                 ret_val = IXGBE_ERR_CONFIG;
3983                 goto out;
3984         }
3985
3986         switch (hw->device_id) {
3987         case IXGBE_DEV_ID_X550EM_X_KR:
3988         case IXGBE_DEV_ID_X550EM_A_KR:
3989         case IXGBE_DEV_ID_X550EM_A_KR_L:
3990                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
3991                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3992                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3993                 if (ret_val != IXGBE_SUCCESS)
3994                         goto out;
3995                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3996                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3997                 if (pause)
3998                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3999                 if (asm_dir)
4000                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4001                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
4002                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4003                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
4004
4005                 /* This device does not fully support AN. */
4006                 hw->fc.disable_fc_autoneg = true;
4007                 break;
4008         default:
4009                 break;
4010         }
4011
4012 out:
4013         return ret_val;
4014 }
4015
4016 /**
4017  *  ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
4018  *  @hw: pointer to hardware structure
4019  *
4020  *  Enable flow control according to IEEE clause 37.
4021  **/
4022 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
4023 {
4024         u32 link_s1, lp_an_page_low, an_cntl_1;
4025         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4026         ixgbe_link_speed speed;
4027         bool link_up;
4028
4029         /* AN should have completed when the cable was plugged in.
4030          * Look for reasons to bail out.  Bail out if:
4031          * - FC autoneg is disabled, or if
4032          * - link is not up.
4033          */
4034         if (hw->fc.disable_fc_autoneg) {
4035                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4036                              "Flow control autoneg is disabled");
4037                 goto out;
4038         }
4039
4040         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4041         if (!link_up) {
4042                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4043                 goto out;
4044         }
4045
4046         /* Check at auto-negotiation has completed */
4047         status = hw->mac.ops.read_iosf_sb_reg(hw,
4048                                         IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4049                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4050
4051         if (status != IXGBE_SUCCESS ||
4052             (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4053                 DEBUGOUT("Auto-Negotiation did not complete\n");
4054                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4055                 goto out;
4056         }
4057
4058         /* Read the 10g AN autoc and LP ability registers and resolve
4059          * local flow control settings accordingly
4060          */
4061         status = hw->mac.ops.read_iosf_sb_reg(hw,
4062                                 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4063                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
4064
4065         if (status != IXGBE_SUCCESS) {
4066                 DEBUGOUT("Auto-Negotiation did not complete\n");
4067                 goto out;
4068         }
4069
4070         status = hw->mac.ops.read_iosf_sb_reg(hw,
4071                                 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
4072                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
4073
4074         if (status != IXGBE_SUCCESS) {
4075                 DEBUGOUT("Auto-Negotiation did not complete\n");
4076                 goto out;
4077         }
4078
4079         status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
4080                                     IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
4081                                     IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
4082                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
4083                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
4084
4085 out:
4086         if (status == IXGBE_SUCCESS) {
4087                 hw->fc.fc_was_autonegged = true;
4088         } else {
4089                 hw->fc.fc_was_autonegged = false;
4090                 hw->fc.current_mode = hw->fc.requested_mode;
4091         }
4092 }
4093
4094 /**
4095  *  ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
4096  *  @hw: pointer to hardware structure
4097  *
4098  **/
4099 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
4100 {
4101         hw->fc.fc_was_autonegged = false;
4102         hw->fc.current_mode = hw->fc.requested_mode;
4103 }
4104
4105 /**
4106  *  ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
4107  *  @hw: pointer to hardware structure
4108  *
4109  *  Enable flow control according to IEEE clause 37.
4110  **/
4111 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
4112 {
4113         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4114         u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
4115         ixgbe_link_speed speed;
4116         bool link_up;
4117
4118         /* AN should have completed when the cable was plugged in.
4119          * Look for reasons to bail out.  Bail out if:
4120          * - FC autoneg is disabled, or if
4121          * - link is not up.
4122          */
4123         if (hw->fc.disable_fc_autoneg) {
4124                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4125                              "Flow control autoneg is disabled");
4126                 goto out;
4127         }
4128
4129         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4130         if (!link_up) {
4131                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4132                 goto out;
4133         }
4134
4135         /* Check if auto-negotiation has completed */
4136         status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info);
4137         if (status != IXGBE_SUCCESS ||
4138             !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) {
4139                 DEBUGOUT("Auto-Negotiation did not complete\n");
4140                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4141                 goto out;
4142         }
4143
4144         /* Negotiate the flow control */
4145         status = ixgbe_negotiate_fc(hw, info[0], info[0],
4146                                     FW_PHY_ACT_GET_LINK_INFO_FC_RX,
4147                                     FW_PHY_ACT_GET_LINK_INFO_FC_TX,
4148                                     FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX,
4149                                     FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX);
4150
4151 out:
4152         if (status == IXGBE_SUCCESS) {
4153                 hw->fc.fc_was_autonegged = true;
4154         } else {
4155                 hw->fc.fc_was_autonegged = false;
4156                 hw->fc.current_mode = hw->fc.requested_mode;
4157         }
4158 }
4159
4160 /**
4161  *  ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4162  *  @hw: pointer to hardware structure
4163  *
4164  *  Called at init time to set up flow control.
4165  **/
4166 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4167 {
4168         s32 status = IXGBE_SUCCESS;
4169         u32 an_cntl = 0;
4170
4171         DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4172
4173         /* Validate the requested mode */
4174         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4175                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4176                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4177                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4178         }
4179
4180         if (hw->fc.requested_mode == ixgbe_fc_default)
4181                 hw->fc.requested_mode = ixgbe_fc_full;
4182
4183         /* Set up the 1G and 10G flow control advertisement registers so the
4184          * HW will be able to do FC autoneg once the cable is plugged in.  If
4185          * we link at 10G, the 1G advertisement is harmless and vice versa.
4186          */
4187         status = hw->mac.ops.read_iosf_sb_reg(hw,
4188                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4189                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4190
4191         if (status != IXGBE_SUCCESS) {
4192                 DEBUGOUT("Auto-Negotiation did not complete\n");
4193                 return status;
4194         }
4195
4196         /* The possible values of fc.requested_mode are:
4197          * 0: Flow control is completely disabled
4198          * 1: Rx flow control is enabled (we can receive pause frames,
4199          *    but not send pause frames).
4200          * 2: Tx flow control is enabled (we can send pause frames but
4201          *    we do not support receiving pause frames).
4202          * 3: Both Rx and Tx flow control (symmetric) are enabled.
4203          * other: Invalid.
4204          */
4205         switch (hw->fc.requested_mode) {
4206         case ixgbe_fc_none:
4207                 /* Flow control completely disabled by software override. */
4208                 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4209                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4210                 break;
4211         case ixgbe_fc_tx_pause:
4212                 /* Tx Flow control is enabled, and Rx Flow control is
4213                  * disabled by software override.
4214                  */
4215                 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4216                 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4217                 break;
4218         case ixgbe_fc_rx_pause:
4219                 /* Rx Flow control is enabled and Tx Flow control is
4220                  * disabled by software override. Since there really
4221                  * isn't a way to advertise that we are capable of RX
4222                  * Pause ONLY, we will advertise that we support both
4223                  * symmetric and asymmetric Rx PAUSE, as such we fall
4224                  * through to the fc_full statement.  Later, we will
4225                  * disable the adapter's ability to send PAUSE frames.
4226                  */
4227         case ixgbe_fc_full:
4228                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4229                 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4230                            IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4231                 break;
4232         default:
4233                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4234                               "Flow control param set incorrectly\n");
4235                 return IXGBE_ERR_CONFIG;
4236         }
4237
4238         status = hw->mac.ops.write_iosf_sb_reg(hw,
4239                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4240                                         IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4241
4242         /* Restart auto-negotiation. */
4243         status = ixgbe_restart_an_internal_phy_x550em(hw);
4244
4245         return status;
4246 }
4247
4248 /**
4249  * ixgbe_set_mux - Set mux for port 1 access with CS4227
4250  * @hw: pointer to hardware structure
4251  * @state: set mux if 1, clear if 0
4252  */
4253 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4254 {
4255         u32 esdp;
4256
4257         if (!hw->bus.lan_id)
4258                 return;
4259         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4260         if (state)
4261                 esdp |= IXGBE_ESDP_SDP1;
4262         else
4263                 esdp &= ~IXGBE_ESDP_SDP1;
4264         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4265         IXGBE_WRITE_FLUSH(hw);
4266 }
4267
4268 /**
4269  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4270  *  @hw: pointer to hardware structure
4271  *  @mask: Mask to specify which semaphore to acquire
4272  *
4273  *  Acquires the SWFW semaphore and sets the I2C MUX
4274  **/
4275 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4276 {
4277         s32 status;
4278
4279         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4280
4281         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4282         if (status)
4283                 return status;
4284
4285         if (mask & IXGBE_GSSR_I2C_MASK)
4286                 ixgbe_set_mux(hw, 1);
4287
4288         return IXGBE_SUCCESS;
4289 }
4290
4291 /**
4292  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4293  *  @hw: pointer to hardware structure
4294  *  @mask: Mask to specify which semaphore to release
4295  *
4296  *  Releases the SWFW semaphore and sets the I2C MUX
4297  **/
4298 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4299 {
4300         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4301
4302         if (mask & IXGBE_GSSR_I2C_MASK)
4303                 ixgbe_set_mux(hw, 0);
4304
4305         ixgbe_release_swfw_sync_X540(hw, mask);
4306 }
4307
4308 /**
4309  *  ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4310  *  @hw: pointer to hardware structure
4311  *  @mask: Mask to specify which semaphore to acquire
4312  *
4313  *  Acquires the SWFW semaphore and get the shared phy token as needed
4314  */
4315 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4316 {
4317         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4318         int retries = FW_PHY_TOKEN_RETRIES;
4319         s32 status = IXGBE_SUCCESS;
4320
4321         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4322
4323         while (--retries) {
4324                 status = IXGBE_SUCCESS;
4325                 if (hmask)
4326                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4327                 if (status)
4328                         return status;
4329                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4330                         return IXGBE_SUCCESS;
4331
4332                 status = ixgbe_get_phy_token(hw);
4333                 if (status == IXGBE_SUCCESS)
4334                         return IXGBE_SUCCESS;
4335
4336                 if (hmask)
4337                         ixgbe_release_swfw_sync_X540(hw, hmask);
4338                 if (status != IXGBE_ERR_TOKEN_RETRY)
4339                         return status;
4340         }
4341
4342         return status;
4343 }
4344
4345 /**
4346  *  ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4347  *  @hw: pointer to hardware structure
4348  *  @mask: Mask to specify which semaphore to release
4349  *
4350  *  Releases the SWFW semaphore and puts the shared phy token as needed
4351  */
4352 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4353 {
4354         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4355
4356         DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4357
4358         if (mask & IXGBE_GSSR_TOKEN_SM)
4359                 ixgbe_put_phy_token(hw);
4360
4361         if (hmask)
4362                 ixgbe_release_swfw_sync_X540(hw, hmask);
4363 }
4364
4365 /**
4366  *  ixgbe_read_phy_reg_x550a  - Reads specified PHY register
4367  *  @hw: pointer to hardware structure
4368  *  @reg_addr: 32 bit address of PHY register to read
4369  *  @phy_data: Pointer to read data from PHY register
4370  *
4371  *  Reads a value from a specified PHY register using the SWFW lock and PHY
4372  *  Token. The PHY Token is needed since the MDIO is shared between to MAC
4373  *  instances.
4374  **/
4375 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4376                                u32 device_type, u16 *phy_data)
4377 {
4378         s32 status;
4379         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4380
4381         DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4382
4383         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4384                 return IXGBE_ERR_SWFW_SYNC;
4385
4386         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4387
4388         hw->mac.ops.release_swfw_sync(hw, mask);
4389
4390         return status;
4391 }
4392
4393 /**
4394  *  ixgbe_write_phy_reg_x550a - Writes specified PHY register
4395  *  @hw: pointer to hardware structure
4396  *  @reg_addr: 32 bit PHY register to write
4397  *  @device_type: 5 bit device type
4398  *  @phy_data: Data to write to the PHY register
4399  *
4400  *  Writes a value to specified PHY register using the SWFW lock and PHY Token.
4401  *  The PHY Token is needed since the MDIO is shared between to MAC instances.
4402  **/
4403 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4404                                 u32 device_type, u16 phy_data)
4405 {
4406         s32 status;
4407         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4408
4409         DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4410
4411         if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4412                 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
4413                                                  phy_data);
4414                 hw->mac.ops.release_swfw_sync(hw, mask);
4415         } else {
4416                 status = IXGBE_ERR_SWFW_SYNC;
4417         }
4418
4419         return status;
4420 }
4421
4422 /**
4423  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4424  * @hw: pointer to hardware structure
4425  *
4426  * Handle external Base T PHY interrupt. If high temperature
4427  * failure alarm then return error, else if link status change
4428  * then setup internal/external PHY link
4429  *
4430  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4431  * failure alarm, else return PHY access status.
4432  */
4433 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4434 {
4435         bool lsc;
4436         u32 status;
4437
4438         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4439
4440         if (status != IXGBE_SUCCESS)
4441                 return status;
4442
4443         if (lsc)
4444                 return ixgbe_setup_internal_phy(hw);
4445
4446         return IXGBE_SUCCESS;
4447 }
4448
4449 /**
4450  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4451  * @hw: pointer to hardware structure
4452  * @speed: new link speed
4453  * @autoneg_wait_to_complete: true when waiting for completion is needed
4454  *
4455  * Setup internal/external PHY link speed based on link speed, then set
4456  * external PHY auto advertised link speed.
4457  *
4458  * Returns error status for any failure
4459  **/
4460 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4461                                   ixgbe_link_speed speed,
4462                                   bool autoneg_wait_to_complete)
4463 {
4464         s32 status;
4465         ixgbe_link_speed force_speed;
4466
4467         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4468
4469         /* Setup internal/external PHY link speed to iXFI (10G), unless
4470          * only 1G is auto advertised then setup KX link.
4471          */
4472         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4473                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4474         else
4475                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4476
4477         /* If X552 and internal link mode is XFI, then setup XFI internal link.
4478          */
4479         if (hw->mac.type == ixgbe_mac_X550EM_x &&
4480             !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4481                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4482
4483                 if (status != IXGBE_SUCCESS)
4484                         return status;
4485         }
4486
4487         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4488 }
4489
4490 /**
4491  * ixgbe_check_link_t_X550em - Determine link and speed status
4492  * @hw: pointer to hardware structure
4493  * @speed: pointer to link speed
4494  * @link_up: true when link is up
4495  * @link_up_wait_to_complete: bool used to wait for link up or not
4496  *
4497  * Check that both the MAC and X557 external PHY have link.
4498  **/
4499 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4500                               bool *link_up, bool link_up_wait_to_complete)
4501 {
4502         u32 status;
4503         u16 i, autoneg_status = 0;
4504
4505         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4506                 return IXGBE_ERR_CONFIG;
4507
4508         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4509                                               link_up_wait_to_complete);
4510
4511         /* If check link fails or MAC link is not up, then return */
4512         if (status != IXGBE_SUCCESS || !(*link_up))
4513                 return status;
4514
4515         /* MAC link is up, so check external PHY link.
4516          * X557 PHY. Link status is latching low, and can only be used to detect
4517          * link drop, and not the current status of the link without performing
4518          * back-to-back reads.
4519          */
4520         for (i = 0; i < 2; i++) {
4521                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4522                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4523                                               &autoneg_status);
4524
4525                 if (status != IXGBE_SUCCESS)
4526                         return status;
4527         }
4528
4529         /* If external PHY link is not up, then indicate link not up */
4530         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4531                 *link_up = false;
4532
4533         return IXGBE_SUCCESS;
4534 }
4535
4536 /**
4537  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4538  *  @hw: pointer to hardware structure
4539  **/
4540 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4541 {
4542         s32 status;
4543
4544         status = ixgbe_reset_phy_generic(hw);
4545
4546         if (status != IXGBE_SUCCESS)
4547                 return status;
4548
4549         /* Configure Link Status Alarm and Temperature Threshold interrupts */
4550         return ixgbe_enable_lasi_ext_t_x550em(hw);
4551 }
4552
4553 /**
4554  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4555  *  @hw: pointer to hardware structure
4556  *  @led_idx: led number to turn on
4557  **/
4558 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4559 {
4560         u16 phy_data;
4561
4562         DEBUGFUNC("ixgbe_led_on_t_X550em");
4563
4564         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4565                 return IXGBE_ERR_PARAM;
4566
4567         /* To turn on the LED, set mode to ON. */
4568         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4569                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4570         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4571         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4572                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4573
4574         return IXGBE_SUCCESS;
4575 }
4576
4577 /**
4578  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4579  *  @hw: pointer to hardware structure
4580  *  @led_idx: led number to turn off
4581  **/
4582 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4583 {
4584         u16 phy_data;
4585
4586         DEBUGFUNC("ixgbe_led_off_t_X550em");
4587
4588         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4589                 return IXGBE_ERR_PARAM;
4590
4591         /* To turn on the LED, set mode to ON. */
4592         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4593                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4594         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4595         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4596                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4597
4598         return IXGBE_SUCCESS;
4599 }
4600
4601 /**
4602  *  ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware
4603  *  @hw: pointer to the HW structure
4604  *  @maj: driver version major number
4605  *  @min: driver version minor number
4606  *  @build: driver version build number
4607  *  @sub: driver version sub build number
4608  *  @len: length of driver_ver string
4609  *  @driver_ver: driver string
4610  *
4611  *  Sends driver version number to firmware through the manageability
4612  *  block.  On success return IXGBE_SUCCESS
4613  *  else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4614  *  semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4615  **/
4616 s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,
4617                               u8 build, u8 sub, u16 len, const char *driver_ver)
4618 {
4619         struct ixgbe_hic_drv_info2 fw_cmd;
4620         s32 ret_val = IXGBE_SUCCESS;
4621         int i;
4622
4623         DEBUGFUNC("ixgbe_set_fw_drv_ver_x550");
4624
4625         if ((len == 0) || (driver_ver == NULL) ||
4626            (len > sizeof(fw_cmd.driver_string)))
4627                 return IXGBE_ERR_INVALID_ARGUMENT;
4628
4629         fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4630         fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len;
4631         fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4632         fw_cmd.port_num = (u8)hw->bus.func;
4633         fw_cmd.ver_maj = maj;
4634         fw_cmd.ver_min = min;
4635         fw_cmd.ver_build = build;
4636         fw_cmd.ver_sub = sub;
4637         fw_cmd.hdr.checksum = 0;
4638         memcpy(fw_cmd.driver_string, driver_ver, len);
4639         fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4640                                 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4641
4642         for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4643                 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4644                                                        sizeof(fw_cmd),
4645                                                        IXGBE_HI_COMMAND_TIMEOUT,
4646                                                        true);
4647                 if (ret_val != IXGBE_SUCCESS)
4648                         continue;
4649
4650                 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4651                     FW_CEM_RESP_STATUS_SUCCESS)
4652                         ret_val = IXGBE_SUCCESS;
4653                 else
4654                         ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4655
4656                 break;
4657         }
4658
4659         return ret_val;
4660 }