1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
42 static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
43 static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
46 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
47 * @hw: pointer to hardware structure
49 * Initialize the function pointers and assign the MAC type for X550.
50 * Does not touch the hardware.
52 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
54 struct ixgbe_mac_info *mac = &hw->mac;
55 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
58 DEBUGFUNC("ixgbe_init_ops_X550");
60 ret_val = ixgbe_init_ops_X540(hw);
61 mac->ops.dmac_config = ixgbe_dmac_config_X550;
62 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
63 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
64 mac->ops.setup_eee = ixgbe_setup_eee_X550;
65 mac->ops.set_source_address_pruning =
66 ixgbe_set_source_address_pruning_X550;
67 mac->ops.set_ethertype_anti_spoofing =
68 ixgbe_set_ethertype_anti_spoofing_X550;
70 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
71 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
72 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
73 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
74 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
75 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
76 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
77 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
78 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
80 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
81 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
82 mac->ops.mdd_event = ixgbe_mdd_event_X550;
83 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
84 mac->ops.disable_rx = ixgbe_disable_rx_x550;
85 switch (hw->device_id) {
86 case IXGBE_DEV_ID_X550EM_X_10G_T:
87 case IXGBE_DEV_ID_X550EM_A_10G_T:
88 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
89 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
98 * ixgbe_read_cs4227 - Read CS4227 register
99 * @hw: pointer to hardware structure
100 * @reg: register number to write
101 * @value: pointer to receive value read
103 * Returns status code
105 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
107 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
111 * ixgbe_write_cs4227 - Write CS4227 register
112 * @hw: pointer to hardware structure
113 * @reg: register number to write
114 * @value: value to write to register
116 * Returns status code
118 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
120 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
124 * ixgbe_read_pe - Read register from port expander
125 * @hw: pointer to hardware structure
126 * @reg: register number to read
127 * @value: pointer to receive read value
129 * Returns status code
131 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
135 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
136 if (status != IXGBE_SUCCESS)
137 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
138 "port expander access failed with %d\n", status);
143 * ixgbe_write_pe - Write register to port expander
144 * @hw: pointer to hardware structure
145 * @reg: register number to write
146 * @value: value to write
148 * Returns status code
150 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
154 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
155 if (status != IXGBE_SUCCESS)
156 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
157 "port expander access failed with %d\n", status);
162 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
163 * @hw: pointer to hardware structure
165 * This function assumes that the caller has acquired the proper semaphore.
168 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
175 /* Trigger hard reset. */
176 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
177 if (status != IXGBE_SUCCESS)
179 reg |= IXGBE_PE_BIT1;
180 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
181 if (status != IXGBE_SUCCESS)
184 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
185 if (status != IXGBE_SUCCESS)
187 reg &= ~IXGBE_PE_BIT1;
188 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
189 if (status != IXGBE_SUCCESS)
192 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
193 if (status != IXGBE_SUCCESS)
195 reg &= ~IXGBE_PE_BIT1;
196 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
197 if (status != IXGBE_SUCCESS)
200 usec_delay(IXGBE_CS4227_RESET_HOLD);
202 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
203 if (status != IXGBE_SUCCESS)
205 reg |= IXGBE_PE_BIT1;
206 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
207 if (status != IXGBE_SUCCESS)
210 /* Wait for the reset to complete. */
211 msec_delay(IXGBE_CS4227_RESET_DELAY);
212 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
213 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
215 if (status == IXGBE_SUCCESS &&
216 value == IXGBE_CS4227_EEPROM_LOAD_OK)
218 msec_delay(IXGBE_CS4227_CHECK_DELAY);
220 if (retry == IXGBE_CS4227_RETRIES) {
221 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
222 "CS4227 reset did not complete.");
223 return IXGBE_ERR_PHY;
226 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
227 if (status != IXGBE_SUCCESS ||
228 !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
229 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
230 "CS4227 EEPROM did not load successfully.");
231 return IXGBE_ERR_PHY;
234 return IXGBE_SUCCESS;
238 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
239 * @hw: pointer to hardware structure
241 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
243 s32 status = IXGBE_SUCCESS;
244 u32 swfw_mask = hw->phy.phy_semaphore_mask;
248 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
249 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
250 if (status != IXGBE_SUCCESS) {
251 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
252 "semaphore failed with %d", status);
253 msec_delay(IXGBE_CS4227_CHECK_DELAY);
257 /* Get status of reset flow. */
258 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
260 if (status == IXGBE_SUCCESS &&
261 value == IXGBE_CS4227_RESET_COMPLETE)
264 if (status != IXGBE_SUCCESS ||
265 value != IXGBE_CS4227_RESET_PENDING)
268 /* Reset is pending. Wait and check again. */
269 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
270 msec_delay(IXGBE_CS4227_CHECK_DELAY);
273 /* If still pending, assume other instance failed. */
274 if (retry == IXGBE_CS4227_RETRIES) {
275 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
276 if (status != IXGBE_SUCCESS) {
277 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
278 "semaphore failed with %d", status);
283 /* Reset the CS4227. */
284 status = ixgbe_reset_cs4227(hw);
285 if (status != IXGBE_SUCCESS) {
286 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
287 "CS4227 reset failed: %d", status);
291 /* Reset takes so long, temporarily release semaphore in case the
292 * other driver instance is waiting for the reset indication.
294 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
295 IXGBE_CS4227_RESET_PENDING);
296 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
298 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
299 if (status != IXGBE_SUCCESS) {
300 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
301 "semaphore failed with %d", status);
305 /* Record completion for next time. */
306 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
307 IXGBE_CS4227_RESET_COMPLETE);
310 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
311 msec_delay(hw->eeprom.semaphore_delay);
315 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
316 * @hw: pointer to hardware structure
318 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
320 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
322 if (hw->bus.lan_id) {
323 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
324 esdp |= IXGBE_ESDP_SDP1_DIR;
326 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
327 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
328 IXGBE_WRITE_FLUSH(hw);
332 * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
333 * @hw: pointer to hardware structure
334 * @reg_addr: 32 bit address of PHY register to read
335 * @dev_type: always unused
336 * @phy_data: Pointer to read data from PHY register
338 static s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
339 u32 dev_type, u16 *phy_data)
341 u32 i, data, command;
342 UNREFERENCED_1PARAMETER(dev_type);
344 /* Setup and write the read command */
345 command = (reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
346 (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
347 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
348 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ |
349 IXGBE_MSCA_MDI_COMMAND;
351 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
353 /* Check every 10 usec to see if the access completed.
354 * The MDI Command bit will clear when the operation is
357 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
360 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
361 if (!(command & IXGBE_MSCA_MDI_COMMAND))
365 if (command & IXGBE_MSCA_MDI_COMMAND) {
366 ERROR_REPORT1(IXGBE_ERROR_POLLING,
367 "PHY read command did not complete.\n");
368 return IXGBE_ERR_PHY;
371 /* Read operation is complete. Get the data from MSRWD */
372 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
373 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
374 *phy_data = (u16)data;
376 return IXGBE_SUCCESS;
380 * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
381 * @hw: pointer to hardware structure
382 * @reg_addr: 32 bit PHY register to write
383 * @dev_type: always unused
384 * @phy_data: Data to write to the PHY register
386 static s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
387 u32 dev_type, u16 phy_data)
390 UNREFERENCED_1PARAMETER(dev_type);
392 /* Put the data in the MDI single read and write data register*/
393 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
395 /* Setup and write the write command */
396 command = (reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
397 (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
398 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
399 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
400 IXGBE_MSCA_MDI_COMMAND;
402 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
404 /* Check every 10 usec to see if the access completed.
405 * The MDI Command bit will clear when the operation is
408 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
411 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
412 if (!(command & IXGBE_MSCA_MDI_COMMAND))
416 if (command & IXGBE_MSCA_MDI_COMMAND) {
417 ERROR_REPORT1(IXGBE_ERROR_POLLING,
418 "PHY write cmd didn't complete\n");
419 return IXGBE_ERR_PHY;
422 return IXGBE_SUCCESS;
426 * ixgbe_identify_phy_1g - Get 1g PHY type based on device id
427 * @hw: pointer to hardware structure
431 static s32 ixgbe_identify_phy_1g(struct ixgbe_hw *hw)
433 u32 swfw_mask = hw->phy.phy_semaphore_mask;
438 rc = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
442 rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_MDIO_PHY_ID_HIGH, 0,
447 rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_MDIO_PHY_ID_LOW, 0,
452 hw->phy.id = (u32)phy_id_high << 16;
453 hw->phy.id |= phy_id_low & IXGBE_PHY_REVISION_MASK;
454 hw->phy.revision = (u32)phy_id_low & ~IXGBE_PHY_REVISION_MASK;
457 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
463 * ixgbe_identify_phy_x550em - Get PHY type based on device id
464 * @hw: pointer to hardware structure
468 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
470 switch (hw->device_id) {
471 case IXGBE_DEV_ID_X550EM_A_SFP:
472 hw->phy.phy_semaphore_mask = IXGBE_GSSR_TOKEN_SM;
474 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
476 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
477 return ixgbe_identify_module_generic(hw);
478 case IXGBE_DEV_ID_X550EM_X_SFP:
479 /* set up for CS4227 usage */
480 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
481 ixgbe_setup_mux_ctl(hw);
482 ixgbe_check_cs4227(hw);
485 case IXGBE_DEV_ID_X550EM_A_SFP_N:
486 return ixgbe_identify_module_generic(hw);
488 case IXGBE_DEV_ID_X550EM_X_KX4:
489 hw->phy.type = ixgbe_phy_x550em_kx4;
491 case IXGBE_DEV_ID_X550EM_X_KR:
492 case IXGBE_DEV_ID_X550EM_A_KR:
493 case IXGBE_DEV_ID_X550EM_A_KR_L:
494 hw->phy.type = ixgbe_phy_x550em_kr;
496 case IXGBE_DEV_ID_X550EM_X_1G_T:
497 case IXGBE_DEV_ID_X550EM_X_10G_T:
498 case IXGBE_DEV_ID_X550EM_A_10G_T:
499 return ixgbe_identify_phy_generic(hw);
500 case IXGBE_DEV_ID_X550EM_A_1G_T:
501 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
502 hw->phy.phy_semaphore_mask = IXGBE_GSSR_TOKEN_SM;
504 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
506 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
507 return ixgbe_identify_phy_1g(hw);
511 return IXGBE_SUCCESS;
514 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
515 u32 device_type, u16 *phy_data)
517 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
518 return IXGBE_NOT_IMPLEMENTED;
521 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
522 u32 device_type, u16 phy_data)
524 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
525 return IXGBE_NOT_IMPLEMENTED;
529 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
530 * @hw: pointer to the hardware structure
531 * @addr: I2C bus address to read from
532 * @reg: I2C device register to read from
533 * @val: pointer to location to receive read value
535 * Returns an error code on error.
537 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
540 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
544 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
545 * @hw: pointer to the hardware structure
546 * @addr: I2C bus address to read from
547 * @reg: I2C device register to read from
548 * @val: pointer to location to receive read value
550 * Returns an error code on error.
553 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
556 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
560 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
561 * @hw: pointer to the hardware structure
562 * @addr: I2C bus address to write to
563 * @reg: I2C device register to write to
564 * @val: value to write
566 * Returns an error code on error.
568 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
569 u8 addr, u16 reg, u16 val)
571 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
575 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
576 * @hw: pointer to the hardware structure
577 * @addr: I2C bus address to write to
578 * @reg: I2C device register to write to
579 * @val: value to write
581 * Returns an error code on error.
584 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
585 u8 addr, u16 reg, u16 val)
587 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
591 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
592 * @hw: pointer to hardware structure
594 * Initialize the function pointers and for MAC type X550EM.
595 * Does not touch the hardware.
597 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
599 struct ixgbe_mac_info *mac = &hw->mac;
600 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
601 struct ixgbe_phy_info *phy = &hw->phy;
602 struct ixgbe_link_info *link = &hw->link;
605 DEBUGFUNC("ixgbe_init_ops_X550EM");
607 /* Similar to X550 so start there. */
608 ret_val = ixgbe_init_ops_X550(hw);
610 /* Since this function eventually calls
611 * ixgbe_init_ops_540 by design, we are setting
612 * the pointers to NULL explicitly here to overwrite
613 * the values being set in the x540 function.
615 /* Thermal sensor not supported in x550EM */
616 mac->ops.get_thermal_sensor_data = NULL;
617 mac->ops.init_thermal_sensor_thresh = NULL;
618 mac->thermal_sensor_enabled = false;
620 /* FCOE not supported in x550EM */
621 mac->ops.get_san_mac_addr = NULL;
622 mac->ops.set_san_mac_addr = NULL;
623 mac->ops.get_wwn_prefix = NULL;
624 mac->ops.get_fcoe_boot_status = NULL;
626 /* IPsec not supported in x550EM */
627 mac->ops.disable_sec_rx_path = NULL;
628 mac->ops.enable_sec_rx_path = NULL;
630 /* AUTOC register is not present in x550EM. */
631 mac->ops.prot_autoc_read = NULL;
632 mac->ops.prot_autoc_write = NULL;
634 /* X550EM bus type is internal*/
635 hw->bus.type = ixgbe_bus_type_internal;
636 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
638 if (hw->mac.type == ixgbe_mac_X550EM_x) {
639 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
640 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
641 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
642 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
643 link->ops.read_link = ixgbe_read_i2c_combined_generic;
644 link->ops.read_link_unlocked =
645 ixgbe_read_i2c_combined_generic_unlocked;
646 link->ops.write_link = ixgbe_write_i2c_combined_generic;
647 link->ops.write_link_unlocked =
648 ixgbe_write_i2c_combined_generic_unlocked;
649 link->addr = IXGBE_CS4227;
651 if (hw->mac.type == ixgbe_mac_X550EM_a) {
652 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
653 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
654 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
655 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
658 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
659 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
660 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
661 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
662 mac->ops.get_supported_physical_layer =
663 ixgbe_get_supported_physical_layer_X550em;
665 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
666 mac->ops.setup_fc = ixgbe_setup_fc_generic;
668 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
670 switch (hw->device_id) {
671 case IXGBE_DEV_ID_X550EM_X_KR:
672 case IXGBE_DEV_ID_X550EM_A_KR:
673 case IXGBE_DEV_ID_X550EM_A_KR_L:
676 mac->ops.setup_eee = NULL;
680 phy->ops.init = ixgbe_init_phy_ops_X550em;
681 phy->ops.identify = ixgbe_identify_phy_x550em;
682 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
683 phy->ops.set_phy_power = NULL;
687 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
688 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
689 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
690 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
691 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
692 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
693 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
694 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
700 * ixgbe_dmac_config_X550
701 * @hw: pointer to hardware structure
703 * Configure DMA coalescing. If enabling dmac, dmac is activated.
704 * When disabling dmac, dmac enable dmac bit is cleared.
706 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
708 u32 reg, high_pri_tc;
710 DEBUGFUNC("ixgbe_dmac_config_X550");
712 /* Disable DMA coalescing before configuring */
713 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
714 reg &= ~IXGBE_DMACR_DMAC_EN;
715 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
717 /* Disable DMA Coalescing if the watchdog timer is 0 */
718 if (!hw->mac.dmac_config.watchdog_timer)
721 ixgbe_dmac_config_tcs_X550(hw);
723 /* Configure DMA Coalescing Control Register */
724 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
726 /* Set the watchdog timer in units of 40.96 usec */
727 reg &= ~IXGBE_DMACR_DMACWT_MASK;
728 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
730 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
731 /* If fcoe is enabled, set high priority traffic class */
732 if (hw->mac.dmac_config.fcoe_en) {
733 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
734 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
735 IXGBE_DMACR_HIGH_PRI_TC_MASK);
737 reg |= IXGBE_DMACR_EN_MNG_IND;
739 /* Enable DMA coalescing after configuration */
740 reg |= IXGBE_DMACR_DMAC_EN;
741 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
744 return IXGBE_SUCCESS;
748 * ixgbe_dmac_config_tcs_X550
749 * @hw: pointer to hardware structure
751 * Configure DMA coalescing threshold per TC. The dmac enable bit must
752 * be cleared before configuring.
754 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
756 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
758 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
760 /* Configure DMA coalescing enabled */
761 switch (hw->mac.dmac_config.link_speed) {
762 case IXGBE_LINK_SPEED_100_FULL:
763 pb_headroom = IXGBE_DMACRXT_100M;
765 case IXGBE_LINK_SPEED_1GB_FULL:
766 pb_headroom = IXGBE_DMACRXT_1G;
769 pb_headroom = IXGBE_DMACRXT_10G;
773 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
774 IXGBE_MHADD_MFS_SHIFT) / 1024);
776 /* Set the per Rx packet buffer receive threshold */
777 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
778 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
779 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
781 if (tc < hw->mac.dmac_config.num_tcs) {
783 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
784 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
785 IXGBE_RXPBSIZE_SHIFT;
787 /* Calculate receive buffer threshold in kilobytes */
788 if (rx_pb_size > pb_headroom)
789 rx_pb_size = rx_pb_size - pb_headroom;
793 /* Minimum of MFS shall be set for DMCTH */
794 reg |= (rx_pb_size > maxframe_size_kb) ?
795 rx_pb_size : maxframe_size_kb;
797 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
799 return IXGBE_SUCCESS;
803 * ixgbe_dmac_update_tcs_X550
804 * @hw: pointer to hardware structure
806 * Disables dmac, updates per TC settings, and then enables dmac.
808 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
812 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
814 /* Disable DMA coalescing before configuring */
815 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
816 reg &= ~IXGBE_DMACR_DMAC_EN;
817 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
819 ixgbe_dmac_config_tcs_X550(hw);
821 /* Enable DMA coalescing after configuration */
822 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
823 reg |= IXGBE_DMACR_DMAC_EN;
824 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
826 return IXGBE_SUCCESS;
830 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
831 * @hw: pointer to hardware structure
833 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
834 * ixgbe_hw struct in order to set up EEPROM access.
836 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
838 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
842 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
844 if (eeprom->type == ixgbe_eeprom_uninitialized) {
845 eeprom->semaphore_delay = 10;
846 eeprom->type = ixgbe_flash;
848 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
849 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
850 IXGBE_EEC_SIZE_SHIFT);
851 eeprom->word_size = 1 << (eeprom_size +
852 IXGBE_EEPROM_WORD_SIZE_SHIFT);
854 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
855 eeprom->type, eeprom->word_size);
858 return IXGBE_SUCCESS;
862 * ixgbe_enable_eee_x550 - Enable EEE support
863 * @hw: pointer to hardware structure
865 static s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
871 if (hw->mac.type == ixgbe_mac_X550) {
872 /* Advertise EEE capability */
873 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
874 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
877 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
878 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
879 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
881 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
882 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
884 return IXGBE_SUCCESS;
887 switch (hw->device_id) {
888 case IXGBE_DEV_ID_X550EM_X_KR:
889 case IXGBE_DEV_ID_X550EM_A_KR:
890 case IXGBE_DEV_ID_X550EM_A_KR_L:
891 status = hw->mac.ops.read_iosf_sb_reg(hw,
892 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
893 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
894 if (status != IXGBE_SUCCESS)
897 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
898 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
900 /* Don't advertise FEC capability when EEE enabled. */
901 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
903 status = hw->mac.ops.write_iosf_sb_reg(hw,
904 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
905 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
906 if (status != IXGBE_SUCCESS)
913 return IXGBE_SUCCESS;
917 * ixgbe_disable_eee_x550 - Disable EEE support
918 * @hw: pointer to hardware structure
920 static s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
926 if (hw->mac.type == ixgbe_mac_X550) {
927 /* Disable advertised EEE capability */
928 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
929 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
932 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
933 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
934 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
936 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
937 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
939 return IXGBE_SUCCESS;
942 switch (hw->device_id) {
943 case IXGBE_DEV_ID_X550EM_X_KR:
944 case IXGBE_DEV_ID_X550EM_A_KR:
945 case IXGBE_DEV_ID_X550EM_A_KR_L:
946 status = hw->mac.ops.read_iosf_sb_reg(hw,
947 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
948 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
949 if (status != IXGBE_SUCCESS)
952 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
953 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
955 /* Advertise FEC capability when EEE is disabled. */
956 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
958 status = hw->mac.ops.write_iosf_sb_reg(hw,
959 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
960 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
961 if (status != IXGBE_SUCCESS)
968 return IXGBE_SUCCESS;
972 * ixgbe_setup_eee_X550 - Enable/disable EEE support
973 * @hw: pointer to the HW structure
974 * @enable_eee: boolean flag to enable EEE
976 * Enable/disable EEE based on enable_eee flag.
977 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
981 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
986 DEBUGFUNC("ixgbe_setup_eee_X550");
988 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
989 /* Enable or disable EEE per flag */
991 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
993 /* Not supported on first revision of X550EM_x. */
994 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
995 !(IXGBE_FUSES0_REV_MASK &
996 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
997 return IXGBE_SUCCESS;
998 status = ixgbe_enable_eee_x550(hw);
1002 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1004 status = ixgbe_disable_eee_x550(hw);
1008 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
1010 return IXGBE_SUCCESS;
1014 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1015 * @hw: pointer to hardware structure
1016 * @enable: enable or disable source address pruning
1017 * @pool: Rx pool to set source address pruning for
1019 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1024 /* max rx pool is 63 */
1028 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1029 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1032 pfflp |= (1ULL << pool);
1034 pfflp &= ~(1ULL << pool);
1036 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1037 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1041 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1042 * @hw: pointer to hardware structure
1043 * @enable: enable or disable switch for Ethertype anti-spoofing
1044 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1047 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1048 bool enable, int vf)
1050 int vf_target_reg = vf >> 3;
1051 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1054 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1056 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1058 pfvfspoof |= (1 << vf_target_shift);
1060 pfvfspoof &= ~(1 << vf_target_shift);
1062 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1066 * ixgbe_iosf_wait - Wait for IOSF command completion
1067 * @hw: pointer to hardware structure
1068 * @ctrl: pointer to location to receive final IOSF control value
1070 * Returns failing status on timeout
1072 * Note: ctrl can be NULL if the IOSF control register value is not needed
1074 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1078 /* Check every 10 usec to see if the address cycle completed.
1079 * The SB IOSF BUSY bit will clear when the operation is
1082 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1083 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1084 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1090 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1091 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1092 return IXGBE_ERR_PHY;
1095 return IXGBE_SUCCESS;
1099 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
1101 * @hw: pointer to hardware structure
1102 * @reg_addr: 32 bit PHY register to write
1103 * @device_type: 3 bit device type
1104 * @data: Data to write to the register
1106 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1107 u32 device_type, u32 data)
1109 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1113 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1114 if (ret != IXGBE_SUCCESS)
1117 ret = ixgbe_iosf_wait(hw, NULL);
1118 if (ret != IXGBE_SUCCESS)
1121 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1122 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1124 /* Write IOSF control register */
1125 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1127 /* Write IOSF data register */
1128 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1130 ret = ixgbe_iosf_wait(hw, &command);
1132 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1133 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1134 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1135 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1136 "Failed to write, error %x\n", error);
1137 ret = IXGBE_ERR_PHY;
1141 ixgbe_release_swfw_semaphore(hw, gssr);
1146 * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
1148 * @hw: pointer to hardware structure
1149 * @reg_addr: 32 bit PHY register to write
1150 * @device_type: 3 bit device type
1151 * @phy_data: Pointer to read data from the register
1153 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1154 u32 device_type, u32 *data)
1156 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1160 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1161 if (ret != IXGBE_SUCCESS)
1164 ret = ixgbe_iosf_wait(hw, NULL);
1165 if (ret != IXGBE_SUCCESS)
1168 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1169 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1171 /* Write IOSF control register */
1172 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1174 ret = ixgbe_iosf_wait(hw, &command);
1176 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1177 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1178 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1179 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1180 "Failed to read, error %x\n", error);
1181 ret = IXGBE_ERR_PHY;
1184 if (ret == IXGBE_SUCCESS)
1185 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1188 ixgbe_release_swfw_semaphore(hw, gssr);
1193 * ixgbe_get_phy_token - Get the token for shared phy access
1194 * @hw: Pointer to hardware structure
1197 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1199 struct ixgbe_hic_phy_token_req token_cmd;
1202 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1203 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1204 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1205 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1206 token_cmd.port_number = hw->bus.lan_id;
1207 token_cmd.command_type = FW_PHY_TOKEN_REQ;
1209 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1211 IXGBE_HI_COMMAND_TIMEOUT,
1215 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1216 return IXGBE_SUCCESS;
1217 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1218 return IXGBE_ERR_FW_RESP_INVALID;
1220 return IXGBE_ERR_TOKEN_RETRY;
1224 * ixgbe_put_phy_token - Put the token for shared phy access
1225 * @hw: Pointer to hardware structure
1228 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1230 struct ixgbe_hic_phy_token_req token_cmd;
1233 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1234 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1235 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1236 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1237 token_cmd.port_number = hw->bus.lan_id;
1238 token_cmd.command_type = FW_PHY_TOKEN_REL;
1240 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1242 IXGBE_HI_COMMAND_TIMEOUT,
1246 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1247 return IXGBE_SUCCESS;
1248 return IXGBE_ERR_FW_RESP_INVALID;
1252 * ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1253 * of the IOSF device
1254 * @hw: pointer to hardware structure
1255 * @reg_addr: 32 bit PHY register to write
1256 * @device_type: 3 bit device type
1257 * @data: Data to write to the register
1259 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1260 u32 device_type, u32 data)
1262 struct ixgbe_hic_internal_phy_req write_cmd;
1264 UNREFERENCED_1PARAMETER(device_type);
1266 memset(&write_cmd, 0, sizeof(write_cmd));
1267 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1268 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1269 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1270 write_cmd.port_number = hw->bus.lan_id;
1271 write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1272 write_cmd.address = (u16)reg_addr;
1273 write_cmd.write_data = data;
1275 status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1277 IXGBE_HI_COMMAND_TIMEOUT, false);
1283 * ixgbe_read_iosf_sb_reg_x550a - Writes a value to specified register
1284 * of the IOSF device.
1285 * @hw: pointer to hardware structure
1286 * @reg_addr: 32 bit PHY register to write
1287 * @device_type: 3 bit device type
1288 * @data: Pointer to read data from the register
1290 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1291 u32 device_type, u32 *data)
1293 struct ixgbe_hic_internal_phy_req read_cmd;
1295 UNREFERENCED_1PARAMETER(device_type);
1297 memset(&read_cmd, 0, sizeof(read_cmd));
1298 read_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1299 read_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1300 read_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1301 read_cmd.port_number = hw->bus.lan_id;
1302 read_cmd.command_type = FW_INT_PHY_REQ_READ;
1303 read_cmd.address = (u16)reg_addr;
1305 status = ixgbe_host_interface_command(hw, (u32 *)&read_cmd,
1307 IXGBE_HI_COMMAND_TIMEOUT, true);
1309 /* Extract the register value from the response. */
1310 *data = ((struct ixgbe_hic_internal_phy_resp *)&read_cmd)->read_data;
1316 * ixgbe_disable_mdd_X550
1317 * @hw: pointer to hardware structure
1319 * Disable malicious driver detection
1321 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1325 DEBUGFUNC("ixgbe_disable_mdd_X550");
1327 /* Disable MDD for TX DMA and interrupt */
1328 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1329 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1330 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1332 /* Disable MDD for RX and interrupt */
1333 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1334 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1335 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1339 * ixgbe_enable_mdd_X550
1340 * @hw: pointer to hardware structure
1342 * Enable malicious driver detection
1344 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1348 DEBUGFUNC("ixgbe_enable_mdd_X550");
1350 /* Enable MDD for TX DMA and interrupt */
1351 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1352 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1353 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1355 /* Enable MDD for RX and interrupt */
1356 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1357 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1358 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1362 * ixgbe_restore_mdd_vf_X550
1363 * @hw: pointer to hardware structure
1366 * Restore VF that was disabled during malicious driver detection event
1368 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1370 u32 idx, reg, num_qs, start_q, bitmask;
1372 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1374 /* Map VF to queues */
1375 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1376 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1377 case IXGBE_MRQC_VMDQRT8TCEN:
1378 num_qs = 8; /* 16 VFs / pools */
1379 bitmask = 0x000000FF;
1381 case IXGBE_MRQC_VMDQRSS32EN:
1382 case IXGBE_MRQC_VMDQRT4TCEN:
1383 num_qs = 4; /* 32 VFs / pools */
1384 bitmask = 0x0000000F;
1386 default: /* 64 VFs / pools */
1388 bitmask = 0x00000003;
1391 start_q = vf * num_qs;
1393 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1396 reg |= (bitmask << (start_q % 32));
1397 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1398 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1402 * ixgbe_mdd_event_X550
1403 * @hw: pointer to hardware structure
1404 * @vf_bitmap: vf bitmap of malicious vfs
1406 * Handle malicious driver detection event.
1408 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1411 u32 i, j, reg, q, shift, vf, idx;
1413 DEBUGFUNC("ixgbe_mdd_event_X550");
1415 /* figure out pool size for mapping to vf's */
1416 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1417 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1418 case IXGBE_MRQC_VMDQRT8TCEN:
1419 shift = 3; /* 16 VFs / pools */
1421 case IXGBE_MRQC_VMDQRSS32EN:
1422 case IXGBE_MRQC_VMDQRT4TCEN:
1423 shift = 2; /* 32 VFs / pools */
1426 shift = 1; /* 64 VFs / pools */
1430 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1431 for (i = 0; i < 4; i++) {
1432 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1433 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1438 /* Get malicious queue */
1439 for (j = 0; j < 32 && wqbr; j++) {
1441 if (!(wqbr & (1 << j)))
1444 /* Get queue from bitmask */
1447 /* Map queue to vf */
1450 /* Set vf bit in vf_bitmap */
1452 vf_bitmap[idx] |= (1 << (vf % 32));
1459 * ixgbe_get_media_type_X550em - Get media type
1460 * @hw: pointer to hardware structure
1462 * Returns the media type (fiber, copper, backplane)
1464 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1466 enum ixgbe_media_type media_type;
1468 DEBUGFUNC("ixgbe_get_media_type_X550em");
1470 /* Detect if there is a copper PHY attached. */
1471 switch (hw->device_id) {
1472 case IXGBE_DEV_ID_X550EM_X_KR:
1473 case IXGBE_DEV_ID_X550EM_X_KX4:
1474 case IXGBE_DEV_ID_X550EM_A_KR:
1475 case IXGBE_DEV_ID_X550EM_A_KR_L:
1476 media_type = ixgbe_media_type_backplane;
1478 case IXGBE_DEV_ID_X550EM_X_SFP:
1479 case IXGBE_DEV_ID_X550EM_A_SFP:
1480 case IXGBE_DEV_ID_X550EM_A_SFP_N:
1481 case IXGBE_DEV_ID_X550EM_A_QSFP:
1482 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1483 media_type = ixgbe_media_type_fiber;
1485 case IXGBE_DEV_ID_X550EM_X_1G_T:
1486 case IXGBE_DEV_ID_X550EM_X_10G_T:
1487 case IXGBE_DEV_ID_X550EM_A_10G_T:
1488 media_type = ixgbe_media_type_copper;
1490 case IXGBE_DEV_ID_X550EM_A_1G_T:
1491 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1492 media_type = ixgbe_media_type_sgmii;
1493 hw->phy.type = ixgbe_phy_sgmii;
1496 media_type = ixgbe_media_type_unknown;
1503 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1504 * @hw: pointer to hardware structure
1505 * @linear: true if SFP module is linear
1507 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1509 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1511 switch (hw->phy.sfp_type) {
1512 case ixgbe_sfp_type_not_present:
1513 return IXGBE_ERR_SFP_NOT_PRESENT;
1514 case ixgbe_sfp_type_da_cu_core0:
1515 case ixgbe_sfp_type_da_cu_core1:
1518 case ixgbe_sfp_type_srlr_core0:
1519 case ixgbe_sfp_type_srlr_core1:
1520 case ixgbe_sfp_type_da_act_lmt_core0:
1521 case ixgbe_sfp_type_da_act_lmt_core1:
1522 case ixgbe_sfp_type_1g_sx_core0:
1523 case ixgbe_sfp_type_1g_sx_core1:
1524 case ixgbe_sfp_type_1g_lx_core0:
1525 case ixgbe_sfp_type_1g_lx_core1:
1528 case ixgbe_sfp_type_unknown:
1529 case ixgbe_sfp_type_1g_cu_core0:
1530 case ixgbe_sfp_type_1g_cu_core1:
1532 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1535 return IXGBE_SUCCESS;
1539 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1540 * @hw: pointer to hardware structure
1542 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1544 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1549 DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1551 status = ixgbe_identify_module_generic(hw);
1553 if (status != IXGBE_SUCCESS)
1556 /* Check if SFP module is supported */
1557 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1563 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1564 * @hw: pointer to hardware structure
1566 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1571 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1573 /* Check if SFP module is supported */
1574 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1576 if (status != IXGBE_SUCCESS)
1579 ixgbe_init_mac_link_ops_X550em(hw);
1580 hw->phy.ops.reset = NULL;
1582 return IXGBE_SUCCESS;
1586 * ixgbe_setup_sgmii - Set up link for sgmii
1587 * @hw: pointer to hardware structure
1589 static s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1590 bool autoneg_wait_to_complete)
1592 struct ixgbe_mac_info *mac = &hw->mac;
1595 UNREFERENCED_2PARAMETER(speed, autoneg_wait_to_complete);
1597 rc = mac->ops.read_iosf_sb_reg(hw,
1598 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1599 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1603 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1604 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1605 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1606 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1607 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1608 rc = mac->ops.write_iosf_sb_reg(hw,
1609 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1610 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1614 rc = mac->ops.read_iosf_sb_reg(hw,
1615 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1616 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1620 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1621 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1622 rc = mac->ops.write_iosf_sb_reg(hw,
1623 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1624 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1628 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1629 rc = mac->ops.write_iosf_sb_reg(hw,
1630 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1631 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1637 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1638 * @hw: pointer to hardware structure
1640 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1642 struct ixgbe_mac_info *mac = &hw->mac;
1644 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1646 switch (hw->mac.ops.get_media_type(hw)) {
1647 case ixgbe_media_type_fiber:
1648 /* CS4227 does not support autoneg, so disable the laser control
1649 * functions for SFP+ fiber
1651 mac->ops.disable_tx_laser = NULL;
1652 mac->ops.enable_tx_laser = NULL;
1653 mac->ops.flap_tx_laser = NULL;
1654 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1655 mac->ops.set_rate_select_speed =
1656 ixgbe_set_soft_rate_select_speed;
1657 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1658 (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1659 mac->ops.setup_mac_link =
1660 ixgbe_setup_mac_link_sfp_x550a;
1662 mac->ops.setup_mac_link =
1663 ixgbe_setup_mac_link_sfp_x550em;
1665 case ixgbe_media_type_copper:
1666 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1667 mac->ops.check_link = ixgbe_check_link_t_X550em;
1669 case ixgbe_media_type_backplane:
1671 case ixgbe_media_type_sgmii:
1672 mac->ops.setup_link = ixgbe_setup_sgmii;
1680 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1681 * @hw: pointer to hardware structure
1682 * @speed: pointer to link speed
1683 * @autoneg: true when autoneg or autotry is enabled
1685 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1686 ixgbe_link_speed *speed,
1689 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1692 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1694 /* CS4227 SFP must not enable auto-negotiation */
1697 /* Check if 1G SFP module. */
1698 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1699 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1700 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1701 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1702 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1703 return IXGBE_SUCCESS;
1706 /* Link capabilities are based on SFP */
1707 if (hw->phy.multispeed_fiber)
1708 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1709 IXGBE_LINK_SPEED_1GB_FULL;
1711 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1713 switch (hw->phy.type) {
1715 *speed = IXGBE_LINK_SPEED_100_FULL |
1716 IXGBE_LINK_SPEED_1GB_FULL;
1718 case ixgbe_phy_sgmii:
1719 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1722 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1723 IXGBE_LINK_SPEED_1GB_FULL;
1729 return IXGBE_SUCCESS;
1733 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1734 * @hw: pointer to hardware structure
1735 * @lsc: pointer to boolean flag which indicates whether external Base T
1736 * PHY interrupt is lsc
1738 * Determime if external Base T PHY interrupt cause is high temperature
1739 * failure alarm or link status change.
1741 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1742 * failure alarm, else return PHY access status.
1744 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1751 /* Vendor alarm triggered */
1752 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1753 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1756 if (status != IXGBE_SUCCESS ||
1757 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1760 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1761 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1762 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1765 if (status != IXGBE_SUCCESS ||
1766 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1767 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1770 /* Global alarm triggered */
1771 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1772 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1775 if (status != IXGBE_SUCCESS)
1778 /* If high temperature failure, then return over temp error and exit */
1779 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1780 /* power down the PHY in case the PHY FW didn't already */
1781 ixgbe_set_copper_phy_power(hw, false);
1782 return IXGBE_ERR_OVERTEMP;
1783 } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1784 /* device fault alarm triggered */
1785 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1786 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1789 if (status != IXGBE_SUCCESS)
1792 /* if device fault was due to high temp alarm handle and exit */
1793 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1794 /* power down the PHY in case the PHY FW didn't */
1795 ixgbe_set_copper_phy_power(hw, false);
1796 return IXGBE_ERR_OVERTEMP;
1800 /* Vendor alarm 2 triggered */
1801 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1802 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1804 if (status != IXGBE_SUCCESS ||
1805 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1808 /* link connect/disconnect event occurred */
1809 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1810 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1812 if (status != IXGBE_SUCCESS)
1816 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1819 return IXGBE_SUCCESS;
1823 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1824 * @hw: pointer to hardware structure
1826 * Enable link status change and temperature failure alarm for the external
1829 * Returns PHY access status
1831 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1837 /* Clear interrupt flags */
1838 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1840 /* Enable link status change alarm */
1841 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1842 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1844 if (status != IXGBE_SUCCESS)
1847 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1849 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1850 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1852 if (status != IXGBE_SUCCESS)
1855 /* Enable high temperature failure and global fault alarms */
1856 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1857 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1860 if (status != IXGBE_SUCCESS)
1863 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
1864 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
1866 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1867 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1870 if (status != IXGBE_SUCCESS)
1873 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1874 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1875 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1878 if (status != IXGBE_SUCCESS)
1881 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1882 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1884 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1885 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1888 if (status != IXGBE_SUCCESS)
1891 /* Enable chip-wide vendor alarm */
1892 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1893 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1896 if (status != IXGBE_SUCCESS)
1899 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1901 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1902 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1909 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1910 * @hw: pointer to hardware structure
1911 * @speed: link speed
1913 * Configures the integrated KR PHY.
1915 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1916 ixgbe_link_speed speed)
1921 status = hw->mac.ops.read_iosf_sb_reg(hw,
1922 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1923 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1927 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1928 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1929 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1931 /* Advertise 10G support. */
1932 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1933 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1935 /* Advertise 1G support. */
1936 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1937 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1939 /* Restart auto-negotiation. */
1940 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1941 status = hw->mac.ops.write_iosf_sb_reg(hw,
1942 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1943 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1949 * ixgbe_set_master_slave_mode - Set up PHY for master/slave mode
1950 * @hw: pointer to hardware structure
1952 * Must be called while holding the PHY semaphore and token
1954 static s32 ixgbe_set_master_slave_mode(struct ixgbe_hw *hw)
1959 /* Resolve master/slave mode */
1960 rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_M88E1500_1000T_CTRL, 0,
1965 /* load defaults for future use */
1966 if (phy_data & IXGBE_M88E1500_1000T_CTRL_MS_ENABLE) {
1967 if (phy_data & IXGBE_M88E1500_1000T_CTRL_MS_VALUE)
1968 hw->phy.original_ms_type = ixgbe_ms_force_master;
1970 hw->phy.original_ms_type = ixgbe_ms_force_slave;
1972 hw->phy.original_ms_type = ixgbe_ms_auto;
1975 switch (hw->phy.ms_type) {
1976 case ixgbe_ms_force_master:
1977 phy_data |= IXGBE_M88E1500_1000T_CTRL_MS_ENABLE;
1978 phy_data |= IXGBE_M88E1500_1000T_CTRL_MS_VALUE;
1980 case ixgbe_ms_force_slave:
1981 phy_data |= IXGBE_M88E1500_1000T_CTRL_MS_ENABLE;
1982 phy_data &= ~IXGBE_M88E1500_1000T_CTRL_MS_VALUE;
1985 phy_data &= ~IXGBE_M88E1500_1000T_CTRL_MS_ENABLE;
1991 return ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_1000T_CTRL, 0,
1996 * ixgbe_reset_phy_m88_nolock - Reset m88 PHY without locking
1997 * @hw: pointer to hardware structure
1999 * Must be called while holding the PHY semaphore and token
2001 static s32 ixgbe_reset_phy_m88_nolock(struct ixgbe_hw *hw)
2005 rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2009 rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_FIBER_CTRL, 0,
2010 IXGBE_M88E1500_FIBER_CTRL_RESET |
2011 IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2012 IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB);
2016 rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 18);
2020 rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_GEN_CTRL, 0,
2021 IXGBE_M88E1500_GEN_CTRL_RESET |
2022 IXGBE_M88E1500_GEN_CTRL_SGMII_COPPER);
2026 rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2030 rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2031 IXGBE_M88E1500_COPPER_CTRL_RESET |
2032 IXGBE_M88E1500_COPPER_CTRL_AN_EN |
2033 IXGBE_M88E1500_COPPER_CTRL_RESTART_AN |
2034 IXGBE_M88E1500_COPPER_CTRL_FULL_DUPLEX |
2035 IXGBE_M88E1500_COPPER_CTRL_SPEED_MSB);
2038 ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2043 * ixgbe_reset_phy_m88 - Reset m88 PHY
2044 * @hw: pointer to hardware structure
2046 static s32 ixgbe_reset_phy_m88(struct ixgbe_hw *hw)
2048 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2051 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2052 return IXGBE_SUCCESS;
2054 rc = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
2058 rc = ixgbe_reset_phy_m88_nolock(hw);
2060 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2065 * ixgbe_setup_m88 - setup m88 PHY
2066 * @hw: pointer to hardware structure
2068 static s32 ixgbe_setup_m88(struct ixgbe_hw *hw)
2070 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2071 struct ixgbe_phy_info *phy = &hw->phy;
2075 if (phy->reset_disable || ixgbe_check_reset_blocked(hw))
2076 return IXGBE_SUCCESS;
2078 rc = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
2082 rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_M88E1500_PHY_SPEC_CTRL, 0,
2087 /* Enable downshift and setting it to X6 */
2088 phy_data &= ~IXGBE_M88E1500_PSCR_DOWNSHIFT_ENABLE;
2089 phy_data |= IXGBE_M88E1500_PSCR_DOWNSHIFT_6X;
2090 phy_data |= IXGBE_M88E1500_PSCR_DOWNSHIFT_ENABLE;
2091 rc = ixgbe_write_phy_reg_mdi_22(hw,
2092 IXGBE_M88E1500_PHY_SPEC_CTRL, 0,
2097 ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2099 /* Commit the changes */
2100 rc = ixgbe_reset_phy_m88_nolock(hw);
2102 DEBUGOUT("Error committing the PHY changes\n");
2106 rc = ixgbe_set_master_slave_mode(hw);
2108 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2112 ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2113 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2118 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2119 * @hw: pointer to hardware structure
2121 * Read NW_MNG_IF_SEL register and save field values, and check for valid field
2124 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2126 /* Save NW management interface connected on board. This is used
2127 * to determine internal PHY mode.
2129 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2131 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2132 * PHY address. This register field was has only been used for X552.
2134 if (hw->mac.type == ixgbe_mac_X550EM_a &&
2135 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2136 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2137 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2138 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2141 return IXGBE_SUCCESS;
2145 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2146 * @hw: pointer to hardware structure
2148 * Initialize any function pointers that were not able to be
2149 * set during init_shared_code because the PHY/SFP type was
2150 * not known. Perform the SFP init if necessary.
2152 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2154 struct ixgbe_phy_info *phy = &hw->phy;
2157 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2159 hw->mac.ops.set_lan_id(hw);
2161 ixgbe_read_mng_if_sel_x550em(hw);
2163 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2164 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2165 ixgbe_setup_mux_ctl(hw);
2166 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2169 /* Identify the PHY or SFP module */
2170 ret_val = phy->ops.identify(hw);
2171 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
2174 /* Setup function pointers based on detected hardware */
2175 ixgbe_init_mac_link_ops_X550em(hw);
2176 if (phy->sfp_type != ixgbe_sfp_type_unknown)
2177 phy->ops.reset = NULL;
2179 /* Set functions pointers based on phy type */
2180 switch (hw->phy.type) {
2181 case ixgbe_phy_x550em_kx4:
2182 phy->ops.setup_link = NULL;
2183 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2184 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2186 case ixgbe_phy_x550em_kr:
2187 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2188 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2189 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2191 case ixgbe_phy_x550em_ext_t:
2192 /* If internal link mode is XFI, then setup iXFI internal link,
2193 * else setup KR now.
2195 phy->ops.setup_internal_link =
2196 ixgbe_setup_internal_phy_t_x550em;
2198 /* setup SW LPLU only for first revision of X550EM_x */
2199 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2200 !(IXGBE_FUSES0_REV_MASK &
2201 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2202 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2204 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2205 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2207 case ixgbe_phy_sgmii:
2208 phy->ops.setup_link = NULL;
2211 phy->ops.setup_link = ixgbe_setup_m88;
2212 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2213 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2214 phy->ops.reset = ixgbe_reset_phy_m88;
2223 * ixgbe_set_mdio_speed - Set MDIO clock speed
2224 * @hw: pointer to hardware structure
2226 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2230 switch (hw->device_id) {
2231 case IXGBE_DEV_ID_X550EM_X_10G_T:
2232 case IXGBE_DEV_ID_X550EM_A_1G_T:
2233 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2234 case IXGBE_DEV_ID_X550EM_A_10G_T:
2235 case IXGBE_DEV_ID_X550EM_A_SFP:
2236 case IXGBE_DEV_ID_X550EM_A_QSFP:
2237 /* Config MDIO clock speed before the first MDIO PHY access */
2238 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2239 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2240 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2248 * ixgbe_reset_hw_X550em - Perform hardware reset
2249 * @hw: pointer to hardware structure
2251 * Resets the hardware by resetting the transmit and receive units, masks
2252 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2255 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2257 ixgbe_link_speed link_speed;
2261 bool link_up = false;
2263 DEBUGFUNC("ixgbe_reset_hw_X550em");
2265 /* Call adapter stop to disable Tx/Rx and clear interrupts */
2266 status = hw->mac.ops.stop_adapter(hw);
2267 if (status != IXGBE_SUCCESS)
2270 /* flush pending Tx transactions */
2271 ixgbe_clear_tx_pending(hw);
2273 ixgbe_set_mdio_speed(hw);
2275 /* PHY ops must be identified and initialized prior to reset */
2276 status = hw->phy.ops.init(hw);
2278 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2281 /* start the external PHY */
2282 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2283 status = ixgbe_init_ext_t_x550em(hw);
2288 /* Setup SFP module if there is one present. */
2289 if (hw->phy.sfp_setup_needed) {
2290 status = hw->mac.ops.setup_sfp(hw);
2291 hw->phy.sfp_setup_needed = false;
2294 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2298 if (!hw->phy.reset_disable && hw->phy.ops.reset)
2299 hw->phy.ops.reset(hw);
2302 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
2303 * If link reset is used when link is up, it might reset the PHY when
2304 * mng is using it. If link is down or the flag to force full link
2305 * reset is set, then perform link reset.
2307 ctrl = IXGBE_CTRL_LNK_RST;
2308 if (!hw->force_full_reset) {
2309 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2311 ctrl = IXGBE_CTRL_RST;
2314 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2315 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2316 IXGBE_WRITE_FLUSH(hw);
2318 /* Poll for reset bit to self-clear meaning reset is complete */
2319 for (i = 0; i < 10; i++) {
2321 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2322 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2326 if (ctrl & IXGBE_CTRL_RST_MASK) {
2327 status = IXGBE_ERR_RESET_FAILED;
2328 DEBUGOUT("Reset polling failed to complete.\n");
2333 /* Double resets are required for recovery from certain error
2334 * conditions. Between resets, it is necessary to stall to
2335 * allow time for any pending HW events to complete.
2337 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2338 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2342 /* Store the permanent mac address */
2343 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2345 /* Store MAC address from RAR0, clear receive address registers, and
2346 * clear the multicast table. Also reset num_rar_entries to 128,
2347 * since we modify this value when programming the SAN MAC address.
2349 hw->mac.num_rar_entries = 128;
2350 hw->mac.ops.init_rx_addrs(hw);
2352 ixgbe_set_mdio_speed(hw);
2354 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2355 ixgbe_setup_mux_ctl(hw);
2361 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2362 * @hw: pointer to hardware structure
2364 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2369 status = hw->phy.ops.read_reg(hw,
2370 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2371 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2374 if (status != IXGBE_SUCCESS)
2377 /* If PHY FW reset completed bit is set then this is the first
2378 * SW instance after a power on so the PHY FW must be un-stalled.
2380 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2381 status = hw->phy.ops.read_reg(hw,
2382 IXGBE_MDIO_GLOBAL_RES_PR_10,
2383 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2386 if (status != IXGBE_SUCCESS)
2389 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2391 status = hw->phy.ops.write_reg(hw,
2392 IXGBE_MDIO_GLOBAL_RES_PR_10,
2393 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2396 if (status != IXGBE_SUCCESS)
2404 * ixgbe_setup_kr_x550em - Configure the KR PHY.
2405 * @hw: pointer to hardware structure
2407 * Configures the integrated KR PHY for X550EM_x.
2409 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2411 if (hw->mac.type != ixgbe_mac_X550EM_x)
2412 return IXGBE_SUCCESS;
2414 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2418 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2419 * @hw: pointer to hardware structure
2421 * Configure the external PHY and the integrated KR PHY for SFP support.
2423 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2424 ixgbe_link_speed speed,
2425 bool autoneg_wait_to_complete)
2428 u16 reg_slice, reg_val;
2429 bool setup_linear = false;
2430 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2432 /* Check if SFP module is supported and linear */
2433 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2435 /* If no SFP module present, then return success. Return success since
2436 * there is no reason to configure CS4227 and SFP not present error is
2437 * not excepted in the setup MAC link flow.
2439 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2440 return IXGBE_SUCCESS;
2442 if (ret_val != IXGBE_SUCCESS)
2445 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2446 /* Configure CS4227 LINE side to 10G SR. */
2447 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
2448 (hw->bus.lan_id << 12);
2449 reg_val = IXGBE_CS4227_SPEED_10G;
2450 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2453 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2454 (hw->bus.lan_id << 12);
2455 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2456 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2459 /* Configure CS4227 for HOST connection rate then type. */
2460 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
2461 (hw->bus.lan_id << 12);
2462 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
2463 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
2464 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2467 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
2468 (hw->bus.lan_id << 12);
2470 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2472 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2473 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2476 /* Setup XFI internal link. */
2477 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2479 /* Configure internal PHY for KR/KX. */
2480 ixgbe_setup_kr_speed_x550em(hw, speed);
2482 /* Configure CS4227 LINE side to proper mode. */
2483 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2484 (hw->bus.lan_id << 12);
2486 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2488 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2489 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2496 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2497 * @hw: pointer to hardware structure
2499 * Configure the the integrated PHY for SFP support.
2501 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2502 ixgbe_link_speed speed,
2503 bool autoneg_wait_to_complete)
2507 bool setup_linear = false;
2508 u32 reg_slice, reg_phy_int, slice_offset;
2510 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2512 /* Check if SFP module is supported and linear */
2513 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2515 /* If no SFP module present, then return success. Return success since
2516 * SFP not present error is not excepted in the setup MAC link flow.
2518 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2519 return IXGBE_SUCCESS;
2521 if (ret_val != IXGBE_SUCCESS)
2524 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2525 /* Configure internal PHY for native SFI */
2526 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2527 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2528 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int);
2530 if (ret_val != IXGBE_SUCCESS)
2534 reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LIMITING;
2535 reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LINEAR;
2537 reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LIMITING;
2538 reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LINEAR;
2541 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2542 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2543 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2545 if (ret_val != IXGBE_SUCCESS)
2548 /* Setup XFI/SFI internal link. */
2549 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2551 /* Configure internal PHY for KR/KX. */
2552 ixgbe_setup_kr_speed_x550em(hw, speed);
2554 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2556 DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2557 return IXGBE_ERR_PHY_ADDR_INVALID;
2560 /* Get external PHY device id */
2561 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_GLOBAL_ID_MSB,
2562 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
2564 if (ret_val != IXGBE_SUCCESS)
2567 /* When configuring quad port CS4223, the MAC instance is part
2568 * of the slice offset.
2570 if (reg_phy_ext == IXGBE_CS4223_PHY_ID)
2571 slice_offset = (hw->bus.lan_id +
2572 (hw->bus.instance_id << 1)) << 12;
2574 slice_offset = hw->bus.lan_id << 12;
2576 /* Configure CS4227/CS4223 LINE side to proper mode. */
2577 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2579 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2581 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2582 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2583 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2589 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2590 * @hw: pointer to hardware structure
2592 * iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2594 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2599 /* Disable training protocol FSM. */
2600 status = ixgbe_read_iosf_sb_reg_x550(hw,
2601 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2602 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2603 if (status != IXGBE_SUCCESS)
2605 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2606 status = ixgbe_write_iosf_sb_reg_x550(hw,
2607 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2608 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2609 if (status != IXGBE_SUCCESS)
2612 /* Disable Flex from training TXFFE. */
2613 status = ixgbe_read_iosf_sb_reg_x550(hw,
2614 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2615 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2616 if (status != IXGBE_SUCCESS)
2618 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2619 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2620 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2621 status = ixgbe_write_iosf_sb_reg_x550(hw,
2622 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2623 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2624 if (status != IXGBE_SUCCESS)
2626 status = ixgbe_read_iosf_sb_reg_x550(hw,
2627 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2628 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2629 if (status != IXGBE_SUCCESS)
2631 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2632 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2633 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2634 status = ixgbe_write_iosf_sb_reg_x550(hw,
2635 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2636 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2637 if (status != IXGBE_SUCCESS)
2640 /* Enable override for coefficients. */
2641 status = ixgbe_read_iosf_sb_reg_x550(hw,
2642 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2643 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2644 if (status != IXGBE_SUCCESS)
2646 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2647 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2648 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2649 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2650 status = ixgbe_write_iosf_sb_reg_x550(hw,
2651 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2652 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2657 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2658 * @hw: pointer to hardware structure
2659 * @speed: the link speed to force
2661 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
2662 * internal and external PHY at a specific speed, without autonegotiation.
2664 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2669 /* Disable AN and force speed to 10G Serial. */
2670 status = ixgbe_read_iosf_sb_reg_x550(hw,
2671 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2672 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2673 if (status != IXGBE_SUCCESS)
2676 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2677 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2679 /* Select forced link speed for internal PHY. */
2681 case IXGBE_LINK_SPEED_10GB_FULL:
2682 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2684 case IXGBE_LINK_SPEED_1GB_FULL:
2685 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2688 /* Other link speeds are not supported by internal KR PHY. */
2689 return IXGBE_ERR_LINK_SETUP;
2692 status = ixgbe_write_iosf_sb_reg_x550(hw,
2693 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2694 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2695 if (status != IXGBE_SUCCESS)
2698 /* Additional configuration needed for x550em_x */
2699 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2700 status = ixgbe_setup_ixfi_x550em_x(hw);
2701 if (status != IXGBE_SUCCESS)
2705 /* Toggle port SW reset by AN reset. */
2706 status = ixgbe_read_iosf_sb_reg_x550(hw,
2707 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2708 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2709 if (status != IXGBE_SUCCESS)
2711 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2712 status = ixgbe_write_iosf_sb_reg_x550(hw,
2713 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2714 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2720 * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2721 * @hw: address of hardware structure
2722 * @link_up: address of boolean to indicate link status
2724 * Returns error code if unable to get link status.
2726 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2733 /* read this twice back to back to indicate current status */
2734 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2735 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2737 if (ret != IXGBE_SUCCESS)
2740 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2741 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2743 if (ret != IXGBE_SUCCESS)
2746 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2748 return IXGBE_SUCCESS;
2752 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2753 * @hw: point to hardware structure
2755 * Configures the link between the integrated KR PHY and the external X557 PHY
2756 * The driver will call this function when it gets a link status change
2757 * interrupt from the X557 PHY. This function configures the link speed
2758 * between the PHYs to match the link speed of the BASE-T link.
2760 * A return of a non-zero value indicates an error, and the base driver should
2761 * not report link up.
2763 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2765 ixgbe_link_speed force_speed;
2770 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2771 return IXGBE_ERR_CONFIG;
2773 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2774 /* If link is down, there is no setup necessary so return */
2775 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2776 if (status != IXGBE_SUCCESS)
2780 return IXGBE_SUCCESS;
2782 status = hw->phy.ops.read_reg(hw,
2783 IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2784 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2786 if (status != IXGBE_SUCCESS)
2789 /* If link is still down - no setup is required so return */
2790 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2791 if (status != IXGBE_SUCCESS)
2794 return IXGBE_SUCCESS;
2796 /* clear everything but the speed and duplex bits */
2797 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2800 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2801 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2803 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2804 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2807 /* Internal PHY does not support anything else */
2808 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2811 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2813 speed = IXGBE_LINK_SPEED_10GB_FULL |
2814 IXGBE_LINK_SPEED_1GB_FULL;
2815 return ixgbe_setup_kr_speed_x550em(hw, speed);
2820 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
2821 * @hw: pointer to hardware structure
2823 * Configures the integrated KR PHY to use internal loopback mode.
2825 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
2830 /* Disable AN and force speed to 10G Serial. */
2831 status = hw->mac.ops.read_iosf_sb_reg(hw,
2832 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2833 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2834 if (status != IXGBE_SUCCESS)
2836 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2837 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2838 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2839 status = hw->mac.ops.write_iosf_sb_reg(hw,
2840 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2841 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2842 if (status != IXGBE_SUCCESS)
2845 /* Set near-end loopback clocks. */
2846 status = hw->mac.ops.read_iosf_sb_reg(hw,
2847 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2848 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2849 if (status != IXGBE_SUCCESS)
2851 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2852 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2853 status = hw->mac.ops.write_iosf_sb_reg(hw,
2854 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2855 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2856 if (status != IXGBE_SUCCESS)
2859 /* Set loopback enable. */
2860 status = hw->mac.ops.read_iosf_sb_reg(hw,
2861 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2862 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2863 if (status != IXGBE_SUCCESS)
2865 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2866 status = hw->mac.ops.write_iosf_sb_reg(hw,
2867 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2868 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2869 if (status != IXGBE_SUCCESS)
2872 /* Training bypass. */
2873 status = hw->mac.ops.read_iosf_sb_reg(hw,
2874 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2875 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2876 if (status != IXGBE_SUCCESS)
2878 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2879 status = hw->mac.ops.write_iosf_sb_reg(hw,
2880 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2881 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2887 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2888 * assuming that the semaphore is already obtained.
2889 * @hw: pointer to hardware structure
2890 * @offset: offset of word in the EEPROM to read
2891 * @data: word read from the EEPROM
2893 * Reads a 16 bit word from the EEPROM using the hostif.
2895 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2899 struct ixgbe_hic_read_shadow_ram buffer;
2901 DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2902 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2903 buffer.hdr.req.buf_lenh = 0;
2904 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2905 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2907 /* convert offset from words to bytes */
2908 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2910 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2912 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2914 IXGBE_HI_COMMAND_TIMEOUT, false);
2919 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2920 FW_NVM_DATA_OFFSET);
2926 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2927 * @hw: pointer to hardware structure
2928 * @offset: offset of word in the EEPROM to read
2929 * @data: word read from the EEPROM
2931 * Reads a 16 bit word from the EEPROM using the hostif.
2933 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2936 s32 status = IXGBE_SUCCESS;
2938 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2940 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2942 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2943 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2945 status = IXGBE_ERR_SWFW_SYNC;
2952 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2953 * @hw: pointer to hardware structure
2954 * @offset: offset of word in the EEPROM to read
2955 * @words: number of words
2956 * @data: word(s) read from the EEPROM
2958 * Reads a 16 bit word(s) from the EEPROM using the hostif.
2960 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2961 u16 offset, u16 words, u16 *data)
2963 struct ixgbe_hic_read_shadow_ram buffer;
2964 u32 current_word = 0;
2969 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2971 /* Take semaphore for the entire operation. */
2972 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2974 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2978 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2979 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2981 words_to_read = words;
2983 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2984 buffer.hdr.req.buf_lenh = 0;
2985 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2986 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2988 /* convert offset from words to bytes */
2989 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2990 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2992 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2994 IXGBE_HI_COMMAND_TIMEOUT,
2998 DEBUGOUT("Host interface command failed\n");
3002 for (i = 0; i < words_to_read; i++) {
3003 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3005 u32 value = IXGBE_READ_REG(hw, reg);
3007 data[current_word] = (u16)(value & 0xffff);
3010 if (i < words_to_read) {
3012 data[current_word] = (u16)(value & 0xffff);
3016 words -= words_to_read;
3020 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3025 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3026 * @hw: pointer to hardware structure
3027 * @offset: offset of word in the EEPROM to write
3028 * @data: word write to the EEPROM
3030 * Write a 16 bit word to the EEPROM using the hostif.
3032 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3036 struct ixgbe_hic_write_shadow_ram buffer;
3038 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3040 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3041 buffer.hdr.req.buf_lenh = 0;
3042 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3043 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3046 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3048 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3050 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3052 IXGBE_HI_COMMAND_TIMEOUT, false);
3058 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3059 * @hw: pointer to hardware structure
3060 * @offset: offset of word in the EEPROM to write
3061 * @data: word write to the EEPROM
3063 * Write a 16 bit word to the EEPROM using the hostif.
3065 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3068 s32 status = IXGBE_SUCCESS;
3070 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3072 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3074 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3075 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3077 DEBUGOUT("write ee hostif failed to get semaphore");
3078 status = IXGBE_ERR_SWFW_SYNC;
3085 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3086 * @hw: pointer to hardware structure
3087 * @offset: offset of word in the EEPROM to write
3088 * @words: number of words
3089 * @data: word(s) write to the EEPROM
3091 * Write a 16 bit word(s) to the EEPROM using the hostif.
3093 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3094 u16 offset, u16 words, u16 *data)
3096 s32 status = IXGBE_SUCCESS;
3099 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3101 /* Take semaphore for the entire operation. */
3102 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3103 if (status != IXGBE_SUCCESS) {
3104 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3108 for (i = 0; i < words; i++) {
3109 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3112 if (status != IXGBE_SUCCESS) {
3113 DEBUGOUT("Eeprom buffered write failed\n");
3118 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3125 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3126 * @hw: pointer to hardware structure
3127 * @ptr: pointer offset in eeprom
3128 * @size: size of section pointed by ptr, if 0 first word will be used as size
3129 * @csum: address of checksum to update
3131 * Returns error status for any failure
3133 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3134 u16 size, u16 *csum, u16 *buffer,
3139 u16 length, bufsz, i, start;
3142 bufsz = sizeof(buf) / sizeof(buf[0]);
3144 /* Read a chunk at the pointer location */
3146 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3148 DEBUGOUT("Failed to read EEPROM image\n");
3153 if (buffer_size < ptr)
3154 return IXGBE_ERR_PARAM;
3155 local_buffer = &buffer[ptr];
3163 length = local_buffer[0];
3165 /* Skip pointer section if length is invalid. */
3166 if (length == 0xFFFF || length == 0 ||
3167 (ptr + length) >= hw->eeprom.word_size)
3168 return IXGBE_SUCCESS;
3171 if (buffer && ((u32)start + (u32)length > buffer_size))
3172 return IXGBE_ERR_PARAM;
3174 for (i = start; length; i++, length--) {
3175 if (i == bufsz && !buffer) {
3181 /* Read a chunk at the pointer location */
3182 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3185 DEBUGOUT("Failed to read EEPROM image\n");
3189 *csum += local_buffer[i];
3191 return IXGBE_SUCCESS;
3195 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3196 * @hw: pointer to hardware structure
3197 * @buffer: pointer to buffer containing calculated checksum
3198 * @buffer_size: size of buffer
3200 * Returns a negative error code on error, or the 16-bit checksum
3202 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3204 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3208 u16 pointer, i, size;
3210 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3212 hw->eeprom.ops.init_params(hw);
3215 /* Read pointer area */
3216 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3217 IXGBE_EEPROM_LAST_WORD + 1,
3220 DEBUGOUT("Failed to read EEPROM image\n");
3223 local_buffer = eeprom_ptrs;
3225 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3226 return IXGBE_ERR_PARAM;
3227 local_buffer = buffer;
3231 * For X550 hardware include 0x0-0x41 in the checksum, skip the
3232 * checksum word itself
3234 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3235 if (i != IXGBE_EEPROM_CHECKSUM)
3236 checksum += local_buffer[i];
3239 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
3240 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3242 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3243 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3246 pointer = local_buffer[i];
3248 /* Skip pointer section if the pointer is invalid. */
3249 if (pointer == 0xFFFF || pointer == 0 ||
3250 pointer >= hw->eeprom.word_size)
3254 case IXGBE_PCIE_GENERAL_PTR:
3255 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3257 case IXGBE_PCIE_CONFIG0_PTR:
3258 case IXGBE_PCIE_CONFIG1_PTR:
3259 size = IXGBE_PCIE_CONFIG_SIZE;
3266 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3267 buffer, buffer_size);
3272 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3274 return (s32)checksum;
3278 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3279 * @hw: pointer to hardware structure
3281 * Returns a negative error code on error, or the 16-bit checksum
3283 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3285 return ixgbe_calc_checksum_X550(hw, NULL, 0);
3289 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3290 * @hw: pointer to hardware structure
3291 * @checksum_val: calculated checksum
3293 * Performs checksum calculation and validates the EEPROM checksum. If the
3294 * caller does not need checksum_val, the value can be NULL.
3296 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3300 u16 read_checksum = 0;
3302 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3304 /* Read the first word from the EEPROM. If this times out or fails, do
3305 * not continue or we could be in for a very long wait while every
3308 status = hw->eeprom.ops.read(hw, 0, &checksum);
3310 DEBUGOUT("EEPROM read failed\n");
3314 status = hw->eeprom.ops.calc_checksum(hw);
3318 checksum = (u16)(status & 0xffff);
3320 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3325 /* Verify read checksum from EEPROM is the same as
3326 * calculated checksum
3328 if (read_checksum != checksum) {
3329 status = IXGBE_ERR_EEPROM_CHECKSUM;
3330 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3331 "Invalid EEPROM checksum");
3334 /* If the user cares, return the calculated checksum */
3336 *checksum_val = checksum;
3342 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3343 * @hw: pointer to hardware structure
3345 * After writing EEPROM to shadow RAM using EEWR register, software calculates
3346 * checksum and updates the EEPROM and instructs the hardware to update
3349 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3354 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3356 /* Read the first word from the EEPROM. If this times out or fails, do
3357 * not continue or we could be in for a very long wait while every
3360 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3362 DEBUGOUT("EEPROM read failed\n");
3366 status = ixgbe_calc_eeprom_checksum_X550(hw);
3370 checksum = (u16)(status & 0xffff);
3372 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3377 status = ixgbe_update_flash_X550(hw);
3383 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3384 * @hw: pointer to hardware structure
3386 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3388 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3390 s32 status = IXGBE_SUCCESS;
3391 union ixgbe_hic_hdr2 buffer;
3393 DEBUGFUNC("ixgbe_update_flash_X550");
3395 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3396 buffer.req.buf_lenh = 0;
3397 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3398 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3400 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3402 IXGBE_HI_COMMAND_TIMEOUT, false);
3408 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3409 * @hw: pointer to hardware structure
3411 * Determines physical layer capabilities of the current configuration.
3413 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3415 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3416 u16 ext_ability = 0;
3418 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3420 hw->phy.ops.identify(hw);
3422 switch (hw->phy.type) {
3423 case ixgbe_phy_x550em_kr:
3424 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3425 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3427 case ixgbe_phy_x550em_kx4:
3428 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3429 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3431 case ixgbe_phy_x550em_ext_t:
3432 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3433 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3435 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3436 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3437 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3438 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3444 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3445 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3447 return physical_layer;
3451 * ixgbe_get_bus_info_x550em - Set PCI bus info
3452 * @hw: pointer to hardware structure
3454 * Sets bus link width and speed to unknown because X550em is
3457 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3460 DEBUGFUNC("ixgbe_get_bus_info_x550em");
3462 hw->bus.width = ixgbe_bus_width_unknown;
3463 hw->bus.speed = ixgbe_bus_speed_unknown;
3465 hw->mac.ops.set_lan_id(hw);
3467 return IXGBE_SUCCESS;
3471 * ixgbe_disable_rx_x550 - Disable RX unit
3473 * Enables the Rx DMA unit for x550
3475 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3477 u32 rxctrl, pfdtxgswc;
3479 struct ixgbe_hic_disable_rxen fw_cmd;
3481 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3483 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3484 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3485 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3486 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3487 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3488 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3489 hw->mac.set_lben = true;
3491 hw->mac.set_lben = false;
3494 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3495 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3496 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3497 fw_cmd.port_number = (u8)hw->bus.lan_id;
3499 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3500 sizeof(struct ixgbe_hic_disable_rxen),
3501 IXGBE_HI_COMMAND_TIMEOUT, true);
3503 /* If we fail - disable RX using register write */
3505 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3506 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3507 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3508 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3515 * ixgbe_enter_lplu_x550em - Transition to low power states
3516 * @hw: pointer to hardware structure
3518 * Configures Low Power Link Up on transition to low power states
3519 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3520 * X557 PHY immediately prior to entering LPLU.
3522 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3524 u16 an_10g_cntl_reg, autoneg_reg, speed;
3526 ixgbe_link_speed lcd_speed;
3530 /* SW LPLU not required on later HW revisions. */
3531 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3532 (IXGBE_FUSES0_REV_MASK &
3533 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3534 return IXGBE_SUCCESS;
3536 /* If blocked by MNG FW, then don't restart AN */
3537 if (ixgbe_check_reset_blocked(hw))
3538 return IXGBE_SUCCESS;
3540 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3541 if (status != IXGBE_SUCCESS)
3544 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3546 if (status != IXGBE_SUCCESS)
3549 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3550 * disabled, then force link down by entering low power mode.
3552 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3553 !(hw->wol_enabled || ixgbe_mng_present(hw)))
3554 return ixgbe_set_copper_phy_power(hw, FALSE);
3557 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3559 if (status != IXGBE_SUCCESS)
3562 /* If no valid LCD link speed, then force link down and exit. */
3563 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3564 return ixgbe_set_copper_phy_power(hw, FALSE);
3566 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3567 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3570 if (status != IXGBE_SUCCESS)
3573 /* If no link now, speed is invalid so take link down */
3574 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3575 if (status != IXGBE_SUCCESS)
3576 return ixgbe_set_copper_phy_power(hw, false);
3578 /* clear everything but the speed bits */
3579 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3581 /* If current speed is already LCD, then exit. */
3582 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3583 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3584 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3585 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3588 /* Clear AN completed indication */
3589 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3590 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3593 if (status != IXGBE_SUCCESS)
3596 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3597 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3600 if (status != IXGBE_SUCCESS)
3603 status = hw->phy.ops.read_reg(hw,
3604 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3605 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3608 if (status != IXGBE_SUCCESS)
3611 save_autoneg = hw->phy.autoneg_advertised;
3613 /* Setup link at least common link speed */
3614 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3616 /* restore autoneg from before setting lplu speed */
3617 hw->phy.autoneg_advertised = save_autoneg;
3623 * ixgbe_get_lcd_x550em - Determine lowest common denominator
3624 * @hw: pointer to hardware structure
3625 * @lcd_speed: pointer to lowest common link speed
3627 * Determine lowest common link speed with link partner.
3629 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3633 u16 word = hw->eeprom.ctrl_word_3;
3635 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3637 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3638 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3641 if (status != IXGBE_SUCCESS)
3644 /* If link partner advertised 1G, return 1G */
3645 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3646 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3650 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3651 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3652 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3655 /* Link partner not capable of lower speeds, return 10G */
3656 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3661 * ixgbe_setup_fc_X550em - Set up flow control
3662 * @hw: pointer to hardware structure
3664 * Called at init time to set up flow control.
3666 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3668 s32 ret_val = IXGBE_SUCCESS;
3669 u32 pause, asm_dir, reg_val;
3671 DEBUGFUNC("ixgbe_setup_fc_X550em");
3673 /* Validate the requested mode */
3674 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3675 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3676 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3677 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3681 /* 10gig parts do not have a word in the EEPROM to determine the
3682 * default flow control setting, so we explicitly set it to full.
3684 if (hw->fc.requested_mode == ixgbe_fc_default)
3685 hw->fc.requested_mode = ixgbe_fc_full;
3687 /* Determine PAUSE and ASM_DIR bits. */
3688 switch (hw->fc.requested_mode) {
3693 case ixgbe_fc_tx_pause:
3697 case ixgbe_fc_rx_pause:
3698 /* Rx Flow control is enabled and Tx Flow control is
3699 * disabled by software override. Since there really
3700 * isn't a way to advertise that we are capable of RX
3701 * Pause ONLY, we will advertise that we support both
3702 * symmetric and asymmetric Rx PAUSE, as such we fall
3703 * through to the fc_full statement. Later, we will
3704 * disable the adapter's ability to send PAUSE frames.
3711 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3712 "Flow control param set incorrectly\n");
3713 ret_val = IXGBE_ERR_CONFIG;
3717 switch (hw->device_id) {
3718 case IXGBE_DEV_ID_X550EM_X_KR:
3719 case IXGBE_DEV_ID_X550EM_A_KR:
3720 case IXGBE_DEV_ID_X550EM_A_KR_L:
3721 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
3722 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3723 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3724 if (ret_val != IXGBE_SUCCESS)
3726 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3727 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3729 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3731 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3732 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
3733 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3734 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3736 /* This device does not fully support AN. */
3737 hw->fc.disable_fc_autoneg = true;
3748 * ixgbe_set_mux - Set mux for port 1 access with CS4227
3749 * @hw: pointer to hardware structure
3750 * @state: set mux if 1, clear if 0
3752 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
3756 if (!hw->bus.lan_id)
3758 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3760 esdp |= IXGBE_ESDP_SDP1;
3762 esdp &= ~IXGBE_ESDP_SDP1;
3763 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
3764 IXGBE_WRITE_FLUSH(hw);
3768 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
3769 * @hw: pointer to hardware structure
3770 * @mask: Mask to specify which semaphore to acquire
3772 * Acquires the SWFW semaphore and sets the I2C MUX
3774 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3778 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
3780 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
3784 if (mask & IXGBE_GSSR_I2C_MASK)
3785 ixgbe_set_mux(hw, 1);
3787 return IXGBE_SUCCESS;
3791 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
3792 * @hw: pointer to hardware structure
3793 * @mask: Mask to specify which semaphore to release
3795 * Releases the SWFW semaphore and sets the I2C MUX
3797 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3799 DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
3801 if (mask & IXGBE_GSSR_I2C_MASK)
3802 ixgbe_set_mux(hw, 0);
3804 ixgbe_release_swfw_sync_X540(hw, mask);
3808 * ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
3809 * @hw: pointer to hardware structure
3810 * @mask: Mask to specify which semaphore to acquire
3812 * Acquires the SWFW semaphore and get the shared phy token as needed
3814 static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
3816 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3817 int retries = FW_PHY_TOKEN_RETRIES;
3818 s32 status = IXGBE_SUCCESS;
3820 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
3823 status = IXGBE_SUCCESS;
3825 status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
3828 if (!(mask & IXGBE_GSSR_TOKEN_SM))
3829 return IXGBE_SUCCESS;
3831 status = ixgbe_get_phy_token(hw);
3832 if (status == IXGBE_SUCCESS)
3833 return IXGBE_SUCCESS;
3836 ixgbe_release_swfw_sync_X540(hw, hmask);
3837 if (status != IXGBE_ERR_TOKEN_RETRY)
3839 msec_delay(FW_PHY_TOKEN_DELAY);
3846 * ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
3847 * @hw: pointer to hardware structure
3848 * @mask: Mask to specify which semaphore to release
3850 * Releases the SWFW semaphore and puts the shared phy token as needed
3852 static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
3854 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3856 DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
3858 if (mask & IXGBE_GSSR_TOKEN_SM)
3859 ixgbe_put_phy_token(hw);
3862 ixgbe_release_swfw_sync_X540(hw, hmask);
3866 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
3867 * @hw: pointer to hardware structure
3869 * Handle external Base T PHY interrupt. If high temperature
3870 * failure alarm then return error, else if link status change
3871 * then setup internal/external PHY link
3873 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
3874 * failure alarm, else return PHY access status.
3876 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
3881 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
3883 if (status != IXGBE_SUCCESS)
3887 return ixgbe_setup_internal_phy(hw);
3889 return IXGBE_SUCCESS;
3893 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
3894 * @hw: pointer to hardware structure
3895 * @speed: new link speed
3896 * @autoneg_wait_to_complete: true when waiting for completion is needed
3898 * Setup internal/external PHY link speed based on link speed, then set
3899 * external PHY auto advertised link speed.
3901 * Returns error status for any failure
3903 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
3904 ixgbe_link_speed speed,
3905 bool autoneg_wait_to_complete)
3908 ixgbe_link_speed force_speed;
3910 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
3912 /* Setup internal/external PHY link speed to iXFI (10G), unless
3913 * only 1G is auto advertised then setup KX link.
3915 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
3916 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3918 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3920 /* If internal link mode is XFI, then setup XFI internal link. */
3921 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3922 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
3924 if (status != IXGBE_SUCCESS)
3928 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
3932 * ixgbe_check_link_t_X550em - Determine link and speed status
3933 * @hw: pointer to hardware structure
3934 * @speed: pointer to link speed
3935 * @link_up: true when link is up
3936 * @link_up_wait_to_complete: bool used to wait for link up or not
3938 * Check that both the MAC and X557 external PHY have link.
3940 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3941 bool *link_up, bool link_up_wait_to_complete)
3946 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3947 return IXGBE_ERR_CONFIG;
3949 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
3950 link_up_wait_to_complete);
3952 /* If check link fails or MAC link is not up, then return */
3953 if (status != IXGBE_SUCCESS || !(*link_up))
3956 /* MAC link is up, so check external PHY link.
3957 * Read this twice back to back to indicate current status.
3959 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3960 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3963 if (status != IXGBE_SUCCESS)
3966 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3967 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3970 if (status != IXGBE_SUCCESS)
3973 /* If external PHY link is not up, then indicate link not up */
3974 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
3977 return IXGBE_SUCCESS;
3981 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
3982 * @hw: pointer to hardware structure
3984 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
3988 status = ixgbe_reset_phy_generic(hw);
3990 if (status != IXGBE_SUCCESS)
3993 /* Configure Link Status Alarm and Temperature Threshold interrupts */
3994 return ixgbe_enable_lasi_ext_t_x550em(hw);
3998 * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
3999 * @hw: pointer to hardware structure
4000 * @led_idx: led number to turn on
4002 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4006 DEBUGFUNC("ixgbe_led_on_t_X550em");
4008 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4009 return IXGBE_ERR_PARAM;
4011 /* To turn on the LED, set mode to ON. */
4012 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4013 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4014 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4015 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4016 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4018 return IXGBE_SUCCESS;
4022 * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4023 * @hw: pointer to hardware structure
4024 * @led_idx: led number to turn off
4026 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4030 DEBUGFUNC("ixgbe_led_off_t_X550em");
4032 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4033 return IXGBE_ERR_PARAM;
4035 /* To turn on the LED, set mode to ON. */
4036 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4037 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4038 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4039 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4040 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4042 return IXGBE_SUCCESS;