drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  44 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw);
  45
  46 /**
  47  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  48  *  @hw: pointer to hardware structure
  49  *
  50  *  Initialize the function pointers and assign the MAC type for X550.
  51  *  Does not touch the hardware.
  52  **/
  53 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  54 {
  55         struct ixgbe_mac_info *mac = &hw->mac;
  56         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  57         s32 ret_val;
  58
  59         DEBUGFUNC("ixgbe_init_ops_X550");
  60
  61         ret_val = ixgbe_init_ops_X540(hw);
  62         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  63         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  64         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  65         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  66         mac->ops.set_source_address_pruning =
  67                         ixgbe_set_source_address_pruning_X550;
  68         mac->ops.set_ethertype_anti_spoofing =
  69                         ixgbe_set_ethertype_anti_spoofing_X550;
  70
  71         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  72         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  73         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  74         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  75         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  76         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  77         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  78         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  79         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  80
  81         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  82         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  83         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  84         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  85         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  86         /* Manageability interface */
  87         mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_x550;
  88         switch (hw->device_id) {
  89         case IXGBE_DEV_ID_X550EM_X_10G_T:
  90         case IXGBE_DEV_ID_X550EM_A_10G_T:
  91                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  92                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  93                 break;
  94         default:
  95                 break;
  96         }
  97         return ret_val;
  98 }
  99
 100 /**
 101  * ixgbe_read_cs4227 - Read CS4227 register
 102  * @hw: pointer to hardware structure
 103  * @reg: register number to write
 104  * @value: pointer to receive value read
 105  *
 106  * Returns status code
 107  **/
 108 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
 109 {
 110         return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
 111 }
 112
 113 /**
 114  * ixgbe_write_cs4227 - Write CS4227 register
 115  * @hw: pointer to hardware structure
 116  * @reg: register number to write
 117  * @value: value to write to register
 118  *
 119  * Returns status code
 120  **/
 121 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 122 {
 123         return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
 124 }
 125
 126 /**
 127  * ixgbe_read_pe - Read register from port expander
 128  * @hw: pointer to hardware structure
 129  * @reg: register number to read
 130  * @value: pointer to receive read value
 131  *
 132  * Returns status code
 133  **/
 134 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 135 {
 136         s32 status;
 137
 138         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 139         if (status != IXGBE_SUCCESS)
 140                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 141                               "port expander access failed with %d\n", status);
 142         return status;
 143 }
 144
 145 /**
 146  * ixgbe_write_pe - Write register to port expander
 147  * @hw: pointer to hardware structure
 148  * @reg: register number to write
 149  * @value: value to write
 150  *
 151  * Returns status code
 152  **/
 153 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 154 {
 155         s32 status;
 156
 157         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 158         if (status != IXGBE_SUCCESS)
 159                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 160                               "port expander access failed with %d\n", status);
 161         return status;
 162 }
 163
 164 /**
 165  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 166  * @hw: pointer to hardware structure
 167  *
 168  * This function assumes that the caller has acquired the proper semaphore.
 169  * Returns error code
 170  **/
 171 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 172 {
 173         s32 status;
 174         u32 retry;
 175         u16 value;
 176         u8 reg;
 177
 178         /* Trigger hard reset. */
 179         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 180         if (status != IXGBE_SUCCESS)
 181                 return status;
 182         reg |= IXGBE_PE_BIT1;
 183         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 184         if (status != IXGBE_SUCCESS)
 185                 return status;
 186
 187         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 188         if (status != IXGBE_SUCCESS)
 189                 return status;
 190         reg &= ~IXGBE_PE_BIT1;
 191         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 192         if (status != IXGBE_SUCCESS)
 193                 return status;
 194
 195         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 196         if (status != IXGBE_SUCCESS)
 197                 return status;
 198         reg &= ~IXGBE_PE_BIT1;
 199         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 200         if (status != IXGBE_SUCCESS)
 201                 return status;
 202
 203         usec_delay(IXGBE_CS4227_RESET_HOLD);
 204
 205         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 206         if (status != IXGBE_SUCCESS)
 207                 return status;
 208         reg |= IXGBE_PE_BIT1;
 209         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 210         if (status != IXGBE_SUCCESS)
 211                 return status;
 212
 213         /* Wait for the reset to complete. */
 214         msec_delay(IXGBE_CS4227_RESET_DELAY);
 215         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 216                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 217                                            &value);
 218                 if (status == IXGBE_SUCCESS &&
 219                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 220                         break;
 221                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 222         }
 223         if (retry == IXGBE_CS4227_RETRIES) {
 224                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 225                         "CS4227 reset did not complete.");
 226                 return IXGBE_ERR_PHY;
 227         }
 228
 229         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 230         if (status != IXGBE_SUCCESS ||
 231             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 232                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 233                         "CS4227 EEPROM did not load successfully.");
 234                 return IXGBE_ERR_PHY;
 235         }
 236
 237         return IXGBE_SUCCESS;
 238 }
 239
 240 /**
 241  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 242  * @hw: pointer to hardware structure
 243  **/
 244 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 245 {
 246         s32 status = IXGBE_SUCCESS;
 247         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 248         u16 value = 0;
 249         u8 retry;
 250
 251         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 252                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 253                 if (status != IXGBE_SUCCESS) {
 254                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 255                                 "semaphore failed with %d", status);
 256                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 257                         continue;
 258                 }
 259
 260                 /* Get status of reset flow. */
 261                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 262
 263                 if (status == IXGBE_SUCCESS &&
 264                     value == IXGBE_CS4227_RESET_COMPLETE)
 265                         goto out;
 266
 267                 if (status != IXGBE_SUCCESS ||
 268                     value != IXGBE_CS4227_RESET_PENDING)
 269                         break;
 270
 271                 /* Reset is pending. Wait and check again. */
 272                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 273                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 274         }
 275
 276         /* If still pending, assume other instance failed. */
 277         if (retry == IXGBE_CS4227_RETRIES) {
 278                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 279                 if (status != IXGBE_SUCCESS) {
 280                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 281                                       "semaphore failed with %d", status);
 282                         return;
 283                 }
 284         }
 285
 286         /* Reset the CS4227. */
 287         status = ixgbe_reset_cs4227(hw);
 288         if (status != IXGBE_SUCCESS) {
 289                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 290                         "CS4227 reset failed: %d", status);
 291                 goto out;
 292         }
 293
 294         /* Reset takes so long, temporarily release semaphore in case the
 295          * other driver instance is waiting for the reset indication.
 296          */
 297         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 298                            IXGBE_CS4227_RESET_PENDING);
 299         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 300         msec_delay(10);
 301         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 302         if (status != IXGBE_SUCCESS) {
 303                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 304                         "semaphore failed with %d", status);
 305                 return;
 306         }
 307
 308         /* Record completion for next time. */
 309         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 310                 IXGBE_CS4227_RESET_COMPLETE);
 311
 312 out:
 313         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 314         msec_delay(hw->eeprom.semaphore_delay);
 315 }
 316
 317 /**
 318  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 319  * @hw: pointer to hardware structure
 320  **/
 321 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 322 {
 323         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 324
 325         if (hw->bus.lan_id) {
 326                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 327                 esdp |= IXGBE_ESDP_SDP1_DIR;
 328         }
 329         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 330         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 331         IXGBE_WRITE_FLUSH(hw);
 332 }
 333
 334 /**
 335  * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
 336  * @hw: pointer to hardware structure
 337  * @reg_addr: 32 bit address of PHY register to read
 338  * @dev_type: always unused
 339  * @phy_data: Pointer to read data from PHY register
 340  */
 341 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 342                                      u32 dev_type, u16 *phy_data)
 343 {
 344         u32 i, data, command;
 345         UNREFERENCED_1PARAMETER(dev_type);
 346
 347         /* Setup and write the read command */
 348         command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 349                   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 350                   IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
 351                   IXGBE_MSCA_MDI_COMMAND;
 352
 353         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 354
 355         /* Check every 10 usec to see if the access completed.
 356          * The MDI Command bit will clear when the operation is
 357          * complete
 358          */
 359         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 360                 usec_delay(10);
 361
 362                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 363                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 364                         break;
 365         }
 366
 367         if (command & IXGBE_MSCA_MDI_COMMAND) {
 368                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 369                               "PHY read command did not complete.\n");
 370                 return IXGBE_ERR_PHY;
 371         }
 372
 373         /* Read operation is complete.  Get the data from MSRWD */
 374         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 375         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 376         *phy_data = (u16)data;
 377
 378         return IXGBE_SUCCESS;
 379 }
 380
 381 /**
 382  * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
 383  * @hw: pointer to hardware structure
 384  * @reg_addr: 32 bit PHY register to write
 385  * @dev_type: always unused
 386  * @phy_data: Data to write to the PHY register
 387  */
 388 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 389                                       u32 dev_type, u16 phy_data)
 390 {
 391         u32 i, command;
 392         UNREFERENCED_1PARAMETER(dev_type);
 393
 394         /* Put the data in the MDI single read and write data register*/
 395         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 396
 397         /* Setup and write the write command */
 398         command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 399                   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 400                   IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
 401                   IXGBE_MSCA_MDI_COMMAND;
 402
 403         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 404
 405         /* Check every 10 usec to see if the access completed.
 406          * The MDI Command bit will clear when the operation is
 407          * complete
 408          */
 409         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 410                 usec_delay(10);
 411
 412                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 413                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 414                         break;
 415         }
 416
 417         if (command & IXGBE_MSCA_MDI_COMMAND) {
 418                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 419                               "PHY write cmd didn't complete\n");
 420                 return IXGBE_ERR_PHY;
 421         }
 422
 423         return IXGBE_SUCCESS;
 424 }
 425
 426 /**
 427  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 428  * @hw: pointer to hardware structure
 429  *
 430  * Returns error code
 431  */
 432 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 433 {
 434         hw->mac.ops.set_lan_id(hw);
 435
 436         ixgbe_read_mng_if_sel_x550em(hw);
 437
 438         switch (hw->device_id) {
 439         case IXGBE_DEV_ID_X550EM_A_SFP:
 440                 return ixgbe_identify_module_generic(hw);
 441         case IXGBE_DEV_ID_X550EM_X_SFP:
 442                 /* set up for CS4227 usage */
 443                 ixgbe_setup_mux_ctl(hw);
 444                 ixgbe_check_cs4227(hw);
 445                 /* Fallthrough */
 446
 447         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 448                 return ixgbe_identify_module_generic(hw);
 449                 break;
 450         case IXGBE_DEV_ID_X550EM_X_KX4:
 451                 hw->phy.type = ixgbe_phy_x550em_kx4;
 452                 break;
 453         case IXGBE_DEV_ID_X550EM_X_KR:
 454         case IXGBE_DEV_ID_X550EM_A_KR:
 455         case IXGBE_DEV_ID_X550EM_A_KR_L:
 456                 hw->phy.type = ixgbe_phy_x550em_kr;
 457                 break;
 458         case IXGBE_DEV_ID_X550EM_A_10G_T:
 459         case IXGBE_DEV_ID_X550EM_A_1G_T:
 460         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 461         case IXGBE_DEV_ID_X550EM_X_1G_T:
 462         case IXGBE_DEV_ID_X550EM_X_10G_T:
 463                 return ixgbe_identify_phy_generic(hw);
 464         default:
 465                 break;
 466         }
 467         return IXGBE_SUCCESS;
 468 }
 469
 470 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 471                                      u32 device_type, u16 *phy_data)
 472 {
 473         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 474         return IXGBE_NOT_IMPLEMENTED;
 475 }
 476
 477 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 478                                       u32 device_type, u16 phy_data)
 479 {
 480         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 481         return IXGBE_NOT_IMPLEMENTED;
 482 }
 483
 484 /**
 485  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 486  * @hw: pointer to the hardware structure
 487  * @addr: I2C bus address to read from
 488  * @reg: I2C device register to read from
 489  * @val: pointer to location to receive read value
 490  *
 491  * Returns an error code on error.
 492  **/
 493 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 494                                            u16 reg, u16 *val)
 495 {
 496         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 497 }
 498
 499 /**
 500  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 501  * @hw: pointer to the hardware structure
 502  * @addr: I2C bus address to read from
 503  * @reg: I2C device register to read from
 504  * @val: pointer to location to receive read value
 505  *
 506  * Returns an error code on error.
 507  **/
 508 STATIC s32
 509 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 510                                          u16 reg, u16 *val)
 511 {
 512         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 513 }
 514
 515 /**
 516  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 517  * @hw: pointer to the hardware structure
 518  * @addr: I2C bus address to write to
 519  * @reg: I2C device register to write to
 520  * @val: value to write
 521  *
 522  * Returns an error code on error.
 523  **/
 524 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 525                                             u8 addr, u16 reg, u16 val)
 526 {
 527         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 528 }
 529
 530 /**
 531  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 532  * @hw: pointer to the hardware structure
 533  * @addr: I2C bus address to write to
 534  * @reg: I2C device register to write to
 535  * @val: value to write
 536  *
 537  * Returns an error code on error.
 538  **/
 539 STATIC s32
 540 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 541                                           u8 addr, u16 reg, u16 val)
 542 {
 543         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 544 }
 545
 546 /**
 547 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 548 *  @hw: pointer to hardware structure
 549 *
 550 *  Initialize the function pointers and for MAC type X550EM.
 551 *  Does not touch the hardware.
 552 **/
 553 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 554 {
 555         struct ixgbe_mac_info *mac = &hw->mac;
 556         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 557         struct ixgbe_phy_info *phy = &hw->phy;
 558         s32 ret_val;
 559
 560         DEBUGFUNC("ixgbe_init_ops_X550EM");
 561
 562         /* Similar to X550 so start there. */
 563         ret_val = ixgbe_init_ops_X550(hw);
 564
 565         /* Since this function eventually calls
 566          * ixgbe_init_ops_540 by design, we are setting
 567          * the pointers to NULL explicitly here to overwrite
 568          * the values being set in the x540 function.
 569          */
 570         /* Thermal sensor not supported in x550EM */
 571         mac->ops.get_thermal_sensor_data = NULL;
 572         mac->ops.init_thermal_sensor_thresh = NULL;
 573         mac->thermal_sensor_enabled = false;
 574
 575         /* FCOE not supported in x550EM */
 576         mac->ops.get_san_mac_addr = NULL;
 577         mac->ops.set_san_mac_addr = NULL;
 578         mac->ops.get_wwn_prefix = NULL;
 579         mac->ops.get_fcoe_boot_status = NULL;
 580
 581         /* IPsec not supported in x550EM */
 582         mac->ops.disable_sec_rx_path = NULL;
 583         mac->ops.enable_sec_rx_path = NULL;
 584
 585         /* AUTOC register is not present in x550EM. */
 586         mac->ops.prot_autoc_read = NULL;
 587         mac->ops.prot_autoc_write = NULL;
 588
 589         /* X550EM bus type is internal*/
 590         hw->bus.type = ixgbe_bus_type_internal;
 591         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 592
 593
 594         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 595         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 596         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 597         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 598         mac->ops.get_supported_physical_layer =
 599                                     ixgbe_get_supported_physical_layer_X550em;
 600
 601         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 602                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 603         else
 604                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 605
 606         switch (hw->device_id) {
 607         case IXGBE_DEV_ID_X550EM_X_KR:
 608         case IXGBE_DEV_ID_X550EM_A_KR:
 609         case IXGBE_DEV_ID_X550EM_A_KR_L:
 610                 break;
 611         default:
 612                 mac->ops.setup_eee = NULL;
 613         }
 614
 615         /* PHY */
 616         phy->ops.init = ixgbe_init_phy_ops_X550em;
 617         phy->ops.identify = ixgbe_identify_phy_x550em;
 618         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 619                 phy->ops.set_phy_power = NULL;
 620
 621
 622         /* EEPROM */
 623         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 624         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 625         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 626         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 627         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 628         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 629         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 630         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 631
 632         return ret_val;
 633 }
 634
 635 /**
 636 *  ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
 637 *  @hw: pointer to hardware structure
 638 *
 639 *  Initialize the function pointers and for MAC type X550EM_a.
 640 *  Does not touch the hardware.
 641 **/
 642 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
 643 {
 644         struct ixgbe_mac_info *mac = &hw->mac;
 645         s32 ret_val;
 646
 647         DEBUGFUNC("ixgbe_init_ops_X550EM_a");
 648
 649         /* Start with generic X550EM init */
 650         ret_val = ixgbe_init_ops_X550EM(hw);
 651
 652         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
 653             hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) {
 654                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 655                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 656         } else {
 657                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
 658                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
 659         }
 660         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
 661         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
 662
 663         switch (mac->ops.get_media_type(hw)) {
 664         case ixgbe_media_type_fiber:
 665                 mac->ops.setup_fc = NULL;
 666                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
 667                 break;
 668         case ixgbe_media_type_backplane:
 669                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
 670                 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
 671                 break;
 672         default:
 673                 break;
 674         }
 675
 676         if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T) ||
 677                 (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)) {
 678                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
 679                 mac->ops.setup_fc = ixgbe_setup_fc_sgmii_x550em_a;
 680         }
 681
 682         return ret_val;
 683 }
 684
 685 /**
 686 *  ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
 687 *  @hw: pointer to hardware structure
 688 *
 689 *  Initialize the function pointers and for MAC type X550EM_x.
 690 *  Does not touch the hardware.
 691 **/
 692 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
 693 {
 694         struct ixgbe_mac_info *mac = &hw->mac;
 695         struct ixgbe_link_info *link = &hw->link;
 696         s32 ret_val;
 697
 698         DEBUGFUNC("ixgbe_init_ops_X550EM_x");
 699
 700         /* Start with generic X550EM init */
 701         ret_val = ixgbe_init_ops_X550EM(hw);
 702
 703         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 704         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 705         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 706         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 707         link->ops.read_link = ixgbe_read_i2c_combined_generic;
 708         link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
 709         link->ops.write_link = ixgbe_write_i2c_combined_generic;
 710         link->ops.write_link_unlocked =
 711                                       ixgbe_write_i2c_combined_generic_unlocked;
 712         link->addr = IXGBE_CS4227;
 713
 714         return ret_val;
 715 }
 716
 717 /**
 718  *  ixgbe_dmac_config_X550
 719  *  @hw: pointer to hardware structure
 720  *
 721  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 722  *  When disabling dmac, dmac enable dmac bit is cleared.
 723  **/
 724 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 725 {
 726         u32 reg, high_pri_tc;
 727
 728         DEBUGFUNC("ixgbe_dmac_config_X550");
 729
 730         /* Disable DMA coalescing before configuring */
 731         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 732         reg &= ~IXGBE_DMACR_DMAC_EN;
 733         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 734
 735         /* Disable DMA Coalescing if the watchdog timer is 0 */
 736         if (!hw->mac.dmac_config.watchdog_timer)
 737                 goto out;
 738
 739         ixgbe_dmac_config_tcs_X550(hw);
 740
 741         /* Configure DMA Coalescing Control Register */
 742         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 743
 744         /* Set the watchdog timer in units of 40.96 usec */
 745         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 746         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 747
 748         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 749         /* If fcoe is enabled, set high priority traffic class */
 750         if (hw->mac.dmac_config.fcoe_en) {
 751                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 752                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 753                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 754         }
 755         reg |= IXGBE_DMACR_EN_MNG_IND;
 756
 757         /* Enable DMA coalescing after configuration */
 758         reg |= IXGBE_DMACR_DMAC_EN;
 759         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 760
 761 out:
 762         return IXGBE_SUCCESS;
 763 }
 764
 765 /**
 766  *  ixgbe_dmac_config_tcs_X550
 767  *  @hw: pointer to hardware structure
 768  *
 769  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 770  *  be cleared before configuring.
 771  **/
 772 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 773 {
 774         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 775
 776         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 777
 778         /* Configure DMA coalescing enabled */
 779         switch (hw->mac.dmac_config.link_speed) {
 780         case IXGBE_LINK_SPEED_10_FULL:
 781         case IXGBE_LINK_SPEED_100_FULL:
 782                 pb_headroom = IXGBE_DMACRXT_100M;
 783                 break;
 784         case IXGBE_LINK_SPEED_1GB_FULL:
 785                 pb_headroom = IXGBE_DMACRXT_1G;
 786                 break;
 787         default:
 788                 pb_headroom = IXGBE_DMACRXT_10G;
 789                 break;
 790         }
 791
 792         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 793                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 794
 795         /* Set the per Rx packet buffer receive threshold */
 796         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 797                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 798                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 799
 800                 if (tc < hw->mac.dmac_config.num_tcs) {
 801                         /* Get Rx PB size */
 802                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 803                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 804                                 IXGBE_RXPBSIZE_SHIFT;
 805
 806                         /* Calculate receive buffer threshold in kilobytes */
 807                         if (rx_pb_size > pb_headroom)
 808                                 rx_pb_size = rx_pb_size - pb_headroom;
 809                         else
 810                                 rx_pb_size = 0;
 811
 812                         /* Minimum of MFS shall be set for DMCTH */
 813                         reg |= (rx_pb_size > maxframe_size_kb) ?
 814                                 rx_pb_size : maxframe_size_kb;
 815                 }
 816                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 817         }
 818         return IXGBE_SUCCESS;
 819 }
 820
 821 /**
 822  *  ixgbe_dmac_update_tcs_X550
 823  *  @hw: pointer to hardware structure
 824  *
 825  *  Disables dmac, updates per TC settings, and then enables dmac.
 826  **/
 827 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 828 {
 829         u32 reg;
 830
 831         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 832
 833         /* Disable DMA coalescing before configuring */
 834         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 835         reg &= ~IXGBE_DMACR_DMAC_EN;
 836         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 837
 838         ixgbe_dmac_config_tcs_X550(hw);
 839
 840         /* Enable DMA coalescing after configuration */
 841         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 842         reg |= IXGBE_DMACR_DMAC_EN;
 843         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 844
 845         return IXGBE_SUCCESS;
 846 }
 847
 848 /**
 849  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 850  *  @hw: pointer to hardware structure
 851  *
 852  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 853  *  ixgbe_hw struct in order to set up EEPROM access.
 854  **/
 855 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 856 {
 857         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 858         u32 eec;
 859         u16 eeprom_size;
 860
 861         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 862
 863         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 864                 eeprom->semaphore_delay = 10;
 865                 eeprom->type = ixgbe_flash;
 866
 867                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 868                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 869                                     IXGBE_EEC_SIZE_SHIFT);
 870                 eeprom->word_size = 1 << (eeprom_size +
 871                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 872
 873                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 874                           eeprom->type, eeprom->word_size);
 875         }
 876
 877         return IXGBE_SUCCESS;
 878 }
 879
 880 /**
 881  * ixgbe_enable_eee_x550 - Enable EEE support
 882  * @hw: pointer to hardware structure
 883  */
 884 STATIC s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
 885 {
 886         u16 autoneg_eee_reg;
 887         u32 link_reg;
 888         s32 status;
 889
 890         if (hw->mac.type == ixgbe_mac_X550) {
 891                 /* Advertise EEE capability */
 892                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 893                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 894                                      &autoneg_eee_reg);
 895
 896                 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 897                                     IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 898                                     IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 899
 900                 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 901                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 902                                       autoneg_eee_reg);
 903                 return IXGBE_SUCCESS;
 904         }
 905
 906         switch (hw->device_id) {
 907         case IXGBE_DEV_ID_X550EM_X_KR:
 908         case IXGBE_DEV_ID_X550EM_A_KR:
 909         case IXGBE_DEV_ID_X550EM_A_KR_L:
 910                 status = hw->mac.ops.read_iosf_sb_reg(hw,
 911                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 912                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 913                 if (status != IXGBE_SUCCESS)
 914                         return status;
 915
 916                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 917                             IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 918
 919                 /* Don't advertise FEC capability when EEE enabled. */
 920                 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 921
 922                 status = hw->mac.ops.write_iosf_sb_reg(hw,
 923                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 924                                         IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 925                 if (status != IXGBE_SUCCESS)
 926                         return status;
 927                 break;
 928         default:
 929                 break;
 930         }
 931
 932         return IXGBE_SUCCESS;
 933 }
 934
 935 /**
 936  * ixgbe_disable_eee_x550 - Disable EEE support
 937  * @hw: pointer to hardware structure
 938  */
 939 STATIC s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
 940 {
 941         u16 autoneg_eee_reg;
 942         u32 link_reg;
 943         s32 status;
 944
 945         if (hw->mac.type == ixgbe_mac_X550) {
 946                 /* Disable advertised EEE capability */
 947                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 948                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 949                                      &autoneg_eee_reg);
 950
 951                 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 952                                      IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 953                                      IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 954
 955                 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 956                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 957                                       autoneg_eee_reg);
 958                 return IXGBE_SUCCESS;
 959         }
 960
 961         switch (hw->device_id) {
 962         case IXGBE_DEV_ID_X550EM_X_KR:
 963         case IXGBE_DEV_ID_X550EM_A_KR:
 964         case IXGBE_DEV_ID_X550EM_A_KR_L:
 965                 status = hw->mac.ops.read_iosf_sb_reg(hw,
 966                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 967                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 968                 if (status != IXGBE_SUCCESS)
 969                         return status;
 970
 971                 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 972                               IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 973
 974                 /* Advertise FEC capability when EEE is disabled. */
 975                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 976
 977                 status = hw->mac.ops.write_iosf_sb_reg(hw,
 978                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 979                                         IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 980                 if (status != IXGBE_SUCCESS)
 981                         return status;
 982                 break;
 983         default:
 984                 break;
 985         }
 986
 987         return IXGBE_SUCCESS;
 988 }
 989
 990 /**
 991  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 992  *  @hw: pointer to the HW structure
 993  *  @enable_eee: boolean flag to enable EEE
 994  *
 995  *  Enable/disable EEE based on enable_eee flag.
 996  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 997  *  are modified.
 998  *
 999  **/
1000 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
1001 {
1002         s32 status;
1003         u32 eeer;
1004
1005         DEBUGFUNC("ixgbe_setup_eee_X550");
1006
1007         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
1008         /* Enable or disable EEE per flag */
1009         if (enable_eee) {
1010                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1011
1012                 /* Not supported on first revision of X550EM_x. */
1013                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
1014                     !(IXGBE_FUSES0_REV_MASK &
1015                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
1016                         return IXGBE_SUCCESS;
1017
1018                 status = ixgbe_enable_eee_x550(hw);
1019                 if (status)
1020                         return status;
1021         } else {
1022                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1023
1024                 status = ixgbe_disable_eee_x550(hw);
1025                 if (status)
1026                         return status;
1027         }
1028         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
1029
1030         return IXGBE_SUCCESS;
1031 }
1032
1033 /**
1034  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1035  * @hw: pointer to hardware structure
1036  * @enable: enable or disable source address pruning
1037  * @pool: Rx pool to set source address pruning for
1038  **/
1039 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1040                                            unsigned int pool)
1041 {
1042         u64 pfflp;
1043
1044         /* max rx pool is 63 */
1045         if (pool > 63)
1046                 return;
1047
1048         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1049         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1050
1051         if (enable)
1052                 pfflp |= (1ULL << pool);
1053         else
1054                 pfflp &= ~(1ULL << pool);
1055
1056         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1057         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1058 }
1059
1060 /**
1061  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1062  *  @hw: pointer to hardware structure
1063  *  @enable: enable or disable switch for Ethertype anti-spoofing
1064  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1065  *
1066  **/
1067 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1068                 bool enable, int vf)
1069 {
1070         int vf_target_reg = vf >> 3;
1071         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1072         u32 pfvfspoof;
1073
1074         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1075
1076         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1077         if (enable)
1078                 pfvfspoof |= (1 << vf_target_shift);
1079         else
1080                 pfvfspoof &= ~(1 << vf_target_shift);
1081
1082         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1083 }
1084
1085 /**
1086  * ixgbe_iosf_wait - Wait for IOSF command completion
1087  * @hw: pointer to hardware structure
1088  * @ctrl: pointer to location to receive final IOSF control value
1089  *
1090  * Returns failing status on timeout
1091  *
1092  * Note: ctrl can be NULL if the IOSF control register value is not needed
1093  **/
1094 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1095 {
1096         u32 i, command = 0;
1097
1098         /* Check every 10 usec to see if the address cycle completed.
1099          * The SB IOSF BUSY bit will clear when the operation is
1100          * complete
1101          */
1102         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1103                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1104                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1105                         break;
1106                 usec_delay(10);
1107         }
1108         if (ctrl)
1109                 *ctrl = command;
1110         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1111                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1112                 return IXGBE_ERR_PHY;
1113         }
1114
1115         return IXGBE_SUCCESS;
1116 }
1117
1118 /**
1119  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register
1120  *  of the IOSF device
1121  *  @hw: pointer to hardware structure
1122  *  @reg_addr: 32 bit PHY register to write
1123  *  @device_type: 3 bit device type
1124  *  @data: Data to write to the register
1125  **/
1126 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1127                             u32 device_type, u32 data)
1128 {
1129         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1130         u32 command, error;
1131         s32 ret;
1132
1133         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1134         if (ret != IXGBE_SUCCESS)
1135                 return ret;
1136
1137         ret = ixgbe_iosf_wait(hw, NULL);
1138         if (ret != IXGBE_SUCCESS)
1139                 goto out;
1140
1141         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1142                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1143
1144         /* Write IOSF control register */
1145         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1146
1147         /* Write IOSF data register */
1148         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1149
1150         ret = ixgbe_iosf_wait(hw, &command);
1151
1152         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1153                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1154                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1155                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1156                               "Failed to write, error %x\n", error);
1157                 ret = IXGBE_ERR_PHY;
1158         }
1159
1160 out:
1161         ixgbe_release_swfw_semaphore(hw, gssr);
1162         return ret;
1163 }
1164
1165 /**
1166  *  ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device
1167  *  @hw: pointer to hardware structure
1168  *  @reg_addr: 32 bit PHY register to write
1169  *  @device_type: 3 bit device type
1170  *  @data: Pointer to read data from the register
1171  **/
1172 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1173                            u32 device_type, u32 *data)
1174 {
1175         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1176         u32 command, error;
1177         s32 ret;
1178
1179         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1180         if (ret != IXGBE_SUCCESS)
1181                 return ret;
1182
1183         ret = ixgbe_iosf_wait(hw, NULL);
1184         if (ret != IXGBE_SUCCESS)
1185                 goto out;
1186
1187         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1188                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1189
1190         /* Write IOSF control register */
1191         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1192
1193         ret = ixgbe_iosf_wait(hw, &command);
1194
1195         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1196                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1197                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1198                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1199                                 "Failed to read, error %x\n", error);
1200                 ret = IXGBE_ERR_PHY;
1201         }
1202
1203         if (ret == IXGBE_SUCCESS)
1204                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1205
1206 out:
1207         ixgbe_release_swfw_semaphore(hw, gssr);
1208         return ret;
1209 }
1210
1211 /**
1212  * ixgbe_get_phy_token - Get the token for shared phy access
1213  * @hw: Pointer to hardware structure
1214  */
1215
1216 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1217 {
1218         struct ixgbe_hic_phy_token_req token_cmd;
1219         s32 status;
1220
1221         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1222         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1223         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1224         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1225         token_cmd.port_number = hw->bus.lan_id;
1226         token_cmd.command_type = FW_PHY_TOKEN_REQ;
1227         token_cmd.pad = 0;
1228         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1229                                               sizeof(token_cmd),
1230                                               IXGBE_HI_COMMAND_TIMEOUT,
1231                                               true);
1232         if (status)
1233                 return status;
1234         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1235                 return IXGBE_SUCCESS;
1236         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1237                 return IXGBE_ERR_FW_RESP_INVALID;
1238
1239         return IXGBE_ERR_TOKEN_RETRY;
1240 }
1241
1242 /**
1243  * ixgbe_put_phy_token - Put the token for shared phy access
1244  * @hw: Pointer to hardware structure
1245  */
1246
1247 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1248 {
1249         struct ixgbe_hic_phy_token_req token_cmd;
1250         s32 status;
1251
1252         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1253         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1254         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1255         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1256         token_cmd.port_number = hw->bus.lan_id;
1257         token_cmd.command_type = FW_PHY_TOKEN_REL;
1258         token_cmd.pad = 0;
1259         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1260                                               sizeof(token_cmd),
1261                                               IXGBE_HI_COMMAND_TIMEOUT,
1262                                               true);
1263         if (status)
1264                 return status;
1265         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1266                 return IXGBE_SUCCESS;
1267
1268         DEBUGOUT("Put PHY Token host interface command failed");
1269         return IXGBE_ERR_FW_RESP_INVALID;
1270 }
1271
1272 /**
1273  *  ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1274  *  of the IOSF device
1275  *  @hw: pointer to hardware structure
1276  *  @reg_addr: 32 bit PHY register to write
1277  *  @device_type: 3 bit device type
1278  *  @data: Data to write to the register
1279  **/
1280 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1281                                   u32 device_type, u32 data)
1282 {
1283         struct ixgbe_hic_internal_phy_req write_cmd;
1284         s32 status;
1285         UNREFERENCED_1PARAMETER(device_type);
1286
1287         memset(&write_cmd, 0, sizeof(write_cmd));
1288         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1289         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1290         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1291         write_cmd.port_number = hw->bus.lan_id;
1292         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1293         write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1294         write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1295
1296         status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1297                                               sizeof(write_cmd),
1298                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1299
1300         return status;
1301 }
1302
1303 /**
1304  *  ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device
1305  *  @hw: pointer to hardware structure
1306  *  @reg_addr: 32 bit PHY register to write
1307  *  @device_type: 3 bit device type
1308  *  @data: Pointer to read data from the register
1309  **/
1310 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1311                                  u32 device_type, u32 *data)
1312 {
1313         union {
1314                 struct ixgbe_hic_internal_phy_req cmd;
1315                 struct ixgbe_hic_internal_phy_resp rsp;
1316         } hic;
1317         s32 status;
1318         UNREFERENCED_1PARAMETER(device_type);
1319
1320         memset(&hic, 0, sizeof(hic));
1321         hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1322         hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1323         hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1324         hic.cmd.port_number = hw->bus.lan_id;
1325         hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1326         hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1327
1328         status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1329                                               sizeof(hic.cmd),
1330                                               IXGBE_HI_COMMAND_TIMEOUT, true);
1331
1332         /* Extract the register value from the response. */
1333         *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1334
1335         return status;
1336 }
1337
1338 /**
1339  *  ixgbe_disable_mdd_X550
1340  *  @hw: pointer to hardware structure
1341  *
1342  *  Disable malicious driver detection
1343  **/
1344 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1345 {
1346         u32 reg;
1347
1348         DEBUGFUNC("ixgbe_disable_mdd_X550");
1349
1350         /* Disable MDD for TX DMA and interrupt */
1351         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1352         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1353         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1354
1355         /* Disable MDD for RX and interrupt */
1356         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1357         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1358         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1359 }
1360
1361 /**
1362  *  ixgbe_enable_mdd_X550
1363  *  @hw: pointer to hardware structure
1364  *
1365  *  Enable malicious driver detection
1366  **/
1367 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1368 {
1369         u32 reg;
1370
1371         DEBUGFUNC("ixgbe_enable_mdd_X550");
1372
1373         /* Enable MDD for TX DMA and interrupt */
1374         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1375         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1376         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1377
1378         /* Enable MDD for RX and interrupt */
1379         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1380         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1381         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1382 }
1383
1384 /**
1385  *  ixgbe_restore_mdd_vf_X550
1386  *  @hw: pointer to hardware structure
1387  *  @vf: vf index
1388  *
1389  *  Restore VF that was disabled during malicious driver detection event
1390  **/
1391 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1392 {
1393         u32 idx, reg, num_qs, start_q, bitmask;
1394
1395         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1396
1397         /* Map VF to queues */
1398         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1399         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1400         case IXGBE_MRQC_VMDQRT8TCEN:
1401                 num_qs = 8;  /* 16 VFs / pools */
1402                 bitmask = 0x000000FF;
1403                 break;
1404         case IXGBE_MRQC_VMDQRSS32EN:
1405         case IXGBE_MRQC_VMDQRT4TCEN:
1406                 num_qs = 4;  /* 32 VFs / pools */
1407                 bitmask = 0x0000000F;
1408                 break;
1409         default:            /* 64 VFs / pools */
1410                 num_qs = 2;
1411                 bitmask = 0x00000003;
1412                 break;
1413         }
1414         start_q = vf * num_qs;
1415
1416         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1417         idx = start_q / 32;
1418         reg = 0;
1419         reg |= (bitmask << (start_q % 32));
1420         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1421         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1422 }
1423
1424 /**
1425  *  ixgbe_mdd_event_X550
1426  *  @hw: pointer to hardware structure
1427  *  @vf_bitmap: vf bitmap of malicious vfs
1428  *
1429  *  Handle malicious driver detection event.
1430  **/
1431 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1432 {
1433         u32 wqbr;
1434         u32 i, j, reg, q, shift, vf, idx;
1435
1436         DEBUGFUNC("ixgbe_mdd_event_X550");
1437
1438         /* figure out pool size for mapping to vf's */
1439         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1440         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1441         case IXGBE_MRQC_VMDQRT8TCEN:
1442                 shift = 3;  /* 16 VFs / pools */
1443                 break;
1444         case IXGBE_MRQC_VMDQRSS32EN:
1445         case IXGBE_MRQC_VMDQRT4TCEN:
1446                 shift = 2;  /* 32 VFs / pools */
1447                 break;
1448         default:
1449                 shift = 1;  /* 64 VFs / pools */
1450                 break;
1451         }
1452
1453         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1454         for (i = 0; i < 4; i++) {
1455                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1456                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1457
1458                 if (!wqbr)
1459                         continue;
1460
1461                 /* Get malicious queue */
1462                 for (j = 0; j < 32 && wqbr; j++) {
1463
1464                         if (!(wqbr & (1 << j)))
1465                                 continue;
1466
1467                         /* Get queue from bitmask */
1468                         q = j + (i * 32);
1469
1470                         /* Map queue to vf */
1471                         vf = (q >> shift);
1472
1473                         /* Set vf bit in vf_bitmap */
1474                         idx = vf / 32;
1475                         vf_bitmap[idx] |= (1 << (vf % 32));
1476                         wqbr &= ~(1 << j);
1477                 }
1478         }
1479 }
1480
1481 /**
1482  *  ixgbe_get_media_type_X550em - Get media type
1483  *  @hw: pointer to hardware structure
1484  *
1485  *  Returns the media type (fiber, copper, backplane)
1486  */
1487 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1488 {
1489         enum ixgbe_media_type media_type;
1490
1491         DEBUGFUNC("ixgbe_get_media_type_X550em");
1492
1493         /* Detect if there is a copper PHY attached. */
1494         switch (hw->device_id) {
1495         case IXGBE_DEV_ID_X550EM_X_KR:
1496         case IXGBE_DEV_ID_X550EM_X_KX4:
1497         case IXGBE_DEV_ID_X550EM_A_KR:
1498         case IXGBE_DEV_ID_X550EM_A_KR_L:
1499                 media_type = ixgbe_media_type_backplane;
1500                 break;
1501         case IXGBE_DEV_ID_X550EM_X_SFP:
1502         case IXGBE_DEV_ID_X550EM_A_SFP:
1503         case IXGBE_DEV_ID_X550EM_A_SFP_N:
1504         case IXGBE_DEV_ID_X550EM_A_QSFP:
1505         case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1506                 media_type = ixgbe_media_type_fiber;
1507                 break;
1508         case IXGBE_DEV_ID_X550EM_X_1G_T:
1509         case IXGBE_DEV_ID_X550EM_X_10G_T:
1510         case IXGBE_DEV_ID_X550EM_A_10G_T:
1511                 media_type = ixgbe_media_type_copper;
1512                 break;
1513         case IXGBE_DEV_ID_X550EM_A_SGMII:
1514         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1515                 media_type = ixgbe_media_type_backplane;
1516                 hw->phy.type = ixgbe_phy_sgmii;
1517                 break;
1518         case IXGBE_DEV_ID_X550EM_A_1G_T:
1519         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1520                 media_type = ixgbe_media_type_copper;
1521                 break;
1522         default:
1523                 media_type = ixgbe_media_type_unknown;
1524                 break;
1525         }
1526         return media_type;
1527 }
1528
1529 /**
1530  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1531  *  @hw: pointer to hardware structure
1532  *  @linear: true if SFP module is linear
1533  */
1534 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1535 {
1536         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1537
1538         switch (hw->phy.sfp_type) {
1539         case ixgbe_sfp_type_not_present:
1540                 return IXGBE_ERR_SFP_NOT_PRESENT;
1541         case ixgbe_sfp_type_da_cu_core0:
1542         case ixgbe_sfp_type_da_cu_core1:
1543                 *linear = true;
1544                 break;
1545         case ixgbe_sfp_type_srlr_core0:
1546         case ixgbe_sfp_type_srlr_core1:
1547         case ixgbe_sfp_type_da_act_lmt_core0:
1548         case ixgbe_sfp_type_da_act_lmt_core1:
1549         case ixgbe_sfp_type_1g_sx_core0:
1550         case ixgbe_sfp_type_1g_sx_core1:
1551         case ixgbe_sfp_type_1g_lx_core0:
1552         case ixgbe_sfp_type_1g_lx_core1:
1553                 *linear = false;
1554                 break;
1555         case ixgbe_sfp_type_unknown:
1556         case ixgbe_sfp_type_1g_cu_core0:
1557         case ixgbe_sfp_type_1g_cu_core1:
1558         default:
1559                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1560         }
1561
1562         return IXGBE_SUCCESS;
1563 }
1564
1565 /**
1566  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1567  *  @hw: pointer to hardware structure
1568  *
1569  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1570  **/
1571 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1572 {
1573         s32 status;
1574         bool linear;
1575
1576         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1577
1578         status = ixgbe_identify_module_generic(hw);
1579
1580         if (status != IXGBE_SUCCESS)
1581                 return status;
1582
1583         /* Check if SFP module is supported */
1584         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1585
1586         return status;
1587 }
1588
1589 /**
1590  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1591  *  @hw: pointer to hardware structure
1592  */
1593 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1594 {
1595         s32 status;
1596         bool linear;
1597
1598         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1599
1600         /* Check if SFP module is supported */
1601         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1602
1603         if (status != IXGBE_SUCCESS)
1604                 return status;
1605
1606         ixgbe_init_mac_link_ops_X550em(hw);
1607         hw->phy.ops.reset = NULL;
1608
1609         return IXGBE_SUCCESS;
1610 }
1611
1612 /**
1613 *  ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1614 *  internal PHY
1615 *  @hw: pointer to hardware structure
1616 **/
1617 STATIC s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1618 {
1619         s32 status;
1620         u32 link_ctrl;
1621
1622         /* Restart auto-negotiation. */
1623         status = hw->mac.ops.read_iosf_sb_reg(hw,
1624                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1625                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1626
1627         if (status) {
1628                 DEBUGOUT("Auto-negotiation did not complete\n");
1629                 return status;
1630         }
1631
1632         link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1633         status = hw->mac.ops.write_iosf_sb_reg(hw,
1634                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1635                                         IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1636
1637         if (hw->mac.type == ixgbe_mac_X550EM_a) {
1638                 u32 flx_mask_st20;
1639
1640                 /* Indicate to FW that AN restart has been asserted */
1641                 status = hw->mac.ops.read_iosf_sb_reg(hw,
1642                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1643                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1644
1645                 if (status) {
1646                         DEBUGOUT("Auto-negotiation did not complete\n");
1647                         return status;
1648                 }
1649
1650                 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1651                 status = hw->mac.ops.write_iosf_sb_reg(hw,
1652                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1653                                 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1654         }
1655
1656         return status;
1657 }
1658
1659 /**
1660  * ixgbe_setup_sgmii - Set up link for sgmii
1661  * @hw: pointer to hardware structure
1662  */
1663 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1664                              bool autoneg_wait)
1665 {
1666         struct ixgbe_mac_info *mac = &hw->mac;
1667         u32 lval, sval, flx_val;
1668         s32 rc;
1669
1670         rc = mac->ops.read_iosf_sb_reg(hw,
1671                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1672                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1673         if (rc)
1674                 return rc;
1675
1676         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1677         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1678         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1679         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1680         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1681         rc = mac->ops.write_iosf_sb_reg(hw,
1682                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1683                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1684         if (rc)
1685                 return rc;
1686
1687         rc = mac->ops.read_iosf_sb_reg(hw,
1688                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1689                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1690         if (rc)
1691                 return rc;
1692
1693         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1694         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1695         rc = mac->ops.write_iosf_sb_reg(hw,
1696                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1697                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1698         if (rc)
1699                 return rc;
1700
1701         rc = mac->ops.read_iosf_sb_reg(hw,
1702                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1703                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1704         if (rc)
1705                 return rc;
1706
1707         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1708         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1709         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1710         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1711         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1712
1713         rc = mac->ops.write_iosf_sb_reg(hw,
1714                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1715                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1716         if (rc)
1717                 return rc;
1718
1719         rc = ixgbe_restart_an_internal_phy_x550em(hw);
1720         if (rc)
1721                 return rc;
1722
1723         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1724 }
1725
1726 /**
1727  * ixgbe_setup_sgmii_m88 - Set up link for sgmii with Marvell PHYs
1728  * @hw: pointer to hardware structure
1729  */
1730 STATIC s32 ixgbe_setup_sgmii_m88(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1731                                  bool autoneg_wait)
1732 {
1733         struct ixgbe_mac_info *mac = &hw->mac;
1734         u32 lval, sval, flx_val;
1735         s32 rc;
1736
1737         rc = mac->ops.read_iosf_sb_reg(hw,
1738                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1739                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1740         if (rc)
1741                 return rc;
1742
1743         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1744         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1745         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1746         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1747         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1748         rc = mac->ops.write_iosf_sb_reg(hw,
1749                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1750                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1751         if (rc)
1752                 return rc;
1753
1754         rc = mac->ops.read_iosf_sb_reg(hw,
1755                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1756                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1757         if (rc)
1758                 return rc;
1759
1760         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1761         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1762         rc = mac->ops.write_iosf_sb_reg(hw,
1763                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1764                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1765         if (rc)
1766                 return rc;
1767
1768         rc = mac->ops.write_iosf_sb_reg(hw,
1769                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1770                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1771         if (rc)
1772                 return rc;
1773
1774         rc = mac->ops.read_iosf_sb_reg(hw,
1775                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1776                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1777         if (rc)
1778                 return rc;
1779
1780         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1781         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1782         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1783         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1784         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1785
1786         rc = mac->ops.write_iosf_sb_reg(hw,
1787                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1788                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1789         if (rc)
1790                 return rc;
1791
1792         rc = ixgbe_restart_an_internal_phy_x550em(hw);
1793
1794         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1795 }
1796
1797 /**
1798  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1799  *  @hw: pointer to hardware structure
1800  */
1801 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1802 {
1803         struct ixgbe_mac_info *mac = &hw->mac;
1804
1805         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1806
1807         switch (hw->mac.ops.get_media_type(hw)) {
1808         case ixgbe_media_type_fiber:
1809                 /* CS4227 does not support autoneg, so disable the laser control
1810                  * functions for SFP+ fiber
1811                  */
1812                 mac->ops.disable_tx_laser = NULL;
1813                 mac->ops.enable_tx_laser = NULL;
1814                 mac->ops.flap_tx_laser = NULL;
1815                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1816                 mac->ops.set_rate_select_speed =
1817                                         ixgbe_set_soft_rate_select_speed;
1818
1819                 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1820                     (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1821                         mac->ops.setup_mac_link =
1822                                                 ixgbe_setup_mac_link_sfp_x550a;
1823                 else
1824                         mac->ops.setup_mac_link =
1825                                                 ixgbe_setup_mac_link_sfp_x550em;
1826                 break;
1827         case ixgbe_media_type_copper:
1828                 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1829                         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
1830                             hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
1831                                 mac->ops.setup_link = ixgbe_setup_sgmii_m88;
1832                         } else {
1833                                 mac->ops.setup_link =
1834                                                   ixgbe_setup_mac_link_t_X550em;
1835                         }
1836                 } else {
1837                         mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1838                         mac->ops.check_link = ixgbe_check_link_t_X550em;
1839                 }
1840                 break;
1841         case ixgbe_media_type_backplane:
1842                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1843                     hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1844                         mac->ops.setup_link = ixgbe_setup_sgmii;
1845                 break;
1846         default:
1847                 break;
1848         }
1849 }
1850
1851 /**
1852  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1853  *  @hw: pointer to hardware structure
1854  *  @speed: pointer to link speed
1855  *  @autoneg: true when autoneg or autotry is enabled
1856  */
1857 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1858                                        ixgbe_link_speed *speed,
1859                                        bool *autoneg)
1860 {
1861         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1862
1863
1864         /* SFP */
1865         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1866
1867                 /* CS4227 SFP must not enable auto-negotiation */
1868                 *autoneg = false;
1869
1870                 /* Check if 1G SFP module. */
1871                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1872                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1873                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1874                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1875                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1876                         return IXGBE_SUCCESS;
1877                 }
1878
1879                 /* Link capabilities are based on SFP */
1880                 if (hw->phy.multispeed_fiber)
1881                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1882                                  IXGBE_LINK_SPEED_1GB_FULL;
1883                 else
1884                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1885         } else {
1886                 switch (hw->phy.type) {
1887                 case ixgbe_phy_m88:
1888                         *speed = IXGBE_LINK_SPEED_1GB_FULL |
1889                                  IXGBE_LINK_SPEED_100_FULL |
1890                                  IXGBE_LINK_SPEED_10_FULL;
1891                         break;
1892                 case ixgbe_phy_sgmii:
1893                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1894                         break;
1895                 case ixgbe_phy_x550em_kr:
1896                         if (hw->mac.type == ixgbe_mac_X550EM_a) {
1897                                 /* check different backplane modes */
1898                                 if (hw->phy.nw_mng_if_sel &
1899                                            IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
1900                                         *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
1901                                         break;
1902                                 } else if (hw->device_id ==
1903                                                    IXGBE_DEV_ID_X550EM_A_KR_L) {
1904                                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1905                                         break;
1906                                 }
1907                         }
1908                         /* fall through */
1909                 default:
1910                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1911                                  IXGBE_LINK_SPEED_1GB_FULL;
1912                         break;
1913                 }
1914                 *autoneg = true;
1915         }
1916
1917         return IXGBE_SUCCESS;
1918 }
1919
1920 /**
1921  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1922  * @hw: pointer to hardware structure
1923  * @lsc: pointer to boolean flag which indicates whether external Base T
1924  *       PHY interrupt is lsc
1925  *
1926  * Determime if external Base T PHY interrupt cause is high temperature
1927  * failure alarm or link status change.
1928  *
1929  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1930  * failure alarm, else return PHY access status.
1931  */
1932 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1933 {
1934         u32 status;
1935         u16 reg;
1936
1937         *lsc = false;
1938
1939         /* Vendor alarm triggered */
1940         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1941                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1942                                       &reg);
1943
1944         if (status != IXGBE_SUCCESS ||
1945             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1946                 return status;
1947
1948         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1949         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1950                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1951                                       &reg);
1952
1953         if (status != IXGBE_SUCCESS ||
1954             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1955             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1956                 return status;
1957
1958         /* Global alarm triggered */
1959         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1960                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1961                                       &reg);
1962
1963         if (status != IXGBE_SUCCESS)
1964                 return status;
1965
1966         /* If high temperature failure, then return over temp error and exit */
1967         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1968                 /* power down the PHY in case the PHY FW didn't already */
1969                 ixgbe_set_copper_phy_power(hw, false);
1970                 return IXGBE_ERR_OVERTEMP;
1971         } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1972                 /*  device fault alarm triggered */
1973                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1974                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1975                                           &reg);
1976
1977                 if (status != IXGBE_SUCCESS)
1978                         return status;
1979
1980                 /* if device fault was due to high temp alarm handle and exit */
1981                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1982                         /* power down the PHY in case the PHY FW didn't */
1983                         ixgbe_set_copper_phy_power(hw, false);
1984                         return IXGBE_ERR_OVERTEMP;
1985                 }
1986         }
1987
1988         /* Vendor alarm 2 triggered */
1989         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1990                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1991
1992         if (status != IXGBE_SUCCESS ||
1993             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1994                 return status;
1995
1996         /* link connect/disconnect event occurred */
1997         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1998                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1999
2000         if (status != IXGBE_SUCCESS)
2001                 return status;
2002
2003         /* Indicate LSC */
2004         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2005                 *lsc = true;
2006
2007         return IXGBE_SUCCESS;
2008 }
2009
2010 /**
2011  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2012  * @hw: pointer to hardware structure
2013  *
2014  * Enable link status change and temperature failure alarm for the external
2015  * Base T PHY
2016  *
2017  * Returns PHY access status
2018  */
2019 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2020 {
2021         u32 status;
2022         u16 reg;
2023         bool lsc;
2024
2025         /* Clear interrupt flags */
2026         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2027
2028         /* Enable link status change alarm */
2029
2030         /* Enable the LASI interrupts on X552 devices to receive notifications
2031          * of the link configurations of the external PHY and correspondingly
2032          * support the configuration of the internal iXFI link, since iXFI does
2033          * not support auto-negotiation. This is not required for X553 devices
2034          * having KR support, which performs auto-negotiations and which is used
2035          * as the internal link to the external PHY. Hence adding a check here
2036          * to avoid enabling LASI interrupts for X553 devices.
2037          */
2038         if (hw->mac.type != ixgbe_mac_X550EM_a) {
2039                 status = hw->phy.ops.read_reg(hw,
2040                                         IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2041                                         IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2042
2043                 if (status != IXGBE_SUCCESS)
2044                         return status;
2045
2046                 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2047
2048                 status = hw->phy.ops.write_reg(hw,
2049                                         IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2050                                         IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
2051
2052                 if (status != IXGBE_SUCCESS)
2053                         return status;
2054         }
2055
2056         /* Enable high temperature failure and global fault alarms */
2057         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2058                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2059                                       &reg);
2060
2061         if (status != IXGBE_SUCCESS)
2062                 return status;
2063
2064         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2065                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2066
2067         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2068                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2069                                        reg);
2070
2071         if (status != IXGBE_SUCCESS)
2072                 return status;
2073
2074         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2075         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2076                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2077                                       &reg);
2078
2079         if (status != IXGBE_SUCCESS)
2080                 return status;
2081
2082         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2083                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2084
2085         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2086                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2087                                        reg);
2088
2089         if (status != IXGBE_SUCCESS)
2090                 return status;
2091
2092         /* Enable chip-wide vendor alarm */
2093         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2094                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2095                                       &reg);
2096
2097         if (status != IXGBE_SUCCESS)
2098                 return status;
2099
2100         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2101
2102         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2103                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2104                                        reg);
2105
2106         return status;
2107 }
2108
2109 /**
2110  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2111  *  @hw: pointer to hardware structure
2112  *  @speed: link speed
2113  *
2114  *  Configures the integrated KR PHY.
2115  **/
2116 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2117                                        ixgbe_link_speed speed)
2118 {
2119         s32 status;
2120         u32 reg_val;
2121
2122         status = hw->mac.ops.read_iosf_sb_reg(hw,
2123                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2124                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2125         if (status)
2126                 return status;
2127
2128         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2129         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2130                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2131
2132         /* Advertise 10G support. */
2133         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2134                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2135
2136         /* Advertise 1G support. */
2137         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2138                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2139
2140         status = hw->mac.ops.write_iosf_sb_reg(hw,
2141                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2142                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2143
2144         if (hw->mac.type == ixgbe_mac_X550EM_a) {
2145                 /* Set lane mode  to KR auto negotiation */
2146                 status = hw->mac.ops.read_iosf_sb_reg(hw,
2147                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2148                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2149
2150                 if (status)
2151                         return status;
2152
2153                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2154                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2155                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2156                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2157                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2158
2159                 status = hw->mac.ops.write_iosf_sb_reg(hw,
2160                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2161                                     IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2162         }
2163
2164         return ixgbe_restart_an_internal_phy_x550em(hw);
2165 }
2166
2167 /**
2168  * ixgbe_setup_m88 - setup m88 PHY
2169  * @hw: pointer to hardware structure
2170  */
2171 STATIC s32 ixgbe_setup_m88(struct ixgbe_hw *hw)
2172 {
2173         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2174         u16 reg;
2175         s32 rc;
2176
2177         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2178                 return IXGBE_SUCCESS;
2179
2180         rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2181         if (rc)
2182                 return rc;
2183
2184         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2185         if (rc)
2186                 goto out;
2187         if (reg & IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN) {
2188                 reg &= ~IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN;
2189                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2190                                           reg);
2191         }
2192
2193         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, &reg);
2194         if (rc)
2195                 goto out;
2196         if (reg & IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN) {
2197                 reg &= ~IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN;
2198                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0,
2199                                           reg);
2200         }
2201
2202         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 2);
2203         if (rc)
2204                 goto out;
2205
2206         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2207                                       &reg);
2208         if (rc)
2209                 goto out;
2210         if (reg & IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN) {
2211                 reg &= ~IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN;
2212                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2213                                           reg);
2214                 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2215                                                0);
2216                 if (rc)
2217                         goto out;
2218                 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2219                                               &reg);
2220                 if (rc)
2221                         goto out;
2222                 reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2223                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2224                                           reg);
2225                 usec_delay(50);
2226         } else {
2227                 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2228                                                0);
2229                 if (rc)
2230                         goto out;
2231         }
2232
2233         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2234         if (rc)
2235                 goto out;
2236
2237         if (!(reg & IXGBE_M88E1500_COPPER_CTRL_AN_EN)) {
2238                 reg |= IXGBE_M88E1500_COPPER_CTRL_AN_EN;
2239                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2240                                           reg);
2241         }
2242
2243         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, &reg);
2244         if (rc)
2245                 goto out;
2246         reg &= ~IXGBE_M88E1500_1000T_CTRL_HALF_DUPLEX;
2247         reg &= ~IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2248         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
2249                 reg |= IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2250         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, reg);
2251
2252         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, &reg);
2253         if (rc)
2254                 goto out;
2255         reg &= ~IXGBE_M88E1500_COPPER_AN_T4;
2256         reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_FD;
2257         reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_HD;
2258         reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_FD;
2259         reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_HD;
2260
2261         /* Flow control auto negotiation configuration was moved from here to
2262          * the function ixgbe_setup_fc_sgmii_x550em_a()
2263          */
2264
2265         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
2266                 reg |= IXGBE_M88E1500_COPPER_AN_100TX_FD;
2267         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL)
2268                 reg |= IXGBE_M88E1500_COPPER_AN_10TX_FD;
2269         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, reg);
2270
2271         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2272         if (rc)
2273                 goto out;
2274         reg |= IXGBE_M88E1500_COPPER_CTRL_RESTART_AN;
2275         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2276
2277
2278         hw->mac.ops.release_swfw_sync(hw, mask);
2279         return rc;
2280
2281 out:
2282         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2283         hw->mac.ops.release_swfw_sync(hw, mask);
2284         return rc;
2285 }
2286
2287 /**
2288  * ixgbe_reset_phy_m88e1500 - Reset m88e1500 PHY
2289  * @hw: pointer to hardware structure
2290  *
2291  * The PHY token must be held when calling this function.
2292  */
2293 static s32 ixgbe_reset_phy_m88e1500(struct ixgbe_hw *hw)
2294 {
2295         u16 reg;
2296         s32 rc;
2297
2298         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2299         if (rc)
2300                 return rc;
2301
2302         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2303         if (rc)
2304                 return rc;
2305
2306         reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2307         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2308
2309         usec_delay(10);
2310
2311         return rc;
2312 }
2313
2314 /**
2315  * ixgbe_reset_phy_m88e1543 - Reset m88e1543 PHY
2316  * @hw: pointer to hardware structure
2317  *
2318  * The PHY token must be held when calling this function.
2319  */
2320 static s32 ixgbe_reset_phy_m88e1543(struct ixgbe_hw *hw)
2321 {
2322         return hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2323 }
2324
2325 /**
2326  * ixgbe_reset_phy_m88 - Reset m88 PHY
2327  * @hw: pointer to hardware structure
2328  */
2329 STATIC s32 ixgbe_reset_phy_m88(struct ixgbe_hw *hw)
2330 {
2331         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2332         u16 reg;
2333         s32 rc;
2334
2335         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2336                 return IXGBE_SUCCESS;
2337
2338         rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2339         if (rc)
2340                 return rc;
2341
2342         switch (hw->phy.id) {
2343         case IXGBE_M88E1500_E_PHY_ID:
2344                 rc = ixgbe_reset_phy_m88e1500(hw);
2345                 break;
2346         case IXGBE_M88E1543_E_PHY_ID:
2347                 rc = ixgbe_reset_phy_m88e1543(hw);
2348                 break;
2349         default:
2350                 rc = IXGBE_ERR_PHY;
2351                 break;
2352         }
2353
2354         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2355         if (rc)
2356                 goto out;
2357
2358         reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2359               IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2360               IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2361         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2362         if (rc)
2363                 goto out;
2364
2365         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 18);
2366         if (rc)
2367                 goto out;
2368
2369         reg = IXGBE_M88E1500_GEN_CTRL_RESET |
2370               IXGBE_M88E1500_GEN_CTRL_MODE_SGMII_COPPER;
2371         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_GEN_CTRL, 0, reg);
2372         if (rc)
2373                 goto out;
2374
2375         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2376         if (rc)
2377                 goto out;
2378
2379         reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2380               IXGBE_M88E1500_FIBER_CTRL_AN_EN |
2381               IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2382               IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2383         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2384         if (rc)
2385                 goto out;
2386
2387         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2388         if (rc)
2389                 goto out;
2390
2391         reg = (IXGBE_M88E1500_MAC_CTRL_1_DWN_4X <<
2392                IXGBE_M88E1500_MAC_CTRL_1_DWN_SHIFT) |
2393               (IXGBE_M88E1500_MAC_CTRL_1_ED_TM <<
2394                IXGBE_M88E1500_MAC_CTRL_1_ED_SHIFT) |
2395               (IXGBE_M88E1500_MAC_CTRL_1_MDIX_AUTO <<
2396                IXGBE_M88E1500_MAC_CTRL_1_MDIX_SHIFT);
2397         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, reg);
2398         if (rc)
2399                 goto out;
2400
2401         reg = IXGBE_M88E1500_COPPER_CTRL_RESET |
2402               IXGBE_M88E1500_COPPER_CTRL_AN_EN |
2403               IXGBE_M88E1500_COPPER_CTRL_RESTART_AN |
2404               IXGBE_M88E1500_COPPER_CTRL_FULL_DUPLEX |
2405               IXGBE_M88E1500_COPPER_CTRL_SPEED_MSB;
2406         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2407         if (rc)
2408                 goto out;
2409
2410         hw->mac.ops.release_swfw_sync(hw, mask);
2411
2412         /* In case of first reset set advertised speeds to default value */
2413         if (!hw->phy.autoneg_advertised)
2414                 hw->phy.autoneg_advertised = IXGBE_LINK_SPEED_1GB_FULL |
2415                                              IXGBE_LINK_SPEED_100_FULL |
2416                                              IXGBE_LINK_SPEED_10_FULL;
2417
2418         return ixgbe_setup_m88(hw);
2419
2420 out:
2421         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2422         hw->mac.ops.release_swfw_sync(hw, mask);
2423         return rc;
2424 }
2425
2426 /**
2427  *  ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2428  *  @hw: pointer to hardware structure
2429  *
2430  *  Read NW_MNG_IF_SEL register and save field values, and check for valid field
2431  *  values.
2432  **/
2433 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2434 {
2435         /* Save NW management interface connected on board. This is used
2436          * to determine internal PHY mode.
2437          */
2438         hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2439
2440         /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2441          * PHY address. This register field was has only been used for X552.
2442          */
2443         if (hw->mac.type == ixgbe_mac_X550EM_a &&
2444             hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2445                 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2446                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2447                                IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2448         }
2449
2450         return IXGBE_SUCCESS;
2451 }
2452
2453 /**
2454  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2455  *  @hw: pointer to hardware structure
2456  *
2457  *  Initialize any function pointers that were not able to be
2458  *  set during init_shared_code because the PHY/SFP type was
2459  *  not known.  Perform the SFP init if necessary.
2460  */
2461 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2462 {
2463         struct ixgbe_phy_info *phy = &hw->phy;
2464         s32 ret_val;
2465
2466         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2467
2468         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2469                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2470                 ixgbe_setup_mux_ctl(hw);
2471                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2472         }
2473
2474         switch (hw->device_id) {
2475         case IXGBE_DEV_ID_X550EM_A_1G_T:
2476         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2477                 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2478                 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2479                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2480                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2481                 if (hw->bus.lan_id)
2482                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2483                 else
2484                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2485
2486                 break;
2487         case IXGBE_DEV_ID_X550EM_A_10G_T:
2488         case IXGBE_DEV_ID_X550EM_A_SFP:
2489                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2490                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2491                 if (hw->bus.lan_id)
2492                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2493                 else
2494                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2495                 break;
2496         case IXGBE_DEV_ID_X550EM_X_SFP:
2497                 /* set up for CS4227 usage */
2498                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2499                 break;
2500         default:
2501                 break;
2502         }
2503
2504         /* Identify the PHY or SFP module */
2505         ret_val = phy->ops.identify(hw);
2506         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
2507                 return ret_val;
2508
2509         /* Setup function pointers based on detected hardware */
2510         ixgbe_init_mac_link_ops_X550em(hw);
2511         if (phy->sfp_type != ixgbe_sfp_type_unknown)
2512                 phy->ops.reset = NULL;
2513
2514         /* Set functions pointers based on phy type */
2515         switch (hw->phy.type) {
2516         case ixgbe_phy_x550em_kx4:
2517                 phy->ops.setup_link = NULL;
2518                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2519                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2520                 break;
2521         case ixgbe_phy_x550em_kr:
2522                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2523                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2524                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2525                 break;
2526         case ixgbe_phy_x550em_ext_t:
2527                 /* If internal link mode is XFI, then setup iXFI internal link,
2528                  * else setup KR now.
2529                  */
2530                 phy->ops.setup_internal_link =
2531                                               ixgbe_setup_internal_phy_t_x550em;
2532
2533                 /* setup SW LPLU only for first revision of X550EM_x */
2534                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2535                     !(IXGBE_FUSES0_REV_MASK &
2536                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2537                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2538
2539                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2540                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2541                 break;
2542         case ixgbe_phy_sgmii:
2543                 phy->ops.setup_link = NULL;
2544                 break;
2545         case ixgbe_phy_m88:
2546                 phy->ops.setup_link = ixgbe_setup_m88;
2547                 phy->ops.reset = ixgbe_reset_phy_m88;
2548                 break;
2549         default:
2550                 break;
2551         }
2552         return ret_val;
2553 }
2554
2555 /**
2556  * ixgbe_set_mdio_speed - Set MDIO clock speed
2557  *  @hw: pointer to hardware structure
2558  */
2559 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2560 {
2561         u32 hlreg0;
2562
2563         switch (hw->device_id) {
2564         case IXGBE_DEV_ID_X550EM_X_10G_T:
2565         case IXGBE_DEV_ID_X550EM_A_SGMII:
2566         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2567         case IXGBE_DEV_ID_X550EM_A_10G_T:
2568         case IXGBE_DEV_ID_X550EM_A_SFP:
2569         case IXGBE_DEV_ID_X550EM_A_QSFP:
2570                 /* Config MDIO clock speed before the first MDIO PHY access */
2571                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2572                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2573                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2574                 break;
2575         case IXGBE_DEV_ID_X550EM_A_1G_T:
2576         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2577                 /* Select fast MDIO clock speed for these devices */
2578                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2579                 hlreg0 |= IXGBE_HLREG0_MDCSPD;
2580                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2581                 break;
2582         default:
2583                 break;
2584         }
2585 }
2586
2587 /**
2588  *  ixgbe_reset_hw_X550em - Perform hardware reset
2589  *  @hw: pointer to hardware structure
2590  *
2591  *  Resets the hardware by resetting the transmit and receive units, masks
2592  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2593  *  reset.
2594  */
2595 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2596 {
2597         ixgbe_link_speed link_speed;
2598         s32 status;
2599         u32 ctrl = 0;
2600         u32 i;
2601         bool link_up = false;
2602
2603         DEBUGFUNC("ixgbe_reset_hw_X550em");
2604
2605         /* Call adapter stop to disable Tx/Rx and clear interrupts */
2606         status = hw->mac.ops.stop_adapter(hw);
2607         if (status != IXGBE_SUCCESS)
2608                 return status;
2609
2610         /* flush pending Tx transactions */
2611         ixgbe_clear_tx_pending(hw);
2612
2613         ixgbe_set_mdio_speed(hw);
2614
2615         /* PHY ops must be identified and initialized prior to reset */
2616         status = hw->phy.ops.init(hw);
2617
2618         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2619                 return status;
2620
2621         /* start the external PHY */
2622         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2623                 status = ixgbe_init_ext_t_x550em(hw);
2624                 if (status)
2625                         return status;
2626         }
2627
2628         /* Setup SFP module if there is one present. */
2629         if (hw->phy.sfp_setup_needed) {
2630                 status = hw->mac.ops.setup_sfp(hw);
2631                 hw->phy.sfp_setup_needed = false;
2632         }
2633
2634         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2635                 return status;
2636
2637         /* Reset PHY */
2638         if (!hw->phy.reset_disable && hw->phy.ops.reset)
2639                 hw->phy.ops.reset(hw);
2640
2641 mac_reset_top:
2642         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2643          * If link reset is used when link is up, it might reset the PHY when
2644          * mng is using it.  If link is down or the flag to force full link
2645          * reset is set, then perform link reset.
2646          */
2647         ctrl = IXGBE_CTRL_LNK_RST;
2648         if (!hw->force_full_reset) {
2649                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2650                 if (link_up)
2651                         ctrl = IXGBE_CTRL_RST;
2652         }
2653
2654         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2655         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2656         IXGBE_WRITE_FLUSH(hw);
2657
2658         /* Poll for reset bit to self-clear meaning reset is complete */
2659         for (i = 0; i < 10; i++) {
2660                 usec_delay(1);
2661                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2662                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2663                         break;
2664         }
2665
2666         if (ctrl & IXGBE_CTRL_RST_MASK) {
2667                 status = IXGBE_ERR_RESET_FAILED;
2668                 DEBUGOUT("Reset polling failed to complete.\n");
2669         }
2670
2671         msec_delay(50);
2672
2673         /* Double resets are required for recovery from certain error
2674          * conditions.  Between resets, it is necessary to stall to
2675          * allow time for any pending HW events to complete.
2676          */
2677         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2678                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2679                 goto mac_reset_top;
2680         }
2681
2682         /* Store the permanent mac address */
2683         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2684
2685         /* Store MAC address from RAR0, clear receive address registers, and
2686          * clear the multicast table.  Also reset num_rar_entries to 128,
2687          * since we modify this value when programming the SAN MAC address.
2688          */
2689         hw->mac.num_rar_entries = 128;
2690         hw->mac.ops.init_rx_addrs(hw);
2691
2692         ixgbe_set_mdio_speed(hw);
2693
2694         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2695                 ixgbe_setup_mux_ctl(hw);
2696
2697         return status;
2698 }
2699
2700 /**
2701  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2702  * @hw: pointer to hardware structure
2703  */
2704 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2705 {
2706         u32 status;
2707         u16 reg;
2708
2709         status = hw->phy.ops.read_reg(hw,
2710                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2711                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2712                                       &reg);
2713
2714         if (status != IXGBE_SUCCESS)
2715                 return status;
2716
2717         /* If PHY FW reset completed bit is set then this is the first
2718          * SW instance after a power on so the PHY FW must be un-stalled.
2719          */
2720         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2721                 status = hw->phy.ops.read_reg(hw,
2722                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2723                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2724                                         &reg);
2725
2726                 if (status != IXGBE_SUCCESS)
2727                         return status;
2728
2729                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2730
2731                 status = hw->phy.ops.write_reg(hw,
2732                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2733                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2734                                         reg);
2735
2736                 if (status != IXGBE_SUCCESS)
2737                         return status;
2738         }
2739
2740         return status;
2741 }
2742
2743 /**
2744  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
2745  *  @hw: pointer to hardware structure
2746  *
2747  *  Configures the integrated KR PHY for X550EM_x.
2748  **/
2749 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2750 {
2751         if (hw->mac.type != ixgbe_mac_X550EM_x)
2752                 return IXGBE_SUCCESS;
2753
2754         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2755 }
2756
2757 /**
2758  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2759  *  @hw: pointer to hardware structure
2760  *
2761  *  Configure the external PHY and the integrated KR PHY for SFP support.
2762  **/
2763 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2764                                     ixgbe_link_speed speed,
2765                                     bool autoneg_wait_to_complete)
2766 {
2767         s32 ret_val;
2768         u16 reg_slice, reg_val;
2769         bool setup_linear = false;
2770         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2771
2772         /* Check if SFP module is supported and linear */
2773         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2774
2775         /* If no SFP module present, then return success. Return success since
2776          * there is no reason to configure CS4227 and SFP not present error is
2777          * not excepted in the setup MAC link flow.
2778          */
2779         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2780                 return IXGBE_SUCCESS;
2781
2782         if (ret_val != IXGBE_SUCCESS)
2783                 return ret_val;
2784
2785         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2786                 /* Configure CS4227 LINE side to 10G SR. */
2787                 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
2788                             (hw->bus.lan_id << 12);
2789                 reg_val = IXGBE_CS4227_SPEED_10G;
2790                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2791                                                   reg_val);
2792
2793                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2794                             (hw->bus.lan_id << 12);
2795                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2796                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2797                                                   reg_val);
2798
2799                 /* Configure CS4227 for HOST connection rate then type. */
2800                 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
2801                             (hw->bus.lan_id << 12);
2802                 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
2803                 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
2804                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2805                                                   reg_val);
2806
2807                 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
2808                             (hw->bus.lan_id << 12);
2809                 if (setup_linear)
2810                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2811                 else
2812                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2813                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2814                                                   reg_val);
2815
2816                 /* Setup XFI internal link. */
2817                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2818         } else {
2819                 /* Configure internal PHY for KR/KX. */
2820                 ixgbe_setup_kr_speed_x550em(hw, speed);
2821
2822                 /* Configure CS4227 LINE side to proper mode. */
2823                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2824                             (hw->bus.lan_id << 12);
2825                 if (setup_linear)
2826                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2827                 else
2828                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2829                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2830                                                   reg_val);
2831         }
2832         return ret_val;
2833 }
2834
2835 /**
2836  *  ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
2837  *  @hw: pointer to hardware structure
2838  *  @speed: the link speed to force
2839  *
2840  *  Configures the integrated PHY for native SFI mode. Used to connect the
2841  *  internal PHY directly to an SFP cage, without autonegotiation.
2842  **/
2843 STATIC s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2844 {
2845         struct ixgbe_mac_info *mac = &hw->mac;
2846         s32 status;
2847         u32 reg_val;
2848
2849         /* Disable all AN and force speed to 10G Serial. */
2850         status = mac->ops.read_iosf_sb_reg(hw,
2851                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2852                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2853         if (status != IXGBE_SUCCESS)
2854                 return status;
2855
2856         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2857         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2858         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2859         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2860
2861         /* Select forced link speed for internal PHY. */
2862         switch (*speed) {
2863         case IXGBE_LINK_SPEED_10GB_FULL:
2864                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
2865                 break;
2866         case IXGBE_LINK_SPEED_1GB_FULL:
2867                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2868                 break;
2869         default:
2870                 /* Other link speeds are not supported by internal PHY. */
2871                 return IXGBE_ERR_LINK_SETUP;
2872         }
2873
2874         status = mac->ops.write_iosf_sb_reg(hw,
2875                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2876                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2877
2878         /* Toggle port SW reset by AN reset. */
2879         status = ixgbe_restart_an_internal_phy_x550em(hw);
2880
2881         return status;
2882 }
2883
2884 /**
2885  *  ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2886  *  @hw: pointer to hardware structure
2887  *
2888  *  Configure the the integrated PHY for SFP support.
2889  **/
2890 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2891                                     ixgbe_link_speed speed,
2892                                     bool autoneg_wait_to_complete)
2893 {
2894         s32 ret_val;
2895         u16 reg_phy_ext;
2896         bool setup_linear = false;
2897         u32 reg_slice, reg_phy_int, slice_offset;
2898
2899         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2900
2901         /* Check if SFP module is supported and linear */
2902         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2903
2904         /* If no SFP module present, then return success. Return success since
2905          * SFP not present error is not excepted in the setup MAC link flow.
2906          */
2907         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2908                 return IXGBE_SUCCESS;
2909
2910         if (ret_val != IXGBE_SUCCESS)
2911                 return ret_val;
2912
2913         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2914                 /* Configure internal PHY for native SFI based on module type */
2915                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2916                                    IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2917                                    IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_phy_int);
2918
2919                 if (ret_val != IXGBE_SUCCESS)
2920                         return ret_val;
2921
2922                 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
2923                 if (!setup_linear)
2924                         reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
2925
2926                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2927                                    IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2928                                    IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2929
2930                 if (ret_val != IXGBE_SUCCESS)
2931                         return ret_val;
2932
2933                 /* Setup SFI internal link. */
2934                 ret_val = ixgbe_setup_sfi_x550a(hw, &speed);
2935         } else {
2936                 /* Configure internal PHY for KR/KX. */
2937                 ixgbe_setup_kr_speed_x550em(hw, speed);
2938
2939                 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2940                         /* Find Address */
2941                         DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2942                         return IXGBE_ERR_PHY_ADDR_INVALID;
2943                 }
2944
2945                 /* Get external PHY SKU id */
2946                 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,
2947                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2948
2949                 if (ret_val != IXGBE_SUCCESS)
2950                         return ret_val;
2951
2952                 /* When configuring quad port CS4223, the MAC instance is part
2953                  * of the slice offset.
2954                  */
2955                 if (reg_phy_ext == IXGBE_CS4223_SKU_ID)
2956                         slice_offset = (hw->bus.lan_id +
2957                                         (hw->bus.instance_id << 1)) << 12;
2958                 else
2959                         slice_offset = hw->bus.lan_id << 12;
2960
2961                 /* Configure CS4227/CS4223 LINE side to proper mode. */
2962                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2963                 if (setup_linear)
2964                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2965                 else
2966                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2967                 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2968                                          IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2969         }
2970         return ret_val;
2971 }
2972
2973 /**
2974  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2975  *  @hw: pointer to hardware structure
2976  *
2977  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2978  **/
2979 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2980 {
2981         struct ixgbe_mac_info *mac = &hw->mac;
2982         s32 status;
2983         u32 reg_val;
2984
2985         /* Disable training protocol FSM. */
2986         status = mac->ops.read_iosf_sb_reg(hw,
2987                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2988                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2989         if (status != IXGBE_SUCCESS)
2990                 return status;
2991         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2992         status = mac->ops.write_iosf_sb_reg(hw,
2993                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2994                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2995         if (status != IXGBE_SUCCESS)
2996                 return status;
2997
2998         /* Disable Flex from training TXFFE. */
2999         status = mac->ops.read_iosf_sb_reg(hw,
3000                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
3001                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3002         if (status != IXGBE_SUCCESS)
3003                 return status;
3004         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
3005         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
3006         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
3007         status = mac->ops.write_iosf_sb_reg(hw,
3008                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
3009                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3010         if (status != IXGBE_SUCCESS)
3011                 return status;
3012         status = mac->ops.read_iosf_sb_reg(hw,
3013                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
3014                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3015         if (status != IXGBE_SUCCESS)
3016                 return status;
3017         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
3018         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
3019         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
3020         status = mac->ops.write_iosf_sb_reg(hw,
3021                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
3022                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3023         if (status != IXGBE_SUCCESS)
3024                 return status;
3025
3026         /* Enable override for coefficients. */
3027         status = mac->ops.read_iosf_sb_reg(hw,
3028                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
3029                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3030         if (status != IXGBE_SUCCESS)
3031                 return status;
3032         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
3033         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
3034         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
3035         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
3036         status = mac->ops.write_iosf_sb_reg(hw,
3037                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
3038                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3039         return status;
3040 }
3041
3042 /**
3043  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
3044  *  @hw: pointer to hardware structure
3045  *  @speed: the link speed to force
3046  *
3047  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
3048  *  internal and external PHY at a specific speed, without autonegotiation.
3049  **/
3050 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
3051 {
3052         struct ixgbe_mac_info *mac = &hw->mac;
3053         s32 status;
3054         u32 reg_val;
3055
3056         /* iXFI is only supported with X552 */
3057         if (mac->type != ixgbe_mac_X550EM_x)
3058                 return IXGBE_ERR_LINK_SETUP;
3059
3060         /* Disable AN and force speed to 10G Serial. */
3061         status = mac->ops.read_iosf_sb_reg(hw,
3062                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3063                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3064         if (status != IXGBE_SUCCESS)
3065                 return status;
3066
3067         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3068         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3069
3070         /* Select forced link speed for internal PHY. */
3071         switch (*speed) {
3072         case IXGBE_LINK_SPEED_10GB_FULL:
3073                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3074                 break;
3075         case IXGBE_LINK_SPEED_1GB_FULL:
3076                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
3077                 break;
3078         default:
3079                 /* Other link speeds are not supported by internal KR PHY. */
3080                 return IXGBE_ERR_LINK_SETUP;
3081         }
3082
3083         status = mac->ops.write_iosf_sb_reg(hw,
3084                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3085                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3086         if (status != IXGBE_SUCCESS)
3087                 return status;
3088
3089         /* Additional configuration needed for x550em_x */
3090         if (hw->mac.type == ixgbe_mac_X550EM_x) {
3091                 status = ixgbe_setup_ixfi_x550em_x(hw);
3092                 if (status != IXGBE_SUCCESS)
3093                         return status;
3094         }
3095
3096         /* Toggle port SW reset by AN reset. */
3097         status = ixgbe_restart_an_internal_phy_x550em(hw);
3098
3099         return status;
3100 }
3101
3102 /**
3103  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
3104  * @hw: address of hardware structure
3105  * @link_up: address of boolean to indicate link status
3106  *
3107  * Returns error code if unable to get link status.
3108  */
3109 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
3110 {
3111         u32 ret;
3112         u16 autoneg_status;
3113
3114         *link_up = false;
3115
3116         /* read this twice back to back to indicate current status */
3117         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3118                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3119                                    &autoneg_status);
3120         if (ret != IXGBE_SUCCESS)
3121                 return ret;
3122
3123         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3124                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3125                                    &autoneg_status);
3126         if (ret != IXGBE_SUCCESS)
3127                 return ret;
3128
3129         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
3130
3131         return IXGBE_SUCCESS;
3132 }
3133
3134 /**
3135  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
3136  * @hw: point to hardware structure
3137  *
3138  * Configures the link between the integrated KR PHY and the external X557 PHY
3139  * The driver will call this function when it gets a link status change
3140  * interrupt from the X557 PHY. This function configures the link speed
3141  * between the PHYs to match the link speed of the BASE-T link.
3142  *
3143  * A return of a non-zero value indicates an error, and the base driver should
3144  * not report link up.
3145  */
3146 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
3147 {
3148         ixgbe_link_speed force_speed;
3149         bool link_up;
3150         u32 status;
3151         u16 speed;
3152
3153         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3154                 return IXGBE_ERR_CONFIG;
3155
3156         if (hw->mac.type == ixgbe_mac_X550EM_x &&
3157             !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3158                 /* If link is down, there is no setup necessary so return  */
3159                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3160                 if (status != IXGBE_SUCCESS)
3161                         return status;
3162
3163                 if (!link_up)
3164                         return IXGBE_SUCCESS;
3165
3166                 status = hw->phy.ops.read_reg(hw,
3167                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3168                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3169                                               &speed);
3170                 if (status != IXGBE_SUCCESS)
3171                         return status;
3172
3173                 /* If link is still down - no setup is required so return */
3174                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3175                 if (status != IXGBE_SUCCESS)
3176                         return status;
3177                 if (!link_up)
3178                         return IXGBE_SUCCESS;
3179
3180                 /* clear everything but the speed and duplex bits */
3181                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
3182
3183                 switch (speed) {
3184                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
3185                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3186                         break;
3187                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
3188                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3189                         break;
3190                 default:
3191                         /* Internal PHY does not support anything else */
3192                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
3193                 }
3194
3195                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
3196         } else {
3197                 speed = IXGBE_LINK_SPEED_10GB_FULL |
3198                         IXGBE_LINK_SPEED_1GB_FULL;
3199                 return ixgbe_setup_kr_speed_x550em(hw, speed);
3200         }
3201 }
3202
3203 /**
3204  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
3205  *  @hw: pointer to hardware structure
3206  *
3207  *  Configures the integrated KR PHY to use internal loopback mode.
3208  **/
3209 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
3210 {
3211         s32 status;
3212         u32 reg_val;
3213
3214         /* Disable AN and force speed to 10G Serial. */
3215         status = hw->mac.ops.read_iosf_sb_reg(hw,
3216                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3217                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3218         if (status != IXGBE_SUCCESS)
3219                 return status;
3220         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3221         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3222         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3223         status = hw->mac.ops.write_iosf_sb_reg(hw,
3224                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3225                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3226         if (status != IXGBE_SUCCESS)
3227                 return status;
3228
3229         /* Set near-end loopback clocks. */
3230         status = hw->mac.ops.read_iosf_sb_reg(hw,
3231                                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3232                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3233         if (status != IXGBE_SUCCESS)
3234                 return status;
3235         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3236         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3237         status = hw->mac.ops.write_iosf_sb_reg(hw,
3238                                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3239                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3240         if (status != IXGBE_SUCCESS)
3241                 return status;
3242
3243         /* Set loopback enable. */
3244         status = hw->mac.ops.read_iosf_sb_reg(hw,
3245                                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3246                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3247         if (status != IXGBE_SUCCESS)
3248                 return status;
3249         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3250         status = hw->mac.ops.write_iosf_sb_reg(hw,
3251                                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3252                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3253         if (status != IXGBE_SUCCESS)
3254                 return status;
3255
3256         /* Training bypass. */
3257         status = hw->mac.ops.read_iosf_sb_reg(hw,
3258                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3259                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3260         if (status != IXGBE_SUCCESS)
3261                 return status;
3262         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3263         status = hw->mac.ops.write_iosf_sb_reg(hw,
3264                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3265                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3266
3267         return status;
3268 }
3269
3270 /**
3271  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3272  *  assuming that the semaphore is already obtained.
3273  *  @hw: pointer to hardware structure
3274  *  @offset: offset of  word in the EEPROM to read
3275  *  @data: word read from the EEPROM
3276  *
3277  *  Reads a 16 bit word from the EEPROM using the hostif.
3278  **/
3279 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
3280 {
3281         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3282         struct ixgbe_hic_read_shadow_ram buffer;
3283         s32 status;
3284
3285         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3286         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3287         buffer.hdr.req.buf_lenh = 0;
3288         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3289         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3290
3291         /* convert offset from words to bytes */
3292         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3293         /* one word */
3294         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3295
3296         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3297         if (status)
3298                 return status;
3299
3300         status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3301                                     IXGBE_HI_COMMAND_TIMEOUT);
3302         if (!status) {
3303                 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3304                                                   FW_NVM_DATA_OFFSET);
3305         }
3306
3307         hw->mac.ops.release_swfw_sync(hw, mask);
3308         return status;
3309 }
3310
3311 /**
3312  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3313  *  @hw: pointer to hardware structure
3314  *  @offset: offset of  word in the EEPROM to read
3315  *  @words: number of words
3316  *  @data: word(s) read from the EEPROM
3317  *
3318  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
3319  **/
3320 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3321                                      u16 offset, u16 words, u16 *data)
3322 {
3323         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3324         struct ixgbe_hic_read_shadow_ram buffer;
3325         u32 current_word = 0;
3326         u16 words_to_read;
3327         s32 status;
3328         u32 i;
3329
3330         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3331
3332         /* Take semaphore for the entire operation. */
3333         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3334         if (status) {
3335                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3336                 return status;
3337         }
3338
3339         while (words) {
3340                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3341                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3342                 else
3343                         words_to_read = words;
3344
3345                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3346                 buffer.hdr.req.buf_lenh = 0;
3347                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3348                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3349
3350                 /* convert offset from words to bytes */
3351                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3352                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3353
3354                 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3355                                             IXGBE_HI_COMMAND_TIMEOUT);
3356
3357                 if (status) {
3358                         DEBUGOUT("Host interface command failed\n");
3359                         goto out;
3360                 }
3361
3362                 for (i = 0; i < words_to_read; i++) {
3363                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3364                                   2 * i;
3365                         u32 value = IXGBE_READ_REG(hw, reg);
3366
3367                         data[current_word] = (u16)(value & 0xffff);
3368                         current_word++;
3369                         i++;
3370                         if (i < words_to_read) {
3371                                 value >>= 16;
3372                                 data[current_word] = (u16)(value & 0xffff);
3373                                 current_word++;
3374                         }
3375                 }
3376                 words -= words_to_read;
3377         }
3378
3379 out:
3380         hw->mac.ops.release_swfw_sync(hw, mask);
3381         return status;
3382 }
3383
3384 /**
3385  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3386  *  @hw: pointer to hardware structure
3387  *  @offset: offset of  word in the EEPROM to write
3388  *  @data: word write to the EEPROM
3389  *
3390  *  Write a 16 bit word to the EEPROM using the hostif.
3391  **/
3392 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3393                                     u16 data)
3394 {
3395         s32 status;
3396         struct ixgbe_hic_write_shadow_ram buffer;
3397
3398         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3399
3400         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3401         buffer.hdr.req.buf_lenh = 0;
3402         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3403         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3404
3405          /* one word */
3406         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3407         buffer.data = data;
3408         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3409
3410         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3411                                               sizeof(buffer),
3412                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3413
3414         return status;
3415 }
3416
3417 /**
3418  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3419  *  @hw: pointer to hardware structure
3420  *  @offset: offset of  word in the EEPROM to write
3421  *  @data: word write to the EEPROM
3422  *
3423  *  Write a 16 bit word to the EEPROM using the hostif.
3424  **/
3425 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3426                                u16 data)
3427 {
3428         s32 status = IXGBE_SUCCESS;
3429
3430         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3431
3432         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3433             IXGBE_SUCCESS) {
3434                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3435                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3436         } else {
3437                 DEBUGOUT("write ee hostif failed to get semaphore");
3438                 status = IXGBE_ERR_SWFW_SYNC;
3439         }
3440
3441         return status;
3442 }
3443
3444 /**
3445  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3446  *  @hw: pointer to hardware structure
3447  *  @offset: offset of  word in the EEPROM to write
3448  *  @words: number of words
3449  *  @data: word(s) write to the EEPROM
3450  *
3451  *  Write a 16 bit word(s) to the EEPROM using the hostif.
3452  **/
3453 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3454                                       u16 offset, u16 words, u16 *data)
3455 {
3456         s32 status = IXGBE_SUCCESS;
3457         u32 i = 0;
3458
3459         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3460
3461         /* Take semaphore for the entire operation. */
3462         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3463         if (status != IXGBE_SUCCESS) {
3464                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3465                 goto out;
3466         }
3467
3468         for (i = 0; i < words; i++) {
3469                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3470                                                          data[i]);
3471
3472                 if (status != IXGBE_SUCCESS) {
3473                         DEBUGOUT("Eeprom buffered write failed\n");
3474                         break;
3475                 }
3476         }
3477
3478         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3479 out:
3480
3481         return status;
3482 }
3483
3484 /**
3485  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3486  * @hw: pointer to hardware structure
3487  * @ptr: pointer offset in eeprom
3488  * @size: size of section pointed by ptr, if 0 first word will be used as size
3489  * @csum: address of checksum to update
3490  *
3491  * Returns error status for any failure
3492  */
3493 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3494                                    u16 size, u16 *csum, u16 *buffer,
3495                                    u32 buffer_size)
3496 {
3497         u16 buf[256];
3498         s32 status;
3499         u16 length, bufsz, i, start;
3500         u16 *local_buffer;
3501
3502         bufsz = sizeof(buf) / sizeof(buf[0]);
3503
3504         /* Read a chunk at the pointer location */
3505         if (!buffer) {
3506                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3507                 if (status) {
3508                         DEBUGOUT("Failed to read EEPROM image\n");
3509                         return status;
3510                 }
3511                 local_buffer = buf;
3512         } else {
3513                 if (buffer_size < ptr)
3514                         return  IXGBE_ERR_PARAM;
3515                 local_buffer = &buffer[ptr];
3516         }
3517
3518         if (size) {
3519                 start = 0;
3520                 length = size;
3521         } else {
3522                 start = 1;
3523                 length = local_buffer[0];
3524
3525                 /* Skip pointer section if length is invalid. */
3526                 if (length == 0xFFFF || length == 0 ||
3527                     (ptr + length) >= hw->eeprom.word_size)
3528                         return IXGBE_SUCCESS;
3529         }
3530
3531         if (buffer && ((u32)start + (u32)length > buffer_size))
3532                 return IXGBE_ERR_PARAM;
3533
3534         for (i = start; length; i++, length--) {
3535                 if (i == bufsz && !buffer) {
3536                         ptr += bufsz;
3537                         i = 0;
3538                         if (length < bufsz)
3539                                 bufsz = length;
3540
3541                         /* Read a chunk at the pointer location */
3542                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3543                                                                   bufsz, buf);
3544                         if (status) {
3545                                 DEBUGOUT("Failed to read EEPROM image\n");
3546                                 return status;
3547                         }
3548                 }
3549                 *csum += local_buffer[i];
3550         }
3551         return IXGBE_SUCCESS;
3552 }
3553
3554 /**
3555  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3556  *  @hw: pointer to hardware structure
3557  *  @buffer: pointer to buffer containing calculated checksum
3558  *  @buffer_size: size of buffer
3559  *
3560  *  Returns a negative error code on error, or the 16-bit checksum
3561  **/
3562 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3563 {
3564         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3565         u16 *local_buffer;
3566         s32 status;
3567         u16 checksum = 0;
3568         u16 pointer, i, size;
3569
3570         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3571
3572         hw->eeprom.ops.init_params(hw);
3573
3574         if (!buffer) {
3575                 /* Read pointer area */
3576                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3577                                                      IXGBE_EEPROM_LAST_WORD + 1,
3578                                                      eeprom_ptrs);
3579                 if (status) {
3580                         DEBUGOUT("Failed to read EEPROM image\n");
3581                         return status;
3582                 }
3583                 local_buffer = eeprom_ptrs;
3584         } else {
3585                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3586                         return IXGBE_ERR_PARAM;
3587                 local_buffer = buffer;
3588         }
3589
3590         /*
3591          * For X550 hardware include 0x0-0x41 in the checksum, skip the
3592          * checksum word itself
3593          */
3594         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3595                 if (i != IXGBE_EEPROM_CHECKSUM)
3596                         checksum += local_buffer[i];
3597
3598         /*
3599          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
3600          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3601          */
3602         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3603                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3604                         continue;
3605
3606                 pointer = local_buffer[i];
3607
3608                 /* Skip pointer section if the pointer is invalid. */
3609                 if (pointer == 0xFFFF || pointer == 0 ||
3610                     pointer >= hw->eeprom.word_size)
3611                         continue;
3612
3613                 switch (i) {
3614                 case IXGBE_PCIE_GENERAL_PTR:
3615                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3616                         break;
3617                 case IXGBE_PCIE_CONFIG0_PTR:
3618                 case IXGBE_PCIE_CONFIG1_PTR:
3619                         size = IXGBE_PCIE_CONFIG_SIZE;
3620                         break;
3621                 default:
3622                         size = 0;
3623                         break;
3624                 }
3625
3626                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3627                                                 buffer, buffer_size);
3628                 if (status)
3629                         return status;
3630         }
3631
3632         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3633
3634         return (s32)checksum;
3635 }
3636
3637 /**
3638  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3639  *  @hw: pointer to hardware structure
3640  *
3641  *  Returns a negative error code on error, or the 16-bit checksum
3642  **/
3643 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3644 {
3645         return ixgbe_calc_checksum_X550(hw, NULL, 0);
3646 }
3647
3648 /**
3649  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3650  *  @hw: pointer to hardware structure
3651  *  @checksum_val: calculated checksum
3652  *
3653  *  Performs checksum calculation and validates the EEPROM checksum.  If the
3654  *  caller does not need checksum_val, the value can be NULL.
3655  **/
3656 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3657 {
3658         s32 status;
3659         u16 checksum;
3660         u16 read_checksum = 0;
3661
3662         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3663
3664         /* Read the first word from the EEPROM. If this times out or fails, do
3665          * not continue or we could be in for a very long wait while every
3666          * EEPROM read fails
3667          */
3668         status = hw->eeprom.ops.read(hw, 0, &checksum);
3669         if (status) {
3670                 DEBUGOUT("EEPROM read failed\n");
3671                 return status;
3672         }
3673
3674         status = hw->eeprom.ops.calc_checksum(hw);
3675         if (status < 0)
3676                 return status;
3677
3678         checksum = (u16)(status & 0xffff);
3679
3680         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3681                                            &read_checksum);
3682         if (status)
3683                 return status;
3684
3685         /* Verify read checksum from EEPROM is the same as
3686          * calculated checksum
3687          */
3688         if (read_checksum != checksum) {
3689                 status = IXGBE_ERR_EEPROM_CHECKSUM;
3690                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3691                              "Invalid EEPROM checksum");
3692         }
3693
3694         /* If the user cares, return the calculated checksum */
3695         if (checksum_val)
3696                 *checksum_val = checksum;
3697
3698         return status;
3699 }
3700
3701 /**
3702  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3703  * @hw: pointer to hardware structure
3704  *
3705  * After writing EEPROM to shadow RAM using EEWR register, software calculates
3706  * checksum and updates the EEPROM and instructs the hardware to update
3707  * the flash.
3708  **/
3709 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3710 {
3711         s32 status;
3712         u16 checksum = 0;
3713
3714         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3715
3716         /* Read the first word from the EEPROM. If this times out or fails, do
3717          * not continue or we could be in for a very long wait while every
3718          * EEPROM read fails
3719          */
3720         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3721         if (status) {
3722                 DEBUGOUT("EEPROM read failed\n");
3723                 return status;
3724         }
3725
3726         status = ixgbe_calc_eeprom_checksum_X550(hw);
3727         if (status < 0)
3728                 return status;
3729
3730         checksum = (u16)(status & 0xffff);
3731
3732         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3733                                             checksum);
3734         if (status)
3735                 return status;
3736
3737         status = ixgbe_update_flash_X550(hw);
3738
3739         return status;
3740 }
3741
3742 /**
3743  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3744  *  @hw: pointer to hardware structure
3745  *
3746  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3747  **/
3748 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3749 {
3750         s32 status = IXGBE_SUCCESS;
3751         union ixgbe_hic_hdr2 buffer;
3752
3753         DEBUGFUNC("ixgbe_update_flash_X550");
3754
3755         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3756         buffer.req.buf_lenh = 0;
3757         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3758         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3759
3760         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3761                                               sizeof(buffer),
3762                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3763
3764         return status;
3765 }
3766
3767 /**
3768  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3769  *  @hw: pointer to hardware structure
3770  *
3771  *  Determines physical layer capabilities of the current configuration.
3772  **/
3773 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3774 {
3775         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3776         u16 ext_ability = 0;
3777
3778         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3779
3780         hw->phy.ops.identify(hw);
3781
3782         switch (hw->phy.type) {
3783         case ixgbe_phy_x550em_kr:
3784                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3785                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3786                 break;
3787         case ixgbe_phy_x550em_kx4:
3788                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3789                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3790                 break;
3791         case ixgbe_phy_x550em_ext_t:
3792                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3793                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3794                                      &ext_ability);
3795                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3796                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3797                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3798                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3799                 break;
3800         case ixgbe_phy_m88:
3801                 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
3802         default:
3803                 break;
3804         }
3805
3806         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3807                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3808
3809         return physical_layer;
3810 }
3811
3812 /**
3813  * ixgbe_get_bus_info_x550em - Set PCI bus info
3814  * @hw: pointer to hardware structure
3815  *
3816  * Sets bus link width and speed to unknown because X550em is
3817  * not a PCI device.
3818  **/
3819 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3820 {
3821
3822         DEBUGFUNC("ixgbe_get_bus_info_x550em");
3823
3824         hw->bus.width = ixgbe_bus_width_unknown;
3825         hw->bus.speed = ixgbe_bus_speed_unknown;
3826
3827         hw->mac.ops.set_lan_id(hw);
3828
3829         return IXGBE_SUCCESS;
3830 }
3831
3832 /**
3833  * ixgbe_disable_rx_x550 - Disable RX unit
3834  *
3835  * Enables the Rx DMA unit for x550
3836  **/
3837 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3838 {
3839         u32 rxctrl, pfdtxgswc;
3840         s32 status;
3841         struct ixgbe_hic_disable_rxen fw_cmd;
3842
3843         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3844
3845         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3846         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3847                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3848                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3849                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3850                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3851                         hw->mac.set_lben = true;
3852                 } else {
3853                         hw->mac.set_lben = false;
3854                 }
3855
3856                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3857                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3858                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3859                 fw_cmd.port_number = (u8)hw->bus.lan_id;
3860
3861                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3862                                         sizeof(struct ixgbe_hic_disable_rxen),
3863                                         IXGBE_HI_COMMAND_TIMEOUT, true);
3864
3865                 /* If we fail - disable RX using register write */
3866                 if (status) {
3867                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3868                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3869                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3870                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3871                         }
3872                 }
3873         }
3874 }
3875
3876 /**
3877  * ixgbe_enter_lplu_x550em - Transition to low power states
3878  *  @hw: pointer to hardware structure
3879  *
3880  * Configures Low Power Link Up on transition to low power states
3881  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3882  * X557 PHY immediately prior to entering LPLU.
3883  **/
3884 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3885 {
3886         u16 an_10g_cntl_reg, autoneg_reg, speed;
3887         s32 status;
3888         ixgbe_link_speed lcd_speed;
3889         u32 save_autoneg;
3890         bool link_up;
3891
3892         /* SW LPLU not required on later HW revisions. */
3893         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3894             (IXGBE_FUSES0_REV_MASK &
3895              IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3896                 return IXGBE_SUCCESS;
3897
3898         /* If blocked by MNG FW, then don't restart AN */
3899         if (ixgbe_check_reset_blocked(hw))
3900                 return IXGBE_SUCCESS;
3901
3902         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3903         if (status != IXGBE_SUCCESS)
3904                 return status;
3905
3906         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3907
3908         if (status != IXGBE_SUCCESS)
3909                 return status;
3910
3911         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3912          * disabled, then force link down by entering low power mode.
3913          */
3914         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3915             !(hw->wol_enabled || ixgbe_mng_present(hw)))
3916                 return ixgbe_set_copper_phy_power(hw, FALSE);
3917
3918         /* Determine LCD */
3919         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3920
3921         if (status != IXGBE_SUCCESS)
3922                 return status;
3923
3924         /* If no valid LCD link speed, then force link down and exit. */
3925         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3926                 return ixgbe_set_copper_phy_power(hw, FALSE);
3927
3928         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3929                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3930                                       &speed);
3931
3932         if (status != IXGBE_SUCCESS)
3933                 return status;
3934
3935         /* If no link now, speed is invalid so take link down */
3936         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3937         if (status != IXGBE_SUCCESS)
3938                 return ixgbe_set_copper_phy_power(hw, false);
3939
3940         /* clear everything but the speed bits */
3941         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3942
3943         /* If current speed is already LCD, then exit. */
3944         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3945              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3946             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3947              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3948                 return status;
3949
3950         /* Clear AN completed indication */
3951         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3952                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3953                                       &autoneg_reg);
3954
3955         if (status != IXGBE_SUCCESS)
3956                 return status;
3957
3958         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3959                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3960                              &an_10g_cntl_reg);
3961
3962         if (status != IXGBE_SUCCESS)
3963                 return status;
3964
3965         status = hw->phy.ops.read_reg(hw,
3966                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3967                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3968                              &autoneg_reg);
3969
3970         if (status != IXGBE_SUCCESS)
3971                 return status;
3972
3973         save_autoneg = hw->phy.autoneg_advertised;
3974
3975         /* Setup link at least common link speed */
3976         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3977
3978         /* restore autoneg from before setting lplu speed */
3979         hw->phy.autoneg_advertised = save_autoneg;
3980
3981         return status;
3982 }
3983
3984 /**
3985  * ixgbe_get_lcd_x550em - Determine lowest common denominator
3986  *  @hw: pointer to hardware structure
3987  *  @lcd_speed: pointer to lowest common link speed
3988  *
3989  * Determine lowest common link speed with link partner.
3990  **/
3991 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3992 {
3993         u16 an_lp_status;
3994         s32 status;
3995         u16 word = hw->eeprom.ctrl_word_3;
3996
3997         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3998
3999         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
4000                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4001                                       &an_lp_status);
4002
4003         if (status != IXGBE_SUCCESS)
4004                 return status;
4005
4006         /* If link partner advertised 1G, return 1G */
4007         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
4008                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
4009                 return status;
4010         }
4011
4012         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
4013         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
4014             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
4015                 return status;
4016
4017         /* Link partner not capable of lower speeds, return 10G */
4018         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
4019         return status;
4020 }
4021
4022 /**
4023  *  ixgbe_setup_fc_X550em - Set up flow control
4024  *  @hw: pointer to hardware structure
4025  *
4026  *  Called at init time to set up flow control.
4027  **/
4028 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
4029 {
4030         s32 ret_val = IXGBE_SUCCESS;
4031         u32 pause, asm_dir, reg_val;
4032
4033         DEBUGFUNC("ixgbe_setup_fc_X550em");
4034
4035         /* Validate the requested mode */
4036         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4037                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4038                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4039                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4040                 goto out;
4041         }
4042
4043         /* 10gig parts do not have a word in the EEPROM to determine the
4044          * default flow control setting, so we explicitly set it to full.
4045          */
4046         if (hw->fc.requested_mode == ixgbe_fc_default)
4047                 hw->fc.requested_mode = ixgbe_fc_full;
4048
4049         /* Determine PAUSE and ASM_DIR bits. */
4050         switch (hw->fc.requested_mode) {
4051         case ixgbe_fc_none:
4052                 pause = 0;
4053                 asm_dir = 0;
4054                 break;
4055         case ixgbe_fc_tx_pause:
4056                 pause = 0;
4057                 asm_dir = 1;
4058                 break;
4059         case ixgbe_fc_rx_pause:
4060                 /* Rx Flow control is enabled and Tx Flow control is
4061                  * disabled by software override. Since there really
4062                  * isn't a way to advertise that we are capable of RX
4063                  * Pause ONLY, we will advertise that we support both
4064                  * symmetric and asymmetric Rx PAUSE, as such we fall
4065                  * through to the fc_full statement.  Later, we will
4066                  * disable the adapter's ability to send PAUSE frames.
4067                  */
4068         case ixgbe_fc_full:
4069                 pause = 1;
4070                 asm_dir = 1;
4071                 break;
4072         default:
4073                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4074                         "Flow control param set incorrectly\n");
4075                 ret_val = IXGBE_ERR_CONFIG;
4076                 goto out;
4077         }
4078
4079         switch (hw->device_id) {
4080         case IXGBE_DEV_ID_X550EM_X_KR:
4081         case IXGBE_DEV_ID_X550EM_A_KR:
4082         case IXGBE_DEV_ID_X550EM_A_KR_L:
4083                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
4084                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4085                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
4086                 if (ret_val != IXGBE_SUCCESS)
4087                         goto out;
4088                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4089                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4090                 if (pause)
4091                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4092                 if (asm_dir)
4093                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4094                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
4095                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4096                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
4097
4098                 /* This device does not fully support AN. */
4099                 hw->fc.disable_fc_autoneg = true;
4100                 break;
4101         default:
4102                 break;
4103         }
4104
4105 out:
4106         return ret_val;
4107 }
4108
4109 /**
4110  *  ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
4111  *  @hw: pointer to hardware structure
4112  *
4113  *  Enable flow control according to IEEE clause 37.
4114  **/
4115 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
4116 {
4117         u32 link_s1, lp_an_page_low, an_cntl_1;
4118         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4119         ixgbe_link_speed speed;
4120         bool link_up;
4121
4122         /* AN should have completed when the cable was plugged in.
4123          * Look for reasons to bail out.  Bail out if:
4124          * - FC autoneg is disabled, or if
4125          * - link is not up.
4126          */
4127         if (hw->fc.disable_fc_autoneg) {
4128                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4129                              "Flow control autoneg is disabled");
4130                 goto out;
4131         }
4132
4133         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4134         if (!link_up) {
4135                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4136                 goto out;
4137         }
4138
4139         /* Check at auto-negotiation has completed */
4140         status = hw->mac.ops.read_iosf_sb_reg(hw,
4141                                         IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4142                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4143
4144         if (status != IXGBE_SUCCESS ||
4145             (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4146                 DEBUGOUT("Auto-Negotiation did not complete\n");
4147                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4148                 goto out;
4149         }
4150
4151         /* Read the 10g AN autoc and LP ability registers and resolve
4152          * local flow control settings accordingly
4153          */
4154         status = hw->mac.ops.read_iosf_sb_reg(hw,
4155                                 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4156                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
4157
4158         if (status != IXGBE_SUCCESS) {
4159                 DEBUGOUT("Auto-Negotiation did not complete\n");
4160                 goto out;
4161         }
4162
4163         status = hw->mac.ops.read_iosf_sb_reg(hw,
4164                                 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
4165                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
4166
4167         if (status != IXGBE_SUCCESS) {
4168                 DEBUGOUT("Auto-Negotiation did not complete\n");
4169                 goto out;
4170         }
4171
4172         status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
4173                                     IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
4174                                     IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
4175                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
4176                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
4177
4178 out:
4179         if (status == IXGBE_SUCCESS) {
4180                 hw->fc.fc_was_autonegged = true;
4181         } else {
4182                 hw->fc.fc_was_autonegged = false;
4183                 hw->fc.current_mode = hw->fc.requested_mode;
4184         }
4185 }
4186
4187 /**
4188  *  ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
4189  *  @hw: pointer to hardware structure
4190  *
4191  **/
4192 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
4193 {
4194         hw->fc.fc_was_autonegged = false;
4195         hw->fc.current_mode = hw->fc.requested_mode;
4196 }
4197
4198 /**
4199  *  ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
4200  *  @hw: pointer to hardware structure
4201  *
4202  *  Enable flow control according to IEEE clause 37.
4203  **/
4204 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
4205 {
4206         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4207         u16 reg, pcs_an_lp, pcs_an;
4208         ixgbe_link_speed speed;
4209         bool link_up;
4210
4211         /* AN should have completed when the cable was plugged in.
4212          * Look for reasons to bail out.  Bail out if:
4213          * - FC autoneg is disabled, or if
4214          * - link is not up.
4215          */
4216         if (hw->fc.disable_fc_autoneg) {
4217                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4218                              "Flow control autoneg is disabled");
4219                 goto out;
4220         }
4221
4222         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4223         if (!link_up) {
4224                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4225                 goto out;
4226         }
4227
4228         /* Check if auto-negotiation has completed */
4229         status = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_STATUS,
4230                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg);
4231         if (status != IXGBE_SUCCESS ||
4232             (reg & IXGBE_M88E1500_COPPER_STATUS_AN_DONE) == 0) {
4233                 DEBUGOUT("Auto-Negotiation did not complete\n");
4234                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4235                 goto out;
4236         }
4237
4238         /* Get the advertized flow control */
4239         status = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_AN,
4240                                         IXGBE_MDIO_ZERO_DEV_TYPE, &pcs_an);
4241         if (status != IXGBE_SUCCESS)
4242                 goto out;
4243
4244         /* Get link partner's flow control */
4245         status = hw->phy.ops.read_reg(hw,
4246                         IXGBE_M88E1500_COPPER_AN_LP_ABILITY,
4247                                         IXGBE_MDIO_ZERO_DEV_TYPE, &pcs_an_lp);
4248         if (status != IXGBE_SUCCESS)
4249                 goto out;
4250
4251         /* Negotiate the flow control */
4252         status = ixgbe_negotiate_fc(hw, (u32)pcs_an, (u32)pcs_an_lp,
4253                                     IXGBE_M88E1500_COPPER_AN_PAUSE,
4254                                     IXGBE_M88E1500_COPPER_AN_AS_PAUSE,
4255                                     IXGBE_M88E1500_COPPER_AN_LP_PAUSE,
4256                                     IXGBE_M88E1500_COPPER_AN_LP_AS_PAUSE);
4257
4258 out:
4259         if (status == IXGBE_SUCCESS) {
4260                 hw->fc.fc_was_autonegged = true;
4261         } else {
4262                 hw->fc.fc_was_autonegged = false;
4263                 hw->fc.current_mode = hw->fc.requested_mode;
4264         }
4265 }
4266
4267 /**
4268  *  ixgbe_setup_fc_sgmii_x550em_a - Set up flow control
4269  *  @hw: pointer to hardware structure
4270  *
4271  *  Called at init time to set up flow control.
4272  **/
4273 s32 ixgbe_setup_fc_sgmii_x550em_a(struct ixgbe_hw *hw)
4274 {
4275         u16 reg;
4276         s32 rc;
4277
4278         /* Validate the requested mode */
4279         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4280                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4281                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4282                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4283         }
4284
4285         if (hw->fc.requested_mode == ixgbe_fc_default)
4286                 hw->fc.requested_mode = ixgbe_fc_full;
4287
4288         /* Read contents of the Auto-Negotiation register, page 0 reg 4 */
4289         rc = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_AN,
4290                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg);
4291         if (rc)
4292                 goto out;
4293
4294         /* Disable all the settings related to Flow control Auto-negotiation */
4295         reg &= ~IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4296         reg &= ~IXGBE_M88E1500_COPPER_AN_PAUSE;
4297
4298         /* Configure the Asymmetric and symmetric pause according to the user
4299          * requested mode.
4300          */
4301         switch (hw->fc.requested_mode) {
4302         case ixgbe_fc_full:
4303                 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
4304                 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4305                 break;
4306         case ixgbe_fc_rx_pause:
4307                 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
4308                 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4309                 break;
4310         case ixgbe_fc_tx_pause:
4311                 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4312                 break;
4313         default:
4314                 break;
4315         }
4316
4317         /* Write back to the Auto-Negotiation register with newly configured
4318          * fields
4319          */
4320         hw->phy.ops.write_reg(hw, IXGBE_M88E1500_COPPER_AN,
4321                                         IXGBE_MDIO_ZERO_DEV_TYPE, reg);
4322
4323         /* In this section of the code we restart Auto-negotiation */
4324
4325         /* Read the CONTROL register, Page 0 reg 0 */
4326         rc = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_CTRL,
4327                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg);
4328         if (rc)
4329                 goto out;
4330
4331         /* Set the bit to restart Auto-Neg. The bit to enable Auto-neg is ON
4332          * by default
4333          */
4334         reg |= IXGBE_M88E1500_COPPER_CTRL_RESTART_AN;
4335
4336         /* write the new values to the register to restart Auto-Negotiation */
4337         hw->phy.ops.write_reg(hw, IXGBE_M88E1500_COPPER_CTRL,
4338                                         IXGBE_MDIO_ZERO_DEV_TYPE, reg);
4339
4340 out:
4341         return rc;
4342 }
4343
4344 /**
4345  *  ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4346  *  @hw: pointer to hardware structure
4347  *
4348  *  Called at init time to set up flow control.
4349  **/
4350 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4351 {
4352         s32 status = IXGBE_SUCCESS;
4353         u32 an_cntl = 0;
4354
4355         DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4356
4357         /* Validate the requested mode */
4358         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4359                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4360                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4361                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4362         }
4363
4364         if (hw->fc.requested_mode == ixgbe_fc_default)
4365                 hw->fc.requested_mode = ixgbe_fc_full;
4366
4367         /* Set up the 1G and 10G flow control advertisement registers so the
4368          * HW will be able to do FC autoneg once the cable is plugged in.  If
4369          * we link at 10G, the 1G advertisement is harmless and vice versa.
4370          */
4371         status = hw->mac.ops.read_iosf_sb_reg(hw,
4372                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4373                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4374
4375         if (status != IXGBE_SUCCESS) {
4376                 DEBUGOUT("Auto-Negotiation did not complete\n");
4377                 return status;
4378         }
4379
4380         /* The possible values of fc.requested_mode are:
4381          * 0: Flow control is completely disabled
4382          * 1: Rx flow control is enabled (we can receive pause frames,
4383          *    but not send pause frames).
4384          * 2: Tx flow control is enabled (we can send pause frames but
4385          *    we do not support receiving pause frames).
4386          * 3: Both Rx and Tx flow control (symmetric) are enabled.
4387          * other: Invalid.
4388          */
4389         switch (hw->fc.requested_mode) {
4390         case ixgbe_fc_none:
4391                 /* Flow control completely disabled by software override. */
4392                 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4393                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4394                 break;
4395         case ixgbe_fc_tx_pause:
4396                 /* Tx Flow control is enabled, and Rx Flow control is
4397                  * disabled by software override.
4398                  */
4399                 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4400                 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4401                 break;
4402         case ixgbe_fc_rx_pause:
4403                 /* Rx Flow control is enabled and Tx Flow control is
4404                  * disabled by software override. Since there really
4405                  * isn't a way to advertise that we are capable of RX
4406                  * Pause ONLY, we will advertise that we support both
4407                  * symmetric and asymmetric Rx PAUSE, as such we fall
4408                  * through to the fc_full statement.  Later, we will
4409                  * disable the adapter's ability to send PAUSE frames.
4410                  */
4411         case ixgbe_fc_full:
4412                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4413                 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4414                            IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4415                 break;
4416         default:
4417                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4418                               "Flow control param set incorrectly\n");
4419                 return IXGBE_ERR_CONFIG;
4420         }
4421
4422         status = hw->mac.ops.write_iosf_sb_reg(hw,
4423                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4424                                         IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4425
4426         /* Restart auto-negotiation. */
4427         status = ixgbe_restart_an_internal_phy_x550em(hw);
4428
4429         return status;
4430 }
4431
4432 /**
4433  * ixgbe_set_mux - Set mux for port 1 access with CS4227
4434  * @hw: pointer to hardware structure
4435  * @state: set mux if 1, clear if 0
4436  */
4437 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4438 {
4439         u32 esdp;
4440
4441         if (!hw->bus.lan_id)
4442                 return;
4443         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4444         if (state)
4445                 esdp |= IXGBE_ESDP_SDP1;
4446         else
4447                 esdp &= ~IXGBE_ESDP_SDP1;
4448         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4449         IXGBE_WRITE_FLUSH(hw);
4450 }
4451
4452 /**
4453  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4454  *  @hw: pointer to hardware structure
4455  *  @mask: Mask to specify which semaphore to acquire
4456  *
4457  *  Acquires the SWFW semaphore and sets the I2C MUX
4458  **/
4459 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4460 {
4461         s32 status;
4462
4463         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4464
4465         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4466         if (status)
4467                 return status;
4468
4469         if (mask & IXGBE_GSSR_I2C_MASK)
4470                 ixgbe_set_mux(hw, 1);
4471
4472         return IXGBE_SUCCESS;
4473 }
4474
4475 /**
4476  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4477  *  @hw: pointer to hardware structure
4478  *  @mask: Mask to specify which semaphore to release
4479  *
4480  *  Releases the SWFW semaphore and sets the I2C MUX
4481  **/
4482 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4483 {
4484         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4485
4486         if (mask & IXGBE_GSSR_I2C_MASK)
4487                 ixgbe_set_mux(hw, 0);
4488
4489         ixgbe_release_swfw_sync_X540(hw, mask);
4490 }
4491
4492 /**
4493  *  ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4494  *  @hw: pointer to hardware structure
4495  *  @mask: Mask to specify which semaphore to acquire
4496  *
4497  *  Acquires the SWFW semaphore and get the shared phy token as needed
4498  */
4499 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4500 {
4501         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4502         int retries = FW_PHY_TOKEN_RETRIES;
4503         s32 status = IXGBE_SUCCESS;
4504
4505         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4506
4507         while (--retries) {
4508                 status = IXGBE_SUCCESS;
4509                 if (hmask)
4510                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4511                 if (status)
4512                         return status;
4513                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4514                         return IXGBE_SUCCESS;
4515
4516                 status = ixgbe_get_phy_token(hw);
4517                 if (status == IXGBE_SUCCESS)
4518                         return IXGBE_SUCCESS;
4519
4520                 if (hmask)
4521                         ixgbe_release_swfw_sync_X540(hw, hmask);
4522                 if (status != IXGBE_ERR_TOKEN_RETRY)
4523                         return status;
4524         }
4525
4526         return status;
4527 }
4528
4529 /**
4530  *  ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4531  *  @hw: pointer to hardware structure
4532  *  @mask: Mask to specify which semaphore to release
4533  *
4534  *  Releases the SWFW semaphore and puts the shared phy token as needed
4535  */
4536 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4537 {
4538         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4539
4540         DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4541
4542         if (mask & IXGBE_GSSR_TOKEN_SM)
4543                 ixgbe_put_phy_token(hw);
4544
4545         if (hmask)
4546                 ixgbe_release_swfw_sync_X540(hw, hmask);
4547 }
4548
4549 /**
4550  *  ixgbe_read_phy_reg_x550a  - Reads specified PHY register
4551  *  @hw: pointer to hardware structure
4552  *  @reg_addr: 32 bit address of PHY register to read
4553  *  @phy_data: Pointer to read data from PHY register
4554  *
4555  *  Reads a value from a specified PHY register using the SWFW lock and PHY
4556  *  Token. The PHY Token is needed since the MDIO is shared between to MAC
4557  *  instances.
4558  **/
4559 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4560                                u32 device_type, u16 *phy_data)
4561 {
4562         s32 status;
4563         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4564
4565         DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4566
4567         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4568                 return IXGBE_ERR_SWFW_SYNC;
4569
4570         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4571
4572         hw->mac.ops.release_swfw_sync(hw, mask);
4573
4574         return status;
4575 }
4576
4577 /**
4578  *  ixgbe_write_phy_reg_x550a - Writes specified PHY register
4579  *  @hw: pointer to hardware structure
4580  *  @reg_addr: 32 bit PHY register to write
4581  *  @device_type: 5 bit device type
4582  *  @phy_data: Data to write to the PHY register
4583  *
4584  *  Writes a value to specified PHY register using the SWFW lock and PHY Token.
4585  *  The PHY Token is needed since the MDIO is shared between to MAC instances.
4586  **/
4587 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4588                                 u32 device_type, u16 phy_data)
4589 {
4590         s32 status;
4591         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4592
4593         DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4594
4595         if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4596                 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
4597                                                  phy_data);
4598                 hw->mac.ops.release_swfw_sync(hw, mask);
4599         } else {
4600                 status = IXGBE_ERR_SWFW_SYNC;
4601         }
4602
4603         return status;
4604 }
4605
4606 /**
4607  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4608  * @hw: pointer to hardware structure
4609  *
4610  * Handle external Base T PHY interrupt. If high temperature
4611  * failure alarm then return error, else if link status change
4612  * then setup internal/external PHY link
4613  *
4614  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4615  * failure alarm, else return PHY access status.
4616  */
4617 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4618 {
4619         bool lsc;
4620         u32 status;
4621
4622         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4623
4624         if (status != IXGBE_SUCCESS)
4625                 return status;
4626
4627         if (lsc)
4628                 return ixgbe_setup_internal_phy(hw);
4629
4630         return IXGBE_SUCCESS;
4631 }
4632
4633 /**
4634  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4635  * @hw: pointer to hardware structure
4636  * @speed: new link speed
4637  * @autoneg_wait_to_complete: true when waiting for completion is needed
4638  *
4639  * Setup internal/external PHY link speed based on link speed, then set
4640  * external PHY auto advertised link speed.
4641  *
4642  * Returns error status for any failure
4643  **/
4644 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4645                                   ixgbe_link_speed speed,
4646                                   bool autoneg_wait_to_complete)
4647 {
4648         s32 status;
4649         ixgbe_link_speed force_speed;
4650
4651         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4652
4653         /* Setup internal/external PHY link speed to iXFI (10G), unless
4654          * only 1G is auto advertised then setup KX link.
4655          */
4656         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4657                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4658         else
4659                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4660
4661         /* If X552 and internal link mode is XFI, then setup XFI internal link.
4662          */
4663         if (hw->mac.type == ixgbe_mac_X550EM_x &&
4664             !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4665                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4666
4667                 if (status != IXGBE_SUCCESS)
4668                         return status;
4669         }
4670
4671         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4672 }
4673
4674 /**
4675  * ixgbe_check_link_t_X550em - Determine link and speed status
4676  * @hw: pointer to hardware structure
4677  * @speed: pointer to link speed
4678  * @link_up: true when link is up
4679  * @link_up_wait_to_complete: bool used to wait for link up or not
4680  *
4681  * Check that both the MAC and X557 external PHY have link.
4682  **/
4683 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4684                               bool *link_up, bool link_up_wait_to_complete)
4685 {
4686         u32 status;
4687         u16 i, autoneg_status = 0;
4688
4689         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4690                 return IXGBE_ERR_CONFIG;
4691
4692         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4693                                               link_up_wait_to_complete);
4694
4695         /* If check link fails or MAC link is not up, then return */
4696         if (status != IXGBE_SUCCESS || !(*link_up))
4697                 return status;
4698
4699         /* MAC link is up, so check external PHY link.
4700          * X557 PHY. Link status is latching low, and can only be used to detect
4701          * link drop, and not the current status of the link without performing
4702          * back-to-back reads.
4703          */
4704         for (i = 0; i < 2; i++) {
4705                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4706                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4707                                               &autoneg_status);
4708
4709                 if (status != IXGBE_SUCCESS)
4710                         return status;
4711         }
4712
4713         /* If external PHY link is not up, then indicate link not up */
4714         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4715                 *link_up = false;
4716
4717         return IXGBE_SUCCESS;
4718 }
4719
4720 /**
4721  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4722  *  @hw: pointer to hardware structure
4723  **/
4724 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4725 {
4726         s32 status;
4727
4728         status = ixgbe_reset_phy_generic(hw);
4729
4730         if (status != IXGBE_SUCCESS)
4731                 return status;
4732
4733         /* Configure Link Status Alarm and Temperature Threshold interrupts */
4734         return ixgbe_enable_lasi_ext_t_x550em(hw);
4735 }
4736
4737 /**
4738  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4739  *  @hw: pointer to hardware structure
4740  *  @led_idx: led number to turn on
4741  **/
4742 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4743 {
4744         u16 phy_data;
4745
4746         DEBUGFUNC("ixgbe_led_on_t_X550em");
4747
4748         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4749                 return IXGBE_ERR_PARAM;
4750
4751         /* To turn on the LED, set mode to ON. */
4752         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4753                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4754         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4755         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4756                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4757
4758         return IXGBE_SUCCESS;
4759 }
4760
4761 /**
4762  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4763  *  @hw: pointer to hardware structure
4764  *  @led_idx: led number to turn off
4765  **/
4766 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4767 {
4768         u16 phy_data;
4769
4770         DEBUGFUNC("ixgbe_led_off_t_X550em");
4771
4772         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4773                 return IXGBE_ERR_PARAM;
4774
4775         /* To turn on the LED, set mode to ON. */
4776         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4777                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4778         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4779         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4780                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4781
4782         return IXGBE_SUCCESS;
4783 }
4784
4785 /**
4786  *  ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware
4787  *  @hw: pointer to the HW structure
4788  *  @maj: driver version major number
4789  *  @min: driver version minor number
4790  *  @build: driver version build number
4791  *  @sub: driver version sub build number
4792  *  @len: length of driver_ver string
4793  *  @driver_ver: driver string
4794  *
4795  *  Sends driver version number to firmware through the manageability
4796  *  block.  On success return IXGBE_SUCCESS
4797  *  else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4798  *  semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4799  **/
4800 s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,
4801                               u8 build, u8 sub, u16 len, const char *driver_ver)
4802 {
4803         struct ixgbe_hic_drv_info2 fw_cmd;
4804         s32 ret_val = IXGBE_SUCCESS;
4805         int i;
4806
4807         DEBUGFUNC("ixgbe_set_fw_drv_ver_x550");
4808
4809         if ((len == 0) || (driver_ver == NULL) ||
4810            (len > sizeof(fw_cmd.driver_string)))
4811                 return IXGBE_ERR_INVALID_ARGUMENT;
4812
4813         fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4814         fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len;
4815         fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4816         fw_cmd.port_num = (u8)hw->bus.func;
4817         fw_cmd.ver_maj = maj;
4818         fw_cmd.ver_min = min;
4819         fw_cmd.ver_build = build;
4820         fw_cmd.ver_sub = sub;
4821         fw_cmd.hdr.checksum = 0;
4822         memcpy(fw_cmd.driver_string, driver_ver, len);
4823         fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4824                                 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4825
4826         for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4827                 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4828                                                        sizeof(fw_cmd),
4829                                                        IXGBE_HI_COMMAND_TIMEOUT,
4830                                                        true);
4831                 if (ret_val != IXGBE_SUCCESS)
4832                         continue;
4833
4834                 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4835                     FW_CEM_RESP_STATUS_SUCCESS)
4836                         ret_val = IXGBE_SUCCESS;
4837                 else
4838                         ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4839
4840                 break;
4841         }
4842
4843         return ret_val;
4844 }