drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41
  42 /**
  43  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  44  *  @hw: pointer to hardware structure
  45  *
  46  *  Initialize the function pointers and assign the MAC type for X550.
  47  *  Does not touch the hardware.
  48  **/
  49 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  50 {
  51         struct ixgbe_mac_info *mac = &hw->mac;
  52         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  53         s32 ret_val;
  54
  55         DEBUGFUNC("ixgbe_init_ops_X550");
  56
  57         ret_val = ixgbe_init_ops_X540(hw);
  58         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  59         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  60         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  61         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  62         mac->ops.set_source_address_pruning =
  63                         ixgbe_set_source_address_pruning_X550;
  64         mac->ops.set_ethertype_anti_spoofing =
  65                         ixgbe_set_ethertype_anti_spoofing_X550;
  66
  67         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  68         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  69         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  70         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  71         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  72         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  73         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  74         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  75         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  76
  77         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  78         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  79         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  80         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  81         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  82         return ret_val;
  83 }
  84
  85 /**
  86  * ixgbe_read_cs4227 - Read CS4227 register
  87  * @hw: pointer to hardware structure
  88  * @reg: register number to write
  89  * @value: pointer to receive value read
  90  *
  91  * Returns status code
  92  **/
  93 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  94 {
  95         return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
  96 }
  97
  98 /**
  99  * ixgbe_write_cs4227 - Write CS4227 register
 100  * @hw: pointer to hardware structure
 101  * @reg: register number to write
 102  * @value: value to write to register
 103  *
 104  * Returns status code
 105  **/
 106 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 107 {
 108         return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 109 }
 110
 111 /**
 112  * ixgbe_get_cs4227_status - Return CS4227 status
 113  * @hw: pointer to hardware structure
 114  *
 115  * Returns error if CS4227 not successfully initialized
 116  **/
 117 STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
 118 {
 119         s32 status;
 120         u16 value = 0;
 121         u8 retry;
 122
 123         for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) {
 124                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB,
 125                                            &value);
 126                 if (status != IXGBE_SUCCESS)
 127                         return status;
 128                 if (value == IXGBE_CS4227_GLOBAL_ID_VALUE)
 129                         break;
 130                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 131         }
 132         if (value != IXGBE_CS4227_GLOBAL_ID_VALUE)
 133                 return IXGBE_ERR_PHY;
 134
 135         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 136                                     IXGBE_CS4227_SCRATCH_VALUE);
 137         if (status != IXGBE_SUCCESS)
 138                 return status;
 139         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 140         if (status != IXGBE_SUCCESS)
 141                 return status;
 142         if (value != IXGBE_CS4227_SCRATCH_VALUE)
 143                 return IXGBE_ERR_PHY;
 144         return IXGBE_SUCCESS;
 145 }
 146
 147 /**
 148  * ixgbe_read_pe - Read register from port expander
 149  * @hw: pointer to hardware structure
 150  * @reg: register number to read
 151  * @value: pointer to receive read value
 152  *
 153  * Returns status code
 154  **/
 155 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 156 {
 157         s32 status;
 158
 159         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 160         if (status != IXGBE_SUCCESS)
 161                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 162                               "port expander access failed with %d\n", status);
 163         return status;
 164 }
 165
 166 /**
 167  * ixgbe_write_pe - Write register to port expander
 168  * @hw: pointer to hardware structure
 169  * @reg: register number to write
 170  * @value: value to write
 171  *
 172  * Returns status code
 173  **/
 174 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 175 {
 176         s32 status;
 177
 178         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 179         if (status != IXGBE_SUCCESS)
 180                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 181                               "port expander access failed with %d\n", status);
 182         return status;
 183 }
 184
 185 /**
 186  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 187  * @hw: pointer to hardware structure
 188  *
 189  * Returns error code
 190  **/
 191 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 192 {
 193         s32 status;
 194         u8 reg;
 195
 196         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 197         if (status != IXGBE_SUCCESS)
 198                 return status;
 199         reg |= IXGBE_PE_BIT1;
 200         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 201         if (status != IXGBE_SUCCESS)
 202                 return status;
 203
 204         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 205         if (status != IXGBE_SUCCESS)
 206                 return status;
 207         reg &= ~IXGBE_PE_BIT1;
 208         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 209         if (status != IXGBE_SUCCESS)
 210                 return status;
 211
 212         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 213         if (status != IXGBE_SUCCESS)
 214                 return status;
 215         reg &= ~IXGBE_PE_BIT1;
 216         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 217         if (status != IXGBE_SUCCESS)
 218                 return status;
 219
 220         usec_delay(IXGBE_CS4227_RESET_HOLD);
 221
 222         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 223         if (status != IXGBE_SUCCESS)
 224                 return status;
 225         reg |= IXGBE_PE_BIT1;
 226         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 227         if (status != IXGBE_SUCCESS)
 228                 return status;
 229
 230         msec_delay(IXGBE_CS4227_RESET_DELAY);
 231
 232         return IXGBE_SUCCESS;
 233 }
 234
 235 /**
 236  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 237  * @hw: pointer to hardware structure
 238  **/
 239 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 240 {
 241         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 242         s32 status;
 243         u8 retry;
 244
 245         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 246                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 247                 if (status != IXGBE_SUCCESS) {
 248                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 249                                       "semaphore failed with %d\n", status);
 250                         return;
 251                 }
 252                 status = ixgbe_get_cs4227_status(hw);
 253                 if (status == IXGBE_SUCCESS) {
 254                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 255                         msec_delay(hw->eeprom.semaphore_delay);
 256                         return;
 257                 }
 258                 ixgbe_reset_cs4227(hw);
 259                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 260                 msec_delay(hw->eeprom.semaphore_delay);
 261         }
 262         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 263                       "Unable to initialize CS4227, err=%d\n", status);
 264 }
 265
 266 /**
 267  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 268  * @hw: pointer to hardware structure
 269  **/
 270 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 271 {
 272         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 273
 274         if (hw->bus.lan_id) {
 275                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 276                 esdp |= IXGBE_ESDP_SDP1_DIR;
 277         }
 278         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 279         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 280         IXGBE_WRITE_FLUSH(hw);
 281 }
 282
 283 /**
 284  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 285  * @hw: pointer to hardware structure
 286  *
 287  * Returns error code
 288  */
 289 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 290 {
 291         switch (hw->device_id) {
 292         case IXGBE_DEV_ID_X550EM_X_SFP:
 293                 /* set up for CS4227 usage */
 294                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 295                 ixgbe_setup_mux_ctl(hw);
 296                 ixgbe_check_cs4227(hw);
 297
 298                 return ixgbe_identify_module_generic(hw);
 299                 break;
 300         case IXGBE_DEV_ID_X550EM_X_KX4:
 301                 hw->phy.type = ixgbe_phy_x550em_kx4;
 302                 break;
 303         case IXGBE_DEV_ID_X550EM_X_KR:
 304                 hw->phy.type = ixgbe_phy_x550em_kr;
 305                 break;
 306         case IXGBE_DEV_ID_X550EM_X_1G_T:
 307         case IXGBE_DEV_ID_X550EM_X_10G_T:
 308                 return ixgbe_identify_phy_generic(hw);
 309         default:
 310                 break;
 311         }
 312         return IXGBE_SUCCESS;
 313 }
 314
 315 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 316                                      u32 device_type, u16 *phy_data)
 317 {
 318         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 319         return IXGBE_NOT_IMPLEMENTED;
 320 }
 321
 322 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 323                                       u32 device_type, u16 phy_data)
 324 {
 325         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 326         return IXGBE_NOT_IMPLEMENTED;
 327 }
 328
 329 /**
 330 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 331 *  @hw: pointer to hardware structure
 332 *
 333 *  Initialize the function pointers and for MAC type X550EM.
 334 *  Does not touch the hardware.
 335 **/
 336 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 337 {
 338         struct ixgbe_mac_info *mac = &hw->mac;
 339         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 340         struct ixgbe_phy_info *phy = &hw->phy;
 341         s32 ret_val;
 342
 343         DEBUGFUNC("ixgbe_init_ops_X550EM");
 344
 345         /* Similar to X550 so start there. */
 346         ret_val = ixgbe_init_ops_X550(hw);
 347
 348         /* Since this function eventually calls
 349          * ixgbe_init_ops_540 by design, we are setting
 350          * the pointers to NULL explicitly here to overwrite
 351          * the values being set in the x540 function.
 352          */
 353         /* Thermal sensor not supported in x550EM */
 354         mac->ops.get_thermal_sensor_data = NULL;
 355         mac->ops.init_thermal_sensor_thresh = NULL;
 356         mac->thermal_sensor_enabled = false;
 357
 358         /* FCOE not supported in x550EM */
 359         mac->ops.get_san_mac_addr = NULL;
 360         mac->ops.set_san_mac_addr = NULL;
 361         mac->ops.get_wwn_prefix = NULL;
 362         mac->ops.get_fcoe_boot_status = NULL;
 363
 364         /* IPsec not supported in x550EM */
 365         mac->ops.disable_sec_rx_path = NULL;
 366         mac->ops.enable_sec_rx_path = NULL;
 367
 368         /* AUTOC register is not present in x550EM. */
 369         mac->ops.prot_autoc_read = NULL;
 370         mac->ops.prot_autoc_write = NULL;
 371
 372         /* X550EM bus type is internal*/
 373         hw->bus.type = ixgbe_bus_type_internal;
 374         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 375
 376         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 377         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 378         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 379         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 380         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 381         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 382         mac->ops.get_supported_physical_layer =
 383                                     ixgbe_get_supported_physical_layer_X550em;
 384
 385         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 386                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 387         else
 388                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 389
 390         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 391         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 392
 393         if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
 394                 mac->ops.setup_eee = NULL;
 395
 396         /* PHY */
 397         phy->ops.init = ixgbe_init_phy_ops_X550em;
 398         phy->ops.identify = ixgbe_identify_phy_x550em;
 399         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 400                 phy->ops.set_phy_power = NULL;
 401
 402
 403         /* EEPROM */
 404         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 405         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 406         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 407         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 408         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 409         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 410         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 411         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 412
 413         return ret_val;
 414 }
 415
 416 /**
 417  *  ixgbe_dmac_config_X550
 418  *  @hw: pointer to hardware structure
 419  *
 420  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 421  *  When disabling dmac, dmac enable dmac bit is cleared.
 422  **/
 423 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 424 {
 425         u32 reg, high_pri_tc;
 426
 427         DEBUGFUNC("ixgbe_dmac_config_X550");
 428
 429         /* Disable DMA coalescing before configuring */
 430         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 431         reg &= ~IXGBE_DMACR_DMAC_EN;
 432         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 433
 434         /* Disable DMA Coalescing if the watchdog timer is 0 */
 435         if (!hw->mac.dmac_config.watchdog_timer)
 436                 goto out;
 437
 438         ixgbe_dmac_config_tcs_X550(hw);
 439
 440         /* Configure DMA Coalescing Control Register */
 441         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 442
 443         /* Set the watchdog timer in units of 40.96 usec */
 444         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 445         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 446
 447         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 448         /* If fcoe is enabled, set high priority traffic class */
 449         if (hw->mac.dmac_config.fcoe_en) {
 450                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 451                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 452                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 453         }
 454         reg |= IXGBE_DMACR_EN_MNG_IND;
 455
 456         /* Enable DMA coalescing after configuration */
 457         reg |= IXGBE_DMACR_DMAC_EN;
 458         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 459
 460 out:
 461         return IXGBE_SUCCESS;
 462 }
 463
 464 /**
 465  *  ixgbe_dmac_config_tcs_X550
 466  *  @hw: pointer to hardware structure
 467  *
 468  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 469  *  be cleared before configuring.
 470  **/
 471 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 472 {
 473         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 474
 475         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 476
 477         /* Configure DMA coalescing enabled */
 478         switch (hw->mac.dmac_config.link_speed) {
 479         case IXGBE_LINK_SPEED_100_FULL:
 480                 pb_headroom = IXGBE_DMACRXT_100M;
 481                 break;
 482         case IXGBE_LINK_SPEED_1GB_FULL:
 483                 pb_headroom = IXGBE_DMACRXT_1G;
 484                 break;
 485         default:
 486                 pb_headroom = IXGBE_DMACRXT_10G;
 487                 break;
 488         }
 489
 490         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 491                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 492
 493         /* Set the per Rx packet buffer receive threshold */
 494         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 495                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 496                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 497
 498                 if (tc < hw->mac.dmac_config.num_tcs) {
 499                         /* Get Rx PB size */
 500                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 501                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 502                                 IXGBE_RXPBSIZE_SHIFT;
 503
 504                         /* Calculate receive buffer threshold in kilobytes */
 505                         if (rx_pb_size > pb_headroom)
 506                                 rx_pb_size = rx_pb_size - pb_headroom;
 507                         else
 508                                 rx_pb_size = 0;
 509
 510                         /* Minimum of MFS shall be set for DMCTH */
 511                         reg |= (rx_pb_size > maxframe_size_kb) ?
 512                                 rx_pb_size : maxframe_size_kb;
 513                 }
 514                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 515         }
 516         return IXGBE_SUCCESS;
 517 }
 518
 519 /**
 520  *  ixgbe_dmac_update_tcs_X550
 521  *  @hw: pointer to hardware structure
 522  *
 523  *  Disables dmac, updates per TC settings, and then enables dmac.
 524  **/
 525 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 526 {
 527         u32 reg;
 528
 529         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 530
 531         /* Disable DMA coalescing before configuring */
 532         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 533         reg &= ~IXGBE_DMACR_DMAC_EN;
 534         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 535
 536         ixgbe_dmac_config_tcs_X550(hw);
 537
 538         /* Enable DMA coalescing after configuration */
 539         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 540         reg |= IXGBE_DMACR_DMAC_EN;
 541         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 542
 543         return IXGBE_SUCCESS;
 544 }
 545
 546 /**
 547  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 548  *  @hw: pointer to hardware structure
 549  *
 550  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 551  *  ixgbe_hw struct in order to set up EEPROM access.
 552  **/
 553 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 554 {
 555         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 556         u32 eec;
 557         u16 eeprom_size;
 558
 559         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 560
 561         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 562                 eeprom->semaphore_delay = 10;
 563                 eeprom->type = ixgbe_flash;
 564
 565                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 566                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 567                                     IXGBE_EEC_SIZE_SHIFT);
 568                 eeprom->word_size = 1 << (eeprom_size +
 569                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 570
 571                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 572                           eeprom->type, eeprom->word_size);
 573         }
 574
 575         return IXGBE_SUCCESS;
 576 }
 577
 578 /**
 579  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 580  *  @hw: pointer to the HW structure
 581  *  @enable_eee: boolean flag to enable EEE
 582  *
 583  *  Enable/disable EEE based on enable_eee flag.
 584  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 585  *  are modified.
 586  *
 587  **/
 588 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 589 {
 590         u32 eeer;
 591         u16 autoneg_eee_reg;
 592         u32 link_reg;
 593         s32 status;
 594
 595         DEBUGFUNC("ixgbe_setup_eee_X550");
 596
 597         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 598         /* Enable or disable EEE per flag */
 599         if (enable_eee) {
 600                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 601
 602                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 603                         /* Advertise EEE capability */
 604                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 605                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 606
 607                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 608                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 609                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 610
 611                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 612                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 613                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 614                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 615                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 616                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 617                         if (status != IXGBE_SUCCESS)
 618                                 return status;
 619
 620                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 621                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 622
 623                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 624                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 625                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 626                         if (status != IXGBE_SUCCESS)
 627                                 return status;
 628                 }
 629         } else {
 630                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 631
 632                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 633                         /* Disable advertised EEE capability */
 634                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 635                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 636
 637                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 638                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 639                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 640
 641                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 642                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 643                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 644                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 645                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 646                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 647                         if (status != IXGBE_SUCCESS)
 648                                 return status;
 649
 650                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 651                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 652
 653                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 654                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 655                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 656                         if (status != IXGBE_SUCCESS)
 657                                 return status;
 658                 }
 659         }
 660         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 661
 662         return IXGBE_SUCCESS;
 663 }
 664
 665 /**
 666  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 667  * @hw: pointer to hardware structure
 668  * @enable: enable or disable source address pruning
 669  * @pool: Rx pool to set source address pruning for
 670  **/
 671 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 672                                            unsigned int pool)
 673 {
 674         u64 pfflp;
 675
 676         /* max rx pool is 63 */
 677         if (pool > 63)
 678                 return;
 679
 680         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 681         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 682
 683         if (enable)
 684                 pfflp |= (1ULL << pool);
 685         else
 686                 pfflp &= ~(1ULL << pool);
 687
 688         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 689         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 690 }
 691
 692 /**
 693  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 694  *  @hw: pointer to hardware structure
 695  *  @enable: enable or disable switch for Ethertype anti-spoofing
 696  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 697  *
 698  **/
 699 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 700                 bool enable, int vf)
 701 {
 702         int vf_target_reg = vf >> 3;
 703         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 704         u32 pfvfspoof;
 705
 706         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 707
 708         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 709         if (enable)
 710                 pfvfspoof |= (1 << vf_target_shift);
 711         else
 712                 pfvfspoof &= ~(1 << vf_target_shift);
 713
 714         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 715 }
 716
 717 /**
 718  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 719  *  device
 720  *  @hw: pointer to hardware structure
 721  *  @reg_addr: 32 bit PHY register to write
 722  *  @device_type: 3 bit device type
 723  *  @data: Data to write to the register
 724  **/
 725 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 726                             u32 device_type, u32 data)
 727 {
 728         u32 i, command, error;
 729
 730         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 731                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 732
 733         /* Write IOSF control register */
 734         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 735
 736         /* Write IOSF data register */
 737         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 738         /*
 739          * Check every 10 usec to see if the address cycle completed.
 740          * The SB IOSF BUSY bit will clear when the operation is
 741          * complete
 742          */
 743         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 744                 usec_delay(10);
 745
 746                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 747                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 748                         break;
 749         }
 750
 751         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 752                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 753                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 754                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 755                               "Failed to write, error %x\n", error);
 756                 return IXGBE_ERR_PHY;
 757         }
 758
 759         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 760                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Write timed out\n");
 761                 return IXGBE_ERR_PHY;
 762         }
 763
 764         return IXGBE_SUCCESS;
 765 }
 766
 767 /**
 768  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 769  *  device
 770  *  @hw: pointer to hardware structure
 771  *  @reg_addr: 32 bit PHY register to write
 772  *  @device_type: 3 bit device type
 773  *  @phy_data: Pointer to read data from the register
 774  **/
 775 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 776                            u32 device_type, u32 *data)
 777 {
 778         u32 i, command, error;
 779
 780         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 781                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 782
 783         /* Write IOSF control register */
 784         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 785
 786         /*
 787          * Check every 10 usec to see if the address cycle completed.
 788          * The SB IOSF BUSY bit will clear when the operation is
 789          * complete
 790          */
 791         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 792                 usec_delay(10);
 793
 794                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 795                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 796                         break;
 797         }
 798
 799         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 800                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 801                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 802                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 803                                 "Failed to read, error %x\n", error);
 804                 return IXGBE_ERR_PHY;
 805         }
 806
 807         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 808                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Read timed out\n");
 809                 return IXGBE_ERR_PHY;
 810         }
 811
 812         *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 813
 814         return IXGBE_SUCCESS;
 815 }
 816
 817 /**
 818  *  ixgbe_disable_mdd_X550
 819  *  @hw: pointer to hardware structure
 820  *
 821  *  Disable malicious driver detection
 822  **/
 823 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
 824 {
 825         u32 reg;
 826
 827         DEBUGFUNC("ixgbe_disable_mdd_X550");
 828
 829         /* Disable MDD for TX DMA and interrupt */
 830         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 831         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 832         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 833
 834         /* Disable MDD for RX and interrupt */
 835         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 836         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 837         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 838 }
 839
 840 /**
 841  *  ixgbe_enable_mdd_X550
 842  *  @hw: pointer to hardware structure
 843  *
 844  *  Enable malicious driver detection
 845  **/
 846 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
 847 {
 848         u32 reg;
 849
 850         DEBUGFUNC("ixgbe_enable_mdd_X550");
 851
 852         /* Enable MDD for TX DMA and interrupt */
 853         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 854         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 855         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 856
 857         /* Enable MDD for RX and interrupt */
 858         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 859         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 860         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 861 }
 862
 863 /**
 864  *  ixgbe_restore_mdd_vf_X550
 865  *  @hw: pointer to hardware structure
 866  *  @vf: vf index
 867  *
 868  *  Restore VF that was disabled during malicious driver detection event
 869  **/
 870 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
 871 {
 872         u32 idx, reg, num_qs, start_q, bitmask;
 873
 874         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
 875
 876         /* Map VF to queues */
 877         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 878         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 879         case IXGBE_MRQC_VMDQRT8TCEN:
 880                 num_qs = 8;  /* 16 VFs / pools */
 881                 bitmask = 0x000000FF;
 882                 break;
 883         case IXGBE_MRQC_VMDQRSS32EN:
 884         case IXGBE_MRQC_VMDQRT4TCEN:
 885                 num_qs = 4;  /* 32 VFs / pools */
 886                 bitmask = 0x0000000F;
 887                 break;
 888         default:            /* 64 VFs / pools */
 889                 num_qs = 2;
 890                 bitmask = 0x00000003;
 891                 break;
 892         }
 893         start_q = vf * num_qs;
 894
 895         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
 896         idx = start_q / 32;
 897         reg = 0;
 898         reg |= (bitmask << (start_q % 32));
 899         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
 900         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
 901 }
 902
 903 /**
 904  *  ixgbe_mdd_event_X550
 905  *  @hw: pointer to hardware structure
 906  *  @vf_bitmap: vf bitmap of malicious vfs
 907  *
 908  *  Handle malicious driver detection event.
 909  **/
 910 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
 911 {
 912         u32 wqbr;
 913         u32 i, j, reg, q, shift, vf, idx;
 914
 915         DEBUGFUNC("ixgbe_mdd_event_X550");
 916
 917         /* figure out pool size for mapping to vf's */
 918         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 919         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 920         case IXGBE_MRQC_VMDQRT8TCEN:
 921                 shift = 3;  /* 16 VFs / pools */
 922                 break;
 923         case IXGBE_MRQC_VMDQRSS32EN:
 924         case IXGBE_MRQC_VMDQRT4TCEN:
 925                 shift = 2;  /* 32 VFs / pools */
 926                 break;
 927         default:
 928                 shift = 1;  /* 64 VFs / pools */
 929                 break;
 930         }
 931
 932         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
 933         for (i = 0; i < 4; i++) {
 934                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
 935                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
 936
 937                 if (!wqbr)
 938                         continue;
 939
 940                 /* Get malicious queue */
 941                 for (j = 0; j < 32 && wqbr; j++) {
 942
 943                         if (!(wqbr & (1 << j)))
 944                                 continue;
 945
 946                         /* Get queue from bitmask */
 947                         q = j + (i * 32);
 948
 949                         /* Map queue to vf */
 950                         vf = (q >> shift);
 951
 952                         /* Set vf bit in vf_bitmap */
 953                         idx = vf / 32;
 954                         vf_bitmap[idx] |= (1 << (vf % 32));
 955                         wqbr &= ~(1 << j);
 956                 }
 957         }
 958 }
 959
 960 /**
 961  *  ixgbe_get_media_type_X550em - Get media type
 962  *  @hw: pointer to hardware structure
 963  *
 964  *  Returns the media type (fiber, copper, backplane)
 965  */
 966 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
 967 {
 968         enum ixgbe_media_type media_type;
 969
 970         DEBUGFUNC("ixgbe_get_media_type_X550em");
 971
 972         /* Detect if there is a copper PHY attached. */
 973         switch (hw->device_id) {
 974         case IXGBE_DEV_ID_X550EM_X_KR:
 975         case IXGBE_DEV_ID_X550EM_X_KX4:
 976                 media_type = ixgbe_media_type_backplane;
 977                 break;
 978         case IXGBE_DEV_ID_X550EM_X_SFP:
 979                 media_type = ixgbe_media_type_fiber;
 980                 break;
 981         case IXGBE_DEV_ID_X550EM_X_1G_T:
 982         case IXGBE_DEV_ID_X550EM_X_10G_T:
 983                 media_type = ixgbe_media_type_copper;
 984                 break;
 985         default:
 986                 media_type = ixgbe_media_type_unknown;
 987                 break;
 988         }
 989         return media_type;
 990 }
 991
 992 /**
 993  *  ixgbe_setup_sfp_modules_X550em - Setup SFP module
 994  *  @hw: pointer to hardware structure
 995  */
 996 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
 997 {
 998         bool setup_linear;
 999         u16 reg_slice, edc_mode;
1000         s32 ret_val;
1001
1002         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1003
1004         switch (hw->phy.sfp_type) {
1005         case ixgbe_sfp_type_unknown:
1006                 return IXGBE_SUCCESS;
1007         case ixgbe_sfp_type_not_present:
1008                 return IXGBE_ERR_SFP_NOT_PRESENT;
1009         case ixgbe_sfp_type_da_cu_core0:
1010         case ixgbe_sfp_type_da_cu_core1:
1011                 setup_linear = true;
1012                 break;
1013         case ixgbe_sfp_type_srlr_core0:
1014         case ixgbe_sfp_type_srlr_core1:
1015         case ixgbe_sfp_type_da_act_lmt_core0:
1016         case ixgbe_sfp_type_da_act_lmt_core1:
1017         case ixgbe_sfp_type_1g_sx_core0:
1018         case ixgbe_sfp_type_1g_sx_core1:
1019         case ixgbe_sfp_type_1g_lx_core0:
1020         case ixgbe_sfp_type_1g_lx_core1:
1021                 setup_linear = false;
1022                 break;
1023         default:
1024                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1025         }
1026
1027         ixgbe_init_mac_link_ops_X550em(hw);
1028         hw->phy.ops.reset = NULL;
1029
1030         /* The CS4227 slice address is the base address + the port-pair reg
1031          * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0.
1032          */
1033         reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->bus.lan_id << 12);
1034
1035         if (setup_linear)
1036                 edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1037         else
1038                 edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1039
1040         /* Configure CS4227 for connection type. */
1041         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1042                                            edc_mode);
1043
1044         if (ret_val != IXGBE_SUCCESS)
1045                 ret_val = ixgbe_write_i2c_combined(hw, 0x80, reg_slice,
1046                                                    edc_mode);
1047
1048         return ret_val;
1049 }
1050
1051 /**
1052  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1053  *  @hw: pointer to hardware structure
1054  */
1055 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1056 {
1057         struct ixgbe_mac_info *mac = &hw->mac;
1058
1059         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1060
1061          switch (hw->mac.ops.get_media_type(hw)) {
1062          case ixgbe_media_type_fiber:
1063                 /* CS4227 does not support autoneg, so disable the laser control
1064                  * functions for SFP+ fiber
1065                  */
1066                 mac->ops.disable_tx_laser = NULL;
1067                 mac->ops.enable_tx_laser = NULL;
1068                 mac->ops.flap_tx_laser = NULL;
1069                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1070                 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1071                 mac->ops.set_rate_select_speed =
1072                                         ixgbe_set_soft_rate_select_speed;
1073                 break;
1074         case ixgbe_media_type_copper:
1075                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1076                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1077                 break;
1078         default:
1079                 break;
1080          }
1081 }
1082
1083 /**
1084  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1085  *  @hw: pointer to hardware structure
1086  *  @speed: pointer to link speed
1087  *  @autoneg: true when autoneg or autotry is enabled
1088  */
1089 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1090                                        ixgbe_link_speed *speed,
1091                                        bool *autoneg)
1092 {
1093         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1094
1095         /* SFP */
1096         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1097
1098                 /* CS4227 SFP must not enable auto-negotiation */
1099                 *autoneg = false;
1100
1101                 /* Check if 1G SFP module. */
1102                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1103                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1104                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1105                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1106                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1107                         return IXGBE_SUCCESS;
1108                 }
1109
1110                 /* Link capabilities are based on SFP */
1111                 if (hw->phy.multispeed_fiber)
1112                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1113                                  IXGBE_LINK_SPEED_1GB_FULL;
1114                 else
1115                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1116         } else {
1117                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1118                          IXGBE_LINK_SPEED_1GB_FULL;
1119                 *autoneg = true;
1120         }
1121
1122         return IXGBE_SUCCESS;
1123 }
1124
1125 /**
1126  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1127  * @hw: pointer to hardware structure
1128  * @lsc: pointer to boolean flag which indicates whether external Base T
1129  *       PHY interrupt is lsc
1130  *
1131  * Determime if external Base T PHY interrupt cause is high temperature
1132  * failure alarm or link status change.
1133  *
1134  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1135  * failure alarm, else return PHY access status.
1136  */
1137 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1138 {
1139         u32 status;
1140         u16 reg;
1141
1142         *lsc = false;
1143
1144         /* Vendor alarm triggered */
1145         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1146                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1147                                       &reg);
1148
1149         if (status != IXGBE_SUCCESS ||
1150             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1151                 return status;
1152
1153         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1154         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1155                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1156                                       &reg);
1157
1158         if (status != IXGBE_SUCCESS ||
1159             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1160             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1161                 return status;
1162
1163         /* High temperature failure alarm triggered */
1164         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1165                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1166                                       &reg);
1167
1168         if (status != IXGBE_SUCCESS)
1169                 return status;
1170
1171         /* If high temperature failure, then return over temp error and exit */
1172         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL)
1173                 return IXGBE_ERR_OVERTEMP;
1174
1175         /* Vendor alarm 2 triggered */
1176         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1177                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1178
1179         if (status != IXGBE_SUCCESS ||
1180             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1181                 return status;
1182
1183         /* link connect/disconnect event occurred */
1184         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1185                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1186
1187         if (status != IXGBE_SUCCESS)
1188                 return status;
1189
1190         /* Indicate LSC */
1191         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1192                 *lsc = true;
1193
1194         return IXGBE_SUCCESS;
1195 }
1196
1197 /**
1198  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1199  * @hw: pointer to hardware structure
1200  *
1201  * Enable link status change and temperature failure alarm for the external
1202  * Base T PHY
1203  *
1204  * Returns PHY access status
1205  */
1206 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1207 {
1208         u32 status;
1209         u16 reg;
1210         bool lsc;
1211
1212         /* Clear interrupt flags */
1213         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1214
1215         /* Enable link status change alarm */
1216         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1217                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1218
1219         if (status != IXGBE_SUCCESS)
1220                 return status;
1221
1222         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1223
1224         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1225                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1226
1227         if (status != IXGBE_SUCCESS)
1228                 return status;
1229
1230         /* Enables high temperature failure alarm */
1231         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1232                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1233                                       &reg);
1234
1235         if (status != IXGBE_SUCCESS)
1236                 return status;
1237
1238         reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;
1239
1240         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1241                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1242                                        reg);
1243
1244         if (status != IXGBE_SUCCESS)
1245                 return status;
1246
1247         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1248         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1249                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1250                                       &reg);
1251
1252         if (status != IXGBE_SUCCESS)
1253                 return status;
1254
1255         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1256                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1257
1258         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1259                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1260                                        reg);
1261
1262         if (status != IXGBE_SUCCESS)
1263                 return status;
1264
1265         /* Enable chip-wide vendor alarm */
1266         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1267                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1268                                       &reg);
1269
1270         if (status != IXGBE_SUCCESS)
1271                 return status;
1272
1273         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1274
1275         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1276                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1277                                        reg);
1278
1279         return status;
1280 }
1281
1282 /**
1283  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1284  *  @hw: pointer to hardware structure
1285  *
1286  *  Initialize any function pointers that were not able to be
1287  *  set during init_shared_code because the PHY/SFP type was
1288  *  not known.  Perform the SFP init if necessary.
1289  */
1290 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1291 {
1292         struct ixgbe_phy_info *phy = &hw->phy;
1293         s32 ret_val;
1294
1295         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1296
1297         hw->mac.ops.set_lan_id(hw);
1298
1299         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1300                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1301                 ixgbe_setup_mux_ctl(hw);
1302         }
1303
1304         /* Identify the PHY or SFP module */
1305         ret_val = phy->ops.identify(hw);
1306         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1307                 return ret_val;
1308
1309         /* Setup function pointers based on detected hardware */
1310         ixgbe_init_mac_link_ops_X550em(hw);
1311         if (phy->sfp_type != ixgbe_sfp_type_unknown)
1312                 phy->ops.reset = NULL;
1313
1314         /* Set functions pointers based on phy type */
1315         switch (hw->phy.type) {
1316         case ixgbe_phy_x550em_kx4:
1317                 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
1318                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1319                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1320                 break;
1321         case ixgbe_phy_x550em_kr:
1322                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1323                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1324                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1325                 break;
1326         case ixgbe_phy_x550em_ext_t:
1327                 phy->ops.setup_internal_link =
1328                                          ixgbe_setup_internal_phy_t_x550em;
1329                 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1330                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1331                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1332                 break;
1333         default:
1334                 break;
1335         }
1336         return ret_val;
1337 }
1338
1339 /**
1340  *  ixgbe_reset_hw_X550em - Perform hardware reset
1341  *  @hw: pointer to hardware structure
1342  *
1343  *  Resets the hardware by resetting the transmit and receive units, masks
1344  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1345  *  reset.
1346  */
1347 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1348 {
1349         struct ixgbe_hic_hdr fw_cmd;
1350         ixgbe_link_speed link_speed;
1351         s32 status;
1352         u32 ctrl = 0;
1353         u32 i;
1354         bool link_up = false;
1355
1356         DEBUGFUNC("ixgbe_reset_hw_X550em");
1357
1358         fw_cmd.cmd = FW_PHY_MGMT_REQ_CMD;
1359         fw_cmd.buf_len = 0;
1360         fw_cmd.cmd_or_resp.cmd_resv = 0;
1361         fw_cmd.checksum = FW_DEFAULT_CHECKSUM;
1362         status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
1363                                               sizeof(fw_cmd),
1364                                               IXGBE_HI_PHY_MGMT_REQ_TIMEOUT,
1365                                               true);
1366         if (status)
1367                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
1368                               "PHY mgmt command failed with %d\n", status);
1369         else if (fw_cmd.cmd_or_resp.ret_status != FW_CEM_RESP_STATUS_SUCCESS)
1370                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
1371                               "PHY mgmt command returned %d\n",
1372                               fw_cmd.cmd_or_resp.ret_status);
1373
1374         /* Call adapter stop to disable Tx/Rx and clear interrupts */
1375         status = hw->mac.ops.stop_adapter(hw);
1376         if (status != IXGBE_SUCCESS)
1377                 return status;
1378
1379         /* flush pending Tx transactions */
1380         ixgbe_clear_tx_pending(hw);
1381
1382         /* PHY ops must be identified and initialized prior to reset */
1383
1384         /* Identify PHY and related function pointers */
1385         status = hw->phy.ops.init(hw);
1386
1387         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1388                 return status;
1389
1390         /* start the external PHY */
1391         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1392                 status = ixgbe_init_ext_t_x550em(hw);
1393                 if (status)
1394                         return status;
1395         }
1396
1397         /* Setup SFP module if there is one present. */
1398         if (hw->phy.sfp_setup_needed) {
1399                 status = hw->mac.ops.setup_sfp(hw);
1400                 hw->phy.sfp_setup_needed = false;
1401         }
1402
1403         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1404                 return status;
1405
1406         /* Reset PHY */
1407         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1408                 hw->phy.ops.reset(hw);
1409
1410 mac_reset_top:
1411         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1412          * If link reset is used when link is up, it might reset the PHY when
1413          * mng is using it.  If link is down or the flag to force full link
1414          * reset is set, then perform link reset.
1415          */
1416         ctrl = IXGBE_CTRL_LNK_RST;
1417         if (!hw->force_full_reset) {
1418                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1419                 if (link_up)
1420                         ctrl = IXGBE_CTRL_RST;
1421         }
1422
1423         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1424         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1425         IXGBE_WRITE_FLUSH(hw);
1426
1427         /* Poll for reset bit to self-clear meaning reset is complete */
1428         for (i = 0; i < 10; i++) {
1429                 usec_delay(1);
1430                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1431                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1432                         break;
1433         }
1434
1435         if (ctrl & IXGBE_CTRL_RST_MASK) {
1436                 status = IXGBE_ERR_RESET_FAILED;
1437                 DEBUGOUT("Reset polling failed to complete.\n");
1438         }
1439
1440         msec_delay(50);
1441
1442         /* Double resets are required for recovery from certain error
1443          * conditions.  Between resets, it is necessary to stall to
1444          * allow time for any pending HW events to complete.
1445          */
1446         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1447                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1448                 goto mac_reset_top;
1449         }
1450
1451         /* Store the permanent mac address */
1452         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1453
1454         /* Store MAC address from RAR0, clear receive address registers, and
1455          * clear the multicast table.  Also reset num_rar_entries to 128,
1456          * since we modify this value when programming the SAN MAC address.
1457          */
1458         hw->mac.num_rar_entries = 128;
1459         hw->mac.ops.init_rx_addrs(hw);
1460
1461
1462         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1463                 ixgbe_setup_mux_ctl(hw);
1464
1465         return status;
1466 }
1467
1468 /**
1469  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1470  * @hw: pointer to hardware structure
1471  */
1472 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1473 {
1474         u32 status;
1475         u16 reg;
1476
1477         status = hw->phy.ops.read_reg(hw,
1478                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1479                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1480                                       &reg);
1481
1482         if (status != IXGBE_SUCCESS)
1483                 return status;
1484
1485         /* If PHY FW reset completed bit is set then this is the first
1486          * SW instance after a power on so the PHY FW must be un-stalled.
1487          */
1488         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1489                 status = hw->phy.ops.read_reg(hw,
1490                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1491                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1492                                         &reg);
1493
1494                 if (status != IXGBE_SUCCESS)
1495                         return status;
1496
1497                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1498
1499                 status = hw->phy.ops.write_reg(hw,
1500                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1501                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1502                                         reg);
1503
1504                 if (status != IXGBE_SUCCESS)
1505                         return status;
1506         }
1507
1508         return status;
1509 }
1510
1511 /**
1512  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1513  *  @hw: pointer to hardware structure
1514  *
1515  *  Configures the integrated KR PHY.
1516  **/
1517 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1518 {
1519         s32 status;
1520         u32 reg_val;
1521
1522         status = ixgbe_read_iosf_sb_reg_x550(hw,
1523                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1524                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1525         if (status)
1526                 return status;
1527
1528         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1529         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ |
1530                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC);
1531         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1532                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1533
1534         /* Advertise 10G support. */
1535         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1536                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1537
1538         /* Advertise 1G support. */
1539         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1540                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1541
1542         /* Restart auto-negotiation. */
1543         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1544         status = ixgbe_write_iosf_sb_reg_x550(hw,
1545                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1546                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1547
1548         return status;
1549 }
1550
1551 /**
1552  *  ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1553  *  @hw: pointer to hardware structure
1554  *
1555  *  Configures the integrated KX4 PHY.
1556  **/
1557 s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1558 {
1559         s32 status;
1560         u32 reg_val;
1561
1562         status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1563                 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, &reg_val);
1564         if (status)
1565                 return status;
1566
1567         reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1568                         IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1569
1570         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1571
1572         /* Advertise 10G support. */
1573         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1574                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1575
1576         /* Advertise 1G support. */
1577         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1578                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1579
1580         /* Restart auto-negotiation. */
1581         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1582         status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1583                 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, reg_val);
1584
1585         return status;
1586 }
1587
1588 /**
1589  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1590  *  @hw: pointer to hardware structure
1591  *  @speed: the link speed to force
1592  *
1593  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1594  *  internal and external PHY at a specific speed, without autonegotiation.
1595  **/
1596 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1597 {
1598         s32 status;
1599         u32 reg_val;
1600
1601         /* Disable AN and force speed to 10G Serial. */
1602         status = ixgbe_read_iosf_sb_reg_x550(hw,
1603                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1604                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1605         if (status != IXGBE_SUCCESS)
1606                 return status;
1607
1608         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1609         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1610
1611         /* Select forced link speed for internal PHY. */
1612         switch (*speed) {
1613         case IXGBE_LINK_SPEED_10GB_FULL:
1614                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1615                 break;
1616         case IXGBE_LINK_SPEED_1GB_FULL:
1617                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1618                 break;
1619         default:
1620                 /* Other link speeds are not supported by internal KR PHY. */
1621                 return IXGBE_ERR_LINK_SETUP;
1622         }
1623
1624         status = ixgbe_write_iosf_sb_reg_x550(hw,
1625                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1626                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1627         if (status != IXGBE_SUCCESS)
1628                 return status;
1629
1630         /* Disable training protocol FSM. */
1631         status = ixgbe_read_iosf_sb_reg_x550(hw,
1632                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1633                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1634         if (status != IXGBE_SUCCESS)
1635                 return status;
1636         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1637         status = ixgbe_write_iosf_sb_reg_x550(hw,
1638                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1639                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1640         if (status != IXGBE_SUCCESS)
1641                 return status;
1642
1643         /* Disable Flex from training TXFFE. */
1644         status = ixgbe_read_iosf_sb_reg_x550(hw,
1645                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1646                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1647         if (status != IXGBE_SUCCESS)
1648                 return status;
1649         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1650         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1651         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1652         status = ixgbe_write_iosf_sb_reg_x550(hw,
1653                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1654                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1655         if (status != IXGBE_SUCCESS)
1656                 return status;
1657         status = ixgbe_read_iosf_sb_reg_x550(hw,
1658                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1659                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1660         if (status != IXGBE_SUCCESS)
1661                 return status;
1662         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1663         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1664         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1665         status = ixgbe_write_iosf_sb_reg_x550(hw,
1666                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1667                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1668         if (status != IXGBE_SUCCESS)
1669                 return status;
1670
1671         /* Enable override for coefficients. */
1672         status = ixgbe_read_iosf_sb_reg_x550(hw,
1673                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1674                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1675         if (status != IXGBE_SUCCESS)
1676                 return status;
1677         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1678         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1679         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1680         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1681         status = ixgbe_write_iosf_sb_reg_x550(hw,
1682                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1683                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1684         if (status != IXGBE_SUCCESS)
1685                 return status;
1686
1687         /* Toggle port SW reset by AN reset. */
1688         status = ixgbe_read_iosf_sb_reg_x550(hw,
1689                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1690                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1691         if (status != IXGBE_SUCCESS)
1692                 return status;
1693         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1694         status = ixgbe_write_iosf_sb_reg_x550(hw,
1695                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1696                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1697
1698         return status;
1699 }
1700
1701 /**
1702  *  ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
1703  *  @hw: pointer to hardware structure
1704  *
1705  *  Configures the integrated KR PHY for SFP support.
1706  **/
1707 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1708                                     ixgbe_link_speed speed,
1709                                     bool autoneg_wait_to_complete)
1710 {
1711         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1712
1713         return ixgbe_setup_ixfi_x550em(hw, &speed);
1714 }
1715
1716 /**
1717  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1718  * @hw: point to hardware structure
1719  *
1720  * Configures the link between the integrated KR PHY and the external X557 PHY
1721  * The driver will call this function when it gets a link status change
1722  * interrupt from the X557 PHY. This function configures the link speed
1723  * between the PHYs to match the link speed of the BASE-T link.
1724  *
1725  * A return of a non-zero value indicates an error, and the base driver should
1726  * not report link up.
1727  */
1728 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
1729 {
1730         u32 status;
1731         u16 autoneg_status, speed;
1732         ixgbe_link_speed force_speed;
1733
1734         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1735                 return IXGBE_ERR_CONFIG;
1736
1737         /* read this twice back to back to indicate current status */
1738         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1739                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1740                                       &autoneg_status);
1741         if (status != IXGBE_SUCCESS)
1742                 return status;
1743
1744         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1745                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1746                                       &autoneg_status);
1747         if (status != IXGBE_SUCCESS)
1748                 return status;
1749
1750         /* If link is not up, then there is no setup necessary so return  */
1751         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1752                 return IXGBE_SUCCESS;
1753
1754         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1755                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1756                                       &speed);
1757
1758         /* clear everything but the speed and duplex bits */
1759         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1760
1761         switch (speed) {
1762         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1763                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1764                 break;
1765         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1766                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1767                 break;
1768         default:
1769                 /* Internal PHY does not support anything else */
1770                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1771         }
1772
1773         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1774 }
1775
1776 /**
1777  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1778  *  @hw: pointer to hardware structure
1779  *
1780  *  Configures the integrated KR PHY to use internal loopback mode.
1781  **/
1782 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1783 {
1784         s32 status;
1785         u32 reg_val;
1786
1787         /* Disable AN and force speed to 10G Serial. */
1788         status = ixgbe_read_iosf_sb_reg_x550(hw,
1789                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1790                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1791         if (status != IXGBE_SUCCESS)
1792                 return status;
1793         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1794         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1795         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1796         status = ixgbe_write_iosf_sb_reg_x550(hw,
1797                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1798                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1799         if (status != IXGBE_SUCCESS)
1800                 return status;
1801
1802         /* Set near-end loopback clocks. */
1803         status = ixgbe_read_iosf_sb_reg_x550(hw,
1804                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1805                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1806         if (status != IXGBE_SUCCESS)
1807                 return status;
1808         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1809         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1810         status = ixgbe_write_iosf_sb_reg_x550(hw,
1811                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1812                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1813         if (status != IXGBE_SUCCESS)
1814                 return status;
1815
1816         /* Set loopback enable. */
1817         status = ixgbe_read_iosf_sb_reg_x550(hw,
1818                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1819                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1820         if (status != IXGBE_SUCCESS)
1821                 return status;
1822         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1823         status = ixgbe_write_iosf_sb_reg_x550(hw,
1824                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1825                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1826         if (status != IXGBE_SUCCESS)
1827                 return status;
1828
1829         /* Training bypass. */
1830         status = ixgbe_read_iosf_sb_reg_x550(hw,
1831                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1832                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1833         if (status != IXGBE_SUCCESS)
1834                 return status;
1835         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
1836         status = ixgbe_write_iosf_sb_reg_x550(hw,
1837                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1838                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1839
1840         return status;
1841 }
1842
1843 /**
1844  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1845  *  assuming that the semaphore is already obtained.
1846  *  @hw: pointer to hardware structure
1847  *  @offset: offset of  word in the EEPROM to read
1848  *  @data: word read from the EEPROM
1849  *
1850  *  Reads a 16 bit word from the EEPROM using the hostif.
1851  **/
1852 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1853                                    u16 *data)
1854 {
1855         s32 status;
1856         struct ixgbe_hic_read_shadow_ram buffer;
1857
1858         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
1859         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1860         buffer.hdr.req.buf_lenh = 0;
1861         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1862         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1863
1864         /* convert offset from words to bytes */
1865         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1866         /* one word */
1867         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1868
1869         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1870                                               sizeof(buffer),
1871                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1872
1873         if (status)
1874                 return status;
1875
1876         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1877                                           FW_NVM_DATA_OFFSET);
1878
1879         return 0;
1880 }
1881
1882 /**
1883  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1884  *  @hw: pointer to hardware structure
1885  *  @offset: offset of  word in the EEPROM to read
1886  *  @data: word read from the EEPROM
1887  *
1888  *  Reads a 16 bit word from the EEPROM using the hostif.
1889  **/
1890 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1891                               u16 *data)
1892 {
1893         s32 status = IXGBE_SUCCESS;
1894
1895         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
1896
1897         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1898             IXGBE_SUCCESS) {
1899                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
1900                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1901         } else {
1902                 status = IXGBE_ERR_SWFW_SYNC;
1903         }
1904
1905         return status;
1906 }
1907
1908 /**
1909  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
1910  *  @hw: pointer to hardware structure
1911  *  @offset: offset of  word in the EEPROM to read
1912  *  @words: number of words
1913  *  @data: word(s) read from the EEPROM
1914  *
1915  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
1916  **/
1917 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1918                                      u16 offset, u16 words, u16 *data)
1919 {
1920         struct ixgbe_hic_read_shadow_ram buffer;
1921         u32 current_word = 0;
1922         u16 words_to_read;
1923         s32 status;
1924         u32 i;
1925
1926         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
1927
1928         /* Take semaphore for the entire operation. */
1929         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1930         if (status) {
1931                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
1932                 return status;
1933         }
1934         while (words) {
1935                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
1936                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
1937                 else
1938                         words_to_read = words;
1939
1940                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1941                 buffer.hdr.req.buf_lenh = 0;
1942                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1943                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1944
1945                 /* convert offset from words to bytes */
1946                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
1947                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
1948
1949                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1950                                                       sizeof(buffer),
1951                                                       IXGBE_HI_COMMAND_TIMEOUT,
1952                                                       false);
1953
1954                 if (status) {
1955                         DEBUGOUT("Host interface command failed\n");
1956                         goto out;
1957                 }
1958
1959                 for (i = 0; i < words_to_read; i++) {
1960                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
1961                                   2 * i;
1962                         u32 value = IXGBE_READ_REG(hw, reg);
1963
1964                         data[current_word] = (u16)(value & 0xffff);
1965                         current_word++;
1966                         i++;
1967                         if (i < words_to_read) {
1968                                 value >>= 16;
1969                                 data[current_word] = (u16)(value & 0xffff);
1970                                 current_word++;
1971                         }
1972                 }
1973                 words -= words_to_read;
1974         }
1975
1976 out:
1977         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1978         return status;
1979 }
1980
1981 /**
1982  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1983  *  @hw: pointer to hardware structure
1984  *  @offset: offset of  word in the EEPROM to write
1985  *  @data: word write to the EEPROM
1986  *
1987  *  Write a 16 bit word to the EEPROM using the hostif.
1988  **/
1989 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1990                                     u16 data)
1991 {
1992         s32 status;
1993         struct ixgbe_hic_write_shadow_ram buffer;
1994
1995         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
1996
1997         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
1998         buffer.hdr.req.buf_lenh = 0;
1999         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
2000         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2001
2002          /* one word */
2003         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2004         buffer.data = data;
2005         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2006
2007         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2008                                               sizeof(buffer),
2009                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2010
2011         return status;
2012 }
2013
2014 /**
2015  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2016  *  @hw: pointer to hardware structure
2017  *  @offset: offset of  word in the EEPROM to write
2018  *  @data: word write to the EEPROM
2019  *
2020  *  Write a 16 bit word to the EEPROM using the hostif.
2021  **/
2022 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2023                                u16 data)
2024 {
2025         s32 status = IXGBE_SUCCESS;
2026
2027         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2028
2029         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2030             IXGBE_SUCCESS) {
2031                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2032                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2033         } else {
2034                 DEBUGOUT("write ee hostif failed to get semaphore");
2035                 status = IXGBE_ERR_SWFW_SYNC;
2036         }
2037
2038         return status;
2039 }
2040
2041 /**
2042  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2043  *  @hw: pointer to hardware structure
2044  *  @offset: offset of  word in the EEPROM to write
2045  *  @words: number of words
2046  *  @data: word(s) write to the EEPROM
2047  *
2048  *  Write a 16 bit word(s) to the EEPROM using the hostif.
2049  **/
2050 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2051                                       u16 offset, u16 words, u16 *data)
2052 {
2053         s32 status = IXGBE_SUCCESS;
2054         u32 i = 0;
2055
2056         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2057
2058         /* Take semaphore for the entire operation. */
2059         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2060         if (status != IXGBE_SUCCESS) {
2061                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2062                 goto out;
2063         }
2064
2065         for (i = 0; i < words; i++) {
2066                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2067                                                          data[i]);
2068
2069                 if (status != IXGBE_SUCCESS) {
2070                         DEBUGOUT("Eeprom buffered write failed\n");
2071                         break;
2072                 }
2073         }
2074
2075         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2076 out:
2077
2078         return status;
2079 }
2080
2081 /**
2082  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2083  * @hw: pointer to hardware structure
2084  * @ptr: pointer offset in eeprom
2085  * @size: size of section pointed by ptr, if 0 first word will be used as size
2086  * @csum: address of checksum to update
2087  *
2088  * Returns error status for any failure
2089  */
2090 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2091                                    u16 size, u16 *csum, u16 *buffer,
2092                                    u32 buffer_size)
2093 {
2094         u16 buf[256];
2095         s32 status;
2096         u16 length, bufsz, i, start;
2097         u16 *local_buffer;
2098
2099         bufsz = sizeof(buf) / sizeof(buf[0]);
2100
2101         /* Read a chunk at the pointer location */
2102         if (!buffer) {
2103                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2104                 if (status) {
2105                         DEBUGOUT("Failed to read EEPROM image\n");
2106                         return status;
2107                 }
2108                 local_buffer = buf;
2109         } else {
2110                 if (buffer_size < ptr)
2111                         return  IXGBE_ERR_PARAM;
2112                 local_buffer = &buffer[ptr];
2113         }
2114
2115         if (size) {
2116                 start = 0;
2117                 length = size;
2118         } else {
2119                 start = 1;
2120                 length = local_buffer[0];
2121
2122                 /* Skip pointer section if length is invalid. */
2123                 if (length == 0xFFFF || length == 0 ||
2124                     (ptr + length) >= hw->eeprom.word_size)
2125                         return IXGBE_SUCCESS;
2126         }
2127
2128         if (buffer && ((u32)start + (u32)length > buffer_size))
2129                 return IXGBE_ERR_PARAM;
2130
2131         for (i = start; length; i++, length--) {
2132                 if (i == bufsz && !buffer) {
2133                         ptr += bufsz;
2134                         i = 0;
2135                         if (length < bufsz)
2136                                 bufsz = length;
2137
2138                         /* Read a chunk at the pointer location */
2139                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2140                                                                   bufsz, buf);
2141                         if (status) {
2142                                 DEBUGOUT("Failed to read EEPROM image\n");
2143                                 return status;
2144                         }
2145                 }
2146                 *csum += local_buffer[i];
2147         }
2148         return IXGBE_SUCCESS;
2149 }
2150
2151 /**
2152  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2153  *  @hw: pointer to hardware structure
2154  *  @buffer: pointer to buffer containing calculated checksum
2155  *  @buffer_size: size of buffer
2156  *
2157  *  Returns a negative error code on error, or the 16-bit checksum
2158  **/
2159 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2160 {
2161         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2162         u16 *local_buffer;
2163         s32 status;
2164         u16 checksum = 0;
2165         u16 pointer, i, size;
2166
2167         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2168
2169         hw->eeprom.ops.init_params(hw);
2170
2171         if (!buffer) {
2172                 /* Read pointer area */
2173                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2174                                                      IXGBE_EEPROM_LAST_WORD + 1,
2175                                                      eeprom_ptrs);
2176                 if (status) {
2177                         DEBUGOUT("Failed to read EEPROM image\n");
2178                         return status;
2179                 }
2180                 local_buffer = eeprom_ptrs;
2181         } else {
2182                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2183                         return IXGBE_ERR_PARAM;
2184                 local_buffer = buffer;
2185         }
2186
2187         /*
2188          * For X550 hardware include 0x0-0x41 in the checksum, skip the
2189          * checksum word itself
2190          */
2191         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2192                 if (i != IXGBE_EEPROM_CHECKSUM)
2193                         checksum += local_buffer[i];
2194
2195         /*
2196          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
2197          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2198          */
2199         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2200                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2201                         continue;
2202
2203                 pointer = local_buffer[i];
2204
2205                 /* Skip pointer section if the pointer is invalid. */
2206                 if (pointer == 0xFFFF || pointer == 0 ||
2207                     pointer >= hw->eeprom.word_size)
2208                         continue;
2209
2210                 switch (i) {
2211                 case IXGBE_PCIE_GENERAL_PTR:
2212                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2213                         break;
2214                 case IXGBE_PCIE_CONFIG0_PTR:
2215                 case IXGBE_PCIE_CONFIG1_PTR:
2216                         size = IXGBE_PCIE_CONFIG_SIZE;
2217                         break;
2218                 default:
2219                         size = 0;
2220                         break;
2221                 }
2222
2223                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2224                                                 buffer, buffer_size);
2225                 if (status)
2226                         return status;
2227         }
2228
2229         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2230
2231         return (s32)checksum;
2232 }
2233
2234 /**
2235  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2236  *  @hw: pointer to hardware structure
2237  *
2238  *  Returns a negative error code on error, or the 16-bit checksum
2239  **/
2240 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2241 {
2242         return ixgbe_calc_checksum_X550(hw, NULL, 0);
2243 }
2244
2245 /**
2246  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2247  *  @hw: pointer to hardware structure
2248  *  @checksum_val: calculated checksum
2249  *
2250  *  Performs checksum calculation and validates the EEPROM checksum.  If the
2251  *  caller does not need checksum_val, the value can be NULL.
2252  **/
2253 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2254 {
2255         s32 status;
2256         u16 checksum;
2257         u16 read_checksum = 0;
2258
2259         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2260
2261         /* Read the first word from the EEPROM. If this times out or fails, do
2262          * not continue or we could be in for a very long wait while every
2263          * EEPROM read fails
2264          */
2265         status = hw->eeprom.ops.read(hw, 0, &checksum);
2266         if (status) {
2267                 DEBUGOUT("EEPROM read failed\n");
2268                 return status;
2269         }
2270
2271         status = hw->eeprom.ops.calc_checksum(hw);
2272         if (status < 0)
2273                 return status;
2274
2275         checksum = (u16)(status & 0xffff);
2276
2277         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2278                                            &read_checksum);
2279         if (status)
2280                 return status;
2281
2282         /* Verify read checksum from EEPROM is the same as
2283          * calculated checksum
2284          */
2285         if (read_checksum != checksum) {
2286                 status = IXGBE_ERR_EEPROM_CHECKSUM;
2287                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2288                              "Invalid EEPROM checksum");
2289         }
2290
2291         /* If the user cares, return the calculated checksum */
2292         if (checksum_val)
2293                 *checksum_val = checksum;
2294
2295         return status;
2296 }
2297
2298 /**
2299  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2300  * @hw: pointer to hardware structure
2301  *
2302  * After writing EEPROM to shadow RAM using EEWR register, software calculates
2303  * checksum and updates the EEPROM and instructs the hardware to update
2304  * the flash.
2305  **/
2306 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2307 {
2308         s32 status;
2309         u16 checksum = 0;
2310
2311         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2312
2313         /* Read the first word from the EEPROM. If this times out or fails, do
2314          * not continue or we could be in for a very long wait while every
2315          * EEPROM read fails
2316          */
2317         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2318         if (status) {
2319                 DEBUGOUT("EEPROM read failed\n");
2320                 return status;
2321         }
2322
2323         status = ixgbe_calc_eeprom_checksum_X550(hw);
2324         if (status < 0)
2325                 return status;
2326
2327         checksum = (u16)(status & 0xffff);
2328
2329         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2330                                             checksum);
2331         if (status)
2332                 return status;
2333
2334         status = ixgbe_update_flash_X550(hw);
2335
2336         return status;
2337 }
2338
2339 /**
2340  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2341  *  @hw: pointer to hardware structure
2342  *
2343  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2344  **/
2345 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2346 {
2347         s32 status = IXGBE_SUCCESS;
2348         union ixgbe_hic_hdr2 buffer;
2349
2350         DEBUGFUNC("ixgbe_update_flash_X550");
2351
2352         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2353         buffer.req.buf_lenh = 0;
2354         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2355         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2356
2357         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2358                                               sizeof(buffer),
2359                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2360
2361         return status;
2362 }
2363
2364 /**
2365  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2366  *  @hw: pointer to hardware structure
2367  *
2368  *  Determines physical layer capabilities of the current configuration.
2369  **/
2370 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2371 {
2372         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2373         u16 ext_ability = 0;
2374
2375         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2376
2377         hw->phy.ops.identify(hw);
2378
2379         switch (hw->phy.type) {
2380         case ixgbe_phy_x550em_kr:
2381                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2382                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2383                 break;
2384         case ixgbe_phy_x550em_kx4:
2385                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2386                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2387                 break;
2388         case ixgbe_phy_x550em_ext_t:
2389                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2390                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2391                                      &ext_ability);
2392                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2393                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2394                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2395                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2396                 break;
2397         default:
2398                 break;
2399         }
2400
2401         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2402                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2403
2404         return physical_layer;
2405 }
2406
2407 /**
2408  * ixgbe_get_bus_info_x550em - Set PCI bus info
2409  * @hw: pointer to hardware structure
2410  *
2411  * Sets bus link width and speed to unknown because X550em is
2412  * not a PCI device.
2413  **/
2414 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2415 {
2416
2417         DEBUGFUNC("ixgbe_get_bus_info_x550em");
2418
2419         hw->bus.width = ixgbe_bus_width_unknown;
2420         hw->bus.speed = ixgbe_bus_speed_unknown;
2421
2422         hw->mac.ops.set_lan_id(hw);
2423
2424         return IXGBE_SUCCESS;
2425 }
2426
2427 /**
2428  * ixgbe_disable_rx_x550 - Disable RX unit
2429  *
2430  * Enables the Rx DMA unit for x550
2431  **/
2432 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2433 {
2434         u32 rxctrl, pfdtxgswc;
2435         s32 status;
2436         struct ixgbe_hic_disable_rxen fw_cmd;
2437
2438         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2439
2440         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2441         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2442                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2443                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2444                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2445                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2446                         hw->mac.set_lben = true;
2447                 } else {
2448                         hw->mac.set_lben = false;
2449                 }
2450
2451                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2452                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2453                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2454                 fw_cmd.port_number = (u8)hw->bus.lan_id;
2455
2456                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2457                                         sizeof(struct ixgbe_hic_disable_rxen),
2458                                         IXGBE_HI_COMMAND_TIMEOUT, true);
2459
2460                 /* If we fail - disable RX using register write */
2461                 if (status) {
2462                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2463                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2464                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2465                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2466                         }
2467                 }
2468         }
2469 }
2470
2471 /**
2472  * ixgbe_enter_lplu_x550em - Transition to low power states
2473  *  @hw: pointer to hardware structure
2474  *
2475  * Configures Low Power Link Up on transition to low power states
2476  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2477  * X557 PHY immediately prior to entering LPLU.
2478  **/
2479 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2480 {
2481         u16 autoneg_status, an_10g_cntl_reg, autoneg_reg, speed;
2482         s32 status;
2483         ixgbe_link_speed lcd_speed;
2484
2485         /* If blocked by MNG FW, then don't restart AN */
2486         if (ixgbe_check_reset_blocked(hw))
2487                 return IXGBE_SUCCESS;
2488
2489         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2490                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2491                                       &autoneg_status);
2492
2493         if (status != IXGBE_SUCCESS)
2494                 return status;
2495
2496         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2497
2498         if (status != IXGBE_SUCCESS)
2499                 return status;
2500
2501         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2502          * disabled, then force link down by entering low power mode.
2503          */
2504         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS) ||
2505             !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2506             !(hw->wol_enabled || ixgbe_mng_present(hw)))
2507                 return ixgbe_set_copper_phy_power(hw, FALSE);
2508
2509         /* Determine LCD */
2510         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2511
2512         if (status != IXGBE_SUCCESS)
2513                 return status;
2514
2515         /* If no valid LCD link speed, then force link down and exit. */
2516         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2517                 return ixgbe_set_copper_phy_power(hw, FALSE);
2518
2519         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2520                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2521                                       &speed);
2522
2523         if (status != IXGBE_SUCCESS)
2524                 return status;
2525
2526         /* clear everything but the speed bits */
2527         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2528
2529         /* If current speed is already LCD, then exit. */
2530         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2531              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2532             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2533              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2534                 return status;
2535
2536         /* Clear AN completed indication */
2537         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2538                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2539                                       &autoneg_status);
2540
2541         if (status != IXGBE_SUCCESS)
2542                 return status;
2543
2544         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2545                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2546                              &an_10g_cntl_reg);
2547
2548         if (status != IXGBE_SUCCESS)
2549                 return status;
2550
2551         status = hw->phy.ops.read_reg(hw,
2552                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2553                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2554                              &autoneg_reg);
2555
2556         if (status != IXGBE_SUCCESS)
2557                 return status;
2558
2559         /* Set AN advertizement to only include LCD  */
2560         if (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL) {
2561                 an_10g_cntl_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
2562                 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
2563         }
2564
2565         if (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL) {
2566                 an_10g_cntl_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
2567                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
2568         }
2569
2570         status = hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2571                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2572                               an_10g_cntl_reg);
2573
2574         if (status != IXGBE_SUCCESS)
2575                 return status;
2576
2577         status = hw->phy.ops.write_reg(hw,
2578                               IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2579                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2580                               autoneg_reg);
2581
2582         if (status != IXGBE_SUCCESS)
2583                 return status;
2584
2585         /* Restart PHY auto-negotiation. */
2586         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
2587                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
2588
2589         if (status != IXGBE_SUCCESS)
2590                 return status;
2591
2592         autoneg_reg |= IXGBE_MII_RESTART;
2593
2594         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
2595                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
2596
2597         if (status != IXGBE_SUCCESS)
2598                 return status;
2599
2600         status = ixgbe_setup_ixfi_x550em(hw, &lcd_speed);
2601
2602         return status;
2603 }
2604
2605 /**
2606  * ixgbe_get_lcd_x550em - Determine lowest common denominator
2607  *  @hw: pointer to hardware structure
2608  *  @lcd_speed: pointer to lowest common link speed
2609  *
2610  * Determine lowest common link speed with link partner.
2611  **/
2612 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2613 {
2614         u16 an_lp_status;
2615         s32 status;
2616         u16 word = hw->eeprom.ctrl_word_3;
2617
2618         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2619
2620         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2621                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2622                                       &an_lp_status);
2623
2624         if (status != IXGBE_SUCCESS)
2625                 return status;
2626
2627         /* If link partner advertised 1G, return 1G */
2628         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2629                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2630                 return status;
2631         }
2632
2633         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2634         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2635             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2636                 return status;
2637
2638         /* Link partner not capable of lower speeds, return 10G */
2639         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2640         return status;
2641 }
2642
2643 /**
2644  *  ixgbe_setup_fc_X550em - Set up flow control
2645  *  @hw: pointer to hardware structure
2646  *
2647  *  Called at init time to set up flow control.
2648  **/
2649 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
2650 {
2651         s32 ret_val = IXGBE_SUCCESS;
2652         u32 pause, asm_dir, reg_val;
2653
2654         DEBUGFUNC("ixgbe_setup_fc_X550em");
2655
2656         /* Validate the requested mode */
2657         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2658                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2659                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2660                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2661                 goto out;
2662         }
2663
2664         /* 10gig parts do not have a word in the EEPROM to determine the
2665          * default flow control setting, so we explicitly set it to full.
2666          */
2667         if (hw->fc.requested_mode == ixgbe_fc_default)
2668                 hw->fc.requested_mode = ixgbe_fc_full;
2669
2670         /* Determine PAUSE and ASM_DIR bits. */
2671         switch (hw->fc.requested_mode) {
2672         case ixgbe_fc_none:
2673                 pause = 0;
2674                 asm_dir = 0;
2675                 break;
2676         case ixgbe_fc_tx_pause:
2677                 pause = 0;
2678                 asm_dir = 1;
2679                 break;
2680         case ixgbe_fc_rx_pause:
2681                 /* Rx Flow control is enabled and Tx Flow control is
2682                  * disabled by software override. Since there really
2683                  * isn't a way to advertise that we are capable of RX
2684                  * Pause ONLY, we will advertise that we support both
2685                  * symmetric and asymmetric Rx PAUSE, as such we fall
2686                  * through to the fc_full statement.  Later, we will
2687                  * disable the adapter's ability to send PAUSE frames.
2688                  */
2689         case ixgbe_fc_full:
2690                 pause = 1;
2691                 asm_dir = 1;
2692                 break;
2693         default:
2694                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2695                         "Flow control param set incorrectly\n");
2696                 ret_val = IXGBE_ERR_CONFIG;
2697                 goto out;
2698         }
2699
2700         if (hw->phy.media_type == ixgbe_media_type_backplane) {
2701                 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
2702                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2703                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2704                 if (ret_val != IXGBE_SUCCESS)
2705                         goto out;
2706                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2707                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2708                 if (pause)
2709                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2710                 if (asm_dir)
2711                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2712                 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
2713                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2714                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2715
2716                 /* Not all devices fully support AN. */
2717                 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR)
2718                         hw->fc.disable_fc_autoneg = true;
2719         }
2720
2721 out:
2722         return ret_val;
2723 }
2724
2725 /**
2726  * ixgbe_set_mux - Set mux for port 1 access with CS4227
2727  * @hw: pointer to hardware structure
2728  * @state: set mux if 1, clear if 0
2729  */
2730 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2731 {
2732         u32 esdp;
2733
2734         if (!hw->bus.lan_id)
2735                 return;
2736         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2737         if (state)
2738                 esdp |= IXGBE_ESDP_SDP1;
2739         else
2740                 esdp &= ~IXGBE_ESDP_SDP1;
2741         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2742         IXGBE_WRITE_FLUSH(hw);
2743 }
2744
2745 /**
2746  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2747  *  @hw: pointer to hardware structure
2748  *  @mask: Mask to specify which semaphore to acquire
2749  *
2750  *  Acquires the SWFW semaphore and sets the I2C MUX
2751  **/
2752 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2753 {
2754         s32 status;
2755
2756         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
2757
2758         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2759         if (status)
2760                 return status;
2761
2762         if (mask & IXGBE_GSSR_I2C_MASK)
2763                 ixgbe_set_mux(hw, 1);
2764
2765         return IXGBE_SUCCESS;
2766 }
2767
2768 /**
2769  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2770  *  @hw: pointer to hardware structure
2771  *  @mask: Mask to specify which semaphore to release
2772  *
2773  *  Releases the SWFW semaphore and sets the I2C MUX
2774  **/
2775 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2776 {
2777         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
2778
2779         if (mask & IXGBE_GSSR_I2C_MASK)
2780                 ixgbe_set_mux(hw, 0);
2781
2782         ixgbe_release_swfw_sync_X540(hw, mask);
2783 }
2784
2785 /**
2786  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2787  * @hw: pointer to hardware structure
2788  *
2789  * Handle external Base T PHY interrupt. If high temperature
2790  * failure alarm then return error, else if link status change
2791  * then setup internal/external PHY link
2792  *
2793  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2794  * failure alarm, else return PHY access status.
2795  */
2796 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2797 {
2798         bool lsc;
2799         u32 status;
2800
2801         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2802
2803         if (status != IXGBE_SUCCESS)
2804                 return status;
2805
2806         if (lsc)
2807                 return ixgbe_setup_internal_phy_t_x550em(hw);
2808
2809         return IXGBE_SUCCESS;
2810 }
2811
2812 /**
2813  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
2814  * @hw: pointer to hardware structure
2815  * @speed: new link speed
2816  * @autoneg_wait_to_complete: true when waiting for completion is needed
2817  *
2818  * Setup internal/external PHY link speed based on link speed, then set
2819  * external PHY auto advertised link speed.
2820  *
2821  * Returns error status for any failure
2822  **/
2823 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
2824                                   ixgbe_link_speed speed,
2825                                   bool autoneg_wait_to_complete)
2826 {
2827         s32 status;
2828         ixgbe_link_speed force_speed;
2829
2830         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
2831
2832         /* Setup internal/external PHY link speed to iXFI (10G), unless
2833          * only 1G is auto advertised then setup KX link.
2834          */
2835         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2836                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2837         else
2838                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2839
2840         status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
2841
2842         if (status != IXGBE_SUCCESS)
2843                 return status;
2844
2845         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
2846 }
2847
2848 /**
2849  * ixgbe_check_link_t_X550em - Determine link and speed status
2850  * @hw: pointer to hardware structure
2851  * @speed: pointer to link speed
2852  * @link_up: true when link is up
2853  * @link_up_wait_to_complete: bool used to wait for link up or not
2854  *
2855  * Check that both the MAC and X557 external PHY have link.
2856  **/
2857 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
2858                               bool *link_up, bool link_up_wait_to_complete)
2859 {
2860         u32 status;
2861         u16 autoneg_status;
2862
2863         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2864                 return IXGBE_ERR_CONFIG;
2865
2866         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
2867                                               link_up_wait_to_complete);
2868
2869         /* If check link fails or MAC link is not up, then return */
2870         if (status != IXGBE_SUCCESS || !(*link_up))
2871                 return status;
2872
2873         /* MAC link is up, so check external PHY link.
2874          * Read this twice back to back to indicate current status.
2875          */
2876         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2877                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2878                                       &autoneg_status);
2879
2880         if (status != IXGBE_SUCCESS)
2881                 return status;
2882
2883         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2884                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2885                                       &autoneg_status);
2886
2887         if (status != IXGBE_SUCCESS)
2888                 return status;
2889
2890         /* If external PHY link is not up, then indicate link not up */
2891         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
2892                 *link_up = false;
2893
2894         return IXGBE_SUCCESS;
2895 }
2896
2897 /**
2898  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
2899  *  @hw: pointer to hardware structure
2900  **/
2901 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
2902 {
2903         s32 status;
2904
2905         status = ixgbe_reset_phy_generic(hw);
2906
2907         if (status != IXGBE_SUCCESS)
2908                 return status;
2909
2910         /* Configure Link Status Alarm and Temperature Threshold interrupts */
2911         return ixgbe_enable_lasi_ext_t_x550em(hw);
2912 }