1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
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7 modification, are permitted provided that the following conditions are met:
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13 notice, this list of conditions and the following disclaimer in the
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32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
46 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
47 * @hw: pointer to hardware structure
49 * Initialize the function pointers and assign the MAC type for X550.
50 * Does not touch the hardware.
52 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
54 struct ixgbe_mac_info *mac = &hw->mac;
55 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
58 DEBUGFUNC("ixgbe_init_ops_X550");
60 ret_val = ixgbe_init_ops_X540(hw);
61 mac->ops.dmac_config = ixgbe_dmac_config_X550;
62 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
63 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
64 mac->ops.setup_eee = ixgbe_setup_eee_X550;
65 mac->ops.set_source_address_pruning =
66 ixgbe_set_source_address_pruning_X550;
67 mac->ops.set_ethertype_anti_spoofing =
68 ixgbe_set_ethertype_anti_spoofing_X550;
70 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
71 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
72 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
73 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
74 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
75 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
76 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
77 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
78 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
80 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
81 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
82 mac->ops.mdd_event = ixgbe_mdd_event_X550;
83 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
84 mac->ops.disable_rx = ixgbe_disable_rx_x550;
85 switch (hw->device_id) {
86 case IXGBE_DEV_ID_X550EM_X_10G_T:
87 case IXGBE_DEV_ID_X550EM_A_10G_T:
88 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
89 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
98 * ixgbe_read_cs4227 - Read CS4227 register
99 * @hw: pointer to hardware structure
100 * @reg: register number to write
101 * @value: pointer to receive value read
103 * Returns status code
105 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
107 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
111 * ixgbe_write_cs4227 - Write CS4227 register
112 * @hw: pointer to hardware structure
113 * @reg: register number to write
114 * @value: value to write to register
116 * Returns status code
118 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
120 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
124 * ixgbe_read_pe - Read register from port expander
125 * @hw: pointer to hardware structure
126 * @reg: register number to read
127 * @value: pointer to receive read value
129 * Returns status code
131 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
135 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
136 if (status != IXGBE_SUCCESS)
137 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
138 "port expander access failed with %d\n", status);
143 * ixgbe_write_pe - Write register to port expander
144 * @hw: pointer to hardware structure
145 * @reg: register number to write
146 * @value: value to write
148 * Returns status code
150 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
154 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
155 if (status != IXGBE_SUCCESS)
156 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
157 "port expander access failed with %d\n", status);
162 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
163 * @hw: pointer to hardware structure
165 * This function assumes that the caller has acquired the proper semaphore.
168 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
175 /* Trigger hard reset. */
176 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
177 if (status != IXGBE_SUCCESS)
179 reg |= IXGBE_PE_BIT1;
180 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
181 if (status != IXGBE_SUCCESS)
184 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
185 if (status != IXGBE_SUCCESS)
187 reg &= ~IXGBE_PE_BIT1;
188 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
189 if (status != IXGBE_SUCCESS)
192 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
193 if (status != IXGBE_SUCCESS)
195 reg &= ~IXGBE_PE_BIT1;
196 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
197 if (status != IXGBE_SUCCESS)
200 usec_delay(IXGBE_CS4227_RESET_HOLD);
202 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
203 if (status != IXGBE_SUCCESS)
205 reg |= IXGBE_PE_BIT1;
206 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
207 if (status != IXGBE_SUCCESS)
210 /* Wait for the reset to complete. */
211 msec_delay(IXGBE_CS4227_RESET_DELAY);
212 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
213 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
215 if (status == IXGBE_SUCCESS &&
216 value == IXGBE_CS4227_EEPROM_LOAD_OK)
218 msec_delay(IXGBE_CS4227_CHECK_DELAY);
220 if (retry == IXGBE_CS4227_RETRIES) {
221 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
222 "CS4227 reset did not complete.");
223 return IXGBE_ERR_PHY;
226 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
227 if (status != IXGBE_SUCCESS ||
228 !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
229 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
230 "CS4227 EEPROM did not load successfully.");
231 return IXGBE_ERR_PHY;
234 return IXGBE_SUCCESS;
238 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
239 * @hw: pointer to hardware structure
241 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
243 s32 status = IXGBE_SUCCESS;
244 u32 swfw_mask = hw->phy.phy_semaphore_mask;
248 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
249 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
250 if (status != IXGBE_SUCCESS) {
251 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
252 "semaphore failed with %d", status);
253 msec_delay(IXGBE_CS4227_CHECK_DELAY);
257 /* Get status of reset flow. */
258 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
260 if (status == IXGBE_SUCCESS &&
261 value == IXGBE_CS4227_RESET_COMPLETE)
264 if (status != IXGBE_SUCCESS ||
265 value != IXGBE_CS4227_RESET_PENDING)
268 /* Reset is pending. Wait and check again. */
269 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
270 msec_delay(IXGBE_CS4227_CHECK_DELAY);
273 /* If still pending, assume other instance failed. */
274 if (retry == IXGBE_CS4227_RETRIES) {
275 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
276 if (status != IXGBE_SUCCESS) {
277 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
278 "semaphore failed with %d", status);
283 /* Reset the CS4227. */
284 status = ixgbe_reset_cs4227(hw);
285 if (status != IXGBE_SUCCESS) {
286 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
287 "CS4227 reset failed: %d", status);
291 /* Reset takes so long, temporarily release semaphore in case the
292 * other driver instance is waiting for the reset indication.
294 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
295 IXGBE_CS4227_RESET_PENDING);
296 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
298 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
299 if (status != IXGBE_SUCCESS) {
300 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
301 "semaphore failed with %d", status);
305 /* Record completion for next time. */
306 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
307 IXGBE_CS4227_RESET_COMPLETE);
310 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
311 msec_delay(hw->eeprom.semaphore_delay);
315 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
316 * @hw: pointer to hardware structure
318 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
320 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
322 if (hw->bus.lan_id) {
323 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
324 esdp |= IXGBE_ESDP_SDP1_DIR;
326 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
327 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
328 IXGBE_WRITE_FLUSH(hw);
332 * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
333 * @hw: pointer to hardware structure
334 * @reg_addr: 32 bit address of PHY register to read
335 * @dev_type: always unused
336 * @phy_data: Pointer to read data from PHY register
338 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
339 u32 dev_type, u16 *phy_data)
341 u32 i, data, command;
342 UNREFERENCED_1PARAMETER(dev_type);
344 /* Setup and write the read command */
345 command = (reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
346 (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
347 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
348 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ |
349 IXGBE_MSCA_MDI_COMMAND;
351 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
353 /* Check every 10 usec to see if the access completed.
354 * The MDI Command bit will clear when the operation is
357 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
360 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
361 if (!(command & IXGBE_MSCA_MDI_COMMAND))
365 if (command & IXGBE_MSCA_MDI_COMMAND) {
366 ERROR_REPORT1(IXGBE_ERROR_POLLING,
367 "PHY read command did not complete.\n");
368 return IXGBE_ERR_PHY;
371 /* Read operation is complete. Get the data from MSRWD */
372 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
373 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
374 *phy_data = (u16)data;
376 return IXGBE_SUCCESS;
380 * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
381 * @hw: pointer to hardware structure
382 * @reg_addr: 32 bit PHY register to write
383 * @dev_type: always unused
384 * @phy_data: Data to write to the PHY register
386 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
387 u32 dev_type, u16 phy_data)
390 UNREFERENCED_1PARAMETER(dev_type);
392 /* Put the data in the MDI single read and write data register*/
393 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
395 /* Setup and write the write command */
396 command = (reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
397 (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
398 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
399 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
400 IXGBE_MSCA_MDI_COMMAND;
402 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
404 /* Check every 10 usec to see if the access completed.
405 * The MDI Command bit will clear when the operation is
408 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
411 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
412 if (!(command & IXGBE_MSCA_MDI_COMMAND))
416 if (command & IXGBE_MSCA_MDI_COMMAND) {
417 ERROR_REPORT1(IXGBE_ERROR_POLLING,
418 "PHY write cmd didn't complete\n");
419 return IXGBE_ERR_PHY;
422 return IXGBE_SUCCESS;
426 * ixgbe_identify_phy_1g - Get 1g PHY type based on device id
427 * @hw: pointer to hardware structure
431 STATIC s32 ixgbe_identify_phy_1g(struct ixgbe_hw *hw)
433 u32 swfw_mask = hw->phy.phy_semaphore_mask;
438 rc = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
442 rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_MDIO_PHY_ID_HIGH, 0,
447 rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_MDIO_PHY_ID_LOW, 0,
452 hw->phy.id = (u32)phy_id_high << 16;
453 hw->phy.id |= phy_id_low & IXGBE_PHY_REVISION_MASK;
454 hw->phy.revision = (u32)phy_id_low & ~IXGBE_PHY_REVISION_MASK;
457 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
463 * ixgbe_identify_phy_x550em - Get PHY type based on device id
464 * @hw: pointer to hardware structure
468 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
470 switch (hw->device_id) {
471 case IXGBE_DEV_ID_X550EM_A_SFP:
472 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
473 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
475 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
477 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
478 return ixgbe_identify_module_generic(hw);
479 case IXGBE_DEV_ID_X550EM_X_SFP:
480 /* set up for CS4227 usage */
481 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
482 ixgbe_setup_mux_ctl(hw);
483 ixgbe_check_cs4227(hw);
486 case IXGBE_DEV_ID_X550EM_A_SFP_N:
487 return ixgbe_identify_module_generic(hw);
489 case IXGBE_DEV_ID_X550EM_X_KX4:
490 hw->phy.type = ixgbe_phy_x550em_kx4;
492 case IXGBE_DEV_ID_X550EM_X_KR:
493 case IXGBE_DEV_ID_X550EM_A_KR:
494 case IXGBE_DEV_ID_X550EM_A_KR_L:
495 hw->phy.type = ixgbe_phy_x550em_kr;
497 case IXGBE_DEV_ID_X550EM_A_10G_T:
498 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
499 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
500 /* Fallthrough to ixgbe_identify_phy_generic */
501 case IXGBE_DEV_ID_X550EM_X_1G_T:
502 case IXGBE_DEV_ID_X550EM_X_10G_T:
503 return ixgbe_identify_phy_generic(hw);
504 case IXGBE_DEV_ID_X550EM_A_1G_T:
505 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
506 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
507 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
509 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
511 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
512 return ixgbe_identify_phy_1g(hw);
516 return IXGBE_SUCCESS;
519 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
520 u32 device_type, u16 *phy_data)
522 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
523 return IXGBE_NOT_IMPLEMENTED;
526 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
527 u32 device_type, u16 phy_data)
529 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
530 return IXGBE_NOT_IMPLEMENTED;
534 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
535 * @hw: pointer to the hardware structure
536 * @addr: I2C bus address to read from
537 * @reg: I2C device register to read from
538 * @val: pointer to location to receive read value
540 * Returns an error code on error.
542 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
545 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
549 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
550 * @hw: pointer to the hardware structure
551 * @addr: I2C bus address to read from
552 * @reg: I2C device register to read from
553 * @val: pointer to location to receive read value
555 * Returns an error code on error.
558 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
561 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
565 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
566 * @hw: pointer to the hardware structure
567 * @addr: I2C bus address to write to
568 * @reg: I2C device register to write to
569 * @val: value to write
571 * Returns an error code on error.
573 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
574 u8 addr, u16 reg, u16 val)
576 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
580 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
581 * @hw: pointer to the hardware structure
582 * @addr: I2C bus address to write to
583 * @reg: I2C device register to write to
584 * @val: value to write
586 * Returns an error code on error.
589 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
590 u8 addr, u16 reg, u16 val)
592 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
596 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
597 * @hw: pointer to hardware structure
599 * Initialize the function pointers and for MAC type X550EM.
600 * Does not touch the hardware.
602 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
604 struct ixgbe_mac_info *mac = &hw->mac;
605 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
606 struct ixgbe_phy_info *phy = &hw->phy;
609 DEBUGFUNC("ixgbe_init_ops_X550EM");
611 /* Similar to X550 so start there. */
612 ret_val = ixgbe_init_ops_X550(hw);
614 /* Since this function eventually calls
615 * ixgbe_init_ops_540 by design, we are setting
616 * the pointers to NULL explicitly here to overwrite
617 * the values being set in the x540 function.
619 /* Thermal sensor not supported in x550EM */
620 mac->ops.get_thermal_sensor_data = NULL;
621 mac->ops.init_thermal_sensor_thresh = NULL;
622 mac->thermal_sensor_enabled = false;
624 /* FCOE not supported in x550EM */
625 mac->ops.get_san_mac_addr = NULL;
626 mac->ops.set_san_mac_addr = NULL;
627 mac->ops.get_wwn_prefix = NULL;
628 mac->ops.get_fcoe_boot_status = NULL;
630 /* IPsec not supported in x550EM */
631 mac->ops.disable_sec_rx_path = NULL;
632 mac->ops.enable_sec_rx_path = NULL;
634 /* AUTOC register is not present in x550EM. */
635 mac->ops.prot_autoc_read = NULL;
636 mac->ops.prot_autoc_write = NULL;
638 /* X550EM bus type is internal*/
639 hw->bus.type = ixgbe_bus_type_internal;
640 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
643 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
644 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
645 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
646 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
647 mac->ops.get_supported_physical_layer =
648 ixgbe_get_supported_physical_layer_X550em;
650 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
651 mac->ops.setup_fc = ixgbe_setup_fc_generic;
653 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
655 switch (hw->device_id) {
656 case IXGBE_DEV_ID_X550EM_X_KR:
657 case IXGBE_DEV_ID_X550EM_A_KR:
658 case IXGBE_DEV_ID_X550EM_A_KR_L:
661 mac->ops.setup_eee = NULL;
665 phy->ops.init = ixgbe_init_phy_ops_X550em;
666 phy->ops.identify = ixgbe_identify_phy_x550em;
667 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
668 phy->ops.set_phy_power = NULL;
672 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
673 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
674 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
675 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
676 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
677 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
678 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
679 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
685 * ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
686 * @hw: pointer to hardware structure
688 * Initialize the function pointers and for MAC type X550EM_a.
689 * Does not touch the hardware.
691 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
693 struct ixgbe_mac_info *mac = &hw->mac;
696 DEBUGFUNC("ixgbe_init_ops_X550EM_a");
698 /* Start with generic X550EM init */
699 ret_val = ixgbe_init_ops_X550EM(hw);
701 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
702 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
703 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
704 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
705 mac->ops.setup_fc = ixgbe_setup_fc_x550a;
706 mac->ops.fc_autoneg = ixgbe_fc_autoneg_x550a;
712 * ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
713 * @hw: pointer to hardware structure
715 * Initialize the function pointers and for MAC type X550EM_x.
716 * Does not touch the hardware.
718 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
720 struct ixgbe_mac_info *mac = &hw->mac;
721 struct ixgbe_link_info *link = &hw->link;
724 DEBUGFUNC("ixgbe_init_ops_X550EM_x");
726 /* Start with generic X550EM init */
727 ret_val = ixgbe_init_ops_X550EM(hw);
729 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
730 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
731 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
732 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
733 link->ops.read_link = ixgbe_read_i2c_combined_generic;
734 link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
735 link->ops.write_link = ixgbe_write_i2c_combined_generic;
736 link->ops.write_link_unlocked =
737 ixgbe_write_i2c_combined_generic_unlocked;
738 link->addr = IXGBE_CS4227;
744 * ixgbe_dmac_config_X550
745 * @hw: pointer to hardware structure
747 * Configure DMA coalescing. If enabling dmac, dmac is activated.
748 * When disabling dmac, dmac enable dmac bit is cleared.
750 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
752 u32 reg, high_pri_tc;
754 DEBUGFUNC("ixgbe_dmac_config_X550");
756 /* Disable DMA coalescing before configuring */
757 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
758 reg &= ~IXGBE_DMACR_DMAC_EN;
759 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
761 /* Disable DMA Coalescing if the watchdog timer is 0 */
762 if (!hw->mac.dmac_config.watchdog_timer)
765 ixgbe_dmac_config_tcs_X550(hw);
767 /* Configure DMA Coalescing Control Register */
768 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
770 /* Set the watchdog timer in units of 40.96 usec */
771 reg &= ~IXGBE_DMACR_DMACWT_MASK;
772 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
774 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
775 /* If fcoe is enabled, set high priority traffic class */
776 if (hw->mac.dmac_config.fcoe_en) {
777 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
778 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
779 IXGBE_DMACR_HIGH_PRI_TC_MASK);
781 reg |= IXGBE_DMACR_EN_MNG_IND;
783 /* Enable DMA coalescing after configuration */
784 reg |= IXGBE_DMACR_DMAC_EN;
785 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
788 return IXGBE_SUCCESS;
792 * ixgbe_dmac_config_tcs_X550
793 * @hw: pointer to hardware structure
795 * Configure DMA coalescing threshold per TC. The dmac enable bit must
796 * be cleared before configuring.
798 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
800 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
802 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
804 /* Configure DMA coalescing enabled */
805 switch (hw->mac.dmac_config.link_speed) {
806 case IXGBE_LINK_SPEED_100_FULL:
807 pb_headroom = IXGBE_DMACRXT_100M;
809 case IXGBE_LINK_SPEED_1GB_FULL:
810 pb_headroom = IXGBE_DMACRXT_1G;
813 pb_headroom = IXGBE_DMACRXT_10G;
817 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
818 IXGBE_MHADD_MFS_SHIFT) / 1024);
820 /* Set the per Rx packet buffer receive threshold */
821 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
822 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
823 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
825 if (tc < hw->mac.dmac_config.num_tcs) {
827 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
828 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
829 IXGBE_RXPBSIZE_SHIFT;
831 /* Calculate receive buffer threshold in kilobytes */
832 if (rx_pb_size > pb_headroom)
833 rx_pb_size = rx_pb_size - pb_headroom;
837 /* Minimum of MFS shall be set for DMCTH */
838 reg |= (rx_pb_size > maxframe_size_kb) ?
839 rx_pb_size : maxframe_size_kb;
841 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
843 return IXGBE_SUCCESS;
847 * ixgbe_dmac_update_tcs_X550
848 * @hw: pointer to hardware structure
850 * Disables dmac, updates per TC settings, and then enables dmac.
852 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
856 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
858 /* Disable DMA coalescing before configuring */
859 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
860 reg &= ~IXGBE_DMACR_DMAC_EN;
861 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
863 ixgbe_dmac_config_tcs_X550(hw);
865 /* Enable DMA coalescing after configuration */
866 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
867 reg |= IXGBE_DMACR_DMAC_EN;
868 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
870 return IXGBE_SUCCESS;
874 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
875 * @hw: pointer to hardware structure
877 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
878 * ixgbe_hw struct in order to set up EEPROM access.
880 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
882 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
886 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
888 if (eeprom->type == ixgbe_eeprom_uninitialized) {
889 eeprom->semaphore_delay = 10;
890 eeprom->type = ixgbe_flash;
892 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
893 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
894 IXGBE_EEC_SIZE_SHIFT);
895 eeprom->word_size = 1 << (eeprom_size +
896 IXGBE_EEPROM_WORD_SIZE_SHIFT);
898 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
899 eeprom->type, eeprom->word_size);
902 return IXGBE_SUCCESS;
906 * ixgbe_enable_eee_x550 - Enable EEE support
907 * @hw: pointer to hardware structure
909 STATIC s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
915 if (hw->mac.type == ixgbe_mac_X550) {
916 /* Advertise EEE capability */
917 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
918 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
921 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
922 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
923 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
925 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
926 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
928 return IXGBE_SUCCESS;
931 switch (hw->device_id) {
932 case IXGBE_DEV_ID_X550EM_X_KR:
933 case IXGBE_DEV_ID_X550EM_A_KR:
934 case IXGBE_DEV_ID_X550EM_A_KR_L:
935 status = hw->mac.ops.read_iosf_sb_reg(hw,
936 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
937 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
938 if (status != IXGBE_SUCCESS)
941 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
942 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
944 /* Don't advertise FEC capability when EEE enabled. */
945 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
947 status = hw->mac.ops.write_iosf_sb_reg(hw,
948 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
949 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
950 if (status != IXGBE_SUCCESS)
957 return IXGBE_SUCCESS;
961 * ixgbe_disable_eee_x550 - Disable EEE support
962 * @hw: pointer to hardware structure
964 STATIC s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
970 if (hw->mac.type == ixgbe_mac_X550) {
971 /* Disable advertised EEE capability */
972 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
973 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
976 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
977 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
978 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
980 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
981 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
983 return IXGBE_SUCCESS;
986 switch (hw->device_id) {
987 case IXGBE_DEV_ID_X550EM_X_KR:
988 case IXGBE_DEV_ID_X550EM_A_KR:
989 case IXGBE_DEV_ID_X550EM_A_KR_L:
990 status = hw->mac.ops.read_iosf_sb_reg(hw,
991 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
992 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
993 if (status != IXGBE_SUCCESS)
996 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
997 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
999 /* Advertise FEC capability when EEE is disabled. */
1000 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
1002 status = hw->mac.ops.write_iosf_sb_reg(hw,
1003 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1004 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
1005 if (status != IXGBE_SUCCESS)
1012 return IXGBE_SUCCESS;
1016 * ixgbe_setup_eee_X550 - Enable/disable EEE support
1017 * @hw: pointer to the HW structure
1018 * @enable_eee: boolean flag to enable EEE
1020 * Enable/disable EEE based on enable_eee flag.
1021 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
1025 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
1030 DEBUGFUNC("ixgbe_setup_eee_X550");
1032 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
1033 /* Enable or disable EEE per flag */
1035 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1037 /* Not supported on first revision of X550EM_x. */
1038 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
1039 !(IXGBE_FUSES0_REV_MASK &
1040 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
1041 return IXGBE_SUCCESS;
1042 status = ixgbe_enable_eee_x550(hw);
1046 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1048 status = ixgbe_disable_eee_x550(hw);
1052 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
1054 return IXGBE_SUCCESS;
1058 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1059 * @hw: pointer to hardware structure
1060 * @enable: enable or disable source address pruning
1061 * @pool: Rx pool to set source address pruning for
1063 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1068 /* max rx pool is 63 */
1072 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1073 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1076 pfflp |= (1ULL << pool);
1078 pfflp &= ~(1ULL << pool);
1080 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1081 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1085 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1086 * @hw: pointer to hardware structure
1087 * @enable: enable or disable switch for Ethertype anti-spoofing
1088 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1091 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1092 bool enable, int vf)
1094 int vf_target_reg = vf >> 3;
1095 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1098 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1100 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1102 pfvfspoof |= (1 << vf_target_shift);
1104 pfvfspoof &= ~(1 << vf_target_shift);
1106 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1110 * ixgbe_iosf_wait - Wait for IOSF command completion
1111 * @hw: pointer to hardware structure
1112 * @ctrl: pointer to location to receive final IOSF control value
1114 * Returns failing status on timeout
1116 * Note: ctrl can be NULL if the IOSF control register value is not needed
1118 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1122 /* Check every 10 usec to see if the address cycle completed.
1123 * The SB IOSF BUSY bit will clear when the operation is
1126 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1127 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1128 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1134 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1135 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1136 return IXGBE_ERR_PHY;
1139 return IXGBE_SUCCESS;
1143 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
1145 * @hw: pointer to hardware structure
1146 * @reg_addr: 32 bit PHY register to write
1147 * @device_type: 3 bit device type
1148 * @data: Data to write to the register
1150 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1151 u32 device_type, u32 data)
1153 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1157 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1158 if (ret != IXGBE_SUCCESS)
1161 ret = ixgbe_iosf_wait(hw, NULL);
1162 if (ret != IXGBE_SUCCESS)
1165 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1166 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1168 /* Write IOSF control register */
1169 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1171 /* Write IOSF data register */
1172 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1174 ret = ixgbe_iosf_wait(hw, &command);
1176 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1177 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1178 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1179 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1180 "Failed to write, error %x\n", error);
1181 ret = IXGBE_ERR_PHY;
1185 ixgbe_release_swfw_semaphore(hw, gssr);
1190 * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
1192 * @hw: pointer to hardware structure
1193 * @reg_addr: 32 bit PHY register to write
1194 * @device_type: 3 bit device type
1195 * @phy_data: Pointer to read data from the register
1197 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1198 u32 device_type, u32 *data)
1200 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1204 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1205 if (ret != IXGBE_SUCCESS)
1208 ret = ixgbe_iosf_wait(hw, NULL);
1209 if (ret != IXGBE_SUCCESS)
1212 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1213 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1215 /* Write IOSF control register */
1216 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1218 ret = ixgbe_iosf_wait(hw, &command);
1220 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1221 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1222 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1223 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1224 "Failed to read, error %x\n", error);
1225 ret = IXGBE_ERR_PHY;
1228 if (ret == IXGBE_SUCCESS)
1229 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1232 ixgbe_release_swfw_semaphore(hw, gssr);
1237 * ixgbe_get_phy_token - Get the token for shared phy access
1238 * @hw: Pointer to hardware structure
1241 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1243 struct ixgbe_hic_phy_token_req token_cmd;
1246 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1247 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1248 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1249 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1250 token_cmd.port_number = hw->bus.lan_id;
1251 token_cmd.command_type = FW_PHY_TOKEN_REQ;
1253 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1255 IXGBE_HI_COMMAND_TIMEOUT,
1259 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1260 return IXGBE_SUCCESS;
1261 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1262 return IXGBE_ERR_FW_RESP_INVALID;
1264 return IXGBE_ERR_TOKEN_RETRY;
1268 * ixgbe_put_phy_token - Put the token for shared phy access
1269 * @hw: Pointer to hardware structure
1272 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1274 struct ixgbe_hic_phy_token_req token_cmd;
1277 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1278 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1279 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1280 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1281 token_cmd.port_number = hw->bus.lan_id;
1282 token_cmd.command_type = FW_PHY_TOKEN_REL;
1284 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1286 IXGBE_HI_COMMAND_TIMEOUT,
1290 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1291 return IXGBE_SUCCESS;
1293 DEBUGOUT("Put PHY Token host interface command failed");
1294 return IXGBE_ERR_FW_RESP_INVALID;
1298 * ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1299 * of the IOSF device
1300 * @hw: pointer to hardware structure
1301 * @reg_addr: 32 bit PHY register to write
1302 * @device_type: 3 bit device type
1303 * @data: Data to write to the register
1305 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1306 u32 device_type, u32 data)
1308 struct ixgbe_hic_internal_phy_req write_cmd;
1310 UNREFERENCED_1PARAMETER(device_type);
1312 memset(&write_cmd, 0, sizeof(write_cmd));
1313 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1314 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1315 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1316 write_cmd.port_number = hw->bus.lan_id;
1317 write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1318 write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1319 write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1321 status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1323 IXGBE_HI_COMMAND_TIMEOUT, false);
1329 * ixgbe_read_iosf_sb_reg_x550a - Writes a value to specified register
1330 * of the IOSF device.
1331 * @hw: pointer to hardware structure
1332 * @reg_addr: 32 bit PHY register to write
1333 * @device_type: 3 bit device type
1334 * @data: Pointer to read data from the register
1336 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1337 u32 device_type, u32 *data)
1340 struct ixgbe_hic_internal_phy_req cmd;
1341 struct ixgbe_hic_internal_phy_resp rsp;
1344 UNREFERENCED_1PARAMETER(device_type);
1346 memset(&hic, 0, sizeof(hic));
1347 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1348 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1349 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1350 hic.cmd.port_number = hw->bus.lan_id;
1351 hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1352 hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1354 status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1356 IXGBE_HI_COMMAND_TIMEOUT, true);
1358 /* Extract the register value from the response. */
1359 *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1365 * ixgbe_disable_mdd_X550
1366 * @hw: pointer to hardware structure
1368 * Disable malicious driver detection
1370 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1374 DEBUGFUNC("ixgbe_disable_mdd_X550");
1376 /* Disable MDD for TX DMA and interrupt */
1377 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1378 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1379 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1381 /* Disable MDD for RX and interrupt */
1382 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1383 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1384 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1388 * ixgbe_enable_mdd_X550
1389 * @hw: pointer to hardware structure
1391 * Enable malicious driver detection
1393 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1397 DEBUGFUNC("ixgbe_enable_mdd_X550");
1399 /* Enable MDD for TX DMA and interrupt */
1400 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1401 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1402 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1404 /* Enable MDD for RX and interrupt */
1405 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1406 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1407 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1411 * ixgbe_restore_mdd_vf_X550
1412 * @hw: pointer to hardware structure
1415 * Restore VF that was disabled during malicious driver detection event
1417 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1419 u32 idx, reg, num_qs, start_q, bitmask;
1421 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1423 /* Map VF to queues */
1424 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1425 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1426 case IXGBE_MRQC_VMDQRT8TCEN:
1427 num_qs = 8; /* 16 VFs / pools */
1428 bitmask = 0x000000FF;
1430 case IXGBE_MRQC_VMDQRSS32EN:
1431 case IXGBE_MRQC_VMDQRT4TCEN:
1432 num_qs = 4; /* 32 VFs / pools */
1433 bitmask = 0x0000000F;
1435 default: /* 64 VFs / pools */
1437 bitmask = 0x00000003;
1440 start_q = vf * num_qs;
1442 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1445 reg |= (bitmask << (start_q % 32));
1446 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1447 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1451 * ixgbe_mdd_event_X550
1452 * @hw: pointer to hardware structure
1453 * @vf_bitmap: vf bitmap of malicious vfs
1455 * Handle malicious driver detection event.
1457 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1460 u32 i, j, reg, q, shift, vf, idx;
1462 DEBUGFUNC("ixgbe_mdd_event_X550");
1464 /* figure out pool size for mapping to vf's */
1465 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1466 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1467 case IXGBE_MRQC_VMDQRT8TCEN:
1468 shift = 3; /* 16 VFs / pools */
1470 case IXGBE_MRQC_VMDQRSS32EN:
1471 case IXGBE_MRQC_VMDQRT4TCEN:
1472 shift = 2; /* 32 VFs / pools */
1475 shift = 1; /* 64 VFs / pools */
1479 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1480 for (i = 0; i < 4; i++) {
1481 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1482 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1487 /* Get malicious queue */
1488 for (j = 0; j < 32 && wqbr; j++) {
1490 if (!(wqbr & (1 << j)))
1493 /* Get queue from bitmask */
1496 /* Map queue to vf */
1499 /* Set vf bit in vf_bitmap */
1501 vf_bitmap[idx] |= (1 << (vf % 32));
1508 * ixgbe_get_media_type_X550em - Get media type
1509 * @hw: pointer to hardware structure
1511 * Returns the media type (fiber, copper, backplane)
1513 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1515 enum ixgbe_media_type media_type;
1517 DEBUGFUNC("ixgbe_get_media_type_X550em");
1519 /* Detect if there is a copper PHY attached. */
1520 switch (hw->device_id) {
1521 case IXGBE_DEV_ID_X550EM_X_KR:
1522 case IXGBE_DEV_ID_X550EM_X_KX4:
1523 case IXGBE_DEV_ID_X550EM_A_KR:
1524 case IXGBE_DEV_ID_X550EM_A_KR_L:
1525 media_type = ixgbe_media_type_backplane;
1527 case IXGBE_DEV_ID_X550EM_X_SFP:
1528 case IXGBE_DEV_ID_X550EM_A_SFP:
1529 case IXGBE_DEV_ID_X550EM_A_SFP_N:
1530 case IXGBE_DEV_ID_X550EM_A_QSFP:
1531 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1532 media_type = ixgbe_media_type_fiber;
1534 case IXGBE_DEV_ID_X550EM_X_1G_T:
1535 case IXGBE_DEV_ID_X550EM_X_10G_T:
1536 case IXGBE_DEV_ID_X550EM_A_10G_T:
1537 media_type = ixgbe_media_type_copper;
1539 case IXGBE_DEV_ID_X550EM_A_SGMII:
1540 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1541 media_type = ixgbe_media_type_backplane;
1542 hw->phy.type = ixgbe_phy_sgmii;
1544 case IXGBE_DEV_ID_X550EM_A_1G_T:
1545 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1546 media_type = ixgbe_media_type_copper;
1547 hw->phy.type = ixgbe_phy_m88;
1550 media_type = ixgbe_media_type_unknown;
1557 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1558 * @hw: pointer to hardware structure
1559 * @linear: true if SFP module is linear
1561 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1563 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1565 switch (hw->phy.sfp_type) {
1566 case ixgbe_sfp_type_not_present:
1567 return IXGBE_ERR_SFP_NOT_PRESENT;
1568 case ixgbe_sfp_type_da_cu_core0:
1569 case ixgbe_sfp_type_da_cu_core1:
1572 case ixgbe_sfp_type_srlr_core0:
1573 case ixgbe_sfp_type_srlr_core1:
1574 case ixgbe_sfp_type_da_act_lmt_core0:
1575 case ixgbe_sfp_type_da_act_lmt_core1:
1576 case ixgbe_sfp_type_1g_sx_core0:
1577 case ixgbe_sfp_type_1g_sx_core1:
1578 case ixgbe_sfp_type_1g_lx_core0:
1579 case ixgbe_sfp_type_1g_lx_core1:
1582 case ixgbe_sfp_type_unknown:
1583 case ixgbe_sfp_type_1g_cu_core0:
1584 case ixgbe_sfp_type_1g_cu_core1:
1586 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1589 return IXGBE_SUCCESS;
1593 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1594 * @hw: pointer to hardware structure
1596 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1598 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1603 DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1605 status = ixgbe_identify_module_generic(hw);
1607 if (status != IXGBE_SUCCESS)
1610 /* Check if SFP module is supported */
1611 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1617 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1618 * @hw: pointer to hardware structure
1620 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1625 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1627 /* Check if SFP module is supported */
1628 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1630 if (status != IXGBE_SUCCESS)
1633 ixgbe_init_mac_link_ops_X550em(hw);
1634 hw->phy.ops.reset = NULL;
1636 return IXGBE_SUCCESS;
1640 * ixgbe_setup_sgmii - Set up link for sgmii
1641 * @hw: pointer to hardware structure
1643 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1644 bool autoneg_wait_to_complete)
1646 struct ixgbe_mac_info *mac = &hw->mac;
1649 UNREFERENCED_2PARAMETER(speed, autoneg_wait_to_complete);
1651 rc = mac->ops.read_iosf_sb_reg(hw,
1652 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1653 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1657 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1658 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1659 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1660 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1661 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1662 rc = mac->ops.write_iosf_sb_reg(hw,
1663 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1664 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1668 rc = mac->ops.read_iosf_sb_reg(hw,
1669 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1670 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1674 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1675 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1676 rc = mac->ops.write_iosf_sb_reg(hw,
1677 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1678 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1682 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1683 rc = mac->ops.write_iosf_sb_reg(hw,
1684 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1685 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1691 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1692 * @hw: pointer to hardware structure
1694 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1696 struct ixgbe_mac_info *mac = &hw->mac;
1698 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1700 switch (hw->mac.ops.get_media_type(hw)) {
1701 case ixgbe_media_type_fiber:
1702 /* CS4227 does not support autoneg, so disable the laser control
1703 * functions for SFP+ fiber
1705 mac->ops.disable_tx_laser = NULL;
1706 mac->ops.enable_tx_laser = NULL;
1707 mac->ops.flap_tx_laser = NULL;
1708 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1709 mac->ops.set_rate_select_speed =
1710 ixgbe_set_soft_rate_select_speed;
1711 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1712 (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1713 mac->ops.setup_mac_link =
1714 ixgbe_setup_mac_link_sfp_x550a;
1716 mac->ops.setup_mac_link =
1717 ixgbe_setup_mac_link_sfp_x550em;
1719 case ixgbe_media_type_copper:
1720 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1721 mac->ops.check_link = ixgbe_check_link_t_X550em;
1723 case ixgbe_media_type_backplane:
1724 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1725 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1726 mac->ops.setup_link = ixgbe_setup_sgmii;
1734 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1735 * @hw: pointer to hardware structure
1736 * @speed: pointer to link speed
1737 * @autoneg: true when autoneg or autotry is enabled
1739 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1740 ixgbe_link_speed *speed,
1743 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1746 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1748 /* CS4227 SFP must not enable auto-negotiation */
1751 /* Check if 1G SFP module. */
1752 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1753 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1754 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1755 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1756 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1757 return IXGBE_SUCCESS;
1760 /* Link capabilities are based on SFP */
1761 if (hw->phy.multispeed_fiber)
1762 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1763 IXGBE_LINK_SPEED_1GB_FULL;
1765 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1767 switch (hw->phy.type) {
1769 *speed = IXGBE_LINK_SPEED_100_FULL |
1770 IXGBE_LINK_SPEED_1GB_FULL;
1772 case ixgbe_phy_sgmii:
1773 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1776 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1777 IXGBE_LINK_SPEED_1GB_FULL;
1783 return IXGBE_SUCCESS;
1787 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1788 * @hw: pointer to hardware structure
1789 * @lsc: pointer to boolean flag which indicates whether external Base T
1790 * PHY interrupt is lsc
1792 * Determime if external Base T PHY interrupt cause is high temperature
1793 * failure alarm or link status change.
1795 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1796 * failure alarm, else return PHY access status.
1798 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1805 /* Vendor alarm triggered */
1806 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1807 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1810 if (status != IXGBE_SUCCESS ||
1811 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1814 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1815 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1816 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1819 if (status != IXGBE_SUCCESS ||
1820 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1821 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1824 /* Global alarm triggered */
1825 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1826 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1829 if (status != IXGBE_SUCCESS)
1832 /* If high temperature failure, then return over temp error and exit */
1833 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1834 /* power down the PHY in case the PHY FW didn't already */
1835 ixgbe_set_copper_phy_power(hw, false);
1836 return IXGBE_ERR_OVERTEMP;
1837 } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1838 /* device fault alarm triggered */
1839 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1840 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1843 if (status != IXGBE_SUCCESS)
1846 /* if device fault was due to high temp alarm handle and exit */
1847 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1848 /* power down the PHY in case the PHY FW didn't */
1849 ixgbe_set_copper_phy_power(hw, false);
1850 return IXGBE_ERR_OVERTEMP;
1854 /* Vendor alarm 2 triggered */
1855 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1856 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1858 if (status != IXGBE_SUCCESS ||
1859 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1862 /* link connect/disconnect event occurred */
1863 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1864 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1866 if (status != IXGBE_SUCCESS)
1870 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1873 return IXGBE_SUCCESS;
1877 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1878 * @hw: pointer to hardware structure
1880 * Enable link status change and temperature failure alarm for the external
1883 * Returns PHY access status
1885 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1891 /* Clear interrupt flags */
1892 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1894 /* Enable link status change alarm */
1895 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1896 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1898 if (status != IXGBE_SUCCESS)
1901 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1903 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1904 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1906 if (status != IXGBE_SUCCESS)
1909 /* Enable high temperature failure and global fault alarms */
1910 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1911 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1914 if (status != IXGBE_SUCCESS)
1917 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
1918 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
1920 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1921 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1924 if (status != IXGBE_SUCCESS)
1927 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1928 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1929 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1932 if (status != IXGBE_SUCCESS)
1935 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1936 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1938 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1939 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1942 if (status != IXGBE_SUCCESS)
1945 /* Enable chip-wide vendor alarm */
1946 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1947 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1950 if (status != IXGBE_SUCCESS)
1953 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1955 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1956 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1963 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1964 * @hw: pointer to hardware structure
1965 * @speed: link speed
1967 * Configures the integrated KR PHY.
1969 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1970 ixgbe_link_speed speed)
1975 status = hw->mac.ops.read_iosf_sb_reg(hw,
1976 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1977 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1981 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1982 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1983 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1985 /* Advertise 10G support. */
1986 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1987 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1989 /* Advertise 1G support. */
1990 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1991 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1993 /* Restart auto-negotiation. */
1994 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1995 status = hw->mac.ops.write_iosf_sb_reg(hw,
1996 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1997 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2003 * ixgbe_set_master_slave_mode - Set up PHY for master/slave mode
2004 * @hw: pointer to hardware structure
2006 * Must be called while holding the PHY semaphore and token
2008 STATIC s32 ixgbe_set_master_slave_mode(struct ixgbe_hw *hw)
2013 /* Resolve master/slave mode */
2014 rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_M88E1500_1000T_CTRL, 0,
2019 /* load defaults for future use */
2020 if (phy_data & IXGBE_M88E1500_1000T_CTRL_MS_ENABLE) {
2021 if (phy_data & IXGBE_M88E1500_1000T_CTRL_MS_VALUE)
2022 hw->phy.original_ms_type = ixgbe_ms_force_master;
2024 hw->phy.original_ms_type = ixgbe_ms_force_slave;
2026 hw->phy.original_ms_type = ixgbe_ms_auto;
2029 switch (hw->phy.ms_type) {
2030 case ixgbe_ms_force_master:
2031 phy_data |= IXGBE_M88E1500_1000T_CTRL_MS_ENABLE;
2032 phy_data |= IXGBE_M88E1500_1000T_CTRL_MS_VALUE;
2034 case ixgbe_ms_force_slave:
2035 phy_data |= IXGBE_M88E1500_1000T_CTRL_MS_ENABLE;
2036 phy_data &= ~IXGBE_M88E1500_1000T_CTRL_MS_VALUE;
2039 phy_data &= ~IXGBE_M88E1500_1000T_CTRL_MS_ENABLE;
2045 return ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_1000T_CTRL, 0,
2050 * ixgbe_reset_phy_m88_nolock - Reset m88 PHY without locking
2051 * @hw: pointer to hardware structure
2053 * Must be called while holding the PHY semaphore and token
2055 STATIC s32 ixgbe_reset_phy_m88_nolock(struct ixgbe_hw *hw)
2059 rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2063 rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_FIBER_CTRL, 0,
2064 IXGBE_M88E1500_FIBER_CTRL_RESET |
2065 IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2066 IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB);
2070 rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 18);
2074 rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_GEN_CTRL, 0,
2075 IXGBE_M88E1500_GEN_CTRL_RESET |
2076 IXGBE_M88E1500_GEN_CTRL_SGMII_COPPER);
2080 rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2084 rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2085 IXGBE_M88E1500_COPPER_CTRL_RESET |
2086 IXGBE_M88E1500_COPPER_CTRL_AN_EN |
2087 IXGBE_M88E1500_COPPER_CTRL_RESTART_AN |
2088 IXGBE_M88E1500_COPPER_CTRL_FULL_DUPLEX |
2089 IXGBE_M88E1500_COPPER_CTRL_SPEED_MSB);
2092 ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2097 * ixgbe_reset_phy_m88 - Reset m88 PHY
2098 * @hw: pointer to hardware structure
2100 STATIC s32 ixgbe_reset_phy_m88(struct ixgbe_hw *hw)
2102 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2105 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2106 return IXGBE_SUCCESS;
2108 rc = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
2112 rc = ixgbe_reset_phy_m88_nolock(hw);
2114 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2119 * ixgbe_setup_m88 - setup m88 PHY
2120 * @hw: pointer to hardware structure
2122 STATIC s32 ixgbe_setup_m88(struct ixgbe_hw *hw)
2124 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2125 struct ixgbe_phy_info *phy = &hw->phy;
2129 if (phy->reset_disable || ixgbe_check_reset_blocked(hw))
2130 return IXGBE_SUCCESS;
2132 rc = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
2136 rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_M88E1500_PHY_SPEC_CTRL, 0,
2141 /* Enable downshift and setting it to X6 */
2142 phy_data &= ~IXGBE_M88E1500_PSCR_DOWNSHIFT_ENABLE;
2143 phy_data |= IXGBE_M88E1500_PSCR_DOWNSHIFT_6X;
2144 phy_data |= IXGBE_M88E1500_PSCR_DOWNSHIFT_ENABLE;
2145 rc = ixgbe_write_phy_reg_mdi_22(hw,
2146 IXGBE_M88E1500_PHY_SPEC_CTRL, 0,
2151 ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2153 /* Commit the changes */
2154 rc = ixgbe_reset_phy_m88_nolock(hw);
2156 DEBUGOUT("Error committing the PHY changes\n");
2160 rc = ixgbe_set_master_slave_mode(hw);
2162 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2166 ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2167 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2172 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2173 * @hw: pointer to hardware structure
2175 * Read NW_MNG_IF_SEL register and save field values, and check for valid field
2178 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2180 /* Save NW management interface connected on board. This is used
2181 * to determine internal PHY mode.
2183 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2185 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2186 * PHY address. This register field was has only been used for X552.
2188 if (hw->mac.type == ixgbe_mac_X550EM_a &&
2189 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2190 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2191 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2192 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2195 return IXGBE_SUCCESS;
2199 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2200 * @hw: pointer to hardware structure
2202 * Initialize any function pointers that were not able to be
2203 * set during init_shared_code because the PHY/SFP type was
2204 * not known. Perform the SFP init if necessary.
2206 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2208 struct ixgbe_phy_info *phy = &hw->phy;
2211 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2213 hw->mac.ops.set_lan_id(hw);
2215 ixgbe_read_mng_if_sel_x550em(hw);
2217 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2218 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2219 ixgbe_setup_mux_ctl(hw);
2220 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2223 /* Identify the PHY or SFP module */
2224 ret_val = phy->ops.identify(hw);
2225 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
2228 /* Setup function pointers based on detected hardware */
2229 ixgbe_init_mac_link_ops_X550em(hw);
2230 if (phy->sfp_type != ixgbe_sfp_type_unknown)
2231 phy->ops.reset = NULL;
2233 /* Set functions pointers based on phy type */
2234 switch (hw->phy.type) {
2235 case ixgbe_phy_x550em_kx4:
2236 phy->ops.setup_link = NULL;
2237 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2238 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2240 case ixgbe_phy_x550em_kr:
2241 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2242 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2243 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2245 case ixgbe_phy_x550em_ext_t:
2246 /* If internal link mode is XFI, then setup iXFI internal link,
2247 * else setup KR now.
2249 phy->ops.setup_internal_link =
2250 ixgbe_setup_internal_phy_t_x550em;
2252 /* setup SW LPLU only for first revision of X550EM_x */
2253 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2254 !(IXGBE_FUSES0_REV_MASK &
2255 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2256 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2258 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2259 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2261 case ixgbe_phy_sgmii:
2262 phy->ops.setup_link = NULL;
2265 phy->ops.setup_link = ixgbe_setup_m88;
2266 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2267 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2268 phy->ops.reset = ixgbe_reset_phy_m88;
2277 * ixgbe_set_mdio_speed - Set MDIO clock speed
2278 * @hw: pointer to hardware structure
2280 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2284 switch (hw->device_id) {
2285 case IXGBE_DEV_ID_X550EM_X_10G_T:
2286 case IXGBE_DEV_ID_X550EM_A_SGMII:
2287 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2288 case IXGBE_DEV_ID_X550EM_A_1G_T:
2289 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2290 case IXGBE_DEV_ID_X550EM_A_10G_T:
2291 case IXGBE_DEV_ID_X550EM_A_SFP:
2292 case IXGBE_DEV_ID_X550EM_A_QSFP:
2293 /* Config MDIO clock speed before the first MDIO PHY access */
2294 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2295 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2296 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2304 * ixgbe_reset_hw_X550em - Perform hardware reset
2305 * @hw: pointer to hardware structure
2307 * Resets the hardware by resetting the transmit and receive units, masks
2308 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2311 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2313 ixgbe_link_speed link_speed;
2317 bool link_up = false;
2319 DEBUGFUNC("ixgbe_reset_hw_X550em");
2321 /* Call adapter stop to disable Tx/Rx and clear interrupts */
2322 status = hw->mac.ops.stop_adapter(hw);
2323 if (status != IXGBE_SUCCESS)
2326 /* flush pending Tx transactions */
2327 ixgbe_clear_tx_pending(hw);
2329 ixgbe_set_mdio_speed(hw);
2331 /* PHY ops must be identified and initialized prior to reset */
2332 status = hw->phy.ops.init(hw);
2334 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2337 /* start the external PHY */
2338 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2339 status = ixgbe_init_ext_t_x550em(hw);
2344 /* Setup SFP module if there is one present. */
2345 if (hw->phy.sfp_setup_needed) {
2346 status = hw->mac.ops.setup_sfp(hw);
2347 hw->phy.sfp_setup_needed = false;
2350 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2354 if (!hw->phy.reset_disable && hw->phy.ops.reset)
2355 hw->phy.ops.reset(hw);
2358 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
2359 * If link reset is used when link is up, it might reset the PHY when
2360 * mng is using it. If link is down or the flag to force full link
2361 * reset is set, then perform link reset.
2363 ctrl = IXGBE_CTRL_LNK_RST;
2364 if (!hw->force_full_reset) {
2365 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2367 ctrl = IXGBE_CTRL_RST;
2370 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2371 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2372 IXGBE_WRITE_FLUSH(hw);
2374 /* Poll for reset bit to self-clear meaning reset is complete */
2375 for (i = 0; i < 10; i++) {
2377 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2378 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2382 if (ctrl & IXGBE_CTRL_RST_MASK) {
2383 status = IXGBE_ERR_RESET_FAILED;
2384 DEBUGOUT("Reset polling failed to complete.\n");
2389 /* Double resets are required for recovery from certain error
2390 * conditions. Between resets, it is necessary to stall to
2391 * allow time for any pending HW events to complete.
2393 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2394 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2398 /* Store the permanent mac address */
2399 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2401 /* Store MAC address from RAR0, clear receive address registers, and
2402 * clear the multicast table. Also reset num_rar_entries to 128,
2403 * since we modify this value when programming the SAN MAC address.
2405 hw->mac.num_rar_entries = 128;
2406 hw->mac.ops.init_rx_addrs(hw);
2408 ixgbe_set_mdio_speed(hw);
2410 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2411 ixgbe_setup_mux_ctl(hw);
2417 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2418 * @hw: pointer to hardware structure
2420 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2425 status = hw->phy.ops.read_reg(hw,
2426 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2427 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2430 if (status != IXGBE_SUCCESS)
2433 /* If PHY FW reset completed bit is set then this is the first
2434 * SW instance after a power on so the PHY FW must be un-stalled.
2436 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2437 status = hw->phy.ops.read_reg(hw,
2438 IXGBE_MDIO_GLOBAL_RES_PR_10,
2439 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2442 if (status != IXGBE_SUCCESS)
2445 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2447 status = hw->phy.ops.write_reg(hw,
2448 IXGBE_MDIO_GLOBAL_RES_PR_10,
2449 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2452 if (status != IXGBE_SUCCESS)
2460 * ixgbe_setup_kr_x550em - Configure the KR PHY.
2461 * @hw: pointer to hardware structure
2463 * Configures the integrated KR PHY for X550EM_x.
2465 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2467 if (hw->mac.type != ixgbe_mac_X550EM_x)
2468 return IXGBE_SUCCESS;
2470 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2474 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2475 * @hw: pointer to hardware structure
2477 * Configure the external PHY and the integrated KR PHY for SFP support.
2479 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2480 ixgbe_link_speed speed,
2481 bool autoneg_wait_to_complete)
2484 u16 reg_slice, reg_val;
2485 bool setup_linear = false;
2486 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2488 /* Check if SFP module is supported and linear */
2489 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2491 /* If no SFP module present, then return success. Return success since
2492 * there is no reason to configure CS4227 and SFP not present error is
2493 * not excepted in the setup MAC link flow.
2495 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2496 return IXGBE_SUCCESS;
2498 if (ret_val != IXGBE_SUCCESS)
2501 /* Configure internal PHY for KR/KX. */
2502 ixgbe_setup_kr_speed_x550em(hw, speed);
2504 /* Configure CS4227 LINE side to proper mode. */
2505 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2506 (hw->bus.lan_id << 12);
2508 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2510 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2511 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2517 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2518 * @hw: pointer to hardware structure
2520 * Configure the the integrated PHY for SFP support.
2522 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2523 ixgbe_link_speed speed,
2524 bool autoneg_wait_to_complete)
2528 bool setup_linear = false;
2529 u32 reg_slice, reg_phy_int, slice_offset;
2531 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2533 /* Check if SFP module is supported and linear */
2534 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2536 /* If no SFP module present, then return success. Return success since
2537 * SFP not present error is not excepted in the setup MAC link flow.
2539 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2540 return IXGBE_SUCCESS;
2542 if (ret_val != IXGBE_SUCCESS)
2545 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2546 /* Configure internal PHY for native SFI */
2547 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2548 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2549 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int);
2551 if (ret_val != IXGBE_SUCCESS)
2555 reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LIMITING;
2556 reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LINEAR;
2558 reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LIMITING;
2559 reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LINEAR;
2562 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2563 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2564 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2566 if (ret_val != IXGBE_SUCCESS)
2569 /* Setup XFI/SFI internal link. */
2570 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2572 /* Configure internal PHY for KR/KX. */
2573 ixgbe_setup_kr_speed_x550em(hw, speed);
2575 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2577 DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2578 return IXGBE_ERR_PHY_ADDR_INVALID;
2581 /* Get external PHY device id */
2582 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_GLOBAL_ID_MSB,
2583 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
2585 if (ret_val != IXGBE_SUCCESS)
2588 /* When configuring quad port CS4223, the MAC instance is part
2589 * of the slice offset.
2591 if (reg_phy_ext == IXGBE_CS4223_PHY_ID)
2592 slice_offset = (hw->bus.lan_id +
2593 (hw->bus.instance_id << 1)) << 12;
2595 slice_offset = hw->bus.lan_id << 12;
2597 /* Configure CS4227/CS4223 LINE side to proper mode. */
2598 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2600 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2602 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2603 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2604 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2610 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2611 * @hw: pointer to hardware structure
2613 * iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2615 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2620 /* Disable training protocol FSM. */
2621 status = ixgbe_read_iosf_sb_reg_x550(hw,
2622 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2623 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2624 if (status != IXGBE_SUCCESS)
2626 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2627 status = ixgbe_write_iosf_sb_reg_x550(hw,
2628 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2629 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2630 if (status != IXGBE_SUCCESS)
2633 /* Disable Flex from training TXFFE. */
2634 status = ixgbe_read_iosf_sb_reg_x550(hw,
2635 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2636 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2637 if (status != IXGBE_SUCCESS)
2639 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2640 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2641 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2642 status = ixgbe_write_iosf_sb_reg_x550(hw,
2643 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2644 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2645 if (status != IXGBE_SUCCESS)
2647 status = ixgbe_read_iosf_sb_reg_x550(hw,
2648 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2649 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2650 if (status != IXGBE_SUCCESS)
2652 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2653 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2654 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2655 status = ixgbe_write_iosf_sb_reg_x550(hw,
2656 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2657 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2658 if (status != IXGBE_SUCCESS)
2661 /* Enable override for coefficients. */
2662 status = ixgbe_read_iosf_sb_reg_x550(hw,
2663 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2664 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2665 if (status != IXGBE_SUCCESS)
2667 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2668 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2669 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2670 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2671 status = ixgbe_write_iosf_sb_reg_x550(hw,
2672 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2673 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2678 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2679 * @hw: pointer to hardware structure
2680 * @speed: the link speed to force
2682 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
2683 * internal and external PHY at a specific speed, without autonegotiation.
2685 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2690 /* Disable AN and force speed to 10G Serial. */
2691 status = ixgbe_read_iosf_sb_reg_x550(hw,
2692 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2693 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2694 if (status != IXGBE_SUCCESS)
2697 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2698 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2700 /* Select forced link speed for internal PHY. */
2702 case IXGBE_LINK_SPEED_10GB_FULL:
2703 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2705 case IXGBE_LINK_SPEED_1GB_FULL:
2706 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2709 /* Other link speeds are not supported by internal KR PHY. */
2710 return IXGBE_ERR_LINK_SETUP;
2713 status = ixgbe_write_iosf_sb_reg_x550(hw,
2714 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2715 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2716 if (status != IXGBE_SUCCESS)
2719 /* Additional configuration needed for x550em_x */
2720 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2721 status = ixgbe_setup_ixfi_x550em_x(hw);
2722 if (status != IXGBE_SUCCESS)
2726 /* Toggle port SW reset by AN reset. */
2727 status = ixgbe_read_iosf_sb_reg_x550(hw,
2728 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2729 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2730 if (status != IXGBE_SUCCESS)
2732 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2733 status = ixgbe_write_iosf_sb_reg_x550(hw,
2734 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2735 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2741 * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2742 * @hw: address of hardware structure
2743 * @link_up: address of boolean to indicate link status
2745 * Returns error code if unable to get link status.
2747 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2754 /* read this twice back to back to indicate current status */
2755 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2756 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2758 if (ret != IXGBE_SUCCESS)
2761 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2762 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2764 if (ret != IXGBE_SUCCESS)
2767 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2769 return IXGBE_SUCCESS;
2773 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2774 * @hw: point to hardware structure
2776 * Configures the link between the integrated KR PHY and the external X557 PHY
2777 * The driver will call this function when it gets a link status change
2778 * interrupt from the X557 PHY. This function configures the link speed
2779 * between the PHYs to match the link speed of the BASE-T link.
2781 * A return of a non-zero value indicates an error, and the base driver should
2782 * not report link up.
2784 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2786 ixgbe_link_speed force_speed;
2791 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2792 return IXGBE_ERR_CONFIG;
2794 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2795 /* If link is down, there is no setup necessary so return */
2796 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2797 if (status != IXGBE_SUCCESS)
2801 return IXGBE_SUCCESS;
2803 status = hw->phy.ops.read_reg(hw,
2804 IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2805 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2807 if (status != IXGBE_SUCCESS)
2810 /* If link is still down - no setup is required so return */
2811 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2812 if (status != IXGBE_SUCCESS)
2815 return IXGBE_SUCCESS;
2817 /* clear everything but the speed and duplex bits */
2818 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2821 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2822 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2824 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2825 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2828 /* Internal PHY does not support anything else */
2829 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2832 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2834 speed = IXGBE_LINK_SPEED_10GB_FULL |
2835 IXGBE_LINK_SPEED_1GB_FULL;
2836 return ixgbe_setup_kr_speed_x550em(hw, speed);
2841 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
2842 * @hw: pointer to hardware structure
2844 * Configures the integrated KR PHY to use internal loopback mode.
2846 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
2851 /* Disable AN and force speed to 10G Serial. */
2852 status = hw->mac.ops.read_iosf_sb_reg(hw,
2853 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2854 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2855 if (status != IXGBE_SUCCESS)
2857 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2858 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2859 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2860 status = hw->mac.ops.write_iosf_sb_reg(hw,
2861 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2862 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2863 if (status != IXGBE_SUCCESS)
2866 /* Set near-end loopback clocks. */
2867 status = hw->mac.ops.read_iosf_sb_reg(hw,
2868 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2869 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2870 if (status != IXGBE_SUCCESS)
2872 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2873 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2874 status = hw->mac.ops.write_iosf_sb_reg(hw,
2875 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2876 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2877 if (status != IXGBE_SUCCESS)
2880 /* Set loopback enable. */
2881 status = hw->mac.ops.read_iosf_sb_reg(hw,
2882 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2883 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2884 if (status != IXGBE_SUCCESS)
2886 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2887 status = hw->mac.ops.write_iosf_sb_reg(hw,
2888 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2889 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2890 if (status != IXGBE_SUCCESS)
2893 /* Training bypass. */
2894 status = hw->mac.ops.read_iosf_sb_reg(hw,
2895 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2896 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2897 if (status != IXGBE_SUCCESS)
2899 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2900 status = hw->mac.ops.write_iosf_sb_reg(hw,
2901 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2902 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2908 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2909 * assuming that the semaphore is already obtained.
2910 * @hw: pointer to hardware structure
2911 * @offset: offset of word in the EEPROM to read
2912 * @data: word read from the EEPROM
2914 * Reads a 16 bit word from the EEPROM using the hostif.
2916 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2920 struct ixgbe_hic_read_shadow_ram buffer;
2922 DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2923 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2924 buffer.hdr.req.buf_lenh = 0;
2925 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2926 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2928 /* convert offset from words to bytes */
2929 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2931 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2933 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2935 IXGBE_HI_COMMAND_TIMEOUT, false);
2940 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2941 FW_NVM_DATA_OFFSET);
2947 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2948 * @hw: pointer to hardware structure
2949 * @offset: offset of word in the EEPROM to read
2950 * @data: word read from the EEPROM
2952 * Reads a 16 bit word from the EEPROM using the hostif.
2954 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2957 s32 status = IXGBE_SUCCESS;
2959 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2961 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2963 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2964 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2966 status = IXGBE_ERR_SWFW_SYNC;
2973 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2974 * @hw: pointer to hardware structure
2975 * @offset: offset of word in the EEPROM to read
2976 * @words: number of words
2977 * @data: word(s) read from the EEPROM
2979 * Reads a 16 bit word(s) from the EEPROM using the hostif.
2981 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2982 u16 offset, u16 words, u16 *data)
2984 struct ixgbe_hic_read_shadow_ram buffer;
2985 u32 current_word = 0;
2990 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2992 /* Take semaphore for the entire operation. */
2993 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2995 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2999 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3000 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3002 words_to_read = words;
3004 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3005 buffer.hdr.req.buf_lenh = 0;
3006 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3007 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3009 /* convert offset from words to bytes */
3010 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3011 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3013 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3015 IXGBE_HI_COMMAND_TIMEOUT,
3019 DEBUGOUT("Host interface command failed\n");
3023 for (i = 0; i < words_to_read; i++) {
3024 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3026 u32 value = IXGBE_READ_REG(hw, reg);
3028 data[current_word] = (u16)(value & 0xffff);
3031 if (i < words_to_read) {
3033 data[current_word] = (u16)(value & 0xffff);
3037 words -= words_to_read;
3041 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3046 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3047 * @hw: pointer to hardware structure
3048 * @offset: offset of word in the EEPROM to write
3049 * @data: word write to the EEPROM
3051 * Write a 16 bit word to the EEPROM using the hostif.
3053 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3057 struct ixgbe_hic_write_shadow_ram buffer;
3059 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3061 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3062 buffer.hdr.req.buf_lenh = 0;
3063 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3064 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3067 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3069 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3071 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3073 IXGBE_HI_COMMAND_TIMEOUT, false);
3079 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3080 * @hw: pointer to hardware structure
3081 * @offset: offset of word in the EEPROM to write
3082 * @data: word write to the EEPROM
3084 * Write a 16 bit word to the EEPROM using the hostif.
3086 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3089 s32 status = IXGBE_SUCCESS;
3091 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3093 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3095 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3096 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3098 DEBUGOUT("write ee hostif failed to get semaphore");
3099 status = IXGBE_ERR_SWFW_SYNC;
3106 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3107 * @hw: pointer to hardware structure
3108 * @offset: offset of word in the EEPROM to write
3109 * @words: number of words
3110 * @data: word(s) write to the EEPROM
3112 * Write a 16 bit word(s) to the EEPROM using the hostif.
3114 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3115 u16 offset, u16 words, u16 *data)
3117 s32 status = IXGBE_SUCCESS;
3120 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3122 /* Take semaphore for the entire operation. */
3123 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3124 if (status != IXGBE_SUCCESS) {
3125 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3129 for (i = 0; i < words; i++) {
3130 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3133 if (status != IXGBE_SUCCESS) {
3134 DEBUGOUT("Eeprom buffered write failed\n");
3139 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3146 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3147 * @hw: pointer to hardware structure
3148 * @ptr: pointer offset in eeprom
3149 * @size: size of section pointed by ptr, if 0 first word will be used as size
3150 * @csum: address of checksum to update
3152 * Returns error status for any failure
3154 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3155 u16 size, u16 *csum, u16 *buffer,
3160 u16 length, bufsz, i, start;
3163 bufsz = sizeof(buf) / sizeof(buf[0]);
3165 /* Read a chunk at the pointer location */
3167 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3169 DEBUGOUT("Failed to read EEPROM image\n");
3174 if (buffer_size < ptr)
3175 return IXGBE_ERR_PARAM;
3176 local_buffer = &buffer[ptr];
3184 length = local_buffer[0];
3186 /* Skip pointer section if length is invalid. */
3187 if (length == 0xFFFF || length == 0 ||
3188 (ptr + length) >= hw->eeprom.word_size)
3189 return IXGBE_SUCCESS;
3192 if (buffer && ((u32)start + (u32)length > buffer_size))
3193 return IXGBE_ERR_PARAM;
3195 for (i = start; length; i++, length--) {
3196 if (i == bufsz && !buffer) {
3202 /* Read a chunk at the pointer location */
3203 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3206 DEBUGOUT("Failed to read EEPROM image\n");
3210 *csum += local_buffer[i];
3212 return IXGBE_SUCCESS;
3216 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3217 * @hw: pointer to hardware structure
3218 * @buffer: pointer to buffer containing calculated checksum
3219 * @buffer_size: size of buffer
3221 * Returns a negative error code on error, or the 16-bit checksum
3223 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3225 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3229 u16 pointer, i, size;
3231 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3233 hw->eeprom.ops.init_params(hw);
3236 /* Read pointer area */
3237 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3238 IXGBE_EEPROM_LAST_WORD + 1,
3241 DEBUGOUT("Failed to read EEPROM image\n");
3244 local_buffer = eeprom_ptrs;
3246 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3247 return IXGBE_ERR_PARAM;
3248 local_buffer = buffer;
3252 * For X550 hardware include 0x0-0x41 in the checksum, skip the
3253 * checksum word itself
3255 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3256 if (i != IXGBE_EEPROM_CHECKSUM)
3257 checksum += local_buffer[i];
3260 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
3261 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3263 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3264 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3267 pointer = local_buffer[i];
3269 /* Skip pointer section if the pointer is invalid. */
3270 if (pointer == 0xFFFF || pointer == 0 ||
3271 pointer >= hw->eeprom.word_size)
3275 case IXGBE_PCIE_GENERAL_PTR:
3276 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3278 case IXGBE_PCIE_CONFIG0_PTR:
3279 case IXGBE_PCIE_CONFIG1_PTR:
3280 size = IXGBE_PCIE_CONFIG_SIZE;
3287 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3288 buffer, buffer_size);
3293 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3295 return (s32)checksum;
3299 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3300 * @hw: pointer to hardware structure
3302 * Returns a negative error code on error, or the 16-bit checksum
3304 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3306 return ixgbe_calc_checksum_X550(hw, NULL, 0);
3310 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3311 * @hw: pointer to hardware structure
3312 * @checksum_val: calculated checksum
3314 * Performs checksum calculation and validates the EEPROM checksum. If the
3315 * caller does not need checksum_val, the value can be NULL.
3317 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3321 u16 read_checksum = 0;
3323 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3325 /* Read the first word from the EEPROM. If this times out or fails, do
3326 * not continue or we could be in for a very long wait while every
3329 status = hw->eeprom.ops.read(hw, 0, &checksum);
3331 DEBUGOUT("EEPROM read failed\n");
3335 status = hw->eeprom.ops.calc_checksum(hw);
3339 checksum = (u16)(status & 0xffff);
3341 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3346 /* Verify read checksum from EEPROM is the same as
3347 * calculated checksum
3349 if (read_checksum != checksum) {
3350 status = IXGBE_ERR_EEPROM_CHECKSUM;
3351 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3352 "Invalid EEPROM checksum");
3355 /* If the user cares, return the calculated checksum */
3357 *checksum_val = checksum;
3363 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3364 * @hw: pointer to hardware structure
3366 * After writing EEPROM to shadow RAM using EEWR register, software calculates
3367 * checksum and updates the EEPROM and instructs the hardware to update
3370 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3375 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3377 /* Read the first word from the EEPROM. If this times out or fails, do
3378 * not continue or we could be in for a very long wait while every
3381 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3383 DEBUGOUT("EEPROM read failed\n");
3387 status = ixgbe_calc_eeprom_checksum_X550(hw);
3391 checksum = (u16)(status & 0xffff);
3393 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3398 status = ixgbe_update_flash_X550(hw);
3404 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3405 * @hw: pointer to hardware structure
3407 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3409 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3411 s32 status = IXGBE_SUCCESS;
3412 union ixgbe_hic_hdr2 buffer;
3414 DEBUGFUNC("ixgbe_update_flash_X550");
3416 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3417 buffer.req.buf_lenh = 0;
3418 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3419 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3421 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3423 IXGBE_HI_COMMAND_TIMEOUT, false);
3429 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3430 * @hw: pointer to hardware structure
3432 * Determines physical layer capabilities of the current configuration.
3434 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3436 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3437 u16 ext_ability = 0;
3439 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3441 hw->phy.ops.identify(hw);
3443 switch (hw->phy.type) {
3444 case ixgbe_phy_x550em_kr:
3445 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3446 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3448 case ixgbe_phy_x550em_kx4:
3449 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3450 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3452 case ixgbe_phy_x550em_ext_t:
3453 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3454 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3456 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3457 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3458 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3459 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3465 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3466 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3468 return physical_layer;
3472 * ixgbe_get_bus_info_x550em - Set PCI bus info
3473 * @hw: pointer to hardware structure
3475 * Sets bus link width and speed to unknown because X550em is
3478 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3481 DEBUGFUNC("ixgbe_get_bus_info_x550em");
3483 hw->bus.width = ixgbe_bus_width_unknown;
3484 hw->bus.speed = ixgbe_bus_speed_unknown;
3486 hw->mac.ops.set_lan_id(hw);
3488 return IXGBE_SUCCESS;
3492 * ixgbe_disable_rx_x550 - Disable RX unit
3494 * Enables the Rx DMA unit for x550
3496 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3498 u32 rxctrl, pfdtxgswc;
3500 struct ixgbe_hic_disable_rxen fw_cmd;
3502 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3504 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3505 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3506 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3507 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3508 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3509 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3510 hw->mac.set_lben = true;
3512 hw->mac.set_lben = false;
3515 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3516 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3517 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3518 fw_cmd.port_number = (u8)hw->bus.lan_id;
3520 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3521 sizeof(struct ixgbe_hic_disable_rxen),
3522 IXGBE_HI_COMMAND_TIMEOUT, true);
3524 /* If we fail - disable RX using register write */
3526 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3527 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3528 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3529 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3536 * ixgbe_enter_lplu_x550em - Transition to low power states
3537 * @hw: pointer to hardware structure
3539 * Configures Low Power Link Up on transition to low power states
3540 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3541 * X557 PHY immediately prior to entering LPLU.
3543 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3545 u16 an_10g_cntl_reg, autoneg_reg, speed;
3547 ixgbe_link_speed lcd_speed;
3551 /* SW LPLU not required on later HW revisions. */
3552 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3553 (IXGBE_FUSES0_REV_MASK &
3554 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3555 return IXGBE_SUCCESS;
3557 /* If blocked by MNG FW, then don't restart AN */
3558 if (ixgbe_check_reset_blocked(hw))
3559 return IXGBE_SUCCESS;
3561 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3562 if (status != IXGBE_SUCCESS)
3565 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3567 if (status != IXGBE_SUCCESS)
3570 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3571 * disabled, then force link down by entering low power mode.
3573 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3574 !(hw->wol_enabled || ixgbe_mng_present(hw)))
3575 return ixgbe_set_copper_phy_power(hw, FALSE);
3578 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3580 if (status != IXGBE_SUCCESS)
3583 /* If no valid LCD link speed, then force link down and exit. */
3584 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3585 return ixgbe_set_copper_phy_power(hw, FALSE);
3587 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3588 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3591 if (status != IXGBE_SUCCESS)
3594 /* If no link now, speed is invalid so take link down */
3595 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3596 if (status != IXGBE_SUCCESS)
3597 return ixgbe_set_copper_phy_power(hw, false);
3599 /* clear everything but the speed bits */
3600 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3602 /* If current speed is already LCD, then exit. */
3603 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3604 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3605 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3606 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3609 /* Clear AN completed indication */
3610 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3611 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3614 if (status != IXGBE_SUCCESS)
3617 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3618 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3621 if (status != IXGBE_SUCCESS)
3624 status = hw->phy.ops.read_reg(hw,
3625 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3626 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3629 if (status != IXGBE_SUCCESS)
3632 save_autoneg = hw->phy.autoneg_advertised;
3634 /* Setup link at least common link speed */
3635 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3637 /* restore autoneg from before setting lplu speed */
3638 hw->phy.autoneg_advertised = save_autoneg;
3644 * ixgbe_get_lcd_x550em - Determine lowest common denominator
3645 * @hw: pointer to hardware structure
3646 * @lcd_speed: pointer to lowest common link speed
3648 * Determine lowest common link speed with link partner.
3650 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3654 u16 word = hw->eeprom.ctrl_word_3;
3656 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3658 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3659 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3662 if (status != IXGBE_SUCCESS)
3665 /* If link partner advertised 1G, return 1G */
3666 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3667 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3671 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3672 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3673 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3676 /* Link partner not capable of lower speeds, return 10G */
3677 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3682 * ixgbe_setup_fc_X550em - Set up flow control
3683 * @hw: pointer to hardware structure
3685 * Called at init time to set up flow control.
3687 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3689 s32 ret_val = IXGBE_SUCCESS;
3690 u32 pause, asm_dir, reg_val;
3692 DEBUGFUNC("ixgbe_setup_fc_X550em");
3694 /* Validate the requested mode */
3695 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3696 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3697 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3698 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3702 /* 10gig parts do not have a word in the EEPROM to determine the
3703 * default flow control setting, so we explicitly set it to full.
3705 if (hw->fc.requested_mode == ixgbe_fc_default)
3706 hw->fc.requested_mode = ixgbe_fc_full;
3708 /* Determine PAUSE and ASM_DIR bits. */
3709 switch (hw->fc.requested_mode) {
3714 case ixgbe_fc_tx_pause:
3718 case ixgbe_fc_rx_pause:
3719 /* Rx Flow control is enabled and Tx Flow control is
3720 * disabled by software override. Since there really
3721 * isn't a way to advertise that we are capable of RX
3722 * Pause ONLY, we will advertise that we support both
3723 * symmetric and asymmetric Rx PAUSE, as such we fall
3724 * through to the fc_full statement. Later, we will
3725 * disable the adapter's ability to send PAUSE frames.
3732 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3733 "Flow control param set incorrectly\n");
3734 ret_val = IXGBE_ERR_CONFIG;
3738 switch (hw->device_id) {
3739 case IXGBE_DEV_ID_X550EM_X_KR:
3740 case IXGBE_DEV_ID_X550EM_A_KR:
3741 case IXGBE_DEV_ID_X550EM_A_KR_L:
3742 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
3743 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3744 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3745 if (ret_val != IXGBE_SUCCESS)
3747 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3748 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3750 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3752 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3753 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
3754 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3755 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3757 /* This device does not fully support AN. */
3758 hw->fc.disable_fc_autoneg = true;
3769 * ixgbe_fc_autoneg_x550a - Enable flow control IEEE clause 37
3770 * @hw: pointer to hardware structure
3772 * Enable flow control according to IEEE clause 37.
3774 void ixgbe_fc_autoneg_x550a(struct ixgbe_hw *hw)
3776 u32 link_s1, lp_an_page_low, an_cntl_1;
3777 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
3778 ixgbe_link_speed speed;
3781 /* AN should have completed when the cable was plugged in.
3782 * Look for reasons to bail out. Bail out if:
3783 * - FC autoneg is disabled, or if
3786 if (hw->fc.disable_fc_autoneg) {
3787 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3788 "Flow control autoneg is disabled");
3792 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3794 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3798 /* Check at auto-negotiation has completed */
3799 status = hw->mac.ops.read_iosf_sb_reg(hw,
3800 IXGBE_KRM_LINK_S1(hw->bus.lan_id),
3801 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
3803 if (status != IXGBE_SUCCESS ||
3804 (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
3805 DEBUGOUT("Auto-Negotiation did not complete\n");
3809 /* Read the 10g AN autoc and LP ability registers and resolve
3810 * local flow control settings accordingly
3812 status = hw->mac.ops.read_iosf_sb_reg(hw,
3813 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3814 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
3816 if (status != IXGBE_SUCCESS) {
3817 DEBUGOUT("Auto-Negotiation did not complete\n");
3821 status = hw->mac.ops.read_iosf_sb_reg(hw,
3822 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
3823 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
3825 if (status != IXGBE_SUCCESS) {
3826 DEBUGOUT("Auto-Negotiation did not complete\n");
3830 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
3831 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
3832 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
3833 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
3834 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
3837 if (status == IXGBE_SUCCESS) {
3838 hw->fc.fc_was_autonegged = true;
3840 hw->fc.fc_was_autonegged = false;
3841 hw->fc.current_mode = hw->fc.requested_mode;
3846 * ixgbe_setup_fc_x550em - Set up flow control
3847 * @hw: pointer to hardware structure
3849 * Called at init time to set up flow control.
3851 s32 ixgbe_setup_fc_x550a(struct ixgbe_hw *hw)
3853 s32 status = IXGBE_SUCCESS;
3854 u32 an_cntl, link_ctrl = 0;
3856 DEBUGFUNC("ixgbe_setup_fc_x550em");
3858 /* Validate the requested mode */
3859 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3860 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3861 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3862 return IXGBE_ERR_INVALID_LINK_SETTINGS;
3865 if (hw->fc.requested_mode == ixgbe_fc_default)
3866 hw->fc.requested_mode = ixgbe_fc_full;
3868 /* Set up the 1G and 10G flow control advertisement registers so the
3869 * HW will be able to do FC autoneg once the cable is plugged in. If
3870 * we link at 10G, the 1G advertisement is harmless and vice versa.
3872 status = hw->mac.ops.read_iosf_sb_reg(hw,
3873 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3874 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
3876 if (status != IXGBE_SUCCESS) {
3877 DEBUGOUT("Auto-Negotiation did not complete\n");
3881 /* The possible values of fc.requested_mode are:
3882 * 0: Flow control is completely disabled
3883 * 1: Rx flow control is enabled (we can receive pause frames,
3884 * but not send pause frames).
3885 * 2: Tx flow control is enabled (we can send pause frames but
3886 * we do not support receiving pause frames).
3887 * 3: Both Rx and Tx flow control (symmetric) are enabled.
3890 switch (hw->fc.requested_mode) {
3892 /* Flow control completely disabled by software override. */
3893 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3894 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3896 case ixgbe_fc_tx_pause:
3897 /* Tx Flow control is enabled, and Rx Flow control is
3898 * disabled by software override.
3900 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3901 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3903 case ixgbe_fc_rx_pause:
3904 /* Rx Flow control is enabled and Tx Flow control is
3905 * disabled by software override. Since there really
3906 * isn't a way to advertise that we are capable of RX
3907 * Pause ONLY, we will advertise that we support both
3908 * symmetric and asymmetric Rx PAUSE, as such we fall
3909 * through to the fc_full statement. Later, we will
3910 * disable the adapter's ability to send PAUSE frames.
3913 /* Flow control (both Rx and Tx) is enabled by SW override. */
3914 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3915 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3918 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3919 "Flow control param set incorrectly\n");
3920 return IXGBE_ERR_CONFIG;
3923 status = hw->mac.ops.write_iosf_sb_reg(hw,
3924 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3925 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
3927 /* Restart auto-negotiation. */
3928 status = hw->mac.ops.read_iosf_sb_reg(hw,
3929 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3930 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
3932 if (status != IXGBE_SUCCESS) {
3933 DEBUGOUT("Auto-Negotiation did not complete\n");
3937 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
3938 status = hw->mac.ops.write_iosf_sb_reg(hw,
3939 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3940 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
3946 * ixgbe_set_mux - Set mux for port 1 access with CS4227
3947 * @hw: pointer to hardware structure
3948 * @state: set mux if 1, clear if 0
3950 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
3954 if (!hw->bus.lan_id)
3956 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3958 esdp |= IXGBE_ESDP_SDP1;
3960 esdp &= ~IXGBE_ESDP_SDP1;
3961 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
3962 IXGBE_WRITE_FLUSH(hw);
3966 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
3967 * @hw: pointer to hardware structure
3968 * @mask: Mask to specify which semaphore to acquire
3970 * Acquires the SWFW semaphore and sets the I2C MUX
3972 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3976 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
3978 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
3982 if (mask & IXGBE_GSSR_I2C_MASK)
3983 ixgbe_set_mux(hw, 1);
3985 return IXGBE_SUCCESS;
3989 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
3990 * @hw: pointer to hardware structure
3991 * @mask: Mask to specify which semaphore to release
3993 * Releases the SWFW semaphore and sets the I2C MUX
3995 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3997 DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
3999 if (mask & IXGBE_GSSR_I2C_MASK)
4000 ixgbe_set_mux(hw, 0);
4002 ixgbe_release_swfw_sync_X540(hw, mask);
4006 * ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4007 * @hw: pointer to hardware structure
4008 * @mask: Mask to specify which semaphore to acquire
4010 * Acquires the SWFW semaphore and get the shared phy token as needed
4012 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4014 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4015 int retries = FW_PHY_TOKEN_RETRIES;
4016 s32 status = IXGBE_SUCCESS;
4018 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4021 status = IXGBE_SUCCESS;
4023 status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4026 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4027 return IXGBE_SUCCESS;
4029 status = ixgbe_get_phy_token(hw);
4030 if (status == IXGBE_SUCCESS)
4031 return IXGBE_SUCCESS;
4034 ixgbe_release_swfw_sync_X540(hw, hmask);
4035 if (status != IXGBE_ERR_TOKEN_RETRY)
4037 msec_delay(FW_PHY_TOKEN_DELAY);
4044 * ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4045 * @hw: pointer to hardware structure
4046 * @mask: Mask to specify which semaphore to release
4048 * Releases the SWFW semaphore and puts the shared phy token as needed
4050 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4052 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4054 DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4056 if (mask & IXGBE_GSSR_TOKEN_SM)
4057 ixgbe_put_phy_token(hw);
4060 ixgbe_release_swfw_sync_X540(hw, hmask);
4064 * ixgbe_read_phy_reg_x550a - Reads specified PHY register
4065 * @hw: pointer to hardware structure
4066 * @reg_addr: 32 bit address of PHY register to read
4067 * @phy_data: Pointer to read data from PHY register
4069 * Reads a value from a specified PHY register using the SWFW lock and PHY
4070 * Token. The PHY Token is needed since the MDIO is shared between to MAC
4073 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4074 u32 device_type, u16 *phy_data)
4077 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4079 DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4081 if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4082 return IXGBE_ERR_SWFW_SYNC;
4084 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4086 hw->mac.ops.release_swfw_sync(hw, mask);
4092 * ixgbe_write_phy_reg_x550a - Writes specified PHY register
4093 * @hw: pointer to hardware structure
4094 * @reg_addr: 32 bit PHY register to write
4095 * @device_type: 5 bit device type
4096 * @phy_data: Data to write to the PHY register
4098 * Writes a value to specified PHY register using the SWFW lock and PHY Token.
4099 * The PHY Token is needed since the MDIO is shared between to MAC instances.
4101 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4102 u32 device_type, u16 phy_data)
4105 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4107 DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4109 if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4110 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
4112 hw->mac.ops.release_swfw_sync(hw, mask);
4114 status = IXGBE_ERR_SWFW_SYNC;
4121 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4122 * @hw: pointer to hardware structure
4124 * Handle external Base T PHY interrupt. If high temperature
4125 * failure alarm then return error, else if link status change
4126 * then setup internal/external PHY link
4128 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4129 * failure alarm, else return PHY access status.
4131 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4136 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4138 if (status != IXGBE_SUCCESS)
4142 return ixgbe_setup_internal_phy(hw);
4144 return IXGBE_SUCCESS;
4148 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4149 * @hw: pointer to hardware structure
4150 * @speed: new link speed
4151 * @autoneg_wait_to_complete: true when waiting for completion is needed
4153 * Setup internal/external PHY link speed based on link speed, then set
4154 * external PHY auto advertised link speed.
4156 * Returns error status for any failure
4158 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4159 ixgbe_link_speed speed,
4160 bool autoneg_wait_to_complete)
4163 ixgbe_link_speed force_speed;
4165 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4167 /* Setup internal/external PHY link speed to iXFI (10G), unless
4168 * only 1G is auto advertised then setup KX link.
4170 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4171 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4173 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4175 /* If internal link mode is XFI, then setup XFI internal link. */
4176 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4177 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4179 if (status != IXGBE_SUCCESS)
4183 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4187 * ixgbe_check_link_t_X550em - Determine link and speed status
4188 * @hw: pointer to hardware structure
4189 * @speed: pointer to link speed
4190 * @link_up: true when link is up
4191 * @link_up_wait_to_complete: bool used to wait for link up or not
4193 * Check that both the MAC and X557 external PHY have link.
4195 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4196 bool *link_up, bool link_up_wait_to_complete)
4201 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4202 return IXGBE_ERR_CONFIG;
4204 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4205 link_up_wait_to_complete);
4207 /* If check link fails or MAC link is not up, then return */
4208 if (status != IXGBE_SUCCESS || !(*link_up))
4211 /* MAC link is up, so check external PHY link.
4212 * Read this twice back to back to indicate current status.
4214 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4215 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4218 if (status != IXGBE_SUCCESS)
4221 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4222 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4225 if (status != IXGBE_SUCCESS)
4228 /* If external PHY link is not up, then indicate link not up */
4229 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4232 return IXGBE_SUCCESS;
4236 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4237 * @hw: pointer to hardware structure
4239 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4243 status = ixgbe_reset_phy_generic(hw);
4245 if (status != IXGBE_SUCCESS)
4248 /* Configure Link Status Alarm and Temperature Threshold interrupts */
4249 return ixgbe_enable_lasi_ext_t_x550em(hw);
4253 * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4254 * @hw: pointer to hardware structure
4255 * @led_idx: led number to turn on
4257 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4261 DEBUGFUNC("ixgbe_led_on_t_X550em");
4263 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4264 return IXGBE_ERR_PARAM;
4266 /* To turn on the LED, set mode to ON. */
4267 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4268 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4269 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4270 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4271 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4273 return IXGBE_SUCCESS;
4277 * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4278 * @hw: pointer to hardware structure
4279 * @led_idx: led number to turn off
4281 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4285 DEBUGFUNC("ixgbe_led_off_t_X550em");
4287 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4288 return IXGBE_ERR_PARAM;
4290 /* To turn on the LED, set mode to ON. */
4291 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4292 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4293 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4294 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4295 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4297 return IXGBE_SUCCESS;