1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
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13 notice, this list of conditions and the following disclaimer in the
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17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
46 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
47 * @hw: pointer to hardware structure
49 * Initialize the function pointers and assign the MAC type for X550.
50 * Does not touch the hardware.
52 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
54 struct ixgbe_mac_info *mac = &hw->mac;
55 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
58 DEBUGFUNC("ixgbe_init_ops_X550");
60 ret_val = ixgbe_init_ops_X540(hw);
61 mac->ops.dmac_config = ixgbe_dmac_config_X550;
62 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
63 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
64 mac->ops.setup_eee = ixgbe_setup_eee_X550;
65 mac->ops.set_source_address_pruning =
66 ixgbe_set_source_address_pruning_X550;
67 mac->ops.set_ethertype_anti_spoofing =
68 ixgbe_set_ethertype_anti_spoofing_X550;
70 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
71 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
72 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
73 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
74 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
75 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
76 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
77 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
78 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
80 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
81 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
82 mac->ops.mdd_event = ixgbe_mdd_event_X550;
83 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
84 mac->ops.disable_rx = ixgbe_disable_rx_x550;
85 switch (hw->device_id) {
86 case IXGBE_DEV_ID_X550EM_X_10G_T:
87 case IXGBE_DEV_ID_X550EM_A_10G_T:
88 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
89 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
98 * ixgbe_read_cs4227 - Read CS4227 register
99 * @hw: pointer to hardware structure
100 * @reg: register number to write
101 * @value: pointer to receive value read
103 * Returns status code
105 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
107 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
111 * ixgbe_write_cs4227 - Write CS4227 register
112 * @hw: pointer to hardware structure
113 * @reg: register number to write
114 * @value: value to write to register
116 * Returns status code
118 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
120 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
124 * ixgbe_read_pe - Read register from port expander
125 * @hw: pointer to hardware structure
126 * @reg: register number to read
127 * @value: pointer to receive read value
129 * Returns status code
131 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
135 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
136 if (status != IXGBE_SUCCESS)
137 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
138 "port expander access failed with %d\n", status);
143 * ixgbe_write_pe - Write register to port expander
144 * @hw: pointer to hardware structure
145 * @reg: register number to write
146 * @value: value to write
148 * Returns status code
150 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
154 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
155 if (status != IXGBE_SUCCESS)
156 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
157 "port expander access failed with %d\n", status);
162 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
163 * @hw: pointer to hardware structure
165 * This function assumes that the caller has acquired the proper semaphore.
168 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
175 /* Trigger hard reset. */
176 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
177 if (status != IXGBE_SUCCESS)
179 reg |= IXGBE_PE_BIT1;
180 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
181 if (status != IXGBE_SUCCESS)
184 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
185 if (status != IXGBE_SUCCESS)
187 reg &= ~IXGBE_PE_BIT1;
188 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
189 if (status != IXGBE_SUCCESS)
192 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
193 if (status != IXGBE_SUCCESS)
195 reg &= ~IXGBE_PE_BIT1;
196 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
197 if (status != IXGBE_SUCCESS)
200 usec_delay(IXGBE_CS4227_RESET_HOLD);
202 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
203 if (status != IXGBE_SUCCESS)
205 reg |= IXGBE_PE_BIT1;
206 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
207 if (status != IXGBE_SUCCESS)
210 /* Wait for the reset to complete. */
211 msec_delay(IXGBE_CS4227_RESET_DELAY);
212 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
213 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
215 if (status == IXGBE_SUCCESS &&
216 value == IXGBE_CS4227_EEPROM_LOAD_OK)
218 msec_delay(IXGBE_CS4227_CHECK_DELAY);
220 if (retry == IXGBE_CS4227_RETRIES) {
221 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
222 "CS4227 reset did not complete.");
223 return IXGBE_ERR_PHY;
226 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
227 if (status != IXGBE_SUCCESS ||
228 !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
229 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
230 "CS4227 EEPROM did not load successfully.");
231 return IXGBE_ERR_PHY;
234 return IXGBE_SUCCESS;
238 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
239 * @hw: pointer to hardware structure
241 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
243 s32 status = IXGBE_SUCCESS;
244 u32 swfw_mask = hw->phy.phy_semaphore_mask;
248 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
249 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
250 if (status != IXGBE_SUCCESS) {
251 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
252 "semaphore failed with %d", status);
253 msec_delay(IXGBE_CS4227_CHECK_DELAY);
257 /* Get status of reset flow. */
258 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
260 if (status == IXGBE_SUCCESS &&
261 value == IXGBE_CS4227_RESET_COMPLETE)
264 if (status != IXGBE_SUCCESS ||
265 value != IXGBE_CS4227_RESET_PENDING)
268 /* Reset is pending. Wait and check again. */
269 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
270 msec_delay(IXGBE_CS4227_CHECK_DELAY);
273 /* If still pending, assume other instance failed. */
274 if (retry == IXGBE_CS4227_RETRIES) {
275 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
276 if (status != IXGBE_SUCCESS) {
277 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
278 "semaphore failed with %d", status);
283 /* Reset the CS4227. */
284 status = ixgbe_reset_cs4227(hw);
285 if (status != IXGBE_SUCCESS) {
286 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
287 "CS4227 reset failed: %d", status);
291 /* Reset takes so long, temporarily release semaphore in case the
292 * other driver instance is waiting for the reset indication.
294 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
295 IXGBE_CS4227_RESET_PENDING);
296 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
298 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
299 if (status != IXGBE_SUCCESS) {
300 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
301 "semaphore failed with %d", status);
305 /* Record completion for next time. */
306 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
307 IXGBE_CS4227_RESET_COMPLETE);
310 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
311 msec_delay(hw->eeprom.semaphore_delay);
315 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
316 * @hw: pointer to hardware structure
318 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
320 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
322 if (hw->bus.lan_id) {
323 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
324 esdp |= IXGBE_ESDP_SDP1_DIR;
326 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
327 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
328 IXGBE_WRITE_FLUSH(hw);
332 * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
333 * @hw: pointer to hardware structure
334 * @reg_addr: 32 bit address of PHY register to read
335 * @dev_type: always unused
336 * @phy_data: Pointer to read data from PHY register
338 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
339 u32 dev_type, u16 *phy_data)
341 u32 i, data, command;
342 UNREFERENCED_1PARAMETER(dev_type);
344 /* Setup and write the read command */
345 command = (reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
346 (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
347 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
348 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ |
349 IXGBE_MSCA_MDI_COMMAND;
351 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
353 /* Check every 10 usec to see if the access completed.
354 * The MDI Command bit will clear when the operation is
357 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
360 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
361 if (!(command & IXGBE_MSCA_MDI_COMMAND))
365 if (command & IXGBE_MSCA_MDI_COMMAND) {
366 ERROR_REPORT1(IXGBE_ERROR_POLLING,
367 "PHY read command did not complete.\n");
368 return IXGBE_ERR_PHY;
371 /* Read operation is complete. Get the data from MSRWD */
372 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
373 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
374 *phy_data = (u16)data;
376 return IXGBE_SUCCESS;
380 * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
381 * @hw: pointer to hardware structure
382 * @reg_addr: 32 bit PHY register to write
383 * @dev_type: always unused
384 * @phy_data: Data to write to the PHY register
386 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
387 u32 dev_type, u16 phy_data)
390 UNREFERENCED_1PARAMETER(dev_type);
392 /* Put the data in the MDI single read and write data register*/
393 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
395 /* Setup and write the write command */
396 command = (reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
397 (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
398 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
399 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
400 IXGBE_MSCA_MDI_COMMAND;
402 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
404 /* Check every 10 usec to see if the access completed.
405 * The MDI Command bit will clear when the operation is
408 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
411 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
412 if (!(command & IXGBE_MSCA_MDI_COMMAND))
416 if (command & IXGBE_MSCA_MDI_COMMAND) {
417 ERROR_REPORT1(IXGBE_ERROR_POLLING,
418 "PHY write cmd didn't complete\n");
419 return IXGBE_ERR_PHY;
422 return IXGBE_SUCCESS;
426 * ixgbe_identify_phy_1g - Get 1g PHY type based on device id
427 * @hw: pointer to hardware structure
431 STATIC s32 ixgbe_identify_phy_1g(struct ixgbe_hw *hw)
433 u32 swfw_mask = hw->phy.phy_semaphore_mask;
438 rc = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
442 rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_MDIO_PHY_ID_HIGH, 0,
447 rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_MDIO_PHY_ID_LOW, 0,
452 hw->phy.id = (u32)phy_id_high << 16;
453 hw->phy.id |= phy_id_low & IXGBE_PHY_REVISION_MASK;
454 hw->phy.revision = (u32)phy_id_low & ~IXGBE_PHY_REVISION_MASK;
457 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
463 * ixgbe_identify_phy_x550em - Get PHY type based on device id
464 * @hw: pointer to hardware structure
468 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
470 switch (hw->device_id) {
471 case IXGBE_DEV_ID_X550EM_A_SFP:
472 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
473 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
475 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
477 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
478 return ixgbe_identify_module_generic(hw);
479 case IXGBE_DEV_ID_X550EM_X_SFP:
480 /* set up for CS4227 usage */
481 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
482 ixgbe_setup_mux_ctl(hw);
483 ixgbe_check_cs4227(hw);
486 case IXGBE_DEV_ID_X550EM_A_SFP_N:
487 return ixgbe_identify_module_generic(hw);
489 case IXGBE_DEV_ID_X550EM_X_KX4:
490 hw->phy.type = ixgbe_phy_x550em_kx4;
492 case IXGBE_DEV_ID_X550EM_X_KR:
493 case IXGBE_DEV_ID_X550EM_A_KR:
494 case IXGBE_DEV_ID_X550EM_A_KR_L:
495 hw->phy.type = ixgbe_phy_x550em_kr;
497 case IXGBE_DEV_ID_X550EM_X_1G_T:
498 case IXGBE_DEV_ID_X550EM_X_10G_T:
499 case IXGBE_DEV_ID_X550EM_A_10G_T:
500 return ixgbe_identify_phy_generic(hw);
501 case IXGBE_DEV_ID_X550EM_A_1G_T:
502 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
503 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
504 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
506 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
508 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
509 return ixgbe_identify_phy_1g(hw);
513 return IXGBE_SUCCESS;
516 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
517 u32 device_type, u16 *phy_data)
519 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
520 return IXGBE_NOT_IMPLEMENTED;
523 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
524 u32 device_type, u16 phy_data)
526 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
527 return IXGBE_NOT_IMPLEMENTED;
531 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
532 * @hw: pointer to the hardware structure
533 * @addr: I2C bus address to read from
534 * @reg: I2C device register to read from
535 * @val: pointer to location to receive read value
537 * Returns an error code on error.
539 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
542 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
546 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
547 * @hw: pointer to the hardware structure
548 * @addr: I2C bus address to read from
549 * @reg: I2C device register to read from
550 * @val: pointer to location to receive read value
552 * Returns an error code on error.
555 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
558 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
562 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
563 * @hw: pointer to the hardware structure
564 * @addr: I2C bus address to write to
565 * @reg: I2C device register to write to
566 * @val: value to write
568 * Returns an error code on error.
570 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
571 u8 addr, u16 reg, u16 val)
573 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
577 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
578 * @hw: pointer to the hardware structure
579 * @addr: I2C bus address to write to
580 * @reg: I2C device register to write to
581 * @val: value to write
583 * Returns an error code on error.
586 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
587 u8 addr, u16 reg, u16 val)
589 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
593 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
594 * @hw: pointer to hardware structure
596 * Initialize the function pointers and for MAC type X550EM.
597 * Does not touch the hardware.
599 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
601 struct ixgbe_mac_info *mac = &hw->mac;
602 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
603 struct ixgbe_phy_info *phy = &hw->phy;
604 struct ixgbe_link_info *link = &hw->link;
607 DEBUGFUNC("ixgbe_init_ops_X550EM");
609 /* Similar to X550 so start there. */
610 ret_val = ixgbe_init_ops_X550(hw);
612 /* Since this function eventually calls
613 * ixgbe_init_ops_540 by design, we are setting
614 * the pointers to NULL explicitly here to overwrite
615 * the values being set in the x540 function.
617 /* Thermal sensor not supported in x550EM */
618 mac->ops.get_thermal_sensor_data = NULL;
619 mac->ops.init_thermal_sensor_thresh = NULL;
620 mac->thermal_sensor_enabled = false;
622 /* FCOE not supported in x550EM */
623 mac->ops.get_san_mac_addr = NULL;
624 mac->ops.set_san_mac_addr = NULL;
625 mac->ops.get_wwn_prefix = NULL;
626 mac->ops.get_fcoe_boot_status = NULL;
628 /* IPsec not supported in x550EM */
629 mac->ops.disable_sec_rx_path = NULL;
630 mac->ops.enable_sec_rx_path = NULL;
632 /* AUTOC register is not present in x550EM. */
633 mac->ops.prot_autoc_read = NULL;
634 mac->ops.prot_autoc_write = NULL;
636 /* X550EM bus type is internal*/
637 hw->bus.type = ixgbe_bus_type_internal;
638 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
640 if (hw->mac.type == ixgbe_mac_X550EM_x) {
641 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
642 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
643 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
644 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
645 link->ops.read_link = ixgbe_read_i2c_combined_generic;
646 link->ops.read_link_unlocked =
647 ixgbe_read_i2c_combined_generic_unlocked;
648 link->ops.write_link = ixgbe_write_i2c_combined_generic;
649 link->ops.write_link_unlocked =
650 ixgbe_write_i2c_combined_generic_unlocked;
651 link->addr = IXGBE_CS4227;
653 if (hw->mac.type == ixgbe_mac_X550EM_a) {
654 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
655 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
656 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
657 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
660 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
661 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
662 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
663 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
664 mac->ops.get_supported_physical_layer =
665 ixgbe_get_supported_physical_layer_X550em;
667 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
668 mac->ops.setup_fc = ixgbe_setup_fc_generic;
670 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
672 switch (hw->device_id) {
673 case IXGBE_DEV_ID_X550EM_X_KR:
674 case IXGBE_DEV_ID_X550EM_A_KR:
675 case IXGBE_DEV_ID_X550EM_A_KR_L:
678 mac->ops.setup_eee = NULL;
682 phy->ops.init = ixgbe_init_phy_ops_X550em;
683 phy->ops.identify = ixgbe_identify_phy_x550em;
684 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
685 phy->ops.set_phy_power = NULL;
689 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
690 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
691 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
692 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
693 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
694 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
695 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
696 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
702 * ixgbe_dmac_config_X550
703 * @hw: pointer to hardware structure
705 * Configure DMA coalescing. If enabling dmac, dmac is activated.
706 * When disabling dmac, dmac enable dmac bit is cleared.
708 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
710 u32 reg, high_pri_tc;
712 DEBUGFUNC("ixgbe_dmac_config_X550");
714 /* Disable DMA coalescing before configuring */
715 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
716 reg &= ~IXGBE_DMACR_DMAC_EN;
717 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
719 /* Disable DMA Coalescing if the watchdog timer is 0 */
720 if (!hw->mac.dmac_config.watchdog_timer)
723 ixgbe_dmac_config_tcs_X550(hw);
725 /* Configure DMA Coalescing Control Register */
726 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
728 /* Set the watchdog timer in units of 40.96 usec */
729 reg &= ~IXGBE_DMACR_DMACWT_MASK;
730 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
732 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
733 /* If fcoe is enabled, set high priority traffic class */
734 if (hw->mac.dmac_config.fcoe_en) {
735 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
736 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
737 IXGBE_DMACR_HIGH_PRI_TC_MASK);
739 reg |= IXGBE_DMACR_EN_MNG_IND;
741 /* Enable DMA coalescing after configuration */
742 reg |= IXGBE_DMACR_DMAC_EN;
743 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
746 return IXGBE_SUCCESS;
750 * ixgbe_dmac_config_tcs_X550
751 * @hw: pointer to hardware structure
753 * Configure DMA coalescing threshold per TC. The dmac enable bit must
754 * be cleared before configuring.
756 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
758 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
760 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
762 /* Configure DMA coalescing enabled */
763 switch (hw->mac.dmac_config.link_speed) {
764 case IXGBE_LINK_SPEED_100_FULL:
765 pb_headroom = IXGBE_DMACRXT_100M;
767 case IXGBE_LINK_SPEED_1GB_FULL:
768 pb_headroom = IXGBE_DMACRXT_1G;
771 pb_headroom = IXGBE_DMACRXT_10G;
775 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
776 IXGBE_MHADD_MFS_SHIFT) / 1024);
778 /* Set the per Rx packet buffer receive threshold */
779 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
780 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
781 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
783 if (tc < hw->mac.dmac_config.num_tcs) {
785 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
786 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
787 IXGBE_RXPBSIZE_SHIFT;
789 /* Calculate receive buffer threshold in kilobytes */
790 if (rx_pb_size > pb_headroom)
791 rx_pb_size = rx_pb_size - pb_headroom;
795 /* Minimum of MFS shall be set for DMCTH */
796 reg |= (rx_pb_size > maxframe_size_kb) ?
797 rx_pb_size : maxframe_size_kb;
799 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
801 return IXGBE_SUCCESS;
805 * ixgbe_dmac_update_tcs_X550
806 * @hw: pointer to hardware structure
808 * Disables dmac, updates per TC settings, and then enables dmac.
810 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
814 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
816 /* Disable DMA coalescing before configuring */
817 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
818 reg &= ~IXGBE_DMACR_DMAC_EN;
819 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
821 ixgbe_dmac_config_tcs_X550(hw);
823 /* Enable DMA coalescing after configuration */
824 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
825 reg |= IXGBE_DMACR_DMAC_EN;
826 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
828 return IXGBE_SUCCESS;
832 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
833 * @hw: pointer to hardware structure
835 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
836 * ixgbe_hw struct in order to set up EEPROM access.
838 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
840 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
844 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
846 if (eeprom->type == ixgbe_eeprom_uninitialized) {
847 eeprom->semaphore_delay = 10;
848 eeprom->type = ixgbe_flash;
850 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
851 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
852 IXGBE_EEC_SIZE_SHIFT);
853 eeprom->word_size = 1 << (eeprom_size +
854 IXGBE_EEPROM_WORD_SIZE_SHIFT);
856 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
857 eeprom->type, eeprom->word_size);
860 return IXGBE_SUCCESS;
864 * ixgbe_enable_eee_x550 - Enable EEE support
865 * @hw: pointer to hardware structure
867 STATIC s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
873 if (hw->mac.type == ixgbe_mac_X550) {
874 /* Advertise EEE capability */
875 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
876 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
879 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
880 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
881 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
883 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
884 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
886 return IXGBE_SUCCESS;
889 switch (hw->device_id) {
890 case IXGBE_DEV_ID_X550EM_X_KR:
891 case IXGBE_DEV_ID_X550EM_A_KR:
892 case IXGBE_DEV_ID_X550EM_A_KR_L:
893 status = hw->mac.ops.read_iosf_sb_reg(hw,
894 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
895 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
896 if (status != IXGBE_SUCCESS)
899 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
900 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
902 /* Don't advertise FEC capability when EEE enabled. */
903 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
905 status = hw->mac.ops.write_iosf_sb_reg(hw,
906 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
907 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
908 if (status != IXGBE_SUCCESS)
915 return IXGBE_SUCCESS;
919 * ixgbe_disable_eee_x550 - Disable EEE support
920 * @hw: pointer to hardware structure
922 STATIC s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
928 if (hw->mac.type == ixgbe_mac_X550) {
929 /* Disable advertised EEE capability */
930 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
931 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
934 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
935 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
936 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
938 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
939 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
941 return IXGBE_SUCCESS;
944 switch (hw->device_id) {
945 case IXGBE_DEV_ID_X550EM_X_KR:
946 case IXGBE_DEV_ID_X550EM_A_KR:
947 case IXGBE_DEV_ID_X550EM_A_KR_L:
948 status = hw->mac.ops.read_iosf_sb_reg(hw,
949 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
950 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
951 if (status != IXGBE_SUCCESS)
954 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
955 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
957 /* Advertise FEC capability when EEE is disabled. */
958 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
960 status = hw->mac.ops.write_iosf_sb_reg(hw,
961 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
962 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
963 if (status != IXGBE_SUCCESS)
970 return IXGBE_SUCCESS;
974 * ixgbe_setup_eee_X550 - Enable/disable EEE support
975 * @hw: pointer to the HW structure
976 * @enable_eee: boolean flag to enable EEE
978 * Enable/disable EEE based on enable_eee flag.
979 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
983 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
988 DEBUGFUNC("ixgbe_setup_eee_X550");
990 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
991 /* Enable or disable EEE per flag */
993 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
995 /* Not supported on first revision of X550EM_x. */
996 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
997 !(IXGBE_FUSES0_REV_MASK &
998 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
999 return IXGBE_SUCCESS;
1000 status = ixgbe_enable_eee_x550(hw);
1004 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1006 status = ixgbe_disable_eee_x550(hw);
1010 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
1012 return IXGBE_SUCCESS;
1016 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1017 * @hw: pointer to hardware structure
1018 * @enable: enable or disable source address pruning
1019 * @pool: Rx pool to set source address pruning for
1021 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1026 /* max rx pool is 63 */
1030 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1031 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1034 pfflp |= (1ULL << pool);
1036 pfflp &= ~(1ULL << pool);
1038 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1039 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1043 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1044 * @hw: pointer to hardware structure
1045 * @enable: enable or disable switch for Ethertype anti-spoofing
1046 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1049 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1050 bool enable, int vf)
1052 int vf_target_reg = vf >> 3;
1053 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1056 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1058 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1060 pfvfspoof |= (1 << vf_target_shift);
1062 pfvfspoof &= ~(1 << vf_target_shift);
1064 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1068 * ixgbe_iosf_wait - Wait for IOSF command completion
1069 * @hw: pointer to hardware structure
1070 * @ctrl: pointer to location to receive final IOSF control value
1072 * Returns failing status on timeout
1074 * Note: ctrl can be NULL if the IOSF control register value is not needed
1076 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1080 /* Check every 10 usec to see if the address cycle completed.
1081 * The SB IOSF BUSY bit will clear when the operation is
1084 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1085 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1086 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1092 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1093 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1094 return IXGBE_ERR_PHY;
1097 return IXGBE_SUCCESS;
1101 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
1103 * @hw: pointer to hardware structure
1104 * @reg_addr: 32 bit PHY register to write
1105 * @device_type: 3 bit device type
1106 * @data: Data to write to the register
1108 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1109 u32 device_type, u32 data)
1111 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1115 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1116 if (ret != IXGBE_SUCCESS)
1119 ret = ixgbe_iosf_wait(hw, NULL);
1120 if (ret != IXGBE_SUCCESS)
1123 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1124 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1126 /* Write IOSF control register */
1127 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1129 /* Write IOSF data register */
1130 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1132 ret = ixgbe_iosf_wait(hw, &command);
1134 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1135 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1136 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1137 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1138 "Failed to write, error %x\n", error);
1139 ret = IXGBE_ERR_PHY;
1143 ixgbe_release_swfw_semaphore(hw, gssr);
1148 * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
1150 * @hw: pointer to hardware structure
1151 * @reg_addr: 32 bit PHY register to write
1152 * @device_type: 3 bit device type
1153 * @phy_data: Pointer to read data from the register
1155 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1156 u32 device_type, u32 *data)
1158 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1162 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1163 if (ret != IXGBE_SUCCESS)
1166 ret = ixgbe_iosf_wait(hw, NULL);
1167 if (ret != IXGBE_SUCCESS)
1170 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1171 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1173 /* Write IOSF control register */
1174 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1176 ret = ixgbe_iosf_wait(hw, &command);
1178 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1179 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1180 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1181 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1182 "Failed to read, error %x\n", error);
1183 ret = IXGBE_ERR_PHY;
1186 if (ret == IXGBE_SUCCESS)
1187 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1190 ixgbe_release_swfw_semaphore(hw, gssr);
1195 * ixgbe_get_phy_token - Get the token for shared phy access
1196 * @hw: Pointer to hardware structure
1199 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1201 struct ixgbe_hic_phy_token_req token_cmd;
1204 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1205 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1206 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1207 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1208 token_cmd.port_number = hw->bus.lan_id;
1209 token_cmd.command_type = FW_PHY_TOKEN_REQ;
1211 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1213 IXGBE_HI_COMMAND_TIMEOUT,
1217 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1218 return IXGBE_SUCCESS;
1219 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1220 return IXGBE_ERR_FW_RESP_INVALID;
1222 return IXGBE_ERR_TOKEN_RETRY;
1226 * ixgbe_put_phy_token - Put the token for shared phy access
1227 * @hw: Pointer to hardware structure
1230 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1232 struct ixgbe_hic_phy_token_req token_cmd;
1235 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1236 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1237 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1238 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1239 token_cmd.port_number = hw->bus.lan_id;
1240 token_cmd.command_type = FW_PHY_TOKEN_REL;
1242 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1244 IXGBE_HI_COMMAND_TIMEOUT,
1248 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1249 return IXGBE_SUCCESS;
1251 DEBUGOUT("Put PHY Token host interface command failed");
1252 return IXGBE_ERR_FW_RESP_INVALID;
1256 * ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1257 * of the IOSF device
1258 * @hw: pointer to hardware structure
1259 * @reg_addr: 32 bit PHY register to write
1260 * @device_type: 3 bit device type
1261 * @data: Data to write to the register
1263 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1264 u32 device_type, u32 data)
1266 struct ixgbe_hic_internal_phy_req write_cmd;
1268 UNREFERENCED_1PARAMETER(device_type);
1270 memset(&write_cmd, 0, sizeof(write_cmd));
1271 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1272 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1273 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1274 write_cmd.port_number = hw->bus.lan_id;
1275 write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1276 write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1277 write_cmd.write_data = IXGBE_CPU_TO_LE32(data);
1279 status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1281 IXGBE_HI_COMMAND_TIMEOUT, false);
1287 * ixgbe_read_iosf_sb_reg_x550a - Writes a value to specified register
1288 * of the IOSF device.
1289 * @hw: pointer to hardware structure
1290 * @reg_addr: 32 bit PHY register to write
1291 * @device_type: 3 bit device type
1292 * @data: Pointer to read data from the register
1294 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1295 u32 device_type, u32 *data)
1298 struct ixgbe_hic_internal_phy_req cmd;
1299 struct ixgbe_hic_internal_phy_resp rsp;
1302 UNREFERENCED_1PARAMETER(device_type);
1304 memset(&hic, 0, sizeof(hic));
1305 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1306 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1307 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1308 hic.cmd.port_number = hw->bus.lan_id;
1309 hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1310 hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1312 status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1314 IXGBE_HI_COMMAND_TIMEOUT, true);
1316 /* Extract the register value from the response. */
1317 *data = IXGBE_LE32_TO_CPU(hic.rsp.read_data);
1323 * ixgbe_disable_mdd_X550
1324 * @hw: pointer to hardware structure
1326 * Disable malicious driver detection
1328 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1332 DEBUGFUNC("ixgbe_disable_mdd_X550");
1334 /* Disable MDD for TX DMA and interrupt */
1335 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1336 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1337 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1339 /* Disable MDD for RX and interrupt */
1340 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1341 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1342 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1346 * ixgbe_enable_mdd_X550
1347 * @hw: pointer to hardware structure
1349 * Enable malicious driver detection
1351 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1355 DEBUGFUNC("ixgbe_enable_mdd_X550");
1357 /* Enable MDD for TX DMA and interrupt */
1358 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1359 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1360 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1362 /* Enable MDD for RX and interrupt */
1363 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1364 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1365 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1369 * ixgbe_restore_mdd_vf_X550
1370 * @hw: pointer to hardware structure
1373 * Restore VF that was disabled during malicious driver detection event
1375 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1377 u32 idx, reg, num_qs, start_q, bitmask;
1379 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1381 /* Map VF to queues */
1382 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1383 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1384 case IXGBE_MRQC_VMDQRT8TCEN:
1385 num_qs = 8; /* 16 VFs / pools */
1386 bitmask = 0x000000FF;
1388 case IXGBE_MRQC_VMDQRSS32EN:
1389 case IXGBE_MRQC_VMDQRT4TCEN:
1390 num_qs = 4; /* 32 VFs / pools */
1391 bitmask = 0x0000000F;
1393 default: /* 64 VFs / pools */
1395 bitmask = 0x00000003;
1398 start_q = vf * num_qs;
1400 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1403 reg |= (bitmask << (start_q % 32));
1404 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1405 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1409 * ixgbe_mdd_event_X550
1410 * @hw: pointer to hardware structure
1411 * @vf_bitmap: vf bitmap of malicious vfs
1413 * Handle malicious driver detection event.
1415 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1418 u32 i, j, reg, q, shift, vf, idx;
1420 DEBUGFUNC("ixgbe_mdd_event_X550");
1422 /* figure out pool size for mapping to vf's */
1423 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1424 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1425 case IXGBE_MRQC_VMDQRT8TCEN:
1426 shift = 3; /* 16 VFs / pools */
1428 case IXGBE_MRQC_VMDQRSS32EN:
1429 case IXGBE_MRQC_VMDQRT4TCEN:
1430 shift = 2; /* 32 VFs / pools */
1433 shift = 1; /* 64 VFs / pools */
1437 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1438 for (i = 0; i < 4; i++) {
1439 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1440 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1445 /* Get malicious queue */
1446 for (j = 0; j < 32 && wqbr; j++) {
1448 if (!(wqbr & (1 << j)))
1451 /* Get queue from bitmask */
1454 /* Map queue to vf */
1457 /* Set vf bit in vf_bitmap */
1459 vf_bitmap[idx] |= (1 << (vf % 32));
1466 * ixgbe_get_media_type_X550em - Get media type
1467 * @hw: pointer to hardware structure
1469 * Returns the media type (fiber, copper, backplane)
1471 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1473 enum ixgbe_media_type media_type;
1475 DEBUGFUNC("ixgbe_get_media_type_X550em");
1477 /* Detect if there is a copper PHY attached. */
1478 switch (hw->device_id) {
1479 case IXGBE_DEV_ID_X550EM_X_KR:
1480 case IXGBE_DEV_ID_X550EM_X_KX4:
1481 case IXGBE_DEV_ID_X550EM_A_KR:
1482 case IXGBE_DEV_ID_X550EM_A_KR_L:
1483 media_type = ixgbe_media_type_backplane;
1485 case IXGBE_DEV_ID_X550EM_X_SFP:
1486 case IXGBE_DEV_ID_X550EM_A_SFP:
1487 case IXGBE_DEV_ID_X550EM_A_SFP_N:
1488 case IXGBE_DEV_ID_X550EM_A_QSFP:
1489 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1490 media_type = ixgbe_media_type_fiber;
1492 case IXGBE_DEV_ID_X550EM_X_1G_T:
1493 case IXGBE_DEV_ID_X550EM_X_10G_T:
1494 case IXGBE_DEV_ID_X550EM_A_10G_T:
1495 media_type = ixgbe_media_type_copper;
1497 case IXGBE_DEV_ID_X550EM_A_SGMII:
1498 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1499 media_type = ixgbe_media_type_backplane;
1500 hw->phy.type = ixgbe_phy_sgmii;
1502 case IXGBE_DEV_ID_X550EM_A_1G_T:
1503 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1504 media_type = ixgbe_media_type_copper;
1505 hw->phy.type = ixgbe_phy_m88;
1508 media_type = ixgbe_media_type_unknown;
1515 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1516 * @hw: pointer to hardware structure
1517 * @linear: true if SFP module is linear
1519 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1521 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1523 switch (hw->phy.sfp_type) {
1524 case ixgbe_sfp_type_not_present:
1525 return IXGBE_ERR_SFP_NOT_PRESENT;
1526 case ixgbe_sfp_type_da_cu_core0:
1527 case ixgbe_sfp_type_da_cu_core1:
1530 case ixgbe_sfp_type_srlr_core0:
1531 case ixgbe_sfp_type_srlr_core1:
1532 case ixgbe_sfp_type_da_act_lmt_core0:
1533 case ixgbe_sfp_type_da_act_lmt_core1:
1534 case ixgbe_sfp_type_1g_sx_core0:
1535 case ixgbe_sfp_type_1g_sx_core1:
1536 case ixgbe_sfp_type_1g_lx_core0:
1537 case ixgbe_sfp_type_1g_lx_core1:
1540 case ixgbe_sfp_type_unknown:
1541 case ixgbe_sfp_type_1g_cu_core0:
1542 case ixgbe_sfp_type_1g_cu_core1:
1544 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1547 return IXGBE_SUCCESS;
1551 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1552 * @hw: pointer to hardware structure
1554 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1556 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1561 DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1563 status = ixgbe_identify_module_generic(hw);
1565 if (status != IXGBE_SUCCESS)
1568 /* Check if SFP module is supported */
1569 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1575 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1576 * @hw: pointer to hardware structure
1578 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1583 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1585 /* Check if SFP module is supported */
1586 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1588 if (status != IXGBE_SUCCESS)
1591 ixgbe_init_mac_link_ops_X550em(hw);
1592 hw->phy.ops.reset = NULL;
1594 return IXGBE_SUCCESS;
1598 * ixgbe_setup_sgmii - Set up link for sgmii
1599 * @hw: pointer to hardware structure
1601 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1602 bool autoneg_wait_to_complete)
1604 struct ixgbe_mac_info *mac = &hw->mac;
1607 UNREFERENCED_2PARAMETER(speed, autoneg_wait_to_complete);
1609 rc = mac->ops.read_iosf_sb_reg(hw,
1610 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1611 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1615 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1616 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1617 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1618 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1619 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1620 rc = mac->ops.write_iosf_sb_reg(hw,
1621 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1622 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1626 rc = mac->ops.read_iosf_sb_reg(hw,
1627 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1628 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1632 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1633 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1634 rc = mac->ops.write_iosf_sb_reg(hw,
1635 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1636 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1640 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1641 rc = mac->ops.write_iosf_sb_reg(hw,
1642 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1643 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1649 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1650 * @hw: pointer to hardware structure
1652 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1654 struct ixgbe_mac_info *mac = &hw->mac;
1656 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1658 switch (hw->mac.ops.get_media_type(hw)) {
1659 case ixgbe_media_type_fiber:
1660 /* CS4227 does not support autoneg, so disable the laser control
1661 * functions for SFP+ fiber
1663 mac->ops.disable_tx_laser = NULL;
1664 mac->ops.enable_tx_laser = NULL;
1665 mac->ops.flap_tx_laser = NULL;
1666 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1667 mac->ops.set_rate_select_speed =
1668 ixgbe_set_soft_rate_select_speed;
1669 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1670 (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1671 mac->ops.setup_mac_link =
1672 ixgbe_setup_mac_link_sfp_x550a;
1674 mac->ops.setup_mac_link =
1675 ixgbe_setup_mac_link_sfp_x550em;
1677 case ixgbe_media_type_copper:
1678 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1679 mac->ops.check_link = ixgbe_check_link_t_X550em;
1681 case ixgbe_media_type_backplane:
1682 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1683 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1684 mac->ops.setup_link = ixgbe_setup_sgmii;
1692 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1693 * @hw: pointer to hardware structure
1694 * @speed: pointer to link speed
1695 * @autoneg: true when autoneg or autotry is enabled
1697 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1698 ixgbe_link_speed *speed,
1701 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1704 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1706 /* CS4227 SFP must not enable auto-negotiation */
1709 /* Check if 1G SFP module. */
1710 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1711 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1712 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1713 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1714 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1715 return IXGBE_SUCCESS;
1718 /* Link capabilities are based on SFP */
1719 if (hw->phy.multispeed_fiber)
1720 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1721 IXGBE_LINK_SPEED_1GB_FULL;
1723 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1725 switch (hw->phy.type) {
1727 *speed = IXGBE_LINK_SPEED_100_FULL |
1728 IXGBE_LINK_SPEED_1GB_FULL;
1730 case ixgbe_phy_sgmii:
1731 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1734 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1735 IXGBE_LINK_SPEED_1GB_FULL;
1741 return IXGBE_SUCCESS;
1745 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1746 * @hw: pointer to hardware structure
1747 * @lsc: pointer to boolean flag which indicates whether external Base T
1748 * PHY interrupt is lsc
1750 * Determime if external Base T PHY interrupt cause is high temperature
1751 * failure alarm or link status change.
1753 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1754 * failure alarm, else return PHY access status.
1756 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1763 /* Vendor alarm triggered */
1764 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1765 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1768 if (status != IXGBE_SUCCESS ||
1769 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1772 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1773 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1774 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1777 if (status != IXGBE_SUCCESS ||
1778 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1779 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1782 /* Global alarm triggered */
1783 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1784 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1787 if (status != IXGBE_SUCCESS)
1790 /* If high temperature failure, then return over temp error and exit */
1791 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1792 /* power down the PHY in case the PHY FW didn't already */
1793 ixgbe_set_copper_phy_power(hw, false);
1794 return IXGBE_ERR_OVERTEMP;
1795 } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1796 /* device fault alarm triggered */
1797 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1798 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1801 if (status != IXGBE_SUCCESS)
1804 /* if device fault was due to high temp alarm handle and exit */
1805 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1806 /* power down the PHY in case the PHY FW didn't */
1807 ixgbe_set_copper_phy_power(hw, false);
1808 return IXGBE_ERR_OVERTEMP;
1812 /* Vendor alarm 2 triggered */
1813 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1814 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1816 if (status != IXGBE_SUCCESS ||
1817 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1820 /* link connect/disconnect event occurred */
1821 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1822 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1824 if (status != IXGBE_SUCCESS)
1828 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1831 return IXGBE_SUCCESS;
1835 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1836 * @hw: pointer to hardware structure
1838 * Enable link status change and temperature failure alarm for the external
1841 * Returns PHY access status
1843 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1849 /* Clear interrupt flags */
1850 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1852 /* Enable link status change alarm */
1853 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1854 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1856 if (status != IXGBE_SUCCESS)
1859 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1861 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1862 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1864 if (status != IXGBE_SUCCESS)
1867 /* Enable high temperature failure and global fault alarms */
1868 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1869 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1872 if (status != IXGBE_SUCCESS)
1875 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
1876 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
1878 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1879 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1882 if (status != IXGBE_SUCCESS)
1885 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1886 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1887 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1890 if (status != IXGBE_SUCCESS)
1893 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1894 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1896 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1897 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1900 if (status != IXGBE_SUCCESS)
1903 /* Enable chip-wide vendor alarm */
1904 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1905 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1908 if (status != IXGBE_SUCCESS)
1911 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1913 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1914 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1921 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1922 * @hw: pointer to hardware structure
1923 * @speed: link speed
1925 * Configures the integrated KR PHY.
1927 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1928 ixgbe_link_speed speed)
1933 status = hw->mac.ops.read_iosf_sb_reg(hw,
1934 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1935 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1939 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1940 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1941 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1943 /* Advertise 10G support. */
1944 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1945 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1947 /* Advertise 1G support. */
1948 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1949 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1951 /* Restart auto-negotiation. */
1952 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1953 status = hw->mac.ops.write_iosf_sb_reg(hw,
1954 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1955 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1961 * ixgbe_set_master_slave_mode - Set up PHY for master/slave mode
1962 * @hw: pointer to hardware structure
1964 * Must be called while holding the PHY semaphore and token
1966 STATIC s32 ixgbe_set_master_slave_mode(struct ixgbe_hw *hw)
1971 /* Resolve master/slave mode */
1972 rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_M88E1500_1000T_CTRL, 0,
1977 /* load defaults for future use */
1978 if (phy_data & IXGBE_M88E1500_1000T_CTRL_MS_ENABLE) {
1979 if (phy_data & IXGBE_M88E1500_1000T_CTRL_MS_VALUE)
1980 hw->phy.original_ms_type = ixgbe_ms_force_master;
1982 hw->phy.original_ms_type = ixgbe_ms_force_slave;
1984 hw->phy.original_ms_type = ixgbe_ms_auto;
1987 switch (hw->phy.ms_type) {
1988 case ixgbe_ms_force_master:
1989 phy_data |= IXGBE_M88E1500_1000T_CTRL_MS_ENABLE;
1990 phy_data |= IXGBE_M88E1500_1000T_CTRL_MS_VALUE;
1992 case ixgbe_ms_force_slave:
1993 phy_data |= IXGBE_M88E1500_1000T_CTRL_MS_ENABLE;
1994 phy_data &= ~IXGBE_M88E1500_1000T_CTRL_MS_VALUE;
1997 phy_data &= ~IXGBE_M88E1500_1000T_CTRL_MS_ENABLE;
2003 return ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_1000T_CTRL, 0,
2008 * ixgbe_reset_phy_m88_nolock - Reset m88 PHY without locking
2009 * @hw: pointer to hardware structure
2011 * Must be called while holding the PHY semaphore and token
2013 STATIC s32 ixgbe_reset_phy_m88_nolock(struct ixgbe_hw *hw)
2017 rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2021 rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_FIBER_CTRL, 0,
2022 IXGBE_M88E1500_FIBER_CTRL_RESET |
2023 IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2024 IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB);
2028 rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 18);
2032 rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_GEN_CTRL, 0,
2033 IXGBE_M88E1500_GEN_CTRL_RESET |
2034 IXGBE_M88E1500_GEN_CTRL_SGMII_COPPER);
2038 rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2042 rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2043 IXGBE_M88E1500_COPPER_CTRL_RESET |
2044 IXGBE_M88E1500_COPPER_CTRL_AN_EN |
2045 IXGBE_M88E1500_COPPER_CTRL_RESTART_AN |
2046 IXGBE_M88E1500_COPPER_CTRL_FULL_DUPLEX |
2047 IXGBE_M88E1500_COPPER_CTRL_SPEED_MSB);
2050 ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2055 * ixgbe_reset_phy_m88 - Reset m88 PHY
2056 * @hw: pointer to hardware structure
2058 STATIC s32 ixgbe_reset_phy_m88(struct ixgbe_hw *hw)
2060 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2063 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2064 return IXGBE_SUCCESS;
2066 rc = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
2070 rc = ixgbe_reset_phy_m88_nolock(hw);
2072 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2077 * ixgbe_setup_m88 - setup m88 PHY
2078 * @hw: pointer to hardware structure
2080 STATIC s32 ixgbe_setup_m88(struct ixgbe_hw *hw)
2082 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2083 struct ixgbe_phy_info *phy = &hw->phy;
2087 if (phy->reset_disable || ixgbe_check_reset_blocked(hw))
2088 return IXGBE_SUCCESS;
2090 rc = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
2094 rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_M88E1500_PHY_SPEC_CTRL, 0,
2099 /* Enable downshift and setting it to X6 */
2100 phy_data &= ~IXGBE_M88E1500_PSCR_DOWNSHIFT_ENABLE;
2101 phy_data |= IXGBE_M88E1500_PSCR_DOWNSHIFT_6X;
2102 phy_data |= IXGBE_M88E1500_PSCR_DOWNSHIFT_ENABLE;
2103 rc = ixgbe_write_phy_reg_mdi_22(hw,
2104 IXGBE_M88E1500_PHY_SPEC_CTRL, 0,
2109 ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2111 /* Commit the changes */
2112 rc = ixgbe_reset_phy_m88_nolock(hw);
2114 DEBUGOUT("Error committing the PHY changes\n");
2118 rc = ixgbe_set_master_slave_mode(hw);
2120 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2124 ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2125 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2130 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2131 * @hw: pointer to hardware structure
2133 * Read NW_MNG_IF_SEL register and save field values, and check for valid field
2136 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2138 /* Save NW management interface connected on board. This is used
2139 * to determine internal PHY mode.
2141 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2143 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2144 * PHY address. This register field was has only been used for X552.
2146 if (hw->mac.type == ixgbe_mac_X550EM_a &&
2147 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2148 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2149 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2150 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2153 return IXGBE_SUCCESS;
2157 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2158 * @hw: pointer to hardware structure
2160 * Initialize any function pointers that were not able to be
2161 * set during init_shared_code because the PHY/SFP type was
2162 * not known. Perform the SFP init if necessary.
2164 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2166 struct ixgbe_phy_info *phy = &hw->phy;
2169 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2171 hw->mac.ops.set_lan_id(hw);
2173 ixgbe_read_mng_if_sel_x550em(hw);
2175 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2176 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2177 ixgbe_setup_mux_ctl(hw);
2178 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2181 /* Identify the PHY or SFP module */
2182 ret_val = phy->ops.identify(hw);
2183 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
2186 /* Setup function pointers based on detected hardware */
2187 ixgbe_init_mac_link_ops_X550em(hw);
2188 if (phy->sfp_type != ixgbe_sfp_type_unknown)
2189 phy->ops.reset = NULL;
2191 /* Set functions pointers based on phy type */
2192 switch (hw->phy.type) {
2193 case ixgbe_phy_x550em_kx4:
2194 phy->ops.setup_link = NULL;
2195 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2196 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2198 case ixgbe_phy_x550em_kr:
2199 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2200 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2201 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2203 case ixgbe_phy_x550em_ext_t:
2204 /* If internal link mode is XFI, then setup iXFI internal link,
2205 * else setup KR now.
2207 phy->ops.setup_internal_link =
2208 ixgbe_setup_internal_phy_t_x550em;
2210 /* setup SW LPLU only for first revision of X550EM_x */
2211 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2212 !(IXGBE_FUSES0_REV_MASK &
2213 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2214 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2216 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2217 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2219 case ixgbe_phy_sgmii:
2220 phy->ops.setup_link = NULL;
2223 phy->ops.setup_link = ixgbe_setup_m88;
2224 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2225 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2226 phy->ops.reset = ixgbe_reset_phy_m88;
2235 * ixgbe_set_mdio_speed - Set MDIO clock speed
2236 * @hw: pointer to hardware structure
2238 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2242 switch (hw->device_id) {
2243 case IXGBE_DEV_ID_X550EM_X_10G_T:
2244 case IXGBE_DEV_ID_X550EM_A_SGMII:
2245 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2246 case IXGBE_DEV_ID_X550EM_A_1G_T:
2247 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2248 case IXGBE_DEV_ID_X550EM_A_10G_T:
2249 case IXGBE_DEV_ID_X550EM_A_SFP:
2250 case IXGBE_DEV_ID_X550EM_A_QSFP:
2251 /* Config MDIO clock speed before the first MDIO PHY access */
2252 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2253 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2254 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2262 * ixgbe_reset_hw_X550em - Perform hardware reset
2263 * @hw: pointer to hardware structure
2265 * Resets the hardware by resetting the transmit and receive units, masks
2266 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2269 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2271 ixgbe_link_speed link_speed;
2275 bool link_up = false;
2277 DEBUGFUNC("ixgbe_reset_hw_X550em");
2279 /* Call adapter stop to disable Tx/Rx and clear interrupts */
2280 status = hw->mac.ops.stop_adapter(hw);
2281 if (status != IXGBE_SUCCESS)
2284 /* flush pending Tx transactions */
2285 ixgbe_clear_tx_pending(hw);
2287 ixgbe_set_mdio_speed(hw);
2289 /* PHY ops must be identified and initialized prior to reset */
2290 status = hw->phy.ops.init(hw);
2292 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2295 /* start the external PHY */
2296 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2297 status = ixgbe_init_ext_t_x550em(hw);
2302 /* Setup SFP module if there is one present. */
2303 if (hw->phy.sfp_setup_needed) {
2304 status = hw->mac.ops.setup_sfp(hw);
2305 hw->phy.sfp_setup_needed = false;
2308 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2312 if (!hw->phy.reset_disable && hw->phy.ops.reset)
2313 hw->phy.ops.reset(hw);
2316 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
2317 * If link reset is used when link is up, it might reset the PHY when
2318 * mng is using it. If link is down or the flag to force full link
2319 * reset is set, then perform link reset.
2321 ctrl = IXGBE_CTRL_LNK_RST;
2322 if (!hw->force_full_reset) {
2323 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2325 ctrl = IXGBE_CTRL_RST;
2328 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2329 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2330 IXGBE_WRITE_FLUSH(hw);
2332 /* Poll for reset bit to self-clear meaning reset is complete */
2333 for (i = 0; i < 10; i++) {
2335 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2336 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2340 if (ctrl & IXGBE_CTRL_RST_MASK) {
2341 status = IXGBE_ERR_RESET_FAILED;
2342 DEBUGOUT("Reset polling failed to complete.\n");
2347 /* Double resets are required for recovery from certain error
2348 * conditions. Between resets, it is necessary to stall to
2349 * allow time for any pending HW events to complete.
2351 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2352 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2356 /* Store the permanent mac address */
2357 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2359 /* Store MAC address from RAR0, clear receive address registers, and
2360 * clear the multicast table. Also reset num_rar_entries to 128,
2361 * since we modify this value when programming the SAN MAC address.
2363 hw->mac.num_rar_entries = 128;
2364 hw->mac.ops.init_rx_addrs(hw);
2366 ixgbe_set_mdio_speed(hw);
2368 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2369 ixgbe_setup_mux_ctl(hw);
2375 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2376 * @hw: pointer to hardware structure
2378 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2383 status = hw->phy.ops.read_reg(hw,
2384 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2385 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2388 if (status != IXGBE_SUCCESS)
2391 /* If PHY FW reset completed bit is set then this is the first
2392 * SW instance after a power on so the PHY FW must be un-stalled.
2394 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2395 status = hw->phy.ops.read_reg(hw,
2396 IXGBE_MDIO_GLOBAL_RES_PR_10,
2397 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2400 if (status != IXGBE_SUCCESS)
2403 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2405 status = hw->phy.ops.write_reg(hw,
2406 IXGBE_MDIO_GLOBAL_RES_PR_10,
2407 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2410 if (status != IXGBE_SUCCESS)
2418 * ixgbe_setup_kr_x550em - Configure the KR PHY.
2419 * @hw: pointer to hardware structure
2421 * Configures the integrated KR PHY for X550EM_x.
2423 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2425 if (hw->mac.type != ixgbe_mac_X550EM_x)
2426 return IXGBE_SUCCESS;
2428 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2432 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2433 * @hw: pointer to hardware structure
2435 * Configure the external PHY and the integrated KR PHY for SFP support.
2437 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2438 ixgbe_link_speed speed,
2439 bool autoneg_wait_to_complete)
2442 u16 reg_slice, reg_val;
2443 bool setup_linear = false;
2444 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2446 /* Check if SFP module is supported and linear */
2447 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2449 /* If no SFP module present, then return success. Return success since
2450 * there is no reason to configure CS4227 and SFP not present error is
2451 * not excepted in the setup MAC link flow.
2453 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2454 return IXGBE_SUCCESS;
2456 if (ret_val != IXGBE_SUCCESS)
2459 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2460 /* Configure CS4227 LINE side to 10G SR. */
2461 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
2462 (hw->bus.lan_id << 12);
2463 reg_val = IXGBE_CS4227_SPEED_10G;
2464 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2467 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2468 (hw->bus.lan_id << 12);
2469 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2470 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2473 /* Configure CS4227 for HOST connection rate then type. */
2474 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
2475 (hw->bus.lan_id << 12);
2476 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
2477 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
2478 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2481 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
2482 (hw->bus.lan_id << 12);
2484 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2486 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2487 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2490 /* Setup XFI internal link. */
2491 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2493 /* Configure internal PHY for KR/KX. */
2494 ixgbe_setup_kr_speed_x550em(hw, speed);
2496 /* Configure CS4227 LINE side to proper mode. */
2497 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2498 (hw->bus.lan_id << 12);
2500 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2502 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2503 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2510 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2511 * @hw: pointer to hardware structure
2513 * Configure the the integrated PHY for SFP support.
2515 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2516 ixgbe_link_speed speed,
2517 bool autoneg_wait_to_complete)
2521 bool setup_linear = false;
2522 u32 reg_slice, reg_phy_int, slice_offset;
2524 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2526 /* Check if SFP module is supported and linear */
2527 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2529 /* If no SFP module present, then return success. Return success since
2530 * SFP not present error is not excepted in the setup MAC link flow.
2532 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2533 return IXGBE_SUCCESS;
2535 if (ret_val != IXGBE_SUCCESS)
2538 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2539 /* Configure internal PHY for native SFI */
2540 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2541 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2542 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int);
2544 if (ret_val != IXGBE_SUCCESS)
2548 reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LIMITING;
2549 reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LINEAR;
2551 reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LIMITING;
2552 reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LINEAR;
2555 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2556 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2557 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2559 if (ret_val != IXGBE_SUCCESS)
2562 /* Setup XFI/SFI internal link. */
2563 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2565 /* Configure internal PHY for KR/KX. */
2566 ixgbe_setup_kr_speed_x550em(hw, speed);
2568 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2570 DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2571 return IXGBE_ERR_PHY_ADDR_INVALID;
2574 /* Get external PHY device id */
2575 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_GLOBAL_ID_MSB,
2576 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
2578 if (ret_val != IXGBE_SUCCESS)
2581 /* When configuring quad port CS4223, the MAC instance is part
2582 * of the slice offset.
2584 if (reg_phy_ext == IXGBE_CS4223_PHY_ID)
2585 slice_offset = (hw->bus.lan_id +
2586 (hw->bus.instance_id << 1)) << 12;
2588 slice_offset = hw->bus.lan_id << 12;
2590 /* Configure CS4227/CS4223 LINE side to proper mode. */
2591 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2593 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2595 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2596 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2597 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2603 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2604 * @hw: pointer to hardware structure
2606 * iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2608 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2613 /* Disable training protocol FSM. */
2614 status = ixgbe_read_iosf_sb_reg_x550(hw,
2615 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2616 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2617 if (status != IXGBE_SUCCESS)
2619 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2620 status = ixgbe_write_iosf_sb_reg_x550(hw,
2621 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2622 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2623 if (status != IXGBE_SUCCESS)
2626 /* Disable Flex from training TXFFE. */
2627 status = ixgbe_read_iosf_sb_reg_x550(hw,
2628 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2629 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2630 if (status != IXGBE_SUCCESS)
2632 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2633 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2634 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2635 status = ixgbe_write_iosf_sb_reg_x550(hw,
2636 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2637 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2638 if (status != IXGBE_SUCCESS)
2640 status = ixgbe_read_iosf_sb_reg_x550(hw,
2641 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2642 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2643 if (status != IXGBE_SUCCESS)
2645 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2646 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2647 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2648 status = ixgbe_write_iosf_sb_reg_x550(hw,
2649 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2650 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2651 if (status != IXGBE_SUCCESS)
2654 /* Enable override for coefficients. */
2655 status = ixgbe_read_iosf_sb_reg_x550(hw,
2656 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2657 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2658 if (status != IXGBE_SUCCESS)
2660 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2661 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2662 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2663 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2664 status = ixgbe_write_iosf_sb_reg_x550(hw,
2665 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2666 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2671 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2672 * @hw: pointer to hardware structure
2673 * @speed: the link speed to force
2675 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
2676 * internal and external PHY at a specific speed, without autonegotiation.
2678 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2683 /* Disable AN and force speed to 10G Serial. */
2684 status = ixgbe_read_iosf_sb_reg_x550(hw,
2685 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2686 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2687 if (status != IXGBE_SUCCESS)
2690 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2691 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2693 /* Select forced link speed for internal PHY. */
2695 case IXGBE_LINK_SPEED_10GB_FULL:
2696 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2698 case IXGBE_LINK_SPEED_1GB_FULL:
2699 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2702 /* Other link speeds are not supported by internal KR PHY. */
2703 return IXGBE_ERR_LINK_SETUP;
2706 status = ixgbe_write_iosf_sb_reg_x550(hw,
2707 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2708 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2709 if (status != IXGBE_SUCCESS)
2712 /* Additional configuration needed for x550em_x */
2713 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2714 status = ixgbe_setup_ixfi_x550em_x(hw);
2715 if (status != IXGBE_SUCCESS)
2719 /* Toggle port SW reset by AN reset. */
2720 status = ixgbe_read_iosf_sb_reg_x550(hw,
2721 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2722 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2723 if (status != IXGBE_SUCCESS)
2725 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2726 status = ixgbe_write_iosf_sb_reg_x550(hw,
2727 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2728 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2734 * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2735 * @hw: address of hardware structure
2736 * @link_up: address of boolean to indicate link status
2738 * Returns error code if unable to get link status.
2740 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2747 /* read this twice back to back to indicate current status */
2748 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2749 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2751 if (ret != IXGBE_SUCCESS)
2754 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2755 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2757 if (ret != IXGBE_SUCCESS)
2760 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2762 return IXGBE_SUCCESS;
2766 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2767 * @hw: point to hardware structure
2769 * Configures the link between the integrated KR PHY and the external X557 PHY
2770 * The driver will call this function when it gets a link status change
2771 * interrupt from the X557 PHY. This function configures the link speed
2772 * between the PHYs to match the link speed of the BASE-T link.
2774 * A return of a non-zero value indicates an error, and the base driver should
2775 * not report link up.
2777 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2779 ixgbe_link_speed force_speed;
2784 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2785 return IXGBE_ERR_CONFIG;
2787 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2788 /* If link is down, there is no setup necessary so return */
2789 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2790 if (status != IXGBE_SUCCESS)
2794 return IXGBE_SUCCESS;
2796 status = hw->phy.ops.read_reg(hw,
2797 IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2798 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2800 if (status != IXGBE_SUCCESS)
2803 /* If link is still down - no setup is required so return */
2804 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2805 if (status != IXGBE_SUCCESS)
2808 return IXGBE_SUCCESS;
2810 /* clear everything but the speed and duplex bits */
2811 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2814 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2815 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2817 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2818 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2821 /* Internal PHY does not support anything else */
2822 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2825 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2827 speed = IXGBE_LINK_SPEED_10GB_FULL |
2828 IXGBE_LINK_SPEED_1GB_FULL;
2829 return ixgbe_setup_kr_speed_x550em(hw, speed);
2834 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
2835 * @hw: pointer to hardware structure
2837 * Configures the integrated KR PHY to use internal loopback mode.
2839 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
2844 /* Disable AN and force speed to 10G Serial. */
2845 status = hw->mac.ops.read_iosf_sb_reg(hw,
2846 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2847 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2848 if (status != IXGBE_SUCCESS)
2850 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2851 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2852 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2853 status = hw->mac.ops.write_iosf_sb_reg(hw,
2854 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2855 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2856 if (status != IXGBE_SUCCESS)
2859 /* Set near-end loopback clocks. */
2860 status = hw->mac.ops.read_iosf_sb_reg(hw,
2861 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2862 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2863 if (status != IXGBE_SUCCESS)
2865 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2866 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2867 status = hw->mac.ops.write_iosf_sb_reg(hw,
2868 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2869 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2870 if (status != IXGBE_SUCCESS)
2873 /* Set loopback enable. */
2874 status = hw->mac.ops.read_iosf_sb_reg(hw,
2875 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2876 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2877 if (status != IXGBE_SUCCESS)
2879 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2880 status = hw->mac.ops.write_iosf_sb_reg(hw,
2881 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2882 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2883 if (status != IXGBE_SUCCESS)
2886 /* Training bypass. */
2887 status = hw->mac.ops.read_iosf_sb_reg(hw,
2888 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2889 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2890 if (status != IXGBE_SUCCESS)
2892 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2893 status = hw->mac.ops.write_iosf_sb_reg(hw,
2894 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2895 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2901 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2902 * assuming that the semaphore is already obtained.
2903 * @hw: pointer to hardware structure
2904 * @offset: offset of word in the EEPROM to read
2905 * @data: word read from the EEPROM
2907 * Reads a 16 bit word from the EEPROM using the hostif.
2909 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2913 struct ixgbe_hic_read_shadow_ram buffer;
2915 DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2916 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2917 buffer.hdr.req.buf_lenh = 0;
2918 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2919 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2921 /* convert offset from words to bytes */
2922 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2924 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2926 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2928 IXGBE_HI_COMMAND_TIMEOUT, false);
2933 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2934 FW_NVM_DATA_OFFSET);
2940 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2941 * @hw: pointer to hardware structure
2942 * @offset: offset of word in the EEPROM to read
2943 * @data: word read from the EEPROM
2945 * Reads a 16 bit word from the EEPROM using the hostif.
2947 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2950 s32 status = IXGBE_SUCCESS;
2952 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2954 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2956 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2957 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2959 status = IXGBE_ERR_SWFW_SYNC;
2966 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2967 * @hw: pointer to hardware structure
2968 * @offset: offset of word in the EEPROM to read
2969 * @words: number of words
2970 * @data: word(s) read from the EEPROM
2972 * Reads a 16 bit word(s) from the EEPROM using the hostif.
2974 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2975 u16 offset, u16 words, u16 *data)
2977 struct ixgbe_hic_read_shadow_ram buffer;
2978 u32 current_word = 0;
2983 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2985 /* Take semaphore for the entire operation. */
2986 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2988 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2992 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2993 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2995 words_to_read = words;
2997 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2998 buffer.hdr.req.buf_lenh = 0;
2999 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3000 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3002 /* convert offset from words to bytes */
3003 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3004 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3006 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3008 IXGBE_HI_COMMAND_TIMEOUT,
3012 DEBUGOUT("Host interface command failed\n");
3016 for (i = 0; i < words_to_read; i++) {
3017 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3019 u32 value = IXGBE_READ_REG(hw, reg);
3021 data[current_word] = (u16)(value & 0xffff);
3024 if (i < words_to_read) {
3026 data[current_word] = (u16)(value & 0xffff);
3030 words -= words_to_read;
3034 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3039 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3040 * @hw: pointer to hardware structure
3041 * @offset: offset of word in the EEPROM to write
3042 * @data: word write to the EEPROM
3044 * Write a 16 bit word to the EEPROM using the hostif.
3046 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3050 struct ixgbe_hic_write_shadow_ram buffer;
3052 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3054 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3055 buffer.hdr.req.buf_lenh = 0;
3056 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3057 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3060 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3062 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3064 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3066 IXGBE_HI_COMMAND_TIMEOUT, false);
3072 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3073 * @hw: pointer to hardware structure
3074 * @offset: offset of word in the EEPROM to write
3075 * @data: word write to the EEPROM
3077 * Write a 16 bit word to the EEPROM using the hostif.
3079 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3082 s32 status = IXGBE_SUCCESS;
3084 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3086 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3088 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3089 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3091 DEBUGOUT("write ee hostif failed to get semaphore");
3092 status = IXGBE_ERR_SWFW_SYNC;
3099 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3100 * @hw: pointer to hardware structure
3101 * @offset: offset of word in the EEPROM to write
3102 * @words: number of words
3103 * @data: word(s) write to the EEPROM
3105 * Write a 16 bit word(s) to the EEPROM using the hostif.
3107 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3108 u16 offset, u16 words, u16 *data)
3110 s32 status = IXGBE_SUCCESS;
3113 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3115 /* Take semaphore for the entire operation. */
3116 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3117 if (status != IXGBE_SUCCESS) {
3118 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3122 for (i = 0; i < words; i++) {
3123 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3126 if (status != IXGBE_SUCCESS) {
3127 DEBUGOUT("Eeprom buffered write failed\n");
3132 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3139 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3140 * @hw: pointer to hardware structure
3141 * @ptr: pointer offset in eeprom
3142 * @size: size of section pointed by ptr, if 0 first word will be used as size
3143 * @csum: address of checksum to update
3145 * Returns error status for any failure
3147 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3148 u16 size, u16 *csum, u16 *buffer,
3153 u16 length, bufsz, i, start;
3156 bufsz = sizeof(buf) / sizeof(buf[0]);
3158 /* Read a chunk at the pointer location */
3160 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3162 DEBUGOUT("Failed to read EEPROM image\n");
3167 if (buffer_size < ptr)
3168 return IXGBE_ERR_PARAM;
3169 local_buffer = &buffer[ptr];
3177 length = local_buffer[0];
3179 /* Skip pointer section if length is invalid. */
3180 if (length == 0xFFFF || length == 0 ||
3181 (ptr + length) >= hw->eeprom.word_size)
3182 return IXGBE_SUCCESS;
3185 if (buffer && ((u32)start + (u32)length > buffer_size))
3186 return IXGBE_ERR_PARAM;
3188 for (i = start; length; i++, length--) {
3189 if (i == bufsz && !buffer) {
3195 /* Read a chunk at the pointer location */
3196 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3199 DEBUGOUT("Failed to read EEPROM image\n");
3203 *csum += local_buffer[i];
3205 return IXGBE_SUCCESS;
3209 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3210 * @hw: pointer to hardware structure
3211 * @buffer: pointer to buffer containing calculated checksum
3212 * @buffer_size: size of buffer
3214 * Returns a negative error code on error, or the 16-bit checksum
3216 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3218 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3222 u16 pointer, i, size;
3224 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3226 hw->eeprom.ops.init_params(hw);
3229 /* Read pointer area */
3230 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3231 IXGBE_EEPROM_LAST_WORD + 1,
3234 DEBUGOUT("Failed to read EEPROM image\n");
3237 local_buffer = eeprom_ptrs;
3239 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3240 return IXGBE_ERR_PARAM;
3241 local_buffer = buffer;
3245 * For X550 hardware include 0x0-0x41 in the checksum, skip the
3246 * checksum word itself
3248 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3249 if (i != IXGBE_EEPROM_CHECKSUM)
3250 checksum += local_buffer[i];
3253 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
3254 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3256 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3257 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3260 pointer = local_buffer[i];
3262 /* Skip pointer section if the pointer is invalid. */
3263 if (pointer == 0xFFFF || pointer == 0 ||
3264 pointer >= hw->eeprom.word_size)
3268 case IXGBE_PCIE_GENERAL_PTR:
3269 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3271 case IXGBE_PCIE_CONFIG0_PTR:
3272 case IXGBE_PCIE_CONFIG1_PTR:
3273 size = IXGBE_PCIE_CONFIG_SIZE;
3280 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3281 buffer, buffer_size);
3286 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3288 return (s32)checksum;
3292 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3293 * @hw: pointer to hardware structure
3295 * Returns a negative error code on error, or the 16-bit checksum
3297 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3299 return ixgbe_calc_checksum_X550(hw, NULL, 0);
3303 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3304 * @hw: pointer to hardware structure
3305 * @checksum_val: calculated checksum
3307 * Performs checksum calculation and validates the EEPROM checksum. If the
3308 * caller does not need checksum_val, the value can be NULL.
3310 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3314 u16 read_checksum = 0;
3316 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3318 /* Read the first word from the EEPROM. If this times out or fails, do
3319 * not continue or we could be in for a very long wait while every
3322 status = hw->eeprom.ops.read(hw, 0, &checksum);
3324 DEBUGOUT("EEPROM read failed\n");
3328 status = hw->eeprom.ops.calc_checksum(hw);
3332 checksum = (u16)(status & 0xffff);
3334 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3339 /* Verify read checksum from EEPROM is the same as
3340 * calculated checksum
3342 if (read_checksum != checksum) {
3343 status = IXGBE_ERR_EEPROM_CHECKSUM;
3344 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3345 "Invalid EEPROM checksum");
3348 /* If the user cares, return the calculated checksum */
3350 *checksum_val = checksum;
3356 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3357 * @hw: pointer to hardware structure
3359 * After writing EEPROM to shadow RAM using EEWR register, software calculates
3360 * checksum and updates the EEPROM and instructs the hardware to update
3363 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3368 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3370 /* Read the first word from the EEPROM. If this times out or fails, do
3371 * not continue or we could be in for a very long wait while every
3374 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3376 DEBUGOUT("EEPROM read failed\n");
3380 status = ixgbe_calc_eeprom_checksum_X550(hw);
3384 checksum = (u16)(status & 0xffff);
3386 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3391 status = ixgbe_update_flash_X550(hw);
3397 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3398 * @hw: pointer to hardware structure
3400 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3402 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3404 s32 status = IXGBE_SUCCESS;
3405 union ixgbe_hic_hdr2 buffer;
3407 DEBUGFUNC("ixgbe_update_flash_X550");
3409 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3410 buffer.req.buf_lenh = 0;
3411 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3412 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3414 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3416 IXGBE_HI_COMMAND_TIMEOUT, false);
3422 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3423 * @hw: pointer to hardware structure
3425 * Determines physical layer capabilities of the current configuration.
3427 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3429 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3430 u16 ext_ability = 0;
3432 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3434 hw->phy.ops.identify(hw);
3436 switch (hw->phy.type) {
3437 case ixgbe_phy_x550em_kr:
3438 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3439 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3441 case ixgbe_phy_x550em_kx4:
3442 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3443 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3445 case ixgbe_phy_x550em_ext_t:
3446 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3447 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3449 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3450 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3451 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3452 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3458 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3459 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3461 return physical_layer;
3465 * ixgbe_get_bus_info_x550em - Set PCI bus info
3466 * @hw: pointer to hardware structure
3468 * Sets bus link width and speed to unknown because X550em is
3471 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3474 DEBUGFUNC("ixgbe_get_bus_info_x550em");
3476 hw->bus.width = ixgbe_bus_width_unknown;
3477 hw->bus.speed = ixgbe_bus_speed_unknown;
3479 hw->mac.ops.set_lan_id(hw);
3481 return IXGBE_SUCCESS;
3485 * ixgbe_disable_rx_x550 - Disable RX unit
3487 * Enables the Rx DMA unit for x550
3489 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3491 u32 rxctrl, pfdtxgswc;
3493 struct ixgbe_hic_disable_rxen fw_cmd;
3495 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3497 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3498 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3499 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3500 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3501 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3502 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3503 hw->mac.set_lben = true;
3505 hw->mac.set_lben = false;
3508 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3509 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3510 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3511 fw_cmd.port_number = (u8)hw->bus.lan_id;
3513 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3514 sizeof(struct ixgbe_hic_disable_rxen),
3515 IXGBE_HI_COMMAND_TIMEOUT, true);
3517 /* If we fail - disable RX using register write */
3519 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3520 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3521 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3522 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3529 * ixgbe_enter_lplu_x550em - Transition to low power states
3530 * @hw: pointer to hardware structure
3532 * Configures Low Power Link Up on transition to low power states
3533 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3534 * X557 PHY immediately prior to entering LPLU.
3536 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3538 u16 an_10g_cntl_reg, autoneg_reg, speed;
3540 ixgbe_link_speed lcd_speed;
3544 /* SW LPLU not required on later HW revisions. */
3545 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3546 (IXGBE_FUSES0_REV_MASK &
3547 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3548 return IXGBE_SUCCESS;
3550 /* If blocked by MNG FW, then don't restart AN */
3551 if (ixgbe_check_reset_blocked(hw))
3552 return IXGBE_SUCCESS;
3554 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3555 if (status != IXGBE_SUCCESS)
3558 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3560 if (status != IXGBE_SUCCESS)
3563 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3564 * disabled, then force link down by entering low power mode.
3566 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3567 !(hw->wol_enabled || ixgbe_mng_present(hw)))
3568 return ixgbe_set_copper_phy_power(hw, FALSE);
3571 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3573 if (status != IXGBE_SUCCESS)
3576 /* If no valid LCD link speed, then force link down and exit. */
3577 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3578 return ixgbe_set_copper_phy_power(hw, FALSE);
3580 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3581 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3584 if (status != IXGBE_SUCCESS)
3587 /* If no link now, speed is invalid so take link down */
3588 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3589 if (status != IXGBE_SUCCESS)
3590 return ixgbe_set_copper_phy_power(hw, false);
3592 /* clear everything but the speed bits */
3593 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3595 /* If current speed is already LCD, then exit. */
3596 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3597 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3598 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3599 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3602 /* Clear AN completed indication */
3603 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3604 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3607 if (status != IXGBE_SUCCESS)
3610 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3611 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3614 if (status != IXGBE_SUCCESS)
3617 status = hw->phy.ops.read_reg(hw,
3618 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3619 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3622 if (status != IXGBE_SUCCESS)
3625 save_autoneg = hw->phy.autoneg_advertised;
3627 /* Setup link at least common link speed */
3628 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3630 /* restore autoneg from before setting lplu speed */
3631 hw->phy.autoneg_advertised = save_autoneg;
3637 * ixgbe_get_lcd_x550em - Determine lowest common denominator
3638 * @hw: pointer to hardware structure
3639 * @lcd_speed: pointer to lowest common link speed
3641 * Determine lowest common link speed with link partner.
3643 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3647 u16 word = hw->eeprom.ctrl_word_3;
3649 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3651 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3652 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3655 if (status != IXGBE_SUCCESS)
3658 /* If link partner advertised 1G, return 1G */
3659 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3660 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3664 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3665 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3666 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3669 /* Link partner not capable of lower speeds, return 10G */
3670 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3675 * ixgbe_setup_fc_X550em - Set up flow control
3676 * @hw: pointer to hardware structure
3678 * Called at init time to set up flow control.
3680 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3682 s32 ret_val = IXGBE_SUCCESS;
3683 u32 pause, asm_dir, reg_val;
3685 DEBUGFUNC("ixgbe_setup_fc_X550em");
3687 /* Validate the requested mode */
3688 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3689 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3690 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3691 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3695 /* 10gig parts do not have a word in the EEPROM to determine the
3696 * default flow control setting, so we explicitly set it to full.
3698 if (hw->fc.requested_mode == ixgbe_fc_default)
3699 hw->fc.requested_mode = ixgbe_fc_full;
3701 /* Determine PAUSE and ASM_DIR bits. */
3702 switch (hw->fc.requested_mode) {
3707 case ixgbe_fc_tx_pause:
3711 case ixgbe_fc_rx_pause:
3712 /* Rx Flow control is enabled and Tx Flow control is
3713 * disabled by software override. Since there really
3714 * isn't a way to advertise that we are capable of RX
3715 * Pause ONLY, we will advertise that we support both
3716 * symmetric and asymmetric Rx PAUSE, as such we fall
3717 * through to the fc_full statement. Later, we will
3718 * disable the adapter's ability to send PAUSE frames.
3725 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3726 "Flow control param set incorrectly\n");
3727 ret_val = IXGBE_ERR_CONFIG;
3731 switch (hw->device_id) {
3732 case IXGBE_DEV_ID_X550EM_X_KR:
3733 case IXGBE_DEV_ID_X550EM_A_KR:
3734 case IXGBE_DEV_ID_X550EM_A_KR_L:
3735 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
3736 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3737 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3738 if (ret_val != IXGBE_SUCCESS)
3740 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3741 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3743 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3745 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3746 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
3747 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3748 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3750 /* This device does not fully support AN. */
3751 hw->fc.disable_fc_autoneg = true;
3762 * ixgbe_set_mux - Set mux for port 1 access with CS4227
3763 * @hw: pointer to hardware structure
3764 * @state: set mux if 1, clear if 0
3766 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
3770 if (!hw->bus.lan_id)
3772 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3774 esdp |= IXGBE_ESDP_SDP1;
3776 esdp &= ~IXGBE_ESDP_SDP1;
3777 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
3778 IXGBE_WRITE_FLUSH(hw);
3782 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
3783 * @hw: pointer to hardware structure
3784 * @mask: Mask to specify which semaphore to acquire
3786 * Acquires the SWFW semaphore and sets the I2C MUX
3788 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3792 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
3794 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
3798 if (mask & IXGBE_GSSR_I2C_MASK)
3799 ixgbe_set_mux(hw, 1);
3801 return IXGBE_SUCCESS;
3805 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
3806 * @hw: pointer to hardware structure
3807 * @mask: Mask to specify which semaphore to release
3809 * Releases the SWFW semaphore and sets the I2C MUX
3811 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3813 DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
3815 if (mask & IXGBE_GSSR_I2C_MASK)
3816 ixgbe_set_mux(hw, 0);
3818 ixgbe_release_swfw_sync_X540(hw, mask);
3822 * ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
3823 * @hw: pointer to hardware structure
3824 * @mask: Mask to specify which semaphore to acquire
3826 * Acquires the SWFW semaphore and get the shared phy token as needed
3828 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
3830 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3831 int retries = FW_PHY_TOKEN_RETRIES;
3832 s32 status = IXGBE_SUCCESS;
3834 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
3837 status = IXGBE_SUCCESS;
3839 status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
3842 if (!(mask & IXGBE_GSSR_TOKEN_SM))
3843 return IXGBE_SUCCESS;
3845 status = ixgbe_get_phy_token(hw);
3846 if (status == IXGBE_SUCCESS)
3847 return IXGBE_SUCCESS;
3850 ixgbe_release_swfw_sync_X540(hw, hmask);
3851 if (status != IXGBE_ERR_TOKEN_RETRY)
3853 msec_delay(FW_PHY_TOKEN_DELAY);
3860 * ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
3861 * @hw: pointer to hardware structure
3862 * @mask: Mask to specify which semaphore to release
3864 * Releases the SWFW semaphore and puts the shared phy token as needed
3866 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
3868 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3870 DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
3872 if (mask & IXGBE_GSSR_TOKEN_SM)
3873 ixgbe_put_phy_token(hw);
3876 ixgbe_release_swfw_sync_X540(hw, hmask);
3880 * ixgbe_read_phy_reg_x550a - Reads specified PHY register
3881 * @hw: pointer to hardware structure
3882 * @reg_addr: 32 bit address of PHY register to read
3883 * @phy_data: Pointer to read data from PHY register
3885 * Reads a value from a specified PHY register using the SWFW lock and PHY
3886 * Token. The PHY Token is needed since the MDIO is shared between to MAC
3889 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
3890 u32 device_type, u16 *phy_data)
3893 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
3895 DEBUGFUNC("ixgbe_read_phy_reg_x550a");
3897 if (hw->mac.ops.acquire_swfw_sync(hw, mask))
3898 return IXGBE_ERR_SWFW_SYNC;
3900 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
3902 hw->mac.ops.release_swfw_sync(hw, mask);
3908 * ixgbe_write_phy_reg_x550a - Writes specified PHY register
3909 * @hw: pointer to hardware structure
3910 * @reg_addr: 32 bit PHY register to write
3911 * @device_type: 5 bit device type
3912 * @phy_data: Data to write to the PHY register
3914 * Writes a value to specified PHY register using the SWFW lock and PHY Token.
3915 * The PHY Token is needed since the MDIO is shared between to MAC instances.
3917 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
3918 u32 device_type, u16 phy_data)
3921 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
3923 DEBUGFUNC("ixgbe_write_phy_reg_x550a");
3925 if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
3926 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
3928 hw->mac.ops.release_swfw_sync(hw, mask);
3930 status = IXGBE_ERR_SWFW_SYNC;
3937 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
3938 * @hw: pointer to hardware structure
3940 * Handle external Base T PHY interrupt. If high temperature
3941 * failure alarm then return error, else if link status change
3942 * then setup internal/external PHY link
3944 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
3945 * failure alarm, else return PHY access status.
3947 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
3952 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
3954 if (status != IXGBE_SUCCESS)
3958 return ixgbe_setup_internal_phy(hw);
3960 return IXGBE_SUCCESS;
3964 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
3965 * @hw: pointer to hardware structure
3966 * @speed: new link speed
3967 * @autoneg_wait_to_complete: true when waiting for completion is needed
3969 * Setup internal/external PHY link speed based on link speed, then set
3970 * external PHY auto advertised link speed.
3972 * Returns error status for any failure
3974 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
3975 ixgbe_link_speed speed,
3976 bool autoneg_wait_to_complete)
3979 ixgbe_link_speed force_speed;
3981 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
3983 /* Setup internal/external PHY link speed to iXFI (10G), unless
3984 * only 1G is auto advertised then setup KX link.
3986 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
3987 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3989 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3991 /* If internal link mode is XFI, then setup XFI internal link. */
3992 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3993 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
3995 if (status != IXGBE_SUCCESS)
3999 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4003 * ixgbe_check_link_t_X550em - Determine link and speed status
4004 * @hw: pointer to hardware structure
4005 * @speed: pointer to link speed
4006 * @link_up: true when link is up
4007 * @link_up_wait_to_complete: bool used to wait for link up or not
4009 * Check that both the MAC and X557 external PHY have link.
4011 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4012 bool *link_up, bool link_up_wait_to_complete)
4017 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4018 return IXGBE_ERR_CONFIG;
4020 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4021 link_up_wait_to_complete);
4023 /* If check link fails or MAC link is not up, then return */
4024 if (status != IXGBE_SUCCESS || !(*link_up))
4027 /* MAC link is up, so check external PHY link.
4028 * Read this twice back to back to indicate current status.
4030 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4031 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4034 if (status != IXGBE_SUCCESS)
4037 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4038 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4041 if (status != IXGBE_SUCCESS)
4044 /* If external PHY link is not up, then indicate link not up */
4045 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4048 return IXGBE_SUCCESS;
4052 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4053 * @hw: pointer to hardware structure
4055 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4059 status = ixgbe_reset_phy_generic(hw);
4061 if (status != IXGBE_SUCCESS)
4064 /* Configure Link Status Alarm and Temperature Threshold interrupts */
4065 return ixgbe_enable_lasi_ext_t_x550em(hw);
4069 * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4070 * @hw: pointer to hardware structure
4071 * @led_idx: led number to turn on
4073 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4077 DEBUGFUNC("ixgbe_led_on_t_X550em");
4079 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4080 return IXGBE_ERR_PARAM;
4082 /* To turn on the LED, set mode to ON. */
4083 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4084 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4085 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4086 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4087 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4089 return IXGBE_SUCCESS;
4093 * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4094 * @hw: pointer to hardware structure
4095 * @led_idx: led number to turn off
4097 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4101 DEBUGFUNC("ixgbe_led_off_t_X550em");
4103 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4104 return IXGBE_ERR_PARAM;
4106 /* To turn on the LED, set mode to ON. */
4107 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4108 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4109 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4110 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4111 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4113 return IXGBE_SUCCESS;