1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
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16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
44 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw);
47 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
48 * @hw: pointer to hardware structure
50 * Initialize the function pointers and assign the MAC type for X550.
51 * Does not touch the hardware.
53 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
55 struct ixgbe_mac_info *mac = &hw->mac;
56 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
59 DEBUGFUNC("ixgbe_init_ops_X550");
61 ret_val = ixgbe_init_ops_X540(hw);
62 mac->ops.dmac_config = ixgbe_dmac_config_X550;
63 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
64 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
65 mac->ops.setup_eee = NULL;
66 mac->ops.set_source_address_pruning =
67 ixgbe_set_source_address_pruning_X550;
68 mac->ops.set_ethertype_anti_spoofing =
69 ixgbe_set_ethertype_anti_spoofing_X550;
71 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
72 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
73 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
74 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
75 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
76 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
77 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
78 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
79 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
81 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
82 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
83 mac->ops.mdd_event = ixgbe_mdd_event_X550;
84 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
85 mac->ops.disable_rx = ixgbe_disable_rx_x550;
86 /* Manageability interface */
87 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_x550;
88 switch (hw->device_id) {
89 case IXGBE_DEV_ID_X550EM_X_10G_T:
90 case IXGBE_DEV_ID_X550EM_A_10G_T:
91 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
92 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
101 * ixgbe_read_cs4227 - Read CS4227 register
102 * @hw: pointer to hardware structure
103 * @reg: register number to write
104 * @value: pointer to receive value read
106 * Returns status code
108 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
110 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
114 * ixgbe_write_cs4227 - Write CS4227 register
115 * @hw: pointer to hardware structure
116 * @reg: register number to write
117 * @value: value to write to register
119 * Returns status code
121 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
123 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
127 * ixgbe_read_pe - Read register from port expander
128 * @hw: pointer to hardware structure
129 * @reg: register number to read
130 * @value: pointer to receive read value
132 * Returns status code
134 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
138 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
139 if (status != IXGBE_SUCCESS)
140 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
141 "port expander access failed with %d\n", status);
146 * ixgbe_write_pe - Write register to port expander
147 * @hw: pointer to hardware structure
148 * @reg: register number to write
149 * @value: value to write
151 * Returns status code
153 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
157 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
158 if (status != IXGBE_SUCCESS)
159 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
160 "port expander access failed with %d\n", status);
165 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
166 * @hw: pointer to hardware structure
168 * This function assumes that the caller has acquired the proper semaphore.
171 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
178 /* Trigger hard reset. */
179 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
180 if (status != IXGBE_SUCCESS)
182 reg |= IXGBE_PE_BIT1;
183 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
184 if (status != IXGBE_SUCCESS)
187 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
188 if (status != IXGBE_SUCCESS)
190 reg &= ~IXGBE_PE_BIT1;
191 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
192 if (status != IXGBE_SUCCESS)
195 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
196 if (status != IXGBE_SUCCESS)
198 reg &= ~IXGBE_PE_BIT1;
199 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
200 if (status != IXGBE_SUCCESS)
203 usec_delay(IXGBE_CS4227_RESET_HOLD);
205 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
206 if (status != IXGBE_SUCCESS)
208 reg |= IXGBE_PE_BIT1;
209 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
210 if (status != IXGBE_SUCCESS)
213 /* Wait for the reset to complete. */
214 msec_delay(IXGBE_CS4227_RESET_DELAY);
215 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
216 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
218 if (status == IXGBE_SUCCESS &&
219 value == IXGBE_CS4227_EEPROM_LOAD_OK)
221 msec_delay(IXGBE_CS4227_CHECK_DELAY);
223 if (retry == IXGBE_CS4227_RETRIES) {
224 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
225 "CS4227 reset did not complete.");
226 return IXGBE_ERR_PHY;
229 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
230 if (status != IXGBE_SUCCESS ||
231 !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
232 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
233 "CS4227 EEPROM did not load successfully.");
234 return IXGBE_ERR_PHY;
237 return IXGBE_SUCCESS;
241 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
242 * @hw: pointer to hardware structure
244 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
246 s32 status = IXGBE_SUCCESS;
247 u32 swfw_mask = hw->phy.phy_semaphore_mask;
251 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
252 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
253 if (status != IXGBE_SUCCESS) {
254 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
255 "semaphore failed with %d", status);
256 msec_delay(IXGBE_CS4227_CHECK_DELAY);
260 /* Get status of reset flow. */
261 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
263 if (status == IXGBE_SUCCESS &&
264 value == IXGBE_CS4227_RESET_COMPLETE)
267 if (status != IXGBE_SUCCESS ||
268 value != IXGBE_CS4227_RESET_PENDING)
271 /* Reset is pending. Wait and check again. */
272 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
273 msec_delay(IXGBE_CS4227_CHECK_DELAY);
276 /* If still pending, assume other instance failed. */
277 if (retry == IXGBE_CS4227_RETRIES) {
278 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
279 if (status != IXGBE_SUCCESS) {
280 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
281 "semaphore failed with %d", status);
286 /* Reset the CS4227. */
287 status = ixgbe_reset_cs4227(hw);
288 if (status != IXGBE_SUCCESS) {
289 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
290 "CS4227 reset failed: %d", status);
294 /* Reset takes so long, temporarily release semaphore in case the
295 * other driver instance is waiting for the reset indication.
297 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
298 IXGBE_CS4227_RESET_PENDING);
299 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
301 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
302 if (status != IXGBE_SUCCESS) {
303 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
304 "semaphore failed with %d", status);
308 /* Record completion for next time. */
309 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
310 IXGBE_CS4227_RESET_COMPLETE);
313 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
314 msec_delay(hw->eeprom.semaphore_delay);
318 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
319 * @hw: pointer to hardware structure
321 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
323 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
325 if (hw->bus.lan_id) {
326 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
327 esdp |= IXGBE_ESDP_SDP1_DIR;
329 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
330 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
331 IXGBE_WRITE_FLUSH(hw);
335 * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
336 * @hw: pointer to hardware structure
337 * @reg_addr: 32 bit address of PHY register to read
338 * @dev_type: always unused
339 * @phy_data: Pointer to read data from PHY register
341 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
342 u32 dev_type, u16 *phy_data)
344 u32 i, data, command;
345 UNREFERENCED_1PARAMETER(dev_type);
347 /* Setup and write the read command */
348 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
349 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
350 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
351 IXGBE_MSCA_MDI_COMMAND;
353 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
355 /* Check every 10 usec to see if the access completed.
356 * The MDI Command bit will clear when the operation is
359 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
362 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
363 if (!(command & IXGBE_MSCA_MDI_COMMAND))
367 if (command & IXGBE_MSCA_MDI_COMMAND) {
368 ERROR_REPORT1(IXGBE_ERROR_POLLING,
369 "PHY read command did not complete.\n");
370 return IXGBE_ERR_PHY;
373 /* Read operation is complete. Get the data from MSRWD */
374 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
375 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
376 *phy_data = (u16)data;
378 return IXGBE_SUCCESS;
382 * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
383 * @hw: pointer to hardware structure
384 * @reg_addr: 32 bit PHY register to write
385 * @dev_type: always unused
386 * @phy_data: Data to write to the PHY register
388 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
389 u32 dev_type, u16 phy_data)
392 UNREFERENCED_1PARAMETER(dev_type);
394 /* Put the data in the MDI single read and write data register*/
395 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
397 /* Setup and write the write command */
398 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
399 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
400 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
401 IXGBE_MSCA_MDI_COMMAND;
403 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
405 /* Check every 10 usec to see if the access completed.
406 * The MDI Command bit will clear when the operation is
409 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
412 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
413 if (!(command & IXGBE_MSCA_MDI_COMMAND))
417 if (command & IXGBE_MSCA_MDI_COMMAND) {
418 ERROR_REPORT1(IXGBE_ERROR_POLLING,
419 "PHY write cmd didn't complete\n");
420 return IXGBE_ERR_PHY;
423 return IXGBE_SUCCESS;
427 * ixgbe_identify_phy_x550em - Get PHY type based on device id
428 * @hw: pointer to hardware structure
432 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
434 hw->mac.ops.set_lan_id(hw);
436 ixgbe_read_mng_if_sel_x550em(hw);
438 switch (hw->device_id) {
439 case IXGBE_DEV_ID_X550EM_A_SFP:
440 return ixgbe_identify_module_generic(hw);
441 case IXGBE_DEV_ID_X550EM_X_SFP:
442 /* set up for CS4227 usage */
443 ixgbe_setup_mux_ctl(hw);
444 ixgbe_check_cs4227(hw);
447 case IXGBE_DEV_ID_X550EM_A_SFP_N:
448 return ixgbe_identify_module_generic(hw);
450 case IXGBE_DEV_ID_X550EM_X_KX4:
451 hw->phy.type = ixgbe_phy_x550em_kx4;
453 case IXGBE_DEV_ID_X550EM_X_XFI:
454 hw->phy.type = ixgbe_phy_x550em_xfi;
456 case IXGBE_DEV_ID_X550EM_X_KR:
457 case IXGBE_DEV_ID_X550EM_A_KR:
458 case IXGBE_DEV_ID_X550EM_A_KR_L:
459 hw->phy.type = ixgbe_phy_x550em_kr;
461 case IXGBE_DEV_ID_X550EM_A_10G_T:
462 case IXGBE_DEV_ID_X550EM_X_1G_T:
463 case IXGBE_DEV_ID_X550EM_X_10G_T:
464 return ixgbe_identify_phy_generic(hw);
465 case IXGBE_DEV_ID_X550EM_A_1G_T:
466 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
467 hw->phy.type = ixgbe_phy_fw;
468 hw->phy.ops.read_reg = NULL;
469 hw->phy.ops.write_reg = NULL;
471 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
473 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
478 return IXGBE_SUCCESS;
482 * ixgbe_fw_phy_activity - Perform an activity on a PHY
483 * @hw: pointer to hardware structure
484 * @activity: activity to perform
485 * @data: Pointer to 4 32-bit words of data
487 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,
488 u32 (*data)[FW_PHY_ACT_DATA_COUNT])
491 struct ixgbe_hic_phy_activity_req cmd;
492 struct ixgbe_hic_phy_activity_resp rsp;
494 u16 retries = FW_PHY_ACT_RETRIES;
499 memset(&hic, 0, sizeof(hic));
500 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD;
501 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN;
502 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
503 hic.cmd.port_number = hw->bus.lan_id;
504 hic.cmd.activity_id = IXGBE_CPU_TO_LE16(activity);
505 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
506 hic.cmd.data[i] = IXGBE_CPU_TO_BE32((*data)[i]);
508 rc = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
510 IXGBE_HI_COMMAND_TIMEOUT,
512 if (rc != IXGBE_SUCCESS)
514 if (hic.rsp.hdr.cmd_or_resp.ret_status ==
515 FW_CEM_RESP_STATUS_SUCCESS) {
516 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
517 (*data)[i] = IXGBE_BE32_TO_CPU(hic.rsp.data[i]);
518 return IXGBE_SUCCESS;
522 } while (retries > 0);
524 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
527 static const struct {
529 ixgbe_link_speed phy_speed;
531 { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL },
532 { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL },
533 { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL },
534 { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL },
535 { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL },
536 { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL },
540 * ixgbe_get_phy_id_fw - Get the phy ID via firmware command
541 * @hw: pointer to hardware structure
545 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw)
547 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
553 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info);
557 hw->phy.speeds_supported = 0;
558 phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK;
559 for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
560 if (phy_speeds & ixgbe_fw_map[i].fw_speed)
561 hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed;
563 if (!hw->phy.autoneg_advertised)
564 hw->phy.autoneg_advertised = hw->phy.speeds_supported;
566 hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK;
567 phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK;
568 hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK;
569 hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK;
570 if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK)
571 return IXGBE_ERR_PHY_ADDR_INVALID;
572 return IXGBE_SUCCESS;
576 * ixgbe_identify_phy_fw - Get PHY type based on firmware command
577 * @hw: pointer to hardware structure
581 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw)
584 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
586 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
588 hw->phy.type = ixgbe_phy_fw;
589 hw->phy.ops.read_reg = NULL;
590 hw->phy.ops.write_reg = NULL;
591 return ixgbe_get_phy_id_fw(hw);
595 * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY
596 * @hw: pointer to hardware structure
600 s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw)
602 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
604 setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF;
605 return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup);
608 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
609 u32 device_type, u16 *phy_data)
611 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
612 return IXGBE_NOT_IMPLEMENTED;
615 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
616 u32 device_type, u16 phy_data)
618 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
619 return IXGBE_NOT_IMPLEMENTED;
623 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
624 * @hw: pointer to the hardware structure
625 * @addr: I2C bus address to read from
626 * @reg: I2C device register to read from
627 * @val: pointer to location to receive read value
629 * Returns an error code on error.
631 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
634 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
638 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
639 * @hw: pointer to the hardware structure
640 * @addr: I2C bus address to read from
641 * @reg: I2C device register to read from
642 * @val: pointer to location to receive read value
644 * Returns an error code on error.
647 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
650 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
654 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
655 * @hw: pointer to the hardware structure
656 * @addr: I2C bus address to write to
657 * @reg: I2C device register to write to
658 * @val: value to write
660 * Returns an error code on error.
662 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
663 u8 addr, u16 reg, u16 val)
665 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
669 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
670 * @hw: pointer to the hardware structure
671 * @addr: I2C bus address to write to
672 * @reg: I2C device register to write to
673 * @val: value to write
675 * Returns an error code on error.
678 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
679 u8 addr, u16 reg, u16 val)
681 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
685 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
686 * @hw: pointer to hardware structure
688 * Initialize the function pointers and for MAC type X550EM.
689 * Does not touch the hardware.
691 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
693 struct ixgbe_mac_info *mac = &hw->mac;
694 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
695 struct ixgbe_phy_info *phy = &hw->phy;
698 DEBUGFUNC("ixgbe_init_ops_X550EM");
700 /* Similar to X550 so start there. */
701 ret_val = ixgbe_init_ops_X550(hw);
703 /* Since this function eventually calls
704 * ixgbe_init_ops_540 by design, we are setting
705 * the pointers to NULL explicitly here to overwrite
706 * the values being set in the x540 function.
708 /* Thermal sensor not supported in x550EM */
709 mac->ops.get_thermal_sensor_data = NULL;
710 mac->ops.init_thermal_sensor_thresh = NULL;
711 mac->thermal_sensor_enabled = false;
713 /* FCOE not supported in x550EM */
714 mac->ops.get_san_mac_addr = NULL;
715 mac->ops.set_san_mac_addr = NULL;
716 mac->ops.get_wwn_prefix = NULL;
717 mac->ops.get_fcoe_boot_status = NULL;
719 /* IPsec not supported in x550EM */
720 mac->ops.disable_sec_rx_path = NULL;
721 mac->ops.enable_sec_rx_path = NULL;
723 /* AUTOC register is not present in x550EM. */
724 mac->ops.prot_autoc_read = NULL;
725 mac->ops.prot_autoc_write = NULL;
727 /* X550EM bus type is internal*/
728 hw->bus.type = ixgbe_bus_type_internal;
729 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
732 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
733 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
734 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
735 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
736 mac->ops.get_supported_physical_layer =
737 ixgbe_get_supported_physical_layer_X550em;
739 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
740 mac->ops.setup_fc = ixgbe_setup_fc_generic;
742 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
745 phy->ops.init = ixgbe_init_phy_ops_X550em;
746 switch (hw->device_id) {
747 case IXGBE_DEV_ID_X550EM_A_1G_T:
748 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
749 mac->ops.setup_fc = NULL;
750 phy->ops.identify = ixgbe_identify_phy_fw;
751 phy->ops.set_phy_power = NULL;
752 phy->ops.get_firmware_version = NULL;
755 phy->ops.identify = ixgbe_identify_phy_x550em;
758 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
759 phy->ops.set_phy_power = NULL;
763 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
764 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
765 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
766 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
767 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
768 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
769 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
770 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
776 * ixgbe_setup_fw_link - Setup firmware-controlled PHYs
777 * @hw: pointer to hardware structure
779 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw)
781 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
785 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
788 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
789 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
790 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
791 return IXGBE_ERR_INVALID_LINK_SETTINGS;
794 switch (hw->fc.requested_mode) {
796 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX <<
797 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
799 case ixgbe_fc_rx_pause:
800 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX <<
801 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
803 case ixgbe_fc_tx_pause:
804 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX <<
805 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
811 for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
812 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)
813 setup[0] |= ixgbe_fw_map[i].fw_speed;
815 setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN;
817 if (hw->phy.eee_speeds_advertised)
818 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE;
820 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup);
823 if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN)
824 return IXGBE_ERR_OVERTEMP;
825 return IXGBE_SUCCESS;
829 * ixgbe_fc_autoneg_fw _ Set up flow control for FW-controlled PHYs
830 * @hw: pointer to hardware structure
832 * Called at init time to set up flow control.
834 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw)
836 if (hw->fc.requested_mode == ixgbe_fc_default)
837 hw->fc.requested_mode = ixgbe_fc_full;
839 return ixgbe_setup_fw_link(hw);
843 * ixgbe_setup_eee_fw - Enable/disable EEE support
844 * @hw: pointer to the HW structure
845 * @enable_eee: boolean flag to enable EEE
847 * Enable/disable EEE based on enable_eee flag.
848 * This function controls EEE for firmware-based PHY implementations.
850 static s32 ixgbe_setup_eee_fw(struct ixgbe_hw *hw, bool enable_eee)
852 if (!!hw->phy.eee_speeds_advertised == enable_eee)
853 return IXGBE_SUCCESS;
855 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
857 hw->phy.eee_speeds_advertised = 0;
858 return hw->phy.ops.setup_link(hw);
862 * ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
863 * @hw: pointer to hardware structure
865 * Initialize the function pointers and for MAC type X550EM_a.
866 * Does not touch the hardware.
868 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
870 struct ixgbe_mac_info *mac = &hw->mac;
873 DEBUGFUNC("ixgbe_init_ops_X550EM_a");
875 /* Start with generic X550EM init */
876 ret_val = ixgbe_init_ops_X550EM(hw);
878 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
879 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) {
880 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
881 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
883 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
884 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
886 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
887 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
889 switch (mac->ops.get_media_type(hw)) {
890 case ixgbe_media_type_fiber:
891 mac->ops.setup_fc = NULL;
892 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
894 case ixgbe_media_type_backplane:
895 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
896 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
902 switch (hw->device_id) {
903 case IXGBE_DEV_ID_X550EM_A_1G_T:
904 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
905 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
906 mac->ops.setup_fc = ixgbe_fc_autoneg_fw;
907 mac->ops.setup_eee = ixgbe_setup_eee_fw;
908 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL |
909 IXGBE_LINK_SPEED_1GB_FULL;
910 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
920 * ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
921 * @hw: pointer to hardware structure
923 * Initialize the function pointers and for MAC type X550EM_x.
924 * Does not touch the hardware.
926 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
928 struct ixgbe_mac_info *mac = &hw->mac;
929 struct ixgbe_link_info *link = &hw->link;
932 DEBUGFUNC("ixgbe_init_ops_X550EM_x");
934 /* Start with generic X550EM init */
935 ret_val = ixgbe_init_ops_X550EM(hw);
937 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
938 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
939 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
940 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
941 link->ops.read_link = ixgbe_read_i2c_combined_generic;
942 link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
943 link->ops.write_link = ixgbe_write_i2c_combined_generic;
944 link->ops.write_link_unlocked =
945 ixgbe_write_i2c_combined_generic_unlocked;
946 link->addr = IXGBE_CS4227;
953 * ixgbe_dmac_config_X550
954 * @hw: pointer to hardware structure
956 * Configure DMA coalescing. If enabling dmac, dmac is activated.
957 * When disabling dmac, dmac enable dmac bit is cleared.
959 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
961 u32 reg, high_pri_tc;
963 DEBUGFUNC("ixgbe_dmac_config_X550");
965 /* Disable DMA coalescing before configuring */
966 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
967 reg &= ~IXGBE_DMACR_DMAC_EN;
968 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
970 /* Disable DMA Coalescing if the watchdog timer is 0 */
971 if (!hw->mac.dmac_config.watchdog_timer)
974 ixgbe_dmac_config_tcs_X550(hw);
976 /* Configure DMA Coalescing Control Register */
977 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
979 /* Set the watchdog timer in units of 40.96 usec */
980 reg &= ~IXGBE_DMACR_DMACWT_MASK;
981 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
983 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
984 /* If fcoe is enabled, set high priority traffic class */
985 if (hw->mac.dmac_config.fcoe_en) {
986 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
987 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
988 IXGBE_DMACR_HIGH_PRI_TC_MASK);
990 reg |= IXGBE_DMACR_EN_MNG_IND;
992 /* Enable DMA coalescing after configuration */
993 reg |= IXGBE_DMACR_DMAC_EN;
994 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
997 return IXGBE_SUCCESS;
1001 * ixgbe_dmac_config_tcs_X550
1002 * @hw: pointer to hardware structure
1004 * Configure DMA coalescing threshold per TC. The dmac enable bit must
1005 * be cleared before configuring.
1007 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
1009 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
1011 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
1013 /* Configure DMA coalescing enabled */
1014 switch (hw->mac.dmac_config.link_speed) {
1015 case IXGBE_LINK_SPEED_10_FULL:
1016 case IXGBE_LINK_SPEED_100_FULL:
1017 pb_headroom = IXGBE_DMACRXT_100M;
1019 case IXGBE_LINK_SPEED_1GB_FULL:
1020 pb_headroom = IXGBE_DMACRXT_1G;
1023 pb_headroom = IXGBE_DMACRXT_10G;
1027 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
1028 IXGBE_MHADD_MFS_SHIFT) / 1024);
1030 /* Set the per Rx packet buffer receive threshold */
1031 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
1032 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
1033 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
1035 if (tc < hw->mac.dmac_config.num_tcs) {
1036 /* Get Rx PB size */
1037 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
1038 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
1039 IXGBE_RXPBSIZE_SHIFT;
1041 /* Calculate receive buffer threshold in kilobytes */
1042 if (rx_pb_size > pb_headroom)
1043 rx_pb_size = rx_pb_size - pb_headroom;
1047 /* Minimum of MFS shall be set for DMCTH */
1048 reg |= (rx_pb_size > maxframe_size_kb) ?
1049 rx_pb_size : maxframe_size_kb;
1051 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
1053 return IXGBE_SUCCESS;
1057 * ixgbe_dmac_update_tcs_X550
1058 * @hw: pointer to hardware structure
1060 * Disables dmac, updates per TC settings, and then enables dmac.
1062 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
1066 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
1068 /* Disable DMA coalescing before configuring */
1069 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
1070 reg &= ~IXGBE_DMACR_DMAC_EN;
1071 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
1073 ixgbe_dmac_config_tcs_X550(hw);
1075 /* Enable DMA coalescing after configuration */
1076 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
1077 reg |= IXGBE_DMACR_DMAC_EN;
1078 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
1080 return IXGBE_SUCCESS;
1084 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
1085 * @hw: pointer to hardware structure
1087 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
1088 * ixgbe_hw struct in order to set up EEPROM access.
1090 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
1092 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1096 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
1098 if (eeprom->type == ixgbe_eeprom_uninitialized) {
1099 eeprom->semaphore_delay = 10;
1100 eeprom->type = ixgbe_flash;
1102 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1103 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1104 IXGBE_EEC_SIZE_SHIFT);
1105 eeprom->word_size = 1 << (eeprom_size +
1106 IXGBE_EEPROM_WORD_SIZE_SHIFT);
1108 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
1109 eeprom->type, eeprom->word_size);
1112 return IXGBE_SUCCESS;
1116 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1117 * @hw: pointer to hardware structure
1118 * @enable: enable or disable source address pruning
1119 * @pool: Rx pool to set source address pruning for
1121 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1126 /* max rx pool is 63 */
1130 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1131 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1134 pfflp |= (1ULL << pool);
1136 pfflp &= ~(1ULL << pool);
1138 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1139 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1143 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1144 * @hw: pointer to hardware structure
1145 * @enable: enable or disable switch for Ethertype anti-spoofing
1146 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1149 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1150 bool enable, int vf)
1152 int vf_target_reg = vf >> 3;
1153 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1156 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1158 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1160 pfvfspoof |= (1 << vf_target_shift);
1162 pfvfspoof &= ~(1 << vf_target_shift);
1164 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1168 * ixgbe_iosf_wait - Wait for IOSF command completion
1169 * @hw: pointer to hardware structure
1170 * @ctrl: pointer to location to receive final IOSF control value
1172 * Returns failing status on timeout
1174 * Note: ctrl can be NULL if the IOSF control register value is not needed
1176 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1180 /* Check every 10 usec to see if the address cycle completed.
1181 * The SB IOSF BUSY bit will clear when the operation is
1184 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1185 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1186 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1192 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1193 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1194 return IXGBE_ERR_PHY;
1197 return IXGBE_SUCCESS;
1201 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register
1202 * of the IOSF device
1203 * @hw: pointer to hardware structure
1204 * @reg_addr: 32 bit PHY register to write
1205 * @device_type: 3 bit device type
1206 * @data: Data to write to the register
1208 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1209 u32 device_type, u32 data)
1211 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1215 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1216 if (ret != IXGBE_SUCCESS)
1219 ret = ixgbe_iosf_wait(hw, NULL);
1220 if (ret != IXGBE_SUCCESS)
1223 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1224 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1226 /* Write IOSF control register */
1227 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1229 /* Write IOSF data register */
1230 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1232 ret = ixgbe_iosf_wait(hw, &command);
1234 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1235 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1236 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1237 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1238 "Failed to write, error %x\n", error);
1239 ret = IXGBE_ERR_PHY;
1243 ixgbe_release_swfw_semaphore(hw, gssr);
1248 * ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device
1249 * @hw: pointer to hardware structure
1250 * @reg_addr: 32 bit PHY register to write
1251 * @device_type: 3 bit device type
1252 * @data: Pointer to read data from the register
1254 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1255 u32 device_type, u32 *data)
1257 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1261 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1262 if (ret != IXGBE_SUCCESS)
1265 ret = ixgbe_iosf_wait(hw, NULL);
1266 if (ret != IXGBE_SUCCESS)
1269 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1270 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1272 /* Write IOSF control register */
1273 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1275 ret = ixgbe_iosf_wait(hw, &command);
1277 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1278 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1279 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1280 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1281 "Failed to read, error %x\n", error);
1282 ret = IXGBE_ERR_PHY;
1285 if (ret == IXGBE_SUCCESS)
1286 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1289 ixgbe_release_swfw_semaphore(hw, gssr);
1294 * ixgbe_get_phy_token - Get the token for shared phy access
1295 * @hw: Pointer to hardware structure
1298 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1300 struct ixgbe_hic_phy_token_req token_cmd;
1303 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1304 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1305 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1306 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1307 token_cmd.port_number = hw->bus.lan_id;
1308 token_cmd.command_type = FW_PHY_TOKEN_REQ;
1310 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1312 IXGBE_HI_COMMAND_TIMEOUT,
1316 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1317 return IXGBE_SUCCESS;
1318 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1319 return IXGBE_ERR_FW_RESP_INVALID;
1321 return IXGBE_ERR_TOKEN_RETRY;
1325 * ixgbe_put_phy_token - Put the token for shared phy access
1326 * @hw: Pointer to hardware structure
1329 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1331 struct ixgbe_hic_phy_token_req token_cmd;
1334 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1335 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1336 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1337 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1338 token_cmd.port_number = hw->bus.lan_id;
1339 token_cmd.command_type = FW_PHY_TOKEN_REL;
1341 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1343 IXGBE_HI_COMMAND_TIMEOUT,
1347 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1348 return IXGBE_SUCCESS;
1350 DEBUGOUT("Put PHY Token host interface command failed");
1351 return IXGBE_ERR_FW_RESP_INVALID;
1355 * ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1356 * of the IOSF device
1357 * @hw: pointer to hardware structure
1358 * @reg_addr: 32 bit PHY register to write
1359 * @device_type: 3 bit device type
1360 * @data: Data to write to the register
1362 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1363 u32 device_type, u32 data)
1365 struct ixgbe_hic_internal_phy_req write_cmd;
1367 UNREFERENCED_1PARAMETER(device_type);
1369 memset(&write_cmd, 0, sizeof(write_cmd));
1370 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1371 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1372 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1373 write_cmd.port_number = hw->bus.lan_id;
1374 write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1375 write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1376 write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1378 status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1380 IXGBE_HI_COMMAND_TIMEOUT, false);
1386 * ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device
1387 * @hw: pointer to hardware structure
1388 * @reg_addr: 32 bit PHY register to write
1389 * @device_type: 3 bit device type
1390 * @data: Pointer to read data from the register
1392 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1393 u32 device_type, u32 *data)
1396 struct ixgbe_hic_internal_phy_req cmd;
1397 struct ixgbe_hic_internal_phy_resp rsp;
1400 UNREFERENCED_1PARAMETER(device_type);
1402 memset(&hic, 0, sizeof(hic));
1403 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1404 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1405 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1406 hic.cmd.port_number = hw->bus.lan_id;
1407 hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1408 hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1410 status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1412 IXGBE_HI_COMMAND_TIMEOUT, true);
1414 /* Extract the register value from the response. */
1415 *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1421 * ixgbe_disable_mdd_X550
1422 * @hw: pointer to hardware structure
1424 * Disable malicious driver detection
1426 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1430 DEBUGFUNC("ixgbe_disable_mdd_X550");
1432 /* Disable MDD for TX DMA and interrupt */
1433 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1434 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1435 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1437 /* Disable MDD for RX and interrupt */
1438 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1439 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1440 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1444 * ixgbe_enable_mdd_X550
1445 * @hw: pointer to hardware structure
1447 * Enable malicious driver detection
1449 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1453 DEBUGFUNC("ixgbe_enable_mdd_X550");
1455 /* Enable MDD for TX DMA and interrupt */
1456 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1457 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1458 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1460 /* Enable MDD for RX and interrupt */
1461 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1462 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1463 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1467 * ixgbe_restore_mdd_vf_X550
1468 * @hw: pointer to hardware structure
1471 * Restore VF that was disabled during malicious driver detection event
1473 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1475 u32 idx, reg, num_qs, start_q, bitmask;
1477 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1479 /* Map VF to queues */
1480 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1481 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1482 case IXGBE_MRQC_VMDQRT8TCEN:
1483 num_qs = 8; /* 16 VFs / pools */
1484 bitmask = 0x000000FF;
1486 case IXGBE_MRQC_VMDQRSS32EN:
1487 case IXGBE_MRQC_VMDQRT4TCEN:
1488 num_qs = 4; /* 32 VFs / pools */
1489 bitmask = 0x0000000F;
1491 default: /* 64 VFs / pools */
1493 bitmask = 0x00000003;
1496 start_q = vf * num_qs;
1498 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1501 reg |= (bitmask << (start_q % 32));
1502 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1503 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1507 * ixgbe_mdd_event_X550
1508 * @hw: pointer to hardware structure
1509 * @vf_bitmap: vf bitmap of malicious vfs
1511 * Handle malicious driver detection event.
1513 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1516 u32 i, j, reg, q, shift, vf, idx;
1518 DEBUGFUNC("ixgbe_mdd_event_X550");
1520 /* figure out pool size for mapping to vf's */
1521 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1522 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1523 case IXGBE_MRQC_VMDQRT8TCEN:
1524 shift = 3; /* 16 VFs / pools */
1526 case IXGBE_MRQC_VMDQRSS32EN:
1527 case IXGBE_MRQC_VMDQRT4TCEN:
1528 shift = 2; /* 32 VFs / pools */
1531 shift = 1; /* 64 VFs / pools */
1535 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1536 for (i = 0; i < 4; i++) {
1537 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1538 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1543 /* Get malicious queue */
1544 for (j = 0; j < 32 && wqbr; j++) {
1546 if (!(wqbr & (1 << j)))
1549 /* Get queue from bitmask */
1552 /* Map queue to vf */
1555 /* Set vf bit in vf_bitmap */
1557 vf_bitmap[idx] |= (1 << (vf % 32));
1564 * ixgbe_get_media_type_X550em - Get media type
1565 * @hw: pointer to hardware structure
1567 * Returns the media type (fiber, copper, backplane)
1569 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1571 enum ixgbe_media_type media_type;
1573 DEBUGFUNC("ixgbe_get_media_type_X550em");
1575 /* Detect if there is a copper PHY attached. */
1576 switch (hw->device_id) {
1577 case IXGBE_DEV_ID_X550EM_X_KR:
1578 case IXGBE_DEV_ID_X550EM_X_KX4:
1579 case IXGBE_DEV_ID_X550EM_X_XFI:
1580 case IXGBE_DEV_ID_X550EM_A_KR:
1581 case IXGBE_DEV_ID_X550EM_A_KR_L:
1582 media_type = ixgbe_media_type_backplane;
1584 case IXGBE_DEV_ID_X550EM_X_SFP:
1585 case IXGBE_DEV_ID_X550EM_A_SFP:
1586 case IXGBE_DEV_ID_X550EM_A_SFP_N:
1587 case IXGBE_DEV_ID_X550EM_A_QSFP:
1588 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1589 media_type = ixgbe_media_type_fiber;
1591 case IXGBE_DEV_ID_X550EM_X_1G_T:
1592 case IXGBE_DEV_ID_X550EM_X_10G_T:
1593 case IXGBE_DEV_ID_X550EM_A_10G_T:
1594 media_type = ixgbe_media_type_copper;
1596 case IXGBE_DEV_ID_X550EM_A_SGMII:
1597 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1598 media_type = ixgbe_media_type_backplane;
1599 hw->phy.type = ixgbe_phy_sgmii;
1601 case IXGBE_DEV_ID_X550EM_A_1G_T:
1602 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1603 media_type = ixgbe_media_type_copper;
1606 media_type = ixgbe_media_type_unknown;
1613 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1614 * @hw: pointer to hardware structure
1615 * @linear: true if SFP module is linear
1617 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1619 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1621 switch (hw->phy.sfp_type) {
1622 case ixgbe_sfp_type_not_present:
1623 return IXGBE_ERR_SFP_NOT_PRESENT;
1624 case ixgbe_sfp_type_da_cu_core0:
1625 case ixgbe_sfp_type_da_cu_core1:
1628 case ixgbe_sfp_type_srlr_core0:
1629 case ixgbe_sfp_type_srlr_core1:
1630 case ixgbe_sfp_type_da_act_lmt_core0:
1631 case ixgbe_sfp_type_da_act_lmt_core1:
1632 case ixgbe_sfp_type_1g_sx_core0:
1633 case ixgbe_sfp_type_1g_sx_core1:
1634 case ixgbe_sfp_type_1g_lx_core0:
1635 case ixgbe_sfp_type_1g_lx_core1:
1638 case ixgbe_sfp_type_unknown:
1639 case ixgbe_sfp_type_1g_cu_core0:
1640 case ixgbe_sfp_type_1g_cu_core1:
1642 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1645 return IXGBE_SUCCESS;
1649 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1650 * @hw: pointer to hardware structure
1652 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1654 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1659 DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1661 status = ixgbe_identify_module_generic(hw);
1663 if (status != IXGBE_SUCCESS)
1666 /* Check if SFP module is supported */
1667 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1673 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1674 * @hw: pointer to hardware structure
1676 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1681 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1683 /* Check if SFP module is supported */
1684 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1686 if (status != IXGBE_SUCCESS)
1689 ixgbe_init_mac_link_ops_X550em(hw);
1690 hw->phy.ops.reset = NULL;
1692 return IXGBE_SUCCESS;
1696 * ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1698 * @hw: pointer to hardware structure
1700 STATIC s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1705 /* Restart auto-negotiation. */
1706 status = hw->mac.ops.read_iosf_sb_reg(hw,
1707 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1708 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1711 DEBUGOUT("Auto-negotiation did not complete\n");
1715 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1716 status = hw->mac.ops.write_iosf_sb_reg(hw,
1717 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1718 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1720 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1723 /* Indicate to FW that AN restart has been asserted */
1724 status = hw->mac.ops.read_iosf_sb_reg(hw,
1725 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1726 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1729 DEBUGOUT("Auto-negotiation did not complete\n");
1733 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1734 status = hw->mac.ops.write_iosf_sb_reg(hw,
1735 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1736 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1743 * ixgbe_setup_sgmii - Set up link for sgmii
1744 * @hw: pointer to hardware structure
1746 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1749 struct ixgbe_mac_info *mac = &hw->mac;
1750 u32 lval, sval, flx_val;
1753 rc = mac->ops.read_iosf_sb_reg(hw,
1754 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1755 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1759 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1760 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1761 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1762 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1763 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1764 rc = mac->ops.write_iosf_sb_reg(hw,
1765 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1766 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1770 rc = mac->ops.read_iosf_sb_reg(hw,
1771 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1772 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1776 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1777 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1778 rc = mac->ops.write_iosf_sb_reg(hw,
1779 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1780 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1784 rc = mac->ops.read_iosf_sb_reg(hw,
1785 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1786 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1790 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1791 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1792 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1793 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1794 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1796 rc = mac->ops.write_iosf_sb_reg(hw,
1797 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1798 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1802 rc = ixgbe_restart_an_internal_phy_x550em(hw);
1806 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1810 * ixgbe_setup_sgmii_fw - Set up link for sgmii with firmware-controlled PHYs
1811 * @hw: pointer to hardware structure
1813 STATIC s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1816 struct ixgbe_mac_info *mac = &hw->mac;
1817 u32 lval, sval, flx_val;
1820 rc = mac->ops.read_iosf_sb_reg(hw,
1821 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1822 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1826 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1827 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1828 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1829 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1830 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1831 rc = mac->ops.write_iosf_sb_reg(hw,
1832 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1833 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1837 rc = mac->ops.read_iosf_sb_reg(hw,
1838 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1839 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1843 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1844 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1845 rc = mac->ops.write_iosf_sb_reg(hw,
1846 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1847 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1851 rc = mac->ops.write_iosf_sb_reg(hw,
1852 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1853 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1857 rc = mac->ops.read_iosf_sb_reg(hw,
1858 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1859 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1863 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1864 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
1865 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1866 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1867 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1869 rc = mac->ops.write_iosf_sb_reg(hw,
1870 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1871 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1875 rc = ixgbe_restart_an_internal_phy_x550em(hw);
1877 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1881 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1882 * @hw: pointer to hardware structure
1884 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1886 struct ixgbe_mac_info *mac = &hw->mac;
1888 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1890 switch (hw->mac.ops.get_media_type(hw)) {
1891 case ixgbe_media_type_fiber:
1892 /* CS4227 does not support autoneg, so disable the laser control
1893 * functions for SFP+ fiber
1895 mac->ops.disable_tx_laser = NULL;
1896 mac->ops.enable_tx_laser = NULL;
1897 mac->ops.flap_tx_laser = NULL;
1898 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1899 mac->ops.set_rate_select_speed =
1900 ixgbe_set_soft_rate_select_speed;
1902 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1903 (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1904 mac->ops.setup_mac_link =
1905 ixgbe_setup_mac_link_sfp_x550a;
1907 mac->ops.setup_mac_link =
1908 ixgbe_setup_mac_link_sfp_x550em;
1910 case ixgbe_media_type_copper:
1911 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1912 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
1913 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
1914 mac->ops.setup_link = ixgbe_setup_sgmii_fw;
1915 mac->ops.check_link =
1916 ixgbe_check_mac_link_generic;
1918 mac->ops.setup_link =
1919 ixgbe_setup_mac_link_t_X550em;
1922 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1923 mac->ops.check_link = ixgbe_check_link_t_X550em;
1926 case ixgbe_media_type_backplane:
1927 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1928 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1929 mac->ops.setup_link = ixgbe_setup_sgmii;
1937 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1938 * @hw: pointer to hardware structure
1939 * @speed: pointer to link speed
1940 * @autoneg: true when autoneg or autotry is enabled
1942 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1943 ixgbe_link_speed *speed,
1946 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1949 if (hw->phy.type == ixgbe_phy_fw) {
1951 *speed = hw->phy.speeds_supported;
1956 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1958 /* CS4227 SFP must not enable auto-negotiation */
1961 /* Check if 1G SFP module. */
1962 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1963 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1964 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1965 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1966 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1967 return IXGBE_SUCCESS;
1970 /* Link capabilities are based on SFP */
1971 if (hw->phy.multispeed_fiber)
1972 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1973 IXGBE_LINK_SPEED_1GB_FULL;
1975 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1977 switch (hw->phy.type) {
1978 case ixgbe_phy_ext_1g_t:
1979 case ixgbe_phy_sgmii:
1980 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1982 case ixgbe_phy_x550em_kr:
1983 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1984 /* check different backplane modes */
1985 if (hw->phy.nw_mng_if_sel &
1986 IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
1987 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
1989 } else if (hw->device_id ==
1990 IXGBE_DEV_ID_X550EM_A_KR_L) {
1991 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1997 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1998 IXGBE_LINK_SPEED_1GB_FULL;
2004 return IXGBE_SUCCESS;
2008 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
2009 * @hw: pointer to hardware structure
2010 * @lsc: pointer to boolean flag which indicates whether external Base T
2011 * PHY interrupt is lsc
2013 * Determime if external Base T PHY interrupt cause is high temperature
2014 * failure alarm or link status change.
2016 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2017 * failure alarm, else return PHY access status.
2019 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
2026 /* Vendor alarm triggered */
2027 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2028 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2031 if (status != IXGBE_SUCCESS ||
2032 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
2035 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
2036 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
2037 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2040 if (status != IXGBE_SUCCESS ||
2041 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2042 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
2045 /* Global alarm triggered */
2046 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
2047 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2050 if (status != IXGBE_SUCCESS)
2053 /* If high temperature failure, then return over temp error and exit */
2054 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
2055 /* power down the PHY in case the PHY FW didn't already */
2056 ixgbe_set_copper_phy_power(hw, false);
2057 return IXGBE_ERR_OVERTEMP;
2058 } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
2059 /* device fault alarm triggered */
2060 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
2061 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2064 if (status != IXGBE_SUCCESS)
2067 /* if device fault was due to high temp alarm handle and exit */
2068 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
2069 /* power down the PHY in case the PHY FW didn't */
2070 ixgbe_set_copper_phy_power(hw, false);
2071 return IXGBE_ERR_OVERTEMP;
2075 /* Vendor alarm 2 triggered */
2076 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2077 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
2079 if (status != IXGBE_SUCCESS ||
2080 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
2083 /* link connect/disconnect event occurred */
2084 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
2085 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
2087 if (status != IXGBE_SUCCESS)
2091 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2094 return IXGBE_SUCCESS;
2098 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2099 * @hw: pointer to hardware structure
2101 * Enable link status change and temperature failure alarm for the external
2104 * Returns PHY access status
2106 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2112 /* Clear interrupt flags */
2113 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2115 /* Enable link status change alarm */
2117 /* Enable the LASI interrupts on X552 devices to receive notifications
2118 * of the link configurations of the external PHY and correspondingly
2119 * support the configuration of the internal iXFI link, since iXFI does
2120 * not support auto-negotiation. This is not required for X553 devices
2121 * having KR support, which performs auto-negotiations and which is used
2122 * as the internal link to the external PHY. Hence adding a check here
2123 * to avoid enabling LASI interrupts for X553 devices.
2125 if (hw->mac.type != ixgbe_mac_X550EM_a) {
2126 status = hw->phy.ops.read_reg(hw,
2127 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2128 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
2130 if (status != IXGBE_SUCCESS)
2133 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2135 status = hw->phy.ops.write_reg(hw,
2136 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2137 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
2139 if (status != IXGBE_SUCCESS)
2143 /* Enable high temperature failure and global fault alarms */
2144 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2145 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2148 if (status != IXGBE_SUCCESS)
2151 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2152 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2154 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2155 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2158 if (status != IXGBE_SUCCESS)
2161 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2162 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2163 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2166 if (status != IXGBE_SUCCESS)
2169 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2170 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2172 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2173 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2176 if (status != IXGBE_SUCCESS)
2179 /* Enable chip-wide vendor alarm */
2180 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2181 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2184 if (status != IXGBE_SUCCESS)
2187 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2189 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2190 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2197 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2198 * @hw: pointer to hardware structure
2199 * @speed: link speed
2201 * Configures the integrated KR PHY.
2203 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2204 ixgbe_link_speed speed)
2209 status = hw->mac.ops.read_iosf_sb_reg(hw,
2210 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2211 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2215 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2216 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2217 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2219 /* Advertise 10G support. */
2220 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2221 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2223 /* Advertise 1G support. */
2224 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2225 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2227 status = hw->mac.ops.write_iosf_sb_reg(hw,
2228 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2229 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2231 if (hw->mac.type == ixgbe_mac_X550EM_a) {
2232 /* Set lane mode to KR auto negotiation */
2233 status = hw->mac.ops.read_iosf_sb_reg(hw,
2234 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2235 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2240 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2241 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2242 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2243 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2244 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2246 status = hw->mac.ops.write_iosf_sb_reg(hw,
2247 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2248 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2251 return ixgbe_restart_an_internal_phy_x550em(hw);
2255 * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs
2256 * @hw: pointer to hardware structure
2258 static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw)
2260 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
2263 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2264 return IXGBE_SUCCESS;
2266 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store);
2269 memset(store, 0, sizeof(store));
2271 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store);
2275 return ixgbe_setup_fw_link(hw);
2279 * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp
2280 * @hw: pointer to hardware structure
2282 static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw)
2284 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
2287 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store);
2291 if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) {
2292 ixgbe_shutdown_fw_phy(hw);
2293 return IXGBE_ERR_OVERTEMP;
2295 return IXGBE_SUCCESS;
2299 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2300 * @hw: pointer to hardware structure
2302 * Read NW_MNG_IF_SEL register and save field values, and check for valid field
2305 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2307 /* Save NW management interface connected on board. This is used
2308 * to determine internal PHY mode.
2310 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2312 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2313 * PHY address. This register field was has only been used for X552.
2315 if (hw->mac.type == ixgbe_mac_X550EM_a &&
2316 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2317 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2318 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2319 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2322 return IXGBE_SUCCESS;
2326 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2327 * @hw: pointer to hardware structure
2329 * Initialize any function pointers that were not able to be
2330 * set during init_shared_code because the PHY/SFP type was
2331 * not known. Perform the SFP init if necessary.
2333 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2335 struct ixgbe_phy_info *phy = &hw->phy;
2338 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2340 hw->mac.ops.set_lan_id(hw);
2341 ixgbe_read_mng_if_sel_x550em(hw);
2343 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2344 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2345 ixgbe_setup_mux_ctl(hw);
2346 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2349 switch (hw->device_id) {
2350 case IXGBE_DEV_ID_X550EM_A_1G_T:
2351 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2352 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2353 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2354 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2355 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2356 phy->ops.check_overtemp = ixgbe_check_overtemp_fw;
2358 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2360 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2363 case IXGBE_DEV_ID_X550EM_A_10G_T:
2364 case IXGBE_DEV_ID_X550EM_A_SFP:
2365 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2366 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2368 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2370 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2372 case IXGBE_DEV_ID_X550EM_X_SFP:
2373 /* set up for CS4227 usage */
2374 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2376 case IXGBE_DEV_ID_X550EM_X_1G_T:
2377 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2378 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2384 /* Identify the PHY or SFP module */
2385 ret_val = phy->ops.identify(hw);
2386 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED ||
2387 ret_val == IXGBE_ERR_PHY_ADDR_INVALID)
2390 /* Setup function pointers based on detected hardware */
2391 ixgbe_init_mac_link_ops_X550em(hw);
2392 if (phy->sfp_type != ixgbe_sfp_type_unknown)
2393 phy->ops.reset = NULL;
2395 /* Set functions pointers based on phy type */
2396 switch (hw->phy.type) {
2397 case ixgbe_phy_x550em_kx4:
2398 phy->ops.setup_link = NULL;
2399 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2400 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2402 case ixgbe_phy_x550em_kr:
2403 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2404 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2405 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2407 case ixgbe_phy_ext_1g_t:
2408 /* link is managed by FW */
2409 phy->ops.setup_link = NULL;
2411 case ixgbe_phy_x550em_xfi:
2412 /* link is managed by HW */
2413 phy->ops.setup_link = NULL;
2414 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2415 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2417 case ixgbe_phy_x550em_ext_t:
2418 /* If internal link mode is XFI, then setup iXFI internal link,
2419 * else setup KR now.
2421 phy->ops.setup_internal_link =
2422 ixgbe_setup_internal_phy_t_x550em;
2424 /* setup SW LPLU only for first revision of X550EM_x */
2425 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2426 !(IXGBE_FUSES0_REV_MASK &
2427 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2428 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2430 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2431 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2433 case ixgbe_phy_sgmii:
2434 phy->ops.setup_link = NULL;
2437 phy->ops.setup_link = ixgbe_setup_fw_link;
2438 phy->ops.reset = ixgbe_reset_phy_fw;
2447 * ixgbe_set_mdio_speed - Set MDIO clock speed
2448 * @hw: pointer to hardware structure
2450 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2454 switch (hw->device_id) {
2455 case IXGBE_DEV_ID_X550EM_X_10G_T:
2456 case IXGBE_DEV_ID_X550EM_A_SGMII:
2457 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2458 case IXGBE_DEV_ID_X550EM_A_10G_T:
2459 case IXGBE_DEV_ID_X550EM_A_SFP:
2460 case IXGBE_DEV_ID_X550EM_A_QSFP:
2461 /* Config MDIO clock speed before the first MDIO PHY access */
2462 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2463 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2464 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2466 case IXGBE_DEV_ID_X550EM_A_1G_T:
2467 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2468 /* Select fast MDIO clock speed for these devices */
2469 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2470 hlreg0 |= IXGBE_HLREG0_MDCSPD;
2471 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2479 * ixgbe_reset_hw_X550em - Perform hardware reset
2480 * @hw: pointer to hardware structure
2482 * Resets the hardware by resetting the transmit and receive units, masks
2483 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2486 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2488 ixgbe_link_speed link_speed;
2492 bool link_up = false;
2494 DEBUGFUNC("ixgbe_reset_hw_X550em");
2496 /* Call adapter stop to disable Tx/Rx and clear interrupts */
2497 status = hw->mac.ops.stop_adapter(hw);
2498 if (status != IXGBE_SUCCESS)
2501 /* flush pending Tx transactions */
2502 ixgbe_clear_tx_pending(hw);
2504 ixgbe_set_mdio_speed(hw);
2506 /* PHY ops must be identified and initialized prior to reset */
2507 status = hw->phy.ops.init(hw);
2509 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2512 /* start the external PHY */
2513 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2514 status = ixgbe_init_ext_t_x550em(hw);
2519 /* Setup SFP module if there is one present. */
2520 if (hw->phy.sfp_setup_needed) {
2521 status = hw->mac.ops.setup_sfp(hw);
2522 hw->phy.sfp_setup_needed = false;
2525 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2529 if (!hw->phy.reset_disable && hw->phy.ops.reset) {
2530 if (hw->phy.ops.reset(hw) == IXGBE_ERR_OVERTEMP)
2531 return IXGBE_ERR_OVERTEMP;
2535 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
2536 * If link reset is used when link is up, it might reset the PHY when
2537 * mng is using it. If link is down or the flag to force full link
2538 * reset is set, then perform link reset.
2540 ctrl = IXGBE_CTRL_LNK_RST;
2541 if (!hw->force_full_reset) {
2542 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2544 ctrl = IXGBE_CTRL_RST;
2547 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2548 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2549 IXGBE_WRITE_FLUSH(hw);
2551 /* Poll for reset bit to self-clear meaning reset is complete */
2552 for (i = 0; i < 10; i++) {
2554 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2555 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2559 if (ctrl & IXGBE_CTRL_RST_MASK) {
2560 status = IXGBE_ERR_RESET_FAILED;
2561 DEBUGOUT("Reset polling failed to complete.\n");
2566 /* Double resets are required for recovery from certain error
2567 * conditions. Between resets, it is necessary to stall to
2568 * allow time for any pending HW events to complete.
2570 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2571 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2575 /* Store the permanent mac address */
2576 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2578 /* Store MAC address from RAR0, clear receive address registers, and
2579 * clear the multicast table. Also reset num_rar_entries to 128,
2580 * since we modify this value when programming the SAN MAC address.
2582 hw->mac.num_rar_entries = 128;
2583 hw->mac.ops.init_rx_addrs(hw);
2585 ixgbe_set_mdio_speed(hw);
2587 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2588 ixgbe_setup_mux_ctl(hw);
2594 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2595 * @hw: pointer to hardware structure
2597 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2602 status = hw->phy.ops.read_reg(hw,
2603 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2604 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2607 if (status != IXGBE_SUCCESS)
2610 /* If PHY FW reset completed bit is set then this is the first
2611 * SW instance after a power on so the PHY FW must be un-stalled.
2613 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2614 status = hw->phy.ops.read_reg(hw,
2615 IXGBE_MDIO_GLOBAL_RES_PR_10,
2616 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2619 if (status != IXGBE_SUCCESS)
2622 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2624 status = hw->phy.ops.write_reg(hw,
2625 IXGBE_MDIO_GLOBAL_RES_PR_10,
2626 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2629 if (status != IXGBE_SUCCESS)
2637 * ixgbe_setup_kr_x550em - Configure the KR PHY.
2638 * @hw: pointer to hardware structure
2640 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2642 /* leave link alone for 2.5G */
2643 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL)
2644 return IXGBE_SUCCESS;
2646 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2650 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2651 * @hw: pointer to hardware structure
2653 * Configure the external PHY and the integrated KR PHY for SFP support.
2655 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2656 ixgbe_link_speed speed,
2657 bool autoneg_wait_to_complete)
2660 u16 reg_slice, reg_val;
2661 bool setup_linear = false;
2662 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2664 /* Check if SFP module is supported and linear */
2665 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2667 /* If no SFP module present, then return success. Return success since
2668 * there is no reason to configure CS4227 and SFP not present error is
2669 * not excepted in the setup MAC link flow.
2671 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2672 return IXGBE_SUCCESS;
2674 if (ret_val != IXGBE_SUCCESS)
2677 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2678 /* Configure CS4227 LINE side to 10G SR. */
2679 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
2680 (hw->bus.lan_id << 12);
2681 reg_val = IXGBE_CS4227_SPEED_10G;
2682 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2685 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2686 (hw->bus.lan_id << 12);
2687 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2688 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2691 /* Configure CS4227 for HOST connection rate then type. */
2692 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
2693 (hw->bus.lan_id << 12);
2694 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
2695 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
2696 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2699 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
2700 (hw->bus.lan_id << 12);
2702 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2704 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2705 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2708 /* Setup XFI internal link. */
2709 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2711 /* Configure internal PHY for KR/KX. */
2712 ixgbe_setup_kr_speed_x550em(hw, speed);
2714 /* Configure CS4227 LINE side to proper mode. */
2715 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2716 (hw->bus.lan_id << 12);
2718 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2720 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2721 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2728 * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
2729 * @hw: pointer to hardware structure
2730 * @speed: the link speed to force
2732 * Configures the integrated PHY for native SFI mode. Used to connect the
2733 * internal PHY directly to an SFP cage, without autonegotiation.
2735 STATIC s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2737 struct ixgbe_mac_info *mac = &hw->mac;
2741 /* Disable all AN and force speed to 10G Serial. */
2742 status = mac->ops.read_iosf_sb_reg(hw,
2743 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2744 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2745 if (status != IXGBE_SUCCESS)
2748 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2749 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2750 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2751 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2753 /* Select forced link speed for internal PHY. */
2755 case IXGBE_LINK_SPEED_10GB_FULL:
2756 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
2758 case IXGBE_LINK_SPEED_1GB_FULL:
2759 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2762 /* Other link speeds are not supported by internal PHY. */
2763 return IXGBE_ERR_LINK_SETUP;
2766 status = mac->ops.write_iosf_sb_reg(hw,
2767 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2768 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2770 /* Toggle port SW reset by AN reset. */
2771 status = ixgbe_restart_an_internal_phy_x550em(hw);
2777 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2778 * @hw: pointer to hardware structure
2780 * Configure the the integrated PHY for SFP support.
2782 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2783 ixgbe_link_speed speed,
2784 bool autoneg_wait_to_complete)
2788 bool setup_linear = false;
2789 u32 reg_slice, reg_phy_int, slice_offset;
2791 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2793 /* Check if SFP module is supported and linear */
2794 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2796 /* If no SFP module present, then return success. Return success since
2797 * SFP not present error is not excepted in the setup MAC link flow.
2799 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2800 return IXGBE_SUCCESS;
2802 if (ret_val != IXGBE_SUCCESS)
2805 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2806 /* Configure internal PHY for native SFI based on module type */
2807 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2808 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2809 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int);
2811 if (ret_val != IXGBE_SUCCESS)
2814 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
2816 reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
2818 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2819 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2820 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2822 if (ret_val != IXGBE_SUCCESS)
2825 /* Setup SFI internal link. */
2826 ret_val = ixgbe_setup_sfi_x550a(hw, &speed);
2828 /* Configure internal PHY for KR/KX. */
2829 ixgbe_setup_kr_speed_x550em(hw, speed);
2831 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2833 DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2834 return IXGBE_ERR_PHY_ADDR_INVALID;
2837 /* Get external PHY SKU id */
2838 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,
2839 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
2841 if (ret_val != IXGBE_SUCCESS)
2844 /* When configuring quad port CS4223, the MAC instance is part
2845 * of the slice offset.
2847 if (reg_phy_ext == IXGBE_CS4223_SKU_ID)
2848 slice_offset = (hw->bus.lan_id +
2849 (hw->bus.instance_id << 1)) << 12;
2851 slice_offset = hw->bus.lan_id << 12;
2853 /* Configure CS4227/CS4223 LINE side to proper mode. */
2854 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2856 ret_val = hw->phy.ops.read_reg(hw, reg_slice,
2857 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
2859 if (ret_val != IXGBE_SUCCESS)
2862 reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) |
2863 (IXGBE_CS4227_EDC_MODE_SR << 1));
2866 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2868 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2869 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2870 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2872 /* Flush previous write with a read */
2873 ret_val = hw->phy.ops.read_reg(hw, reg_slice,
2874 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
2880 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2881 * @hw: pointer to hardware structure
2883 * iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2885 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2887 struct ixgbe_mac_info *mac = &hw->mac;
2891 /* Disable training protocol FSM. */
2892 status = mac->ops.read_iosf_sb_reg(hw,
2893 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2894 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2895 if (status != IXGBE_SUCCESS)
2897 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2898 status = mac->ops.write_iosf_sb_reg(hw,
2899 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2900 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2901 if (status != IXGBE_SUCCESS)
2904 /* Disable Flex from training TXFFE. */
2905 status = mac->ops.read_iosf_sb_reg(hw,
2906 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2907 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2908 if (status != IXGBE_SUCCESS)
2910 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2911 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2912 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2913 status = mac->ops.write_iosf_sb_reg(hw,
2914 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2915 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2916 if (status != IXGBE_SUCCESS)
2918 status = mac->ops.read_iosf_sb_reg(hw,
2919 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2920 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2921 if (status != IXGBE_SUCCESS)
2923 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2924 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2925 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2926 status = mac->ops.write_iosf_sb_reg(hw,
2927 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2928 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2929 if (status != IXGBE_SUCCESS)
2932 /* Enable override for coefficients. */
2933 status = mac->ops.read_iosf_sb_reg(hw,
2934 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2935 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2936 if (status != IXGBE_SUCCESS)
2938 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2939 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2940 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2941 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2942 status = mac->ops.write_iosf_sb_reg(hw,
2943 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2944 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2949 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2950 * @hw: pointer to hardware structure
2951 * @speed: the link speed to force
2953 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
2954 * internal and external PHY at a specific speed, without autonegotiation.
2956 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2958 struct ixgbe_mac_info *mac = &hw->mac;
2962 /* iXFI is only supported with X552 */
2963 if (mac->type != ixgbe_mac_X550EM_x)
2964 return IXGBE_ERR_LINK_SETUP;
2966 /* Disable AN and force speed to 10G Serial. */
2967 status = mac->ops.read_iosf_sb_reg(hw,
2968 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2969 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2970 if (status != IXGBE_SUCCESS)
2973 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2974 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2976 /* Select forced link speed for internal PHY. */
2978 case IXGBE_LINK_SPEED_10GB_FULL:
2979 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2981 case IXGBE_LINK_SPEED_1GB_FULL:
2982 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2985 /* Other link speeds are not supported by internal KR PHY. */
2986 return IXGBE_ERR_LINK_SETUP;
2989 status = mac->ops.write_iosf_sb_reg(hw,
2990 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2991 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2992 if (status != IXGBE_SUCCESS)
2995 /* Additional configuration needed for x550em_x */
2996 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2997 status = ixgbe_setup_ixfi_x550em_x(hw);
2998 if (status != IXGBE_SUCCESS)
3002 /* Toggle port SW reset by AN reset. */
3003 status = ixgbe_restart_an_internal_phy_x550em(hw);
3009 * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
3010 * @hw: address of hardware structure
3011 * @link_up: address of boolean to indicate link status
3013 * Returns error code if unable to get link status.
3015 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
3022 /* read this twice back to back to indicate current status */
3023 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3024 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3026 if (ret != IXGBE_SUCCESS)
3029 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3030 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3032 if (ret != IXGBE_SUCCESS)
3035 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
3037 return IXGBE_SUCCESS;
3041 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
3042 * @hw: point to hardware structure
3044 * Configures the link between the integrated KR PHY and the external X557 PHY
3045 * The driver will call this function when it gets a link status change
3046 * interrupt from the X557 PHY. This function configures the link speed
3047 * between the PHYs to match the link speed of the BASE-T link.
3049 * A return of a non-zero value indicates an error, and the base driver should
3050 * not report link up.
3052 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
3054 ixgbe_link_speed force_speed;
3059 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3060 return IXGBE_ERR_CONFIG;
3062 if (hw->mac.type == ixgbe_mac_X550EM_x &&
3063 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3064 /* If link is down, there is no setup necessary so return */
3065 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3066 if (status != IXGBE_SUCCESS)
3070 return IXGBE_SUCCESS;
3072 status = hw->phy.ops.read_reg(hw,
3073 IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3074 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3076 if (status != IXGBE_SUCCESS)
3079 /* If link is still down - no setup is required so return */
3080 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3081 if (status != IXGBE_SUCCESS)
3084 return IXGBE_SUCCESS;
3086 /* clear everything but the speed and duplex bits */
3087 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
3090 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
3091 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3093 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
3094 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3097 /* Internal PHY does not support anything else */
3098 return IXGBE_ERR_INVALID_LINK_SETTINGS;
3101 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
3103 speed = IXGBE_LINK_SPEED_10GB_FULL |
3104 IXGBE_LINK_SPEED_1GB_FULL;
3105 return ixgbe_setup_kr_speed_x550em(hw, speed);
3110 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
3111 * @hw: pointer to hardware structure
3113 * Configures the integrated KR PHY to use internal loopback mode.
3115 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
3120 /* Disable AN and force speed to 10G Serial. */
3121 status = hw->mac.ops.read_iosf_sb_reg(hw,
3122 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3123 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3124 if (status != IXGBE_SUCCESS)
3126 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3127 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3128 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3129 status = hw->mac.ops.write_iosf_sb_reg(hw,
3130 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3131 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3132 if (status != IXGBE_SUCCESS)
3135 /* Set near-end loopback clocks. */
3136 status = hw->mac.ops.read_iosf_sb_reg(hw,
3137 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3138 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3139 if (status != IXGBE_SUCCESS)
3141 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3142 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3143 status = hw->mac.ops.write_iosf_sb_reg(hw,
3144 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3145 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3146 if (status != IXGBE_SUCCESS)
3149 /* Set loopback enable. */
3150 status = hw->mac.ops.read_iosf_sb_reg(hw,
3151 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3152 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3153 if (status != IXGBE_SUCCESS)
3155 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3156 status = hw->mac.ops.write_iosf_sb_reg(hw,
3157 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3158 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3159 if (status != IXGBE_SUCCESS)
3162 /* Training bypass. */
3163 status = hw->mac.ops.read_iosf_sb_reg(hw,
3164 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3165 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3166 if (status != IXGBE_SUCCESS)
3168 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3169 status = hw->mac.ops.write_iosf_sb_reg(hw,
3170 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3171 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3177 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3178 * assuming that the semaphore is already obtained.
3179 * @hw: pointer to hardware structure
3180 * @offset: offset of word in the EEPROM to read
3181 * @data: word read from the EEPROM
3183 * Reads a 16 bit word from the EEPROM using the hostif.
3185 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
3187 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3188 struct ixgbe_hic_read_shadow_ram buffer;
3191 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3192 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3193 buffer.hdr.req.buf_lenh = 0;
3194 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3195 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3197 /* convert offset from words to bytes */
3198 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3200 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3202 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3206 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3207 IXGBE_HI_COMMAND_TIMEOUT);
3209 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3210 FW_NVM_DATA_OFFSET);
3213 hw->mac.ops.release_swfw_sync(hw, mask);
3218 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3219 * @hw: pointer to hardware structure
3220 * @offset: offset of word in the EEPROM to read
3221 * @words: number of words
3222 * @data: word(s) read from the EEPROM
3224 * Reads a 16 bit word(s) from the EEPROM using the hostif.
3226 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3227 u16 offset, u16 words, u16 *data)
3229 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3230 struct ixgbe_hic_read_shadow_ram buffer;
3231 u32 current_word = 0;
3236 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3238 /* Take semaphore for the entire operation. */
3239 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3241 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3246 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3247 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3249 words_to_read = words;
3251 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3252 buffer.hdr.req.buf_lenh = 0;
3253 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3254 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3256 /* convert offset from words to bytes */
3257 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3258 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3260 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3261 IXGBE_HI_COMMAND_TIMEOUT);
3264 DEBUGOUT("Host interface command failed\n");
3268 for (i = 0; i < words_to_read; i++) {
3269 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3271 u32 value = IXGBE_READ_REG(hw, reg);
3273 data[current_word] = (u16)(value & 0xffff);
3276 if (i < words_to_read) {
3278 data[current_word] = (u16)(value & 0xffff);
3282 words -= words_to_read;
3286 hw->mac.ops.release_swfw_sync(hw, mask);
3291 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3292 * @hw: pointer to hardware structure
3293 * @offset: offset of word in the EEPROM to write
3294 * @data: word write to the EEPROM
3296 * Write a 16 bit word to the EEPROM using the hostif.
3298 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3302 struct ixgbe_hic_write_shadow_ram buffer;
3304 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3306 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3307 buffer.hdr.req.buf_lenh = 0;
3308 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3309 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3312 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3314 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3316 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3318 IXGBE_HI_COMMAND_TIMEOUT, false);
3324 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3325 * @hw: pointer to hardware structure
3326 * @offset: offset of word in the EEPROM to write
3327 * @data: word write to the EEPROM
3329 * Write a 16 bit word to the EEPROM using the hostif.
3331 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3334 s32 status = IXGBE_SUCCESS;
3336 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3338 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3340 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3341 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3343 DEBUGOUT("write ee hostif failed to get semaphore");
3344 status = IXGBE_ERR_SWFW_SYNC;
3351 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3352 * @hw: pointer to hardware structure
3353 * @offset: offset of word in the EEPROM to write
3354 * @words: number of words
3355 * @data: word(s) write to the EEPROM
3357 * Write a 16 bit word(s) to the EEPROM using the hostif.
3359 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3360 u16 offset, u16 words, u16 *data)
3362 s32 status = IXGBE_SUCCESS;
3365 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3367 /* Take semaphore for the entire operation. */
3368 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3369 if (status != IXGBE_SUCCESS) {
3370 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3374 for (i = 0; i < words; i++) {
3375 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3378 if (status != IXGBE_SUCCESS) {
3379 DEBUGOUT("Eeprom buffered write failed\n");
3384 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3391 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3392 * @hw: pointer to hardware structure
3393 * @ptr: pointer offset in eeprom
3394 * @size: size of section pointed by ptr, if 0 first word will be used as size
3395 * @csum: address of checksum to update
3397 * Returns error status for any failure
3399 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3400 u16 size, u16 *csum, u16 *buffer,
3405 u16 length, bufsz, i, start;
3408 bufsz = sizeof(buf) / sizeof(buf[0]);
3410 /* Read a chunk at the pointer location */
3412 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3414 DEBUGOUT("Failed to read EEPROM image\n");
3419 if (buffer_size < ptr)
3420 return IXGBE_ERR_PARAM;
3421 local_buffer = &buffer[ptr];
3429 length = local_buffer[0];
3431 /* Skip pointer section if length is invalid. */
3432 if (length == 0xFFFF || length == 0 ||
3433 (ptr + length) >= hw->eeprom.word_size)
3434 return IXGBE_SUCCESS;
3437 if (buffer && ((u32)start + (u32)length > buffer_size))
3438 return IXGBE_ERR_PARAM;
3440 for (i = start; length; i++, length--) {
3441 if (i == bufsz && !buffer) {
3447 /* Read a chunk at the pointer location */
3448 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3451 DEBUGOUT("Failed to read EEPROM image\n");
3455 *csum += local_buffer[i];
3457 return IXGBE_SUCCESS;
3461 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3462 * @hw: pointer to hardware structure
3463 * @buffer: pointer to buffer containing calculated checksum
3464 * @buffer_size: size of buffer
3466 * Returns a negative error code on error, or the 16-bit checksum
3468 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3470 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3474 u16 pointer, i, size;
3476 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3478 hw->eeprom.ops.init_params(hw);
3481 /* Read pointer area */
3482 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3483 IXGBE_EEPROM_LAST_WORD + 1,
3486 DEBUGOUT("Failed to read EEPROM image\n");
3489 local_buffer = eeprom_ptrs;
3491 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3492 return IXGBE_ERR_PARAM;
3493 local_buffer = buffer;
3497 * For X550 hardware include 0x0-0x41 in the checksum, skip the
3498 * checksum word itself
3500 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3501 if (i != IXGBE_EEPROM_CHECKSUM)
3502 checksum += local_buffer[i];
3505 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
3506 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3508 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3509 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3512 pointer = local_buffer[i];
3514 /* Skip pointer section if the pointer is invalid. */
3515 if (pointer == 0xFFFF || pointer == 0 ||
3516 pointer >= hw->eeprom.word_size)
3520 case IXGBE_PCIE_GENERAL_PTR:
3521 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3523 case IXGBE_PCIE_CONFIG0_PTR:
3524 case IXGBE_PCIE_CONFIG1_PTR:
3525 size = IXGBE_PCIE_CONFIG_SIZE;
3532 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3533 buffer, buffer_size);
3538 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3540 return (s32)checksum;
3544 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3545 * @hw: pointer to hardware structure
3547 * Returns a negative error code on error, or the 16-bit checksum
3549 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3551 return ixgbe_calc_checksum_X550(hw, NULL, 0);
3555 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3556 * @hw: pointer to hardware structure
3557 * @checksum_val: calculated checksum
3559 * Performs checksum calculation and validates the EEPROM checksum. If the
3560 * caller does not need checksum_val, the value can be NULL.
3562 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3566 u16 read_checksum = 0;
3568 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3570 /* Read the first word from the EEPROM. If this times out or fails, do
3571 * not continue or we could be in for a very long wait while every
3574 status = hw->eeprom.ops.read(hw, 0, &checksum);
3576 DEBUGOUT("EEPROM read failed\n");
3580 status = hw->eeprom.ops.calc_checksum(hw);
3584 checksum = (u16)(status & 0xffff);
3586 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3591 /* Verify read checksum from EEPROM is the same as
3592 * calculated checksum
3594 if (read_checksum != checksum) {
3595 status = IXGBE_ERR_EEPROM_CHECKSUM;
3596 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3597 "Invalid EEPROM checksum");
3600 /* If the user cares, return the calculated checksum */
3602 *checksum_val = checksum;
3608 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3609 * @hw: pointer to hardware structure
3611 * After writing EEPROM to shadow RAM using EEWR register, software calculates
3612 * checksum and updates the EEPROM and instructs the hardware to update
3615 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3620 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3622 /* Read the first word from the EEPROM. If this times out or fails, do
3623 * not continue or we could be in for a very long wait while every
3626 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3628 DEBUGOUT("EEPROM read failed\n");
3632 status = ixgbe_calc_eeprom_checksum_X550(hw);
3636 checksum = (u16)(status & 0xffff);
3638 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3643 status = ixgbe_update_flash_X550(hw);
3649 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3650 * @hw: pointer to hardware structure
3652 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3654 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3656 s32 status = IXGBE_SUCCESS;
3657 union ixgbe_hic_hdr2 buffer;
3659 DEBUGFUNC("ixgbe_update_flash_X550");
3661 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3662 buffer.req.buf_lenh = 0;
3663 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3664 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3666 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3668 IXGBE_HI_COMMAND_TIMEOUT, false);
3674 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3675 * @hw: pointer to hardware structure
3677 * Determines physical layer capabilities of the current configuration.
3679 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3681 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3682 u16 ext_ability = 0;
3684 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3686 hw->phy.ops.identify(hw);
3688 switch (hw->phy.type) {
3689 case ixgbe_phy_x550em_kr:
3690 case ixgbe_phy_x550em_xfi:
3691 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3692 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3694 case ixgbe_phy_x550em_kx4:
3695 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3696 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3698 case ixgbe_phy_x550em_ext_t:
3699 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3700 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3702 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3703 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3704 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3705 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3708 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_1GB_FULL)
3709 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3710 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_100_FULL)
3711 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
3712 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_10_FULL)
3713 physical_layer |= IXGBE_PHYSICAL_LAYER_10BASE_T;
3715 case ixgbe_phy_sgmii:
3716 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3718 case ixgbe_phy_ext_1g_t:
3719 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3725 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3726 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3728 return physical_layer;
3732 * ixgbe_get_bus_info_x550em - Set PCI bus info
3733 * @hw: pointer to hardware structure
3735 * Sets bus link width and speed to unknown because X550em is
3738 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3741 DEBUGFUNC("ixgbe_get_bus_info_x550em");
3743 hw->bus.width = ixgbe_bus_width_unknown;
3744 hw->bus.speed = ixgbe_bus_speed_unknown;
3746 hw->mac.ops.set_lan_id(hw);
3748 return IXGBE_SUCCESS;
3752 * ixgbe_disable_rx_x550 - Disable RX unit
3754 * Enables the Rx DMA unit for x550
3756 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3758 u32 rxctrl, pfdtxgswc;
3760 struct ixgbe_hic_disable_rxen fw_cmd;
3762 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3764 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3765 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3766 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3767 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3768 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3769 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3770 hw->mac.set_lben = true;
3772 hw->mac.set_lben = false;
3775 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3776 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3777 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3778 fw_cmd.port_number = (u8)hw->bus.lan_id;
3780 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3781 sizeof(struct ixgbe_hic_disable_rxen),
3782 IXGBE_HI_COMMAND_TIMEOUT, true);
3784 /* If we fail - disable RX using register write */
3786 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3787 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3788 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3789 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3796 * ixgbe_enter_lplu_x550em - Transition to low power states
3797 * @hw: pointer to hardware structure
3799 * Configures Low Power Link Up on transition to low power states
3800 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3801 * X557 PHY immediately prior to entering LPLU.
3803 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3805 u16 an_10g_cntl_reg, autoneg_reg, speed;
3807 ixgbe_link_speed lcd_speed;
3811 /* SW LPLU not required on later HW revisions. */
3812 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3813 (IXGBE_FUSES0_REV_MASK &
3814 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3815 return IXGBE_SUCCESS;
3817 /* If blocked by MNG FW, then don't restart AN */
3818 if (ixgbe_check_reset_blocked(hw))
3819 return IXGBE_SUCCESS;
3821 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3822 if (status != IXGBE_SUCCESS)
3825 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3827 if (status != IXGBE_SUCCESS)
3830 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3831 * disabled, then force link down by entering low power mode.
3833 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3834 !(hw->wol_enabled || ixgbe_mng_present(hw)))
3835 return ixgbe_set_copper_phy_power(hw, FALSE);
3838 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3840 if (status != IXGBE_SUCCESS)
3843 /* If no valid LCD link speed, then force link down and exit. */
3844 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3845 return ixgbe_set_copper_phy_power(hw, FALSE);
3847 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3848 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3851 if (status != IXGBE_SUCCESS)
3854 /* If no link now, speed is invalid so take link down */
3855 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3856 if (status != IXGBE_SUCCESS)
3857 return ixgbe_set_copper_phy_power(hw, false);
3859 /* clear everything but the speed bits */
3860 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3862 /* If current speed is already LCD, then exit. */
3863 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3864 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3865 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3866 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3869 /* Clear AN completed indication */
3870 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3871 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3874 if (status != IXGBE_SUCCESS)
3877 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3878 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3881 if (status != IXGBE_SUCCESS)
3884 status = hw->phy.ops.read_reg(hw,
3885 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3886 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3889 if (status != IXGBE_SUCCESS)
3892 save_autoneg = hw->phy.autoneg_advertised;
3894 /* Setup link at least common link speed */
3895 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3897 /* restore autoneg from before setting lplu speed */
3898 hw->phy.autoneg_advertised = save_autoneg;
3904 * ixgbe_get_lcd_x550em - Determine lowest common denominator
3905 * @hw: pointer to hardware structure
3906 * @lcd_speed: pointer to lowest common link speed
3908 * Determine lowest common link speed with link partner.
3910 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3914 u16 word = hw->eeprom.ctrl_word_3;
3916 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3918 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3919 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3922 if (status != IXGBE_SUCCESS)
3925 /* If link partner advertised 1G, return 1G */
3926 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3927 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3931 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3932 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3933 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3936 /* Link partner not capable of lower speeds, return 10G */
3937 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3942 * ixgbe_setup_fc_X550em - Set up flow control
3943 * @hw: pointer to hardware structure
3945 * Called at init time to set up flow control.
3947 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3949 s32 ret_val = IXGBE_SUCCESS;
3950 u32 pause, asm_dir, reg_val;
3952 DEBUGFUNC("ixgbe_setup_fc_X550em");
3954 /* Validate the requested mode */
3955 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3956 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3957 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3958 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3962 /* 10gig parts do not have a word in the EEPROM to determine the
3963 * default flow control setting, so we explicitly set it to full.
3965 if (hw->fc.requested_mode == ixgbe_fc_default)
3966 hw->fc.requested_mode = ixgbe_fc_full;
3968 /* Determine PAUSE and ASM_DIR bits. */
3969 switch (hw->fc.requested_mode) {
3974 case ixgbe_fc_tx_pause:
3978 case ixgbe_fc_rx_pause:
3979 /* Rx Flow control is enabled and Tx Flow control is
3980 * disabled by software override. Since there really
3981 * isn't a way to advertise that we are capable of RX
3982 * Pause ONLY, we will advertise that we support both
3983 * symmetric and asymmetric Rx PAUSE, as such we fall
3984 * through to the fc_full statement. Later, we will
3985 * disable the adapter's ability to send PAUSE frames.
3992 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3993 "Flow control param set incorrectly\n");
3994 ret_val = IXGBE_ERR_CONFIG;
3998 switch (hw->device_id) {
3999 case IXGBE_DEV_ID_X550EM_X_KR:
4000 case IXGBE_DEV_ID_X550EM_A_KR:
4001 case IXGBE_DEV_ID_X550EM_A_KR_L:
4002 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
4003 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4004 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
4005 if (ret_val != IXGBE_SUCCESS)
4007 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4008 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4010 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4012 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4013 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
4014 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4015 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
4017 /* This device does not fully support AN. */
4018 hw->fc.disable_fc_autoneg = true;
4029 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
4030 * @hw: pointer to hardware structure
4032 * Enable flow control according to IEEE clause 37.
4034 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
4036 u32 link_s1, lp_an_page_low, an_cntl_1;
4037 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4038 ixgbe_link_speed speed;
4041 /* AN should have completed when the cable was plugged in.
4042 * Look for reasons to bail out. Bail out if:
4043 * - FC autoneg is disabled, or if
4046 if (hw->fc.disable_fc_autoneg) {
4047 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4048 "Flow control autoneg is disabled");
4052 hw->mac.ops.check_link(hw, &speed, &link_up, false);
4054 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4058 /* Check at auto-negotiation has completed */
4059 status = hw->mac.ops.read_iosf_sb_reg(hw,
4060 IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4061 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4063 if (status != IXGBE_SUCCESS ||
4064 (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4065 DEBUGOUT("Auto-Negotiation did not complete\n");
4066 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4070 /* Read the 10g AN autoc and LP ability registers and resolve
4071 * local flow control settings accordingly
4073 status = hw->mac.ops.read_iosf_sb_reg(hw,
4074 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4075 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
4077 if (status != IXGBE_SUCCESS) {
4078 DEBUGOUT("Auto-Negotiation did not complete\n");
4082 status = hw->mac.ops.read_iosf_sb_reg(hw,
4083 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
4084 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
4086 if (status != IXGBE_SUCCESS) {
4087 DEBUGOUT("Auto-Negotiation did not complete\n");
4091 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
4092 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
4093 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
4094 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
4095 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
4098 if (status == IXGBE_SUCCESS) {
4099 hw->fc.fc_was_autonegged = true;
4101 hw->fc.fc_was_autonegged = false;
4102 hw->fc.current_mode = hw->fc.requested_mode;
4107 * ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
4108 * @hw: pointer to hardware structure
4111 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
4113 hw->fc.fc_was_autonegged = false;
4114 hw->fc.current_mode = hw->fc.requested_mode;
4118 * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
4119 * @hw: pointer to hardware structure
4121 * Enable flow control according to IEEE clause 37.
4123 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
4125 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4126 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
4127 ixgbe_link_speed speed;
4130 /* AN should have completed when the cable was plugged in.
4131 * Look for reasons to bail out. Bail out if:
4132 * - FC autoneg is disabled, or if
4135 if (hw->fc.disable_fc_autoneg) {
4136 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4137 "Flow control autoneg is disabled");
4141 hw->mac.ops.check_link(hw, &speed, &link_up, false);
4143 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4147 /* Check if auto-negotiation has completed */
4148 status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info);
4149 if (status != IXGBE_SUCCESS ||
4150 !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) {
4151 DEBUGOUT("Auto-Negotiation did not complete\n");
4152 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4156 /* Negotiate the flow control */
4157 status = ixgbe_negotiate_fc(hw, info[0], info[0],
4158 FW_PHY_ACT_GET_LINK_INFO_FC_RX,
4159 FW_PHY_ACT_GET_LINK_INFO_FC_TX,
4160 FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX,
4161 FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX);
4164 if (status == IXGBE_SUCCESS) {
4165 hw->fc.fc_was_autonegged = true;
4167 hw->fc.fc_was_autonegged = false;
4168 hw->fc.current_mode = hw->fc.requested_mode;
4173 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4174 * @hw: pointer to hardware structure
4176 * Called at init time to set up flow control.
4178 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4180 s32 status = IXGBE_SUCCESS;
4183 DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4185 /* Validate the requested mode */
4186 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4187 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4188 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4189 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4192 if (hw->fc.requested_mode == ixgbe_fc_default)
4193 hw->fc.requested_mode = ixgbe_fc_full;
4195 /* Set up the 1G and 10G flow control advertisement registers so the
4196 * HW will be able to do FC autoneg once the cable is plugged in. If
4197 * we link at 10G, the 1G advertisement is harmless and vice versa.
4199 status = hw->mac.ops.read_iosf_sb_reg(hw,
4200 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4201 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4203 if (status != IXGBE_SUCCESS) {
4204 DEBUGOUT("Auto-Negotiation did not complete\n");
4208 /* The possible values of fc.requested_mode are:
4209 * 0: Flow control is completely disabled
4210 * 1: Rx flow control is enabled (we can receive pause frames,
4211 * but not send pause frames).
4212 * 2: Tx flow control is enabled (we can send pause frames but
4213 * we do not support receiving pause frames).
4214 * 3: Both Rx and Tx flow control (symmetric) are enabled.
4217 switch (hw->fc.requested_mode) {
4219 /* Flow control completely disabled by software override. */
4220 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4221 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4223 case ixgbe_fc_tx_pause:
4224 /* Tx Flow control is enabled, and Rx Flow control is
4225 * disabled by software override.
4227 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4228 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4230 case ixgbe_fc_rx_pause:
4231 /* Rx Flow control is enabled and Tx Flow control is
4232 * disabled by software override. Since there really
4233 * isn't a way to advertise that we are capable of RX
4234 * Pause ONLY, we will advertise that we support both
4235 * symmetric and asymmetric Rx PAUSE, as such we fall
4236 * through to the fc_full statement. Later, we will
4237 * disable the adapter's ability to send PAUSE frames.
4240 /* Flow control (both Rx and Tx) is enabled by SW override. */
4241 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4242 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4245 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4246 "Flow control param set incorrectly\n");
4247 return IXGBE_ERR_CONFIG;
4250 status = hw->mac.ops.write_iosf_sb_reg(hw,
4251 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4252 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4254 /* Restart auto-negotiation. */
4255 status = ixgbe_restart_an_internal_phy_x550em(hw);
4261 * ixgbe_set_mux - Set mux for port 1 access with CS4227
4262 * @hw: pointer to hardware structure
4263 * @state: set mux if 1, clear if 0
4265 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4269 if (!hw->bus.lan_id)
4271 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4273 esdp |= IXGBE_ESDP_SDP1;
4275 esdp &= ~IXGBE_ESDP_SDP1;
4276 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4277 IXGBE_WRITE_FLUSH(hw);
4281 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4282 * @hw: pointer to hardware structure
4283 * @mask: Mask to specify which semaphore to acquire
4285 * Acquires the SWFW semaphore and sets the I2C MUX
4287 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4291 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4293 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4297 if (mask & IXGBE_GSSR_I2C_MASK)
4298 ixgbe_set_mux(hw, 1);
4300 return IXGBE_SUCCESS;
4304 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4305 * @hw: pointer to hardware structure
4306 * @mask: Mask to specify which semaphore to release
4308 * Releases the SWFW semaphore and sets the I2C MUX
4310 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4312 DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4314 if (mask & IXGBE_GSSR_I2C_MASK)
4315 ixgbe_set_mux(hw, 0);
4317 ixgbe_release_swfw_sync_X540(hw, mask);
4321 * ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4322 * @hw: pointer to hardware structure
4323 * @mask: Mask to specify which semaphore to acquire
4325 * Acquires the SWFW semaphore and get the shared phy token as needed
4327 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4329 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4330 int retries = FW_PHY_TOKEN_RETRIES;
4331 s32 status = IXGBE_SUCCESS;
4333 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4336 status = IXGBE_SUCCESS;
4338 status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4341 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4342 return IXGBE_SUCCESS;
4344 status = ixgbe_get_phy_token(hw);
4345 if (status == IXGBE_SUCCESS)
4346 return IXGBE_SUCCESS;
4349 ixgbe_release_swfw_sync_X540(hw, hmask);
4350 if (status != IXGBE_ERR_TOKEN_RETRY)
4358 * ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4359 * @hw: pointer to hardware structure
4360 * @mask: Mask to specify which semaphore to release
4362 * Releases the SWFW semaphore and puts the shared phy token as needed
4364 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4366 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4368 DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4370 if (mask & IXGBE_GSSR_TOKEN_SM)
4371 ixgbe_put_phy_token(hw);
4374 ixgbe_release_swfw_sync_X540(hw, hmask);
4378 * ixgbe_read_phy_reg_x550a - Reads specified PHY register
4379 * @hw: pointer to hardware structure
4380 * @reg_addr: 32 bit address of PHY register to read
4381 * @phy_data: Pointer to read data from PHY register
4383 * Reads a value from a specified PHY register using the SWFW lock and PHY
4384 * Token. The PHY Token is needed since the MDIO is shared between to MAC
4387 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4388 u32 device_type, u16 *phy_data)
4391 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4393 DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4395 if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4396 return IXGBE_ERR_SWFW_SYNC;
4398 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4400 hw->mac.ops.release_swfw_sync(hw, mask);
4406 * ixgbe_write_phy_reg_x550a - Writes specified PHY register
4407 * @hw: pointer to hardware structure
4408 * @reg_addr: 32 bit PHY register to write
4409 * @device_type: 5 bit device type
4410 * @phy_data: Data to write to the PHY register
4412 * Writes a value to specified PHY register using the SWFW lock and PHY Token.
4413 * The PHY Token is needed since the MDIO is shared between to MAC instances.
4415 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4416 u32 device_type, u16 phy_data)
4419 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4421 DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4423 if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4424 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
4426 hw->mac.ops.release_swfw_sync(hw, mask);
4428 status = IXGBE_ERR_SWFW_SYNC;
4435 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4436 * @hw: pointer to hardware structure
4438 * Handle external Base T PHY interrupt. If high temperature
4439 * failure alarm then return error, else if link status change
4440 * then setup internal/external PHY link
4442 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4443 * failure alarm, else return PHY access status.
4445 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4450 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4452 if (status != IXGBE_SUCCESS)
4456 return ixgbe_setup_internal_phy(hw);
4458 return IXGBE_SUCCESS;
4462 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4463 * @hw: pointer to hardware structure
4464 * @speed: new link speed
4465 * @autoneg_wait_to_complete: true when waiting for completion is needed
4467 * Setup internal/external PHY link speed based on link speed, then set
4468 * external PHY auto advertised link speed.
4470 * Returns error status for any failure
4472 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4473 ixgbe_link_speed speed,
4474 bool autoneg_wait_to_complete)
4477 ixgbe_link_speed force_speed;
4479 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4481 /* Setup internal/external PHY link speed to iXFI (10G), unless
4482 * only 1G is auto advertised then setup KX link.
4484 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4485 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4487 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4489 /* If X552 and internal link mode is XFI, then setup XFI internal link.
4491 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4492 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4493 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4495 if (status != IXGBE_SUCCESS)
4499 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4503 * ixgbe_check_link_t_X550em - Determine link and speed status
4504 * @hw: pointer to hardware structure
4505 * @speed: pointer to link speed
4506 * @link_up: true when link is up
4507 * @link_up_wait_to_complete: bool used to wait for link up or not
4509 * Check that both the MAC and X557 external PHY have link.
4511 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4512 bool *link_up, bool link_up_wait_to_complete)
4515 u16 i, autoneg_status = 0;
4517 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4518 return IXGBE_ERR_CONFIG;
4520 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4521 link_up_wait_to_complete);
4523 /* If check link fails or MAC link is not up, then return */
4524 if (status != IXGBE_SUCCESS || !(*link_up))
4527 /* MAC link is up, so check external PHY link.
4528 * X557 PHY. Link status is latching low, and can only be used to detect
4529 * link drop, and not the current status of the link without performing
4530 * back-to-back reads.
4532 for (i = 0; i < 2; i++) {
4533 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4534 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4537 if (status != IXGBE_SUCCESS)
4541 /* If external PHY link is not up, then indicate link not up */
4542 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4545 return IXGBE_SUCCESS;
4549 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4550 * @hw: pointer to hardware structure
4552 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4556 status = ixgbe_reset_phy_generic(hw);
4558 if (status != IXGBE_SUCCESS)
4561 /* Configure Link Status Alarm and Temperature Threshold interrupts */
4562 return ixgbe_enable_lasi_ext_t_x550em(hw);
4566 * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4567 * @hw: pointer to hardware structure
4568 * @led_idx: led number to turn on
4570 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4574 DEBUGFUNC("ixgbe_led_on_t_X550em");
4576 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4577 return IXGBE_ERR_PARAM;
4579 /* To turn on the LED, set mode to ON. */
4580 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4581 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4582 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4583 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4584 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4586 return IXGBE_SUCCESS;
4590 * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4591 * @hw: pointer to hardware structure
4592 * @led_idx: led number to turn off
4594 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4598 DEBUGFUNC("ixgbe_led_off_t_X550em");
4600 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4601 return IXGBE_ERR_PARAM;
4603 /* To turn on the LED, set mode to ON. */
4604 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4605 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4606 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4607 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4608 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4610 return IXGBE_SUCCESS;
4614 * ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware
4615 * @hw: pointer to the HW structure
4616 * @maj: driver version major number
4617 * @min: driver version minor number
4618 * @build: driver version build number
4619 * @sub: driver version sub build number
4620 * @len: length of driver_ver string
4621 * @driver_ver: driver string
4623 * Sends driver version number to firmware through the manageability
4624 * block. On success return IXGBE_SUCCESS
4625 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4626 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4628 s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,
4629 u8 build, u8 sub, u16 len, const char *driver_ver)
4631 struct ixgbe_hic_drv_info2 fw_cmd;
4632 s32 ret_val = IXGBE_SUCCESS;
4635 DEBUGFUNC("ixgbe_set_fw_drv_ver_x550");
4637 if ((len == 0) || (driver_ver == NULL) ||
4638 (len > sizeof(fw_cmd.driver_string)))
4639 return IXGBE_ERR_INVALID_ARGUMENT;
4641 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4642 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len;
4643 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4644 fw_cmd.port_num = (u8)hw->bus.func;
4645 fw_cmd.ver_maj = maj;
4646 fw_cmd.ver_min = min;
4647 fw_cmd.ver_build = build;
4648 fw_cmd.ver_sub = sub;
4649 fw_cmd.hdr.checksum = 0;
4650 memcpy(fw_cmd.driver_string, driver_ver, len);
4651 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4652 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4654 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4655 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4657 IXGBE_HI_COMMAND_TIMEOUT,
4659 if (ret_val != IXGBE_SUCCESS)
4662 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4663 FW_CEM_RESP_STATUS_SUCCESS)
4664 ret_val = IXGBE_SUCCESS;
4666 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;