drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  44 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw);
  45
  46 /**
  47  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  48  *  @hw: pointer to hardware structure
  49  *
  50  *  Initialize the function pointers and assign the MAC type for X550.
  51  *  Does not touch the hardware.
  52  **/
  53 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  54 {
  55         struct ixgbe_mac_info *mac = &hw->mac;
  56         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  57         s32 ret_val;
  58
  59         DEBUGFUNC("ixgbe_init_ops_X550");
  60
  61         ret_val = ixgbe_init_ops_X540(hw);
  62         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  63         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  64         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  65         mac->ops.setup_eee = NULL;
  66         mac->ops.set_source_address_pruning =
  67                         ixgbe_set_source_address_pruning_X550;
  68         mac->ops.set_ethertype_anti_spoofing =
  69                         ixgbe_set_ethertype_anti_spoofing_X550;
  70
  71         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  72         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  73         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  74         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  75         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  76         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  77         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  78         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  79         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  80
  81         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  82         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  83         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  84         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  85         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  86         /* Manageability interface */
  87         mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_x550;
  88         switch (hw->device_id) {
  89         case IXGBE_DEV_ID_X550EM_X_1G_T:
  90                 hw->mac.ops.led_on = NULL;
  91                 hw->mac.ops.led_off = NULL;
  92                 break;
  93         case IXGBE_DEV_ID_X550EM_X_10G_T:
  94         case IXGBE_DEV_ID_X550EM_A_10G_T:
  95                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  96                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  97                 break;
  98         default:
  99                 break;
 100         }
 101         return ret_val;
 102 }
 103
 104 /**
 105  * ixgbe_read_cs4227 - Read CS4227 register
 106  * @hw: pointer to hardware structure
 107  * @reg: register number to write
 108  * @value: pointer to receive value read
 109  *
 110  * Returns status code
 111  **/
 112 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
 113 {
 114         return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
 115 }
 116
 117 /**
 118  * ixgbe_write_cs4227 - Write CS4227 register
 119  * @hw: pointer to hardware structure
 120  * @reg: register number to write
 121  * @value: value to write to register
 122  *
 123  * Returns status code
 124  **/
 125 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 126 {
 127         return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
 128 }
 129
 130 /**
 131  * ixgbe_read_pe - Read register from port expander
 132  * @hw: pointer to hardware structure
 133  * @reg: register number to read
 134  * @value: pointer to receive read value
 135  *
 136  * Returns status code
 137  **/
 138 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 139 {
 140         s32 status;
 141
 142         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 143         if (status != IXGBE_SUCCESS)
 144                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 145                               "port expander access failed with %d\n", status);
 146         return status;
 147 }
 148
 149 /**
 150  * ixgbe_write_pe - Write register to port expander
 151  * @hw: pointer to hardware structure
 152  * @reg: register number to write
 153  * @value: value to write
 154  *
 155  * Returns status code
 156  **/
 157 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 158 {
 159         s32 status;
 160
 161         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 162         if (status != IXGBE_SUCCESS)
 163                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 164                               "port expander access failed with %d\n", status);
 165         return status;
 166 }
 167
 168 /**
 169  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 170  * @hw: pointer to hardware structure
 171  *
 172  * This function assumes that the caller has acquired the proper semaphore.
 173  * Returns error code
 174  **/
 175 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 176 {
 177         s32 status;
 178         u32 retry;
 179         u16 value;
 180         u8 reg;
 181
 182         /* Trigger hard reset. */
 183         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 184         if (status != IXGBE_SUCCESS)
 185                 return status;
 186         reg |= IXGBE_PE_BIT1;
 187         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 188         if (status != IXGBE_SUCCESS)
 189                 return status;
 190
 191         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 192         if (status != IXGBE_SUCCESS)
 193                 return status;
 194         reg &= ~IXGBE_PE_BIT1;
 195         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 196         if (status != IXGBE_SUCCESS)
 197                 return status;
 198
 199         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 200         if (status != IXGBE_SUCCESS)
 201                 return status;
 202         reg &= ~IXGBE_PE_BIT1;
 203         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 204         if (status != IXGBE_SUCCESS)
 205                 return status;
 206
 207         usec_delay(IXGBE_CS4227_RESET_HOLD);
 208
 209         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 210         if (status != IXGBE_SUCCESS)
 211                 return status;
 212         reg |= IXGBE_PE_BIT1;
 213         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 214         if (status != IXGBE_SUCCESS)
 215                 return status;
 216
 217         /* Wait for the reset to complete. */
 218         msec_delay(IXGBE_CS4227_RESET_DELAY);
 219         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 220                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 221                                            &value);
 222                 if (status == IXGBE_SUCCESS &&
 223                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 224                         break;
 225                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 226         }
 227         if (retry == IXGBE_CS4227_RETRIES) {
 228                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 229                         "CS4227 reset did not complete.");
 230                 return IXGBE_ERR_PHY;
 231         }
 232
 233         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 234         if (status != IXGBE_SUCCESS ||
 235             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 236                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 237                         "CS4227 EEPROM did not load successfully.");
 238                 return IXGBE_ERR_PHY;
 239         }
 240
 241         return IXGBE_SUCCESS;
 242 }
 243
 244 /**
 245  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 246  * @hw: pointer to hardware structure
 247  **/
 248 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 249 {
 250         s32 status = IXGBE_SUCCESS;
 251         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 252         u16 value = 0;
 253         u8 retry;
 254
 255         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 256                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 257                 if (status != IXGBE_SUCCESS) {
 258                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 259                                 "semaphore failed with %d", status);
 260                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 261                         continue;
 262                 }
 263
 264                 /* Get status of reset flow. */
 265                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 266
 267                 if (status == IXGBE_SUCCESS &&
 268                     value == IXGBE_CS4227_RESET_COMPLETE)
 269                         goto out;
 270
 271                 if (status != IXGBE_SUCCESS ||
 272                     value != IXGBE_CS4227_RESET_PENDING)
 273                         break;
 274
 275                 /* Reset is pending. Wait and check again. */
 276                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 277                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 278         }
 279
 280         /* If still pending, assume other instance failed. */
 281         if (retry == IXGBE_CS4227_RETRIES) {
 282                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 283                 if (status != IXGBE_SUCCESS) {
 284                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 285                                       "semaphore failed with %d", status);
 286                         return;
 287                 }
 288         }
 289
 290         /* Reset the CS4227. */
 291         status = ixgbe_reset_cs4227(hw);
 292         if (status != IXGBE_SUCCESS) {
 293                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 294                         "CS4227 reset failed: %d", status);
 295                 goto out;
 296         }
 297
 298         /* Reset takes so long, temporarily release semaphore in case the
 299          * other driver instance is waiting for the reset indication.
 300          */
 301         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 302                            IXGBE_CS4227_RESET_PENDING);
 303         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 304         msec_delay(10);
 305         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 306         if (status != IXGBE_SUCCESS) {
 307                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 308                         "semaphore failed with %d", status);
 309                 return;
 310         }
 311
 312         /* Record completion for next time. */
 313         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 314                 IXGBE_CS4227_RESET_COMPLETE);
 315
 316 out:
 317         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 318         msec_delay(hw->eeprom.semaphore_delay);
 319 }
 320
 321 /**
 322  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 323  * @hw: pointer to hardware structure
 324  **/
 325 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 326 {
 327         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 328
 329         if (hw->bus.lan_id) {
 330                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 331                 esdp |= IXGBE_ESDP_SDP1_DIR;
 332         }
 333         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 334         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 335         IXGBE_WRITE_FLUSH(hw);
 336 }
 337
 338 /**
 339  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 340  * @hw: pointer to hardware structure
 341  *
 342  * Returns error code
 343  */
 344 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 345 {
 346         hw->mac.ops.set_lan_id(hw);
 347
 348         ixgbe_read_mng_if_sel_x550em(hw);
 349
 350         switch (hw->device_id) {
 351         case IXGBE_DEV_ID_X550EM_A_SFP:
 352                 return ixgbe_identify_module_generic(hw);
 353         case IXGBE_DEV_ID_X550EM_X_SFP:
 354                 /* set up for CS4227 usage */
 355                 ixgbe_setup_mux_ctl(hw);
 356                 ixgbe_check_cs4227(hw);
 357                 /* Fallthrough */
 358
 359         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 360                 return ixgbe_identify_module_generic(hw);
 361                 break;
 362         case IXGBE_DEV_ID_X550EM_X_KX4:
 363                 hw->phy.type = ixgbe_phy_x550em_kx4;
 364                 break;
 365         case IXGBE_DEV_ID_X550EM_X_XFI:
 366                 hw->phy.type = ixgbe_phy_x550em_xfi;
 367                 break;
 368         case IXGBE_DEV_ID_X550EM_X_KR:
 369         case IXGBE_DEV_ID_X550EM_A_KR:
 370         case IXGBE_DEV_ID_X550EM_A_KR_L:
 371                 hw->phy.type = ixgbe_phy_x550em_kr;
 372                 break;
 373         case IXGBE_DEV_ID_X550EM_A_10G_T:
 374         case IXGBE_DEV_ID_X550EM_X_10G_T:
 375                 return ixgbe_identify_phy_generic(hw);
 376         case IXGBE_DEV_ID_X550EM_X_1G_T:
 377                 hw->phy.type = ixgbe_phy_ext_1g_t;
 378                 break;
 379         case IXGBE_DEV_ID_X550EM_A_1G_T:
 380         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 381                 hw->phy.type = ixgbe_phy_fw;
 382                 if (hw->bus.lan_id)
 383                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 384                 else
 385                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 386                 break;
 387         default:
 388                 break;
 389         }
 390         return IXGBE_SUCCESS;
 391 }
 392
 393 /**
 394  * ixgbe_fw_phy_activity - Perform an activity on a PHY
 395  * @hw: pointer to hardware structure
 396  * @activity: activity to perform
 397  * @data: Pointer to 4 32-bit words of data
 398  */
 399 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,
 400                           u32 (*data)[FW_PHY_ACT_DATA_COUNT])
 401 {
 402         union {
 403                 struct ixgbe_hic_phy_activity_req cmd;
 404                 struct ixgbe_hic_phy_activity_resp rsp;
 405         } hic;
 406         u16 retries = FW_PHY_ACT_RETRIES;
 407         s32 rc;
 408         u16 i;
 409
 410         do {
 411                 memset(&hic, 0, sizeof(hic));
 412                 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD;
 413                 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN;
 414                 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 415                 hic.cmd.port_number = hw->bus.lan_id;
 416                 hic.cmd.activity_id = IXGBE_CPU_TO_LE16(activity);
 417                 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
 418                         hic.cmd.data[i] = IXGBE_CPU_TO_BE32((*data)[i]);
 419
 420                 rc = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
 421                                                   sizeof(hic.cmd),
 422                                                   IXGBE_HI_COMMAND_TIMEOUT,
 423                                                   true);
 424                 if (rc != IXGBE_SUCCESS)
 425                         return rc;
 426                 if (hic.rsp.hdr.cmd_or_resp.ret_status ==
 427                     FW_CEM_RESP_STATUS_SUCCESS) {
 428                         for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
 429                                 (*data)[i] = IXGBE_BE32_TO_CPU(hic.rsp.data[i]);
 430                         return IXGBE_SUCCESS;
 431                 }
 432                 usec_delay(20);
 433                 --retries;
 434         } while (retries > 0);
 435
 436         return IXGBE_ERR_HOST_INTERFACE_COMMAND;
 437 }
 438
 439 static const struct {
 440         u16 fw_speed;
 441         ixgbe_link_speed phy_speed;
 442 } ixgbe_fw_map[] = {
 443         { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL },
 444         { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL },
 445         { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL },
 446         { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL },
 447         { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL },
 448         { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL },
 449 };
 450
 451 /**
 452  * ixgbe_get_phy_id_fw - Get the phy ID via firmware command
 453  * @hw: pointer to hardware structure
 454  *
 455  * Returns error code
 456  */
 457 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw)
 458 {
 459         u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
 460         u16 phy_speeds;
 461         u16 phy_id_lo;
 462         s32 rc;
 463         u16 i;
 464
 465         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info);
 466         if (rc)
 467                 return rc;
 468
 469         hw->phy.speeds_supported = 0;
 470         phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK;
 471         for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
 472                 if (phy_speeds & ixgbe_fw_map[i].fw_speed)
 473                         hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed;
 474         }
 475         if (!hw->phy.autoneg_advertised)
 476                 hw->phy.autoneg_advertised = hw->phy.speeds_supported;
 477
 478         hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK;
 479         phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK;
 480         hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK;
 481         hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK;
 482         if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK)
 483                 return IXGBE_ERR_PHY_ADDR_INVALID;
 484         return IXGBE_SUCCESS;
 485 }
 486
 487 /**
 488  * ixgbe_identify_phy_fw - Get PHY type based on firmware command
 489  * @hw: pointer to hardware structure
 490  *
 491  * Returns error code
 492  */
 493 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw)
 494 {
 495         if (hw->bus.lan_id)
 496                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 497         else
 498                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 499
 500         hw->phy.type = ixgbe_phy_fw;
 501         hw->phy.ops.read_reg = NULL;
 502         hw->phy.ops.write_reg = NULL;
 503         return ixgbe_get_phy_id_fw(hw);
 504 }
 505
 506 /**
 507  * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY
 508  * @hw: pointer to hardware structure
 509  *
 510  * Returns error code
 511  */
 512 s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw)
 513 {
 514         u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
 515
 516         setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF;
 517         return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup);
 518 }
 519
 520 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 521                                      u32 device_type, u16 *phy_data)
 522 {
 523         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 524         return IXGBE_NOT_IMPLEMENTED;
 525 }
 526
 527 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 528                                       u32 device_type, u16 phy_data)
 529 {
 530         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 531         return IXGBE_NOT_IMPLEMENTED;
 532 }
 533
 534 /**
 535  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 536  * @hw: pointer to the hardware structure
 537  * @addr: I2C bus address to read from
 538  * @reg: I2C device register to read from
 539  * @val: pointer to location to receive read value
 540  *
 541  * Returns an error code on error.
 542  **/
 543 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 544                                            u16 reg, u16 *val)
 545 {
 546         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 547 }
 548
 549 /**
 550  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 551  * @hw: pointer to the hardware structure
 552  * @addr: I2C bus address to read from
 553  * @reg: I2C device register to read from
 554  * @val: pointer to location to receive read value
 555  *
 556  * Returns an error code on error.
 557  **/
 558 STATIC s32
 559 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 560                                          u16 reg, u16 *val)
 561 {
 562         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 563 }
 564
 565 /**
 566  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 567  * @hw: pointer to the hardware structure
 568  * @addr: I2C bus address to write to
 569  * @reg: I2C device register to write to
 570  * @val: value to write
 571  *
 572  * Returns an error code on error.
 573  **/
 574 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 575                                             u8 addr, u16 reg, u16 val)
 576 {
 577         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 578 }
 579
 580 /**
 581  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 582  * @hw: pointer to the hardware structure
 583  * @addr: I2C bus address to write to
 584  * @reg: I2C device register to write to
 585  * @val: value to write
 586  *
 587  * Returns an error code on error.
 588  **/
 589 STATIC s32
 590 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 591                                           u8 addr, u16 reg, u16 val)
 592 {
 593         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 594 }
 595
 596 /**
 597 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 598 *  @hw: pointer to hardware structure
 599 *
 600 *  Initialize the function pointers and for MAC type X550EM.
 601 *  Does not touch the hardware.
 602 **/
 603 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 604 {
 605         struct ixgbe_mac_info *mac = &hw->mac;
 606         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 607         struct ixgbe_phy_info *phy = &hw->phy;
 608         s32 ret_val;
 609
 610         DEBUGFUNC("ixgbe_init_ops_X550EM");
 611
 612         /* Similar to X550 so start there. */
 613         ret_val = ixgbe_init_ops_X550(hw);
 614
 615         /* Since this function eventually calls
 616          * ixgbe_init_ops_540 by design, we are setting
 617          * the pointers to NULL explicitly here to overwrite
 618          * the values being set in the x540 function.
 619          */
 620         /* Thermal sensor not supported in x550EM */
 621         mac->ops.get_thermal_sensor_data = NULL;
 622         mac->ops.init_thermal_sensor_thresh = NULL;
 623         mac->thermal_sensor_enabled = false;
 624
 625         /* FCOE not supported in x550EM */
 626         mac->ops.get_san_mac_addr = NULL;
 627         mac->ops.set_san_mac_addr = NULL;
 628         mac->ops.get_wwn_prefix = NULL;
 629         mac->ops.get_fcoe_boot_status = NULL;
 630
 631         /* IPsec not supported in x550EM */
 632         mac->ops.disable_sec_rx_path = NULL;
 633         mac->ops.enable_sec_rx_path = NULL;
 634
 635         /* AUTOC register is not present in x550EM. */
 636         mac->ops.prot_autoc_read = NULL;
 637         mac->ops.prot_autoc_write = NULL;
 638
 639         /* X550EM bus type is internal*/
 640         hw->bus.type = ixgbe_bus_type_internal;
 641         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 642
 643
 644         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 645         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 646         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 647         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 648         mac->ops.get_supported_physical_layer =
 649                                     ixgbe_get_supported_physical_layer_X550em;
 650
 651         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 652                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 653         else
 654                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 655
 656         /* PHY */
 657         phy->ops.init = ixgbe_init_phy_ops_X550em;
 658         switch (hw->device_id) {
 659         case IXGBE_DEV_ID_X550EM_A_1G_T:
 660         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 661                 mac->ops.setup_fc = NULL;
 662                 phy->ops.identify = ixgbe_identify_phy_fw;
 663                 phy->ops.set_phy_power = NULL;
 664                 phy->ops.get_firmware_version = NULL;
 665                 break;
 666         case IXGBE_DEV_ID_X550EM_X_1G_T:
 667                 mac->ops.setup_fc = NULL;
 668                 phy->ops.identify = ixgbe_identify_phy_x550em;
 669                 phy->ops.set_phy_power = NULL;
 670                 break;
 671         default:
 672                 phy->ops.identify = ixgbe_identify_phy_x550em;
 673         }
 674
 675         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 676                 phy->ops.set_phy_power = NULL;
 677
 678
 679         /* EEPROM */
 680         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 681         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 682         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 683         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 684         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 685         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 686         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 687         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 688
 689         return ret_val;
 690 }
 691
 692 /**
 693  * ixgbe_setup_fw_link - Setup firmware-controlled PHYs
 694  * @hw: pointer to hardware structure
 695  */
 696 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw)
 697 {
 698         u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
 699         s32 rc;
 700         u16 i;
 701
 702         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
 703                 return 0;
 704
 705         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
 706                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
 707                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
 708                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
 709         }
 710
 711         switch (hw->fc.requested_mode) {
 712         case ixgbe_fc_full:
 713                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX <<
 714                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 715                 break;
 716         case ixgbe_fc_rx_pause:
 717                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX <<
 718                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 719                 break;
 720         case ixgbe_fc_tx_pause:
 721                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX <<
 722                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 723                 break;
 724         default:
 725                 break;
 726         }
 727
 728         for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
 729                 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)
 730                         setup[0] |= ixgbe_fw_map[i].fw_speed;
 731         }
 732         setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN;
 733
 734         if (hw->phy.eee_speeds_advertised)
 735                 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE;
 736
 737         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup);
 738         if (rc)
 739                 return rc;
 740         if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN)
 741                 return IXGBE_ERR_OVERTEMP;
 742         return IXGBE_SUCCESS;
 743 }
 744
 745 /**
 746  * ixgbe_fc_autoneg_fw _ Set up flow control for FW-controlled PHYs
 747  * @hw: pointer to hardware structure
 748  *
 749  *  Called at init time to set up flow control.
 750  */
 751 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw)
 752 {
 753         if (hw->fc.requested_mode == ixgbe_fc_default)
 754                 hw->fc.requested_mode = ixgbe_fc_full;
 755
 756         return ixgbe_setup_fw_link(hw);
 757 }
 758
 759 /**
 760  * ixgbe_setup_eee_fw - Enable/disable EEE support
 761  * @hw: pointer to the HW structure
 762  * @enable_eee: boolean flag to enable EEE
 763  *
 764  * Enable/disable EEE based on enable_eee flag.
 765  * This function controls EEE for firmware-based PHY implementations.
 766  */
 767 static s32 ixgbe_setup_eee_fw(struct ixgbe_hw *hw, bool enable_eee)
 768 {
 769         if (!!hw->phy.eee_speeds_advertised == enable_eee)
 770                 return IXGBE_SUCCESS;
 771         if (enable_eee)
 772                 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
 773         else
 774                 hw->phy.eee_speeds_advertised = 0;
 775         return hw->phy.ops.setup_link(hw);
 776 }
 777
 778 /**
 779 *  ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
 780 *  @hw: pointer to hardware structure
 781 *
 782 *  Initialize the function pointers and for MAC type X550EM_a.
 783 *  Does not touch the hardware.
 784 **/
 785 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
 786 {
 787         struct ixgbe_mac_info *mac = &hw->mac;
 788         s32 ret_val;
 789
 790         DEBUGFUNC("ixgbe_init_ops_X550EM_a");
 791
 792         /* Start with generic X550EM init */
 793         ret_val = ixgbe_init_ops_X550EM(hw);
 794
 795         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
 796             hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) {
 797                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 798                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 799         } else {
 800                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
 801                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
 802         }
 803         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
 804         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
 805
 806         switch (mac->ops.get_media_type(hw)) {
 807         case ixgbe_media_type_fiber:
 808                 mac->ops.setup_fc = NULL;
 809                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
 810                 break;
 811         case ixgbe_media_type_backplane:
 812                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
 813                 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
 814                 break;
 815         default:
 816                 break;
 817         }
 818
 819         switch (hw->device_id) {
 820         case IXGBE_DEV_ID_X550EM_A_1G_T:
 821         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 822                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
 823                 mac->ops.setup_fc = ixgbe_fc_autoneg_fw;
 824                 mac->ops.setup_eee = ixgbe_setup_eee_fw;
 825                 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL |
 826                                                IXGBE_LINK_SPEED_1GB_FULL;
 827                 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
 828                 break;
 829         default:
 830                 break;
 831         }
 832
 833         return ret_val;
 834 }
 835
 836 /**
 837 *  ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
 838 *  @hw: pointer to hardware structure
 839 *
 840 *  Initialize the function pointers and for MAC type X550EM_x.
 841 *  Does not touch the hardware.
 842 **/
 843 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
 844 {
 845         struct ixgbe_mac_info *mac = &hw->mac;
 846         struct ixgbe_link_info *link = &hw->link;
 847         s32 ret_val;
 848
 849         DEBUGFUNC("ixgbe_init_ops_X550EM_x");
 850
 851         /* Start with generic X550EM init */
 852         ret_val = ixgbe_init_ops_X550EM(hw);
 853
 854         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 855         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 856         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 857         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 858         link->ops.read_link = ixgbe_read_i2c_combined_generic;
 859         link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
 860         link->ops.write_link = ixgbe_write_i2c_combined_generic;
 861         link->ops.write_link_unlocked =
 862                                       ixgbe_write_i2c_combined_generic_unlocked;
 863         link->addr = IXGBE_CS4227;
 864
 865         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T) {
 866                 mac->ops.setup_fc = NULL;
 867                 mac->ops.setup_eee = NULL;
 868                 mac->ops.init_led_link_act = NULL;
 869         }
 870
 871         return ret_val;
 872 }
 873
 874 /**
 875  *  ixgbe_dmac_config_X550
 876  *  @hw: pointer to hardware structure
 877  *
 878  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 879  *  When disabling dmac, dmac enable dmac bit is cleared.
 880  **/
 881 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 882 {
 883         u32 reg, high_pri_tc;
 884
 885         DEBUGFUNC("ixgbe_dmac_config_X550");
 886
 887         /* Disable DMA coalescing before configuring */
 888         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 889         reg &= ~IXGBE_DMACR_DMAC_EN;
 890         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 891
 892         /* Disable DMA Coalescing if the watchdog timer is 0 */
 893         if (!hw->mac.dmac_config.watchdog_timer)
 894                 goto out;
 895
 896         ixgbe_dmac_config_tcs_X550(hw);
 897
 898         /* Configure DMA Coalescing Control Register */
 899         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 900
 901         /* Set the watchdog timer in units of 40.96 usec */
 902         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 903         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 904
 905         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 906         /* If fcoe is enabled, set high priority traffic class */
 907         if (hw->mac.dmac_config.fcoe_en) {
 908                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 909                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 910                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 911         }
 912         reg |= IXGBE_DMACR_EN_MNG_IND;
 913
 914         /* Enable DMA coalescing after configuration */
 915         reg |= IXGBE_DMACR_DMAC_EN;
 916         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 917
 918 out:
 919         return IXGBE_SUCCESS;
 920 }
 921
 922 /**
 923  *  ixgbe_dmac_config_tcs_X550
 924  *  @hw: pointer to hardware structure
 925  *
 926  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 927  *  be cleared before configuring.
 928  **/
 929 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 930 {
 931         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 932
 933         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 934
 935         /* Configure DMA coalescing enabled */
 936         switch (hw->mac.dmac_config.link_speed) {
 937         case IXGBE_LINK_SPEED_10_FULL:
 938         case IXGBE_LINK_SPEED_100_FULL:
 939                 pb_headroom = IXGBE_DMACRXT_100M;
 940                 break;
 941         case IXGBE_LINK_SPEED_1GB_FULL:
 942                 pb_headroom = IXGBE_DMACRXT_1G;
 943                 break;
 944         default:
 945                 pb_headroom = IXGBE_DMACRXT_10G;
 946                 break;
 947         }
 948
 949         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 950                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 951
 952         /* Set the per Rx packet buffer receive threshold */
 953         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 954                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 955                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 956
 957                 if (tc < hw->mac.dmac_config.num_tcs) {
 958                         /* Get Rx PB size */
 959                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 960                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 961                                 IXGBE_RXPBSIZE_SHIFT;
 962
 963                         /* Calculate receive buffer threshold in kilobytes */
 964                         if (rx_pb_size > pb_headroom)
 965                                 rx_pb_size = rx_pb_size - pb_headroom;
 966                         else
 967                                 rx_pb_size = 0;
 968
 969                         /* Minimum of MFS shall be set for DMCTH */
 970                         reg |= (rx_pb_size > maxframe_size_kb) ?
 971                                 rx_pb_size : maxframe_size_kb;
 972                 }
 973                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 974         }
 975         return IXGBE_SUCCESS;
 976 }
 977
 978 /**
 979  *  ixgbe_dmac_update_tcs_X550
 980  *  @hw: pointer to hardware structure
 981  *
 982  *  Disables dmac, updates per TC settings, and then enables dmac.
 983  **/
 984 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 985 {
 986         u32 reg;
 987
 988         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 989
 990         /* Disable DMA coalescing before configuring */
 991         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 992         reg &= ~IXGBE_DMACR_DMAC_EN;
 993         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 994
 995         ixgbe_dmac_config_tcs_X550(hw);
 996
 997         /* Enable DMA coalescing after configuration */
 998         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 999         reg |= IXGBE_DMACR_DMAC_EN;
1000         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
1001
1002         return IXGBE_SUCCESS;
1003 }
1004
1005 /**
1006  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
1007  *  @hw: pointer to hardware structure
1008  *
1009  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
1010  *  ixgbe_hw struct in order to set up EEPROM access.
1011  **/
1012 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
1013 {
1014         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1015         u32 eec;
1016         u16 eeprom_size;
1017
1018         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
1019
1020         if (eeprom->type == ixgbe_eeprom_uninitialized) {
1021                 eeprom->semaphore_delay = 10;
1022                 eeprom->type = ixgbe_flash;
1023
1024                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1025                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1026                                     IXGBE_EEC_SIZE_SHIFT);
1027                 eeprom->word_size = 1 << (eeprom_size +
1028                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
1029
1030                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
1031                           eeprom->type, eeprom->word_size);
1032         }
1033
1034         return IXGBE_SUCCESS;
1035 }
1036
1037 /**
1038  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1039  * @hw: pointer to hardware structure
1040  * @enable: enable or disable source address pruning
1041  * @pool: Rx pool to set source address pruning for
1042  **/
1043 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1044                                            unsigned int pool)
1045 {
1046         u64 pfflp;
1047
1048         /* max rx pool is 63 */
1049         if (pool > 63)
1050                 return;
1051
1052         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1053         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1054
1055         if (enable)
1056                 pfflp |= (1ULL << pool);
1057         else
1058                 pfflp &= ~(1ULL << pool);
1059
1060         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1061         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1062 }
1063
1064 /**
1065  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1066  *  @hw: pointer to hardware structure
1067  *  @enable: enable or disable switch for Ethertype anti-spoofing
1068  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1069  *
1070  **/
1071 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1072                 bool enable, int vf)
1073 {
1074         int vf_target_reg = vf >> 3;
1075         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1076         u32 pfvfspoof;
1077
1078         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1079
1080         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1081         if (enable)
1082                 pfvfspoof |= (1 << vf_target_shift);
1083         else
1084                 pfvfspoof &= ~(1 << vf_target_shift);
1085
1086         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1087 }
1088
1089 /**
1090  * ixgbe_iosf_wait - Wait for IOSF command completion
1091  * @hw: pointer to hardware structure
1092  * @ctrl: pointer to location to receive final IOSF control value
1093  *
1094  * Returns failing status on timeout
1095  *
1096  * Note: ctrl can be NULL if the IOSF control register value is not needed
1097  **/
1098 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1099 {
1100         u32 i, command = 0;
1101
1102         /* Check every 10 usec to see if the address cycle completed.
1103          * The SB IOSF BUSY bit will clear when the operation is
1104          * complete
1105          */
1106         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1107                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1108                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1109                         break;
1110                 usec_delay(10);
1111         }
1112         if (ctrl)
1113                 *ctrl = command;
1114         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1115                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1116                 return IXGBE_ERR_PHY;
1117         }
1118
1119         return IXGBE_SUCCESS;
1120 }
1121
1122 /**
1123  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register
1124  *  of the IOSF device
1125  *  @hw: pointer to hardware structure
1126  *  @reg_addr: 32 bit PHY register to write
1127  *  @device_type: 3 bit device type
1128  *  @data: Data to write to the register
1129  **/
1130 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1131                             u32 device_type, u32 data)
1132 {
1133         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1134         u32 command, error;
1135         s32 ret;
1136
1137         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1138         if (ret != IXGBE_SUCCESS)
1139                 return ret;
1140
1141         ret = ixgbe_iosf_wait(hw, NULL);
1142         if (ret != IXGBE_SUCCESS)
1143                 goto out;
1144
1145         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1146                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1147
1148         /* Write IOSF control register */
1149         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1150
1151         /* Write IOSF data register */
1152         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1153
1154         ret = ixgbe_iosf_wait(hw, &command);
1155
1156         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1157                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1158                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1159                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1160                               "Failed to write, error %x\n", error);
1161                 ret = IXGBE_ERR_PHY;
1162         }
1163
1164 out:
1165         ixgbe_release_swfw_semaphore(hw, gssr);
1166         return ret;
1167 }
1168
1169 /**
1170  *  ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device
1171  *  @hw: pointer to hardware structure
1172  *  @reg_addr: 32 bit PHY register to write
1173  *  @device_type: 3 bit device type
1174  *  @data: Pointer to read data from the register
1175  **/
1176 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1177                            u32 device_type, u32 *data)
1178 {
1179         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1180         u32 command, error;
1181         s32 ret;
1182
1183         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1184         if (ret != IXGBE_SUCCESS)
1185                 return ret;
1186
1187         ret = ixgbe_iosf_wait(hw, NULL);
1188         if (ret != IXGBE_SUCCESS)
1189                 goto out;
1190
1191         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1192                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1193
1194         /* Write IOSF control register */
1195         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1196
1197         ret = ixgbe_iosf_wait(hw, &command);
1198
1199         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1200                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1201                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1202                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1203                                 "Failed to read, error %x\n", error);
1204                 ret = IXGBE_ERR_PHY;
1205         }
1206
1207         if (ret == IXGBE_SUCCESS)
1208                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1209
1210 out:
1211         ixgbe_release_swfw_semaphore(hw, gssr);
1212         return ret;
1213 }
1214
1215 /**
1216  * ixgbe_get_phy_token - Get the token for shared phy access
1217  * @hw: Pointer to hardware structure
1218  */
1219
1220 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1221 {
1222         struct ixgbe_hic_phy_token_req token_cmd;
1223         s32 status;
1224
1225         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1226         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1227         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1228         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1229         token_cmd.port_number = hw->bus.lan_id;
1230         token_cmd.command_type = FW_PHY_TOKEN_REQ;
1231         token_cmd.pad = 0;
1232         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1233                                               sizeof(token_cmd),
1234                                               IXGBE_HI_COMMAND_TIMEOUT,
1235                                               true);
1236         if (status) {
1237                 DEBUGOUT1("Issuing host interface command failed with Status = %d\n",
1238                           status);
1239                 return status;
1240         }
1241         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1242                 return IXGBE_SUCCESS;
1243         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY) {
1244                 DEBUGOUT1("Host interface command returned 0x%08x , returning IXGBE_ERR_FW_RESP_INVALID\n",
1245                           token_cmd.hdr.cmd_or_resp.ret_status);
1246                 return IXGBE_ERR_FW_RESP_INVALID;
1247         }
1248
1249         DEBUGOUT("Returning  IXGBE_ERR_TOKEN_RETRY\n");
1250         return IXGBE_ERR_TOKEN_RETRY;
1251 }
1252
1253 /**
1254  * ixgbe_put_phy_token - Put the token for shared phy access
1255  * @hw: Pointer to hardware structure
1256  */
1257
1258 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1259 {
1260         struct ixgbe_hic_phy_token_req token_cmd;
1261         s32 status;
1262
1263         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1264         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1265         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1266         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1267         token_cmd.port_number = hw->bus.lan_id;
1268         token_cmd.command_type = FW_PHY_TOKEN_REL;
1269         token_cmd.pad = 0;
1270         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1271                                               sizeof(token_cmd),
1272                                               IXGBE_HI_COMMAND_TIMEOUT,
1273                                               true);
1274         if (status)
1275                 return status;
1276         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1277                 return IXGBE_SUCCESS;
1278
1279         DEBUGOUT("Put PHY Token host interface command failed");
1280         return IXGBE_ERR_FW_RESP_INVALID;
1281 }
1282
1283 /**
1284  *  ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1285  *  of the IOSF device
1286  *  @hw: pointer to hardware structure
1287  *  @reg_addr: 32 bit PHY register to write
1288  *  @device_type: 3 bit device type
1289  *  @data: Data to write to the register
1290  **/
1291 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1292                                   u32 device_type, u32 data)
1293 {
1294         struct ixgbe_hic_internal_phy_req write_cmd;
1295         s32 status;
1296         UNREFERENCED_1PARAMETER(device_type);
1297
1298         memset(&write_cmd, 0, sizeof(write_cmd));
1299         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1300         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1301         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1302         write_cmd.port_number = hw->bus.lan_id;
1303         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1304         write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1305         write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1306
1307         status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1308                                               sizeof(write_cmd),
1309                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1310
1311         return status;
1312 }
1313
1314 /**
1315  *  ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device
1316  *  @hw: pointer to hardware structure
1317  *  @reg_addr: 32 bit PHY register to write
1318  *  @device_type: 3 bit device type
1319  *  @data: Pointer to read data from the register
1320  **/
1321 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1322                                  u32 device_type, u32 *data)
1323 {
1324         union {
1325                 struct ixgbe_hic_internal_phy_req cmd;
1326                 struct ixgbe_hic_internal_phy_resp rsp;
1327         } hic;
1328         s32 status;
1329         UNREFERENCED_1PARAMETER(device_type);
1330
1331         memset(&hic, 0, sizeof(hic));
1332         hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1333         hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1334         hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1335         hic.cmd.port_number = hw->bus.lan_id;
1336         hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1337         hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1338
1339         status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1340                                               sizeof(hic.cmd),
1341                                               IXGBE_HI_COMMAND_TIMEOUT, true);
1342
1343         /* Extract the register value from the response. */
1344         *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1345
1346         return status;
1347 }
1348
1349 /**
1350  *  ixgbe_disable_mdd_X550
1351  *  @hw: pointer to hardware structure
1352  *
1353  *  Disable malicious driver detection
1354  **/
1355 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1356 {
1357         u32 reg;
1358
1359         DEBUGFUNC("ixgbe_disable_mdd_X550");
1360
1361         /* Disable MDD for TX DMA and interrupt */
1362         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1363         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1364         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1365
1366         /* Disable MDD for RX and interrupt */
1367         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1368         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1369         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1370 }
1371
1372 /**
1373  *  ixgbe_enable_mdd_X550
1374  *  @hw: pointer to hardware structure
1375  *
1376  *  Enable malicious driver detection
1377  **/
1378 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1379 {
1380         u32 reg;
1381
1382         DEBUGFUNC("ixgbe_enable_mdd_X550");
1383
1384         /* Enable MDD for TX DMA and interrupt */
1385         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1386         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1387         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1388
1389         /* Enable MDD for RX and interrupt */
1390         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1391         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1392         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1393 }
1394
1395 /**
1396  *  ixgbe_restore_mdd_vf_X550
1397  *  @hw: pointer to hardware structure
1398  *  @vf: vf index
1399  *
1400  *  Restore VF that was disabled during malicious driver detection event
1401  **/
1402 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1403 {
1404         u32 idx, reg, num_qs, start_q, bitmask;
1405
1406         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1407
1408         /* Map VF to queues */
1409         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1410         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1411         case IXGBE_MRQC_VMDQRT8TCEN:
1412                 num_qs = 8;  /* 16 VFs / pools */
1413                 bitmask = 0x000000FF;
1414                 break;
1415         case IXGBE_MRQC_VMDQRSS32EN:
1416         case IXGBE_MRQC_VMDQRT4TCEN:
1417                 num_qs = 4;  /* 32 VFs / pools */
1418                 bitmask = 0x0000000F;
1419                 break;
1420         default:            /* 64 VFs / pools */
1421                 num_qs = 2;
1422                 bitmask = 0x00000003;
1423                 break;
1424         }
1425         start_q = vf * num_qs;
1426
1427         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1428         idx = start_q / 32;
1429         reg = 0;
1430         reg |= (bitmask << (start_q % 32));
1431         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1432         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1433 }
1434
1435 /**
1436  *  ixgbe_mdd_event_X550
1437  *  @hw: pointer to hardware structure
1438  *  @vf_bitmap: vf bitmap of malicious vfs
1439  *
1440  *  Handle malicious driver detection event.
1441  **/
1442 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1443 {
1444         u32 wqbr;
1445         u32 i, j, reg, q, shift, vf, idx;
1446
1447         DEBUGFUNC("ixgbe_mdd_event_X550");
1448
1449         /* figure out pool size for mapping to vf's */
1450         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1451         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1452         case IXGBE_MRQC_VMDQRT8TCEN:
1453                 shift = 3;  /* 16 VFs / pools */
1454                 break;
1455         case IXGBE_MRQC_VMDQRSS32EN:
1456         case IXGBE_MRQC_VMDQRT4TCEN:
1457                 shift = 2;  /* 32 VFs / pools */
1458                 break;
1459         default:
1460                 shift = 1;  /* 64 VFs / pools */
1461                 break;
1462         }
1463
1464         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1465         for (i = 0; i < 4; i++) {
1466                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1467                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1468
1469                 if (!wqbr)
1470                         continue;
1471
1472                 /* Get malicious queue */
1473                 for (j = 0; j < 32 && wqbr; j++) {
1474
1475                         if (!(wqbr & (1 << j)))
1476                                 continue;
1477
1478                         /* Get queue from bitmask */
1479                         q = j + (i * 32);
1480
1481                         /* Map queue to vf */
1482                         vf = (q >> shift);
1483
1484                         /* Set vf bit in vf_bitmap */
1485                         idx = vf / 32;
1486                         vf_bitmap[idx] |= (1 << (vf % 32));
1487                         wqbr &= ~(1 << j);
1488                 }
1489         }
1490 }
1491
1492 /**
1493  *  ixgbe_get_media_type_X550em - Get media type
1494  *  @hw: pointer to hardware structure
1495  *
1496  *  Returns the media type (fiber, copper, backplane)
1497  */
1498 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1499 {
1500         enum ixgbe_media_type media_type;
1501
1502         DEBUGFUNC("ixgbe_get_media_type_X550em");
1503
1504         /* Detect if there is a copper PHY attached. */
1505         switch (hw->device_id) {
1506         case IXGBE_DEV_ID_X550EM_X_KR:
1507         case IXGBE_DEV_ID_X550EM_X_KX4:
1508         case IXGBE_DEV_ID_X550EM_X_XFI:
1509         case IXGBE_DEV_ID_X550EM_A_KR:
1510         case IXGBE_DEV_ID_X550EM_A_KR_L:
1511                 media_type = ixgbe_media_type_backplane;
1512                 break;
1513         case IXGBE_DEV_ID_X550EM_X_SFP:
1514         case IXGBE_DEV_ID_X550EM_A_SFP:
1515         case IXGBE_DEV_ID_X550EM_A_SFP_N:
1516         case IXGBE_DEV_ID_X550EM_A_QSFP:
1517         case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1518                 media_type = ixgbe_media_type_fiber;
1519                 break;
1520         case IXGBE_DEV_ID_X550EM_X_1G_T:
1521         case IXGBE_DEV_ID_X550EM_X_10G_T:
1522         case IXGBE_DEV_ID_X550EM_A_10G_T:
1523                 media_type = ixgbe_media_type_copper;
1524                 break;
1525         case IXGBE_DEV_ID_X550EM_A_SGMII:
1526         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1527                 media_type = ixgbe_media_type_backplane;
1528                 hw->phy.type = ixgbe_phy_sgmii;
1529                 break;
1530         case IXGBE_DEV_ID_X550EM_A_1G_T:
1531         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1532                 media_type = ixgbe_media_type_copper;
1533                 break;
1534         default:
1535                 media_type = ixgbe_media_type_unknown;
1536                 break;
1537         }
1538         return media_type;
1539 }
1540
1541 /**
1542  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1543  *  @hw: pointer to hardware structure
1544  *  @linear: true if SFP module is linear
1545  */
1546 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1547 {
1548         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1549
1550         switch (hw->phy.sfp_type) {
1551         case ixgbe_sfp_type_not_present:
1552                 return IXGBE_ERR_SFP_NOT_PRESENT;
1553         case ixgbe_sfp_type_da_cu_core0:
1554         case ixgbe_sfp_type_da_cu_core1:
1555                 *linear = true;
1556                 break;
1557         case ixgbe_sfp_type_srlr_core0:
1558         case ixgbe_sfp_type_srlr_core1:
1559         case ixgbe_sfp_type_da_act_lmt_core0:
1560         case ixgbe_sfp_type_da_act_lmt_core1:
1561         case ixgbe_sfp_type_1g_sx_core0:
1562         case ixgbe_sfp_type_1g_sx_core1:
1563         case ixgbe_sfp_type_1g_lx_core0:
1564         case ixgbe_sfp_type_1g_lx_core1:
1565                 *linear = false;
1566                 break;
1567         case ixgbe_sfp_type_unknown:
1568         case ixgbe_sfp_type_1g_cu_core0:
1569         case ixgbe_sfp_type_1g_cu_core1:
1570         default:
1571                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1572         }
1573
1574         return IXGBE_SUCCESS;
1575 }
1576
1577 /**
1578  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1579  *  @hw: pointer to hardware structure
1580  *
1581  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1582  **/
1583 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1584 {
1585         s32 status;
1586         bool linear;
1587
1588         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1589
1590         status = ixgbe_identify_module_generic(hw);
1591
1592         if (status != IXGBE_SUCCESS)
1593                 return status;
1594
1595         /* Check if SFP module is supported */
1596         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1597
1598         return status;
1599 }
1600
1601 /**
1602  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1603  *  @hw: pointer to hardware structure
1604  */
1605 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1606 {
1607         s32 status;
1608         bool linear;
1609
1610         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1611
1612         /* Check if SFP module is supported */
1613         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1614
1615         if (status != IXGBE_SUCCESS)
1616                 return status;
1617
1618         ixgbe_init_mac_link_ops_X550em(hw);
1619         hw->phy.ops.reset = NULL;
1620
1621         return IXGBE_SUCCESS;
1622 }
1623
1624 /**
1625 *  ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1626 *  internal PHY
1627 *  @hw: pointer to hardware structure
1628 **/
1629 STATIC s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1630 {
1631         s32 status;
1632         u32 link_ctrl;
1633
1634         /* Restart auto-negotiation. */
1635         status = hw->mac.ops.read_iosf_sb_reg(hw,
1636                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1637                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1638
1639         if (status) {
1640                 DEBUGOUT("Auto-negotiation did not complete\n");
1641                 return status;
1642         }
1643
1644         link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1645         status = hw->mac.ops.write_iosf_sb_reg(hw,
1646                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1647                                         IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1648
1649         if (hw->mac.type == ixgbe_mac_X550EM_a) {
1650                 u32 flx_mask_st20;
1651
1652                 /* Indicate to FW that AN restart has been asserted */
1653                 status = hw->mac.ops.read_iosf_sb_reg(hw,
1654                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1655                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1656
1657                 if (status) {
1658                         DEBUGOUT("Auto-negotiation did not complete\n");
1659                         return status;
1660                 }
1661
1662                 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1663                 status = hw->mac.ops.write_iosf_sb_reg(hw,
1664                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1665                                 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1666         }
1667
1668         return status;
1669 }
1670
1671 #ifndef PREBOOT_SUPPORT
1672 /**
1673  * ixgbe_setup_sgmii - Set up link for sgmii
1674  * @hw: pointer to hardware structure
1675  * @speed: new link speed
1676  * @autoneg_wait: true when waiting for completion is needed
1677  */
1678 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1679                              bool autoneg_wait)
1680 {
1681         struct ixgbe_mac_info *mac = &hw->mac;
1682         u32 lval, sval, flx_val;
1683         s32 rc;
1684
1685         rc = mac->ops.read_iosf_sb_reg(hw,
1686                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1687                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1688         if (rc)
1689                 return rc;
1690
1691         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1692         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1693         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1694         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1695         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1696         rc = mac->ops.write_iosf_sb_reg(hw,
1697                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1698                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1699         if (rc)
1700                 return rc;
1701
1702         rc = mac->ops.read_iosf_sb_reg(hw,
1703                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1704                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1705         if (rc)
1706                 return rc;
1707
1708         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1709         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1710         rc = mac->ops.write_iosf_sb_reg(hw,
1711                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1712                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1713         if (rc)
1714                 return rc;
1715
1716         rc = mac->ops.read_iosf_sb_reg(hw,
1717                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1718                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1719         if (rc)
1720                 return rc;
1721
1722         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1723         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1724         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1725         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1726         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1727
1728         rc = mac->ops.write_iosf_sb_reg(hw,
1729                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1730                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1731         if (rc)
1732                 return rc;
1733
1734         rc = ixgbe_restart_an_internal_phy_x550em(hw);
1735         if (rc)
1736                 return rc;
1737
1738         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1739 }
1740
1741 #endif /* PREBOOT_SUPPORT */
1742 /**
1743  * ixgbe_setup_sgmii_fw - Set up link for internal PHY SGMII auto-negotiation
1744  * @hw: pointer to hardware structure
1745  * @speed: new link speed
1746  * @autoneg_wait: true when waiting for completion is needed
1747  */
1748 STATIC s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1749                                 bool autoneg_wait)
1750 {
1751         struct ixgbe_mac_info *mac = &hw->mac;
1752         u32 lval, sval, flx_val;
1753         s32 rc;
1754
1755         rc = mac->ops.read_iosf_sb_reg(hw,
1756                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1757                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1758         if (rc)
1759                 return rc;
1760
1761         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1762         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1763         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1764         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1765         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1766         rc = mac->ops.write_iosf_sb_reg(hw,
1767                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1768                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1769         if (rc)
1770                 return rc;
1771
1772         rc = mac->ops.read_iosf_sb_reg(hw,
1773                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1774                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1775         if (rc)
1776                 return rc;
1777
1778         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1779         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1780         rc = mac->ops.write_iosf_sb_reg(hw,
1781                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1782                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1783         if (rc)
1784                 return rc;
1785
1786         rc = mac->ops.write_iosf_sb_reg(hw,
1787                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1788                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1789         if (rc)
1790                 return rc;
1791
1792         rc = mac->ops.read_iosf_sb_reg(hw,
1793                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1794                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1795         if (rc)
1796                 return rc;
1797
1798         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1799         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
1800         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1801         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1802         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1803
1804         rc = mac->ops.write_iosf_sb_reg(hw,
1805                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1806                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1807         if (rc)
1808                 return rc;
1809
1810         rc = ixgbe_restart_an_internal_phy_x550em(hw);
1811
1812         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1813 }
1814
1815 /**
1816  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1817  *  @hw: pointer to hardware structure
1818  */
1819 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1820 {
1821         struct ixgbe_mac_info *mac = &hw->mac;
1822
1823         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1824
1825         switch (hw->mac.ops.get_media_type(hw)) {
1826         case ixgbe_media_type_fiber:
1827                 /* CS4227 does not support autoneg, so disable the laser control
1828                  * functions for SFP+ fiber
1829                  */
1830                 mac->ops.disable_tx_laser = NULL;
1831                 mac->ops.enable_tx_laser = NULL;
1832                 mac->ops.flap_tx_laser = NULL;
1833                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1834                 mac->ops.set_rate_select_speed =
1835                                         ixgbe_set_soft_rate_select_speed;
1836
1837                 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1838                     (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1839                         mac->ops.setup_mac_link =
1840                                                 ixgbe_setup_mac_link_sfp_x550a;
1841                 else
1842                         mac->ops.setup_mac_link =
1843                                                 ixgbe_setup_mac_link_sfp_x550em;
1844                 break;
1845         case ixgbe_media_type_copper:
1846                 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T)
1847                         break;
1848                 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1849                         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
1850                             hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
1851                                 mac->ops.setup_link = ixgbe_setup_sgmii_fw;
1852                                 mac->ops.check_link =
1853                                                    ixgbe_check_mac_link_generic;
1854                         } else {
1855                                 mac->ops.setup_link =
1856                                                   ixgbe_setup_mac_link_t_X550em;
1857                         }
1858                 } else {
1859                         mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1860                         mac->ops.check_link = ixgbe_check_link_t_X550em;
1861                 }
1862                 break;
1863         case ixgbe_media_type_backplane:
1864                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1865                     hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1866 #ifdef PREBOOT_SUPPORT
1867                         mac->ops.setup_link = ixgbe_setup_sgmii_fw;
1868 #else
1869                         mac->ops.setup_link = ixgbe_setup_sgmii;
1870 #endif /* PREBOOT_SUPPORT */
1871                 break;
1872         default:
1873                 break;
1874         }
1875 }
1876
1877 /**
1878  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1879  *  @hw: pointer to hardware structure
1880  *  @speed: pointer to link speed
1881  *  @autoneg: true when autoneg or autotry is enabled
1882  */
1883 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1884                                        ixgbe_link_speed *speed,
1885                                        bool *autoneg)
1886 {
1887         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1888
1889
1890         if (hw->phy.type == ixgbe_phy_fw) {
1891                 *autoneg = true;
1892                 *speed = hw->phy.speeds_supported;
1893                 return 0;
1894         }
1895
1896         /* SFP */
1897         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1898
1899                 /* CS4227 SFP must not enable auto-negotiation */
1900                 *autoneg = false;
1901
1902                 /* Check if 1G SFP module. */
1903                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1904                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1905                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1906                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1907                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1908                         return IXGBE_SUCCESS;
1909                 }
1910
1911                 /* Link capabilities are based on SFP */
1912                 if (hw->phy.multispeed_fiber)
1913                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1914                                  IXGBE_LINK_SPEED_1GB_FULL;
1915                 else
1916                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1917         } else {
1918                 switch (hw->phy.type) {
1919                 case ixgbe_phy_ext_1g_t:
1920 #ifdef PREBOOT_SUPPORT
1921                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1922                         break;
1923 #endif /* PREBOOT_SUPPORT */
1924                 case ixgbe_phy_sgmii:
1925 #ifdef PREBOOT_SUPPORT
1926                         *speed = IXGBE_LINK_SPEED_1GB_FULL |
1927                                  IXGBE_LINK_SPEED_100_FULL |
1928                                  IXGBE_LINK_SPEED_10_FULL;
1929 #else
1930                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1931 #endif /* PREBOOT_SUPPORT */
1932                         break;
1933                 case ixgbe_phy_x550em_kr:
1934                         if (hw->mac.type == ixgbe_mac_X550EM_a) {
1935                                 /* check different backplane modes */
1936                                 if (hw->phy.nw_mng_if_sel &
1937                                            IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
1938                                         *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
1939                                         break;
1940                                 } else if (hw->device_id ==
1941                                                    IXGBE_DEV_ID_X550EM_A_KR_L) {
1942                                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1943                                         break;
1944                                 }
1945                         }
1946                         /* fall through */
1947                 default:
1948                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1949                                  IXGBE_LINK_SPEED_1GB_FULL;
1950                         break;
1951                 }
1952                 *autoneg = true;
1953         }
1954
1955         return IXGBE_SUCCESS;
1956 }
1957
1958 /**
1959  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1960  * @hw: pointer to hardware structure
1961  * @lsc: pointer to boolean flag which indicates whether external Base T
1962  *       PHY interrupt is lsc
1963  *
1964  * Determime if external Base T PHY interrupt cause is high temperature
1965  * failure alarm or link status change.
1966  *
1967  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1968  * failure alarm, else return PHY access status.
1969  */
1970 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1971 {
1972         u32 status;
1973         u16 reg;
1974
1975         *lsc = false;
1976
1977         /* Vendor alarm triggered */
1978         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1979                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1980                                       &reg);
1981
1982         if (status != IXGBE_SUCCESS ||
1983             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1984                 return status;
1985
1986         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1987         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1988                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1989                                       &reg);
1990
1991         if (status != IXGBE_SUCCESS ||
1992             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1993             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1994                 return status;
1995
1996         /* Global alarm triggered */
1997         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1998                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1999                                       &reg);
2000
2001         if (status != IXGBE_SUCCESS)
2002                 return status;
2003
2004         /* If high temperature failure, then return over temp error and exit */
2005         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
2006                 /* power down the PHY in case the PHY FW didn't already */
2007                 ixgbe_set_copper_phy_power(hw, false);
2008                 return IXGBE_ERR_OVERTEMP;
2009         } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
2010                 /*  device fault alarm triggered */
2011                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
2012                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2013                                           &reg);
2014
2015                 if (status != IXGBE_SUCCESS)
2016                         return status;
2017
2018                 /* if device fault was due to high temp alarm handle and exit */
2019                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
2020                         /* power down the PHY in case the PHY FW didn't */
2021                         ixgbe_set_copper_phy_power(hw, false);
2022                         return IXGBE_ERR_OVERTEMP;
2023                 }
2024         }
2025
2026         /* Vendor alarm 2 triggered */
2027         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2028                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2029
2030         if (status != IXGBE_SUCCESS ||
2031             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
2032                 return status;
2033
2034         /* link connect/disconnect event occurred */
2035         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
2036                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2037
2038         if (status != IXGBE_SUCCESS)
2039                 return status;
2040
2041         /* Indicate LSC */
2042         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2043                 *lsc = true;
2044
2045         return IXGBE_SUCCESS;
2046 }
2047
2048 /**
2049  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2050  * @hw: pointer to hardware structure
2051  *
2052  * Enable link status change and temperature failure alarm for the external
2053  * Base T PHY
2054  *
2055  * Returns PHY access status
2056  */
2057 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2058 {
2059         u32 status;
2060         u16 reg;
2061         bool lsc;
2062
2063         /* Clear interrupt flags */
2064         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2065
2066         /* Enable link status change alarm */
2067
2068         /* Enable the LASI interrupts on X552 devices to receive notifications
2069          * of the link configurations of the external PHY and correspondingly
2070          * support the configuration of the internal iXFI link, since iXFI does
2071          * not support auto-negotiation. This is not required for X553 devices
2072          * having KR support, which performs auto-negotiations and which is used
2073          * as the internal link to the external PHY. Hence adding a check here
2074          * to avoid enabling LASI interrupts for X553 devices.
2075          */
2076         if (hw->mac.type != ixgbe_mac_X550EM_a) {
2077                 status = hw->phy.ops.read_reg(hw,
2078                                         IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2079                                         IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2080
2081                 if (status != IXGBE_SUCCESS)
2082                         return status;
2083
2084                 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2085
2086                 status = hw->phy.ops.write_reg(hw,
2087                                         IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2088                                         IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
2089
2090                 if (status != IXGBE_SUCCESS)
2091                         return status;
2092         }
2093
2094         /* Enable high temperature failure and global fault alarms */
2095         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2096                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2097                                       &reg);
2098
2099         if (status != IXGBE_SUCCESS)
2100                 return status;
2101
2102         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2103                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2104
2105         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2106                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2107                                        reg);
2108
2109         if (status != IXGBE_SUCCESS)
2110                 return status;
2111
2112         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2113         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2114                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2115                                       &reg);
2116
2117         if (status != IXGBE_SUCCESS)
2118                 return status;
2119
2120         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2121                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2122
2123         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2124                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2125                                        reg);
2126
2127         if (status != IXGBE_SUCCESS)
2128                 return status;
2129
2130         /* Enable chip-wide vendor alarm */
2131         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2132                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2133                                       &reg);
2134
2135         if (status != IXGBE_SUCCESS)
2136                 return status;
2137
2138         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2139
2140         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2141                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2142                                        reg);
2143
2144         return status;
2145 }
2146
2147 /**
2148  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2149  *  @hw: pointer to hardware structure
2150  *  @speed: link speed
2151  *
2152  *  Configures the integrated KR PHY.
2153  **/
2154 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2155                                        ixgbe_link_speed speed)
2156 {
2157         s32 status;
2158         u32 reg_val;
2159
2160         status = hw->mac.ops.read_iosf_sb_reg(hw,
2161                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2162                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2163         if (status)
2164                 return status;
2165
2166         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2167         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2168                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2169
2170         /* Advertise 10G support. */
2171         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2172                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2173
2174         /* Advertise 1G support. */
2175         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2176                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2177
2178         status = hw->mac.ops.write_iosf_sb_reg(hw,
2179                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2180                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2181
2182         if (hw->mac.type == ixgbe_mac_X550EM_a) {
2183                 /* Set lane mode  to KR auto negotiation */
2184                 status = hw->mac.ops.read_iosf_sb_reg(hw,
2185                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2186                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2187
2188                 if (status)
2189                         return status;
2190
2191                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2192                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2193                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2194                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2195                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2196
2197                 status = hw->mac.ops.write_iosf_sb_reg(hw,
2198                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2199                                     IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2200         }
2201
2202         return ixgbe_restart_an_internal_phy_x550em(hw);
2203 }
2204
2205 /**
2206  * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs
2207  * @hw: pointer to hardware structure
2208  */
2209 static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw)
2210 {
2211         u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
2212         s32 rc;
2213
2214         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2215                 return IXGBE_SUCCESS;
2216
2217         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store);
2218         if (rc)
2219                 return rc;
2220         memset(store, 0, sizeof(store));
2221
2222         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store);
2223         if (rc)
2224                 return rc;
2225
2226         return ixgbe_setup_fw_link(hw);
2227 }
2228
2229 /**
2230  * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp
2231  * @hw: pointer to hardware structure
2232  */
2233 static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw)
2234 {
2235         u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
2236         s32 rc;
2237
2238         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store);
2239         if (rc)
2240                 return rc;
2241
2242         if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) {
2243                 ixgbe_shutdown_fw_phy(hw);
2244                 return IXGBE_ERR_OVERTEMP;
2245         }
2246         return IXGBE_SUCCESS;
2247 }
2248
2249 /**
2250  *  ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2251  *  @hw: pointer to hardware structure
2252  *
2253  *  Read NW_MNG_IF_SEL register and save field values, and check for valid field
2254  *  values.
2255  **/
2256 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2257 {
2258         /* Save NW management interface connected on board. This is used
2259          * to determine internal PHY mode.
2260          */
2261         hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2262
2263         /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2264          * PHY address. This register field was has only been used for X552.
2265          */
2266         if (hw->mac.type == ixgbe_mac_X550EM_a &&
2267             hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2268                 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2269                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2270                                IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2271         }
2272
2273         return IXGBE_SUCCESS;
2274 }
2275
2276 /**
2277  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2278  *  @hw: pointer to hardware structure
2279  *
2280  *  Initialize any function pointers that were not able to be
2281  *  set during init_shared_code because the PHY/SFP type was
2282  *  not known.  Perform the SFP init if necessary.
2283  */
2284 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2285 {
2286         struct ixgbe_phy_info *phy = &hw->phy;
2287         s32 ret_val;
2288
2289         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2290
2291         hw->mac.ops.set_lan_id(hw);
2292         ixgbe_read_mng_if_sel_x550em(hw);
2293
2294         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2295                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2296                 ixgbe_setup_mux_ctl(hw);
2297                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2298         }
2299
2300         switch (hw->device_id) {
2301         case IXGBE_DEV_ID_X550EM_A_1G_T:
2302         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2303                 phy->ops.read_reg_mdi = NULL;
2304                 phy->ops.write_reg_mdi = NULL;
2305                 hw->phy.ops.read_reg = NULL;
2306                 hw->phy.ops.write_reg = NULL;
2307                 phy->ops.check_overtemp = ixgbe_check_overtemp_fw;
2308                 if (hw->bus.lan_id)
2309                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2310                 else
2311                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2312
2313                 break;
2314         case IXGBE_DEV_ID_X550EM_A_10G_T:
2315         case IXGBE_DEV_ID_X550EM_A_SFP:
2316                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2317                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2318                 if (hw->bus.lan_id)
2319                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2320                 else
2321                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2322                 break;
2323         case IXGBE_DEV_ID_X550EM_X_SFP:
2324                 /* set up for CS4227 usage */
2325                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2326                 break;
2327         case IXGBE_DEV_ID_X550EM_X_1G_T:
2328                 phy->ops.read_reg_mdi = NULL;
2329                 phy->ops.write_reg_mdi = NULL;
2330         default:
2331                 break;
2332         }
2333
2334         /* Identify the PHY or SFP module */
2335         ret_val = phy->ops.identify(hw);
2336         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED ||
2337             ret_val == IXGBE_ERR_PHY_ADDR_INVALID)
2338                 return ret_val;
2339
2340         /* Setup function pointers based on detected hardware */
2341         ixgbe_init_mac_link_ops_X550em(hw);
2342         if (phy->sfp_type != ixgbe_sfp_type_unknown)
2343                 phy->ops.reset = NULL;
2344
2345         /* Set functions pointers based on phy type */
2346         switch (hw->phy.type) {
2347         case ixgbe_phy_x550em_kx4:
2348                 phy->ops.setup_link = NULL;
2349                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2350                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2351                 break;
2352         case ixgbe_phy_x550em_kr:
2353                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2354                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2355                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2356                 break;
2357         case ixgbe_phy_ext_1g_t:
2358                 /* link is managed by FW */
2359                 phy->ops.setup_link = NULL;
2360                 phy->ops.reset = NULL;
2361                 break;
2362         case ixgbe_phy_x550em_xfi:
2363                 /* link is managed by HW */
2364                 phy->ops.setup_link = NULL;
2365                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2366                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2367                 break;
2368         case ixgbe_phy_x550em_ext_t:
2369                 /* If internal link mode is XFI, then setup iXFI internal link,
2370                  * else setup KR now.
2371                  */
2372                 phy->ops.setup_internal_link =
2373                                               ixgbe_setup_internal_phy_t_x550em;
2374
2375                 /* setup SW LPLU only for first revision of X550EM_x */
2376                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2377                     !(IXGBE_FUSES0_REV_MASK &
2378                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2379                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2380
2381                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2382                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2383                 break;
2384         case ixgbe_phy_sgmii:
2385                 phy->ops.setup_link = NULL;
2386                 break;
2387         case ixgbe_phy_fw:
2388                 phy->ops.setup_link = ixgbe_setup_fw_link;
2389                 phy->ops.reset = ixgbe_reset_phy_fw;
2390                 break;
2391         default:
2392                 break;
2393         }
2394         return ret_val;
2395 }
2396
2397 /**
2398  * ixgbe_set_mdio_speed - Set MDIO clock speed
2399  *  @hw: pointer to hardware structure
2400  */
2401 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2402 {
2403         u32 hlreg0;
2404
2405         switch (hw->device_id) {
2406         case IXGBE_DEV_ID_X550EM_X_10G_T:
2407         case IXGBE_DEV_ID_X550EM_A_SGMII:
2408         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2409         case IXGBE_DEV_ID_X550EM_A_10G_T:
2410         case IXGBE_DEV_ID_X550EM_A_SFP:
2411         case IXGBE_DEV_ID_X550EM_A_QSFP:
2412                 /* Config MDIO clock speed before the first MDIO PHY access */
2413                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2414                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2415                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2416                 break;
2417         case IXGBE_DEV_ID_X550EM_A_1G_T:
2418         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2419                 /* Select fast MDIO clock speed for these devices */
2420                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2421                 hlreg0 |= IXGBE_HLREG0_MDCSPD;
2422                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2423                 break;
2424         default:
2425                 break;
2426         }
2427 }
2428
2429 /**
2430  *  ixgbe_reset_hw_X550em - Perform hardware reset
2431  *  @hw: pointer to hardware structure
2432  *
2433  *  Resets the hardware by resetting the transmit and receive units, masks
2434  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2435  *  reset.
2436  */
2437 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2438 {
2439         ixgbe_link_speed link_speed;
2440         s32 status;
2441         u32 ctrl = 0;
2442         u32 i;
2443         bool link_up = false;
2444         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2445
2446         DEBUGFUNC("ixgbe_reset_hw_X550em");
2447
2448         /* Call adapter stop to disable Tx/Rx and clear interrupts */
2449         status = hw->mac.ops.stop_adapter(hw);
2450         if (status != IXGBE_SUCCESS) {
2451                 DEBUGOUT1("Failed to stop adapter, STATUS = %d\n", status);
2452                 return status;
2453         }
2454         /* flush pending Tx transactions */
2455         ixgbe_clear_tx_pending(hw);
2456
2457         ixgbe_set_mdio_speed(hw);
2458
2459         /* PHY ops must be identified and initialized prior to reset */
2460         status = hw->phy.ops.init(hw);
2461
2462         if (status)
2463                 DEBUGOUT1("Failed to initialize PHY ops, STATUS = %d\n",
2464                           status);
2465
2466         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED ||
2467             status == IXGBE_ERR_PHY_ADDR_INVALID) {
2468                 DEBUGOUT("Returning from reset HW due to PHY init failure\n");
2469                 return status;
2470         }
2471
2472         /* start the external PHY */
2473         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2474                 status = ixgbe_init_ext_t_x550em(hw);
2475                 if (status) {
2476                         DEBUGOUT1("Failed to start the external PHY, STATUS = %d\n",
2477                                   status);
2478                         return status;
2479                 }
2480         }
2481
2482         /* Setup SFP module if there is one present. */
2483         if (hw->phy.sfp_setup_needed) {
2484                 status = hw->mac.ops.setup_sfp(hw);
2485                 hw->phy.sfp_setup_needed = false;
2486         }
2487
2488         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2489                 return status;
2490
2491         /* Reset PHY */
2492         if (!hw->phy.reset_disable && hw->phy.ops.reset) {
2493                 if (hw->phy.ops.reset(hw) == IXGBE_ERR_OVERTEMP)
2494                         return IXGBE_ERR_OVERTEMP;
2495         }
2496
2497 mac_reset_top:
2498         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2499          * If link reset is used when link is up, it might reset the PHY when
2500          * mng is using it.  If link is down or the flag to force full link
2501          * reset is set, then perform link reset.
2502          */
2503         ctrl = IXGBE_CTRL_LNK_RST;
2504         if (!hw->force_full_reset) {
2505                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2506                 if (link_up)
2507                         ctrl = IXGBE_CTRL_RST;
2508         }
2509
2510         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
2511         if (status != IXGBE_SUCCESS) {
2512                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
2513                         "semaphore failed with %d", status);
2514                 return IXGBE_ERR_SWFW_SYNC;
2515         }
2516         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2517         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2518         IXGBE_WRITE_FLUSH(hw);
2519         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2520
2521         /* Poll for reset bit to self-clear meaning reset is complete */
2522         for (i = 0; i < 10; i++) {
2523                 usec_delay(1);
2524                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2525                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2526                         break;
2527         }
2528
2529         if (ctrl & IXGBE_CTRL_RST_MASK) {
2530                 status = IXGBE_ERR_RESET_FAILED;
2531                 DEBUGOUT("Reset polling failed to complete.\n");
2532         }
2533
2534         msec_delay(50);
2535
2536         /* Double resets are required for recovery from certain error
2537          * conditions.  Between resets, it is necessary to stall to
2538          * allow time for any pending HW events to complete.
2539          */
2540         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2541                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2542                 goto mac_reset_top;
2543         }
2544
2545         /* Store the permanent mac address */
2546         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2547
2548         /* Store MAC address from RAR0, clear receive address registers, and
2549          * clear the multicast table.  Also reset num_rar_entries to 128,
2550          * since we modify this value when programming the SAN MAC address.
2551          */
2552         hw->mac.num_rar_entries = 128;
2553         hw->mac.ops.init_rx_addrs(hw);
2554
2555         ixgbe_set_mdio_speed(hw);
2556
2557         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2558                 ixgbe_setup_mux_ctl(hw);
2559
2560         if (status != IXGBE_SUCCESS)
2561                 DEBUGOUT1("Reset HW failed, STATUS = %d\n", status);
2562
2563         return status;
2564 }
2565
2566 /**
2567  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2568  * @hw: pointer to hardware structure
2569  */
2570 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2571 {
2572         u32 status;
2573         u16 reg;
2574
2575         status = hw->phy.ops.read_reg(hw,
2576                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2577                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2578                                       &reg);
2579
2580         if (status != IXGBE_SUCCESS)
2581                 return status;
2582
2583         /* If PHY FW reset completed bit is set then this is the first
2584          * SW instance after a power on so the PHY FW must be un-stalled.
2585          */
2586         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2587                 status = hw->phy.ops.read_reg(hw,
2588                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2589                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2590                                         &reg);
2591
2592                 if (status != IXGBE_SUCCESS)
2593                         return status;
2594
2595                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2596
2597                 status = hw->phy.ops.write_reg(hw,
2598                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2599                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2600                                         reg);
2601
2602                 if (status != IXGBE_SUCCESS)
2603                         return status;
2604         }
2605
2606         return status;
2607 }
2608
2609 /**
2610  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
2611  *  @hw: pointer to hardware structure
2612  **/
2613 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2614 {
2615         /* leave link alone for 2.5G */
2616         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL)
2617                 return IXGBE_SUCCESS;
2618
2619         if (ixgbe_check_reset_blocked(hw))
2620                 return 0;
2621
2622         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2623 }
2624
2625 /**
2626  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2627  *  @hw: pointer to hardware structure
2628  *  @speed: new link speed
2629  *  @autoneg_wait_to_complete: unused
2630  *
2631  *  Configure the external PHY and the integrated KR PHY for SFP support.
2632  **/
2633 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2634                                     ixgbe_link_speed speed,
2635                                     bool autoneg_wait_to_complete)
2636 {
2637         s32 ret_val;
2638         u16 reg_slice, reg_val;
2639         bool setup_linear = false;
2640         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2641
2642         /* Check if SFP module is supported and linear */
2643         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2644
2645         /* If no SFP module present, then return success. Return success since
2646          * there is no reason to configure CS4227 and SFP not present error is
2647          * not excepted in the setup MAC link flow.
2648          */
2649         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2650                 return IXGBE_SUCCESS;
2651
2652         if (ret_val != IXGBE_SUCCESS)
2653                 return ret_val;
2654
2655         /* Configure internal PHY for KR/KX. */
2656         ixgbe_setup_kr_speed_x550em(hw, speed);
2657
2658         /* Configure CS4227 LINE side to proper mode. */
2659         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2660                     (hw->bus.lan_id << 12);
2661         if (setup_linear)
2662                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2663         else
2664                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2665         ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2666                                           reg_val);
2667         return ret_val;
2668 }
2669
2670 /**
2671  *  ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
2672  *  @hw: pointer to hardware structure
2673  *  @speed: the link speed to force
2674  *
2675  *  Configures the integrated PHY for native SFI mode. Used to connect the
2676  *  internal PHY directly to an SFP cage, without autonegotiation.
2677  **/
2678 STATIC s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2679 {
2680         struct ixgbe_mac_info *mac = &hw->mac;
2681         s32 status;
2682         u32 reg_val;
2683
2684         /* Disable all AN and force speed to 10G Serial. */
2685         status = mac->ops.read_iosf_sb_reg(hw,
2686                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2687                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2688         if (status != IXGBE_SUCCESS)
2689                 return status;
2690
2691         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2692         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2693         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2694         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2695
2696         /* Select forced link speed for internal PHY. */
2697         switch (*speed) {
2698         case IXGBE_LINK_SPEED_10GB_FULL:
2699                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
2700                 break;
2701         case IXGBE_LINK_SPEED_1GB_FULL:
2702                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2703                 break;
2704         default:
2705                 /* Other link speeds are not supported by internal PHY. */
2706                 return IXGBE_ERR_LINK_SETUP;
2707         }
2708
2709         status = mac->ops.write_iosf_sb_reg(hw,
2710                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2711                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2712
2713         /* Toggle port SW reset by AN reset. */
2714         status = ixgbe_restart_an_internal_phy_x550em(hw);
2715
2716         return status;
2717 }
2718
2719 /**
2720  *  ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2721  *  @hw: pointer to hardware structure
2722  *  @speed: new link speed
2723  *  @autoneg_wait_to_complete: unused
2724  *
2725  *  Configure the integrated PHY for SFP support.
2726  **/
2727 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2728                                     ixgbe_link_speed speed,
2729                                     bool autoneg_wait_to_complete)
2730 {
2731         s32 ret_val;
2732         u16 reg_phy_ext;
2733         bool setup_linear = false;
2734         u32 reg_slice, reg_phy_int, slice_offset;
2735
2736         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2737
2738         /* Check if SFP module is supported and linear */
2739         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2740
2741         /* If no SFP module present, then return success. Return success since
2742          * SFP not present error is not excepted in the setup MAC link flow.
2743          */
2744         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2745                 return IXGBE_SUCCESS;
2746
2747         if (ret_val != IXGBE_SUCCESS)
2748                 return ret_val;
2749
2750         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2751                 /* Configure internal PHY for native SFI based on module type */
2752                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2753                                    IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2754                                    IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_phy_int);
2755
2756                 if (ret_val != IXGBE_SUCCESS)
2757                         return ret_val;
2758
2759                 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
2760                 if (!setup_linear)
2761                         reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
2762
2763                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2764                                    IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2765                                    IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2766
2767                 if (ret_val != IXGBE_SUCCESS)
2768                         return ret_val;
2769
2770                 /* Setup SFI internal link. */
2771                 ret_val = ixgbe_setup_sfi_x550a(hw, &speed);
2772         } else {
2773                 /* Configure internal PHY for KR/KX. */
2774                 ixgbe_setup_kr_speed_x550em(hw, speed);
2775
2776                 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2777                         /* Find Address */
2778                         DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2779                         return IXGBE_ERR_PHY_ADDR_INVALID;
2780                 }
2781
2782                 /* Get external PHY SKU id */
2783                 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,
2784                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2785
2786                 if (ret_val != IXGBE_SUCCESS)
2787                         return ret_val;
2788
2789                 /* When configuring quad port CS4223, the MAC instance is part
2790                  * of the slice offset.
2791                  */
2792                 if (reg_phy_ext == IXGBE_CS4223_SKU_ID)
2793                         slice_offset = (hw->bus.lan_id +
2794                                         (hw->bus.instance_id << 1)) << 12;
2795                 else
2796                         slice_offset = hw->bus.lan_id << 12;
2797
2798                 /* Configure CS4227/CS4223 LINE side to proper mode. */
2799                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2800
2801                 ret_val = hw->phy.ops.read_reg(hw, reg_slice,
2802                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2803
2804                 if (ret_val != IXGBE_SUCCESS)
2805                         return ret_val;
2806
2807                 reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) |
2808                                  (IXGBE_CS4227_EDC_MODE_SR << 1));
2809
2810                 if (setup_linear)
2811                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2812                 else
2813                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2814                 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2815                                          IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2816
2817                 /* Flush previous write with a read */
2818                 ret_val = hw->phy.ops.read_reg(hw, reg_slice,
2819                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2820         }
2821         return ret_val;
2822 }
2823
2824 /**
2825  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2826  *  @hw: pointer to hardware structure
2827  *
2828  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2829  **/
2830 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2831 {
2832         struct ixgbe_mac_info *mac = &hw->mac;
2833         s32 status;
2834         u32 reg_val;
2835
2836         /* Disable training protocol FSM. */
2837         status = mac->ops.read_iosf_sb_reg(hw,
2838                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2839                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2840         if (status != IXGBE_SUCCESS)
2841                 return status;
2842         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2843         status = mac->ops.write_iosf_sb_reg(hw,
2844                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2845                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2846         if (status != IXGBE_SUCCESS)
2847                 return status;
2848
2849         /* Disable Flex from training TXFFE. */
2850         status = mac->ops.read_iosf_sb_reg(hw,
2851                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2852                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2853         if (status != IXGBE_SUCCESS)
2854                 return status;
2855         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2856         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2857         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2858         status = mac->ops.write_iosf_sb_reg(hw,
2859                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2860                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2861         if (status != IXGBE_SUCCESS)
2862                 return status;
2863         status = mac->ops.read_iosf_sb_reg(hw,
2864                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2865                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2866         if (status != IXGBE_SUCCESS)
2867                 return status;
2868         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2869         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2870         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2871         status = mac->ops.write_iosf_sb_reg(hw,
2872                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2873                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2874         if (status != IXGBE_SUCCESS)
2875                 return status;
2876
2877         /* Enable override for coefficients. */
2878         status = mac->ops.read_iosf_sb_reg(hw,
2879                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2880                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2881         if (status != IXGBE_SUCCESS)
2882                 return status;
2883         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2884         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2885         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2886         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2887         status = mac->ops.write_iosf_sb_reg(hw,
2888                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2889                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2890         return status;
2891 }
2892
2893 /**
2894  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2895  *  @hw: pointer to hardware structure
2896  *  @speed: the link speed to force
2897  *
2898  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
2899  *  internal and external PHY at a specific speed, without autonegotiation.
2900  **/
2901 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2902 {
2903         struct ixgbe_mac_info *mac = &hw->mac;
2904         s32 status;
2905         u32 reg_val;
2906
2907         /* iXFI is only supported with X552 */
2908         if (mac->type != ixgbe_mac_X550EM_x)
2909                 return IXGBE_ERR_LINK_SETUP;
2910
2911         /* Disable AN and force speed to 10G Serial. */
2912         status = mac->ops.read_iosf_sb_reg(hw,
2913                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2914                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2915         if (status != IXGBE_SUCCESS)
2916                 return status;
2917
2918         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2919         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2920
2921         /* Select forced link speed for internal PHY. */
2922         switch (*speed) {
2923         case IXGBE_LINK_SPEED_10GB_FULL:
2924                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2925                 break;
2926         case IXGBE_LINK_SPEED_1GB_FULL:
2927                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2928                 break;
2929         default:
2930                 /* Other link speeds are not supported by internal KR PHY. */
2931                 return IXGBE_ERR_LINK_SETUP;
2932         }
2933
2934         status = mac->ops.write_iosf_sb_reg(hw,
2935                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2936                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2937         if (status != IXGBE_SUCCESS)
2938                 return status;
2939
2940         /* Additional configuration needed for x550em_x */
2941         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2942                 status = ixgbe_setup_ixfi_x550em_x(hw);
2943                 if (status != IXGBE_SUCCESS)
2944                         return status;
2945         }
2946
2947         /* Toggle port SW reset by AN reset. */
2948         status = ixgbe_restart_an_internal_phy_x550em(hw);
2949
2950         return status;
2951 }
2952
2953 /**
2954  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2955  * @hw: address of hardware structure
2956  * @link_up: address of boolean to indicate link status
2957  *
2958  * Returns error code if unable to get link status.
2959  */
2960 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2961 {
2962         u32 ret;
2963         u16 autoneg_status;
2964
2965         *link_up = false;
2966
2967         /* read this twice back to back to indicate current status */
2968         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2969                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2970                                    &autoneg_status);
2971         if (ret != IXGBE_SUCCESS)
2972                 return ret;
2973
2974         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2975                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2976                                    &autoneg_status);
2977         if (ret != IXGBE_SUCCESS)
2978                 return ret;
2979
2980         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2981
2982         return IXGBE_SUCCESS;
2983 }
2984
2985 /**
2986  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2987  * @hw: point to hardware structure
2988  *
2989  * Configures the link between the integrated KR PHY and the external X557 PHY
2990  * The driver will call this function when it gets a link status change
2991  * interrupt from the X557 PHY. This function configures the link speed
2992  * between the PHYs to match the link speed of the BASE-T link.
2993  *
2994  * A return of a non-zero value indicates an error, and the base driver should
2995  * not report link up.
2996  */
2997 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2998 {
2999         ixgbe_link_speed force_speed;
3000         bool link_up;
3001         u32 status;
3002         u16 speed;
3003
3004         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3005                 return IXGBE_ERR_CONFIG;
3006
3007         if (hw->mac.type == ixgbe_mac_X550EM_x &&
3008             !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3009                 /* If link is down, there is no setup necessary so return  */
3010                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3011                 if (status != IXGBE_SUCCESS)
3012                         return status;
3013
3014                 if (!link_up)
3015                         return IXGBE_SUCCESS;
3016
3017                 status = hw->phy.ops.read_reg(hw,
3018                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3019                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3020                                               &speed);
3021                 if (status != IXGBE_SUCCESS)
3022                         return status;
3023
3024                 /* If link is still down - no setup is required so return */
3025                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3026                 if (status != IXGBE_SUCCESS)
3027                         return status;
3028                 if (!link_up)
3029                         return IXGBE_SUCCESS;
3030
3031                 /* clear everything but the speed and duplex bits */
3032                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
3033
3034                 switch (speed) {
3035                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
3036                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3037                         break;
3038                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
3039                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3040                         break;
3041                 default:
3042                         /* Internal PHY does not support anything else */
3043                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
3044                 }
3045
3046                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
3047         } else {
3048                 speed = IXGBE_LINK_SPEED_10GB_FULL |
3049                         IXGBE_LINK_SPEED_1GB_FULL;
3050                 return ixgbe_setup_kr_speed_x550em(hw, speed);
3051         }
3052 }
3053
3054 /**
3055  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
3056  *  @hw: pointer to hardware structure
3057  *
3058  *  Configures the integrated KR PHY to use internal loopback mode.
3059  **/
3060 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
3061 {
3062         s32 status;
3063         u32 reg_val;
3064
3065         /* Disable AN and force speed to 10G Serial. */
3066         status = hw->mac.ops.read_iosf_sb_reg(hw,
3067                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3068                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3069         if (status != IXGBE_SUCCESS)
3070                 return status;
3071         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3072         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3073         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3074         status = hw->mac.ops.write_iosf_sb_reg(hw,
3075                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3076                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3077         if (status != IXGBE_SUCCESS)
3078                 return status;
3079
3080         /* Set near-end loopback clocks. */
3081         status = hw->mac.ops.read_iosf_sb_reg(hw,
3082                                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3083                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3084         if (status != IXGBE_SUCCESS)
3085                 return status;
3086         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3087         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3088         status = hw->mac.ops.write_iosf_sb_reg(hw,
3089                                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3090                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3091         if (status != IXGBE_SUCCESS)
3092                 return status;
3093
3094         /* Set loopback enable. */
3095         status = hw->mac.ops.read_iosf_sb_reg(hw,
3096                                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3097                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3098         if (status != IXGBE_SUCCESS)
3099                 return status;
3100         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3101         status = hw->mac.ops.write_iosf_sb_reg(hw,
3102                                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3103                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3104         if (status != IXGBE_SUCCESS)
3105                 return status;
3106
3107         /* Training bypass. */
3108         status = hw->mac.ops.read_iosf_sb_reg(hw,
3109                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3110                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3111         if (status != IXGBE_SUCCESS)
3112                 return status;
3113         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3114         status = hw->mac.ops.write_iosf_sb_reg(hw,
3115                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3116                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3117
3118         return status;
3119 }
3120
3121 /**
3122  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3123  *  assuming that the semaphore is already obtained.
3124  *  @hw: pointer to hardware structure
3125  *  @offset: offset of  word in the EEPROM to read
3126  *  @data: word read from the EEPROM
3127  *
3128  *  Reads a 16 bit word from the EEPROM using the hostif.
3129  **/
3130 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
3131 {
3132         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3133         struct ixgbe_hic_read_shadow_ram buffer;
3134         s32 status;
3135
3136         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3137         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3138         buffer.hdr.req.buf_lenh = 0;
3139         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3140         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3141
3142         /* convert offset from words to bytes */
3143         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3144         /* one word */
3145         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3146         buffer.pad2 = 0;
3147         buffer.pad3 = 0;
3148
3149         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3150         if (status)
3151                 return status;
3152
3153         status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3154                                     IXGBE_HI_COMMAND_TIMEOUT);
3155         if (!status) {
3156                 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3157                                                   FW_NVM_DATA_OFFSET);
3158         }
3159
3160         hw->mac.ops.release_swfw_sync(hw, mask);
3161         return status;
3162 }
3163
3164 /**
3165  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3166  *  @hw: pointer to hardware structure
3167  *  @offset: offset of  word in the EEPROM to read
3168  *  @words: number of words
3169  *  @data: word(s) read from the EEPROM
3170  *
3171  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
3172  **/
3173 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3174                                      u16 offset, u16 words, u16 *data)
3175 {
3176         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3177         struct ixgbe_hic_read_shadow_ram buffer;
3178         u32 current_word = 0;
3179         u16 words_to_read;
3180         s32 status;
3181         u32 i;
3182
3183         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3184
3185         /* Take semaphore for the entire operation. */
3186         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3187         if (status) {
3188                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3189                 return status;
3190         }
3191
3192         while (words) {
3193                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3194                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3195                 else
3196                         words_to_read = words;
3197
3198                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3199                 buffer.hdr.req.buf_lenh = 0;
3200                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3201                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3202
3203                 /* convert offset from words to bytes */
3204                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3205                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3206                 buffer.pad2 = 0;
3207                 buffer.pad3 = 0;
3208
3209                 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3210                                             IXGBE_HI_COMMAND_TIMEOUT);
3211
3212                 if (status) {
3213                         DEBUGOUT("Host interface command failed\n");
3214                         goto out;
3215                 }
3216
3217                 for (i = 0; i < words_to_read; i++) {
3218                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3219                                   2 * i;
3220                         u32 value = IXGBE_READ_REG(hw, reg);
3221
3222                         data[current_word] = (u16)(value & 0xffff);
3223                         current_word++;
3224                         i++;
3225                         if (i < words_to_read) {
3226                                 value >>= 16;
3227                                 data[current_word] = (u16)(value & 0xffff);
3228                                 current_word++;
3229                         }
3230                 }
3231                 words -= words_to_read;
3232         }
3233
3234 out:
3235         hw->mac.ops.release_swfw_sync(hw, mask);
3236         return status;
3237 }
3238
3239 /**
3240  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3241  *  @hw: pointer to hardware structure
3242  *  @offset: offset of  word in the EEPROM to write
3243  *  @data: word write to the EEPROM
3244  *
3245  *  Write a 16 bit word to the EEPROM using the hostif.
3246  **/
3247 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3248                                     u16 data)
3249 {
3250         s32 status;
3251         struct ixgbe_hic_write_shadow_ram buffer;
3252
3253         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3254
3255         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3256         buffer.hdr.req.buf_lenh = 0;
3257         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3258         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3259
3260          /* one word */
3261         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3262         buffer.data = data;
3263         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3264
3265         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3266                                               sizeof(buffer),
3267                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3268
3269         return status;
3270 }
3271
3272 /**
3273  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3274  *  @hw: pointer to hardware structure
3275  *  @offset: offset of  word in the EEPROM to write
3276  *  @data: word write to the EEPROM
3277  *
3278  *  Write a 16 bit word to the EEPROM using the hostif.
3279  **/
3280 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3281                                u16 data)
3282 {
3283         s32 status = IXGBE_SUCCESS;
3284
3285         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3286
3287         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3288             IXGBE_SUCCESS) {
3289                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3290                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3291         } else {
3292                 DEBUGOUT("write ee hostif failed to get semaphore");
3293                 status = IXGBE_ERR_SWFW_SYNC;
3294         }
3295
3296         return status;
3297 }
3298
3299 /**
3300  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3301  *  @hw: pointer to hardware structure
3302  *  @offset: offset of  word in the EEPROM to write
3303  *  @words: number of words
3304  *  @data: word(s) write to the EEPROM
3305  *
3306  *  Write a 16 bit word(s) to the EEPROM using the hostif.
3307  **/
3308 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3309                                       u16 offset, u16 words, u16 *data)
3310 {
3311         s32 status = IXGBE_SUCCESS;
3312         u32 i = 0;
3313
3314         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3315
3316         /* Take semaphore for the entire operation. */
3317         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3318         if (status != IXGBE_SUCCESS) {
3319                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3320                 goto out;
3321         }
3322
3323         for (i = 0; i < words; i++) {
3324                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3325                                                          data[i]);
3326
3327                 if (status != IXGBE_SUCCESS) {
3328                         DEBUGOUT("Eeprom buffered write failed\n");
3329                         break;
3330                 }
3331         }
3332
3333         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3334 out:
3335
3336         return status;
3337 }
3338
3339 /**
3340  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3341  * @hw: pointer to hardware structure
3342  * @ptr: pointer offset in eeprom
3343  * @size: size of section pointed by ptr, if 0 first word will be used as size
3344  * @csum: address of checksum to update
3345  * @buffer: pointer to buffer containing calculated checksum
3346  * @buffer_size: size of buffer
3347  *
3348  * Returns error status for any failure
3349  */
3350 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3351                                    u16 size, u16 *csum, u16 *buffer,
3352                                    u32 buffer_size)
3353 {
3354         u16 buf[256];
3355         s32 status;
3356         u16 length, bufsz, i, start;
3357         u16 *local_buffer;
3358
3359         bufsz = sizeof(buf) / sizeof(buf[0]);
3360
3361         /* Read a chunk at the pointer location */
3362         if (!buffer) {
3363                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3364                 if (status) {
3365                         DEBUGOUT("Failed to read EEPROM image\n");
3366                         return status;
3367                 }
3368                 local_buffer = buf;
3369         } else {
3370                 if (buffer_size < ptr)
3371                         return  IXGBE_ERR_PARAM;
3372                 local_buffer = &buffer[ptr];
3373         }
3374
3375         if (size) {
3376                 start = 0;
3377                 length = size;
3378         } else {
3379                 start = 1;
3380                 length = local_buffer[0];
3381
3382                 /* Skip pointer section if length is invalid. */
3383                 if (length == 0xFFFF || length == 0 ||
3384                     (ptr + length) >= hw->eeprom.word_size)
3385                         return IXGBE_SUCCESS;
3386         }
3387
3388         if (buffer && ((u32)start + (u32)length > buffer_size))
3389                 return IXGBE_ERR_PARAM;
3390
3391         for (i = start; length; i++, length--) {
3392                 if (i == bufsz && !buffer) {
3393                         ptr += bufsz;
3394                         i = 0;
3395                         if (length < bufsz)
3396                                 bufsz = length;
3397
3398                         /* Read a chunk at the pointer location */
3399                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3400                                                                   bufsz, buf);
3401                         if (status) {
3402                                 DEBUGOUT("Failed to read EEPROM image\n");
3403                                 return status;
3404                         }
3405                 }
3406                 *csum += local_buffer[i];
3407         }
3408         return IXGBE_SUCCESS;
3409 }
3410
3411 /**
3412  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3413  *  @hw: pointer to hardware structure
3414  *  @buffer: pointer to buffer containing calculated checksum
3415  *  @buffer_size: size of buffer
3416  *
3417  *  Returns a negative error code on error, or the 16-bit checksum
3418  **/
3419 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3420 {
3421         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3422         u16 *local_buffer;
3423         s32 status;
3424         u16 checksum = 0;
3425         u16 pointer, i, size;
3426
3427         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3428
3429         hw->eeprom.ops.init_params(hw);
3430
3431         if (!buffer) {
3432                 /* Read pointer area */
3433                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3434                                                      IXGBE_EEPROM_LAST_WORD + 1,
3435                                                      eeprom_ptrs);
3436                 if (status) {
3437                         DEBUGOUT("Failed to read EEPROM image\n");
3438                         return status;
3439                 }
3440                 local_buffer = eeprom_ptrs;
3441         } else {
3442                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3443                         return IXGBE_ERR_PARAM;
3444                 local_buffer = buffer;
3445         }
3446
3447         /*
3448          * For X550 hardware include 0x0-0x41 in the checksum, skip the
3449          * checksum word itself
3450          */
3451         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3452                 if (i != IXGBE_EEPROM_CHECKSUM)
3453                         checksum += local_buffer[i];
3454
3455         /*
3456          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
3457          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3458          */
3459         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3460                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3461                         continue;
3462
3463                 pointer = local_buffer[i];
3464
3465                 /* Skip pointer section if the pointer is invalid. */
3466                 if (pointer == 0xFFFF || pointer == 0 ||
3467                     pointer >= hw->eeprom.word_size)
3468                         continue;
3469
3470                 switch (i) {
3471                 case IXGBE_PCIE_GENERAL_PTR:
3472                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3473                         break;
3474                 case IXGBE_PCIE_CONFIG0_PTR:
3475                 case IXGBE_PCIE_CONFIG1_PTR:
3476                         size = IXGBE_PCIE_CONFIG_SIZE;
3477                         break;
3478                 default:
3479                         size = 0;
3480                         break;
3481                 }
3482
3483                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3484                                                 buffer, buffer_size);
3485                 if (status)
3486                         return status;
3487         }
3488
3489         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3490
3491         return (s32)checksum;
3492 }
3493
3494 /**
3495  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3496  *  @hw: pointer to hardware structure
3497  *
3498  *  Returns a negative error code on error, or the 16-bit checksum
3499  **/
3500 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3501 {
3502         return ixgbe_calc_checksum_X550(hw, NULL, 0);
3503 }
3504
3505 /**
3506  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3507  *  @hw: pointer to hardware structure
3508  *  @checksum_val: calculated checksum
3509  *
3510  *  Performs checksum calculation and validates the EEPROM checksum.  If the
3511  *  caller does not need checksum_val, the value can be NULL.
3512  **/
3513 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3514 {
3515         s32 status;
3516         u16 checksum;
3517         u16 read_checksum = 0;
3518
3519         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3520
3521         /* Read the first word from the EEPROM. If this times out or fails, do
3522          * not continue or we could be in for a very long wait while every
3523          * EEPROM read fails
3524          */
3525         status = hw->eeprom.ops.read(hw, 0, &checksum);
3526         if (status) {
3527                 DEBUGOUT("EEPROM read failed\n");
3528                 return status;
3529         }
3530
3531         status = hw->eeprom.ops.calc_checksum(hw);
3532         if (status < 0)
3533                 return status;
3534
3535         checksum = (u16)(status & 0xffff);
3536
3537         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3538                                            &read_checksum);
3539         if (status)
3540                 return status;
3541
3542         /* Verify read checksum from EEPROM is the same as
3543          * calculated checksum
3544          */
3545         if (read_checksum != checksum) {
3546                 status = IXGBE_ERR_EEPROM_CHECKSUM;
3547                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3548                              "Invalid EEPROM checksum");
3549         }
3550
3551         /* If the user cares, return the calculated checksum */
3552         if (checksum_val)
3553                 *checksum_val = checksum;
3554
3555         return status;
3556 }
3557
3558 /**
3559  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3560  * @hw: pointer to hardware structure
3561  *
3562  * After writing EEPROM to shadow RAM using EEWR register, software calculates
3563  * checksum and updates the EEPROM and instructs the hardware to update
3564  * the flash.
3565  **/
3566 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3567 {
3568         s32 status;
3569         u16 checksum = 0;
3570
3571         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3572
3573         /* Read the first word from the EEPROM. If this times out or fails, do
3574          * not continue or we could be in for a very long wait while every
3575          * EEPROM read fails
3576          */
3577         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3578         if (status) {
3579                 DEBUGOUT("EEPROM read failed\n");
3580                 return status;
3581         }
3582
3583         status = ixgbe_calc_eeprom_checksum_X550(hw);
3584         if (status < 0)
3585                 return status;
3586
3587         checksum = (u16)(status & 0xffff);
3588
3589         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3590                                             checksum);
3591         if (status)
3592                 return status;
3593
3594         status = ixgbe_update_flash_X550(hw);
3595
3596         return status;
3597 }
3598
3599 /**
3600  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3601  *  @hw: pointer to hardware structure
3602  *
3603  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3604  **/
3605 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3606 {
3607         s32 status = IXGBE_SUCCESS;
3608         union ixgbe_hic_hdr2 buffer;
3609
3610         DEBUGFUNC("ixgbe_update_flash_X550");
3611
3612         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3613         buffer.req.buf_lenh = 0;
3614         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3615         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3616
3617         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3618                                               sizeof(buffer),
3619                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3620
3621         return status;
3622 }
3623
3624 /**
3625  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3626  *  @hw: pointer to hardware structure
3627  *
3628  *  Determines physical layer capabilities of the current configuration.
3629  **/
3630 u64 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3631 {
3632         u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3633         u16 ext_ability = 0;
3634
3635         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3636
3637         hw->phy.ops.identify(hw);
3638
3639         switch (hw->phy.type) {
3640         case ixgbe_phy_x550em_kr:
3641                 if (hw->mac.type == ixgbe_mac_X550EM_a) {
3642                         if (hw->phy.nw_mng_if_sel &
3643                             IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
3644                                 physical_layer =
3645                                         IXGBE_PHYSICAL_LAYER_2500BASE_KX;
3646                                 break;
3647                         } else if (hw->device_id ==
3648                                    IXGBE_DEV_ID_X550EM_A_KR_L) {
3649                                 physical_layer =
3650                                         IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3651                                 break;
3652                         }
3653                 }
3654                 /* fall through */
3655         case ixgbe_phy_x550em_xfi:
3656                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3657                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3658                 break;
3659         case ixgbe_phy_x550em_kx4:
3660                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3661                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3662                 break;
3663         case ixgbe_phy_x550em_ext_t:
3664                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3665                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3666                                      &ext_ability);
3667                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3668                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3669                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3670                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3671                 break;
3672         case ixgbe_phy_fw:
3673                 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_1GB_FULL)
3674                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3675                 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_100_FULL)
3676                         physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
3677                 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_10_FULL)
3678                         physical_layer |= IXGBE_PHYSICAL_LAYER_10BASE_T;
3679                 break;
3680         case ixgbe_phy_sgmii:
3681 #ifdef PREBOOT_SUPPORT
3682                 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
3683                                  IXGBE_PHYSICAL_LAYER_100BASE_TX |
3684                                  IXGBE_PHYSICAL_LAYER_10BASE_T;
3685 #else
3686                 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3687 #endif /* PREBOOT_SUPPORT */
3688                 break;
3689         case ixgbe_phy_ext_1g_t:
3690                 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3691                 break;
3692         default:
3693                 break;
3694         }
3695
3696         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3697                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3698
3699         return physical_layer;
3700 }
3701
3702 /**
3703  * ixgbe_get_bus_info_x550em - Set PCI bus info
3704  * @hw: pointer to hardware structure
3705  *
3706  * Sets bus link width and speed to unknown because X550em is
3707  * not a PCI device.
3708  **/
3709 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3710 {
3711
3712         DEBUGFUNC("ixgbe_get_bus_info_x550em");
3713
3714         hw->bus.width = ixgbe_bus_width_unknown;
3715         hw->bus.speed = ixgbe_bus_speed_unknown;
3716
3717         hw->mac.ops.set_lan_id(hw);
3718
3719         return IXGBE_SUCCESS;
3720 }
3721
3722 /**
3723  * ixgbe_disable_rx_x550 - Disable RX unit
3724  * @hw: pointer to hardware structure
3725  *
3726  * Enables the Rx DMA unit for x550
3727  **/
3728 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3729 {
3730         u32 rxctrl, pfdtxgswc;
3731         s32 status;
3732         struct ixgbe_hic_disable_rxen fw_cmd;
3733
3734         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3735
3736         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3737         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3738                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3739                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3740                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3741                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3742                         hw->mac.set_lben = true;
3743                 } else {
3744                         hw->mac.set_lben = false;
3745                 }
3746
3747                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3748                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3749                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3750                 fw_cmd.port_number = (u8)hw->bus.lan_id;
3751
3752                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3753                                         sizeof(struct ixgbe_hic_disable_rxen),
3754                                         IXGBE_HI_COMMAND_TIMEOUT, true);
3755
3756                 /* If we fail - disable RX using register write */
3757                 if (status) {
3758                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3759                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3760                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3761                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3762                         }
3763                 }
3764         }
3765 }
3766
3767 /**
3768  * ixgbe_enter_lplu_x550em - Transition to low power states
3769  *  @hw: pointer to hardware structure
3770  *
3771  * Configures Low Power Link Up on transition to low power states
3772  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3773  * X557 PHY immediately prior to entering LPLU.
3774  **/
3775 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3776 {
3777         u16 an_10g_cntl_reg, autoneg_reg, speed;
3778         s32 status;
3779         ixgbe_link_speed lcd_speed;
3780         u32 save_autoneg;
3781         bool link_up;
3782
3783         /* SW LPLU not required on later HW revisions. */
3784         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3785             (IXGBE_FUSES0_REV_MASK &
3786              IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3787                 return IXGBE_SUCCESS;
3788
3789         /* If blocked by MNG FW, then don't restart AN */
3790         if (ixgbe_check_reset_blocked(hw))
3791                 return IXGBE_SUCCESS;
3792
3793         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3794         if (status != IXGBE_SUCCESS)
3795                 return status;
3796
3797         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3798
3799         if (status != IXGBE_SUCCESS)
3800                 return status;
3801
3802         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3803          * disabled, then force link down by entering low power mode.
3804          */
3805         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3806             !(hw->wol_enabled || ixgbe_mng_present(hw)))
3807                 return ixgbe_set_copper_phy_power(hw, FALSE);
3808
3809         /* Determine LCD */
3810         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3811
3812         if (status != IXGBE_SUCCESS)
3813                 return status;
3814
3815         /* If no valid LCD link speed, then force link down and exit. */
3816         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3817                 return ixgbe_set_copper_phy_power(hw, FALSE);
3818
3819         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3820                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3821                                       &speed);
3822
3823         if (status != IXGBE_SUCCESS)
3824                 return status;
3825
3826         /* If no link now, speed is invalid so take link down */
3827         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3828         if (status != IXGBE_SUCCESS)
3829                 return ixgbe_set_copper_phy_power(hw, false);
3830
3831         /* clear everything but the speed bits */
3832         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3833
3834         /* If current speed is already LCD, then exit. */
3835         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3836              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3837             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3838              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3839                 return status;
3840
3841         /* Clear AN completed indication */
3842         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3843                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3844                                       &autoneg_reg);
3845
3846         if (status != IXGBE_SUCCESS)
3847                 return status;
3848
3849         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3850                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3851                              &an_10g_cntl_reg);
3852
3853         if (status != IXGBE_SUCCESS)
3854                 return status;
3855
3856         status = hw->phy.ops.read_reg(hw,
3857                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3858                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3859                              &autoneg_reg);
3860
3861         if (status != IXGBE_SUCCESS)
3862                 return status;
3863
3864         save_autoneg = hw->phy.autoneg_advertised;
3865
3866         /* Setup link at least common link speed */
3867         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3868
3869         /* restore autoneg from before setting lplu speed */
3870         hw->phy.autoneg_advertised = save_autoneg;
3871
3872         return status;
3873 }
3874
3875 /**
3876  * ixgbe_get_lcd_x550em - Determine lowest common denominator
3877  *  @hw: pointer to hardware structure
3878  *  @lcd_speed: pointer to lowest common link speed
3879  *
3880  * Determine lowest common link speed with link partner.
3881  **/
3882 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3883 {
3884         u16 an_lp_status;
3885         s32 status;
3886         u16 word = hw->eeprom.ctrl_word_3;
3887
3888         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3889
3890         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3891                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3892                                       &an_lp_status);
3893
3894         if (status != IXGBE_SUCCESS)
3895                 return status;
3896
3897         /* If link partner advertised 1G, return 1G */
3898         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3899                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3900                 return status;
3901         }
3902
3903         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3904         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3905             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3906                 return status;
3907
3908         /* Link partner not capable of lower speeds, return 10G */
3909         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3910         return status;
3911 }
3912
3913 /**
3914  *  ixgbe_setup_fc_X550em - Set up flow control
3915  *  @hw: pointer to hardware structure
3916  *
3917  *  Called at init time to set up flow control.
3918  **/
3919 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3920 {
3921         s32 ret_val = IXGBE_SUCCESS;
3922         u32 pause, asm_dir, reg_val;
3923
3924         DEBUGFUNC("ixgbe_setup_fc_X550em");
3925
3926         /* Validate the requested mode */
3927         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3928                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3929                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3930                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3931                 goto out;
3932         }
3933
3934         /* 10gig parts do not have a word in the EEPROM to determine the
3935          * default flow control setting, so we explicitly set it to full.
3936          */
3937         if (hw->fc.requested_mode == ixgbe_fc_default)
3938                 hw->fc.requested_mode = ixgbe_fc_full;
3939
3940         /* Determine PAUSE and ASM_DIR bits. */
3941         switch (hw->fc.requested_mode) {
3942         case ixgbe_fc_none:
3943                 pause = 0;
3944                 asm_dir = 0;
3945                 break;
3946         case ixgbe_fc_tx_pause:
3947                 pause = 0;
3948                 asm_dir = 1;
3949                 break;
3950         case ixgbe_fc_rx_pause:
3951                 /* Rx Flow control is enabled and Tx Flow control is
3952                  * disabled by software override. Since there really
3953                  * isn't a way to advertise that we are capable of RX
3954                  * Pause ONLY, we will advertise that we support both
3955                  * symmetric and asymmetric Rx PAUSE, as such we fall
3956                  * through to the fc_full statement.  Later, we will
3957                  * disable the adapter's ability to send PAUSE frames.
3958                  */
3959         case ixgbe_fc_full:
3960                 pause = 1;
3961                 asm_dir = 1;
3962                 break;
3963         default:
3964                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3965                         "Flow control param set incorrectly\n");
3966                 ret_val = IXGBE_ERR_CONFIG;
3967                 goto out;
3968         }
3969
3970         switch (hw->device_id) {
3971         case IXGBE_DEV_ID_X550EM_X_KR:
3972         case IXGBE_DEV_ID_X550EM_A_KR:
3973         case IXGBE_DEV_ID_X550EM_A_KR_L:
3974                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
3975                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3976                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3977                 if (ret_val != IXGBE_SUCCESS)
3978                         goto out;
3979                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3980                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3981                 if (pause)
3982                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3983                 if (asm_dir)
3984                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3985                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
3986                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3987                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3988
3989                 /* This device does not fully support AN. */
3990                 hw->fc.disable_fc_autoneg = true;
3991                 break;
3992         case IXGBE_DEV_ID_X550EM_X_XFI:
3993                 hw->fc.disable_fc_autoneg = true;
3994                 break;
3995         default:
3996                 break;
3997         }
3998
3999 out:
4000         return ret_val;
4001 }
4002
4003 /**
4004  *  ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
4005  *  @hw: pointer to hardware structure
4006  *
4007  *  Enable flow control according to IEEE clause 37.
4008  **/
4009 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
4010 {
4011         u32 link_s1, lp_an_page_low, an_cntl_1;
4012         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4013         ixgbe_link_speed speed;
4014         bool link_up;
4015
4016         /* AN should have completed when the cable was plugged in.
4017          * Look for reasons to bail out.  Bail out if:
4018          * - FC autoneg is disabled, or if
4019          * - link is not up.
4020          */
4021         if (hw->fc.disable_fc_autoneg) {
4022                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4023                              "Flow control autoneg is disabled");
4024                 goto out;
4025         }
4026
4027         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4028         if (!link_up) {
4029                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4030                 goto out;
4031         }
4032
4033         /* Check at auto-negotiation has completed */
4034         status = hw->mac.ops.read_iosf_sb_reg(hw,
4035                                         IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4036                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4037
4038         if (status != IXGBE_SUCCESS ||
4039             (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4040                 DEBUGOUT("Auto-Negotiation did not complete\n");
4041                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4042                 goto out;
4043         }
4044
4045         /* Read the 10g AN autoc and LP ability registers and resolve
4046          * local flow control settings accordingly
4047          */
4048         status = hw->mac.ops.read_iosf_sb_reg(hw,
4049                                 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4050                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
4051
4052         if (status != IXGBE_SUCCESS) {
4053                 DEBUGOUT("Auto-Negotiation did not complete\n");
4054                 goto out;
4055         }
4056
4057         status = hw->mac.ops.read_iosf_sb_reg(hw,
4058                                 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
4059                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
4060
4061         if (status != IXGBE_SUCCESS) {
4062                 DEBUGOUT("Auto-Negotiation did not complete\n");
4063                 goto out;
4064         }
4065
4066         status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
4067                                     IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
4068                                     IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
4069                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
4070                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
4071
4072 out:
4073         if (status == IXGBE_SUCCESS) {
4074                 hw->fc.fc_was_autonegged = true;
4075         } else {
4076                 hw->fc.fc_was_autonegged = false;
4077                 hw->fc.current_mode = hw->fc.requested_mode;
4078         }
4079 }
4080
4081 /**
4082  *  ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
4083  *  @hw: pointer to hardware structure
4084  *
4085  **/
4086 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
4087 {
4088         hw->fc.fc_was_autonegged = false;
4089         hw->fc.current_mode = hw->fc.requested_mode;
4090 }
4091
4092 /**
4093  *  ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
4094  *  @hw: pointer to hardware structure
4095  *
4096  *  Enable flow control according to IEEE clause 37.
4097  **/
4098 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
4099 {
4100         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4101         u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
4102         ixgbe_link_speed speed;
4103         bool link_up;
4104
4105         /* AN should have completed when the cable was plugged in.
4106          * Look for reasons to bail out.  Bail out if:
4107          * - FC autoneg is disabled, or if
4108          * - link is not up.
4109          */
4110         if (hw->fc.disable_fc_autoneg) {
4111                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4112                              "Flow control autoneg is disabled");
4113                 goto out;
4114         }
4115
4116         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4117         if (!link_up) {
4118                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4119                 goto out;
4120         }
4121
4122         /* Check if auto-negotiation has completed */
4123         status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info);
4124         if (status != IXGBE_SUCCESS ||
4125             !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) {
4126                 DEBUGOUT("Auto-Negotiation did not complete\n");
4127                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4128                 goto out;
4129         }
4130
4131         /* Negotiate the flow control */
4132         status = ixgbe_negotiate_fc(hw, info[0], info[0],
4133                                     FW_PHY_ACT_GET_LINK_INFO_FC_RX,
4134                                     FW_PHY_ACT_GET_LINK_INFO_FC_TX,
4135                                     FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX,
4136                                     FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX);
4137
4138 out:
4139         if (status == IXGBE_SUCCESS) {
4140                 hw->fc.fc_was_autonegged = true;
4141         } else {
4142                 hw->fc.fc_was_autonegged = false;
4143                 hw->fc.current_mode = hw->fc.requested_mode;
4144         }
4145 }
4146
4147 /**
4148  *  ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4149  *  @hw: pointer to hardware structure
4150  *
4151  *  Called at init time to set up flow control.
4152  **/
4153 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4154 {
4155         s32 status = IXGBE_SUCCESS;
4156         u32 an_cntl = 0;
4157
4158         DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4159
4160         /* Validate the requested mode */
4161         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4162                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4163                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4164                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4165         }
4166
4167         if (hw->fc.requested_mode == ixgbe_fc_default)
4168                 hw->fc.requested_mode = ixgbe_fc_full;
4169
4170         /* Set up the 1G and 10G flow control advertisement registers so the
4171          * HW will be able to do FC autoneg once the cable is plugged in.  If
4172          * we link at 10G, the 1G advertisement is harmless and vice versa.
4173          */
4174         status = hw->mac.ops.read_iosf_sb_reg(hw,
4175                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4176                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4177
4178         if (status != IXGBE_SUCCESS) {
4179                 DEBUGOUT("Auto-Negotiation did not complete\n");
4180                 return status;
4181         }
4182
4183         /* The possible values of fc.requested_mode are:
4184          * 0: Flow control is completely disabled
4185          * 1: Rx flow control is enabled (we can receive pause frames,
4186          *    but not send pause frames).
4187          * 2: Tx flow control is enabled (we can send pause frames but
4188          *    we do not support receiving pause frames).
4189          * 3: Both Rx and Tx flow control (symmetric) are enabled.
4190          * other: Invalid.
4191          */
4192         switch (hw->fc.requested_mode) {
4193         case ixgbe_fc_none:
4194                 /* Flow control completely disabled by software override. */
4195                 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4196                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4197                 break;
4198         case ixgbe_fc_tx_pause:
4199                 /* Tx Flow control is enabled, and Rx Flow control is
4200                  * disabled by software override.
4201                  */
4202                 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4203                 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4204                 break;
4205         case ixgbe_fc_rx_pause:
4206                 /* Rx Flow control is enabled and Tx Flow control is
4207                  * disabled by software override. Since there really
4208                  * isn't a way to advertise that we are capable of RX
4209                  * Pause ONLY, we will advertise that we support both
4210                  * symmetric and asymmetric Rx PAUSE, as such we fall
4211                  * through to the fc_full statement.  Later, we will
4212                  * disable the adapter's ability to send PAUSE frames.
4213                  */
4214         case ixgbe_fc_full:
4215                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4216                 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4217                            IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4218                 break;
4219         default:
4220                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4221                               "Flow control param set incorrectly\n");
4222                 return IXGBE_ERR_CONFIG;
4223         }
4224
4225         status = hw->mac.ops.write_iosf_sb_reg(hw,
4226                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4227                                         IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4228
4229         /* Restart auto-negotiation. */
4230         status = ixgbe_restart_an_internal_phy_x550em(hw);
4231
4232         return status;
4233 }
4234
4235 /**
4236  * ixgbe_set_mux - Set mux for port 1 access with CS4227
4237  * @hw: pointer to hardware structure
4238  * @state: set mux if 1, clear if 0
4239  */
4240 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4241 {
4242         u32 esdp;
4243
4244         if (!hw->bus.lan_id)
4245                 return;
4246         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4247         if (state)
4248                 esdp |= IXGBE_ESDP_SDP1;
4249         else
4250                 esdp &= ~IXGBE_ESDP_SDP1;
4251         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4252         IXGBE_WRITE_FLUSH(hw);
4253 }
4254
4255 /**
4256  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4257  *  @hw: pointer to hardware structure
4258  *  @mask: Mask to specify which semaphore to acquire
4259  *
4260  *  Acquires the SWFW semaphore and sets the I2C MUX
4261  **/
4262 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4263 {
4264         s32 status;
4265
4266         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4267
4268         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4269         if (status)
4270                 return status;
4271
4272         if (mask & IXGBE_GSSR_I2C_MASK)
4273                 ixgbe_set_mux(hw, 1);
4274
4275         return IXGBE_SUCCESS;
4276 }
4277
4278 /**
4279  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4280  *  @hw: pointer to hardware structure
4281  *  @mask: Mask to specify which semaphore to release
4282  *
4283  *  Releases the SWFW semaphore and sets the I2C MUX
4284  **/
4285 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4286 {
4287         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4288
4289         if (mask & IXGBE_GSSR_I2C_MASK)
4290                 ixgbe_set_mux(hw, 0);
4291
4292         ixgbe_release_swfw_sync_X540(hw, mask);
4293 }
4294
4295 /**
4296  *  ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4297  *  @hw: pointer to hardware structure
4298  *  @mask: Mask to specify which semaphore to acquire
4299  *
4300  *  Acquires the SWFW semaphore and get the shared phy token as needed
4301  */
4302 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4303 {
4304         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4305         int retries = FW_PHY_TOKEN_RETRIES;
4306         s32 status = IXGBE_SUCCESS;
4307
4308         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4309
4310         while (--retries) {
4311                 status = IXGBE_SUCCESS;
4312                 if (hmask)
4313                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4314                 if (status) {
4315                         DEBUGOUT1("Could not acquire SWFW semaphore, Status = %d\n",
4316                                   status);
4317                         return status;
4318                 }
4319                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4320                         return IXGBE_SUCCESS;
4321
4322                 status = ixgbe_get_phy_token(hw);
4323                 if (status == IXGBE_ERR_TOKEN_RETRY)
4324                         DEBUGOUT1("Could not acquire PHY token, Status = %d\n",
4325                                   status);
4326
4327                 if (status == IXGBE_SUCCESS)
4328                         return IXGBE_SUCCESS;
4329
4330                 if (hmask)
4331                         ixgbe_release_swfw_sync_X540(hw, hmask);
4332
4333                 if (status != IXGBE_ERR_TOKEN_RETRY) {
4334                         DEBUGOUT1("Unable to retry acquiring the PHY token, Status = %d\n",
4335                                   status);
4336                         return status;
4337                 }
4338         }
4339
4340         DEBUGOUT1("Semaphore acquisition retries failed!: PHY ID = 0x%08X\n",
4341                   hw->phy.id);
4342         return status;
4343 }
4344
4345 /**
4346  *  ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4347  *  @hw: pointer to hardware structure
4348  *  @mask: Mask to specify which semaphore to release
4349  *
4350  *  Releases the SWFW semaphore and puts the shared phy token as needed
4351  */
4352 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4353 {
4354         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4355
4356         DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4357
4358         if (mask & IXGBE_GSSR_TOKEN_SM)
4359                 ixgbe_put_phy_token(hw);
4360
4361         if (hmask)
4362                 ixgbe_release_swfw_sync_X540(hw, hmask);
4363 }
4364
4365 /**
4366  *  ixgbe_read_phy_reg_x550a  - Reads specified PHY register
4367  *  @hw: pointer to hardware structure
4368  *  @reg_addr: 32 bit address of PHY register to read
4369  *  @device_type: 5 bit device type
4370  *  @phy_data: Pointer to read data from PHY register
4371  *
4372  *  Reads a value from a specified PHY register using the SWFW lock and PHY
4373  *  Token. The PHY Token is needed since the MDIO is shared between to MAC
4374  *  instances.
4375  **/
4376 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4377                                u32 device_type, u16 *phy_data)
4378 {
4379         s32 status;
4380         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4381
4382         DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4383
4384         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4385                 return IXGBE_ERR_SWFW_SYNC;
4386
4387         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4388
4389         hw->mac.ops.release_swfw_sync(hw, mask);
4390
4391         return status;
4392 }
4393
4394 /**
4395  *  ixgbe_write_phy_reg_x550a - Writes specified PHY register
4396  *  @hw: pointer to hardware structure
4397  *  @reg_addr: 32 bit PHY register to write
4398  *  @device_type: 5 bit device type
4399  *  @phy_data: Data to write to the PHY register
4400  *
4401  *  Writes a value to specified PHY register using the SWFW lock and PHY Token.
4402  *  The PHY Token is needed since the MDIO is shared between to MAC instances.
4403  **/
4404 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4405                                 u32 device_type, u16 phy_data)
4406 {
4407         s32 status;
4408         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4409
4410         DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4411
4412         if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4413                 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
4414                                                  phy_data);
4415                 hw->mac.ops.release_swfw_sync(hw, mask);
4416         } else {
4417                 status = IXGBE_ERR_SWFW_SYNC;
4418         }
4419
4420         return status;
4421 }
4422
4423 /**
4424  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4425  * @hw: pointer to hardware structure
4426  *
4427  * Handle external Base T PHY interrupt. If high temperature
4428  * failure alarm then return error, else if link status change
4429  * then setup internal/external PHY link
4430  *
4431  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4432  * failure alarm, else return PHY access status.
4433  */
4434 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4435 {
4436         bool lsc;
4437         u32 status;
4438
4439         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4440
4441         if (status != IXGBE_SUCCESS)
4442                 return status;
4443
4444         if (lsc)
4445                 return ixgbe_setup_internal_phy(hw);
4446
4447         return IXGBE_SUCCESS;
4448 }
4449
4450 /**
4451  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4452  * @hw: pointer to hardware structure
4453  * @speed: new link speed
4454  * @autoneg_wait_to_complete: true when waiting for completion is needed
4455  *
4456  * Setup internal/external PHY link speed based on link speed, then set
4457  * external PHY auto advertised link speed.
4458  *
4459  * Returns error status for any failure
4460  **/
4461 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4462                                   ixgbe_link_speed speed,
4463                                   bool autoneg_wait_to_complete)
4464 {
4465         s32 status;
4466         ixgbe_link_speed force_speed;
4467
4468         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4469
4470         /* Setup internal/external PHY link speed to iXFI (10G), unless
4471          * only 1G is auto advertised then setup KX link.
4472          */
4473         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4474                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4475         else
4476                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4477
4478         /* If X552 and internal link mode is XFI, then setup XFI internal link.
4479          */
4480         if (hw->mac.type == ixgbe_mac_X550EM_x &&
4481             !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4482                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4483
4484                 if (status != IXGBE_SUCCESS)
4485                         return status;
4486         }
4487
4488         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4489 }
4490
4491 /**
4492  * ixgbe_check_link_t_X550em - Determine link and speed status
4493  * @hw: pointer to hardware structure
4494  * @speed: pointer to link speed
4495  * @link_up: true when link is up
4496  * @link_up_wait_to_complete: bool used to wait for link up or not
4497  *
4498  * Check that both the MAC and X557 external PHY have link.
4499  **/
4500 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4501                               bool *link_up, bool link_up_wait_to_complete)
4502 {
4503         u32 status;
4504         u16 i, autoneg_status = 0;
4505
4506         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4507                 return IXGBE_ERR_CONFIG;
4508
4509         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4510                                               link_up_wait_to_complete);
4511
4512         /* If check link fails or MAC link is not up, then return */
4513         if (status != IXGBE_SUCCESS || !(*link_up))
4514                 return status;
4515
4516         /* MAC link is up, so check external PHY link.
4517          * X557 PHY. Link status is latching low, and can only be used to detect
4518          * link drop, and not the current status of the link without performing
4519          * back-to-back reads.
4520          */
4521         for (i = 0; i < 2; i++) {
4522                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4523                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4524                                               &autoneg_status);
4525
4526                 if (status != IXGBE_SUCCESS)
4527                         return status;
4528         }
4529
4530         /* If external PHY link is not up, then indicate link not up */
4531         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4532                 *link_up = false;
4533
4534         return IXGBE_SUCCESS;
4535 }
4536
4537 /**
4538  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4539  *  @hw: pointer to hardware structure
4540  **/
4541 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4542 {
4543         s32 status;
4544
4545         status = ixgbe_reset_phy_generic(hw);
4546
4547         if (status != IXGBE_SUCCESS)
4548                 return status;
4549
4550         /* Configure Link Status Alarm and Temperature Threshold interrupts */
4551         return ixgbe_enable_lasi_ext_t_x550em(hw);
4552 }
4553
4554 /**
4555  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4556  *  @hw: pointer to hardware structure
4557  *  @led_idx: led number to turn on
4558  **/
4559 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4560 {
4561         u16 phy_data;
4562
4563         DEBUGFUNC("ixgbe_led_on_t_X550em");
4564
4565         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4566                 return IXGBE_ERR_PARAM;
4567
4568         /* To turn on the LED, set mode to ON. */
4569         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4570                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4571         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4572         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4573                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4574
4575         /* Some designs have the LEDs wired to the MAC */
4576         return ixgbe_led_on_generic(hw, led_idx);
4577 }
4578
4579 /**
4580  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4581  *  @hw: pointer to hardware structure
4582  *  @led_idx: led number to turn off
4583  **/
4584 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4585 {
4586         u16 phy_data;
4587
4588         DEBUGFUNC("ixgbe_led_off_t_X550em");
4589
4590         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4591                 return IXGBE_ERR_PARAM;
4592
4593         /* To turn on the LED, set mode to ON. */
4594         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4595                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4596         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4597         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4598                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4599
4600         /* Some designs have the LEDs wired to the MAC */
4601         return ixgbe_led_off_generic(hw, led_idx);
4602 }
4603
4604 /**
4605  *  ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware
4606  *  @hw: pointer to the HW structure
4607  *  @maj: driver version major number
4608  *  @min: driver version minor number
4609  *  @build: driver version build number
4610  *  @sub: driver version sub build number
4611  *  @len: length of driver_ver string
4612  *  @driver_ver: driver string
4613  *
4614  *  Sends driver version number to firmware through the manageability
4615  *  block.  On success return IXGBE_SUCCESS
4616  *  else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4617  *  semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4618  **/
4619 s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,
4620                               u8 build, u8 sub, u16 len, const char *driver_ver)
4621 {
4622         struct ixgbe_hic_drv_info2 fw_cmd;
4623         s32 ret_val = IXGBE_SUCCESS;
4624         int i;
4625
4626         DEBUGFUNC("ixgbe_set_fw_drv_ver_x550");
4627
4628         if ((len == 0) || (driver_ver == NULL) ||
4629            (len > sizeof(fw_cmd.driver_string)))
4630                 return IXGBE_ERR_INVALID_ARGUMENT;
4631
4632         fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4633         fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len;
4634         fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4635         fw_cmd.port_num = (u8)hw->bus.func;
4636         fw_cmd.ver_maj = maj;
4637         fw_cmd.ver_min = min;
4638         fw_cmd.ver_build = build;
4639         fw_cmd.ver_sub = sub;
4640         fw_cmd.hdr.checksum = 0;
4641         memcpy(fw_cmd.driver_string, driver_ver, len);
4642         fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4643                                 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4644
4645         for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4646                 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4647                                                        sizeof(fw_cmd),
4648                                                        IXGBE_HI_COMMAND_TIMEOUT,
4649                                                        true);
4650                 if (ret_val != IXGBE_SUCCESS)
4651                         continue;
4652
4653                 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4654                     FW_CEM_RESP_STATUS_SUCCESS)
4655                         ret_val = IXGBE_SUCCESS;
4656                 else
4657                         ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4658
4659                 break;
4660         }
4661
4662         return ret_val;
4663 }