drivers/net/ixgbe/base/ixgbe_x550.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2018
   3  */
   4
   5 #include "ixgbe_x550.h"
   6 #include "ixgbe_x540.h"
   7 #include "ixgbe_type.h"
   8 #include "ixgbe_api.h"
   9 #include "ixgbe_common.h"
  10 #include "ixgbe_phy.h"
  11
  12 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  13 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  14 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  15 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw);
  16
  17 /**
  18  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  19  *  @hw: pointer to hardware structure
  20  *
  21  *  Initialize the function pointers and assign the MAC type for X550.
  22  *  Does not touch the hardware.
  23  **/
  24 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  25 {
  26         struct ixgbe_mac_info *mac = &hw->mac;
  27         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  28         s32 ret_val;
  29
  30         DEBUGFUNC("ixgbe_init_ops_X550");
  31
  32         ret_val = ixgbe_init_ops_X540(hw);
  33         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  34         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  35         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  36         mac->ops.setup_eee = NULL;
  37         mac->ops.set_source_address_pruning =
  38                         ixgbe_set_source_address_pruning_X550;
  39         mac->ops.set_ethertype_anti_spoofing =
  40                         ixgbe_set_ethertype_anti_spoofing_X550;
  41
  42         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  43         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  44         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  45         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  46         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  47         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  48         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  49         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  50         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  51
  52         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  53         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  54         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  55         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  56         mac->ops.fw_recovery_mode = ixgbe_fw_recovery_mode_X550;
  57         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  58         /* Manageability interface */
  59         mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_x550;
  60         switch (hw->device_id) {
  61         case IXGBE_DEV_ID_X550EM_X_1G_T:
  62                 hw->mac.ops.led_on = NULL;
  63                 hw->mac.ops.led_off = NULL;
  64                 break;
  65         case IXGBE_DEV_ID_X550EM_X_10G_T:
  66         case IXGBE_DEV_ID_X550EM_A_10G_T:
  67                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  68                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  69                 break;
  70         default:
  71                 break;
  72         }
  73         return ret_val;
  74 }
  75
  76 /**
  77  * ixgbe_read_cs4227 - Read CS4227 register
  78  * @hw: pointer to hardware structure
  79  * @reg: register number to write
  80  * @value: pointer to receive value read
  81  *
  82  * Returns status code
  83  **/
  84 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  85 {
  86         return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
  87 }
  88
  89 /**
  90  * ixgbe_write_cs4227 - Write CS4227 register
  91  * @hw: pointer to hardware structure
  92  * @reg: register number to write
  93  * @value: value to write to register
  94  *
  95  * Returns status code
  96  **/
  97 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
  98 {
  99         return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
 100 }
 101
 102 /**
 103  * ixgbe_read_pe - Read register from port expander
 104  * @hw: pointer to hardware structure
 105  * @reg: register number to read
 106  * @value: pointer to receive read value
 107  *
 108  * Returns status code
 109  **/
 110 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 111 {
 112         s32 status;
 113
 114         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 115         if (status != IXGBE_SUCCESS)
 116                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 117                               "port expander access failed with %d\n", status);
 118         return status;
 119 }
 120
 121 /**
 122  * ixgbe_write_pe - Write register to port expander
 123  * @hw: pointer to hardware structure
 124  * @reg: register number to write
 125  * @value: value to write
 126  *
 127  * Returns status code
 128  **/
 129 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 130 {
 131         s32 status;
 132
 133         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 134         if (status != IXGBE_SUCCESS)
 135                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 136                               "port expander access failed with %d\n", status);
 137         return status;
 138 }
 139
 140 /**
 141  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 142  * @hw: pointer to hardware structure
 143  *
 144  * This function assumes that the caller has acquired the proper semaphore.
 145  * Returns error code
 146  **/
 147 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 148 {
 149         s32 status;
 150         u32 retry;
 151         u16 value;
 152         u8 reg;
 153
 154         /* Trigger hard reset. */
 155         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 156         if (status != IXGBE_SUCCESS)
 157                 return status;
 158         reg |= IXGBE_PE_BIT1;
 159         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 160         if (status != IXGBE_SUCCESS)
 161                 return status;
 162
 163         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 164         if (status != IXGBE_SUCCESS)
 165                 return status;
 166         reg &= ~IXGBE_PE_BIT1;
 167         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 168         if (status != IXGBE_SUCCESS)
 169                 return status;
 170
 171         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 172         if (status != IXGBE_SUCCESS)
 173                 return status;
 174         reg &= ~IXGBE_PE_BIT1;
 175         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 176         if (status != IXGBE_SUCCESS)
 177                 return status;
 178
 179         usec_delay(IXGBE_CS4227_RESET_HOLD);
 180
 181         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 182         if (status != IXGBE_SUCCESS)
 183                 return status;
 184         reg |= IXGBE_PE_BIT1;
 185         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 186         if (status != IXGBE_SUCCESS)
 187                 return status;
 188
 189         /* Wait for the reset to complete. */
 190         msec_delay(IXGBE_CS4227_RESET_DELAY);
 191         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 192                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 193                                            &value);
 194                 if (status == IXGBE_SUCCESS &&
 195                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 196                         break;
 197                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 198         }
 199         if (retry == IXGBE_CS4227_RETRIES) {
 200                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 201                         "CS4227 reset did not complete.");
 202                 return IXGBE_ERR_PHY;
 203         }
 204
 205         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 206         if (status != IXGBE_SUCCESS ||
 207             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 208                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 209                         "CS4227 EEPROM did not load successfully.");
 210                 return IXGBE_ERR_PHY;
 211         }
 212
 213         return IXGBE_SUCCESS;
 214 }
 215
 216 /**
 217  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 218  * @hw: pointer to hardware structure
 219  **/
 220 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 221 {
 222         s32 status = IXGBE_SUCCESS;
 223         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 224         u16 value = 0;
 225         u8 retry;
 226
 227         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 228                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 229                 if (status != IXGBE_SUCCESS) {
 230                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 231                                 "semaphore failed with %d", status);
 232                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 233                         continue;
 234                 }
 235
 236                 /* Get status of reset flow. */
 237                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 238
 239                 if (status == IXGBE_SUCCESS &&
 240                     value == IXGBE_CS4227_RESET_COMPLETE)
 241                         goto out;
 242
 243                 if (status != IXGBE_SUCCESS ||
 244                     value != IXGBE_CS4227_RESET_PENDING)
 245                         break;
 246
 247                 /* Reset is pending. Wait and check again. */
 248                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 249                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 250         }
 251
 252         /* If still pending, assume other instance failed. */
 253         if (retry == IXGBE_CS4227_RETRIES) {
 254                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 255                 if (status != IXGBE_SUCCESS) {
 256                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 257                                       "semaphore failed with %d", status);
 258                         return;
 259                 }
 260         }
 261
 262         /* Reset the CS4227. */
 263         status = ixgbe_reset_cs4227(hw);
 264         if (status != IXGBE_SUCCESS) {
 265                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 266                         "CS4227 reset failed: %d", status);
 267                 goto out;
 268         }
 269
 270         /* Reset takes so long, temporarily release semaphore in case the
 271          * other driver instance is waiting for the reset indication.
 272          */
 273         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 274                            IXGBE_CS4227_RESET_PENDING);
 275         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 276         msec_delay(10);
 277         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 278         if (status != IXGBE_SUCCESS) {
 279                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 280                         "semaphore failed with %d", status);
 281                 return;
 282         }
 283
 284         /* Record completion for next time. */
 285         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 286                 IXGBE_CS4227_RESET_COMPLETE);
 287
 288 out:
 289         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 290         msec_delay(hw->eeprom.semaphore_delay);
 291 }
 292
 293 /**
 294  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 295  * @hw: pointer to hardware structure
 296  **/
 297 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 298 {
 299         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 300
 301         if (hw->bus.lan_id) {
 302                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 303                 esdp |= IXGBE_ESDP_SDP1_DIR;
 304         }
 305         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 306         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 307         IXGBE_WRITE_FLUSH(hw);
 308 }
 309
 310 /**
 311  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 312  * @hw: pointer to hardware structure
 313  *
 314  * Returns error code
 315  */
 316 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 317 {
 318         hw->mac.ops.set_lan_id(hw);
 319
 320         ixgbe_read_mng_if_sel_x550em(hw);
 321
 322         switch (hw->device_id) {
 323         case IXGBE_DEV_ID_X550EM_A_SFP:
 324                 return ixgbe_identify_sfp_module_X550em(hw);
 325         case IXGBE_DEV_ID_X550EM_X_SFP:
 326                 /* set up for CS4227 usage */
 327                 ixgbe_setup_mux_ctl(hw);
 328                 ixgbe_check_cs4227(hw);
 329                 /* Fallthrough */
 330
 331         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 332                 return ixgbe_identify_sfp_module_X550em(hw);
 333                 break;
 334         case IXGBE_DEV_ID_X550EM_X_KX4:
 335                 hw->phy.type = ixgbe_phy_x550em_kx4;
 336                 break;
 337         case IXGBE_DEV_ID_X550EM_X_XFI:
 338                 hw->phy.type = ixgbe_phy_x550em_xfi;
 339                 break;
 340         case IXGBE_DEV_ID_X550EM_X_KR:
 341         case IXGBE_DEV_ID_X550EM_A_KR:
 342         case IXGBE_DEV_ID_X550EM_A_KR_L:
 343                 hw->phy.type = ixgbe_phy_x550em_kr;
 344                 break;
 345         case IXGBE_DEV_ID_X550EM_A_10G_T:
 346         case IXGBE_DEV_ID_X550EM_X_10G_T:
 347                 return ixgbe_identify_phy_generic(hw);
 348         case IXGBE_DEV_ID_X550EM_X_1G_T:
 349                 hw->phy.type = ixgbe_phy_ext_1g_t;
 350                 break;
 351         case IXGBE_DEV_ID_X550EM_A_1G_T:
 352         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 353                 hw->phy.type = ixgbe_phy_fw;
 354                 if (hw->bus.lan_id)
 355                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 356                 else
 357                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 358                 break;
 359         default:
 360                 break;
 361         }
 362         return IXGBE_SUCCESS;
 363 }
 364
 365 /**
 366  * ixgbe_fw_phy_activity - Perform an activity on a PHY
 367  * @hw: pointer to hardware structure
 368  * @activity: activity to perform
 369  * @data: Pointer to 4 32-bit words of data
 370  */
 371 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,
 372                           u32 (*data)[FW_PHY_ACT_DATA_COUNT])
 373 {
 374         union {
 375                 struct ixgbe_hic_phy_activity_req cmd;
 376                 struct ixgbe_hic_phy_activity_resp rsp;
 377         } hic;
 378         u16 retries = FW_PHY_ACT_RETRIES;
 379         s32 rc;
 380         u16 i;
 381
 382         do {
 383                 memset(&hic, 0, sizeof(hic));
 384                 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD;
 385                 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN;
 386                 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 387                 hic.cmd.port_number = hw->bus.lan_id;
 388                 hic.cmd.activity_id = IXGBE_CPU_TO_LE16(activity);
 389                 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
 390                         hic.cmd.data[i] = IXGBE_CPU_TO_BE32((*data)[i]);
 391
 392                 rc = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
 393                                                   sizeof(hic.cmd),
 394                                                   IXGBE_HI_COMMAND_TIMEOUT,
 395                                                   true);
 396                 if (rc != IXGBE_SUCCESS)
 397                         return rc;
 398                 if (hic.rsp.hdr.cmd_or_resp.ret_status ==
 399                     FW_CEM_RESP_STATUS_SUCCESS) {
 400                         for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
 401                                 (*data)[i] = IXGBE_BE32_TO_CPU(hic.rsp.data[i]);
 402                         return IXGBE_SUCCESS;
 403                 }
 404                 usec_delay(20);
 405                 --retries;
 406         } while (retries > 0);
 407
 408         return IXGBE_ERR_HOST_INTERFACE_COMMAND;
 409 }
 410
 411 static const struct {
 412         u16 fw_speed;
 413         ixgbe_link_speed phy_speed;
 414 } ixgbe_fw_map[] = {
 415         { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL },
 416         { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL },
 417         { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL },
 418         { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL },
 419         { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL },
 420         { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL },
 421 };
 422
 423 /**
 424  * ixgbe_get_phy_id_fw - Get the phy ID via firmware command
 425  * @hw: pointer to hardware structure
 426  *
 427  * Returns error code
 428  */
 429 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw)
 430 {
 431         u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
 432         u16 phy_speeds;
 433         u16 phy_id_lo;
 434         s32 rc;
 435         u16 i;
 436
 437         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info);
 438         if (rc)
 439                 return rc;
 440
 441         hw->phy.speeds_supported = 0;
 442         phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK;
 443         for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
 444                 if (phy_speeds & ixgbe_fw_map[i].fw_speed)
 445                         hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed;
 446         }
 447         if (!hw->phy.autoneg_advertised)
 448                 hw->phy.autoneg_advertised = hw->phy.speeds_supported;
 449
 450         hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK;
 451         phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK;
 452         hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK;
 453         hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK;
 454         if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK)
 455                 return IXGBE_ERR_PHY_ADDR_INVALID;
 456         return IXGBE_SUCCESS;
 457 }
 458
 459 /**
 460  * ixgbe_identify_phy_fw - Get PHY type based on firmware command
 461  * @hw: pointer to hardware structure
 462  *
 463  * Returns error code
 464  */
 465 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw)
 466 {
 467         if (hw->bus.lan_id)
 468                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 469         else
 470                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 471
 472         hw->phy.type = ixgbe_phy_fw;
 473         hw->phy.ops.read_reg = NULL;
 474         hw->phy.ops.write_reg = NULL;
 475         return ixgbe_get_phy_id_fw(hw);
 476 }
 477
 478 /**
 479  * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY
 480  * @hw: pointer to hardware structure
 481  *
 482  * Returns error code
 483  */
 484 s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw)
 485 {
 486         u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
 487
 488         setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF;
 489         return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup);
 490 }
 491
 492 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 493                                      u32 device_type, u16 *phy_data)
 494 {
 495         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 496         return IXGBE_NOT_IMPLEMENTED;
 497 }
 498
 499 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 500                                       u32 device_type, u16 phy_data)
 501 {
 502         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 503         return IXGBE_NOT_IMPLEMENTED;
 504 }
 505
 506 /**
 507  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 508  * @hw: pointer to the hardware structure
 509  * @addr: I2C bus address to read from
 510  * @reg: I2C device register to read from
 511  * @val: pointer to location to receive read value
 512  *
 513  * Returns an error code on error.
 514  **/
 515 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 516                                            u16 reg, u16 *val)
 517 {
 518         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 519 }
 520
 521 /**
 522  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 523  * @hw: pointer to the hardware structure
 524  * @addr: I2C bus address to read from
 525  * @reg: I2C device register to read from
 526  * @val: pointer to location to receive read value
 527  *
 528  * Returns an error code on error.
 529  **/
 530 STATIC s32
 531 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 532                                          u16 reg, u16 *val)
 533 {
 534         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 535 }
 536
 537 /**
 538  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 539  * @hw: pointer to the hardware structure
 540  * @addr: I2C bus address to write to
 541  * @reg: I2C device register to write to
 542  * @val: value to write
 543  *
 544  * Returns an error code on error.
 545  **/
 546 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 547                                             u8 addr, u16 reg, u16 val)
 548 {
 549         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 550 }
 551
 552 /**
 553  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 554  * @hw: pointer to the hardware structure
 555  * @addr: I2C bus address to write to
 556  * @reg: I2C device register to write to
 557  * @val: value to write
 558  *
 559  * Returns an error code on error.
 560  **/
 561 STATIC s32
 562 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 563                                           u8 addr, u16 reg, u16 val)
 564 {
 565         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 566 }
 567
 568 /**
 569 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 570 *  @hw: pointer to hardware structure
 571 *
 572 *  Initialize the function pointers and for MAC type X550EM.
 573 *  Does not touch the hardware.
 574 **/
 575 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 576 {
 577         struct ixgbe_mac_info *mac = &hw->mac;
 578         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 579         struct ixgbe_phy_info *phy = &hw->phy;
 580         s32 ret_val;
 581
 582         DEBUGFUNC("ixgbe_init_ops_X550EM");
 583
 584         /* Similar to X550 so start there. */
 585         ret_val = ixgbe_init_ops_X550(hw);
 586
 587         /* Since this function eventually calls
 588          * ixgbe_init_ops_540 by design, we are setting
 589          * the pointers to NULL explicitly here to overwrite
 590          * the values being set in the x540 function.
 591          */
 592         /* Thermal sensor not supported in x550EM */
 593         mac->ops.get_thermal_sensor_data = NULL;
 594         mac->ops.init_thermal_sensor_thresh = NULL;
 595         mac->thermal_sensor_enabled = false;
 596
 597         /* FCOE not supported in x550EM */
 598         mac->ops.get_san_mac_addr = NULL;
 599         mac->ops.set_san_mac_addr = NULL;
 600         mac->ops.get_wwn_prefix = NULL;
 601         mac->ops.get_fcoe_boot_status = NULL;
 602
 603         /* IPsec not supported in x550EM */
 604         mac->ops.disable_sec_rx_path = NULL;
 605         mac->ops.enable_sec_rx_path = NULL;
 606
 607         /* AUTOC register is not present in x550EM. */
 608         mac->ops.prot_autoc_read = NULL;
 609         mac->ops.prot_autoc_write = NULL;
 610
 611         /* X550EM bus type is internal*/
 612         hw->bus.type = ixgbe_bus_type_internal;
 613         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 614
 615
 616         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 617         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 618         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 619         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 620         mac->ops.get_supported_physical_layer =
 621                                     ixgbe_get_supported_physical_layer_X550em;
 622
 623         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 624                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 625         else
 626                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 627
 628         /* PHY */
 629         phy->ops.init = ixgbe_init_phy_ops_X550em;
 630         switch (hw->device_id) {
 631         case IXGBE_DEV_ID_X550EM_A_1G_T:
 632         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 633                 mac->ops.setup_fc = NULL;
 634                 phy->ops.identify = ixgbe_identify_phy_fw;
 635                 phy->ops.set_phy_power = NULL;
 636                 phy->ops.get_firmware_version = NULL;
 637                 break;
 638         case IXGBE_DEV_ID_X550EM_X_1G_T:
 639                 mac->ops.setup_fc = NULL;
 640                 phy->ops.identify = ixgbe_identify_phy_x550em;
 641                 phy->ops.set_phy_power = NULL;
 642                 break;
 643         default:
 644                 phy->ops.identify = ixgbe_identify_phy_x550em;
 645         }
 646
 647         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 648                 phy->ops.set_phy_power = NULL;
 649
 650
 651         /* EEPROM */
 652         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 653         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 654         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 655         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 656         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 657         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 658         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 659         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 660
 661         return ret_val;
 662 }
 663
 664 /**
 665  * ixgbe_setup_fw_link - Setup firmware-controlled PHYs
 666  * @hw: pointer to hardware structure
 667  */
 668 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw)
 669 {
 670         u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
 671         s32 rc;
 672         u16 i;
 673
 674         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
 675                 return 0;
 676
 677         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
 678                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
 679                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
 680                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
 681         }
 682
 683         switch (hw->fc.requested_mode) {
 684         case ixgbe_fc_full:
 685                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX <<
 686                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 687                 break;
 688         case ixgbe_fc_rx_pause:
 689                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX <<
 690                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 691                 break;
 692         case ixgbe_fc_tx_pause:
 693                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX <<
 694                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 695                 break;
 696         default:
 697                 break;
 698         }
 699
 700         for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
 701                 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)
 702                         setup[0] |= ixgbe_fw_map[i].fw_speed;
 703         }
 704         setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN;
 705
 706         if (hw->phy.eee_speeds_advertised)
 707                 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE;
 708
 709         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup);
 710         if (rc)
 711                 return rc;
 712         if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN)
 713                 return IXGBE_ERR_OVERTEMP;
 714         return IXGBE_SUCCESS;
 715 }
 716
 717 /**
 718  * ixgbe_fc_autoneg_fw _ Set up flow control for FW-controlled PHYs
 719  * @hw: pointer to hardware structure
 720  *
 721  *  Called at init time to set up flow control.
 722  */
 723 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw)
 724 {
 725         if (hw->fc.requested_mode == ixgbe_fc_default)
 726                 hw->fc.requested_mode = ixgbe_fc_full;
 727
 728         return ixgbe_setup_fw_link(hw);
 729 }
 730
 731 /**
 732  * ixgbe_setup_eee_fw - Enable/disable EEE support
 733  * @hw: pointer to the HW structure
 734  * @enable_eee: boolean flag to enable EEE
 735  *
 736  * Enable/disable EEE based on enable_eee flag.
 737  * This function controls EEE for firmware-based PHY implementations.
 738  */
 739 static s32 ixgbe_setup_eee_fw(struct ixgbe_hw *hw, bool enable_eee)
 740 {
 741         if (!!hw->phy.eee_speeds_advertised == enable_eee)
 742                 return IXGBE_SUCCESS;
 743         if (enable_eee)
 744                 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
 745         else
 746                 hw->phy.eee_speeds_advertised = 0;
 747         return hw->phy.ops.setup_link(hw);
 748 }
 749
 750 /**
 751 *  ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
 752 *  @hw: pointer to hardware structure
 753 *
 754 *  Initialize the function pointers and for MAC type X550EM_a.
 755 *  Does not touch the hardware.
 756 **/
 757 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
 758 {
 759         struct ixgbe_mac_info *mac = &hw->mac;
 760         s32 ret_val;
 761
 762         DEBUGFUNC("ixgbe_init_ops_X550EM_a");
 763
 764         /* Start with generic X550EM init */
 765         ret_val = ixgbe_init_ops_X550EM(hw);
 766
 767         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
 768             hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) {
 769                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 770                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 771         } else {
 772                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
 773                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
 774         }
 775         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
 776         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
 777
 778         switch (mac->ops.get_media_type(hw)) {
 779         case ixgbe_media_type_fiber:
 780                 mac->ops.setup_fc = NULL;
 781                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
 782                 break;
 783         case ixgbe_media_type_backplane:
 784                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
 785                 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
 786                 break;
 787         default:
 788                 break;
 789         }
 790
 791         switch (hw->device_id) {
 792         case IXGBE_DEV_ID_X550EM_A_1G_T:
 793         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 794                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
 795                 mac->ops.setup_fc = ixgbe_fc_autoneg_fw;
 796                 mac->ops.setup_eee = ixgbe_setup_eee_fw;
 797                 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL |
 798                                                IXGBE_LINK_SPEED_1GB_FULL;
 799                 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
 800                 break;
 801         default:
 802                 break;
 803         }
 804
 805         return ret_val;
 806 }
 807
 808 /**
 809 *  ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
 810 *  @hw: pointer to hardware structure
 811 *
 812 *  Initialize the function pointers and for MAC type X550EM_x.
 813 *  Does not touch the hardware.
 814 **/
 815 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
 816 {
 817         struct ixgbe_mac_info *mac = &hw->mac;
 818         struct ixgbe_link_info *link = &hw->link;
 819         s32 ret_val;
 820
 821         DEBUGFUNC("ixgbe_init_ops_X550EM_x");
 822
 823         /* Start with generic X550EM init */
 824         ret_val = ixgbe_init_ops_X550EM(hw);
 825
 826         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 827         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 828         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 829         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 830         link->ops.read_link = ixgbe_read_i2c_combined_generic;
 831         link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
 832         link->ops.write_link = ixgbe_write_i2c_combined_generic;
 833         link->ops.write_link_unlocked =
 834                                       ixgbe_write_i2c_combined_generic_unlocked;
 835         link->addr = IXGBE_CS4227;
 836
 837         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T) {
 838                 mac->ops.setup_fc = NULL;
 839                 mac->ops.setup_eee = NULL;
 840                 mac->ops.init_led_link_act = NULL;
 841         }
 842
 843         return ret_val;
 844 }
 845
 846 /**
 847  *  ixgbe_dmac_config_X550
 848  *  @hw: pointer to hardware structure
 849  *
 850  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 851  *  When disabling dmac, dmac enable dmac bit is cleared.
 852  **/
 853 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 854 {
 855         u32 reg, high_pri_tc;
 856
 857         DEBUGFUNC("ixgbe_dmac_config_X550");
 858
 859         /* Disable DMA coalescing before configuring */
 860         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 861         reg &= ~IXGBE_DMACR_DMAC_EN;
 862         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 863
 864         /* Disable DMA Coalescing if the watchdog timer is 0 */
 865         if (!hw->mac.dmac_config.watchdog_timer)
 866                 goto out;
 867
 868         ixgbe_dmac_config_tcs_X550(hw);
 869
 870         /* Configure DMA Coalescing Control Register */
 871         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 872
 873         /* Set the watchdog timer in units of 40.96 usec */
 874         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 875         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 876
 877         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 878         /* If fcoe is enabled, set high priority traffic class */
 879         if (hw->mac.dmac_config.fcoe_en) {
 880                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 881                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 882                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 883         }
 884         reg |= IXGBE_DMACR_EN_MNG_IND;
 885
 886         /* Enable DMA coalescing after configuration */
 887         reg |= IXGBE_DMACR_DMAC_EN;
 888         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 889
 890 out:
 891         return IXGBE_SUCCESS;
 892 }
 893
 894 /**
 895  *  ixgbe_dmac_config_tcs_X550
 896  *  @hw: pointer to hardware structure
 897  *
 898  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 899  *  be cleared before configuring.
 900  **/
 901 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 902 {
 903         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 904
 905         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 906
 907         /* Configure DMA coalescing enabled */
 908         switch (hw->mac.dmac_config.link_speed) {
 909         case IXGBE_LINK_SPEED_10_FULL:
 910         case IXGBE_LINK_SPEED_100_FULL:
 911                 pb_headroom = IXGBE_DMACRXT_100M;
 912                 break;
 913         case IXGBE_LINK_SPEED_1GB_FULL:
 914                 pb_headroom = IXGBE_DMACRXT_1G;
 915                 break;
 916         default:
 917                 pb_headroom = IXGBE_DMACRXT_10G;
 918                 break;
 919         }
 920
 921         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 922                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 923
 924         /* Set the per Rx packet buffer receive threshold */
 925         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 926                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 927                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 928
 929                 if (tc < hw->mac.dmac_config.num_tcs) {
 930                         /* Get Rx PB size */
 931                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 932                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 933                                 IXGBE_RXPBSIZE_SHIFT;
 934
 935                         /* Calculate receive buffer threshold in kilobytes */
 936                         if (rx_pb_size > pb_headroom)
 937                                 rx_pb_size = rx_pb_size - pb_headroom;
 938                         else
 939                                 rx_pb_size = 0;
 940
 941                         /* Minimum of MFS shall be set for DMCTH */
 942                         reg |= (rx_pb_size > maxframe_size_kb) ?
 943                                 rx_pb_size : maxframe_size_kb;
 944                 }
 945                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 946         }
 947         return IXGBE_SUCCESS;
 948 }
 949
 950 /**
 951  *  ixgbe_dmac_update_tcs_X550
 952  *  @hw: pointer to hardware structure
 953  *
 954  *  Disables dmac, updates per TC settings, and then enables dmac.
 955  **/
 956 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 957 {
 958         u32 reg;
 959
 960         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 961
 962         /* Disable DMA coalescing before configuring */
 963         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 964         reg &= ~IXGBE_DMACR_DMAC_EN;
 965         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 966
 967         ixgbe_dmac_config_tcs_X550(hw);
 968
 969         /* Enable DMA coalescing after configuration */
 970         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 971         reg |= IXGBE_DMACR_DMAC_EN;
 972         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 973
 974         return IXGBE_SUCCESS;
 975 }
 976
 977 /**
 978  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 979  *  @hw: pointer to hardware structure
 980  *
 981  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 982  *  ixgbe_hw struct in order to set up EEPROM access.
 983  **/
 984 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 985 {
 986         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 987         u32 eec;
 988         u16 eeprom_size;
 989
 990         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 991
 992         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 993                 eeprom->semaphore_delay = 10;
 994                 eeprom->type = ixgbe_flash;
 995
 996                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 997                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 998                                     IXGBE_EEC_SIZE_SHIFT);
 999                 eeprom->word_size = 1 << (eeprom_size +
1000                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
1001
1002                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
1003                           eeprom->type, eeprom->word_size);
1004         }
1005
1006         return IXGBE_SUCCESS;
1007 }
1008
1009 /**
1010  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1011  * @hw: pointer to hardware structure
1012  * @enable: enable or disable source address pruning
1013  * @pool: Rx pool to set source address pruning for
1014  **/
1015 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1016                                            unsigned int pool)
1017 {
1018         u64 pfflp;
1019
1020         /* max rx pool is 63 */
1021         if (pool > 63)
1022                 return;
1023
1024         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1025         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1026
1027         if (enable)
1028                 pfflp |= (1ULL << pool);
1029         else
1030                 pfflp &= ~(1ULL << pool);
1031
1032         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1033         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1034 }
1035
1036 /**
1037  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1038  *  @hw: pointer to hardware structure
1039  *  @enable: enable or disable switch for Ethertype anti-spoofing
1040  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1041  *
1042  **/
1043 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1044                 bool enable, int vf)
1045 {
1046         int vf_target_reg = vf >> 3;
1047         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1048         u32 pfvfspoof;
1049
1050         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1051
1052         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1053         if (enable)
1054                 pfvfspoof |= (1 << vf_target_shift);
1055         else
1056                 pfvfspoof &= ~(1 << vf_target_shift);
1057
1058         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1059 }
1060
1061 /**
1062  * ixgbe_iosf_wait - Wait for IOSF command completion
1063  * @hw: pointer to hardware structure
1064  * @ctrl: pointer to location to receive final IOSF control value
1065  *
1066  * Returns failing status on timeout
1067  *
1068  * Note: ctrl can be NULL if the IOSF control register value is not needed
1069  **/
1070 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1071 {
1072         u32 i, command = 0;
1073
1074         /* Check every 10 usec to see if the address cycle completed.
1075          * The SB IOSF BUSY bit will clear when the operation is
1076          * complete
1077          */
1078         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1079                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1080                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1081                         break;
1082                 usec_delay(10);
1083         }
1084         if (ctrl)
1085                 *ctrl = command;
1086         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1087                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1088                 return IXGBE_ERR_PHY;
1089         }
1090
1091         return IXGBE_SUCCESS;
1092 }
1093
1094 /**
1095  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register
1096  *  of the IOSF device
1097  *  @hw: pointer to hardware structure
1098  *  @reg_addr: 32 bit PHY register to write
1099  *  @device_type: 3 bit device type
1100  *  @data: Data to write to the register
1101  **/
1102 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1103                             u32 device_type, u32 data)
1104 {
1105         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1106         u32 command, error;
1107         s32 ret;
1108
1109         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1110         if (ret != IXGBE_SUCCESS)
1111                 return ret;
1112
1113         ret = ixgbe_iosf_wait(hw, NULL);
1114         if (ret != IXGBE_SUCCESS)
1115                 goto out;
1116
1117         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1118                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1119
1120         /* Write IOSF control register */
1121         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1122
1123         /* Write IOSF data register */
1124         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1125
1126         ret = ixgbe_iosf_wait(hw, &command);
1127
1128         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1129                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1130                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1131                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1132                               "Failed to write, error %x\n", error);
1133                 ret = IXGBE_ERR_PHY;
1134         }
1135
1136 out:
1137         ixgbe_release_swfw_semaphore(hw, gssr);
1138         return ret;
1139 }
1140
1141 /**
1142  *  ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device
1143  *  @hw: pointer to hardware structure
1144  *  @reg_addr: 32 bit PHY register to write
1145  *  @device_type: 3 bit device type
1146  *  @data: Pointer to read data from the register
1147  **/
1148 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1149                            u32 device_type, u32 *data)
1150 {
1151         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1152         u32 command, error;
1153         s32 ret;
1154
1155         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1156         if (ret != IXGBE_SUCCESS)
1157                 return ret;
1158
1159         ret = ixgbe_iosf_wait(hw, NULL);
1160         if (ret != IXGBE_SUCCESS)
1161                 goto out;
1162
1163         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1164                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1165
1166         /* Write IOSF control register */
1167         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1168
1169         ret = ixgbe_iosf_wait(hw, &command);
1170
1171         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1172                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1173                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1174                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1175                                 "Failed to read, error %x\n", error);
1176                 ret = IXGBE_ERR_PHY;
1177         }
1178
1179         if (ret == IXGBE_SUCCESS)
1180                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1181
1182 out:
1183         ixgbe_release_swfw_semaphore(hw, gssr);
1184         return ret;
1185 }
1186
1187 /**
1188  * ixgbe_get_phy_token - Get the token for shared phy access
1189  * @hw: Pointer to hardware structure
1190  */
1191
1192 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1193 {
1194         struct ixgbe_hic_phy_token_req token_cmd;
1195         s32 status;
1196
1197         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1198         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1199         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1200         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1201         token_cmd.port_number = hw->bus.lan_id;
1202         token_cmd.command_type = FW_PHY_TOKEN_REQ;
1203         token_cmd.pad = 0;
1204         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1205                                               sizeof(token_cmd),
1206                                               IXGBE_HI_COMMAND_TIMEOUT,
1207                                               true);
1208         if (status) {
1209                 DEBUGOUT1("Issuing host interface command failed with Status = %d\n",
1210                           status);
1211                 return status;
1212         }
1213         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1214                 return IXGBE_SUCCESS;
1215         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY) {
1216                 DEBUGOUT1("Host interface command returned 0x%08x , returning IXGBE_ERR_FW_RESP_INVALID\n",
1217                           token_cmd.hdr.cmd_or_resp.ret_status);
1218                 return IXGBE_ERR_FW_RESP_INVALID;
1219         }
1220
1221         DEBUGOUT("Returning  IXGBE_ERR_TOKEN_RETRY\n");
1222         return IXGBE_ERR_TOKEN_RETRY;
1223 }
1224
1225 /**
1226  * ixgbe_put_phy_token - Put the token for shared phy access
1227  * @hw: Pointer to hardware structure
1228  */
1229
1230 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1231 {
1232         struct ixgbe_hic_phy_token_req token_cmd;
1233         s32 status;
1234
1235         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1236         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1237         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1238         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1239         token_cmd.port_number = hw->bus.lan_id;
1240         token_cmd.command_type = FW_PHY_TOKEN_REL;
1241         token_cmd.pad = 0;
1242         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1243                                               sizeof(token_cmd),
1244                                               IXGBE_HI_COMMAND_TIMEOUT,
1245                                               true);
1246         if (status)
1247                 return status;
1248         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1249                 return IXGBE_SUCCESS;
1250
1251         DEBUGOUT("Put PHY Token host interface command failed");
1252         return IXGBE_ERR_FW_RESP_INVALID;
1253 }
1254
1255 /**
1256  *  ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1257  *  of the IOSF device
1258  *  @hw: pointer to hardware structure
1259  *  @reg_addr: 32 bit PHY register to write
1260  *  @device_type: 3 bit device type
1261  *  @data: Data to write to the register
1262  **/
1263 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1264                                   u32 device_type, u32 data)
1265 {
1266         struct ixgbe_hic_internal_phy_req write_cmd;
1267         s32 status;
1268         UNREFERENCED_1PARAMETER(device_type);
1269
1270         memset(&write_cmd, 0, sizeof(write_cmd));
1271         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1272         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1273         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1274         write_cmd.port_number = hw->bus.lan_id;
1275         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1276         write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1277         write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1278
1279         status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1280                                               sizeof(write_cmd),
1281                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1282
1283         return status;
1284 }
1285
1286 /**
1287  *  ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device
1288  *  @hw: pointer to hardware structure
1289  *  @reg_addr: 32 bit PHY register to write
1290  *  @device_type: 3 bit device type
1291  *  @data: Pointer to read data from the register
1292  **/
1293 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1294                                  u32 device_type, u32 *data)
1295 {
1296         union {
1297                 struct ixgbe_hic_internal_phy_req cmd;
1298                 struct ixgbe_hic_internal_phy_resp rsp;
1299         } hic;
1300         s32 status;
1301         UNREFERENCED_1PARAMETER(device_type);
1302
1303         memset(&hic, 0, sizeof(hic));
1304         hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1305         hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1306         hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1307         hic.cmd.port_number = hw->bus.lan_id;
1308         hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1309         hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1310
1311         status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1312                                               sizeof(hic.cmd),
1313                                               IXGBE_HI_COMMAND_TIMEOUT, true);
1314
1315         /* Extract the register value from the response. */
1316         *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1317
1318         return status;
1319 }
1320
1321 /**
1322  *  ixgbe_disable_mdd_X550
1323  *  @hw: pointer to hardware structure
1324  *
1325  *  Disable malicious driver detection
1326  **/
1327 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1328 {
1329         u32 reg;
1330
1331         DEBUGFUNC("ixgbe_disable_mdd_X550");
1332
1333         /* Disable MDD for TX DMA and interrupt */
1334         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1335         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1336         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1337
1338         /* Disable MDD for RX and interrupt */
1339         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1340         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1341         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1342 }
1343
1344 /**
1345  *  ixgbe_enable_mdd_X550
1346  *  @hw: pointer to hardware structure
1347  *
1348  *  Enable malicious driver detection
1349  **/
1350 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1351 {
1352         u32 reg;
1353
1354         DEBUGFUNC("ixgbe_enable_mdd_X550");
1355
1356         /* Enable MDD for TX DMA and interrupt */
1357         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1358         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1359         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1360
1361         /* Enable MDD for RX and interrupt */
1362         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1363         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1364         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1365 }
1366
1367 /**
1368  *  ixgbe_restore_mdd_vf_X550
1369  *  @hw: pointer to hardware structure
1370  *  @vf: vf index
1371  *
1372  *  Restore VF that was disabled during malicious driver detection event
1373  **/
1374 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1375 {
1376         u32 idx, reg, num_qs, start_q, bitmask;
1377
1378         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1379
1380         /* Map VF to queues */
1381         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1382         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1383         case IXGBE_MRQC_VMDQRT8TCEN:
1384                 num_qs = 8;  /* 16 VFs / pools */
1385                 bitmask = 0x000000FF;
1386                 break;
1387         case IXGBE_MRQC_VMDQRSS32EN:
1388         case IXGBE_MRQC_VMDQRT4TCEN:
1389                 num_qs = 4;  /* 32 VFs / pools */
1390                 bitmask = 0x0000000F;
1391                 break;
1392         default:            /* 64 VFs / pools */
1393                 num_qs = 2;
1394                 bitmask = 0x00000003;
1395                 break;
1396         }
1397         start_q = vf * num_qs;
1398
1399         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1400         idx = start_q / 32;
1401         reg = 0;
1402         reg |= (bitmask << (start_q % 32));
1403         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1404         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1405 }
1406
1407 /**
1408  *  ixgbe_mdd_event_X550
1409  *  @hw: pointer to hardware structure
1410  *  @vf_bitmap: vf bitmap of malicious vfs
1411  *
1412  *  Handle malicious driver detection event.
1413  **/
1414 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1415 {
1416         u32 wqbr;
1417         u32 i, j, reg, q, shift, vf, idx;
1418
1419         DEBUGFUNC("ixgbe_mdd_event_X550");
1420
1421         /* figure out pool size for mapping to vf's */
1422         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1423         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1424         case IXGBE_MRQC_VMDQRT8TCEN:
1425                 shift = 3;  /* 16 VFs / pools */
1426                 break;
1427         case IXGBE_MRQC_VMDQRSS32EN:
1428         case IXGBE_MRQC_VMDQRT4TCEN:
1429                 shift = 2;  /* 32 VFs / pools */
1430                 break;
1431         default:
1432                 shift = 1;  /* 64 VFs / pools */
1433                 break;
1434         }
1435
1436         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1437         for (i = 0; i < 4; i++) {
1438                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1439                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1440
1441                 if (!wqbr)
1442                         continue;
1443
1444                 /* Get malicious queue */
1445                 for (j = 0; j < 32 && wqbr; j++) {
1446
1447                         if (!(wqbr & (1 << j)))
1448                                 continue;
1449
1450                         /* Get queue from bitmask */
1451                         q = j + (i * 32);
1452
1453                         /* Map queue to vf */
1454                         vf = (q >> shift);
1455
1456                         /* Set vf bit in vf_bitmap */
1457                         idx = vf / 32;
1458                         vf_bitmap[idx] |= (1 << (vf % 32));
1459                         wqbr &= ~(1 << j);
1460                 }
1461         }
1462 }
1463
1464 /**
1465  *  ixgbe_get_media_type_X550em - Get media type
1466  *  @hw: pointer to hardware structure
1467  *
1468  *  Returns the media type (fiber, copper, backplane)
1469  */
1470 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1471 {
1472         enum ixgbe_media_type media_type;
1473
1474         DEBUGFUNC("ixgbe_get_media_type_X550em");
1475
1476         /* Detect if there is a copper PHY attached. */
1477         switch (hw->device_id) {
1478         case IXGBE_DEV_ID_X550EM_X_KR:
1479         case IXGBE_DEV_ID_X550EM_X_KX4:
1480         case IXGBE_DEV_ID_X550EM_X_XFI:
1481         case IXGBE_DEV_ID_X550EM_A_KR:
1482         case IXGBE_DEV_ID_X550EM_A_KR_L:
1483                 media_type = ixgbe_media_type_backplane;
1484                 break;
1485         case IXGBE_DEV_ID_X550EM_X_SFP:
1486         case IXGBE_DEV_ID_X550EM_A_SFP:
1487         case IXGBE_DEV_ID_X550EM_A_SFP_N:
1488         case IXGBE_DEV_ID_X550EM_A_QSFP:
1489         case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1490                 media_type = ixgbe_media_type_fiber;
1491                 break;
1492         case IXGBE_DEV_ID_X550EM_X_1G_T:
1493         case IXGBE_DEV_ID_X550EM_X_10G_T:
1494         case IXGBE_DEV_ID_X550EM_A_10G_T:
1495                 media_type = ixgbe_media_type_copper;
1496                 break;
1497         case IXGBE_DEV_ID_X550EM_A_SGMII:
1498         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1499                 media_type = ixgbe_media_type_backplane;
1500                 hw->phy.type = ixgbe_phy_sgmii;
1501                 break;
1502         case IXGBE_DEV_ID_X550EM_A_1G_T:
1503         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1504                 media_type = ixgbe_media_type_copper;
1505                 break;
1506         default:
1507                 media_type = ixgbe_media_type_unknown;
1508                 break;
1509         }
1510         return media_type;
1511 }
1512
1513 /**
1514  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1515  *  @hw: pointer to hardware structure
1516  *  @linear: true if SFP module is linear
1517  */
1518 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1519 {
1520         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1521
1522         switch (hw->phy.sfp_type) {
1523         case ixgbe_sfp_type_not_present:
1524                 return IXGBE_ERR_SFP_NOT_PRESENT;
1525         case ixgbe_sfp_type_da_cu_core0:
1526         case ixgbe_sfp_type_da_cu_core1:
1527                 *linear = true;
1528                 break;
1529         case ixgbe_sfp_type_srlr_core0:
1530         case ixgbe_sfp_type_srlr_core1:
1531         case ixgbe_sfp_type_da_act_lmt_core0:
1532         case ixgbe_sfp_type_da_act_lmt_core1:
1533         case ixgbe_sfp_type_1g_sx_core0:
1534         case ixgbe_sfp_type_1g_sx_core1:
1535         case ixgbe_sfp_type_1g_lx_core0:
1536         case ixgbe_sfp_type_1g_lx_core1:
1537                 *linear = false;
1538                 break;
1539         case ixgbe_sfp_type_unknown:
1540         case ixgbe_sfp_type_1g_cu_core0:
1541         case ixgbe_sfp_type_1g_cu_core1:
1542         default:
1543                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1544         }
1545
1546         return IXGBE_SUCCESS;
1547 }
1548
1549 /**
1550  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1551  *  @hw: pointer to hardware structure
1552  *
1553  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1554  **/
1555 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1556 {
1557         s32 status;
1558         bool linear;
1559
1560         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1561
1562         status = ixgbe_identify_module_generic(hw);
1563
1564         if (status != IXGBE_SUCCESS)
1565                 return status;
1566
1567         /* Check if SFP module is supported */
1568         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1569
1570         return status;
1571 }
1572
1573 /**
1574  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1575  *  @hw: pointer to hardware structure
1576  */
1577 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1578 {
1579         s32 status;
1580         bool linear;
1581
1582         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1583
1584         /* Check if SFP module is supported */
1585         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1586
1587         if (status != IXGBE_SUCCESS)
1588                 return status;
1589
1590         ixgbe_init_mac_link_ops_X550em(hw);
1591         hw->phy.ops.reset = NULL;
1592
1593         return IXGBE_SUCCESS;
1594 }
1595
1596 /**
1597 *  ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1598 *  internal PHY
1599 *  @hw: pointer to hardware structure
1600 **/
1601 STATIC s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1602 {
1603         s32 status;
1604         u32 link_ctrl;
1605
1606         /* Restart auto-negotiation. */
1607         status = hw->mac.ops.read_iosf_sb_reg(hw,
1608                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1609                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1610
1611         if (status) {
1612                 DEBUGOUT("Auto-negotiation did not complete\n");
1613                 return status;
1614         }
1615
1616         link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1617         status = hw->mac.ops.write_iosf_sb_reg(hw,
1618                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1619                                         IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1620
1621         if (hw->mac.type == ixgbe_mac_X550EM_a) {
1622                 u32 flx_mask_st20;
1623
1624                 /* Indicate to FW that AN restart has been asserted */
1625                 status = hw->mac.ops.read_iosf_sb_reg(hw,
1626                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1627                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1628
1629                 if (status) {
1630                         DEBUGOUT("Auto-negotiation did not complete\n");
1631                         return status;
1632                 }
1633
1634                 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1635                 status = hw->mac.ops.write_iosf_sb_reg(hw,
1636                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1637                                 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1638         }
1639
1640         return status;
1641 }
1642
1643 #ifndef PREBOOT_SUPPORT
1644 /**
1645  * ixgbe_setup_sgmii - Set up link for sgmii
1646  * @hw: pointer to hardware structure
1647  * @speed: new link speed
1648  * @autoneg_wait: true when waiting for completion is needed
1649  */
1650 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1651                              bool autoneg_wait)
1652 {
1653         struct ixgbe_mac_info *mac = &hw->mac;
1654         u32 lval, sval, flx_val;
1655         s32 rc;
1656
1657         rc = mac->ops.read_iosf_sb_reg(hw,
1658                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1659                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1660         if (rc)
1661                 return rc;
1662
1663         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1664         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1665         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1666         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1667         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1668         rc = mac->ops.write_iosf_sb_reg(hw,
1669                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1670                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1671         if (rc)
1672                 return rc;
1673
1674         rc = mac->ops.read_iosf_sb_reg(hw,
1675                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1676                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1677         if (rc)
1678                 return rc;
1679
1680         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1681         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1682         rc = mac->ops.write_iosf_sb_reg(hw,
1683                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1684                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1685         if (rc)
1686                 return rc;
1687
1688         rc = mac->ops.read_iosf_sb_reg(hw,
1689                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1690                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1691         if (rc)
1692                 return rc;
1693
1694         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1695         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1696         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1697         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1698         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1699
1700         rc = mac->ops.write_iosf_sb_reg(hw,
1701                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1702                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1703         if (rc)
1704                 return rc;
1705
1706         rc = ixgbe_restart_an_internal_phy_x550em(hw);
1707         if (rc)
1708                 return rc;
1709
1710         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1711 }
1712
1713 #endif /* PREBOOT_SUPPORT */
1714 /**
1715  * ixgbe_setup_sgmii_fw - Set up link for internal PHY SGMII auto-negotiation
1716  * @hw: pointer to hardware structure
1717  * @speed: new link speed
1718  * @autoneg_wait: true when waiting for completion is needed
1719  */
1720 STATIC s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1721                                 bool autoneg_wait)
1722 {
1723         struct ixgbe_mac_info *mac = &hw->mac;
1724         u32 lval, sval, flx_val;
1725         s32 rc;
1726
1727         rc = mac->ops.read_iosf_sb_reg(hw,
1728                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1729                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1730         if (rc)
1731                 return rc;
1732
1733         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1734         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1735         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1736         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1737         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1738         rc = mac->ops.write_iosf_sb_reg(hw,
1739                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1740                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1741         if (rc)
1742                 return rc;
1743
1744         rc = mac->ops.read_iosf_sb_reg(hw,
1745                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1746                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1747         if (rc)
1748                 return rc;
1749
1750         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1751         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1752         rc = mac->ops.write_iosf_sb_reg(hw,
1753                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1754                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1755         if (rc)
1756                 return rc;
1757
1758         rc = mac->ops.write_iosf_sb_reg(hw,
1759                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1760                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1761         if (rc)
1762                 return rc;
1763
1764         rc = mac->ops.read_iosf_sb_reg(hw,
1765                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1766                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1767         if (rc)
1768                 return rc;
1769
1770         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1771         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
1772         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1773         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1774         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1775
1776         rc = mac->ops.write_iosf_sb_reg(hw,
1777                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1778                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1779         if (rc)
1780                 return rc;
1781
1782         rc = ixgbe_restart_an_internal_phy_x550em(hw);
1783
1784         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1785 }
1786
1787 /**
1788  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1789  *  @hw: pointer to hardware structure
1790  */
1791 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1792 {
1793         struct ixgbe_mac_info *mac = &hw->mac;
1794
1795         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1796
1797         switch (hw->mac.ops.get_media_type(hw)) {
1798         case ixgbe_media_type_fiber:
1799                 /* CS4227 does not support autoneg, so disable the laser control
1800                  * functions for SFP+ fiber
1801                  */
1802                 mac->ops.disable_tx_laser = NULL;
1803                 mac->ops.enable_tx_laser = NULL;
1804                 mac->ops.flap_tx_laser = NULL;
1805                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1806                 mac->ops.set_rate_select_speed =
1807                                         ixgbe_set_soft_rate_select_speed;
1808
1809                 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1810                     (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1811                         mac->ops.setup_mac_link =
1812                                                 ixgbe_setup_mac_link_sfp_x550a;
1813                 else
1814                         mac->ops.setup_mac_link =
1815                                                 ixgbe_setup_mac_link_sfp_x550em;
1816                 break;
1817         case ixgbe_media_type_copper:
1818                 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T)
1819                         break;
1820                 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1821                         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
1822                             hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
1823                                 mac->ops.setup_link = ixgbe_setup_sgmii_fw;
1824                                 mac->ops.check_link =
1825                                                    ixgbe_check_mac_link_generic;
1826                         } else {
1827                                 mac->ops.setup_link =
1828                                                   ixgbe_setup_mac_link_t_X550em;
1829                         }
1830                 } else {
1831                         mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1832                         mac->ops.check_link = ixgbe_check_link_t_X550em;
1833                 }
1834                 break;
1835         case ixgbe_media_type_backplane:
1836                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1837                     hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1838 #ifdef PREBOOT_SUPPORT
1839                         mac->ops.setup_link = ixgbe_setup_sgmii_fw;
1840 #else
1841                         mac->ops.setup_link = ixgbe_setup_sgmii;
1842 #endif /* PREBOOT_SUPPORT */
1843                 break;
1844         default:
1845                 break;
1846         }
1847 }
1848
1849 /**
1850  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1851  *  @hw: pointer to hardware structure
1852  *  @speed: pointer to link speed
1853  *  @autoneg: true when autoneg or autotry is enabled
1854  */
1855 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1856                                        ixgbe_link_speed *speed,
1857                                        bool *autoneg)
1858 {
1859         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1860
1861
1862         if (hw->phy.type == ixgbe_phy_fw) {
1863                 *autoneg = true;
1864                 *speed = hw->phy.speeds_supported;
1865                 return 0;
1866         }
1867
1868         /* SFP */
1869         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1870
1871                 /* CS4227 SFP must not enable auto-negotiation */
1872                 *autoneg = false;
1873
1874                 /* Check if 1G SFP module. */
1875                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1876                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1877                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1878                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1879                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1880                         return IXGBE_SUCCESS;
1881                 }
1882
1883                 /* Link capabilities are based on SFP */
1884                 if (hw->phy.multispeed_fiber)
1885                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1886                                  IXGBE_LINK_SPEED_1GB_FULL;
1887                 else
1888                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1889         } else {
1890                 switch (hw->phy.type) {
1891                 case ixgbe_phy_ext_1g_t:
1892 #ifdef PREBOOT_SUPPORT
1893                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1894                         break;
1895 #endif /* PREBOOT_SUPPORT */
1896                 case ixgbe_phy_sgmii:
1897 #ifdef PREBOOT_SUPPORT
1898                         *speed = IXGBE_LINK_SPEED_1GB_FULL |
1899                                  IXGBE_LINK_SPEED_100_FULL |
1900                                  IXGBE_LINK_SPEED_10_FULL;
1901 #else
1902                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1903 #endif /* PREBOOT_SUPPORT */
1904                         break;
1905                 case ixgbe_phy_x550em_kr:
1906                         if (hw->mac.type == ixgbe_mac_X550EM_a) {
1907                                 /* check different backplane modes */
1908                                 if (hw->phy.nw_mng_if_sel &
1909                                            IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
1910                                         *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
1911                                         break;
1912                                 } else if (hw->device_id ==
1913                                                    IXGBE_DEV_ID_X550EM_A_KR_L) {
1914                                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1915                                         break;
1916                                 }
1917                         }
1918                         /* fall through */
1919                 default:
1920                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1921                                  IXGBE_LINK_SPEED_1GB_FULL;
1922                         break;
1923                 }
1924                 *autoneg = true;
1925         }
1926
1927         return IXGBE_SUCCESS;
1928 }
1929
1930 /**
1931  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1932  * @hw: pointer to hardware structure
1933  * @lsc: pointer to boolean flag which indicates whether external Base T
1934  *       PHY interrupt is lsc
1935  *
1936  * Determime if external Base T PHY interrupt cause is high temperature
1937  * failure alarm or link status change.
1938  *
1939  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1940  * failure alarm, else return PHY access status.
1941  */
1942 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1943 {
1944         u32 status;
1945         u16 reg;
1946
1947         *lsc = false;
1948
1949         /* Vendor alarm triggered */
1950         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1951                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1952                                       &reg);
1953
1954         if (status != IXGBE_SUCCESS ||
1955             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1956                 return status;
1957
1958         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1959         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1960                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1961                                       &reg);
1962
1963         if (status != IXGBE_SUCCESS ||
1964             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1965             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1966                 return status;
1967
1968         /* Global alarm triggered */
1969         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1970                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1971                                       &reg);
1972
1973         if (status != IXGBE_SUCCESS)
1974                 return status;
1975
1976         /* If high temperature failure, then return over temp error and exit */
1977         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1978                 /* power down the PHY in case the PHY FW didn't already */
1979                 ixgbe_set_copper_phy_power(hw, false);
1980                 return IXGBE_ERR_OVERTEMP;
1981         } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1982                 /*  device fault alarm triggered */
1983                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1984                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1985                                           &reg);
1986
1987                 if (status != IXGBE_SUCCESS)
1988                         return status;
1989
1990                 /* if device fault was due to high temp alarm handle and exit */
1991                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1992                         /* power down the PHY in case the PHY FW didn't */
1993                         ixgbe_set_copper_phy_power(hw, false);
1994                         return IXGBE_ERR_OVERTEMP;
1995                 }
1996         }
1997
1998         /* Vendor alarm 2 triggered */
1999         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2000                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2001
2002         if (status != IXGBE_SUCCESS ||
2003             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
2004                 return status;
2005
2006         /* link connect/disconnect event occurred */
2007         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
2008                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2009
2010         if (status != IXGBE_SUCCESS)
2011                 return status;
2012
2013         /* Indicate LSC */
2014         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2015                 *lsc = true;
2016
2017         return IXGBE_SUCCESS;
2018 }
2019
2020 /**
2021  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2022  * @hw: pointer to hardware structure
2023  *
2024  * Enable link status change and temperature failure alarm for the external
2025  * Base T PHY
2026  *
2027  * Returns PHY access status
2028  */
2029 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2030 {
2031         u32 status;
2032         u16 reg;
2033         bool lsc;
2034
2035         /* Clear interrupt flags */
2036         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2037
2038         /* Enable link status change alarm */
2039
2040         /* Enable the LASI interrupts on X552 devices to receive notifications
2041          * of the link configurations of the external PHY and correspondingly
2042          * support the configuration of the internal iXFI link, since iXFI does
2043          * not support auto-negotiation. This is not required for X553 devices
2044          * having KR support, which performs auto-negotiations and which is used
2045          * as the internal link to the external PHY. Hence adding a check here
2046          * to avoid enabling LASI interrupts for X553 devices.
2047          */
2048         if (hw->mac.type != ixgbe_mac_X550EM_a) {
2049                 status = hw->phy.ops.read_reg(hw,
2050                                         IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2051                                         IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2052
2053                 if (status != IXGBE_SUCCESS)
2054                         return status;
2055
2056                 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2057
2058                 status = hw->phy.ops.write_reg(hw,
2059                                         IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2060                                         IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
2061
2062                 if (status != IXGBE_SUCCESS)
2063                         return status;
2064         }
2065
2066         /* Enable high temperature failure and global fault alarms */
2067         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2068                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2069                                       &reg);
2070
2071         if (status != IXGBE_SUCCESS)
2072                 return status;
2073
2074         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2075                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2076
2077         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2078                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2079                                        reg);
2080
2081         if (status != IXGBE_SUCCESS)
2082                 return status;
2083
2084         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2085         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2086                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2087                                       &reg);
2088
2089         if (status != IXGBE_SUCCESS)
2090                 return status;
2091
2092         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2093                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2094
2095         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2096                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2097                                        reg);
2098
2099         if (status != IXGBE_SUCCESS)
2100                 return status;
2101
2102         /* Enable chip-wide vendor alarm */
2103         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2104                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2105                                       &reg);
2106
2107         if (status != IXGBE_SUCCESS)
2108                 return status;
2109
2110         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2111
2112         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2113                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2114                                        reg);
2115
2116         return status;
2117 }
2118
2119 /**
2120  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2121  *  @hw: pointer to hardware structure
2122  *  @speed: link speed
2123  *
2124  *  Configures the integrated KR PHY.
2125  **/
2126 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2127                                        ixgbe_link_speed speed)
2128 {
2129         s32 status;
2130         u32 reg_val;
2131
2132         status = hw->mac.ops.read_iosf_sb_reg(hw,
2133                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2134                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2135         if (status)
2136                 return status;
2137
2138         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2139         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2140                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2141
2142         /* Advertise 10G support. */
2143         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2144                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2145
2146         /* Advertise 1G support. */
2147         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2148                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2149
2150         status = hw->mac.ops.write_iosf_sb_reg(hw,
2151                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2152                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2153
2154         if (hw->mac.type == ixgbe_mac_X550EM_a) {
2155                 /* Set lane mode  to KR auto negotiation */
2156                 status = hw->mac.ops.read_iosf_sb_reg(hw,
2157                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2158                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2159
2160                 if (status)
2161                         return status;
2162
2163                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2164                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2165                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2166                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2167                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2168
2169                 status = hw->mac.ops.write_iosf_sb_reg(hw,
2170                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2171                                     IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2172         }
2173
2174         return ixgbe_restart_an_internal_phy_x550em(hw);
2175 }
2176
2177 /**
2178  * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs
2179  * @hw: pointer to hardware structure
2180  */
2181 static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw)
2182 {
2183         u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
2184         s32 rc;
2185
2186         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2187                 return IXGBE_SUCCESS;
2188
2189         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store);
2190         if (rc)
2191                 return rc;
2192         memset(store, 0, sizeof(store));
2193
2194         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store);
2195         if (rc)
2196                 return rc;
2197
2198         return ixgbe_setup_fw_link(hw);
2199 }
2200
2201 /**
2202  * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp
2203  * @hw: pointer to hardware structure
2204  */
2205 static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw)
2206 {
2207         u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
2208         s32 rc;
2209
2210         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store);
2211         if (rc)
2212                 return rc;
2213
2214         if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) {
2215                 ixgbe_shutdown_fw_phy(hw);
2216                 return IXGBE_ERR_OVERTEMP;
2217         }
2218         return IXGBE_SUCCESS;
2219 }
2220
2221 /**
2222  *  ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2223  *  @hw: pointer to hardware structure
2224  *
2225  *  Read NW_MNG_IF_SEL register and save field values, and check for valid field
2226  *  values.
2227  **/
2228 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2229 {
2230         /* Save NW management interface connected on board. This is used
2231          * to determine internal PHY mode.
2232          */
2233         hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2234
2235         /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2236          * PHY address. This register field was has only been used for X552.
2237          */
2238         if (hw->mac.type == ixgbe_mac_X550EM_a &&
2239             hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2240                 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2241                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2242                                IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2243         }
2244
2245         return IXGBE_SUCCESS;
2246 }
2247
2248 /**
2249  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2250  *  @hw: pointer to hardware structure
2251  *
2252  *  Initialize any function pointers that were not able to be
2253  *  set during init_shared_code because the PHY/SFP type was
2254  *  not known.  Perform the SFP init if necessary.
2255  */
2256 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2257 {
2258         struct ixgbe_phy_info *phy = &hw->phy;
2259         s32 ret_val;
2260
2261         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2262
2263         hw->mac.ops.set_lan_id(hw);
2264         ixgbe_read_mng_if_sel_x550em(hw);
2265
2266         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2267                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2268                 ixgbe_setup_mux_ctl(hw);
2269                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2270         }
2271
2272         switch (hw->device_id) {
2273         case IXGBE_DEV_ID_X550EM_A_1G_T:
2274         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2275                 phy->ops.read_reg_mdi = NULL;
2276                 phy->ops.write_reg_mdi = NULL;
2277                 hw->phy.ops.read_reg = NULL;
2278                 hw->phy.ops.write_reg = NULL;
2279                 phy->ops.check_overtemp = ixgbe_check_overtemp_fw;
2280                 if (hw->bus.lan_id)
2281                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2282                 else
2283                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2284
2285                 break;
2286         case IXGBE_DEV_ID_X550EM_A_10G_T:
2287         case IXGBE_DEV_ID_X550EM_A_SFP:
2288                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2289                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2290                 if (hw->bus.lan_id)
2291                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2292                 else
2293                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2294                 break;
2295         case IXGBE_DEV_ID_X550EM_X_SFP:
2296                 /* set up for CS4227 usage */
2297                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2298                 break;
2299         case IXGBE_DEV_ID_X550EM_X_1G_T:
2300                 phy->ops.read_reg_mdi = NULL;
2301                 phy->ops.write_reg_mdi = NULL;
2302         default:
2303                 break;
2304         }
2305
2306         /* Identify the PHY or SFP module */
2307         ret_val = phy->ops.identify(hw);
2308         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED ||
2309             ret_val == IXGBE_ERR_PHY_ADDR_INVALID)
2310                 return ret_val;
2311
2312         /* Setup function pointers based on detected hardware */
2313         ixgbe_init_mac_link_ops_X550em(hw);
2314         if (phy->sfp_type != ixgbe_sfp_type_unknown)
2315                 phy->ops.reset = NULL;
2316
2317         /* Set functions pointers based on phy type */
2318         switch (hw->phy.type) {
2319         case ixgbe_phy_x550em_kx4:
2320                 phy->ops.setup_link = NULL;
2321                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2322                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2323                 break;
2324         case ixgbe_phy_x550em_kr:
2325                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2326                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2327                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2328                 break;
2329         case ixgbe_phy_ext_1g_t:
2330                 /* link is managed by FW */
2331                 phy->ops.setup_link = NULL;
2332                 phy->ops.reset = NULL;
2333                 break;
2334         case ixgbe_phy_x550em_xfi:
2335                 /* link is managed by HW */
2336                 phy->ops.setup_link = NULL;
2337                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2338                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2339                 break;
2340         case ixgbe_phy_x550em_ext_t:
2341                 /* If internal link mode is XFI, then setup iXFI internal link,
2342                  * else setup KR now.
2343                  */
2344                 phy->ops.setup_internal_link =
2345                                               ixgbe_setup_internal_phy_t_x550em;
2346
2347                 /* setup SW LPLU only for first revision of X550EM_x */
2348                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2349                     !(IXGBE_FUSES0_REV_MASK &
2350                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2351                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2352
2353                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2354                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2355                 break;
2356         case ixgbe_phy_sgmii:
2357                 phy->ops.setup_link = NULL;
2358                 break;
2359         case ixgbe_phy_fw:
2360                 phy->ops.setup_link = ixgbe_setup_fw_link;
2361                 phy->ops.reset = ixgbe_reset_phy_fw;
2362                 break;
2363         default:
2364                 break;
2365         }
2366         return ret_val;
2367 }
2368
2369 /**
2370  * ixgbe_set_mdio_speed - Set MDIO clock speed
2371  *  @hw: pointer to hardware structure
2372  */
2373 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2374 {
2375         u32 hlreg0;
2376
2377         switch (hw->device_id) {
2378         case IXGBE_DEV_ID_X550EM_X_10G_T:
2379         case IXGBE_DEV_ID_X550EM_A_SGMII:
2380         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2381         case IXGBE_DEV_ID_X550EM_A_10G_T:
2382         case IXGBE_DEV_ID_X550EM_A_SFP:
2383         case IXGBE_DEV_ID_X550EM_A_QSFP:
2384                 /* Config MDIO clock speed before the first MDIO PHY access */
2385                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2386                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2387                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2388                 break;
2389         case IXGBE_DEV_ID_X550EM_A_1G_T:
2390         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2391                 /* Select fast MDIO clock speed for these devices */
2392                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2393                 hlreg0 |= IXGBE_HLREG0_MDCSPD;
2394                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2395                 break;
2396         default:
2397                 break;
2398         }
2399 }
2400
2401 /**
2402  *  ixgbe_reset_hw_X550em - Perform hardware reset
2403  *  @hw: pointer to hardware structure
2404  *
2405  *  Resets the hardware by resetting the transmit and receive units, masks
2406  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2407  *  reset.
2408  */
2409 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2410 {
2411         ixgbe_link_speed link_speed;
2412         s32 status;
2413         u32 ctrl = 0;
2414         u32 i;
2415         bool link_up = false;
2416         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2417
2418         DEBUGFUNC("ixgbe_reset_hw_X550em");
2419
2420         /* Call adapter stop to disable Tx/Rx and clear interrupts */
2421         status = hw->mac.ops.stop_adapter(hw);
2422         if (status != IXGBE_SUCCESS) {
2423                 DEBUGOUT1("Failed to stop adapter, STATUS = %d\n", status);
2424                 return status;
2425         }
2426         /* flush pending Tx transactions */
2427         ixgbe_clear_tx_pending(hw);
2428
2429         ixgbe_set_mdio_speed(hw);
2430
2431         /* PHY ops must be identified and initialized prior to reset */
2432         status = hw->phy.ops.init(hw);
2433
2434         if (status)
2435                 DEBUGOUT1("Failed to initialize PHY ops, STATUS = %d\n",
2436                           status);
2437
2438         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED ||
2439             status == IXGBE_ERR_PHY_ADDR_INVALID) {
2440                 DEBUGOUT("Returning from reset HW due to PHY init failure\n");
2441                 return status;
2442         }
2443
2444         /* start the external PHY */
2445         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2446                 status = ixgbe_init_ext_t_x550em(hw);
2447                 if (status) {
2448                         DEBUGOUT1("Failed to start the external PHY, STATUS = %d\n",
2449                                   status);
2450                         return status;
2451                 }
2452         }
2453
2454         /* Setup SFP module if there is one present. */
2455         if (hw->phy.sfp_setup_needed) {
2456                 status = hw->mac.ops.setup_sfp(hw);
2457                 hw->phy.sfp_setup_needed = false;
2458         }
2459
2460         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2461                 return status;
2462
2463         /* Reset PHY */
2464         if (!hw->phy.reset_disable && hw->phy.ops.reset) {
2465                 if (hw->phy.ops.reset(hw) == IXGBE_ERR_OVERTEMP)
2466                         return IXGBE_ERR_OVERTEMP;
2467         }
2468
2469 mac_reset_top:
2470         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2471          * If link reset is used when link is up, it might reset the PHY when
2472          * mng is using it.  If link is down or the flag to force full link
2473          * reset is set, then perform link reset.
2474          */
2475         ctrl = IXGBE_CTRL_LNK_RST;
2476         if (!hw->force_full_reset) {
2477                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2478                 if (link_up)
2479                         ctrl = IXGBE_CTRL_RST;
2480         }
2481
2482         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
2483         if (status != IXGBE_SUCCESS) {
2484                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
2485                         "semaphore failed with %d", status);
2486                 return IXGBE_ERR_SWFW_SYNC;
2487         }
2488         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2489         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2490         IXGBE_WRITE_FLUSH(hw);
2491         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2492
2493         /* Poll for reset bit to self-clear meaning reset is complete */
2494         for (i = 0; i < 10; i++) {
2495                 usec_delay(1);
2496                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2497                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2498                         break;
2499         }
2500
2501         if (ctrl & IXGBE_CTRL_RST_MASK) {
2502                 status = IXGBE_ERR_RESET_FAILED;
2503                 DEBUGOUT("Reset polling failed to complete.\n");
2504         }
2505
2506         msec_delay(50);
2507
2508         /* Double resets are required for recovery from certain error
2509          * conditions.  Between resets, it is necessary to stall to
2510          * allow time for any pending HW events to complete.
2511          */
2512         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2513                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2514                 goto mac_reset_top;
2515         }
2516
2517         /* Store the permanent mac address */
2518         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2519
2520         /* Store MAC address from RAR0, clear receive address registers, and
2521          * clear the multicast table.  Also reset num_rar_entries to 128,
2522          * since we modify this value when programming the SAN MAC address.
2523          */
2524         hw->mac.num_rar_entries = 128;
2525         hw->mac.ops.init_rx_addrs(hw);
2526
2527         ixgbe_set_mdio_speed(hw);
2528
2529         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2530                 ixgbe_setup_mux_ctl(hw);
2531
2532         if (status != IXGBE_SUCCESS)
2533                 DEBUGOUT1("Reset HW failed, STATUS = %d\n", status);
2534
2535         return status;
2536 }
2537
2538 /**
2539  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2540  * @hw: pointer to hardware structure
2541  */
2542 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2543 {
2544         u32 status;
2545         u16 reg;
2546
2547         status = hw->phy.ops.read_reg(hw,
2548                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2549                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2550                                       &reg);
2551
2552         if (status != IXGBE_SUCCESS)
2553                 return status;
2554
2555         /* If PHY FW reset completed bit is set then this is the first
2556          * SW instance after a power on so the PHY FW must be un-stalled.
2557          */
2558         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2559                 status = hw->phy.ops.read_reg(hw,
2560                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2561                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2562                                         &reg);
2563
2564                 if (status != IXGBE_SUCCESS)
2565                         return status;
2566
2567                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2568
2569                 status = hw->phy.ops.write_reg(hw,
2570                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2571                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2572                                         reg);
2573
2574                 if (status != IXGBE_SUCCESS)
2575                         return status;
2576         }
2577
2578         return status;
2579 }
2580
2581 /**
2582  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
2583  *  @hw: pointer to hardware structure
2584  **/
2585 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2586 {
2587         /* leave link alone for 2.5G */
2588         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL)
2589                 return IXGBE_SUCCESS;
2590
2591         if (ixgbe_check_reset_blocked(hw))
2592                 return 0;
2593
2594         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2595 }
2596
2597 /**
2598  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2599  *  @hw: pointer to hardware structure
2600  *  @speed: new link speed
2601  *  @autoneg_wait_to_complete: unused
2602  *
2603  *  Configure the external PHY and the integrated KR PHY for SFP support.
2604  **/
2605 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2606                                     ixgbe_link_speed speed,
2607                                     bool autoneg_wait_to_complete)
2608 {
2609         s32 ret_val;
2610         u16 reg_slice, reg_val;
2611         bool setup_linear = false;
2612         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2613
2614         /* Check if SFP module is supported and linear */
2615         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2616
2617         /* If no SFP module present, then return success. Return success since
2618          * there is no reason to configure CS4227 and SFP not present error is
2619          * not excepted in the setup MAC link flow.
2620          */
2621         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2622                 return IXGBE_SUCCESS;
2623
2624         if (ret_val != IXGBE_SUCCESS)
2625                 return ret_val;
2626
2627         /* Configure internal PHY for KR/KX. */
2628         ixgbe_setup_kr_speed_x550em(hw, speed);
2629
2630         /* Configure CS4227 LINE side to proper mode. */
2631         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2632                     (hw->bus.lan_id << 12);
2633         if (setup_linear)
2634                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2635         else
2636                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2637         ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2638                                           reg_val);
2639         return ret_val;
2640 }
2641
2642 /**
2643  *  ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
2644  *  @hw: pointer to hardware structure
2645  *  @speed: the link speed to force
2646  *
2647  *  Configures the integrated PHY for native SFI mode. Used to connect the
2648  *  internal PHY directly to an SFP cage, without autonegotiation.
2649  **/
2650 STATIC s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2651 {
2652         struct ixgbe_mac_info *mac = &hw->mac;
2653         s32 status;
2654         u32 reg_val;
2655
2656         /* Disable all AN and force speed to 10G Serial. */
2657         status = mac->ops.read_iosf_sb_reg(hw,
2658                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2659                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2660         if (status != IXGBE_SUCCESS)
2661                 return status;
2662
2663         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2664         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2665         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2666         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2667
2668         /* Select forced link speed for internal PHY. */
2669         switch (*speed) {
2670         case IXGBE_LINK_SPEED_10GB_FULL:
2671                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
2672                 break;
2673         case IXGBE_LINK_SPEED_1GB_FULL:
2674                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2675                 break;
2676         default:
2677                 /* Other link speeds are not supported by internal PHY. */
2678                 return IXGBE_ERR_LINK_SETUP;
2679         }
2680
2681         status = mac->ops.write_iosf_sb_reg(hw,
2682                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2683                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2684
2685         /* Toggle port SW reset by AN reset. */
2686         status = ixgbe_restart_an_internal_phy_x550em(hw);
2687
2688         return status;
2689 }
2690
2691 /**
2692  *  ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2693  *  @hw: pointer to hardware structure
2694  *  @speed: new link speed
2695  *  @autoneg_wait_to_complete: unused
2696  *
2697  *  Configure the integrated PHY for SFP support.
2698  **/
2699 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2700                                     ixgbe_link_speed speed,
2701                                     bool autoneg_wait_to_complete)
2702 {
2703         s32 ret_val;
2704         u16 reg_phy_ext;
2705         bool setup_linear = false;
2706         u32 reg_slice, reg_phy_int, slice_offset;
2707
2708         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2709
2710         /* Check if SFP module is supported and linear */
2711         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2712
2713         /* If no SFP module present, then return success. Return success since
2714          * SFP not present error is not excepted in the setup MAC link flow.
2715          */
2716         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2717                 return IXGBE_SUCCESS;
2718
2719         if (ret_val != IXGBE_SUCCESS)
2720                 return ret_val;
2721
2722         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2723                 /* Configure internal PHY for native SFI based on module type */
2724                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2725                                    IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2726                                    IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_phy_int);
2727
2728                 if (ret_val != IXGBE_SUCCESS)
2729                         return ret_val;
2730
2731                 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
2732                 if (!setup_linear)
2733                         reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
2734
2735                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2736                                    IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2737                                    IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2738
2739                 if (ret_val != IXGBE_SUCCESS)
2740                         return ret_val;
2741
2742                 /* Setup SFI internal link. */
2743                 ret_val = ixgbe_setup_sfi_x550a(hw, &speed);
2744         } else {
2745                 /* Configure internal PHY for KR/KX. */
2746                 ixgbe_setup_kr_speed_x550em(hw, speed);
2747
2748                 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2749                         /* Find Address */
2750                         DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2751                         return IXGBE_ERR_PHY_ADDR_INVALID;
2752                 }
2753
2754                 /* Get external PHY SKU id */
2755                 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,
2756                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2757
2758                 if (ret_val != IXGBE_SUCCESS)
2759                         return ret_val;
2760
2761                 /* When configuring quad port CS4223, the MAC instance is part
2762                  * of the slice offset.
2763                  */
2764                 if (reg_phy_ext == IXGBE_CS4223_SKU_ID)
2765                         slice_offset = (hw->bus.lan_id +
2766                                         (hw->bus.instance_id << 1)) << 12;
2767                 else
2768                         slice_offset = hw->bus.lan_id << 12;
2769
2770                 /* Configure CS4227/CS4223 LINE side to proper mode. */
2771                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2772
2773                 ret_val = hw->phy.ops.read_reg(hw, reg_slice,
2774                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2775
2776                 if (ret_val != IXGBE_SUCCESS)
2777                         return ret_val;
2778
2779                 reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) |
2780                                  (IXGBE_CS4227_EDC_MODE_SR << 1));
2781
2782                 if (setup_linear)
2783                         reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2784                 else
2785                         reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2786                 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2787                                          IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2788
2789                 /* Flush previous write with a read */
2790                 ret_val = hw->phy.ops.read_reg(hw, reg_slice,
2791                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2792         }
2793         return ret_val;
2794 }
2795
2796 /**
2797  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2798  *  @hw: pointer to hardware structure
2799  *
2800  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2801  **/
2802 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2803 {
2804         struct ixgbe_mac_info *mac = &hw->mac;
2805         s32 status;
2806         u32 reg_val;
2807
2808         /* Disable training protocol FSM. */
2809         status = mac->ops.read_iosf_sb_reg(hw,
2810                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2811                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2812         if (status != IXGBE_SUCCESS)
2813                 return status;
2814         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2815         status = mac->ops.write_iosf_sb_reg(hw,
2816                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2817                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2818         if (status != IXGBE_SUCCESS)
2819                 return status;
2820
2821         /* Disable Flex from training TXFFE. */
2822         status = mac->ops.read_iosf_sb_reg(hw,
2823                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2824                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2825         if (status != IXGBE_SUCCESS)
2826                 return status;
2827         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2828         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2829         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2830         status = mac->ops.write_iosf_sb_reg(hw,
2831                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2832                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2833         if (status != IXGBE_SUCCESS)
2834                 return status;
2835         status = mac->ops.read_iosf_sb_reg(hw,
2836                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2837                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2838         if (status != IXGBE_SUCCESS)
2839                 return status;
2840         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2841         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2842         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2843         status = mac->ops.write_iosf_sb_reg(hw,
2844                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2845                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2846         if (status != IXGBE_SUCCESS)
2847                 return status;
2848
2849         /* Enable override for coefficients. */
2850         status = mac->ops.read_iosf_sb_reg(hw,
2851                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2852                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2853         if (status != IXGBE_SUCCESS)
2854                 return status;
2855         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2856         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2857         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2858         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2859         status = mac->ops.write_iosf_sb_reg(hw,
2860                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2861                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2862         return status;
2863 }
2864
2865 /**
2866  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2867  *  @hw: pointer to hardware structure
2868  *  @speed: the link speed to force
2869  *
2870  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
2871  *  internal and external PHY at a specific speed, without autonegotiation.
2872  **/
2873 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2874 {
2875         struct ixgbe_mac_info *mac = &hw->mac;
2876         s32 status;
2877         u32 reg_val;
2878
2879         /* iXFI is only supported with X552 */
2880         if (mac->type != ixgbe_mac_X550EM_x)
2881                 return IXGBE_ERR_LINK_SETUP;
2882
2883         /* Disable AN and force speed to 10G Serial. */
2884         status = mac->ops.read_iosf_sb_reg(hw,
2885                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2886                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2887         if (status != IXGBE_SUCCESS)
2888                 return status;
2889
2890         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2891         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2892
2893         /* Select forced link speed for internal PHY. */
2894         switch (*speed) {
2895         case IXGBE_LINK_SPEED_10GB_FULL:
2896                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2897                 break;
2898         case IXGBE_LINK_SPEED_1GB_FULL:
2899                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2900                 break;
2901         default:
2902                 /* Other link speeds are not supported by internal KR PHY. */
2903                 return IXGBE_ERR_LINK_SETUP;
2904         }
2905
2906         status = mac->ops.write_iosf_sb_reg(hw,
2907                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2908                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2909         if (status != IXGBE_SUCCESS)
2910                 return status;
2911
2912         /* Additional configuration needed for x550em_x */
2913         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2914                 status = ixgbe_setup_ixfi_x550em_x(hw);
2915                 if (status != IXGBE_SUCCESS)
2916                         return status;
2917         }
2918
2919         /* Toggle port SW reset by AN reset. */
2920         status = ixgbe_restart_an_internal_phy_x550em(hw);
2921
2922         return status;
2923 }
2924
2925 /**
2926  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2927  * @hw: address of hardware structure
2928  * @link_up: address of boolean to indicate link status
2929  *
2930  * Returns error code if unable to get link status.
2931  */
2932 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2933 {
2934         u32 ret;
2935         u16 autoneg_status;
2936
2937         *link_up = false;
2938
2939         /* read this twice back to back to indicate current status */
2940         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2941                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2942                                    &autoneg_status);
2943         if (ret != IXGBE_SUCCESS)
2944                 return ret;
2945
2946         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2947                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2948                                    &autoneg_status);
2949         if (ret != IXGBE_SUCCESS)
2950                 return ret;
2951
2952         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2953
2954         return IXGBE_SUCCESS;
2955 }
2956
2957 /**
2958  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2959  * @hw: point to hardware structure
2960  *
2961  * Configures the link between the integrated KR PHY and the external X557 PHY
2962  * The driver will call this function when it gets a link status change
2963  * interrupt from the X557 PHY. This function configures the link speed
2964  * between the PHYs to match the link speed of the BASE-T link.
2965  *
2966  * A return of a non-zero value indicates an error, and the base driver should
2967  * not report link up.
2968  */
2969 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2970 {
2971         ixgbe_link_speed force_speed;
2972         bool link_up;
2973         u32 status;
2974         u16 speed;
2975
2976         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2977                 return IXGBE_ERR_CONFIG;
2978
2979         if (hw->mac.type == ixgbe_mac_X550EM_x &&
2980             !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2981                 /* If link is down, there is no setup necessary so return  */
2982                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2983                 if (status != IXGBE_SUCCESS)
2984                         return status;
2985
2986                 if (!link_up)
2987                         return IXGBE_SUCCESS;
2988
2989                 status = hw->phy.ops.read_reg(hw,
2990                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2991                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2992                                               &speed);
2993                 if (status != IXGBE_SUCCESS)
2994                         return status;
2995
2996                 /* If link is still down - no setup is required so return */
2997                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2998                 if (status != IXGBE_SUCCESS)
2999                         return status;
3000                 if (!link_up)
3001                         return IXGBE_SUCCESS;
3002
3003                 /* clear everything but the speed and duplex bits */
3004                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
3005
3006                 switch (speed) {
3007                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
3008                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3009                         break;
3010                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
3011                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3012                         break;
3013                 default:
3014                         /* Internal PHY does not support anything else */
3015                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
3016                 }
3017
3018                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
3019         } else {
3020                 speed = IXGBE_LINK_SPEED_10GB_FULL |
3021                         IXGBE_LINK_SPEED_1GB_FULL;
3022                 return ixgbe_setup_kr_speed_x550em(hw, speed);
3023         }
3024 }
3025
3026 /**
3027  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
3028  *  @hw: pointer to hardware structure
3029  *
3030  *  Configures the integrated KR PHY to use internal loopback mode.
3031  **/
3032 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
3033 {
3034         s32 status;
3035         u32 reg_val;
3036
3037         /* Disable AN and force speed to 10G Serial. */
3038         status = hw->mac.ops.read_iosf_sb_reg(hw,
3039                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3040                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3041         if (status != IXGBE_SUCCESS)
3042                 return status;
3043         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3044         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3045         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3046         status = hw->mac.ops.write_iosf_sb_reg(hw,
3047                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3048                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3049         if (status != IXGBE_SUCCESS)
3050                 return status;
3051
3052         /* Set near-end loopback clocks. */
3053         status = hw->mac.ops.read_iosf_sb_reg(hw,
3054                                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3055                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3056         if (status != IXGBE_SUCCESS)
3057                 return status;
3058         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3059         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3060         status = hw->mac.ops.write_iosf_sb_reg(hw,
3061                                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3062                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3063         if (status != IXGBE_SUCCESS)
3064                 return status;
3065
3066         /* Set loopback enable. */
3067         status = hw->mac.ops.read_iosf_sb_reg(hw,
3068                                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3069                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3070         if (status != IXGBE_SUCCESS)
3071                 return status;
3072         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3073         status = hw->mac.ops.write_iosf_sb_reg(hw,
3074                                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3075                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3076         if (status != IXGBE_SUCCESS)
3077                 return status;
3078
3079         /* Training bypass. */
3080         status = hw->mac.ops.read_iosf_sb_reg(hw,
3081                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3082                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3083         if (status != IXGBE_SUCCESS)
3084                 return status;
3085         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3086         status = hw->mac.ops.write_iosf_sb_reg(hw,
3087                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3088                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3089
3090         return status;
3091 }
3092
3093 /**
3094  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3095  *  assuming that the semaphore is already obtained.
3096  *  @hw: pointer to hardware structure
3097  *  @offset: offset of  word in the EEPROM to read
3098  *  @data: word read from the EEPROM
3099  *
3100  *  Reads a 16 bit word from the EEPROM using the hostif.
3101  **/
3102 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
3103 {
3104         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3105         struct ixgbe_hic_read_shadow_ram buffer;
3106         s32 status;
3107
3108         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3109         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3110         buffer.hdr.req.buf_lenh = 0;
3111         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3112         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3113
3114         /* convert offset from words to bytes */
3115         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3116         /* one word */
3117         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3118         buffer.pad2 = 0;
3119         buffer.pad3 = 0;
3120
3121         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3122         if (status)
3123                 return status;
3124
3125         status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3126                                     IXGBE_HI_COMMAND_TIMEOUT);
3127         if (!status) {
3128                 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3129                                                   FW_NVM_DATA_OFFSET);
3130         }
3131
3132         hw->mac.ops.release_swfw_sync(hw, mask);
3133         return status;
3134 }
3135
3136 /**
3137  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3138  *  @hw: pointer to hardware structure
3139  *  @offset: offset of  word in the EEPROM to read
3140  *  @words: number of words
3141  *  @data: word(s) read from the EEPROM
3142  *
3143  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
3144  **/
3145 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3146                                      u16 offset, u16 words, u16 *data)
3147 {
3148         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3149         struct ixgbe_hic_read_shadow_ram buffer;
3150         u32 current_word = 0;
3151         u16 words_to_read;
3152         s32 status;
3153         u32 i;
3154
3155         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3156
3157         /* Take semaphore for the entire operation. */
3158         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3159         if (status) {
3160                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3161                 return status;
3162         }
3163
3164         while (words) {
3165                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3166                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3167                 else
3168                         words_to_read = words;
3169
3170                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3171                 buffer.hdr.req.buf_lenh = 0;
3172                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3173                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3174
3175                 /* convert offset from words to bytes */
3176                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3177                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3178                 buffer.pad2 = 0;
3179                 buffer.pad3 = 0;
3180
3181                 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3182                                             IXGBE_HI_COMMAND_TIMEOUT);
3183
3184                 if (status) {
3185                         DEBUGOUT("Host interface command failed\n");
3186                         goto out;
3187                 }
3188
3189                 for (i = 0; i < words_to_read; i++) {
3190                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3191                                   2 * i;
3192                         u32 value = IXGBE_READ_REG(hw, reg);
3193
3194                         data[current_word] = (u16)(value & 0xffff);
3195                         current_word++;
3196                         i++;
3197                         if (i < words_to_read) {
3198                                 value >>= 16;
3199                                 data[current_word] = (u16)(value & 0xffff);
3200                                 current_word++;
3201                         }
3202                 }
3203                 words -= words_to_read;
3204         }
3205
3206 out:
3207         hw->mac.ops.release_swfw_sync(hw, mask);
3208         return status;
3209 }
3210
3211 /**
3212  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3213  *  @hw: pointer to hardware structure
3214  *  @offset: offset of  word in the EEPROM to write
3215  *  @data: word write to the EEPROM
3216  *
3217  *  Write a 16 bit word to the EEPROM using the hostif.
3218  **/
3219 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3220                                     u16 data)
3221 {
3222         s32 status;
3223         struct ixgbe_hic_write_shadow_ram buffer;
3224
3225         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3226
3227         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3228         buffer.hdr.req.buf_lenh = 0;
3229         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3230         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3231
3232          /* one word */
3233         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3234         buffer.data = data;
3235         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3236
3237         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3238                                               sizeof(buffer),
3239                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3240
3241         return status;
3242 }
3243
3244 /**
3245  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3246  *  @hw: pointer to hardware structure
3247  *  @offset: offset of  word in the EEPROM to write
3248  *  @data: word write to the EEPROM
3249  *
3250  *  Write a 16 bit word to the EEPROM using the hostif.
3251  **/
3252 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3253                                u16 data)
3254 {
3255         s32 status = IXGBE_SUCCESS;
3256
3257         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3258
3259         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3260             IXGBE_SUCCESS) {
3261                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3262                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3263         } else {
3264                 DEBUGOUT("write ee hostif failed to get semaphore");
3265                 status = IXGBE_ERR_SWFW_SYNC;
3266         }
3267
3268         return status;
3269 }
3270
3271 /**
3272  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3273  *  @hw: pointer to hardware structure
3274  *  @offset: offset of  word in the EEPROM to write
3275  *  @words: number of words
3276  *  @data: word(s) write to the EEPROM
3277  *
3278  *  Write a 16 bit word(s) to the EEPROM using the hostif.
3279  **/
3280 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3281                                       u16 offset, u16 words, u16 *data)
3282 {
3283         s32 status = IXGBE_SUCCESS;
3284         u32 i = 0;
3285
3286         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3287
3288         /* Take semaphore for the entire operation. */
3289         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3290         if (status != IXGBE_SUCCESS) {
3291                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3292                 goto out;
3293         }
3294
3295         for (i = 0; i < words; i++) {
3296                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3297                                                          data[i]);
3298
3299                 if (status != IXGBE_SUCCESS) {
3300                         DEBUGOUT("Eeprom buffered write failed\n");
3301                         break;
3302                 }
3303         }
3304
3305         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3306 out:
3307
3308         return status;
3309 }
3310
3311 /**
3312  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3313  * @hw: pointer to hardware structure
3314  * @ptr: pointer offset in eeprom
3315  * @size: size of section pointed by ptr, if 0 first word will be used as size
3316  * @csum: address of checksum to update
3317  * @buffer: pointer to buffer containing calculated checksum
3318  * @buffer_size: size of buffer
3319  *
3320  * Returns error status for any failure
3321  */
3322 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3323                                    u16 size, u16 *csum, u16 *buffer,
3324                                    u32 buffer_size)
3325 {
3326         u16 buf[256];
3327         s32 status;
3328         u16 length, bufsz, i, start;
3329         u16 *local_buffer;
3330
3331         bufsz = sizeof(buf) / sizeof(buf[0]);
3332
3333         /* Read a chunk at the pointer location */
3334         if (!buffer) {
3335                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3336                 if (status) {
3337                         DEBUGOUT("Failed to read EEPROM image\n");
3338                         return status;
3339                 }
3340                 local_buffer = buf;
3341         } else {
3342                 if (buffer_size < ptr)
3343                         return  IXGBE_ERR_PARAM;
3344                 local_buffer = &buffer[ptr];
3345         }
3346
3347         if (size) {
3348                 start = 0;
3349                 length = size;
3350         } else {
3351                 start = 1;
3352                 length = local_buffer[0];
3353
3354                 /* Skip pointer section if length is invalid. */
3355                 if (length == 0xFFFF || length == 0 ||
3356                     (ptr + length) >= hw->eeprom.word_size)
3357                         return IXGBE_SUCCESS;
3358         }
3359
3360         if (buffer && ((u32)start + (u32)length > buffer_size))
3361                 return IXGBE_ERR_PARAM;
3362
3363         for (i = start; length; i++, length--) {
3364                 if (i == bufsz && !buffer) {
3365                         ptr += bufsz;
3366                         i = 0;
3367                         if (length < bufsz)
3368                                 bufsz = length;
3369
3370                         /* Read a chunk at the pointer location */
3371                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3372                                                                   bufsz, buf);
3373                         if (status) {
3374                                 DEBUGOUT("Failed to read EEPROM image\n");
3375                                 return status;
3376                         }
3377                 }
3378                 *csum += local_buffer[i];
3379         }
3380         return IXGBE_SUCCESS;
3381 }
3382
3383 /**
3384  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3385  *  @hw: pointer to hardware structure
3386  *  @buffer: pointer to buffer containing calculated checksum
3387  *  @buffer_size: size of buffer
3388  *
3389  *  Returns a negative error code on error, or the 16-bit checksum
3390  **/
3391 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3392 {
3393         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3394         u16 *local_buffer;
3395         s32 status;
3396         u16 checksum = 0;
3397         u16 pointer, i, size;
3398
3399         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3400
3401         hw->eeprom.ops.init_params(hw);
3402
3403         if (!buffer) {
3404                 /* Read pointer area */
3405                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3406                                                      IXGBE_EEPROM_LAST_WORD + 1,
3407                                                      eeprom_ptrs);
3408                 if (status) {
3409                         DEBUGOUT("Failed to read EEPROM image\n");
3410                         return status;
3411                 }
3412                 local_buffer = eeprom_ptrs;
3413         } else {
3414                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3415                         return IXGBE_ERR_PARAM;
3416                 local_buffer = buffer;
3417         }
3418
3419         /*
3420          * For X550 hardware include 0x0-0x41 in the checksum, skip the
3421          * checksum word itself
3422          */
3423         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3424                 if (i != IXGBE_EEPROM_CHECKSUM)
3425                         checksum += local_buffer[i];
3426
3427         /*
3428          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
3429          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3430          */
3431         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3432                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3433                         continue;
3434
3435                 pointer = local_buffer[i];
3436
3437                 /* Skip pointer section if the pointer is invalid. */
3438                 if (pointer == 0xFFFF || pointer == 0 ||
3439                     pointer >= hw->eeprom.word_size)
3440                         continue;
3441
3442                 switch (i) {
3443                 case IXGBE_PCIE_GENERAL_PTR:
3444                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3445                         break;
3446                 case IXGBE_PCIE_CONFIG0_PTR:
3447                 case IXGBE_PCIE_CONFIG1_PTR:
3448                         size = IXGBE_PCIE_CONFIG_SIZE;
3449                         break;
3450                 default:
3451                         size = 0;
3452                         break;
3453                 }
3454
3455                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3456                                                 buffer, buffer_size);
3457                 if (status)
3458                         return status;
3459         }
3460
3461         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3462
3463         return (s32)checksum;
3464 }
3465
3466 /**
3467  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3468  *  @hw: pointer to hardware structure
3469  *
3470  *  Returns a negative error code on error, or the 16-bit checksum
3471  **/
3472 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3473 {
3474         return ixgbe_calc_checksum_X550(hw, NULL, 0);
3475 }
3476
3477 /**
3478  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3479  *  @hw: pointer to hardware structure
3480  *  @checksum_val: calculated checksum
3481  *
3482  *  Performs checksum calculation and validates the EEPROM checksum.  If the
3483  *  caller does not need checksum_val, the value can be NULL.
3484  **/
3485 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3486 {
3487         s32 status;
3488         u16 checksum;
3489         u16 read_checksum = 0;
3490
3491         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3492
3493         /* Read the first word from the EEPROM. If this times out or fails, do
3494          * not continue or we could be in for a very long wait while every
3495          * EEPROM read fails
3496          */
3497         status = hw->eeprom.ops.read(hw, 0, &checksum);
3498         if (status) {
3499                 DEBUGOUT("EEPROM read failed\n");
3500                 return status;
3501         }
3502
3503         status = hw->eeprom.ops.calc_checksum(hw);
3504         if (status < 0)
3505                 return status;
3506
3507         checksum = (u16)(status & 0xffff);
3508
3509         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3510                                            &read_checksum);
3511         if (status)
3512                 return status;
3513
3514         /* Verify read checksum from EEPROM is the same as
3515          * calculated checksum
3516          */
3517         if (read_checksum != checksum) {
3518                 status = IXGBE_ERR_EEPROM_CHECKSUM;
3519                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3520                              "Invalid EEPROM checksum");
3521         }
3522
3523         /* If the user cares, return the calculated checksum */
3524         if (checksum_val)
3525                 *checksum_val = checksum;
3526
3527         return status;
3528 }
3529
3530 /**
3531  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3532  * @hw: pointer to hardware structure
3533  *
3534  * After writing EEPROM to shadow RAM using EEWR register, software calculates
3535  * checksum and updates the EEPROM and instructs the hardware to update
3536  * the flash.
3537  **/
3538 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3539 {
3540         s32 status;
3541         u16 checksum = 0;
3542
3543         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3544
3545         /* Read the first word from the EEPROM. If this times out or fails, do
3546          * not continue or we could be in for a very long wait while every
3547          * EEPROM read fails
3548          */
3549         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3550         if (status) {
3551                 DEBUGOUT("EEPROM read failed\n");
3552                 return status;
3553         }
3554
3555         status = ixgbe_calc_eeprom_checksum_X550(hw);
3556         if (status < 0)
3557                 return status;
3558
3559         checksum = (u16)(status & 0xffff);
3560
3561         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3562                                             checksum);
3563         if (status)
3564                 return status;
3565
3566         status = ixgbe_update_flash_X550(hw);
3567
3568         return status;
3569 }
3570
3571 /**
3572  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3573  *  @hw: pointer to hardware structure
3574  *
3575  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3576  **/
3577 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3578 {
3579         s32 status = IXGBE_SUCCESS;
3580         union ixgbe_hic_hdr2 buffer;
3581
3582         DEBUGFUNC("ixgbe_update_flash_X550");
3583
3584         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3585         buffer.req.buf_lenh = 0;
3586         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3587         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3588
3589         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3590                                               sizeof(buffer),
3591                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3592
3593         return status;
3594 }
3595
3596 /**
3597  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3598  *  @hw: pointer to hardware structure
3599  *
3600  *  Determines physical layer capabilities of the current configuration.
3601  **/
3602 u64 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3603 {
3604         u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3605         u16 ext_ability = 0;
3606
3607         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3608
3609         hw->phy.ops.identify(hw);
3610
3611         switch (hw->phy.type) {
3612         case ixgbe_phy_x550em_kr:
3613                 if (hw->mac.type == ixgbe_mac_X550EM_a) {
3614                         if (hw->phy.nw_mng_if_sel &
3615                             IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
3616                                 physical_layer =
3617                                         IXGBE_PHYSICAL_LAYER_2500BASE_KX;
3618                                 break;
3619                         } else if (hw->device_id ==
3620                                    IXGBE_DEV_ID_X550EM_A_KR_L) {
3621                                 physical_layer =
3622                                         IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3623                                 break;
3624                         }
3625                 }
3626                 /* fall through */
3627         case ixgbe_phy_x550em_xfi:
3628                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3629                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3630                 break;
3631         case ixgbe_phy_x550em_kx4:
3632                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3633                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3634                 break;
3635         case ixgbe_phy_x550em_ext_t:
3636                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3637                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3638                                      &ext_ability);
3639                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3640                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3641                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3642                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3643                 break;
3644         case ixgbe_phy_fw:
3645                 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_1GB_FULL)
3646                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3647                 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_100_FULL)
3648                         physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
3649                 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_10_FULL)
3650                         physical_layer |= IXGBE_PHYSICAL_LAYER_10BASE_T;
3651                 break;
3652         case ixgbe_phy_sgmii:
3653 #ifdef PREBOOT_SUPPORT
3654                 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
3655                                  IXGBE_PHYSICAL_LAYER_100BASE_TX |
3656                                  IXGBE_PHYSICAL_LAYER_10BASE_T;
3657 #else
3658                 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3659 #endif /* PREBOOT_SUPPORT */
3660                 break;
3661         case ixgbe_phy_ext_1g_t:
3662                 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3663                 break;
3664         default:
3665                 break;
3666         }
3667
3668         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3669                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3670
3671         return physical_layer;
3672 }
3673
3674 /**
3675  * ixgbe_get_bus_info_x550em - Set PCI bus info
3676  * @hw: pointer to hardware structure
3677  *
3678  * Sets bus link width and speed to unknown because X550em is
3679  * not a PCI device.
3680  **/
3681 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3682 {
3683
3684         DEBUGFUNC("ixgbe_get_bus_info_x550em");
3685
3686         hw->bus.width = ixgbe_bus_width_unknown;
3687         hw->bus.speed = ixgbe_bus_speed_unknown;
3688
3689         hw->mac.ops.set_lan_id(hw);
3690
3691         return IXGBE_SUCCESS;
3692 }
3693
3694 /**
3695  * ixgbe_disable_rx_x550 - Disable RX unit
3696  * @hw: pointer to hardware structure
3697  *
3698  * Enables the Rx DMA unit for x550
3699  **/
3700 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3701 {
3702         u32 rxctrl, pfdtxgswc;
3703         s32 status;
3704         struct ixgbe_hic_disable_rxen fw_cmd;
3705
3706         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3707
3708         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3709         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3710                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3711                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3712                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3713                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3714                         hw->mac.set_lben = true;
3715                 } else {
3716                         hw->mac.set_lben = false;
3717                 }
3718
3719                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3720                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3721                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3722                 fw_cmd.port_number = (u8)hw->bus.lan_id;
3723
3724                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3725                                         sizeof(struct ixgbe_hic_disable_rxen),
3726                                         IXGBE_HI_COMMAND_TIMEOUT, true);
3727
3728                 /* If we fail - disable RX using register write */
3729                 if (status) {
3730                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3731                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3732                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3733                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3734                         }
3735                 }
3736         }
3737 }
3738
3739 /**
3740  * ixgbe_enter_lplu_x550em - Transition to low power states
3741  *  @hw: pointer to hardware structure
3742  *
3743  * Configures Low Power Link Up on transition to low power states
3744  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3745  * X557 PHY immediately prior to entering LPLU.
3746  **/
3747 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3748 {
3749         u16 an_10g_cntl_reg, autoneg_reg, speed;
3750         s32 status;
3751         ixgbe_link_speed lcd_speed;
3752         u32 save_autoneg;
3753         bool link_up;
3754
3755         /* SW LPLU not required on later HW revisions. */
3756         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3757             (IXGBE_FUSES0_REV_MASK &
3758              IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3759                 return IXGBE_SUCCESS;
3760
3761         /* If blocked by MNG FW, then don't restart AN */
3762         if (ixgbe_check_reset_blocked(hw))
3763                 return IXGBE_SUCCESS;
3764
3765         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3766         if (status != IXGBE_SUCCESS)
3767                 return status;
3768
3769         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3770
3771         if (status != IXGBE_SUCCESS)
3772                 return status;
3773
3774         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3775          * disabled, then force link down by entering low power mode.
3776          */
3777         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3778             !(hw->wol_enabled || ixgbe_mng_present(hw)))
3779                 return ixgbe_set_copper_phy_power(hw, FALSE);
3780
3781         /* Determine LCD */
3782         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3783
3784         if (status != IXGBE_SUCCESS)
3785                 return status;
3786
3787         /* If no valid LCD link speed, then force link down and exit. */
3788         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3789                 return ixgbe_set_copper_phy_power(hw, FALSE);
3790
3791         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3792                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3793                                       &speed);
3794
3795         if (status != IXGBE_SUCCESS)
3796                 return status;
3797
3798         /* If no link now, speed is invalid so take link down */
3799         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3800         if (status != IXGBE_SUCCESS)
3801                 return ixgbe_set_copper_phy_power(hw, false);
3802
3803         /* clear everything but the speed bits */
3804         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3805
3806         /* If current speed is already LCD, then exit. */
3807         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3808              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3809             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3810              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3811                 return status;
3812
3813         /* Clear AN completed indication */
3814         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3815                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3816                                       &autoneg_reg);
3817
3818         if (status != IXGBE_SUCCESS)
3819                 return status;
3820
3821         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3822                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3823                              &an_10g_cntl_reg);
3824
3825         if (status != IXGBE_SUCCESS)
3826                 return status;
3827
3828         status = hw->phy.ops.read_reg(hw,
3829                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3830                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3831                              &autoneg_reg);
3832
3833         if (status != IXGBE_SUCCESS)
3834                 return status;
3835
3836         save_autoneg = hw->phy.autoneg_advertised;
3837
3838         /* Setup link at least common link speed */
3839         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3840
3841         /* restore autoneg from before setting lplu speed */
3842         hw->phy.autoneg_advertised = save_autoneg;
3843
3844         return status;
3845 }
3846
3847 /**
3848  * ixgbe_get_lcd_x550em - Determine lowest common denominator
3849  *  @hw: pointer to hardware structure
3850  *  @lcd_speed: pointer to lowest common link speed
3851  *
3852  * Determine lowest common link speed with link partner.
3853  **/
3854 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3855 {
3856         u16 an_lp_status;
3857         s32 status;
3858         u16 word = hw->eeprom.ctrl_word_3;
3859
3860         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3861
3862         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3863                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3864                                       &an_lp_status);
3865
3866         if (status != IXGBE_SUCCESS)
3867                 return status;
3868
3869         /* If link partner advertised 1G, return 1G */
3870         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3871                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3872                 return status;
3873         }
3874
3875         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3876         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3877             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3878                 return status;
3879
3880         /* Link partner not capable of lower speeds, return 10G */
3881         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3882         return status;
3883 }
3884
3885 /**
3886  *  ixgbe_setup_fc_X550em - Set up flow control
3887  *  @hw: pointer to hardware structure
3888  *
3889  *  Called at init time to set up flow control.
3890  **/
3891 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3892 {
3893         s32 ret_val = IXGBE_SUCCESS;
3894         u32 pause, asm_dir, reg_val;
3895
3896         DEBUGFUNC("ixgbe_setup_fc_X550em");
3897
3898         /* Validate the requested mode */
3899         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3900                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3901                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3902                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3903                 goto out;
3904         }
3905
3906         /* 10gig parts do not have a word in the EEPROM to determine the
3907          * default flow control setting, so we explicitly set it to full.
3908          */
3909         if (hw->fc.requested_mode == ixgbe_fc_default)
3910                 hw->fc.requested_mode = ixgbe_fc_full;
3911
3912         /* Determine PAUSE and ASM_DIR bits. */
3913         switch (hw->fc.requested_mode) {
3914         case ixgbe_fc_none:
3915                 pause = 0;
3916                 asm_dir = 0;
3917                 break;
3918         case ixgbe_fc_tx_pause:
3919                 pause = 0;
3920                 asm_dir = 1;
3921                 break;
3922         case ixgbe_fc_rx_pause:
3923                 /* Rx Flow control is enabled and Tx Flow control is
3924                  * disabled by software override. Since there really
3925                  * isn't a way to advertise that we are capable of RX
3926                  * Pause ONLY, we will advertise that we support both
3927                  * symmetric and asymmetric Rx PAUSE, as such we fall
3928                  * through to the fc_full statement.  Later, we will
3929                  * disable the adapter's ability to send PAUSE frames.
3930                  */
3931         case ixgbe_fc_full:
3932                 pause = 1;
3933                 asm_dir = 1;
3934                 break;
3935         default:
3936                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3937                         "Flow control param set incorrectly\n");
3938                 ret_val = IXGBE_ERR_CONFIG;
3939                 goto out;
3940         }
3941
3942         switch (hw->device_id) {
3943         case IXGBE_DEV_ID_X550EM_X_KR:
3944         case IXGBE_DEV_ID_X550EM_A_KR:
3945         case IXGBE_DEV_ID_X550EM_A_KR_L:
3946                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
3947                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3948                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3949                 if (ret_val != IXGBE_SUCCESS)
3950                         goto out;
3951                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3952                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3953                 if (pause)
3954                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3955                 if (asm_dir)
3956                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3957                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
3958                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3959                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3960
3961                 /* This device does not fully support AN. */
3962                 hw->fc.disable_fc_autoneg = true;
3963                 break;
3964         case IXGBE_DEV_ID_X550EM_X_XFI:
3965                 hw->fc.disable_fc_autoneg = true;
3966                 break;
3967         default:
3968                 break;
3969         }
3970
3971 out:
3972         return ret_val;
3973 }
3974
3975 /**
3976  *  ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
3977  *  @hw: pointer to hardware structure
3978  *
3979  *  Enable flow control according to IEEE clause 37.
3980  **/
3981 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
3982 {
3983         u32 link_s1, lp_an_page_low, an_cntl_1;
3984         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
3985         ixgbe_link_speed speed;
3986         bool link_up;
3987
3988         /* AN should have completed when the cable was plugged in.
3989          * Look for reasons to bail out.  Bail out if:
3990          * - FC autoneg is disabled, or if
3991          * - link is not up.
3992          */
3993         if (hw->fc.disable_fc_autoneg) {
3994                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3995                              "Flow control autoneg is disabled");
3996                 goto out;
3997         }
3998
3999         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4000         if (!link_up) {
4001                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4002                 goto out;
4003         }
4004
4005         /* Check at auto-negotiation has completed */
4006         status = hw->mac.ops.read_iosf_sb_reg(hw,
4007                                         IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4008                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4009
4010         if (status != IXGBE_SUCCESS ||
4011             (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4012                 DEBUGOUT("Auto-Negotiation did not complete\n");
4013                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4014                 goto out;
4015         }
4016
4017         /* Read the 10g AN autoc and LP ability registers and resolve
4018          * local flow control settings accordingly
4019          */
4020         status = hw->mac.ops.read_iosf_sb_reg(hw,
4021                                 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4022                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
4023
4024         if (status != IXGBE_SUCCESS) {
4025                 DEBUGOUT("Auto-Negotiation did not complete\n");
4026                 goto out;
4027         }
4028
4029         status = hw->mac.ops.read_iosf_sb_reg(hw,
4030                                 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
4031                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
4032
4033         if (status != IXGBE_SUCCESS) {
4034                 DEBUGOUT("Auto-Negotiation did not complete\n");
4035                 goto out;
4036         }
4037
4038         status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
4039                                     IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
4040                                     IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
4041                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
4042                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
4043
4044 out:
4045         if (status == IXGBE_SUCCESS) {
4046                 hw->fc.fc_was_autonegged = true;
4047         } else {
4048                 hw->fc.fc_was_autonegged = false;
4049                 hw->fc.current_mode = hw->fc.requested_mode;
4050         }
4051 }
4052
4053 /**
4054  *  ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
4055  *  @hw: pointer to hardware structure
4056  *
4057  **/
4058 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
4059 {
4060         hw->fc.fc_was_autonegged = false;
4061         hw->fc.current_mode = hw->fc.requested_mode;
4062 }
4063
4064 /**
4065  *  ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
4066  *  @hw: pointer to hardware structure
4067  *
4068  *  Enable flow control according to IEEE clause 37.
4069  **/
4070 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
4071 {
4072         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4073         u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
4074         ixgbe_link_speed speed;
4075         bool link_up;
4076
4077         /* AN should have completed when the cable was plugged in.
4078          * Look for reasons to bail out.  Bail out if:
4079          * - FC autoneg is disabled, or if
4080          * - link is not up.
4081          */
4082         if (hw->fc.disable_fc_autoneg) {
4083                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4084                              "Flow control autoneg is disabled");
4085                 goto out;
4086         }
4087
4088         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4089         if (!link_up) {
4090                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4091                 goto out;
4092         }
4093
4094         /* Check if auto-negotiation has completed */
4095         status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info);
4096         if (status != IXGBE_SUCCESS ||
4097             !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) {
4098                 DEBUGOUT("Auto-Negotiation did not complete\n");
4099                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4100                 goto out;
4101         }
4102
4103         /* Negotiate the flow control */
4104         status = ixgbe_negotiate_fc(hw, info[0], info[0],
4105                                     FW_PHY_ACT_GET_LINK_INFO_FC_RX,
4106                                     FW_PHY_ACT_GET_LINK_INFO_FC_TX,
4107                                     FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX,
4108                                     FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX);
4109
4110 out:
4111         if (status == IXGBE_SUCCESS) {
4112                 hw->fc.fc_was_autonegged = true;
4113         } else {
4114                 hw->fc.fc_was_autonegged = false;
4115                 hw->fc.current_mode = hw->fc.requested_mode;
4116         }
4117 }
4118
4119 /**
4120  *  ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4121  *  @hw: pointer to hardware structure
4122  *
4123  *  Called at init time to set up flow control.
4124  **/
4125 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4126 {
4127         s32 status = IXGBE_SUCCESS;
4128         u32 an_cntl = 0;
4129
4130         DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4131
4132         /* Validate the requested mode */
4133         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4134                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4135                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4136                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4137         }
4138
4139         if (hw->fc.requested_mode == ixgbe_fc_default)
4140                 hw->fc.requested_mode = ixgbe_fc_full;
4141
4142         /* Set up the 1G and 10G flow control advertisement registers so the
4143          * HW will be able to do FC autoneg once the cable is plugged in.  If
4144          * we link at 10G, the 1G advertisement is harmless and vice versa.
4145          */
4146         status = hw->mac.ops.read_iosf_sb_reg(hw,
4147                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4148                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4149
4150         if (status != IXGBE_SUCCESS) {
4151                 DEBUGOUT("Auto-Negotiation did not complete\n");
4152                 return status;
4153         }
4154
4155         /* The possible values of fc.requested_mode are:
4156          * 0: Flow control is completely disabled
4157          * 1: Rx flow control is enabled (we can receive pause frames,
4158          *    but not send pause frames).
4159          * 2: Tx flow control is enabled (we can send pause frames but
4160          *    we do not support receiving pause frames).
4161          * 3: Both Rx and Tx flow control (symmetric) are enabled.
4162          * other: Invalid.
4163          */
4164         switch (hw->fc.requested_mode) {
4165         case ixgbe_fc_none:
4166                 /* Flow control completely disabled by software override. */
4167                 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4168                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4169                 break;
4170         case ixgbe_fc_tx_pause:
4171                 /* Tx Flow control is enabled, and Rx Flow control is
4172                  * disabled by software override.
4173                  */
4174                 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4175                 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4176                 break;
4177         case ixgbe_fc_rx_pause:
4178                 /* Rx Flow control is enabled and Tx Flow control is
4179                  * disabled by software override. Since there really
4180                  * isn't a way to advertise that we are capable of RX
4181                  * Pause ONLY, we will advertise that we support both
4182                  * symmetric and asymmetric Rx PAUSE, as such we fall
4183                  * through to the fc_full statement.  Later, we will
4184                  * disable the adapter's ability to send PAUSE frames.
4185                  */
4186         case ixgbe_fc_full:
4187                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4188                 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4189                            IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4190                 break;
4191         default:
4192                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4193                               "Flow control param set incorrectly\n");
4194                 return IXGBE_ERR_CONFIG;
4195         }
4196
4197         status = hw->mac.ops.write_iosf_sb_reg(hw,
4198                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4199                                         IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4200
4201         /* Restart auto-negotiation. */
4202         status = ixgbe_restart_an_internal_phy_x550em(hw);
4203
4204         return status;
4205 }
4206
4207 /**
4208  * ixgbe_set_mux - Set mux for port 1 access with CS4227
4209  * @hw: pointer to hardware structure
4210  * @state: set mux if 1, clear if 0
4211  */
4212 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4213 {
4214         u32 esdp;
4215
4216         if (!hw->bus.lan_id)
4217                 return;
4218         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4219         if (state)
4220                 esdp |= IXGBE_ESDP_SDP1;
4221         else
4222                 esdp &= ~IXGBE_ESDP_SDP1;
4223         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4224         IXGBE_WRITE_FLUSH(hw);
4225 }
4226
4227 /**
4228  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4229  *  @hw: pointer to hardware structure
4230  *  @mask: Mask to specify which semaphore to acquire
4231  *
4232  *  Acquires the SWFW semaphore and sets the I2C MUX
4233  **/
4234 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4235 {
4236         s32 status;
4237
4238         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4239
4240         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4241         if (status)
4242                 return status;
4243
4244         if (mask & IXGBE_GSSR_I2C_MASK)
4245                 ixgbe_set_mux(hw, 1);
4246
4247         return IXGBE_SUCCESS;
4248 }
4249
4250 /**
4251  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4252  *  @hw: pointer to hardware structure
4253  *  @mask: Mask to specify which semaphore to release
4254  *
4255  *  Releases the SWFW semaphore and sets the I2C MUX
4256  **/
4257 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4258 {
4259         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4260
4261         if (mask & IXGBE_GSSR_I2C_MASK)
4262                 ixgbe_set_mux(hw, 0);
4263
4264         ixgbe_release_swfw_sync_X540(hw, mask);
4265 }
4266
4267 /**
4268  *  ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4269  *  @hw: pointer to hardware structure
4270  *  @mask: Mask to specify which semaphore to acquire
4271  *
4272  *  Acquires the SWFW semaphore and get the shared phy token as needed
4273  */
4274 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4275 {
4276         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4277         int retries = FW_PHY_TOKEN_RETRIES;
4278         s32 status = IXGBE_SUCCESS;
4279
4280         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4281
4282         while (--retries) {
4283                 status = IXGBE_SUCCESS;
4284                 if (hmask)
4285                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4286                 if (status) {
4287                         DEBUGOUT1("Could not acquire SWFW semaphore, Status = %d\n",
4288                                   status);
4289                         return status;
4290                 }
4291                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4292                         return IXGBE_SUCCESS;
4293
4294                 status = ixgbe_get_phy_token(hw);
4295                 if (status == IXGBE_ERR_TOKEN_RETRY)
4296                         DEBUGOUT1("Could not acquire PHY token, Status = %d\n",
4297                                   status);
4298
4299                 if (status == IXGBE_SUCCESS)
4300                         return IXGBE_SUCCESS;
4301
4302                 if (hmask)
4303                         ixgbe_release_swfw_sync_X540(hw, hmask);
4304
4305                 if (status != IXGBE_ERR_TOKEN_RETRY) {
4306                         DEBUGOUT1("Unable to retry acquiring the PHY token, Status = %d\n",
4307                                   status);
4308                         return status;
4309                 }
4310         }
4311
4312         DEBUGOUT1("Semaphore acquisition retries failed!: PHY ID = 0x%08X\n",
4313                   hw->phy.id);
4314         return status;
4315 }
4316
4317 /**
4318  *  ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4319  *  @hw: pointer to hardware structure
4320  *  @mask: Mask to specify which semaphore to release
4321  *
4322  *  Releases the SWFW semaphore and puts the shared phy token as needed
4323  */
4324 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4325 {
4326         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4327
4328         DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4329
4330         if (mask & IXGBE_GSSR_TOKEN_SM)
4331                 ixgbe_put_phy_token(hw);
4332
4333         if (hmask)
4334                 ixgbe_release_swfw_sync_X540(hw, hmask);
4335 }
4336
4337 /**
4338  *  ixgbe_read_phy_reg_x550a  - Reads specified PHY register
4339  *  @hw: pointer to hardware structure
4340  *  @reg_addr: 32 bit address of PHY register to read
4341  *  @device_type: 5 bit device type
4342  *  @phy_data: Pointer to read data from PHY register
4343  *
4344  *  Reads a value from a specified PHY register using the SWFW lock and PHY
4345  *  Token. The PHY Token is needed since the MDIO is shared between to MAC
4346  *  instances.
4347  **/
4348 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4349                                u32 device_type, u16 *phy_data)
4350 {
4351         s32 status;
4352         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4353
4354         DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4355
4356         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4357                 return IXGBE_ERR_SWFW_SYNC;
4358
4359         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4360
4361         hw->mac.ops.release_swfw_sync(hw, mask);
4362
4363         return status;
4364 }
4365
4366 /**
4367  *  ixgbe_write_phy_reg_x550a - Writes specified PHY register
4368  *  @hw: pointer to hardware structure
4369  *  @reg_addr: 32 bit PHY register to write
4370  *  @device_type: 5 bit device type
4371  *  @phy_data: Data to write to the PHY register
4372  *
4373  *  Writes a value to specified PHY register using the SWFW lock and PHY Token.
4374  *  The PHY Token is needed since the MDIO is shared between to MAC instances.
4375  **/
4376 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4377                                 u32 device_type, u16 phy_data)
4378 {
4379         s32 status;
4380         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4381
4382         DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4383
4384         if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4385                 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
4386                                                  phy_data);
4387                 hw->mac.ops.release_swfw_sync(hw, mask);
4388         } else {
4389                 status = IXGBE_ERR_SWFW_SYNC;
4390         }
4391
4392         return status;
4393 }
4394
4395 /**
4396  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4397  * @hw: pointer to hardware structure
4398  *
4399  * Handle external Base T PHY interrupt. If high temperature
4400  * failure alarm then return error, else if link status change
4401  * then setup internal/external PHY link
4402  *
4403  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4404  * failure alarm, else return PHY access status.
4405  */
4406 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4407 {
4408         bool lsc;
4409         u32 status;
4410
4411         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4412
4413         if (status != IXGBE_SUCCESS)
4414                 return status;
4415
4416         if (lsc)
4417                 return ixgbe_setup_internal_phy(hw);
4418
4419         return IXGBE_SUCCESS;
4420 }
4421
4422 /**
4423  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4424  * @hw: pointer to hardware structure
4425  * @speed: new link speed
4426  * @autoneg_wait_to_complete: true when waiting for completion is needed
4427  *
4428  * Setup internal/external PHY link speed based on link speed, then set
4429  * external PHY auto advertised link speed.
4430  *
4431  * Returns error status for any failure
4432  **/
4433 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4434                                   ixgbe_link_speed speed,
4435                                   bool autoneg_wait_to_complete)
4436 {
4437         s32 status;
4438         ixgbe_link_speed force_speed;
4439
4440         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4441
4442         /* Setup internal/external PHY link speed to iXFI (10G), unless
4443          * only 1G is auto advertised then setup KX link.
4444          */
4445         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4446                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4447         else
4448                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4449
4450         /* If X552 and internal link mode is XFI, then setup XFI internal link.
4451          */
4452         if (hw->mac.type == ixgbe_mac_X550EM_x &&
4453             !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4454                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4455
4456                 if (status != IXGBE_SUCCESS)
4457                         return status;
4458         }
4459
4460         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4461 }
4462
4463 /**
4464  * ixgbe_check_link_t_X550em - Determine link and speed status
4465  * @hw: pointer to hardware structure
4466  * @speed: pointer to link speed
4467  * @link_up: true when link is up
4468  * @link_up_wait_to_complete: bool used to wait for link up or not
4469  *
4470  * Check that both the MAC and X557 external PHY have link.
4471  **/
4472 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4473                               bool *link_up, bool link_up_wait_to_complete)
4474 {
4475         u32 status;
4476         u16 i, autoneg_status = 0;
4477
4478         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4479                 return IXGBE_ERR_CONFIG;
4480
4481         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4482                                               link_up_wait_to_complete);
4483
4484         /* If check link fails or MAC link is not up, then return */
4485         if (status != IXGBE_SUCCESS || !(*link_up))
4486                 return status;
4487
4488         /* MAC link is up, so check external PHY link.
4489          * X557 PHY. Link status is latching low, and can only be used to detect
4490          * link drop, and not the current status of the link without performing
4491          * back-to-back reads.
4492          */
4493         for (i = 0; i < 2; i++) {
4494                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4495                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4496                                               &autoneg_status);
4497
4498                 if (status != IXGBE_SUCCESS)
4499                         return status;
4500         }
4501
4502         /* If external PHY link is not up, then indicate link not up */
4503         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4504                 *link_up = false;
4505
4506         return IXGBE_SUCCESS;
4507 }
4508
4509 /**
4510  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4511  *  @hw: pointer to hardware structure
4512  **/
4513 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4514 {
4515         s32 status;
4516
4517         status = ixgbe_reset_phy_generic(hw);
4518
4519         if (status != IXGBE_SUCCESS)
4520                 return status;
4521
4522         /* Configure Link Status Alarm and Temperature Threshold interrupts */
4523         return ixgbe_enable_lasi_ext_t_x550em(hw);
4524 }
4525
4526 /**
4527  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4528  *  @hw: pointer to hardware structure
4529  *  @led_idx: led number to turn on
4530  **/
4531 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4532 {
4533         u16 phy_data;
4534
4535         DEBUGFUNC("ixgbe_led_on_t_X550em");
4536
4537         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4538                 return IXGBE_ERR_PARAM;
4539
4540         /* To turn on the LED, set mode to ON. */
4541         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4542                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4543         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4544         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4545                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4546
4547         /* Some designs have the LEDs wired to the MAC */
4548         return ixgbe_led_on_generic(hw, led_idx);
4549 }
4550
4551 /**
4552  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4553  *  @hw: pointer to hardware structure
4554  *  @led_idx: led number to turn off
4555  **/
4556 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4557 {
4558         u16 phy_data;
4559
4560         DEBUGFUNC("ixgbe_led_off_t_X550em");
4561
4562         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4563                 return IXGBE_ERR_PARAM;
4564
4565         /* To turn on the LED, set mode to ON. */
4566         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4567                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4568         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4569         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4570                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4571
4572         /* Some designs have the LEDs wired to the MAC */
4573         return ixgbe_led_off_generic(hw, led_idx);
4574 }
4575
4576 /**
4577  *  ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware
4578  *  @hw: pointer to the HW structure
4579  *  @maj: driver version major number
4580  *  @min: driver version minor number
4581  *  @build: driver version build number
4582  *  @sub: driver version sub build number
4583  *  @len: length of driver_ver string
4584  *  @driver_ver: driver string
4585  *
4586  *  Sends driver version number to firmware through the manageability
4587  *  block.  On success return IXGBE_SUCCESS
4588  *  else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4589  *  semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4590  **/
4591 s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,
4592                               u8 build, u8 sub, u16 len, const char *driver_ver)
4593 {
4594         struct ixgbe_hic_drv_info2 fw_cmd;
4595         s32 ret_val = IXGBE_SUCCESS;
4596         int i;
4597
4598         DEBUGFUNC("ixgbe_set_fw_drv_ver_x550");
4599
4600         if ((len == 0) || (driver_ver == NULL) ||
4601            (len > sizeof(fw_cmd.driver_string)))
4602                 return IXGBE_ERR_INVALID_ARGUMENT;
4603
4604         fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4605         fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len;
4606         fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4607         fw_cmd.port_num = (u8)hw->bus.func;
4608         fw_cmd.ver_maj = maj;
4609         fw_cmd.ver_min = min;
4610         fw_cmd.ver_build = build;
4611         fw_cmd.ver_sub = sub;
4612         fw_cmd.hdr.checksum = 0;
4613         memcpy(fw_cmd.driver_string, driver_ver, len);
4614         fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4615                                 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4616
4617         for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4618                 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4619                                                        sizeof(fw_cmd),
4620                                                        IXGBE_HI_COMMAND_TIMEOUT,
4621                                                        true);
4622                 if (ret_val != IXGBE_SUCCESS)
4623                         continue;
4624
4625                 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4626                     FW_CEM_RESP_STATUS_SUCCESS)
4627                         ret_val = IXGBE_SUCCESS;
4628                 else
4629                         ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4630
4631                 break;
4632         }
4633
4634         return ret_val;
4635 }
4636
4637 /**
4638  * ixgbe_fw_recovery_mode_X550 - Check FW NVM recovery mode
4639  * @hw: pointer t hardware structure
4640  *
4641  * Returns true if in FW NVM recovery mode.
4642  **/
4643 bool ixgbe_fw_recovery_mode_X550(struct ixgbe_hw *hw)
4644 {
4645         u32 fwsm;
4646
4647         fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
4648
4649         return !!(fwsm & IXGBE_FWSM_FW_NVM_RECOVERY_MODE);
4650 }