drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42
  43 /**
  44  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  45  *  @hw: pointer to hardware structure
  46  *
  47  *  Initialize the function pointers and assign the MAC type for X550.
  48  *  Does not touch the hardware.
  49  **/
  50 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  51 {
  52         struct ixgbe_mac_info *mac = &hw->mac;
  53         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  54         s32 ret_val;
  55
  56         DEBUGFUNC("ixgbe_init_ops_X550");
  57
  58         ret_val = ixgbe_init_ops_X540(hw);
  59         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  60         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  61         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  62         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  63         mac->ops.set_source_address_pruning =
  64                         ixgbe_set_source_address_pruning_X550;
  65         mac->ops.set_ethertype_anti_spoofing =
  66                         ixgbe_set_ethertype_anti_spoofing_X550;
  67
  68         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  69         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  70         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  71         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  72         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  73         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  74         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  75         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  76         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  77
  78         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  79         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  80         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  81         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  82         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  83         return ret_val;
  84 }
  85
  86 /**
  87  * ixgbe_read_cs4227 - Read CS4227 register
  88  * @hw: pointer to hardware structure
  89  * @reg: register number to write
  90  * @value: pointer to receive value read
  91  *
  92  * Returns status code
  93  **/
  94 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  95 {
  96         return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
  97 }
  98
  99 /**
 100  * ixgbe_write_cs4227 - Write CS4227 register
 101  * @hw: pointer to hardware structure
 102  * @reg: register number to write
 103  * @value: value to write to register
 104  *
 105  * Returns status code
 106  **/
 107 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 108 {
 109         return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 110 }
 111
 112 /**
 113  * ixgbe_get_cs4227_status - Return CS4227 status
 114  * @hw: pointer to hardware structure
 115  *
 116  * Returns error if CS4227 not successfully initialized
 117  **/
 118 STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
 119 {
 120         s32 status;
 121         u16 value = 0;
 122         u16 reg_slice, reg_val;
 123         u8 retry;
 124
 125         for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) {
 126                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB,
 127                                            &value);
 128                 if (status != IXGBE_SUCCESS)
 129                         return status;
 130                 if (value == IXGBE_CS4227_GLOBAL_ID_VALUE)
 131                         break;
 132                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 133         }
 134         if (value != IXGBE_CS4227_GLOBAL_ID_VALUE)
 135                 return IXGBE_ERR_PHY;
 136
 137         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 138         if (status != IXGBE_SUCCESS)
 139                 return status;
 140
 141         /* If this is the first time after power-on, check the ucode.
 142          * Otherwise, this will disrupt link on all ports. Because we
 143          * can only do this the first time, we must check all ports,
 144          * not just our own.
 145          */
 146         if (value != IXGBE_CS4227_SCRATCH_VALUE) {
 147                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB;
 148                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
 149                 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
 150                 if (status != IXGBE_SUCCESS)
 151                         return status;
 152
 153                 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB;
 154                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
 155                 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
 156                 if (status != IXGBE_SUCCESS)
 157                         return status;
 158
 159                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (1 << 12);
 160                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
 161                 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
 162                 if (status != IXGBE_SUCCESS)
 163                         return status;
 164
 165                 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (1 << 12);
 166                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
 167                 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
 168                 if (status != IXGBE_SUCCESS)
 169                         return status;
 170
 171                 msec_delay(10);
 172         }
 173
 174         /* Verify that the ucode is operational on all ports. */
 175         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB;
 176         reg_val = 0xFFFF;
 177         status = ixgbe_read_cs4227(hw, reg_slice, &reg_val);
 178         if (status != IXGBE_SUCCESS)
 179                 return status;
 180         if (reg_val != 0)
 181                 return IXGBE_ERR_PHY;
 182
 183         reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB;
 184         reg_val = 0xFFFF;
 185         status = ixgbe_read_cs4227(hw, reg_slice, &reg_val);
 186         if (status != IXGBE_SUCCESS)
 187                 return status;
 188         if (reg_val != 0)
 189                 return IXGBE_ERR_PHY;
 190
 191         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (1 << 12);
 192         reg_val = 0xFFFF;
 193         status = ixgbe_read_cs4227(hw, reg_slice, &reg_val);
 194         if (status != IXGBE_SUCCESS)
 195                 return status;
 196         if (reg_val != 0)
 197                 return IXGBE_ERR_PHY;
 198
 199         reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (1 << 12);
 200         reg_val = 0xFFFF;
 201         status = ixgbe_read_cs4227(hw, reg_slice, &reg_val);
 202         if (status != IXGBE_SUCCESS)
 203                 return status;
 204         if (reg_val != 0)
 205                 return IXGBE_ERR_PHY;
 206
 207         /* Set scratch indicating that the diagnostic was successful. */
 208         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 209                                     IXGBE_CS4227_SCRATCH_VALUE);
 210         if (status != IXGBE_SUCCESS)
 211                 return status;
 212         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 213         if (status != IXGBE_SUCCESS)
 214                 return status;
 215         if (value != IXGBE_CS4227_SCRATCH_VALUE)
 216                 return IXGBE_ERR_PHY;
 217
 218         return IXGBE_SUCCESS;
 219 }
 220
 221 /**
 222  * ixgbe_read_pe - Read register from port expander
 223  * @hw: pointer to hardware structure
 224  * @reg: register number to read
 225  * @value: pointer to receive read value
 226  *
 227  * Returns status code
 228  **/
 229 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 230 {
 231         s32 status;
 232
 233         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 234         if (status != IXGBE_SUCCESS)
 235                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 236                               "port expander access failed with %d\n", status);
 237         return status;
 238 }
 239
 240 /**
 241  * ixgbe_write_pe - Write register to port expander
 242  * @hw: pointer to hardware structure
 243  * @reg: register number to write
 244  * @value: value to write
 245  *
 246  * Returns status code
 247  **/
 248 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 249 {
 250         s32 status;
 251
 252         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 253         if (status != IXGBE_SUCCESS)
 254                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 255                               "port expander access failed with %d\n", status);
 256         return status;
 257 }
 258
 259 /**
 260  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 261  * @hw: pointer to hardware structure
 262  *
 263  * Returns error code
 264  **/
 265 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 266 {
 267         s32 status;
 268         u8 reg;
 269
 270         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 271         if (status != IXGBE_SUCCESS)
 272                 return status;
 273         reg |= IXGBE_PE_BIT1;
 274         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 275         if (status != IXGBE_SUCCESS)
 276                 return status;
 277
 278         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 279         if (status != IXGBE_SUCCESS)
 280                 return status;
 281         reg &= ~IXGBE_PE_BIT1;
 282         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 283         if (status != IXGBE_SUCCESS)
 284                 return status;
 285
 286         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 287         if (status != IXGBE_SUCCESS)
 288                 return status;
 289         reg &= ~IXGBE_PE_BIT1;
 290         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 291         if (status != IXGBE_SUCCESS)
 292                 return status;
 293
 294         usec_delay(IXGBE_CS4227_RESET_HOLD);
 295
 296         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 297         if (status != IXGBE_SUCCESS)
 298                 return status;
 299         reg |= IXGBE_PE_BIT1;
 300         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 301         if (status != IXGBE_SUCCESS)
 302                 return status;
 303
 304         msec_delay(IXGBE_CS4227_RESET_DELAY);
 305
 306         return IXGBE_SUCCESS;
 307 }
 308
 309 /**
 310  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 311  * @hw: pointer to hardware structure
 312  **/
 313 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 314 {
 315         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 316         s32 status;
 317         u8 retry;
 318
 319         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 320                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 321                 if (status != IXGBE_SUCCESS) {
 322                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 323                                       "semaphore failed with %d\n", status);
 324                         return;
 325                 }
 326                 status = ixgbe_get_cs4227_status(hw);
 327                 if (status == IXGBE_SUCCESS) {
 328                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 329                         msec_delay(hw->eeprom.semaphore_delay);
 330                         return;
 331                 }
 332                 ixgbe_reset_cs4227(hw);
 333                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 334                 msec_delay(hw->eeprom.semaphore_delay);
 335         }
 336         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 337                       "Unable to initialize CS4227, err=%d\n", status);
 338 }
 339
 340 /**
 341  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 342  * @hw: pointer to hardware structure
 343  **/
 344 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 345 {
 346         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 347
 348         if (hw->bus.lan_id) {
 349                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 350                 esdp |= IXGBE_ESDP_SDP1_DIR;
 351         }
 352         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 353         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 354         IXGBE_WRITE_FLUSH(hw);
 355 }
 356
 357 /**
 358  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 359  * @hw: pointer to hardware structure
 360  *
 361  * Returns error code
 362  */
 363 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 364 {
 365         switch (hw->device_id) {
 366         case IXGBE_DEV_ID_X550EM_X_SFP:
 367                 /* set up for CS4227 usage */
 368                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 369                 ixgbe_setup_mux_ctl(hw);
 370                 ixgbe_check_cs4227(hw);
 371
 372                 return ixgbe_identify_module_generic(hw);
 373                 break;
 374         case IXGBE_DEV_ID_X550EM_X_KX4:
 375                 hw->phy.type = ixgbe_phy_x550em_kx4;
 376                 break;
 377         case IXGBE_DEV_ID_X550EM_X_KR:
 378                 hw->phy.type = ixgbe_phy_x550em_kr;
 379                 break;
 380         case IXGBE_DEV_ID_X550EM_X_1G_T:
 381         case IXGBE_DEV_ID_X550EM_X_10G_T:
 382                 return ixgbe_identify_phy_generic(hw);
 383         default:
 384                 break;
 385         }
 386         return IXGBE_SUCCESS;
 387 }
 388
 389 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 390                                      u32 device_type, u16 *phy_data)
 391 {
 392         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 393         return IXGBE_NOT_IMPLEMENTED;
 394 }
 395
 396 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 397                                       u32 device_type, u16 phy_data)
 398 {
 399         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 400         return IXGBE_NOT_IMPLEMENTED;
 401 }
 402
 403 /**
 404 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 405 *  @hw: pointer to hardware structure
 406 *
 407 *  Initialize the function pointers and for MAC type X550EM.
 408 *  Does not touch the hardware.
 409 **/
 410 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 411 {
 412         struct ixgbe_mac_info *mac = &hw->mac;
 413         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 414         struct ixgbe_phy_info *phy = &hw->phy;
 415         s32 ret_val;
 416
 417         DEBUGFUNC("ixgbe_init_ops_X550EM");
 418
 419         /* Similar to X550 so start there. */
 420         ret_val = ixgbe_init_ops_X550(hw);
 421
 422         /* Since this function eventually calls
 423          * ixgbe_init_ops_540 by design, we are setting
 424          * the pointers to NULL explicitly here to overwrite
 425          * the values being set in the x540 function.
 426          */
 427         /* Thermal sensor not supported in x550EM */
 428         mac->ops.get_thermal_sensor_data = NULL;
 429         mac->ops.init_thermal_sensor_thresh = NULL;
 430         mac->thermal_sensor_enabled = false;
 431
 432         /* FCOE not supported in x550EM */
 433         mac->ops.get_san_mac_addr = NULL;
 434         mac->ops.set_san_mac_addr = NULL;
 435         mac->ops.get_wwn_prefix = NULL;
 436         mac->ops.get_fcoe_boot_status = NULL;
 437
 438         /* IPsec not supported in x550EM */
 439         mac->ops.disable_sec_rx_path = NULL;
 440         mac->ops.enable_sec_rx_path = NULL;
 441
 442         /* AUTOC register is not present in x550EM. */
 443         mac->ops.prot_autoc_read = NULL;
 444         mac->ops.prot_autoc_write = NULL;
 445
 446         /* X550EM bus type is internal*/
 447         hw->bus.type = ixgbe_bus_type_internal;
 448         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 449
 450         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 451         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 452         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 453         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 454         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 455         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 456         mac->ops.get_supported_physical_layer =
 457                                     ixgbe_get_supported_physical_layer_X550em;
 458
 459         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 460                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 461         else
 462                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 463
 464         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 465         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 466
 467         if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
 468                 mac->ops.setup_eee = NULL;
 469
 470         /* PHY */
 471         phy->ops.init = ixgbe_init_phy_ops_X550em;
 472         phy->ops.identify = ixgbe_identify_phy_x550em;
 473         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 474                 phy->ops.set_phy_power = NULL;
 475
 476
 477         /* EEPROM */
 478         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 479         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 480         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 481         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 482         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 483         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 484         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 485         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 486
 487         return ret_val;
 488 }
 489
 490 /**
 491  *  ixgbe_dmac_config_X550
 492  *  @hw: pointer to hardware structure
 493  *
 494  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 495  *  When disabling dmac, dmac enable dmac bit is cleared.
 496  **/
 497 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 498 {
 499         u32 reg, high_pri_tc;
 500
 501         DEBUGFUNC("ixgbe_dmac_config_X550");
 502
 503         /* Disable DMA coalescing before configuring */
 504         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 505         reg &= ~IXGBE_DMACR_DMAC_EN;
 506         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 507
 508         /* Disable DMA Coalescing if the watchdog timer is 0 */
 509         if (!hw->mac.dmac_config.watchdog_timer)
 510                 goto out;
 511
 512         ixgbe_dmac_config_tcs_X550(hw);
 513
 514         /* Configure DMA Coalescing Control Register */
 515         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 516
 517         /* Set the watchdog timer in units of 40.96 usec */
 518         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 519         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 520
 521         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 522         /* If fcoe is enabled, set high priority traffic class */
 523         if (hw->mac.dmac_config.fcoe_en) {
 524                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 525                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 526                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 527         }
 528         reg |= IXGBE_DMACR_EN_MNG_IND;
 529
 530         /* Enable DMA coalescing after configuration */
 531         reg |= IXGBE_DMACR_DMAC_EN;
 532         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 533
 534 out:
 535         return IXGBE_SUCCESS;
 536 }
 537
 538 /**
 539  *  ixgbe_dmac_config_tcs_X550
 540  *  @hw: pointer to hardware structure
 541  *
 542  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 543  *  be cleared before configuring.
 544  **/
 545 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 546 {
 547         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 548
 549         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 550
 551         /* Configure DMA coalescing enabled */
 552         switch (hw->mac.dmac_config.link_speed) {
 553         case IXGBE_LINK_SPEED_100_FULL:
 554                 pb_headroom = IXGBE_DMACRXT_100M;
 555                 break;
 556         case IXGBE_LINK_SPEED_1GB_FULL:
 557                 pb_headroom = IXGBE_DMACRXT_1G;
 558                 break;
 559         default:
 560                 pb_headroom = IXGBE_DMACRXT_10G;
 561                 break;
 562         }
 563
 564         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 565                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 566
 567         /* Set the per Rx packet buffer receive threshold */
 568         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 569                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 570                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 571
 572                 if (tc < hw->mac.dmac_config.num_tcs) {
 573                         /* Get Rx PB size */
 574                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 575                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 576                                 IXGBE_RXPBSIZE_SHIFT;
 577
 578                         /* Calculate receive buffer threshold in kilobytes */
 579                         if (rx_pb_size > pb_headroom)
 580                                 rx_pb_size = rx_pb_size - pb_headroom;
 581                         else
 582                                 rx_pb_size = 0;
 583
 584                         /* Minimum of MFS shall be set for DMCTH */
 585                         reg |= (rx_pb_size > maxframe_size_kb) ?
 586                                 rx_pb_size : maxframe_size_kb;
 587                 }
 588                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 589         }
 590         return IXGBE_SUCCESS;
 591 }
 592
 593 /**
 594  *  ixgbe_dmac_update_tcs_X550
 595  *  @hw: pointer to hardware structure
 596  *
 597  *  Disables dmac, updates per TC settings, and then enables dmac.
 598  **/
 599 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 600 {
 601         u32 reg;
 602
 603         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 604
 605         /* Disable DMA coalescing before configuring */
 606         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 607         reg &= ~IXGBE_DMACR_DMAC_EN;
 608         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 609
 610         ixgbe_dmac_config_tcs_X550(hw);
 611
 612         /* Enable DMA coalescing after configuration */
 613         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 614         reg |= IXGBE_DMACR_DMAC_EN;
 615         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 616
 617         return IXGBE_SUCCESS;
 618 }
 619
 620 /**
 621  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 622  *  @hw: pointer to hardware structure
 623  *
 624  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 625  *  ixgbe_hw struct in order to set up EEPROM access.
 626  **/
 627 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 628 {
 629         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 630         u32 eec;
 631         u16 eeprom_size;
 632
 633         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 634
 635         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 636                 eeprom->semaphore_delay = 10;
 637                 eeprom->type = ixgbe_flash;
 638
 639                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 640                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 641                                     IXGBE_EEC_SIZE_SHIFT);
 642                 eeprom->word_size = 1 << (eeprom_size +
 643                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 644
 645                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 646                           eeprom->type, eeprom->word_size);
 647         }
 648
 649         return IXGBE_SUCCESS;
 650 }
 651
 652 /**
 653  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 654  *  @hw: pointer to the HW structure
 655  *  @enable_eee: boolean flag to enable EEE
 656  *
 657  *  Enable/disable EEE based on enable_eee flag.
 658  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 659  *  are modified.
 660  *
 661  **/
 662 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 663 {
 664         u32 eeer;
 665         u16 autoneg_eee_reg;
 666         u32 link_reg;
 667         s32 status;
 668         u32 fuse;
 669
 670         DEBUGFUNC("ixgbe_setup_eee_X550");
 671
 672         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 673         /* Enable or disable EEE per flag */
 674         if (enable_eee) {
 675                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 676
 677                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 678                         /* Advertise EEE capability */
 679                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 680                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 681
 682                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 683                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 684                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 685
 686                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 687                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 688                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 689                         /* Not supported on first revision. */
 690                         fuse = IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0));
 691                         if (!(fuse & IXGBE_FUSES0_REV1))
 692                                 return IXGBE_SUCCESS;
 693
 694                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 695                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 696                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 697                         if (status != IXGBE_SUCCESS)
 698                                 return status;
 699
 700                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 701                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 702
 703                         /* Don't advertise FEC capability when EEE enabled. */
 704                         link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 705
 706                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 707                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 708                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 709                         if (status != IXGBE_SUCCESS)
 710                                 return status;
 711                 }
 712         } else {
 713                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 714
 715                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 716                         /* Disable advertised EEE capability */
 717                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 718                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 719
 720                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 721                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 722                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 723
 724                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 725                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 726                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 727                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 728                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 729                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 730                         if (status != IXGBE_SUCCESS)
 731                                 return status;
 732
 733                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 734                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 735
 736                         /* Advertise FEC capability when EEE is disabled. */
 737                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 738
 739                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 740                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 741                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 742                         if (status != IXGBE_SUCCESS)
 743                                 return status;
 744                 }
 745         }
 746         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 747
 748         return IXGBE_SUCCESS;
 749 }
 750
 751 /**
 752  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 753  * @hw: pointer to hardware structure
 754  * @enable: enable or disable source address pruning
 755  * @pool: Rx pool to set source address pruning for
 756  **/
 757 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 758                                            unsigned int pool)
 759 {
 760         u64 pfflp;
 761
 762         /* max rx pool is 63 */
 763         if (pool > 63)
 764                 return;
 765
 766         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 767         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 768
 769         if (enable)
 770                 pfflp |= (1ULL << pool);
 771         else
 772                 pfflp &= ~(1ULL << pool);
 773
 774         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 775         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 776 }
 777
 778 /**
 779  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 780  *  @hw: pointer to hardware structure
 781  *  @enable: enable or disable switch for Ethertype anti-spoofing
 782  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 783  *
 784  **/
 785 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 786                 bool enable, int vf)
 787 {
 788         int vf_target_reg = vf >> 3;
 789         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 790         u32 pfvfspoof;
 791
 792         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 793
 794         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 795         if (enable)
 796                 pfvfspoof |= (1 << vf_target_shift);
 797         else
 798                 pfvfspoof &= ~(1 << vf_target_shift);
 799
 800         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 801 }
 802
 803 /**
 804  * ixgbe_iosf_wait - Wait for IOSF command completion
 805  * @hw: pointer to hardware structure
 806  * @ctrl: pointer to location to receive final IOSF control value
 807  *
 808  * Returns failing status on timeout
 809  *
 810  * Note: ctrl can be NULL if the IOSF control register value is not needed
 811  **/
 812 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
 813 {
 814         u32 i, command = 0;
 815
 816         /* Check every 10 usec to see if the address cycle completed.
 817          * The SB IOSF BUSY bit will clear when the operation is
 818          * complete
 819          */
 820         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 821                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 822                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 823                         break;
 824                 usec_delay(10);
 825         }
 826         if (ctrl)
 827                 *ctrl = command;
 828         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 829                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
 830                 return IXGBE_ERR_PHY;
 831         }
 832
 833         return IXGBE_SUCCESS;
 834 }
 835
 836 /**
 837  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 838  *  device
 839  *  @hw: pointer to hardware structure
 840  *  @reg_addr: 32 bit PHY register to write
 841  *  @device_type: 3 bit device type
 842  *  @data: Data to write to the register
 843  **/
 844 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 845                             u32 device_type, u32 data)
 846 {
 847         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 848         u32 command, error;
 849         s32 ret;
 850
 851         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
 852         if (ret != IXGBE_SUCCESS)
 853                 return ret;
 854
 855         ret = ixgbe_iosf_wait(hw, NULL);
 856         if (ret != IXGBE_SUCCESS)
 857                 goto out;
 858
 859         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 860                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 861
 862         /* Write IOSF control register */
 863         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 864
 865         /* Write IOSF data register */
 866         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 867
 868         ret = ixgbe_iosf_wait(hw, &command);
 869
 870         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 871                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 872                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 873                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 874                               "Failed to write, error %x\n", error);
 875                 ret = IXGBE_ERR_PHY;
 876         }
 877
 878 out:
 879         ixgbe_release_swfw_semaphore(hw, gssr);
 880         return ret;
 881 }
 882
 883 /**
 884  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 885  *  device
 886  *  @hw: pointer to hardware structure
 887  *  @reg_addr: 32 bit PHY register to write
 888  *  @device_type: 3 bit device type
 889  *  @phy_data: Pointer to read data from the register
 890  **/
 891 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 892                            u32 device_type, u32 *data)
 893 {
 894         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 895         u32 command, error;
 896         s32 ret;
 897
 898         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
 899         if (ret != IXGBE_SUCCESS)
 900                 return ret;
 901
 902         ret = ixgbe_iosf_wait(hw, NULL);
 903         if (ret != IXGBE_SUCCESS)
 904                 goto out;
 905
 906         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 907                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 908
 909         /* Write IOSF control register */
 910         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 911
 912         ret = ixgbe_iosf_wait(hw, &command);
 913
 914         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 915                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 916                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 917                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 918                                 "Failed to read, error %x\n", error);
 919                 ret = IXGBE_ERR_PHY;
 920         }
 921
 922         if (ret == IXGBE_SUCCESS)
 923                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 924
 925 out:
 926         ixgbe_release_swfw_semaphore(hw, gssr);
 927         return ret;
 928 }
 929
 930 /**
 931  *  ixgbe_disable_mdd_X550
 932  *  @hw: pointer to hardware structure
 933  *
 934  *  Disable malicious driver detection
 935  **/
 936 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
 937 {
 938         u32 reg;
 939
 940         DEBUGFUNC("ixgbe_disable_mdd_X550");
 941
 942         /* Disable MDD for TX DMA and interrupt */
 943         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 944         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 945         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 946
 947         /* Disable MDD for RX and interrupt */
 948         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 949         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 950         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 951 }
 952
 953 /**
 954  *  ixgbe_enable_mdd_X550
 955  *  @hw: pointer to hardware structure
 956  *
 957  *  Enable malicious driver detection
 958  **/
 959 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
 960 {
 961         u32 reg;
 962
 963         DEBUGFUNC("ixgbe_enable_mdd_X550");
 964
 965         /* Enable MDD for TX DMA and interrupt */
 966         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 967         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 968         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 969
 970         /* Enable MDD for RX and interrupt */
 971         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 972         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 973         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 974 }
 975
 976 /**
 977  *  ixgbe_restore_mdd_vf_X550
 978  *  @hw: pointer to hardware structure
 979  *  @vf: vf index
 980  *
 981  *  Restore VF that was disabled during malicious driver detection event
 982  **/
 983 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
 984 {
 985         u32 idx, reg, num_qs, start_q, bitmask;
 986
 987         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
 988
 989         /* Map VF to queues */
 990         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 991         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 992         case IXGBE_MRQC_VMDQRT8TCEN:
 993                 num_qs = 8;  /* 16 VFs / pools */
 994                 bitmask = 0x000000FF;
 995                 break;
 996         case IXGBE_MRQC_VMDQRSS32EN:
 997         case IXGBE_MRQC_VMDQRT4TCEN:
 998                 num_qs = 4;  /* 32 VFs / pools */
 999                 bitmask = 0x0000000F;
1000                 break;
1001         default:            /* 64 VFs / pools */
1002                 num_qs = 2;
1003                 bitmask = 0x00000003;
1004                 break;
1005         }
1006         start_q = vf * num_qs;
1007
1008         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1009         idx = start_q / 32;
1010         reg = 0;
1011         reg |= (bitmask << (start_q % 32));
1012         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1013         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1014 }
1015
1016 /**
1017  *  ixgbe_mdd_event_X550
1018  *  @hw: pointer to hardware structure
1019  *  @vf_bitmap: vf bitmap of malicious vfs
1020  *
1021  *  Handle malicious driver detection event.
1022  **/
1023 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1024 {
1025         u32 wqbr;
1026         u32 i, j, reg, q, shift, vf, idx;
1027
1028         DEBUGFUNC("ixgbe_mdd_event_X550");
1029
1030         /* figure out pool size for mapping to vf's */
1031         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1032         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1033         case IXGBE_MRQC_VMDQRT8TCEN:
1034                 shift = 3;  /* 16 VFs / pools */
1035                 break;
1036         case IXGBE_MRQC_VMDQRSS32EN:
1037         case IXGBE_MRQC_VMDQRT4TCEN:
1038                 shift = 2;  /* 32 VFs / pools */
1039                 break;
1040         default:
1041                 shift = 1;  /* 64 VFs / pools */
1042                 break;
1043         }
1044
1045         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1046         for (i = 0; i < 4; i++) {
1047                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1048                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1049
1050                 if (!wqbr)
1051                         continue;
1052
1053                 /* Get malicious queue */
1054                 for (j = 0; j < 32 && wqbr; j++) {
1055
1056                         if (!(wqbr & (1 << j)))
1057                                 continue;
1058
1059                         /* Get queue from bitmask */
1060                         q = j + (i * 32);
1061
1062                         /* Map queue to vf */
1063                         vf = (q >> shift);
1064
1065                         /* Set vf bit in vf_bitmap */
1066                         idx = vf / 32;
1067                         vf_bitmap[idx] |= (1 << (vf % 32));
1068                         wqbr &= ~(1 << j);
1069                 }
1070         }
1071 }
1072
1073 /**
1074  *  ixgbe_get_media_type_X550em - Get media type
1075  *  @hw: pointer to hardware structure
1076  *
1077  *  Returns the media type (fiber, copper, backplane)
1078  */
1079 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1080 {
1081         enum ixgbe_media_type media_type;
1082
1083         DEBUGFUNC("ixgbe_get_media_type_X550em");
1084
1085         /* Detect if there is a copper PHY attached. */
1086         switch (hw->device_id) {
1087         case IXGBE_DEV_ID_X550EM_X_KR:
1088         case IXGBE_DEV_ID_X550EM_X_KX4:
1089                 media_type = ixgbe_media_type_backplane;
1090                 break;
1091         case IXGBE_DEV_ID_X550EM_X_SFP:
1092                 media_type = ixgbe_media_type_fiber;
1093                 break;
1094         case IXGBE_DEV_ID_X550EM_X_1G_T:
1095         case IXGBE_DEV_ID_X550EM_X_10G_T:
1096                 media_type = ixgbe_media_type_copper;
1097                 break;
1098         default:
1099                 media_type = ixgbe_media_type_unknown;
1100                 break;
1101         }
1102         return media_type;
1103 }
1104
1105 /**
1106  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1107  *  @hw: pointer to hardware structure
1108  *  @linear: true if SFP module is linear
1109  */
1110 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1111 {
1112         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1113
1114         switch (hw->phy.sfp_type) {
1115         case ixgbe_sfp_type_not_present:
1116                 return IXGBE_ERR_SFP_NOT_PRESENT;
1117         case ixgbe_sfp_type_da_cu_core0:
1118         case ixgbe_sfp_type_da_cu_core1:
1119                 *linear = true;
1120                 break;
1121         case ixgbe_sfp_type_srlr_core0:
1122         case ixgbe_sfp_type_srlr_core1:
1123         case ixgbe_sfp_type_da_act_lmt_core0:
1124         case ixgbe_sfp_type_da_act_lmt_core1:
1125         case ixgbe_sfp_type_1g_sx_core0:
1126         case ixgbe_sfp_type_1g_sx_core1:
1127         case ixgbe_sfp_type_1g_lx_core0:
1128         case ixgbe_sfp_type_1g_lx_core1:
1129                 *linear = false;
1130                 break;
1131         case ixgbe_sfp_type_unknown:
1132         case ixgbe_sfp_type_1g_cu_core0:
1133         case ixgbe_sfp_type_1g_cu_core1:
1134         default:
1135                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1136         }
1137
1138         return IXGBE_SUCCESS;
1139 }
1140
1141 /**
1142  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1143  *  @hw: pointer to hardware structure
1144  *
1145  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1146  **/
1147 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1148 {
1149         s32 status;
1150         bool linear;
1151
1152         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1153
1154         status = ixgbe_identify_module_generic(hw);
1155
1156         if (status != IXGBE_SUCCESS)
1157                 return status;
1158
1159         /* Check if SFP module is supported */
1160         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1161
1162         return status;
1163 }
1164
1165 /**
1166  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1167  *  @hw: pointer to hardware structure
1168  */
1169 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1170 {
1171         s32 status;
1172         bool linear;
1173
1174         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1175
1176         /* Check if SFP module is supported */
1177         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1178
1179         if (status != IXGBE_SUCCESS)
1180                 return status;
1181
1182         ixgbe_init_mac_link_ops_X550em(hw);
1183         hw->phy.ops.reset = NULL;
1184
1185         return IXGBE_SUCCESS;
1186 }
1187
1188 /**
1189  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1190  *  @hw: pointer to hardware structure
1191  */
1192 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1193 {
1194         struct ixgbe_mac_info *mac = &hw->mac;
1195
1196         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1197
1198          switch (hw->mac.ops.get_media_type(hw)) {
1199          case ixgbe_media_type_fiber:
1200                 /* CS4227 does not support autoneg, so disable the laser control
1201                  * functions for SFP+ fiber
1202                  */
1203                 mac->ops.disable_tx_laser = NULL;
1204                 mac->ops.enable_tx_laser = NULL;
1205                 mac->ops.flap_tx_laser = NULL;
1206                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1207                 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1208                 mac->ops.set_rate_select_speed =
1209                                         ixgbe_set_soft_rate_select_speed;
1210                 break;
1211         case ixgbe_media_type_copper:
1212                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1213                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1214                 break;
1215         default:
1216                 break;
1217          }
1218 }
1219
1220 /**
1221  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1222  *  @hw: pointer to hardware structure
1223  *  @speed: pointer to link speed
1224  *  @autoneg: true when autoneg or autotry is enabled
1225  */
1226 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1227                                        ixgbe_link_speed *speed,
1228                                        bool *autoneg)
1229 {
1230         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1231
1232         /* SFP */
1233         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1234
1235                 /* CS4227 SFP must not enable auto-negotiation */
1236                 *autoneg = false;
1237
1238                 /* Check if 1G SFP module. */
1239                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1240                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1241                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1242                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1243                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1244                         return IXGBE_SUCCESS;
1245                 }
1246
1247                 /* Link capabilities are based on SFP */
1248                 if (hw->phy.multispeed_fiber)
1249                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1250                                  IXGBE_LINK_SPEED_1GB_FULL;
1251                 else
1252                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1253         } else {
1254                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1255                          IXGBE_LINK_SPEED_1GB_FULL;
1256                 *autoneg = true;
1257         }
1258
1259         return IXGBE_SUCCESS;
1260 }
1261
1262 /**
1263  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1264  * @hw: pointer to hardware structure
1265  * @lsc: pointer to boolean flag which indicates whether external Base T
1266  *       PHY interrupt is lsc
1267  *
1268  * Determime if external Base T PHY interrupt cause is high temperature
1269  * failure alarm or link status change.
1270  *
1271  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1272  * failure alarm, else return PHY access status.
1273  */
1274 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1275 {
1276         u32 status;
1277         u16 reg;
1278
1279         *lsc = false;
1280
1281         /* Vendor alarm triggered */
1282         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1283                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1284                                       &reg);
1285
1286         if (status != IXGBE_SUCCESS ||
1287             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1288                 return status;
1289
1290         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1291         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1292                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1293                                       &reg);
1294
1295         if (status != IXGBE_SUCCESS ||
1296             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1297             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1298                 return status;
1299
1300         /* High temperature failure alarm triggered */
1301         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1302                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1303                                       &reg);
1304
1305         if (status != IXGBE_SUCCESS)
1306                 return status;
1307
1308         /* If high temperature failure, then return over temp error and exit */
1309         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1310                 /* power down the PHY in case the PHY FW didn't already */
1311                 ixgbe_set_copper_phy_power(hw, false);
1312                 return IXGBE_ERR_OVERTEMP;
1313         }
1314
1315         /* Vendor alarm 2 triggered */
1316         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1317                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1318
1319         if (status != IXGBE_SUCCESS ||
1320             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1321                 return status;
1322
1323         /* link connect/disconnect event occurred */
1324         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1325                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1326
1327         if (status != IXGBE_SUCCESS)
1328                 return status;
1329
1330         /* Indicate LSC */
1331         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1332                 *lsc = true;
1333
1334         return IXGBE_SUCCESS;
1335 }
1336
1337 /**
1338  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1339  * @hw: pointer to hardware structure
1340  *
1341  * Enable link status change and temperature failure alarm for the external
1342  * Base T PHY
1343  *
1344  * Returns PHY access status
1345  */
1346 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1347 {
1348         u32 status;
1349         u16 reg;
1350         bool lsc;
1351
1352         /* Clear interrupt flags */
1353         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1354
1355         /* Enable link status change alarm */
1356         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1357                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1358
1359         if (status != IXGBE_SUCCESS)
1360                 return status;
1361
1362         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1363
1364         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1365                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1366
1367         if (status != IXGBE_SUCCESS)
1368                 return status;
1369
1370         /* Enables high temperature failure alarm */
1371         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1372                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1373                                       &reg);
1374
1375         if (status != IXGBE_SUCCESS)
1376                 return status;
1377
1378         reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;
1379
1380         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1381                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1382                                        reg);
1383
1384         if (status != IXGBE_SUCCESS)
1385                 return status;
1386
1387         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1388         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1389                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1390                                       &reg);
1391
1392         if (status != IXGBE_SUCCESS)
1393                 return status;
1394
1395         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1396                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1397
1398         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1399                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1400                                        reg);
1401
1402         if (status != IXGBE_SUCCESS)
1403                 return status;
1404
1405         /* Enable chip-wide vendor alarm */
1406         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1407                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1408                                       &reg);
1409
1410         if (status != IXGBE_SUCCESS)
1411                 return status;
1412
1413         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1414
1415         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1416                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1417                                        reg);
1418
1419         return status;
1420 }
1421
1422 /**
1423  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1424  *  @hw: pointer to hardware structure
1425  *  @speed: link speed
1426  *
1427  *  Configures the integrated KR PHY.
1428  **/
1429 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1430                                        ixgbe_link_speed speed)
1431 {
1432         s32 status;
1433         u32 reg_val;
1434
1435         status = ixgbe_read_iosf_sb_reg_x550(hw,
1436                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1437                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1438         if (status)
1439                 return status;
1440
1441         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1442         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1443                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1444
1445         /* Advertise 10G support. */
1446         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1447                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1448
1449         /* Advertise 1G support. */
1450         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1451                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1452
1453         /* Restart auto-negotiation. */
1454         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1455         status = ixgbe_write_iosf_sb_reg_x550(hw,
1456                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1457                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1458
1459         return status;
1460 }
1461
1462 /**
1463  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1464  *  @hw: pointer to hardware structure
1465  *
1466  *  Initialize any function pointers that were not able to be
1467  *  set during init_shared_code because the PHY/SFP type was
1468  *  not known.  Perform the SFP init if necessary.
1469  */
1470 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1471 {
1472         struct ixgbe_phy_info *phy = &hw->phy;
1473         ixgbe_link_speed speed;
1474         s32 ret_val;
1475
1476         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1477
1478         hw->mac.ops.set_lan_id(hw);
1479
1480         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1481                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1482                 ixgbe_setup_mux_ctl(hw);
1483
1484                 /* Save NW management interface connected on board. This is used
1485                  * to determine internal PHY mode.
1486                  */
1487                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1488
1489                 /* If internal PHY mode is KR, then initialize KR link */
1490                 if (phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) {
1491                         speed = IXGBE_LINK_SPEED_10GB_FULL |
1492                                 IXGBE_LINK_SPEED_1GB_FULL;
1493                         ret_val = ixgbe_setup_kr_speed_x550em(hw, speed);
1494                 }
1495
1496                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
1497         }
1498
1499         /* Identify the PHY or SFP module */
1500         ret_val = phy->ops.identify(hw);
1501         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1502                 return ret_val;
1503
1504         /* Setup function pointers based on detected hardware */
1505         ixgbe_init_mac_link_ops_X550em(hw);
1506         if (phy->sfp_type != ixgbe_sfp_type_unknown)
1507                 phy->ops.reset = NULL;
1508
1509         /* Set functions pointers based on phy type */
1510         switch (hw->phy.type) {
1511         case ixgbe_phy_x550em_kx4:
1512                 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
1513                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1514                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1515                 break;
1516         case ixgbe_phy_x550em_kr:
1517                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1518                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1519                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1520                 break;
1521         case ixgbe_phy_x550em_ext_t:
1522                 /* Save NW management interface connected on board. This is used
1523                  * to determine internal PHY mode
1524                  */
1525                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1526
1527                 /* If internal link mode is XFI, then setup iXFI internal link,
1528                  * else setup KR now.
1529                  */
1530                 if (!(phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1531                         phy->ops.setup_internal_link =
1532                                               ixgbe_setup_internal_phy_t_x550em;
1533                 } else {
1534                         speed = IXGBE_LINK_SPEED_10GB_FULL |
1535                                 IXGBE_LINK_SPEED_1GB_FULL;
1536                         ret_val = ixgbe_setup_kr_speed_x550em(hw, speed);
1537                 }
1538
1539                 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1540                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1541                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1542                 break;
1543         default:
1544                 break;
1545         }
1546         return ret_val;
1547 }
1548
1549 /**
1550  *  ixgbe_reset_hw_X550em - Perform hardware reset
1551  *  @hw: pointer to hardware structure
1552  *
1553  *  Resets the hardware by resetting the transmit and receive units, masks
1554  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1555  *  reset.
1556  */
1557 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1558 {
1559         ixgbe_link_speed link_speed;
1560         s32 status;
1561         u32 ctrl = 0;
1562         u32 i;
1563         u32 hlreg0;
1564         bool link_up = false;
1565
1566         DEBUGFUNC("ixgbe_reset_hw_X550em");
1567
1568         /* Call adapter stop to disable Tx/Rx and clear interrupts */
1569         status = hw->mac.ops.stop_adapter(hw);
1570         if (status != IXGBE_SUCCESS)
1571                 return status;
1572
1573         /* flush pending Tx transactions */
1574         ixgbe_clear_tx_pending(hw);
1575
1576         /* PHY ops must be identified and initialized prior to reset */
1577
1578         /* Identify PHY and related function pointers */
1579         status = hw->phy.ops.init(hw);
1580
1581         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1582                 return status;
1583
1584         /* start the external PHY */
1585         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1586                 status = ixgbe_init_ext_t_x550em(hw);
1587                 if (status)
1588                         return status;
1589         }
1590
1591         /* Setup SFP module if there is one present. */
1592         if (hw->phy.sfp_setup_needed) {
1593                 status = hw->mac.ops.setup_sfp(hw);
1594                 hw->phy.sfp_setup_needed = false;
1595         }
1596
1597         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1598                 return status;
1599
1600         /* Reset PHY */
1601         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1602                 hw->phy.ops.reset(hw);
1603
1604 mac_reset_top:
1605         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1606          * If link reset is used when link is up, it might reset the PHY when
1607          * mng is using it.  If link is down or the flag to force full link
1608          * reset is set, then perform link reset.
1609          */
1610         ctrl = IXGBE_CTRL_LNK_RST;
1611         if (!hw->force_full_reset) {
1612                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1613                 if (link_up)
1614                         ctrl = IXGBE_CTRL_RST;
1615         }
1616
1617         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1618         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1619         IXGBE_WRITE_FLUSH(hw);
1620
1621         /* Poll for reset bit to self-clear meaning reset is complete */
1622         for (i = 0; i < 10; i++) {
1623                 usec_delay(1);
1624                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1625                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1626                         break;
1627         }
1628
1629         if (ctrl & IXGBE_CTRL_RST_MASK) {
1630                 status = IXGBE_ERR_RESET_FAILED;
1631                 DEBUGOUT("Reset polling failed to complete.\n");
1632         }
1633
1634         msec_delay(50);
1635
1636         /* Double resets are required for recovery from certain error
1637          * conditions.  Between resets, it is necessary to stall to
1638          * allow time for any pending HW events to complete.
1639          */
1640         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1641                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1642                 goto mac_reset_top;
1643         }
1644
1645         /* Store the permanent mac address */
1646         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1647
1648         /* Store MAC address from RAR0, clear receive address registers, and
1649          * clear the multicast table.  Also reset num_rar_entries to 128,
1650          * since we modify this value when programming the SAN MAC address.
1651          */
1652         hw->mac.num_rar_entries = 128;
1653         hw->mac.ops.init_rx_addrs(hw);
1654
1655         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
1656                 /* Config MDIO clock speed. */
1657                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1658                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
1659                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1660         }
1661
1662         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1663                 ixgbe_setup_mux_ctl(hw);
1664
1665         return status;
1666 }
1667
1668 /**
1669  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1670  * @hw: pointer to hardware structure
1671  */
1672 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1673 {
1674         u32 status;
1675         u16 reg;
1676
1677         status = hw->phy.ops.read_reg(hw,
1678                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1679                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1680                                       &reg);
1681
1682         if (status != IXGBE_SUCCESS)
1683                 return status;
1684
1685         /* If PHY FW reset completed bit is set then this is the first
1686          * SW instance after a power on so the PHY FW must be un-stalled.
1687          */
1688         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1689                 status = hw->phy.ops.read_reg(hw,
1690                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1691                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1692                                         &reg);
1693
1694                 if (status != IXGBE_SUCCESS)
1695                         return status;
1696
1697                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1698
1699                 status = hw->phy.ops.write_reg(hw,
1700                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1701                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1702                                         reg);
1703
1704                 if (status != IXGBE_SUCCESS)
1705                         return status;
1706         }
1707
1708         return status;
1709 }
1710
1711 /**
1712  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1713  *  @hw: pointer to hardware structure
1714  *
1715  *  Configures the integrated KR PHY.
1716  **/
1717 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1718 {
1719         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
1720 }
1721
1722 /**
1723  *  ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1724  *  @hw: pointer to hardware structure
1725  *
1726  *  Configures the integrated KX4 PHY.
1727  **/
1728 s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1729 {
1730         s32 status;
1731         u32 reg_val;
1732
1733         status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1734                 IXGBE_SB_IOSF_TARGET_KX4_PCS, &reg_val);
1735         if (status)
1736                 return status;
1737
1738         reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1739                         IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1740
1741         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1742
1743         /* Advertise 10G support. */
1744         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1745                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1746
1747         /* Advertise 1G support. */
1748         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1749                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1750
1751         /* Restart auto-negotiation. */
1752         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1753         status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1754                 IXGBE_SB_IOSF_TARGET_KX4_PCS, reg_val);
1755
1756         return status;
1757 }
1758
1759 /**
1760  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1761  *  @hw: pointer to hardware structure
1762  *  @speed: the link speed to force
1763  *
1764  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1765  *  internal and external PHY at a specific speed, without autonegotiation.
1766  **/
1767 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1768 {
1769         s32 status;
1770         u32 reg_val;
1771
1772         /* Disable AN and force speed to 10G Serial. */
1773         status = ixgbe_read_iosf_sb_reg_x550(hw,
1774                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1775                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1776         if (status != IXGBE_SUCCESS)
1777                 return status;
1778
1779         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1780         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1781
1782         /* Select forced link speed for internal PHY. */
1783         switch (*speed) {
1784         case IXGBE_LINK_SPEED_10GB_FULL:
1785                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1786                 break;
1787         case IXGBE_LINK_SPEED_1GB_FULL:
1788                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1789                 break;
1790         default:
1791                 /* Other link speeds are not supported by internal KR PHY. */
1792                 return IXGBE_ERR_LINK_SETUP;
1793         }
1794
1795         status = ixgbe_write_iosf_sb_reg_x550(hw,
1796                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1797                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1798         if (status != IXGBE_SUCCESS)
1799                 return status;
1800
1801         /* Disable training protocol FSM. */
1802         status = ixgbe_read_iosf_sb_reg_x550(hw,
1803                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1804                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1805         if (status != IXGBE_SUCCESS)
1806                 return status;
1807         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1808         status = ixgbe_write_iosf_sb_reg_x550(hw,
1809                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1810                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1811         if (status != IXGBE_SUCCESS)
1812                 return status;
1813
1814         /* Disable Flex from training TXFFE. */
1815         status = ixgbe_read_iosf_sb_reg_x550(hw,
1816                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1817                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1818         if (status != IXGBE_SUCCESS)
1819                 return status;
1820         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1821         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1822         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1823         status = ixgbe_write_iosf_sb_reg_x550(hw,
1824                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1825                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1826         if (status != IXGBE_SUCCESS)
1827                 return status;
1828         status = ixgbe_read_iosf_sb_reg_x550(hw,
1829                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1830                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1831         if (status != IXGBE_SUCCESS)
1832                 return status;
1833         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1834         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1835         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1836         status = ixgbe_write_iosf_sb_reg_x550(hw,
1837                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1838                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1839         if (status != IXGBE_SUCCESS)
1840                 return status;
1841
1842         /* Enable override for coefficients. */
1843         status = ixgbe_read_iosf_sb_reg_x550(hw,
1844                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1845                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1846         if (status != IXGBE_SUCCESS)
1847                 return status;
1848         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1849         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1850         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1851         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1852         status = ixgbe_write_iosf_sb_reg_x550(hw,
1853                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1854                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1855         if (status != IXGBE_SUCCESS)
1856                 return status;
1857
1858         /* Toggle port SW reset by AN reset. */
1859         status = ixgbe_read_iosf_sb_reg_x550(hw,
1860                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1861                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1862         if (status != IXGBE_SUCCESS)
1863                 return status;
1864         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1865         status = ixgbe_write_iosf_sb_reg_x550(hw,
1866                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1867                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1868
1869         return status;
1870 }
1871
1872 /**
1873  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
1874  * @hw: address of hardware structure
1875  * @link_up: address of boolean to indicate link status
1876  *
1877  * Returns error code if unable to get link status.
1878  */
1879 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
1880 {
1881         u32 ret;
1882         u16 autoneg_status;
1883
1884         *link_up = false;
1885
1886         /* read this twice back to back to indicate current status */
1887         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1888                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1889                                    &autoneg_status);
1890         if (ret != IXGBE_SUCCESS)
1891                 return ret;
1892
1893         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1894                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1895                                    &autoneg_status);
1896         if (ret != IXGBE_SUCCESS)
1897                 return ret;
1898
1899         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
1900
1901         return IXGBE_SUCCESS;
1902 }
1903
1904 /**
1905  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
1906  *  @hw: pointer to hardware structure
1907  *
1908  *  Configure the external PHY and the integrated KR PHY for SFP support.
1909  **/
1910 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1911                                     ixgbe_link_speed speed,
1912                                     bool autoneg_wait_to_complete)
1913 {
1914         s32 ret_val;
1915         u16 reg_slice, reg_val;
1916         bool setup_linear = false;
1917         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1918
1919         /* Check if SFP module is supported and linear */
1920         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1921
1922         /* If no SFP module present, then return success. Return success since
1923          * there is no reason to configure CS4227 and SFP not present error is
1924          * not excepted in the setup MAC link flow.
1925          */
1926         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1927                 return IXGBE_SUCCESS;
1928
1929         if (ret_val != IXGBE_SUCCESS)
1930                 return ret_val;
1931
1932         /* Configure CS4227 for LINE connection rate then type. */
1933         reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB + (hw->bus.lan_id << 12);
1934         reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000;
1935         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1936                                            reg_val);
1937
1938         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1939         if (setup_linear)
1940                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1941         else
1942                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1943         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1944                                            reg_val);
1945
1946         /* Configure CS4227 for HOST connection rate then type. */
1947         reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB + (hw->bus.lan_id << 12);
1948         reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000;
1949         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1950                                            reg_val);
1951
1952         reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (hw->bus.lan_id << 12);
1953         if (setup_linear)
1954                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1955         else
1956                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1957         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1958                                            reg_val);
1959
1960         /* If internal link mode is XFI, then setup XFI internal link. */
1961         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE))
1962                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
1963
1964         return ret_val;
1965 }
1966
1967 /**
1968  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1969  * @hw: point to hardware structure
1970  *
1971  * Configures the link between the integrated KR PHY and the external X557 PHY
1972  * The driver will call this function when it gets a link status change
1973  * interrupt from the X557 PHY. This function configures the link speed
1974  * between the PHYs to match the link speed of the BASE-T link.
1975  *
1976  * A return of a non-zero value indicates an error, and the base driver should
1977  * not report link up.
1978  */
1979 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
1980 {
1981         ixgbe_link_speed force_speed;
1982         bool link_up;
1983         u32 status;
1984         u16 speed;
1985
1986         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1987                 return IXGBE_ERR_CONFIG;
1988
1989         /* If link is not up, then there is no setup necessary so return  */
1990         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1991         if (status != IXGBE_SUCCESS)
1992                 return status;
1993
1994         if (!link_up)
1995                 return IXGBE_SUCCESS;
1996
1997         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1998                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1999                                       &speed);
2000         if (status != IXGBE_SUCCESS)
2001                 return status;
2002
2003         /* If link is not still up, then no setup is necessary so return */
2004         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2005         if (status != IXGBE_SUCCESS)
2006                 return status;
2007         if (!link_up)
2008                 return IXGBE_SUCCESS;
2009
2010         /* clear everything but the speed and duplex bits */
2011         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2012
2013         switch (speed) {
2014         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2015                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2016                 break;
2017         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2018                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2019                 break;
2020         default:
2021                 /* Internal PHY does not support anything else */
2022                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2023         }
2024
2025         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2026 }
2027
2028 /**
2029  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
2030  *  @hw: pointer to hardware structure
2031  *
2032  *  Configures the integrated KR PHY to use internal loopback mode.
2033  **/
2034 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
2035 {
2036         s32 status;
2037         u32 reg_val;
2038
2039         /* Disable AN and force speed to 10G Serial. */
2040         status = ixgbe_read_iosf_sb_reg_x550(hw,
2041                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2042                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2043         if (status != IXGBE_SUCCESS)
2044                 return status;
2045         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2046         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2047         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2048         status = ixgbe_write_iosf_sb_reg_x550(hw,
2049                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2050                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2051         if (status != IXGBE_SUCCESS)
2052                 return status;
2053
2054         /* Set near-end loopback clocks. */
2055         status = ixgbe_read_iosf_sb_reg_x550(hw,
2056                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2057                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2058         if (status != IXGBE_SUCCESS)
2059                 return status;
2060         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2061         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2062         status = ixgbe_write_iosf_sb_reg_x550(hw,
2063                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2064                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2065         if (status != IXGBE_SUCCESS)
2066                 return status;
2067
2068         /* Set loopback enable. */
2069         status = ixgbe_read_iosf_sb_reg_x550(hw,
2070                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2071                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2072         if (status != IXGBE_SUCCESS)
2073                 return status;
2074         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2075         status = ixgbe_write_iosf_sb_reg_x550(hw,
2076                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2077                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2078         if (status != IXGBE_SUCCESS)
2079                 return status;
2080
2081         /* Training bypass. */
2082         status = ixgbe_read_iosf_sb_reg_x550(hw,
2083                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2084                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2085         if (status != IXGBE_SUCCESS)
2086                 return status;
2087         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2088         status = ixgbe_write_iosf_sb_reg_x550(hw,
2089                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2090                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2091
2092         return status;
2093 }
2094
2095 /**
2096  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2097  *  assuming that the semaphore is already obtained.
2098  *  @hw: pointer to hardware structure
2099  *  @offset: offset of  word in the EEPROM to read
2100  *  @data: word read from the EEPROM
2101  *
2102  *  Reads a 16 bit word from the EEPROM using the hostif.
2103  **/
2104 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2105                                    u16 *data)
2106 {
2107         s32 status;
2108         struct ixgbe_hic_read_shadow_ram buffer;
2109
2110         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2111         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2112         buffer.hdr.req.buf_lenh = 0;
2113         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2114         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2115
2116         /* convert offset from words to bytes */
2117         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2118         /* one word */
2119         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2120
2121         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2122                                               sizeof(buffer),
2123                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2124
2125         if (status)
2126                 return status;
2127
2128         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2129                                           FW_NVM_DATA_OFFSET);
2130
2131         return 0;
2132 }
2133
2134 /**
2135  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2136  *  @hw: pointer to hardware structure
2137  *  @offset: offset of  word in the EEPROM to read
2138  *  @data: word read from the EEPROM
2139  *
2140  *  Reads a 16 bit word from the EEPROM using the hostif.
2141  **/
2142 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2143                               u16 *data)
2144 {
2145         s32 status = IXGBE_SUCCESS;
2146
2147         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2148
2149         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2150             IXGBE_SUCCESS) {
2151                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2152                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2153         } else {
2154                 status = IXGBE_ERR_SWFW_SYNC;
2155         }
2156
2157         return status;
2158 }
2159
2160 /**
2161  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2162  *  @hw: pointer to hardware structure
2163  *  @offset: offset of  word in the EEPROM to read
2164  *  @words: number of words
2165  *  @data: word(s) read from the EEPROM
2166  *
2167  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
2168  **/
2169 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2170                                      u16 offset, u16 words, u16 *data)
2171 {
2172         struct ixgbe_hic_read_shadow_ram buffer;
2173         u32 current_word = 0;
2174         u16 words_to_read;
2175         s32 status;
2176         u32 i;
2177
2178         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2179
2180         /* Take semaphore for the entire operation. */
2181         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2182         if (status) {
2183                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2184                 return status;
2185         }
2186         while (words) {
2187                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2188                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2189                 else
2190                         words_to_read = words;
2191
2192                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2193                 buffer.hdr.req.buf_lenh = 0;
2194                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2195                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2196
2197                 /* convert offset from words to bytes */
2198                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2199                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2200
2201                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2202                                                       sizeof(buffer),
2203                                                       IXGBE_HI_COMMAND_TIMEOUT,
2204                                                       false);
2205
2206                 if (status) {
2207                         DEBUGOUT("Host interface command failed\n");
2208                         goto out;
2209                 }
2210
2211                 for (i = 0; i < words_to_read; i++) {
2212                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
2213                                   2 * i;
2214                         u32 value = IXGBE_READ_REG(hw, reg);
2215
2216                         data[current_word] = (u16)(value & 0xffff);
2217                         current_word++;
2218                         i++;
2219                         if (i < words_to_read) {
2220                                 value >>= 16;
2221                                 data[current_word] = (u16)(value & 0xffff);
2222                                 current_word++;
2223                         }
2224                 }
2225                 words -= words_to_read;
2226         }
2227
2228 out:
2229         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2230         return status;
2231 }
2232
2233 /**
2234  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2235  *  @hw: pointer to hardware structure
2236  *  @offset: offset of  word in the EEPROM to write
2237  *  @data: word write to the EEPROM
2238  *
2239  *  Write a 16 bit word to the EEPROM using the hostif.
2240  **/
2241 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2242                                     u16 data)
2243 {
2244         s32 status;
2245         struct ixgbe_hic_write_shadow_ram buffer;
2246
2247         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
2248
2249         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
2250         buffer.hdr.req.buf_lenh = 0;
2251         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
2252         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2253
2254          /* one word */
2255         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2256         buffer.data = data;
2257         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2258
2259         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2260                                               sizeof(buffer),
2261                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2262
2263         return status;
2264 }
2265
2266 /**
2267  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2268  *  @hw: pointer to hardware structure
2269  *  @offset: offset of  word in the EEPROM to write
2270  *  @data: word write to the EEPROM
2271  *
2272  *  Write a 16 bit word to the EEPROM using the hostif.
2273  **/
2274 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2275                                u16 data)
2276 {
2277         s32 status = IXGBE_SUCCESS;
2278
2279         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2280
2281         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2282             IXGBE_SUCCESS) {
2283                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2284                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2285         } else {
2286                 DEBUGOUT("write ee hostif failed to get semaphore");
2287                 status = IXGBE_ERR_SWFW_SYNC;
2288         }
2289
2290         return status;
2291 }
2292
2293 /**
2294  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2295  *  @hw: pointer to hardware structure
2296  *  @offset: offset of  word in the EEPROM to write
2297  *  @words: number of words
2298  *  @data: word(s) write to the EEPROM
2299  *
2300  *  Write a 16 bit word(s) to the EEPROM using the hostif.
2301  **/
2302 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2303                                       u16 offset, u16 words, u16 *data)
2304 {
2305         s32 status = IXGBE_SUCCESS;
2306         u32 i = 0;
2307
2308         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2309
2310         /* Take semaphore for the entire operation. */
2311         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2312         if (status != IXGBE_SUCCESS) {
2313                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2314                 goto out;
2315         }
2316
2317         for (i = 0; i < words; i++) {
2318                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2319                                                          data[i]);
2320
2321                 if (status != IXGBE_SUCCESS) {
2322                         DEBUGOUT("Eeprom buffered write failed\n");
2323                         break;
2324                 }
2325         }
2326
2327         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2328 out:
2329
2330         return status;
2331 }
2332
2333 /**
2334  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2335  * @hw: pointer to hardware structure
2336  * @ptr: pointer offset in eeprom
2337  * @size: size of section pointed by ptr, if 0 first word will be used as size
2338  * @csum: address of checksum to update
2339  *
2340  * Returns error status for any failure
2341  */
2342 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2343                                    u16 size, u16 *csum, u16 *buffer,
2344                                    u32 buffer_size)
2345 {
2346         u16 buf[256];
2347         s32 status;
2348         u16 length, bufsz, i, start;
2349         u16 *local_buffer;
2350
2351         bufsz = sizeof(buf) / sizeof(buf[0]);
2352
2353         /* Read a chunk at the pointer location */
2354         if (!buffer) {
2355                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2356                 if (status) {
2357                         DEBUGOUT("Failed to read EEPROM image\n");
2358                         return status;
2359                 }
2360                 local_buffer = buf;
2361         } else {
2362                 if (buffer_size < ptr)
2363                         return  IXGBE_ERR_PARAM;
2364                 local_buffer = &buffer[ptr];
2365         }
2366
2367         if (size) {
2368                 start = 0;
2369                 length = size;
2370         } else {
2371                 start = 1;
2372                 length = local_buffer[0];
2373
2374                 /* Skip pointer section if length is invalid. */
2375                 if (length == 0xFFFF || length == 0 ||
2376                     (ptr + length) >= hw->eeprom.word_size)
2377                         return IXGBE_SUCCESS;
2378         }
2379
2380         if (buffer && ((u32)start + (u32)length > buffer_size))
2381                 return IXGBE_ERR_PARAM;
2382
2383         for (i = start; length; i++, length--) {
2384                 if (i == bufsz && !buffer) {
2385                         ptr += bufsz;
2386                         i = 0;
2387                         if (length < bufsz)
2388                                 bufsz = length;
2389
2390                         /* Read a chunk at the pointer location */
2391                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2392                                                                   bufsz, buf);
2393                         if (status) {
2394                                 DEBUGOUT("Failed to read EEPROM image\n");
2395                                 return status;
2396                         }
2397                 }
2398                 *csum += local_buffer[i];
2399         }
2400         return IXGBE_SUCCESS;
2401 }
2402
2403 /**
2404  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2405  *  @hw: pointer to hardware structure
2406  *  @buffer: pointer to buffer containing calculated checksum
2407  *  @buffer_size: size of buffer
2408  *
2409  *  Returns a negative error code on error, or the 16-bit checksum
2410  **/
2411 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2412 {
2413         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2414         u16 *local_buffer;
2415         s32 status;
2416         u16 checksum = 0;
2417         u16 pointer, i, size;
2418
2419         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2420
2421         hw->eeprom.ops.init_params(hw);
2422
2423         if (!buffer) {
2424                 /* Read pointer area */
2425                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2426                                                      IXGBE_EEPROM_LAST_WORD + 1,
2427                                                      eeprom_ptrs);
2428                 if (status) {
2429                         DEBUGOUT("Failed to read EEPROM image\n");
2430                         return status;
2431                 }
2432                 local_buffer = eeprom_ptrs;
2433         } else {
2434                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2435                         return IXGBE_ERR_PARAM;
2436                 local_buffer = buffer;
2437         }
2438
2439         /*
2440          * For X550 hardware include 0x0-0x41 in the checksum, skip the
2441          * checksum word itself
2442          */
2443         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2444                 if (i != IXGBE_EEPROM_CHECKSUM)
2445                         checksum += local_buffer[i];
2446
2447         /*
2448          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
2449          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2450          */
2451         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2452                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2453                         continue;
2454
2455                 pointer = local_buffer[i];
2456
2457                 /* Skip pointer section if the pointer is invalid. */
2458                 if (pointer == 0xFFFF || pointer == 0 ||
2459                     pointer >= hw->eeprom.word_size)
2460                         continue;
2461
2462                 switch (i) {
2463                 case IXGBE_PCIE_GENERAL_PTR:
2464                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2465                         break;
2466                 case IXGBE_PCIE_CONFIG0_PTR:
2467                 case IXGBE_PCIE_CONFIG1_PTR:
2468                         size = IXGBE_PCIE_CONFIG_SIZE;
2469                         break;
2470                 default:
2471                         size = 0;
2472                         break;
2473                 }
2474
2475                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2476                                                 buffer, buffer_size);
2477                 if (status)
2478                         return status;
2479         }
2480
2481         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2482
2483         return (s32)checksum;
2484 }
2485
2486 /**
2487  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2488  *  @hw: pointer to hardware structure
2489  *
2490  *  Returns a negative error code on error, or the 16-bit checksum
2491  **/
2492 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2493 {
2494         return ixgbe_calc_checksum_X550(hw, NULL, 0);
2495 }
2496
2497 /**
2498  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2499  *  @hw: pointer to hardware structure
2500  *  @checksum_val: calculated checksum
2501  *
2502  *  Performs checksum calculation and validates the EEPROM checksum.  If the
2503  *  caller does not need checksum_val, the value can be NULL.
2504  **/
2505 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2506 {
2507         s32 status;
2508         u16 checksum;
2509         u16 read_checksum = 0;
2510
2511         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2512
2513         /* Read the first word from the EEPROM. If this times out or fails, do
2514          * not continue or we could be in for a very long wait while every
2515          * EEPROM read fails
2516          */
2517         status = hw->eeprom.ops.read(hw, 0, &checksum);
2518         if (status) {
2519                 DEBUGOUT("EEPROM read failed\n");
2520                 return status;
2521         }
2522
2523         status = hw->eeprom.ops.calc_checksum(hw);
2524         if (status < 0)
2525                 return status;
2526
2527         checksum = (u16)(status & 0xffff);
2528
2529         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2530                                            &read_checksum);
2531         if (status)
2532                 return status;
2533
2534         /* Verify read checksum from EEPROM is the same as
2535          * calculated checksum
2536          */
2537         if (read_checksum != checksum) {
2538                 status = IXGBE_ERR_EEPROM_CHECKSUM;
2539                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2540                              "Invalid EEPROM checksum");
2541         }
2542
2543         /* If the user cares, return the calculated checksum */
2544         if (checksum_val)
2545                 *checksum_val = checksum;
2546
2547         return status;
2548 }
2549
2550 /**
2551  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2552  * @hw: pointer to hardware structure
2553  *
2554  * After writing EEPROM to shadow RAM using EEWR register, software calculates
2555  * checksum and updates the EEPROM and instructs the hardware to update
2556  * the flash.
2557  **/
2558 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2559 {
2560         s32 status;
2561         u16 checksum = 0;
2562
2563         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2564
2565         /* Read the first word from the EEPROM. If this times out or fails, do
2566          * not continue or we could be in for a very long wait while every
2567          * EEPROM read fails
2568          */
2569         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2570         if (status) {
2571                 DEBUGOUT("EEPROM read failed\n");
2572                 return status;
2573         }
2574
2575         status = ixgbe_calc_eeprom_checksum_X550(hw);
2576         if (status < 0)
2577                 return status;
2578
2579         checksum = (u16)(status & 0xffff);
2580
2581         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2582                                             checksum);
2583         if (status)
2584                 return status;
2585
2586         status = ixgbe_update_flash_X550(hw);
2587
2588         return status;
2589 }
2590
2591 /**
2592  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2593  *  @hw: pointer to hardware structure
2594  *
2595  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2596  **/
2597 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2598 {
2599         s32 status = IXGBE_SUCCESS;
2600         union ixgbe_hic_hdr2 buffer;
2601
2602         DEBUGFUNC("ixgbe_update_flash_X550");
2603
2604         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2605         buffer.req.buf_lenh = 0;
2606         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2607         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2608
2609         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2610                                               sizeof(buffer),
2611                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2612
2613         return status;
2614 }
2615
2616 /**
2617  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2618  *  @hw: pointer to hardware structure
2619  *
2620  *  Determines physical layer capabilities of the current configuration.
2621  **/
2622 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2623 {
2624         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2625         u16 ext_ability = 0;
2626
2627         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2628
2629         hw->phy.ops.identify(hw);
2630
2631         switch (hw->phy.type) {
2632         case ixgbe_phy_x550em_kr:
2633                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2634                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2635                 break;
2636         case ixgbe_phy_x550em_kx4:
2637                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2638                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2639                 break;
2640         case ixgbe_phy_x550em_ext_t:
2641                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2642                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2643                                      &ext_ability);
2644                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2645                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2646                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2647                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2648                 break;
2649         default:
2650                 break;
2651         }
2652
2653         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2654                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2655
2656         return physical_layer;
2657 }
2658
2659 /**
2660  * ixgbe_get_bus_info_x550em - Set PCI bus info
2661  * @hw: pointer to hardware structure
2662  *
2663  * Sets bus link width and speed to unknown because X550em is
2664  * not a PCI device.
2665  **/
2666 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2667 {
2668
2669         DEBUGFUNC("ixgbe_get_bus_info_x550em");
2670
2671         hw->bus.width = ixgbe_bus_width_unknown;
2672         hw->bus.speed = ixgbe_bus_speed_unknown;
2673
2674         hw->mac.ops.set_lan_id(hw);
2675
2676         return IXGBE_SUCCESS;
2677 }
2678
2679 /**
2680  * ixgbe_disable_rx_x550 - Disable RX unit
2681  *
2682  * Enables the Rx DMA unit for x550
2683  **/
2684 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2685 {
2686         u32 rxctrl, pfdtxgswc;
2687         s32 status;
2688         struct ixgbe_hic_disable_rxen fw_cmd;
2689
2690         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2691
2692         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2693         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2694                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2695                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2696                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2697                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2698                         hw->mac.set_lben = true;
2699                 } else {
2700                         hw->mac.set_lben = false;
2701                 }
2702
2703                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2704                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2705                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2706                 fw_cmd.port_number = (u8)hw->bus.lan_id;
2707
2708                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2709                                         sizeof(struct ixgbe_hic_disable_rxen),
2710                                         IXGBE_HI_COMMAND_TIMEOUT, true);
2711
2712                 /* If we fail - disable RX using register write */
2713                 if (status) {
2714                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2715                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2716                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2717                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2718                         }
2719                 }
2720         }
2721 }
2722
2723 /**
2724  * ixgbe_enter_lplu_x550em - Transition to low power states
2725  *  @hw: pointer to hardware structure
2726  *
2727  * Configures Low Power Link Up on transition to low power states
2728  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2729  * X557 PHY immediately prior to entering LPLU.
2730  **/
2731 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2732 {
2733         u16 an_10g_cntl_reg, autoneg_reg, speed;
2734         s32 status;
2735         ixgbe_link_speed lcd_speed;
2736         u32 save_autoneg;
2737         bool link_up;
2738
2739         /* If blocked by MNG FW, then don't restart AN */
2740         if (ixgbe_check_reset_blocked(hw))
2741                 return IXGBE_SUCCESS;
2742
2743         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2744         if (status != IXGBE_SUCCESS)
2745                 return status;
2746
2747         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2748
2749         if (status != IXGBE_SUCCESS)
2750                 return status;
2751
2752         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2753          * disabled, then force link down by entering low power mode.
2754          */
2755         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2756             !(hw->wol_enabled || ixgbe_mng_present(hw)))
2757                 return ixgbe_set_copper_phy_power(hw, FALSE);
2758
2759         /* Determine LCD */
2760         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2761
2762         if (status != IXGBE_SUCCESS)
2763                 return status;
2764
2765         /* If no valid LCD link speed, then force link down and exit. */
2766         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2767                 return ixgbe_set_copper_phy_power(hw, FALSE);
2768
2769         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2770                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2771                                       &speed);
2772
2773         if (status != IXGBE_SUCCESS)
2774                 return status;
2775
2776         /* If no link now, speed is invalid so take link down */
2777         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2778         if (status != IXGBE_SUCCESS)
2779                 return ixgbe_set_copper_phy_power(hw, false);
2780
2781         /* clear everything but the speed bits */
2782         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2783
2784         /* If current speed is already LCD, then exit. */
2785         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2786              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2787             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2788              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2789                 return status;
2790
2791         /* Clear AN completed indication */
2792         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2793                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2794                                       &autoneg_reg);
2795
2796         if (status != IXGBE_SUCCESS)
2797                 return status;
2798
2799         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2800                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2801                              &an_10g_cntl_reg);
2802
2803         if (status != IXGBE_SUCCESS)
2804                 return status;
2805
2806         status = hw->phy.ops.read_reg(hw,
2807                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2808                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2809                              &autoneg_reg);
2810
2811         if (status != IXGBE_SUCCESS)
2812                 return status;
2813
2814         save_autoneg = hw->phy.autoneg_advertised;
2815
2816         /* Setup link at least common link speed */
2817         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
2818
2819         /* restore autoneg from before setting lplu speed */
2820         hw->phy.autoneg_advertised = save_autoneg;
2821
2822         return status;
2823 }
2824
2825 /**
2826  * ixgbe_get_lcd_x550em - Determine lowest common denominator
2827  *  @hw: pointer to hardware structure
2828  *  @lcd_speed: pointer to lowest common link speed
2829  *
2830  * Determine lowest common link speed with link partner.
2831  **/
2832 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2833 {
2834         u16 an_lp_status;
2835         s32 status;
2836         u16 word = hw->eeprom.ctrl_word_3;
2837
2838         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2839
2840         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2841                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2842                                       &an_lp_status);
2843
2844         if (status != IXGBE_SUCCESS)
2845                 return status;
2846
2847         /* If link partner advertised 1G, return 1G */
2848         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2849                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2850                 return status;
2851         }
2852
2853         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2854         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2855             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2856                 return status;
2857
2858         /* Link partner not capable of lower speeds, return 10G */
2859         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2860         return status;
2861 }
2862
2863 /**
2864  *  ixgbe_setup_fc_X550em - Set up flow control
2865  *  @hw: pointer to hardware structure
2866  *
2867  *  Called at init time to set up flow control.
2868  **/
2869 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
2870 {
2871         s32 ret_val = IXGBE_SUCCESS;
2872         u32 pause, asm_dir, reg_val;
2873
2874         DEBUGFUNC("ixgbe_setup_fc_X550em");
2875
2876         /* Validate the requested mode */
2877         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2878                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2879                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2880                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2881                 goto out;
2882         }
2883
2884         /* 10gig parts do not have a word in the EEPROM to determine the
2885          * default flow control setting, so we explicitly set it to full.
2886          */
2887         if (hw->fc.requested_mode == ixgbe_fc_default)
2888                 hw->fc.requested_mode = ixgbe_fc_full;
2889
2890         /* Determine PAUSE and ASM_DIR bits. */
2891         switch (hw->fc.requested_mode) {
2892         case ixgbe_fc_none:
2893                 pause = 0;
2894                 asm_dir = 0;
2895                 break;
2896         case ixgbe_fc_tx_pause:
2897                 pause = 0;
2898                 asm_dir = 1;
2899                 break;
2900         case ixgbe_fc_rx_pause:
2901                 /* Rx Flow control is enabled and Tx Flow control is
2902                  * disabled by software override. Since there really
2903                  * isn't a way to advertise that we are capable of RX
2904                  * Pause ONLY, we will advertise that we support both
2905                  * symmetric and asymmetric Rx PAUSE, as such we fall
2906                  * through to the fc_full statement.  Later, we will
2907                  * disable the adapter's ability to send PAUSE frames.
2908                  */
2909         case ixgbe_fc_full:
2910                 pause = 1;
2911                 asm_dir = 1;
2912                 break;
2913         default:
2914                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2915                         "Flow control param set incorrectly\n");
2916                 ret_val = IXGBE_ERR_CONFIG;
2917                 goto out;
2918         }
2919
2920         if (hw->phy.media_type == ixgbe_media_type_backplane) {
2921                 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
2922                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2923                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2924                 if (ret_val != IXGBE_SUCCESS)
2925                         goto out;
2926                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2927                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2928                 if (pause)
2929                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2930                 if (asm_dir)
2931                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2932                 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
2933                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2934                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2935
2936                 /* Not all devices fully support AN. */
2937                 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR)
2938                         hw->fc.disable_fc_autoneg = true;
2939         }
2940
2941 out:
2942         return ret_val;
2943 }
2944
2945 /**
2946  * ixgbe_set_mux - Set mux for port 1 access with CS4227
2947  * @hw: pointer to hardware structure
2948  * @state: set mux if 1, clear if 0
2949  */
2950 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2951 {
2952         u32 esdp;
2953
2954         if (!hw->bus.lan_id)
2955                 return;
2956         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2957         if (state)
2958                 esdp |= IXGBE_ESDP_SDP1;
2959         else
2960                 esdp &= ~IXGBE_ESDP_SDP1;
2961         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2962         IXGBE_WRITE_FLUSH(hw);
2963 }
2964
2965 /**
2966  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2967  *  @hw: pointer to hardware structure
2968  *  @mask: Mask to specify which semaphore to acquire
2969  *
2970  *  Acquires the SWFW semaphore and sets the I2C MUX
2971  **/
2972 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2973 {
2974         s32 status;
2975
2976         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
2977
2978         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2979         if (status)
2980                 return status;
2981
2982         if (mask & IXGBE_GSSR_I2C_MASK)
2983                 ixgbe_set_mux(hw, 1);
2984
2985         return IXGBE_SUCCESS;
2986 }
2987
2988 /**
2989  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2990  *  @hw: pointer to hardware structure
2991  *  @mask: Mask to specify which semaphore to release
2992  *
2993  *  Releases the SWFW semaphore and sets the I2C MUX
2994  **/
2995 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2996 {
2997         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
2998
2999         if (mask & IXGBE_GSSR_I2C_MASK)
3000                 ixgbe_set_mux(hw, 0);
3001
3002         ixgbe_release_swfw_sync_X540(hw, mask);
3003 }
3004
3005 /**
3006  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
3007  * @hw: pointer to hardware structure
3008  *
3009  * Handle external Base T PHY interrupt. If high temperature
3010  * failure alarm then return error, else if link status change
3011  * then setup internal/external PHY link
3012  *
3013  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
3014  * failure alarm, else return PHY access status.
3015  */
3016 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
3017 {
3018         bool lsc;
3019         u32 status;
3020
3021         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
3022
3023         if (status != IXGBE_SUCCESS)
3024                 return status;
3025
3026         if (lsc)
3027                 return ixgbe_setup_internal_phy(hw);
3028
3029         return IXGBE_SUCCESS;
3030 }
3031
3032 /**
3033  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
3034  * @hw: pointer to hardware structure
3035  * @speed: new link speed
3036  * @autoneg_wait_to_complete: true when waiting for completion is needed
3037  *
3038  * Setup internal/external PHY link speed based on link speed, then set
3039  * external PHY auto advertised link speed.
3040  *
3041  * Returns error status for any failure
3042  **/
3043 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
3044                                   ixgbe_link_speed speed,
3045                                   bool autoneg_wait_to_complete)
3046 {
3047         s32 status;
3048         ixgbe_link_speed force_speed;
3049
3050         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
3051
3052         /* Setup internal/external PHY link speed to iXFI (10G), unless
3053          * only 1G is auto advertised then setup KX link.
3054          */
3055         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
3056                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3057         else
3058                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3059
3060         /* If internal link mode is XFI, then setup XFI internal link. */
3061         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3062                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
3063
3064                 if (status != IXGBE_SUCCESS)
3065                         return status;
3066         }
3067
3068         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
3069 }
3070
3071 /**
3072  * ixgbe_check_link_t_X550em - Determine link and speed status
3073  * @hw: pointer to hardware structure
3074  * @speed: pointer to link speed
3075  * @link_up: true when link is up
3076  * @link_up_wait_to_complete: bool used to wait for link up or not
3077  *
3078  * Check that both the MAC and X557 external PHY have link.
3079  **/
3080 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3081                               bool *link_up, bool link_up_wait_to_complete)
3082 {
3083         u32 status;
3084         u16 autoneg_status;
3085
3086         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3087                 return IXGBE_ERR_CONFIG;
3088
3089         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
3090                                               link_up_wait_to_complete);
3091
3092         /* If check link fails or MAC link is not up, then return */
3093         if (status != IXGBE_SUCCESS || !(*link_up))
3094                 return status;
3095
3096         /* MAC link is up, so check external PHY link.
3097          * Read this twice back to back to indicate current status.
3098          */
3099         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3100                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3101                                       &autoneg_status);
3102
3103         if (status != IXGBE_SUCCESS)
3104                 return status;
3105
3106         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3107                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3108                                       &autoneg_status);
3109
3110         if (status != IXGBE_SUCCESS)
3111                 return status;
3112
3113         /* If external PHY link is not up, then indicate link not up */
3114         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
3115                 *link_up = false;
3116
3117         return IXGBE_SUCCESS;
3118 }
3119
3120 /**
3121  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
3122  *  @hw: pointer to hardware structure
3123  **/
3124 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
3125 {
3126         s32 status;
3127
3128         status = ixgbe_reset_phy_generic(hw);
3129
3130         if (status != IXGBE_SUCCESS)
3131                 return status;
3132
3133         /* Configure Link Status Alarm and Temperature Threshold interrupts */
3134         return ixgbe_enable_lasi_ext_t_x550em(hw);
3135 }