drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42 static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  43 static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  44
  45 /**
  46  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  47  *  @hw: pointer to hardware structure
  48  *
  49  *  Initialize the function pointers and assign the MAC type for X550.
  50  *  Does not touch the hardware.
  51  **/
  52 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  53 {
  54         struct ixgbe_mac_info *mac = &hw->mac;
  55         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  56         s32 ret_val;
  57
  58         DEBUGFUNC("ixgbe_init_ops_X550");
  59
  60         ret_val = ixgbe_init_ops_X540(hw);
  61         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  62         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  63         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  64         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  65         mac->ops.set_source_address_pruning =
  66                         ixgbe_set_source_address_pruning_X550;
  67         mac->ops.set_ethertype_anti_spoofing =
  68                         ixgbe_set_ethertype_anti_spoofing_X550;
  69
  70         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  71         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  72         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  73         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  74         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  75         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  76         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  77         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  78         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  79
  80         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  81         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  82         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  83         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  84         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  85         switch (hw->device_id) {
  86         case IXGBE_DEV_ID_X550EM_X_10G_T:
  87         case IXGBE_DEV_ID_X550EM_A_10G_T:
  88                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  89                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  90                 break;
  91         default:
  92                 break;
  93         }
  94         return ret_val;
  95 }
  96
  97 /**
  98  * ixgbe_read_cs4227 - Read CS4227 register
  99  * @hw: pointer to hardware structure
 100  * @reg: register number to write
 101  * @value: pointer to receive value read
 102  *
 103  * Returns status code
 104  **/
 105 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
 106 {
 107         return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 108 }
 109
 110 /**
 111  * ixgbe_write_cs4227 - Write CS4227 register
 112  * @hw: pointer to hardware structure
 113  * @reg: register number to write
 114  * @value: value to write to register
 115  *
 116  * Returns status code
 117  **/
 118 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 119 {
 120         return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 121 }
 122
 123 /**
 124  * ixgbe_read_pe - Read register from port expander
 125  * @hw: pointer to hardware structure
 126  * @reg: register number to read
 127  * @value: pointer to receive read value
 128  *
 129  * Returns status code
 130  **/
 131 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 132 {
 133         s32 status;
 134
 135         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 136         if (status != IXGBE_SUCCESS)
 137                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 138                               "port expander access failed with %d\n", status);
 139         return status;
 140 }
 141
 142 /**
 143  * ixgbe_write_pe - Write register to port expander
 144  * @hw: pointer to hardware structure
 145  * @reg: register number to write
 146  * @value: value to write
 147  *
 148  * Returns status code
 149  **/
 150 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 151 {
 152         s32 status;
 153
 154         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 155         if (status != IXGBE_SUCCESS)
 156                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 157                               "port expander access failed with %d\n", status);
 158         return status;
 159 }
 160
 161 /**
 162  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 163  * @hw: pointer to hardware structure
 164  *
 165  * This function assumes that the caller has acquired the proper semaphore.
 166  * Returns error code
 167  **/
 168 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 169 {
 170         s32 status;
 171         u32 retry;
 172         u16 value;
 173         u8 reg;
 174
 175         /* Trigger hard reset. */
 176         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 177         if (status != IXGBE_SUCCESS)
 178                 return status;
 179         reg |= IXGBE_PE_BIT1;
 180         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 181         if (status != IXGBE_SUCCESS)
 182                 return status;
 183
 184         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 185         if (status != IXGBE_SUCCESS)
 186                 return status;
 187         reg &= ~IXGBE_PE_BIT1;
 188         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 189         if (status != IXGBE_SUCCESS)
 190                 return status;
 191
 192         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 193         if (status != IXGBE_SUCCESS)
 194                 return status;
 195         reg &= ~IXGBE_PE_BIT1;
 196         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 197         if (status != IXGBE_SUCCESS)
 198                 return status;
 199
 200         usec_delay(IXGBE_CS4227_RESET_HOLD);
 201
 202         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 203         if (status != IXGBE_SUCCESS)
 204                 return status;
 205         reg |= IXGBE_PE_BIT1;
 206         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 207         if (status != IXGBE_SUCCESS)
 208                 return status;
 209
 210         /* Wait for the reset to complete. */
 211         msec_delay(IXGBE_CS4227_RESET_DELAY);
 212         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 213                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 214                                            &value);
 215                 if (status == IXGBE_SUCCESS &&
 216                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 217                         break;
 218                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 219         }
 220         if (retry == IXGBE_CS4227_RETRIES) {
 221                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 222                         "CS4227 reset did not complete.");
 223                 return IXGBE_ERR_PHY;
 224         }
 225
 226         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 227         if (status != IXGBE_SUCCESS ||
 228             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 229                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 230                         "CS4227 EEPROM did not load successfully.");
 231                 return IXGBE_ERR_PHY;
 232         }
 233
 234         return IXGBE_SUCCESS;
 235 }
 236
 237 /**
 238  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 239  * @hw: pointer to hardware structure
 240  **/
 241 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 242 {
 243         s32 status = IXGBE_SUCCESS;
 244         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 245         u16 value = 0;
 246         u8 retry;
 247
 248         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 249                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 250                 if (status != IXGBE_SUCCESS) {
 251                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 252                                 "semaphore failed with %d", status);
 253                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 254                         continue;
 255                 }
 256
 257                 /* Get status of reset flow. */
 258                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 259
 260                 if (status == IXGBE_SUCCESS &&
 261                     value == IXGBE_CS4227_RESET_COMPLETE)
 262                         goto out;
 263
 264                 if (status != IXGBE_SUCCESS ||
 265                     value != IXGBE_CS4227_RESET_PENDING)
 266                         break;
 267
 268                 /* Reset is pending. Wait and check again. */
 269                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 270                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 271         }
 272
 273         /* If still pending, assume other instance failed. */
 274         if (retry == IXGBE_CS4227_RETRIES) {
 275                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 276                 if (status != IXGBE_SUCCESS) {
 277                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 278                                       "semaphore failed with %d", status);
 279                         return;
 280                 }
 281         }
 282
 283         /* Reset the CS4227. */
 284         status = ixgbe_reset_cs4227(hw);
 285         if (status != IXGBE_SUCCESS) {
 286                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 287                         "CS4227 reset failed: %d", status);
 288                 goto out;
 289         }
 290
 291         /* Reset takes so long, temporarily release semaphore in case the
 292          * other driver instance is waiting for the reset indication.
 293          */
 294         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 295                            IXGBE_CS4227_RESET_PENDING);
 296         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 297         msec_delay(10);
 298         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 299         if (status != IXGBE_SUCCESS) {
 300                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 301                         "semaphore failed with %d", status);
 302                 return;
 303         }
 304
 305         /* Record completion for next time. */
 306         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 307                 IXGBE_CS4227_RESET_COMPLETE);
 308
 309 out:
 310         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 311         msec_delay(hw->eeprom.semaphore_delay);
 312 }
 313
 314 /**
 315  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 316  * @hw: pointer to hardware structure
 317  **/
 318 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 319 {
 320         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 321
 322         if (hw->bus.lan_id) {
 323                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 324                 esdp |= IXGBE_ESDP_SDP1_DIR;
 325         }
 326         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 327         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 328         IXGBE_WRITE_FLUSH(hw);
 329 }
 330
 331 /**
 332  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 333  * @hw: pointer to hardware structure
 334  *
 335  * Returns error code
 336  */
 337 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 338 {
 339         switch (hw->device_id) {
 340         case IXGBE_DEV_ID_X550EM_A_SFP:
 341                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_TOKEN_SM;
 342                 if (hw->bus.lan_id)
 343                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 344                 else
 345                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 346                 return ixgbe_identify_module_generic(hw);
 347         case IXGBE_DEV_ID_X550EM_X_SFP:
 348                 /* set up for CS4227 usage */
 349                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 350                 ixgbe_setup_mux_ctl(hw);
 351                 ixgbe_check_cs4227(hw);
 352                 /* Fallthrough */
 353
 354         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 355                 return ixgbe_identify_module_generic(hw);
 356                 break;
 357         case IXGBE_DEV_ID_X550EM_X_KX4:
 358                 hw->phy.type = ixgbe_phy_x550em_kx4;
 359                 break;
 360         case IXGBE_DEV_ID_X550EM_X_KR:
 361         case IXGBE_DEV_ID_X550EM_A_KR:
 362         case IXGBE_DEV_ID_X550EM_A_KR_L:
 363                 hw->phy.type = ixgbe_phy_x550em_kr;
 364                 break;
 365         case IXGBE_DEV_ID_X550EM_X_1G_T:
 366         case IXGBE_DEV_ID_X550EM_X_10G_T:
 367         case IXGBE_DEV_ID_X550EM_A_1G_T:
 368         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 369         case IXGBE_DEV_ID_X550EM_A_10G_T:
 370                 return ixgbe_identify_phy_generic(hw);
 371         default:
 372                 break;
 373         }
 374         return IXGBE_SUCCESS;
 375 }
 376
 377 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 378                                      u32 device_type, u16 *phy_data)
 379 {
 380         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 381         return IXGBE_NOT_IMPLEMENTED;
 382 }
 383
 384 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 385                                       u32 device_type, u16 phy_data)
 386 {
 387         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 388         return IXGBE_NOT_IMPLEMENTED;
 389 }
 390
 391 /**
 392 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 393 *  @hw: pointer to hardware structure
 394 *
 395 *  Initialize the function pointers and for MAC type X550EM.
 396 *  Does not touch the hardware.
 397 **/
 398 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 399 {
 400         struct ixgbe_mac_info *mac = &hw->mac;
 401         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 402         struct ixgbe_phy_info *phy = &hw->phy;
 403         s32 ret_val;
 404
 405         DEBUGFUNC("ixgbe_init_ops_X550EM");
 406
 407         /* Similar to X550 so start there. */
 408         ret_val = ixgbe_init_ops_X550(hw);
 409
 410         /* Since this function eventually calls
 411          * ixgbe_init_ops_540 by design, we are setting
 412          * the pointers to NULL explicitly here to overwrite
 413          * the values being set in the x540 function.
 414          */
 415         /* Thermal sensor not supported in x550EM */
 416         mac->ops.get_thermal_sensor_data = NULL;
 417         mac->ops.init_thermal_sensor_thresh = NULL;
 418         mac->thermal_sensor_enabled = false;
 419
 420         /* FCOE not supported in x550EM */
 421         mac->ops.get_san_mac_addr = NULL;
 422         mac->ops.set_san_mac_addr = NULL;
 423         mac->ops.get_wwn_prefix = NULL;
 424         mac->ops.get_fcoe_boot_status = NULL;
 425
 426         /* IPsec not supported in x550EM */
 427         mac->ops.disable_sec_rx_path = NULL;
 428         mac->ops.enable_sec_rx_path = NULL;
 429
 430         /* AUTOC register is not present in x550EM. */
 431         mac->ops.prot_autoc_read = NULL;
 432         mac->ops.prot_autoc_write = NULL;
 433
 434         /* X550EM bus type is internal*/
 435         hw->bus.type = ixgbe_bus_type_internal;
 436         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 437
 438         if (hw->mac.type == ixgbe_mac_X550EM_x) {
 439                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 440                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 441                 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 442                 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 443         }
 444         if (hw->mac.type == ixgbe_mac_X550EM_a) {
 445                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
 446                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
 447                 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
 448                 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
 449         }
 450
 451         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 452         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 453         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 454         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 455         mac->ops.get_supported_physical_layer =
 456                                     ixgbe_get_supported_physical_layer_X550em;
 457
 458         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 459                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 460         else
 461                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 462
 463
 464         if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
 465                 mac->ops.setup_eee = NULL;
 466
 467         /* PHY */
 468         phy->ops.init = ixgbe_init_phy_ops_X550em;
 469         phy->ops.identify = ixgbe_identify_phy_x550em;
 470         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 471                 phy->ops.set_phy_power = NULL;
 472
 473
 474         /* EEPROM */
 475         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 476         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 477         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 478         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 479         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 480         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 481         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 482         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 483
 484         return ret_val;
 485 }
 486
 487 /**
 488  *  ixgbe_dmac_config_X550
 489  *  @hw: pointer to hardware structure
 490  *
 491  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 492  *  When disabling dmac, dmac enable dmac bit is cleared.
 493  **/
 494 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 495 {
 496         u32 reg, high_pri_tc;
 497
 498         DEBUGFUNC("ixgbe_dmac_config_X550");
 499
 500         /* Disable DMA coalescing before configuring */
 501         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 502         reg &= ~IXGBE_DMACR_DMAC_EN;
 503         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 504
 505         /* Disable DMA Coalescing if the watchdog timer is 0 */
 506         if (!hw->mac.dmac_config.watchdog_timer)
 507                 goto out;
 508
 509         ixgbe_dmac_config_tcs_X550(hw);
 510
 511         /* Configure DMA Coalescing Control Register */
 512         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 513
 514         /* Set the watchdog timer in units of 40.96 usec */
 515         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 516         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 517
 518         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 519         /* If fcoe is enabled, set high priority traffic class */
 520         if (hw->mac.dmac_config.fcoe_en) {
 521                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 522                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 523                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 524         }
 525         reg |= IXGBE_DMACR_EN_MNG_IND;
 526
 527         /* Enable DMA coalescing after configuration */
 528         reg |= IXGBE_DMACR_DMAC_EN;
 529         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 530
 531 out:
 532         return IXGBE_SUCCESS;
 533 }
 534
 535 /**
 536  *  ixgbe_dmac_config_tcs_X550
 537  *  @hw: pointer to hardware structure
 538  *
 539  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 540  *  be cleared before configuring.
 541  **/
 542 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 543 {
 544         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 545
 546         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 547
 548         /* Configure DMA coalescing enabled */
 549         switch (hw->mac.dmac_config.link_speed) {
 550         case IXGBE_LINK_SPEED_100_FULL:
 551                 pb_headroom = IXGBE_DMACRXT_100M;
 552                 break;
 553         case IXGBE_LINK_SPEED_1GB_FULL:
 554                 pb_headroom = IXGBE_DMACRXT_1G;
 555                 break;
 556         default:
 557                 pb_headroom = IXGBE_DMACRXT_10G;
 558                 break;
 559         }
 560
 561         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 562                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 563
 564         /* Set the per Rx packet buffer receive threshold */
 565         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 566                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 567                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 568
 569                 if (tc < hw->mac.dmac_config.num_tcs) {
 570                         /* Get Rx PB size */
 571                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 572                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 573                                 IXGBE_RXPBSIZE_SHIFT;
 574
 575                         /* Calculate receive buffer threshold in kilobytes */
 576                         if (rx_pb_size > pb_headroom)
 577                                 rx_pb_size = rx_pb_size - pb_headroom;
 578                         else
 579                                 rx_pb_size = 0;
 580
 581                         /* Minimum of MFS shall be set for DMCTH */
 582                         reg |= (rx_pb_size > maxframe_size_kb) ?
 583                                 rx_pb_size : maxframe_size_kb;
 584                 }
 585                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 586         }
 587         return IXGBE_SUCCESS;
 588 }
 589
 590 /**
 591  *  ixgbe_dmac_update_tcs_X550
 592  *  @hw: pointer to hardware structure
 593  *
 594  *  Disables dmac, updates per TC settings, and then enables dmac.
 595  **/
 596 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 597 {
 598         u32 reg;
 599
 600         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 601
 602         /* Disable DMA coalescing before configuring */
 603         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 604         reg &= ~IXGBE_DMACR_DMAC_EN;
 605         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 606
 607         ixgbe_dmac_config_tcs_X550(hw);
 608
 609         /* Enable DMA coalescing after configuration */
 610         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 611         reg |= IXGBE_DMACR_DMAC_EN;
 612         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 613
 614         return IXGBE_SUCCESS;
 615 }
 616
 617 /**
 618  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 619  *  @hw: pointer to hardware structure
 620  *
 621  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 622  *  ixgbe_hw struct in order to set up EEPROM access.
 623  **/
 624 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 625 {
 626         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 627         u32 eec;
 628         u16 eeprom_size;
 629
 630         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 631
 632         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 633                 eeprom->semaphore_delay = 10;
 634                 eeprom->type = ixgbe_flash;
 635
 636                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 637                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 638                                     IXGBE_EEC_SIZE_SHIFT);
 639                 eeprom->word_size = 1 << (eeprom_size +
 640                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 641
 642                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 643                           eeprom->type, eeprom->word_size);
 644         }
 645
 646         return IXGBE_SUCCESS;
 647 }
 648
 649 /**
 650  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 651  *  @hw: pointer to the HW structure
 652  *  @enable_eee: boolean flag to enable EEE
 653  *
 654  *  Enable/disable EEE based on enable_eee flag.
 655  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 656  *  are modified.
 657  *
 658  **/
 659 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 660 {
 661         u32 eeer;
 662         u16 autoneg_eee_reg;
 663         u32 link_reg;
 664         s32 status;
 665
 666         DEBUGFUNC("ixgbe_setup_eee_X550");
 667
 668         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 669         /* Enable or disable EEE per flag */
 670         if (enable_eee) {
 671                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 672
 673                 if (hw->mac.type == ixgbe_mac_X550) {
 674                         /* Advertise EEE capability */
 675                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 676                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 677
 678                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 679                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 680                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 681
 682                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 683                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 684                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 685                         /* Not supported on first revision of X550EM_x. */
 686                         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
 687                             !(IXGBE_FUSES0_REV_MASK &
 688                               IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
 689                                 return IXGBE_SUCCESS;
 690
 691                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 692                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 693                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 694                         if (status != IXGBE_SUCCESS)
 695                                 return status;
 696
 697                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 698                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 699
 700                         /* Don't advertise FEC capability when EEE enabled. */
 701                         link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 702
 703                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 704                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 705                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 706                         if (status != IXGBE_SUCCESS)
 707                                 return status;
 708                 }
 709         } else {
 710                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 711
 712                 if (hw->mac.type == ixgbe_mac_X550) {
 713                         /* Disable advertised EEE capability */
 714                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 715                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 716
 717                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 718                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 719                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 720
 721                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 722                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 723                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 724                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 725                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 726                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 727                         if (status != IXGBE_SUCCESS)
 728                                 return status;
 729
 730                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 731                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 732
 733                         /* Advertise FEC capability when EEE is disabled. */
 734                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 735
 736                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 737                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 738                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 739                         if (status != IXGBE_SUCCESS)
 740                                 return status;
 741                 }
 742         }
 743         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 744
 745         return IXGBE_SUCCESS;
 746 }
 747
 748 /**
 749  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 750  * @hw: pointer to hardware structure
 751  * @enable: enable or disable source address pruning
 752  * @pool: Rx pool to set source address pruning for
 753  **/
 754 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 755                                            unsigned int pool)
 756 {
 757         u64 pfflp;
 758
 759         /* max rx pool is 63 */
 760         if (pool > 63)
 761                 return;
 762
 763         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 764         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 765
 766         if (enable)
 767                 pfflp |= (1ULL << pool);
 768         else
 769                 pfflp &= ~(1ULL << pool);
 770
 771         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 772         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 773 }
 774
 775 /**
 776  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 777  *  @hw: pointer to hardware structure
 778  *  @enable: enable or disable switch for Ethertype anti-spoofing
 779  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 780  *
 781  **/
 782 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 783                 bool enable, int vf)
 784 {
 785         int vf_target_reg = vf >> 3;
 786         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 787         u32 pfvfspoof;
 788
 789         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 790
 791         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 792         if (enable)
 793                 pfvfspoof |= (1 << vf_target_shift);
 794         else
 795                 pfvfspoof &= ~(1 << vf_target_shift);
 796
 797         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 798 }
 799
 800 /**
 801  * ixgbe_iosf_wait - Wait for IOSF command completion
 802  * @hw: pointer to hardware structure
 803  * @ctrl: pointer to location to receive final IOSF control value
 804  *
 805  * Returns failing status on timeout
 806  *
 807  * Note: ctrl can be NULL if the IOSF control register value is not needed
 808  **/
 809 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
 810 {
 811         u32 i, command = 0;
 812
 813         /* Check every 10 usec to see if the address cycle completed.
 814          * The SB IOSF BUSY bit will clear when the operation is
 815          * complete
 816          */
 817         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 818                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 819                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 820                         break;
 821                 usec_delay(10);
 822         }
 823         if (ctrl)
 824                 *ctrl = command;
 825         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 826                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
 827                 return IXGBE_ERR_PHY;
 828         }
 829
 830         return IXGBE_SUCCESS;
 831 }
 832
 833 /**
 834  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 835  *  device
 836  *  @hw: pointer to hardware structure
 837  *  @reg_addr: 32 bit PHY register to write
 838  *  @device_type: 3 bit device type
 839  *  @data: Data to write to the register
 840  **/
 841 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 842                             u32 device_type, u32 data)
 843 {
 844         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 845         u32 command, error;
 846         s32 ret;
 847
 848         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
 849         if (ret != IXGBE_SUCCESS)
 850                 return ret;
 851
 852         ret = ixgbe_iosf_wait(hw, NULL);
 853         if (ret != IXGBE_SUCCESS)
 854                 goto out;
 855
 856         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 857                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 858
 859         /* Write IOSF control register */
 860         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 861
 862         /* Write IOSF data register */
 863         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 864
 865         ret = ixgbe_iosf_wait(hw, &command);
 866
 867         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 868                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 869                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 870                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 871                               "Failed to write, error %x\n", error);
 872                 ret = IXGBE_ERR_PHY;
 873         }
 874
 875 out:
 876         ixgbe_release_swfw_semaphore(hw, gssr);
 877         return ret;
 878 }
 879
 880 /**
 881  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 882  *  device
 883  *  @hw: pointer to hardware structure
 884  *  @reg_addr: 32 bit PHY register to write
 885  *  @device_type: 3 bit device type
 886  *  @phy_data: Pointer to read data from the register
 887  **/
 888 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 889                            u32 device_type, u32 *data)
 890 {
 891         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 892         u32 command, error;
 893         s32 ret;
 894
 895         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
 896         if (ret != IXGBE_SUCCESS)
 897                 return ret;
 898
 899         ret = ixgbe_iosf_wait(hw, NULL);
 900         if (ret != IXGBE_SUCCESS)
 901                 goto out;
 902
 903         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 904                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 905
 906         /* Write IOSF control register */
 907         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 908
 909         ret = ixgbe_iosf_wait(hw, &command);
 910
 911         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 912                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 913                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 914                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 915                                 "Failed to read, error %x\n", error);
 916                 ret = IXGBE_ERR_PHY;
 917         }
 918
 919         if (ret == IXGBE_SUCCESS)
 920                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 921
 922 out:
 923         ixgbe_release_swfw_semaphore(hw, gssr);
 924         return ret;
 925 }
 926
 927 /**
 928  * ixgbe_get_phy_token - Get the token for shared phy access
 929  * @hw: Pointer to hardware structure
 930  */
 931
 932 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
 933 {
 934         struct ixgbe_hic_phy_token_req token_cmd;
 935         s32 status;
 936
 937         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
 938         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
 939         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
 940         token_cmd.port_number = hw->bus.lan_id;
 941         token_cmd.command_type = FW_PHY_TOKEN_REQ;
 942         token_cmd.pad = 0;
 943         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
 944                                               sizeof(token_cmd),
 945                                               IXGBE_HI_COMMAND_TIMEOUT,
 946                                               true);
 947         if (status)
 948                 return status;
 949         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
 950                 return IXGBE_SUCCESS;
 951         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
 952                 return IXGBE_ERR_FW_RESP_INVALID;
 953
 954         return IXGBE_ERR_TOKEN_RETRY;
 955 }
 956
 957 /**
 958  * ixgbe_put_phy_token - Put the token for shared phy access
 959  * @hw: Pointer to hardware structure
 960  */
 961
 962 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
 963 {
 964         struct ixgbe_hic_phy_token_req token_cmd;
 965         s32 status;
 966
 967         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
 968         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
 969         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
 970         token_cmd.port_number = hw->bus.lan_id;
 971         token_cmd.command_type = FW_PHY_TOKEN_REL;
 972         token_cmd.pad = 0;
 973         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
 974                                               sizeof(token_cmd),
 975                                               IXGBE_HI_COMMAND_TIMEOUT,
 976                                               true);
 977         if (status)
 978                 return status;
 979         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
 980                 return IXGBE_SUCCESS;
 981         return IXGBE_ERR_FW_RESP_INVALID;
 982 }
 983
 984 /**
 985  *  ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
 986  *  of the IOSF device
 987  *  @hw: pointer to hardware structure
 988  *  @reg_addr: 32 bit PHY register to write
 989  *  @device_type: 3 bit device type
 990  *  @data: Data to write to the register
 991  **/
 992 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
 993         u32 device_type, u32 data)
 994 {
 995         struct ixgbe_hic_internal_phy_req write_cmd;
 996         s32 status;
 997         UNREFERENCED_1PARAMETER(device_type);
 998
 999         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1000         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1001         write_cmd.port_number = hw->bus.lan_id;
1002         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1003         write_cmd.address = (u16)reg_addr;
1004         write_cmd.rsv1 = 0;
1005         write_cmd.write_data = data;
1006         write_cmd.pad = 0;
1007
1008         status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1009                 sizeof(write_cmd), IXGBE_HI_COMMAND_TIMEOUT, false);
1010
1011         return status;
1012 }
1013
1014 /**
1015  *  ixgbe_read_iosf_sb_reg_x550a - Writes a value to specified register
1016  *  of the IOSF device.
1017  *  @hw: pointer to hardware structure
1018  *  @reg_addr: 32 bit PHY register to write
1019  *  @device_type: 3 bit device type
1020  *  @data: Pointer to read data from the register
1021  **/
1022 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1023         u32 device_type, u32 *data)
1024 {
1025         struct ixgbe_hic_internal_phy_req read_cmd;
1026         s32 status;
1027         UNREFERENCED_1PARAMETER(device_type);
1028
1029         read_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1030         read_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1031         read_cmd.port_number = hw->bus.lan_id;
1032         read_cmd.command_type = FW_INT_PHY_REQ_READ;
1033         read_cmd.address = (u16)reg_addr;
1034         read_cmd.rsv1 = 0;
1035         read_cmd.write_data = 0;
1036         read_cmd.pad = 0;
1037
1038         status = ixgbe_host_interface_command(hw, (u32 *)&read_cmd,
1039                 sizeof(read_cmd), IXGBE_HI_COMMAND_TIMEOUT, true);
1040
1041         /* Extract the register value from the response. */
1042         *data = ((struct ixgbe_hic_internal_phy_resp *)&read_cmd)->read_data;
1043
1044         return status;
1045 }
1046
1047 /**
1048  *  ixgbe_disable_mdd_X550
1049  *  @hw: pointer to hardware structure
1050  *
1051  *  Disable malicious driver detection
1052  **/
1053 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1054 {
1055         u32 reg;
1056
1057         DEBUGFUNC("ixgbe_disable_mdd_X550");
1058
1059         /* Disable MDD for TX DMA and interrupt */
1060         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1061         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1062         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1063
1064         /* Disable MDD for RX and interrupt */
1065         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1066         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1067         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1068 }
1069
1070 /**
1071  *  ixgbe_enable_mdd_X550
1072  *  @hw: pointer to hardware structure
1073  *
1074  *  Enable malicious driver detection
1075  **/
1076 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1077 {
1078         u32 reg;
1079
1080         DEBUGFUNC("ixgbe_enable_mdd_X550");
1081
1082         /* Enable MDD for TX DMA and interrupt */
1083         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1084         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1085         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1086
1087         /* Enable MDD for RX and interrupt */
1088         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1089         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1090         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1091 }
1092
1093 /**
1094  *  ixgbe_restore_mdd_vf_X550
1095  *  @hw: pointer to hardware structure
1096  *  @vf: vf index
1097  *
1098  *  Restore VF that was disabled during malicious driver detection event
1099  **/
1100 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1101 {
1102         u32 idx, reg, num_qs, start_q, bitmask;
1103
1104         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1105
1106         /* Map VF to queues */
1107         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1108         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1109         case IXGBE_MRQC_VMDQRT8TCEN:
1110                 num_qs = 8;  /* 16 VFs / pools */
1111                 bitmask = 0x000000FF;
1112                 break;
1113         case IXGBE_MRQC_VMDQRSS32EN:
1114         case IXGBE_MRQC_VMDQRT4TCEN:
1115                 num_qs = 4;  /* 32 VFs / pools */
1116                 bitmask = 0x0000000F;
1117                 break;
1118         default:            /* 64 VFs / pools */
1119                 num_qs = 2;
1120                 bitmask = 0x00000003;
1121                 break;
1122         }
1123         start_q = vf * num_qs;
1124
1125         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1126         idx = start_q / 32;
1127         reg = 0;
1128         reg |= (bitmask << (start_q % 32));
1129         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1130         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1131 }
1132
1133 /**
1134  *  ixgbe_mdd_event_X550
1135  *  @hw: pointer to hardware structure
1136  *  @vf_bitmap: vf bitmap of malicious vfs
1137  *
1138  *  Handle malicious driver detection event.
1139  **/
1140 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1141 {
1142         u32 wqbr;
1143         u32 i, j, reg, q, shift, vf, idx;
1144
1145         DEBUGFUNC("ixgbe_mdd_event_X550");
1146
1147         /* figure out pool size for mapping to vf's */
1148         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1149         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1150         case IXGBE_MRQC_VMDQRT8TCEN:
1151                 shift = 3;  /* 16 VFs / pools */
1152                 break;
1153         case IXGBE_MRQC_VMDQRSS32EN:
1154         case IXGBE_MRQC_VMDQRT4TCEN:
1155                 shift = 2;  /* 32 VFs / pools */
1156                 break;
1157         default:
1158                 shift = 1;  /* 64 VFs / pools */
1159                 break;
1160         }
1161
1162         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1163         for (i = 0; i < 4; i++) {
1164                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1165                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1166
1167                 if (!wqbr)
1168                         continue;
1169
1170                 /* Get malicious queue */
1171                 for (j = 0; j < 32 && wqbr; j++) {
1172
1173                         if (!(wqbr & (1 << j)))
1174                                 continue;
1175
1176                         /* Get queue from bitmask */
1177                         q = j + (i * 32);
1178
1179                         /* Map queue to vf */
1180                         vf = (q >> shift);
1181
1182                         /* Set vf bit in vf_bitmap */
1183                         idx = vf / 32;
1184                         vf_bitmap[idx] |= (1 << (vf % 32));
1185                         wqbr &= ~(1 << j);
1186                 }
1187         }
1188 }
1189
1190 /**
1191  *  ixgbe_get_media_type_X550em - Get media type
1192  *  @hw: pointer to hardware structure
1193  *
1194  *  Returns the media type (fiber, copper, backplane)
1195  */
1196 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1197 {
1198         enum ixgbe_media_type media_type;
1199
1200         DEBUGFUNC("ixgbe_get_media_type_X550em");
1201
1202         /* Detect if there is a copper PHY attached. */
1203         switch (hw->device_id) {
1204         case IXGBE_DEV_ID_X550EM_X_KR:
1205         case IXGBE_DEV_ID_X550EM_X_KX4:
1206         case IXGBE_DEV_ID_X550EM_A_KR:
1207         case IXGBE_DEV_ID_X550EM_A_KR_L:
1208                 media_type = ixgbe_media_type_backplane;
1209                 break;
1210         case IXGBE_DEV_ID_X550EM_X_SFP:
1211         case IXGBE_DEV_ID_X550EM_A_SFP:
1212         case IXGBE_DEV_ID_X550EM_A_SFP_N:
1213         case IXGBE_DEV_ID_X550EM_A_QSFP:
1214         case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1215                 media_type = ixgbe_media_type_fiber;
1216                 break;
1217         case IXGBE_DEV_ID_X550EM_X_1G_T:
1218         case IXGBE_DEV_ID_X550EM_X_10G_T:
1219         case IXGBE_DEV_ID_X550EM_A_1G_T:
1220         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1221         case IXGBE_DEV_ID_X550EM_A_10G_T:
1222                 media_type = ixgbe_media_type_copper;
1223                 break;
1224         default:
1225                 media_type = ixgbe_media_type_unknown;
1226                 break;
1227         }
1228         return media_type;
1229 }
1230
1231 /**
1232  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1233  *  @hw: pointer to hardware structure
1234  *  @linear: true if SFP module is linear
1235  */
1236 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1237 {
1238         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1239
1240         switch (hw->phy.sfp_type) {
1241         case ixgbe_sfp_type_not_present:
1242                 return IXGBE_ERR_SFP_NOT_PRESENT;
1243         case ixgbe_sfp_type_da_cu_core0:
1244         case ixgbe_sfp_type_da_cu_core1:
1245                 *linear = true;
1246                 break;
1247         case ixgbe_sfp_type_srlr_core0:
1248         case ixgbe_sfp_type_srlr_core1:
1249         case ixgbe_sfp_type_da_act_lmt_core0:
1250         case ixgbe_sfp_type_da_act_lmt_core1:
1251         case ixgbe_sfp_type_1g_sx_core0:
1252         case ixgbe_sfp_type_1g_sx_core1:
1253         case ixgbe_sfp_type_1g_lx_core0:
1254         case ixgbe_sfp_type_1g_lx_core1:
1255                 *linear = false;
1256                 break;
1257         case ixgbe_sfp_type_unknown:
1258         case ixgbe_sfp_type_1g_cu_core0:
1259         case ixgbe_sfp_type_1g_cu_core1:
1260         default:
1261                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1262         }
1263
1264         return IXGBE_SUCCESS;
1265 }
1266
1267 /**
1268  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1269  *  @hw: pointer to hardware structure
1270  *
1271  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1272  **/
1273 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1274 {
1275         s32 status;
1276         bool linear;
1277
1278         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1279
1280         status = ixgbe_identify_module_generic(hw);
1281
1282         if (status != IXGBE_SUCCESS)
1283                 return status;
1284
1285         /* Check if SFP module is supported */
1286         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1287
1288         return status;
1289 }
1290
1291 /**
1292  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1293  *  @hw: pointer to hardware structure
1294  */
1295 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1296 {
1297         s32 status;
1298         bool linear;
1299
1300         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1301
1302         /* Check if SFP module is supported */
1303         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1304
1305         if (status != IXGBE_SUCCESS)
1306                 return status;
1307
1308         ixgbe_init_mac_link_ops_X550em(hw);
1309         hw->phy.ops.reset = NULL;
1310
1311         return IXGBE_SUCCESS;
1312 }
1313
1314 /**
1315  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1316  *  @hw: pointer to hardware structure
1317  */
1318 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1319 {
1320         struct ixgbe_mac_info *mac = &hw->mac;
1321
1322         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1323
1324          switch (hw->mac.ops.get_media_type(hw)) {
1325          case ixgbe_media_type_fiber:
1326                 /* CS4227 does not support autoneg, so disable the laser control
1327                  * functions for SFP+ fiber
1328                  */
1329                 mac->ops.disable_tx_laser = NULL;
1330                 mac->ops.enable_tx_laser = NULL;
1331                 mac->ops.flap_tx_laser = NULL;
1332                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1333                 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1334                 mac->ops.set_rate_select_speed =
1335                                         ixgbe_set_soft_rate_select_speed;
1336                 break;
1337         case ixgbe_media_type_copper:
1338                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1339                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1340                 break;
1341         default:
1342                 break;
1343          }
1344 }
1345
1346 /**
1347  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1348  *  @hw: pointer to hardware structure
1349  *  @speed: pointer to link speed
1350  *  @autoneg: true when autoneg or autotry is enabled
1351  */
1352 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1353                                        ixgbe_link_speed *speed,
1354                                        bool *autoneg)
1355 {
1356         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1357
1358         /* SFP */
1359         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1360
1361                 /* CS4227 SFP must not enable auto-negotiation */
1362                 *autoneg = false;
1363
1364                 /* Check if 1G SFP module. */
1365                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1366                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1367                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1368                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1369                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1370                         return IXGBE_SUCCESS;
1371                 }
1372
1373                 /* Link capabilities are based on SFP */
1374                 if (hw->phy.multispeed_fiber)
1375                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1376                                  IXGBE_LINK_SPEED_1GB_FULL;
1377                 else
1378                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1379         } else {
1380                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1381                          IXGBE_LINK_SPEED_1GB_FULL;
1382                 *autoneg = true;
1383         }
1384
1385         return IXGBE_SUCCESS;
1386 }
1387
1388 /**
1389  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1390  * @hw: pointer to hardware structure
1391  * @lsc: pointer to boolean flag which indicates whether external Base T
1392  *       PHY interrupt is lsc
1393  *
1394  * Determime if external Base T PHY interrupt cause is high temperature
1395  * failure alarm or link status change.
1396  *
1397  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1398  * failure alarm, else return PHY access status.
1399  */
1400 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1401 {
1402         u32 status;
1403         u16 reg;
1404
1405         *lsc = false;
1406
1407         /* Vendor alarm triggered */
1408         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1409                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1410                                       &reg);
1411
1412         if (status != IXGBE_SUCCESS ||
1413             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1414                 return status;
1415
1416         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1417         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1418                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1419                                       &reg);
1420
1421         if (status != IXGBE_SUCCESS ||
1422             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1423             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1424                 return status;
1425
1426         /* Global alarm triggered */
1427         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1428                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1429                                       &reg);
1430
1431         if (status != IXGBE_SUCCESS)
1432                 return status;
1433
1434         /* If high temperature failure, then return over temp error and exit */
1435         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1436                 /* power down the PHY in case the PHY FW didn't already */
1437                 ixgbe_set_copper_phy_power(hw, false);
1438                 return IXGBE_ERR_OVERTEMP;
1439         } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1440                 /*  device fault alarm triggered */
1441                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1442                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1443                                           &reg);
1444
1445                 if (status != IXGBE_SUCCESS)
1446                         return status;
1447
1448                 /* if device fault was due to high temp alarm handle and exit */
1449                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1450                         /* power down the PHY in case the PHY FW didn't */
1451                         ixgbe_set_copper_phy_power(hw, false);
1452                         return IXGBE_ERR_OVERTEMP;
1453                 }
1454         }
1455
1456         /* Vendor alarm 2 triggered */
1457         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1458                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1459
1460         if (status != IXGBE_SUCCESS ||
1461             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1462                 return status;
1463
1464         /* link connect/disconnect event occurred */
1465         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1466                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1467
1468         if (status != IXGBE_SUCCESS)
1469                 return status;
1470
1471         /* Indicate LSC */
1472         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1473                 *lsc = true;
1474
1475         return IXGBE_SUCCESS;
1476 }
1477
1478 /**
1479  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1480  * @hw: pointer to hardware structure
1481  *
1482  * Enable link status change and temperature failure alarm for the external
1483  * Base T PHY
1484  *
1485  * Returns PHY access status
1486  */
1487 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1488 {
1489         u32 status;
1490         u16 reg;
1491         bool lsc;
1492
1493         /* Clear interrupt flags */
1494         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1495
1496         /* Enable link status change alarm */
1497         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1498                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1499
1500         if (status != IXGBE_SUCCESS)
1501                 return status;
1502
1503         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1504
1505         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1506                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1507
1508         if (status != IXGBE_SUCCESS)
1509                 return status;
1510
1511         /* Enable high temperature failure and global fault alarms */
1512         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1513                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1514                                       &reg);
1515
1516         if (status != IXGBE_SUCCESS)
1517                 return status;
1518
1519         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
1520                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
1521
1522         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1523                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1524                                        reg);
1525
1526         if (status != IXGBE_SUCCESS)
1527                 return status;
1528
1529         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1530         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1531                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1532                                       &reg);
1533
1534         if (status != IXGBE_SUCCESS)
1535                 return status;
1536
1537         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1538                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1539
1540         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1541                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1542                                        reg);
1543
1544         if (status != IXGBE_SUCCESS)
1545                 return status;
1546
1547         /* Enable chip-wide vendor alarm */
1548         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1549                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1550                                       &reg);
1551
1552         if (status != IXGBE_SUCCESS)
1553                 return status;
1554
1555         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1556
1557         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1558                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1559                                        reg);
1560
1561         return status;
1562 }
1563
1564 /**
1565  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1566  *  @hw: pointer to hardware structure
1567  *  @speed: link speed
1568  *
1569  *  Configures the integrated KR PHY.
1570  **/
1571 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1572                                        ixgbe_link_speed speed)
1573 {
1574         s32 status;
1575         u32 reg_val;
1576
1577         status = ixgbe_read_iosf_sb_reg_x550(hw,
1578                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1579                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1580         if (status)
1581                 return status;
1582
1583         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1584         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1585                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1586
1587         /* Advertise 10G support. */
1588         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1589                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1590
1591         /* Advertise 1G support. */
1592         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1593                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1594
1595         /* Restart auto-negotiation. */
1596         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1597         status = ixgbe_write_iosf_sb_reg_x550(hw,
1598                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1599                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1600
1601         return status;
1602 }
1603
1604 /**
1605  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1606  *  @hw: pointer to hardware structure
1607  *
1608  *  Initialize any function pointers that were not able to be
1609  *  set during init_shared_code because the PHY/SFP type was
1610  *  not known.  Perform the SFP init if necessary.
1611  */
1612 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1613 {
1614         struct ixgbe_phy_info *phy = &hw->phy;
1615         s32 ret_val;
1616
1617         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1618
1619         hw->mac.ops.set_lan_id(hw);
1620
1621         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1622                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1623                 ixgbe_setup_mux_ctl(hw);
1624
1625                 /* Save NW management interface connected on board. This is used
1626                  * to determine internal PHY mode.
1627                  */
1628                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1629                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
1630         }
1631
1632         /* Identify the PHY or SFP module */
1633         ret_val = phy->ops.identify(hw);
1634         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1635                 return ret_val;
1636
1637         /* Setup function pointers based on detected hardware */
1638         ixgbe_init_mac_link_ops_X550em(hw);
1639         if (phy->sfp_type != ixgbe_sfp_type_unknown)
1640                 phy->ops.reset = NULL;
1641
1642         /* Set functions pointers based on phy type */
1643         switch (hw->phy.type) {
1644         case ixgbe_phy_x550em_kx4:
1645                 phy->ops.setup_link = NULL;
1646                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1647                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1648                 break;
1649         case ixgbe_phy_x550em_kr:
1650                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1651                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1652                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1653                 break;
1654         case ixgbe_phy_x550em_ext_t:
1655                 /* Save NW management interface connected on board. This is used
1656                  * to determine internal PHY mode
1657                  */
1658                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1659
1660                 /* If internal link mode is XFI, then setup iXFI internal link,
1661                  * else setup KR now.
1662                  */
1663                 phy->ops.setup_internal_link =
1664                                               ixgbe_setup_internal_phy_t_x550em;
1665
1666                 /* setup SW LPLU only for first revision of X550EM_x */
1667                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
1668                     !(IXGBE_FUSES0_REV_MASK &
1669                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
1670                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1671
1672                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1673                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1674                 break;
1675         default:
1676                 break;
1677         }
1678         return ret_val;
1679 }
1680
1681 /**
1682  * ixgbe_set_mdio_speed - Set MDIO clock speed
1683  *  @hw: pointer to hardware structure
1684  */
1685 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
1686 {
1687         u32 hlreg0;
1688
1689         switch (hw->device_id) {
1690         case IXGBE_DEV_ID_X550EM_X_10G_T:
1691         case IXGBE_DEV_ID_X550EM_A_1G_T:
1692         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1693         case IXGBE_DEV_ID_X550EM_A_10G_T:
1694         case IXGBE_DEV_ID_X550EM_A_SFP:
1695         case IXGBE_DEV_ID_X550EM_A_QSFP:
1696                 /* Config MDIO clock speed before the first MDIO PHY access */
1697                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1698                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
1699                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1700                 break;
1701         default:
1702                 break;
1703         }
1704 }
1705
1706 /**
1707  *  ixgbe_reset_hw_X550em - Perform hardware reset
1708  *  @hw: pointer to hardware structure
1709  *
1710  *  Resets the hardware by resetting the transmit and receive units, masks
1711  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1712  *  reset.
1713  */
1714 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1715 {
1716         ixgbe_link_speed link_speed;
1717         s32 status;
1718         u32 ctrl = 0;
1719         u32 i;
1720         bool link_up = false;
1721
1722         DEBUGFUNC("ixgbe_reset_hw_X550em");
1723
1724         /* Call adapter stop to disable Tx/Rx and clear interrupts */
1725         status = hw->mac.ops.stop_adapter(hw);
1726         if (status != IXGBE_SUCCESS)
1727                 return status;
1728
1729         /* flush pending Tx transactions */
1730         ixgbe_clear_tx_pending(hw);
1731
1732         ixgbe_set_mdio_speed(hw);
1733
1734         /* PHY ops must be identified and initialized prior to reset */
1735         status = hw->phy.ops.init(hw);
1736
1737         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1738                 return status;
1739
1740         /* start the external PHY */
1741         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1742                 status = ixgbe_init_ext_t_x550em(hw);
1743                 if (status)
1744                         return status;
1745         }
1746
1747         /* Setup SFP module if there is one present. */
1748         if (hw->phy.sfp_setup_needed) {
1749                 status = hw->mac.ops.setup_sfp(hw);
1750                 hw->phy.sfp_setup_needed = false;
1751         }
1752
1753         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1754                 return status;
1755
1756         /* Reset PHY */
1757         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1758                 hw->phy.ops.reset(hw);
1759
1760 mac_reset_top:
1761         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1762          * If link reset is used when link is up, it might reset the PHY when
1763          * mng is using it.  If link is down or the flag to force full link
1764          * reset is set, then perform link reset.
1765          */
1766         ctrl = IXGBE_CTRL_LNK_RST;
1767         if (!hw->force_full_reset) {
1768                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1769                 if (link_up)
1770                         ctrl = IXGBE_CTRL_RST;
1771         }
1772
1773         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1774         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1775         IXGBE_WRITE_FLUSH(hw);
1776
1777         /* Poll for reset bit to self-clear meaning reset is complete */
1778         for (i = 0; i < 10; i++) {
1779                 usec_delay(1);
1780                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1781                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1782                         break;
1783         }
1784
1785         if (ctrl & IXGBE_CTRL_RST_MASK) {
1786                 status = IXGBE_ERR_RESET_FAILED;
1787                 DEBUGOUT("Reset polling failed to complete.\n");
1788         }
1789
1790         msec_delay(50);
1791
1792         /* Double resets are required for recovery from certain error
1793          * conditions.  Between resets, it is necessary to stall to
1794          * allow time for any pending HW events to complete.
1795          */
1796         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1797                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1798                 goto mac_reset_top;
1799         }
1800
1801         /* Store the permanent mac address */
1802         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1803
1804         /* Store MAC address from RAR0, clear receive address registers, and
1805          * clear the multicast table.  Also reset num_rar_entries to 128,
1806          * since we modify this value when programming the SAN MAC address.
1807          */
1808         hw->mac.num_rar_entries = 128;
1809         hw->mac.ops.init_rx_addrs(hw);
1810
1811         ixgbe_set_mdio_speed(hw);
1812
1813         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1814                 ixgbe_setup_mux_ctl(hw);
1815
1816         return status;
1817 }
1818
1819 /**
1820  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1821  * @hw: pointer to hardware structure
1822  */
1823 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1824 {
1825         u32 status;
1826         u16 reg;
1827
1828         status = hw->phy.ops.read_reg(hw,
1829                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1830                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1831                                       &reg);
1832
1833         if (status != IXGBE_SUCCESS)
1834                 return status;
1835
1836         /* If PHY FW reset completed bit is set then this is the first
1837          * SW instance after a power on so the PHY FW must be un-stalled.
1838          */
1839         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1840                 status = hw->phy.ops.read_reg(hw,
1841                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1842                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1843                                         &reg);
1844
1845                 if (status != IXGBE_SUCCESS)
1846                         return status;
1847
1848                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1849
1850                 status = hw->phy.ops.write_reg(hw,
1851                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1852                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1853                                         reg);
1854
1855                 if (status != IXGBE_SUCCESS)
1856                         return status;
1857         }
1858
1859         return status;
1860 }
1861
1862 /**
1863  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1864  *  @hw: pointer to hardware structure
1865  *
1866  *  Configures the integrated KR PHY.
1867  **/
1868 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1869 {
1870         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
1871 }
1872
1873 /**
1874  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
1875  *  @hw: pointer to hardware structure
1876  *
1877  *  Configure the external PHY and the integrated KR PHY for SFP support.
1878  **/
1879 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1880                                     ixgbe_link_speed speed,
1881                                     bool autoneg_wait_to_complete)
1882 {
1883         s32 ret_val;
1884         u16 reg_slice, reg_val;
1885         bool setup_linear = false;
1886         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1887
1888         /* Check if SFP module is supported and linear */
1889         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1890
1891         /* If no SFP module present, then return success. Return success since
1892          * there is no reason to configure CS4227 and SFP not present error is
1893          * not excepted in the setup MAC link flow.
1894          */
1895         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1896                 return IXGBE_SUCCESS;
1897
1898         if (ret_val != IXGBE_SUCCESS)
1899                 return ret_val;
1900
1901         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1902                 /* Configure CS4227 LINE side to 10G SR. */
1903                 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
1904                             (hw->bus.lan_id << 12);
1905                 reg_val = IXGBE_CS4227_SPEED_10G;
1906                 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1907                                                    reg_val);
1908
1909                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
1910                             (hw->bus.lan_id << 12);
1911                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1912                 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1913                                                    reg_val);
1914
1915                 /* Configure CS4227 for HOST connection rate then type. */
1916                 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
1917                             (hw->bus.lan_id << 12);
1918                 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
1919                 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
1920                 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1921                                                    reg_val);
1922
1923                 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
1924                             (hw->bus.lan_id << 12);
1925                 if (setup_linear)
1926                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1927                 else
1928                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1929                 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1930                                                    reg_val);
1931
1932                 /* Setup XFI internal link. */
1933                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
1934         } else {
1935                 /* Configure internal PHY for KR/KX. */
1936                 ixgbe_setup_kr_speed_x550em(hw, speed);
1937
1938                 /* Configure CS4227 LINE side to proper mode. */
1939                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
1940                             (hw->bus.lan_id << 12);
1941                 if (setup_linear)
1942                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1943                 else
1944                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1945                 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1946                                                    reg_val);
1947         }
1948         return ret_val;
1949 }
1950
1951 /**
1952  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
1953  *  @hw: pointer to hardware structure
1954  *
1955  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
1956  **/
1957 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
1958 {
1959         s32 status;
1960         u32 reg_val;
1961
1962         /* Disable training protocol FSM. */
1963         status = ixgbe_read_iosf_sb_reg_x550(hw,
1964                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1965                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1966         if (status != IXGBE_SUCCESS)
1967                 return status;
1968         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1969         status = ixgbe_write_iosf_sb_reg_x550(hw,
1970                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1971                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1972         if (status != IXGBE_SUCCESS)
1973                 return status;
1974
1975         /* Disable Flex from training TXFFE. */
1976         status = ixgbe_read_iosf_sb_reg_x550(hw,
1977                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1978                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1979         if (status != IXGBE_SUCCESS)
1980                 return status;
1981         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1982         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1983         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1984         status = ixgbe_write_iosf_sb_reg_x550(hw,
1985                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1986                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1987         if (status != IXGBE_SUCCESS)
1988                 return status;
1989         status = ixgbe_read_iosf_sb_reg_x550(hw,
1990                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1991                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1992         if (status != IXGBE_SUCCESS)
1993                 return status;
1994         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1995         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1996         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1997         status = ixgbe_write_iosf_sb_reg_x550(hw,
1998                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1999                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2000         if (status != IXGBE_SUCCESS)
2001                 return status;
2002
2003         /* Enable override for coefficients. */
2004         status = ixgbe_read_iosf_sb_reg_x550(hw,
2005                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2006                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2007         if (status != IXGBE_SUCCESS)
2008                 return status;
2009         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2010         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2011         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2012         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2013         status = ixgbe_write_iosf_sb_reg_x550(hw,
2014                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2015                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2016         return status;
2017 }
2018
2019 /**
2020  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2021  *  @hw: pointer to hardware structure
2022  *  @speed: the link speed to force
2023  *
2024  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
2025  *  internal and external PHY at a specific speed, without autonegotiation.
2026  **/
2027 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2028 {
2029         s32 status;
2030         u32 reg_val;
2031
2032         /* Disable AN and force speed to 10G Serial. */
2033         status = ixgbe_read_iosf_sb_reg_x550(hw,
2034                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2035                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2036         if (status != IXGBE_SUCCESS)
2037                 return status;
2038
2039         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2040         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2041
2042         /* Select forced link speed for internal PHY. */
2043         switch (*speed) {
2044         case IXGBE_LINK_SPEED_10GB_FULL:
2045                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2046                 break;
2047         case IXGBE_LINK_SPEED_1GB_FULL:
2048                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2049                 break;
2050         default:
2051                 /* Other link speeds are not supported by internal KR PHY. */
2052                 return IXGBE_ERR_LINK_SETUP;
2053         }
2054
2055         status = ixgbe_write_iosf_sb_reg_x550(hw,
2056                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2057                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2058         if (status != IXGBE_SUCCESS)
2059                 return status;
2060
2061         /* Additional configuration needed for x550em_x */
2062         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2063                 status = ixgbe_setup_ixfi_x550em_x(hw);
2064                 if (status != IXGBE_SUCCESS)
2065                         return status;
2066         }
2067
2068         /* Toggle port SW reset by AN reset. */
2069         status = ixgbe_read_iosf_sb_reg_x550(hw,
2070                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2071                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2072         if (status != IXGBE_SUCCESS)
2073                 return status;
2074         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2075         status = ixgbe_write_iosf_sb_reg_x550(hw,
2076                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2077                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2078
2079         return status;
2080 }
2081
2082 /**
2083  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2084  * @hw: address of hardware structure
2085  * @link_up: address of boolean to indicate link status
2086  *
2087  * Returns error code if unable to get link status.
2088  */
2089 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2090 {
2091         u32 ret;
2092         u16 autoneg_status;
2093
2094         *link_up = false;
2095
2096         /* read this twice back to back to indicate current status */
2097         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2098                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2099                                    &autoneg_status);
2100         if (ret != IXGBE_SUCCESS)
2101                 return ret;
2102
2103         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2104                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2105                                    &autoneg_status);
2106         if (ret != IXGBE_SUCCESS)
2107                 return ret;
2108
2109         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2110
2111         return IXGBE_SUCCESS;
2112 }
2113
2114 /**
2115  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2116  * @hw: point to hardware structure
2117  *
2118  * Configures the link between the integrated KR PHY and the external X557 PHY
2119  * The driver will call this function when it gets a link status change
2120  * interrupt from the X557 PHY. This function configures the link speed
2121  * between the PHYs to match the link speed of the BASE-T link.
2122  *
2123  * A return of a non-zero value indicates an error, and the base driver should
2124  * not report link up.
2125  */
2126 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2127 {
2128         ixgbe_link_speed force_speed;
2129         bool link_up;
2130         u32 status;
2131         u16 speed;
2132
2133         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2134                 return IXGBE_ERR_CONFIG;
2135
2136         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2137                 /* If link is down, there is no setup necessary so return  */
2138                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2139                 if (status != IXGBE_SUCCESS)
2140                         return status;
2141
2142                 if (!link_up)
2143                         return IXGBE_SUCCESS;
2144
2145                 status = hw->phy.ops.read_reg(hw,
2146                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2147                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2148                                               &speed);
2149                 if (status != IXGBE_SUCCESS)
2150                         return status;
2151
2152                 /* If link is still down - no setup is required so return */
2153                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2154                 if (status != IXGBE_SUCCESS)
2155                         return status;
2156                 if (!link_up)
2157                         return IXGBE_SUCCESS;
2158
2159                 /* clear everything but the speed and duplex bits */
2160                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2161
2162                 switch (speed) {
2163                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2164                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2165                         break;
2166                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2167                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2168                         break;
2169                 default:
2170                         /* Internal PHY does not support anything else */
2171                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
2172                 }
2173
2174                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2175         } else {
2176                 speed = IXGBE_LINK_SPEED_10GB_FULL |
2177                         IXGBE_LINK_SPEED_1GB_FULL;
2178                 return ixgbe_setup_kr_speed_x550em(hw, speed);
2179         }
2180 }
2181
2182 /**
2183  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
2184  *  @hw: pointer to hardware structure
2185  *
2186  *  Configures the integrated KR PHY to use internal loopback mode.
2187  **/
2188 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
2189 {
2190         s32 status;
2191         u32 reg_val;
2192
2193         /* Disable AN and force speed to 10G Serial. */
2194         status = ixgbe_read_iosf_sb_reg_x550(hw,
2195                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2196                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2197         if (status != IXGBE_SUCCESS)
2198                 return status;
2199         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2200         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2201         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2202         status = ixgbe_write_iosf_sb_reg_x550(hw,
2203                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2204                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2205         if (status != IXGBE_SUCCESS)
2206                 return status;
2207
2208         /* Set near-end loopback clocks. */
2209         status = ixgbe_read_iosf_sb_reg_x550(hw,
2210                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2211                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2212         if (status != IXGBE_SUCCESS)
2213                 return status;
2214         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2215         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2216         status = ixgbe_write_iosf_sb_reg_x550(hw,
2217                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2218                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2219         if (status != IXGBE_SUCCESS)
2220                 return status;
2221
2222         /* Set loopback enable. */
2223         status = ixgbe_read_iosf_sb_reg_x550(hw,
2224                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2225                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2226         if (status != IXGBE_SUCCESS)
2227                 return status;
2228         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2229         status = ixgbe_write_iosf_sb_reg_x550(hw,
2230                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2231                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2232         if (status != IXGBE_SUCCESS)
2233                 return status;
2234
2235         /* Training bypass. */
2236         status = ixgbe_read_iosf_sb_reg_x550(hw,
2237                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2238                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2239         if (status != IXGBE_SUCCESS)
2240                 return status;
2241         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2242         status = ixgbe_write_iosf_sb_reg_x550(hw,
2243                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2244                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2245
2246         return status;
2247 }
2248
2249 /**
2250  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2251  *  assuming that the semaphore is already obtained.
2252  *  @hw: pointer to hardware structure
2253  *  @offset: offset of  word in the EEPROM to read
2254  *  @data: word read from the EEPROM
2255  *
2256  *  Reads a 16 bit word from the EEPROM using the hostif.
2257  **/
2258 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2259                                    u16 *data)
2260 {
2261         s32 status;
2262         struct ixgbe_hic_read_shadow_ram buffer;
2263
2264         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2265         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2266         buffer.hdr.req.buf_lenh = 0;
2267         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2268         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2269
2270         /* convert offset from words to bytes */
2271         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2272         /* one word */
2273         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2274
2275         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2276                                               sizeof(buffer),
2277                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2278
2279         if (status)
2280                 return status;
2281
2282         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2283                                           FW_NVM_DATA_OFFSET);
2284
2285         return 0;
2286 }
2287
2288 /**
2289  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2290  *  @hw: pointer to hardware structure
2291  *  @offset: offset of  word in the EEPROM to read
2292  *  @data: word read from the EEPROM
2293  *
2294  *  Reads a 16 bit word from the EEPROM using the hostif.
2295  **/
2296 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2297                               u16 *data)
2298 {
2299         s32 status = IXGBE_SUCCESS;
2300
2301         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2302
2303         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2304             IXGBE_SUCCESS) {
2305                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2306                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2307         } else {
2308                 status = IXGBE_ERR_SWFW_SYNC;
2309         }
2310
2311         return status;
2312 }
2313
2314 /**
2315  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2316  *  @hw: pointer to hardware structure
2317  *  @offset: offset of  word in the EEPROM to read
2318  *  @words: number of words
2319  *  @data: word(s) read from the EEPROM
2320  *
2321  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
2322  **/
2323 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2324                                      u16 offset, u16 words, u16 *data)
2325 {
2326         struct ixgbe_hic_read_shadow_ram buffer;
2327         u32 current_word = 0;
2328         u16 words_to_read;
2329         s32 status;
2330         u32 i;
2331
2332         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2333
2334         /* Take semaphore for the entire operation. */
2335         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2336         if (status) {
2337                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2338                 return status;
2339         }
2340         while (words) {
2341                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2342                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2343                 else
2344                         words_to_read = words;
2345
2346                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2347                 buffer.hdr.req.buf_lenh = 0;
2348                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2349                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2350
2351                 /* convert offset from words to bytes */
2352                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2353                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2354
2355                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2356                                                       sizeof(buffer),
2357                                                       IXGBE_HI_COMMAND_TIMEOUT,
2358                                                       false);
2359
2360                 if (status) {
2361                         DEBUGOUT("Host interface command failed\n");
2362                         goto out;
2363                 }
2364
2365                 for (i = 0; i < words_to_read; i++) {
2366                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
2367                                   2 * i;
2368                         u32 value = IXGBE_READ_REG(hw, reg);
2369
2370                         data[current_word] = (u16)(value & 0xffff);
2371                         current_word++;
2372                         i++;
2373                         if (i < words_to_read) {
2374                                 value >>= 16;
2375                                 data[current_word] = (u16)(value & 0xffff);
2376                                 current_word++;
2377                         }
2378                 }
2379                 words -= words_to_read;
2380         }
2381
2382 out:
2383         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2384         return status;
2385 }
2386
2387 /**
2388  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2389  *  @hw: pointer to hardware structure
2390  *  @offset: offset of  word in the EEPROM to write
2391  *  @data: word write to the EEPROM
2392  *
2393  *  Write a 16 bit word to the EEPROM using the hostif.
2394  **/
2395 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2396                                     u16 data)
2397 {
2398         s32 status;
2399         struct ixgbe_hic_write_shadow_ram buffer;
2400
2401         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
2402
2403         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
2404         buffer.hdr.req.buf_lenh = 0;
2405         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
2406         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2407
2408          /* one word */
2409         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2410         buffer.data = data;
2411         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2412
2413         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2414                                               sizeof(buffer),
2415                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2416
2417         return status;
2418 }
2419
2420 /**
2421  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2422  *  @hw: pointer to hardware structure
2423  *  @offset: offset of  word in the EEPROM to write
2424  *  @data: word write to the EEPROM
2425  *
2426  *  Write a 16 bit word to the EEPROM using the hostif.
2427  **/
2428 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2429                                u16 data)
2430 {
2431         s32 status = IXGBE_SUCCESS;
2432
2433         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2434
2435         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2436             IXGBE_SUCCESS) {
2437                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2438                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2439         } else {
2440                 DEBUGOUT("write ee hostif failed to get semaphore");
2441                 status = IXGBE_ERR_SWFW_SYNC;
2442         }
2443
2444         return status;
2445 }
2446
2447 /**
2448  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2449  *  @hw: pointer to hardware structure
2450  *  @offset: offset of  word in the EEPROM to write
2451  *  @words: number of words
2452  *  @data: word(s) write to the EEPROM
2453  *
2454  *  Write a 16 bit word(s) to the EEPROM using the hostif.
2455  **/
2456 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2457                                       u16 offset, u16 words, u16 *data)
2458 {
2459         s32 status = IXGBE_SUCCESS;
2460         u32 i = 0;
2461
2462         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2463
2464         /* Take semaphore for the entire operation. */
2465         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2466         if (status != IXGBE_SUCCESS) {
2467                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2468                 goto out;
2469         }
2470
2471         for (i = 0; i < words; i++) {
2472                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2473                                                          data[i]);
2474
2475                 if (status != IXGBE_SUCCESS) {
2476                         DEBUGOUT("Eeprom buffered write failed\n");
2477                         break;
2478                 }
2479         }
2480
2481         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2482 out:
2483
2484         return status;
2485 }
2486
2487 /**
2488  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2489  * @hw: pointer to hardware structure
2490  * @ptr: pointer offset in eeprom
2491  * @size: size of section pointed by ptr, if 0 first word will be used as size
2492  * @csum: address of checksum to update
2493  *
2494  * Returns error status for any failure
2495  */
2496 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2497                                    u16 size, u16 *csum, u16 *buffer,
2498                                    u32 buffer_size)
2499 {
2500         u16 buf[256];
2501         s32 status;
2502         u16 length, bufsz, i, start;
2503         u16 *local_buffer;
2504
2505         bufsz = sizeof(buf) / sizeof(buf[0]);
2506
2507         /* Read a chunk at the pointer location */
2508         if (!buffer) {
2509                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2510                 if (status) {
2511                         DEBUGOUT("Failed to read EEPROM image\n");
2512                         return status;
2513                 }
2514                 local_buffer = buf;
2515         } else {
2516                 if (buffer_size < ptr)
2517                         return  IXGBE_ERR_PARAM;
2518                 local_buffer = &buffer[ptr];
2519         }
2520
2521         if (size) {
2522                 start = 0;
2523                 length = size;
2524         } else {
2525                 start = 1;
2526                 length = local_buffer[0];
2527
2528                 /* Skip pointer section if length is invalid. */
2529                 if (length == 0xFFFF || length == 0 ||
2530                     (ptr + length) >= hw->eeprom.word_size)
2531                         return IXGBE_SUCCESS;
2532         }
2533
2534         if (buffer && ((u32)start + (u32)length > buffer_size))
2535                 return IXGBE_ERR_PARAM;
2536
2537         for (i = start; length; i++, length--) {
2538                 if (i == bufsz && !buffer) {
2539                         ptr += bufsz;
2540                         i = 0;
2541                         if (length < bufsz)
2542                                 bufsz = length;
2543
2544                         /* Read a chunk at the pointer location */
2545                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2546                                                                   bufsz, buf);
2547                         if (status) {
2548                                 DEBUGOUT("Failed to read EEPROM image\n");
2549                                 return status;
2550                         }
2551                 }
2552                 *csum += local_buffer[i];
2553         }
2554         return IXGBE_SUCCESS;
2555 }
2556
2557 /**
2558  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2559  *  @hw: pointer to hardware structure
2560  *  @buffer: pointer to buffer containing calculated checksum
2561  *  @buffer_size: size of buffer
2562  *
2563  *  Returns a negative error code on error, or the 16-bit checksum
2564  **/
2565 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2566 {
2567         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2568         u16 *local_buffer;
2569         s32 status;
2570         u16 checksum = 0;
2571         u16 pointer, i, size;
2572
2573         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2574
2575         hw->eeprom.ops.init_params(hw);
2576
2577         if (!buffer) {
2578                 /* Read pointer area */
2579                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2580                                                      IXGBE_EEPROM_LAST_WORD + 1,
2581                                                      eeprom_ptrs);
2582                 if (status) {
2583                         DEBUGOUT("Failed to read EEPROM image\n");
2584                         return status;
2585                 }
2586                 local_buffer = eeprom_ptrs;
2587         } else {
2588                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2589                         return IXGBE_ERR_PARAM;
2590                 local_buffer = buffer;
2591         }
2592
2593         /*
2594          * For X550 hardware include 0x0-0x41 in the checksum, skip the
2595          * checksum word itself
2596          */
2597         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2598                 if (i != IXGBE_EEPROM_CHECKSUM)
2599                         checksum += local_buffer[i];
2600
2601         /*
2602          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
2603          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2604          */
2605         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2606                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2607                         continue;
2608
2609                 pointer = local_buffer[i];
2610
2611                 /* Skip pointer section if the pointer is invalid. */
2612                 if (pointer == 0xFFFF || pointer == 0 ||
2613                     pointer >= hw->eeprom.word_size)
2614                         continue;
2615
2616                 switch (i) {
2617                 case IXGBE_PCIE_GENERAL_PTR:
2618                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2619                         break;
2620                 case IXGBE_PCIE_CONFIG0_PTR:
2621                 case IXGBE_PCIE_CONFIG1_PTR:
2622                         size = IXGBE_PCIE_CONFIG_SIZE;
2623                         break;
2624                 default:
2625                         size = 0;
2626                         break;
2627                 }
2628
2629                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2630                                                 buffer, buffer_size);
2631                 if (status)
2632                         return status;
2633         }
2634
2635         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2636
2637         return (s32)checksum;
2638 }
2639
2640 /**
2641  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2642  *  @hw: pointer to hardware structure
2643  *
2644  *  Returns a negative error code on error, or the 16-bit checksum
2645  **/
2646 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2647 {
2648         return ixgbe_calc_checksum_X550(hw, NULL, 0);
2649 }
2650
2651 /**
2652  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2653  *  @hw: pointer to hardware structure
2654  *  @checksum_val: calculated checksum
2655  *
2656  *  Performs checksum calculation and validates the EEPROM checksum.  If the
2657  *  caller does not need checksum_val, the value can be NULL.
2658  **/
2659 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2660 {
2661         s32 status;
2662         u16 checksum;
2663         u16 read_checksum = 0;
2664
2665         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2666
2667         /* Read the first word from the EEPROM. If this times out or fails, do
2668          * not continue or we could be in for a very long wait while every
2669          * EEPROM read fails
2670          */
2671         status = hw->eeprom.ops.read(hw, 0, &checksum);
2672         if (status) {
2673                 DEBUGOUT("EEPROM read failed\n");
2674                 return status;
2675         }
2676
2677         status = hw->eeprom.ops.calc_checksum(hw);
2678         if (status < 0)
2679                 return status;
2680
2681         checksum = (u16)(status & 0xffff);
2682
2683         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2684                                            &read_checksum);
2685         if (status)
2686                 return status;
2687
2688         /* Verify read checksum from EEPROM is the same as
2689          * calculated checksum
2690          */
2691         if (read_checksum != checksum) {
2692                 status = IXGBE_ERR_EEPROM_CHECKSUM;
2693                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2694                              "Invalid EEPROM checksum");
2695         }
2696
2697         /* If the user cares, return the calculated checksum */
2698         if (checksum_val)
2699                 *checksum_val = checksum;
2700
2701         return status;
2702 }
2703
2704 /**
2705  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2706  * @hw: pointer to hardware structure
2707  *
2708  * After writing EEPROM to shadow RAM using EEWR register, software calculates
2709  * checksum and updates the EEPROM and instructs the hardware to update
2710  * the flash.
2711  **/
2712 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2713 {
2714         s32 status;
2715         u16 checksum = 0;
2716
2717         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2718
2719         /* Read the first word from the EEPROM. If this times out or fails, do
2720          * not continue or we could be in for a very long wait while every
2721          * EEPROM read fails
2722          */
2723         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2724         if (status) {
2725                 DEBUGOUT("EEPROM read failed\n");
2726                 return status;
2727         }
2728
2729         status = ixgbe_calc_eeprom_checksum_X550(hw);
2730         if (status < 0)
2731                 return status;
2732
2733         checksum = (u16)(status & 0xffff);
2734
2735         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2736                                             checksum);
2737         if (status)
2738                 return status;
2739
2740         status = ixgbe_update_flash_X550(hw);
2741
2742         return status;
2743 }
2744
2745 /**
2746  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2747  *  @hw: pointer to hardware structure
2748  *
2749  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2750  **/
2751 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2752 {
2753         s32 status = IXGBE_SUCCESS;
2754         union ixgbe_hic_hdr2 buffer;
2755
2756         DEBUGFUNC("ixgbe_update_flash_X550");
2757
2758         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2759         buffer.req.buf_lenh = 0;
2760         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2761         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2762
2763         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2764                                               sizeof(buffer),
2765                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2766
2767         return status;
2768 }
2769
2770 /**
2771  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2772  *  @hw: pointer to hardware structure
2773  *
2774  *  Determines physical layer capabilities of the current configuration.
2775  **/
2776 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2777 {
2778         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2779         u16 ext_ability = 0;
2780
2781         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2782
2783         hw->phy.ops.identify(hw);
2784
2785         switch (hw->phy.type) {
2786         case ixgbe_phy_x550em_kr:
2787                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2788                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2789                 break;
2790         case ixgbe_phy_x550em_kx4:
2791                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2792                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2793                 break;
2794         case ixgbe_phy_x550em_ext_t:
2795                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2796                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2797                                      &ext_ability);
2798                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2799                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2800                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2801                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2802                 break;
2803         default:
2804                 break;
2805         }
2806
2807         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2808                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2809
2810         return physical_layer;
2811 }
2812
2813 /**
2814  * ixgbe_get_bus_info_x550em - Set PCI bus info
2815  * @hw: pointer to hardware structure
2816  *
2817  * Sets bus link width and speed to unknown because X550em is
2818  * not a PCI device.
2819  **/
2820 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2821 {
2822
2823         DEBUGFUNC("ixgbe_get_bus_info_x550em");
2824
2825         hw->bus.width = ixgbe_bus_width_unknown;
2826         hw->bus.speed = ixgbe_bus_speed_unknown;
2827
2828         hw->mac.ops.set_lan_id(hw);
2829
2830         return IXGBE_SUCCESS;
2831 }
2832
2833 /**
2834  * ixgbe_disable_rx_x550 - Disable RX unit
2835  *
2836  * Enables the Rx DMA unit for x550
2837  **/
2838 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2839 {
2840         u32 rxctrl, pfdtxgswc;
2841         s32 status;
2842         struct ixgbe_hic_disable_rxen fw_cmd;
2843
2844         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2845
2846         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2847         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2848                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2849                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2850                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2851                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2852                         hw->mac.set_lben = true;
2853                 } else {
2854                         hw->mac.set_lben = false;
2855                 }
2856
2857                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2858                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2859                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2860                 fw_cmd.port_number = (u8)hw->bus.lan_id;
2861
2862                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2863                                         sizeof(struct ixgbe_hic_disable_rxen),
2864                                         IXGBE_HI_COMMAND_TIMEOUT, true);
2865
2866                 /* If we fail - disable RX using register write */
2867                 if (status) {
2868                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2869                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2870                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2871                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2872                         }
2873                 }
2874         }
2875 }
2876
2877 /**
2878  * ixgbe_enter_lplu_x550em - Transition to low power states
2879  *  @hw: pointer to hardware structure
2880  *
2881  * Configures Low Power Link Up on transition to low power states
2882  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2883  * X557 PHY immediately prior to entering LPLU.
2884  **/
2885 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2886 {
2887         u16 an_10g_cntl_reg, autoneg_reg, speed;
2888         s32 status;
2889         ixgbe_link_speed lcd_speed;
2890         u32 save_autoneg;
2891         bool link_up;
2892
2893         /* SW LPLU not required on later HW revisions. */
2894         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2895             (IXGBE_FUSES0_REV_MASK &
2896              IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2897                 return IXGBE_SUCCESS;
2898
2899         /* If blocked by MNG FW, then don't restart AN */
2900         if (ixgbe_check_reset_blocked(hw))
2901                 return IXGBE_SUCCESS;
2902
2903         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2904         if (status != IXGBE_SUCCESS)
2905                 return status;
2906
2907         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2908
2909         if (status != IXGBE_SUCCESS)
2910                 return status;
2911
2912         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2913          * disabled, then force link down by entering low power mode.
2914          */
2915         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2916             !(hw->wol_enabled || ixgbe_mng_present(hw)))
2917                 return ixgbe_set_copper_phy_power(hw, FALSE);
2918
2919         /* Determine LCD */
2920         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2921
2922         if (status != IXGBE_SUCCESS)
2923                 return status;
2924
2925         /* If no valid LCD link speed, then force link down and exit. */
2926         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2927                 return ixgbe_set_copper_phy_power(hw, FALSE);
2928
2929         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2930                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2931                                       &speed);
2932
2933         if (status != IXGBE_SUCCESS)
2934                 return status;
2935
2936         /* If no link now, speed is invalid so take link down */
2937         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2938         if (status != IXGBE_SUCCESS)
2939                 return ixgbe_set_copper_phy_power(hw, false);
2940
2941         /* clear everything but the speed bits */
2942         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2943
2944         /* If current speed is already LCD, then exit. */
2945         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2946              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2947             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2948              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2949                 return status;
2950
2951         /* Clear AN completed indication */
2952         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2953                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2954                                       &autoneg_reg);
2955
2956         if (status != IXGBE_SUCCESS)
2957                 return status;
2958
2959         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2960                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2961                              &an_10g_cntl_reg);
2962
2963         if (status != IXGBE_SUCCESS)
2964                 return status;
2965
2966         status = hw->phy.ops.read_reg(hw,
2967                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2968                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2969                              &autoneg_reg);
2970
2971         if (status != IXGBE_SUCCESS)
2972                 return status;
2973
2974         save_autoneg = hw->phy.autoneg_advertised;
2975
2976         /* Setup link at least common link speed */
2977         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
2978
2979         /* restore autoneg from before setting lplu speed */
2980         hw->phy.autoneg_advertised = save_autoneg;
2981
2982         return status;
2983 }
2984
2985 /**
2986  * ixgbe_get_lcd_x550em - Determine lowest common denominator
2987  *  @hw: pointer to hardware structure
2988  *  @lcd_speed: pointer to lowest common link speed
2989  *
2990  * Determine lowest common link speed with link partner.
2991  **/
2992 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2993 {
2994         u16 an_lp_status;
2995         s32 status;
2996         u16 word = hw->eeprom.ctrl_word_3;
2997
2998         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2999
3000         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3001                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3002                                       &an_lp_status);
3003
3004         if (status != IXGBE_SUCCESS)
3005                 return status;
3006
3007         /* If link partner advertised 1G, return 1G */
3008         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3009                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3010                 return status;
3011         }
3012
3013         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3014         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3015             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3016                 return status;
3017
3018         /* Link partner not capable of lower speeds, return 10G */
3019         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3020         return status;
3021 }
3022
3023 /**
3024  *  ixgbe_setup_fc_X550em - Set up flow control
3025  *  @hw: pointer to hardware structure
3026  *
3027  *  Called at init time to set up flow control.
3028  **/
3029 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3030 {
3031         s32 ret_val = IXGBE_SUCCESS;
3032         u32 pause, asm_dir, reg_val;
3033
3034         DEBUGFUNC("ixgbe_setup_fc_X550em");
3035
3036         /* Validate the requested mode */
3037         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3038                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3039                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3040                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3041                 goto out;
3042         }
3043
3044         /* 10gig parts do not have a word in the EEPROM to determine the
3045          * default flow control setting, so we explicitly set it to full.
3046          */
3047         if (hw->fc.requested_mode == ixgbe_fc_default)
3048                 hw->fc.requested_mode = ixgbe_fc_full;
3049
3050         /* Determine PAUSE and ASM_DIR bits. */
3051         switch (hw->fc.requested_mode) {
3052         case ixgbe_fc_none:
3053                 pause = 0;
3054                 asm_dir = 0;
3055                 break;
3056         case ixgbe_fc_tx_pause:
3057                 pause = 0;
3058                 asm_dir = 1;
3059                 break;
3060         case ixgbe_fc_rx_pause:
3061                 /* Rx Flow control is enabled and Tx Flow control is
3062                  * disabled by software override. Since there really
3063                  * isn't a way to advertise that we are capable of RX
3064                  * Pause ONLY, we will advertise that we support both
3065                  * symmetric and asymmetric Rx PAUSE, as such we fall
3066                  * through to the fc_full statement.  Later, we will
3067                  * disable the adapter's ability to send PAUSE frames.
3068                  */
3069         case ixgbe_fc_full:
3070                 pause = 1;
3071                 asm_dir = 1;
3072                 break;
3073         default:
3074                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3075                         "Flow control param set incorrectly\n");
3076                 ret_val = IXGBE_ERR_CONFIG;
3077                 goto out;
3078         }
3079
3080         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
3081                 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
3082                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3083                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3084                 if (ret_val != IXGBE_SUCCESS)
3085                         goto out;
3086                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3087                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3088                 if (pause)
3089                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3090                 if (asm_dir)
3091                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3092                 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
3093                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3094                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3095
3096                 /* This device does not fully support AN. */
3097                 hw->fc.disable_fc_autoneg = true;
3098         }
3099
3100 out:
3101         return ret_val;
3102 }
3103
3104 /**
3105  * ixgbe_set_mux - Set mux for port 1 access with CS4227
3106  * @hw: pointer to hardware structure
3107  * @state: set mux if 1, clear if 0
3108  */
3109 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
3110 {
3111         u32 esdp;
3112
3113         if (!hw->bus.lan_id)
3114                 return;
3115         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3116         if (state)
3117                 esdp |= IXGBE_ESDP_SDP1;
3118         else
3119                 esdp &= ~IXGBE_ESDP_SDP1;
3120         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
3121         IXGBE_WRITE_FLUSH(hw);
3122 }
3123
3124 /**
3125  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
3126  *  @hw: pointer to hardware structure
3127  *  @mask: Mask to specify which semaphore to acquire
3128  *
3129  *  Acquires the SWFW semaphore and sets the I2C MUX
3130  **/
3131 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3132 {
3133         s32 status;
3134
3135         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
3136
3137         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
3138         if (status)
3139                 return status;
3140
3141         if (mask & IXGBE_GSSR_I2C_MASK)
3142                 ixgbe_set_mux(hw, 1);
3143
3144         return IXGBE_SUCCESS;
3145 }
3146
3147 /**
3148  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
3149  *  @hw: pointer to hardware structure
3150  *  @mask: Mask to specify which semaphore to release
3151  *
3152  *  Releases the SWFW semaphore and sets the I2C MUX
3153  **/
3154 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3155 {
3156         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
3157
3158         if (mask & IXGBE_GSSR_I2C_MASK)
3159                 ixgbe_set_mux(hw, 0);
3160
3161         ixgbe_release_swfw_sync_X540(hw, mask);
3162 }
3163
3164 /**
3165  *  ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
3166  *  @hw: pointer to hardware structure
3167  *  @mask: Mask to specify which semaphore to acquire
3168  *
3169  *  Acquires the SWFW semaphore and get the shared phy token as needed
3170  */
3171 static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
3172 {
3173         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3174         int retries = FW_PHY_TOKEN_RETRIES;
3175         s32 status = IXGBE_SUCCESS;
3176
3177         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
3178
3179         while (--retries) {
3180                 if (hmask)
3181                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
3182                 if (status)
3183                         break;
3184                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
3185                         break;
3186                 status = ixgbe_get_phy_token(hw);
3187                 if (status != IXGBE_ERR_TOKEN_RETRY)
3188                         break;
3189                 if (hmask)
3190                         ixgbe_release_swfw_sync_X540(hw, hmask);
3191                 msec_delay(FW_PHY_TOKEN_DELAY);
3192         }
3193
3194         return status;
3195 }
3196
3197 /**
3198  *  ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
3199  *  @hw: pointer to hardware structure
3200  *  @mask: Mask to specify which semaphore to release
3201  *
3202  *  Releases the SWFW semaphore and puts the shared phy token as needed
3203  */
3204 static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
3205 {
3206         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3207
3208         DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
3209
3210         if (mask & IXGBE_GSSR_TOKEN_SM)
3211                 ixgbe_put_phy_token(hw);
3212
3213         if (hmask)
3214                 ixgbe_release_swfw_sync_X540(hw, hmask);
3215 }
3216
3217 /**
3218  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
3219  * @hw: pointer to hardware structure
3220  *
3221  * Handle external Base T PHY interrupt. If high temperature
3222  * failure alarm then return error, else if link status change
3223  * then setup internal/external PHY link
3224  *
3225  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
3226  * failure alarm, else return PHY access status.
3227  */
3228 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
3229 {
3230         bool lsc;
3231         u32 status;
3232
3233         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
3234
3235         if (status != IXGBE_SUCCESS)
3236                 return status;
3237
3238         if (lsc)
3239                 return ixgbe_setup_internal_phy(hw);
3240
3241         return IXGBE_SUCCESS;
3242 }
3243
3244 /**
3245  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
3246  * @hw: pointer to hardware structure
3247  * @speed: new link speed
3248  * @autoneg_wait_to_complete: true when waiting for completion is needed
3249  *
3250  * Setup internal/external PHY link speed based on link speed, then set
3251  * external PHY auto advertised link speed.
3252  *
3253  * Returns error status for any failure
3254  **/
3255 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
3256                                   ixgbe_link_speed speed,
3257                                   bool autoneg_wait_to_complete)
3258 {
3259         s32 status;
3260         ixgbe_link_speed force_speed;
3261
3262         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
3263
3264         /* Setup internal/external PHY link speed to iXFI (10G), unless
3265          * only 1G is auto advertised then setup KX link.
3266          */
3267         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
3268                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3269         else
3270                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3271
3272         /* If internal link mode is XFI, then setup XFI internal link. */
3273         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3274                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
3275
3276                 if (status != IXGBE_SUCCESS)
3277                         return status;
3278         }
3279
3280         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
3281 }
3282
3283 /**
3284  * ixgbe_check_link_t_X550em - Determine link and speed status
3285  * @hw: pointer to hardware structure
3286  * @speed: pointer to link speed
3287  * @link_up: true when link is up
3288  * @link_up_wait_to_complete: bool used to wait for link up or not
3289  *
3290  * Check that both the MAC and X557 external PHY have link.
3291  **/
3292 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3293                               bool *link_up, bool link_up_wait_to_complete)
3294 {
3295         u32 status;
3296         u16 autoneg_status;
3297
3298         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3299                 return IXGBE_ERR_CONFIG;
3300
3301         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
3302                                               link_up_wait_to_complete);
3303
3304         /* If check link fails or MAC link is not up, then return */
3305         if (status != IXGBE_SUCCESS || !(*link_up))
3306                 return status;
3307
3308         /* MAC link is up, so check external PHY link.
3309          * Read this twice back to back to indicate current status.
3310          */
3311         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3312                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3313                                       &autoneg_status);
3314
3315         if (status != IXGBE_SUCCESS)
3316                 return status;
3317
3318         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3319                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3320                                       &autoneg_status);
3321
3322         if (status != IXGBE_SUCCESS)
3323                 return status;
3324
3325         /* If external PHY link is not up, then indicate link not up */
3326         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
3327                 *link_up = false;
3328
3329         return IXGBE_SUCCESS;
3330 }
3331
3332 /**
3333  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
3334  *  @hw: pointer to hardware structure
3335  **/
3336 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
3337 {
3338         s32 status;
3339
3340         status = ixgbe_reset_phy_generic(hw);
3341
3342         if (status != IXGBE_SUCCESS)
3343                 return status;
3344
3345         /* Configure Link Status Alarm and Temperature Threshold interrupts */
3346         return ixgbe_enable_lasi_ext_t_x550em(hw);
3347 }
3348
3349 /**
3350  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
3351  *  @hw: pointer to hardware structure
3352  *  @led_idx: led number to turn on
3353  **/
3354 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3355 {
3356         u16 phy_data;
3357
3358         DEBUGFUNC("ixgbe_led_on_t_X550em");
3359
3360         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3361                 return IXGBE_ERR_PARAM;
3362
3363         /* To turn on the LED, set mode to ON. */
3364         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3365                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3366         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
3367         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3368                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3369
3370         return IXGBE_SUCCESS;
3371 }
3372
3373 /**
3374  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
3375  *  @hw: pointer to hardware structure
3376  *  @led_idx: led number to turn off
3377  **/
3378 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3379 {
3380         u16 phy_data;
3381
3382         DEBUGFUNC("ixgbe_led_off_t_X550em");
3383
3384         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3385                 return IXGBE_ERR_PARAM;
3386
3387         /* To turn on the LED, set mode to ON. */
3388         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3389                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3390         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
3391         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3392                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3393
3394         return IXGBE_SUCCESS;
3395 }
3396