1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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13 notice, this list of conditions and the following disclaimer in the
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20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
43 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
44 * @hw: pointer to hardware structure
46 * Initialize the function pointers and assign the MAC type for X550.
47 * Does not touch the hardware.
49 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
51 struct ixgbe_mac_info *mac = &hw->mac;
52 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
55 DEBUGFUNC("ixgbe_init_ops_X550");
57 ret_val = ixgbe_init_ops_X540(hw);
58 mac->ops.dmac_config = ixgbe_dmac_config_X550;
59 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
60 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
61 mac->ops.setup_eee = ixgbe_setup_eee_X550;
62 mac->ops.set_source_address_pruning =
63 ixgbe_set_source_address_pruning_X550;
64 mac->ops.set_ethertype_anti_spoofing =
65 ixgbe_set_ethertype_anti_spoofing_X550;
67 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
68 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
69 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
70 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
71 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
72 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
73 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
74 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
75 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
77 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
78 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
79 mac->ops.mdd_event = ixgbe_mdd_event_X550;
80 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
81 mac->ops.disable_rx = ixgbe_disable_rx_x550;
86 * ixgbe_read_cs4227 - Read CS4227 register
87 * @hw: pointer to hardware structure
88 * @reg: register number to write
89 * @value: pointer to receive value read
93 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
95 return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
99 * ixgbe_write_cs4227 - Write CS4227 register
100 * @hw: pointer to hardware structure
101 * @reg: register number to write
102 * @value: value to write to register
104 * Returns status code
106 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
108 return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
112 * ixgbe_get_cs4227_status - Return CS4227 status
113 * @hw: pointer to hardware structure
115 * Returns error if CS4227 not successfully initialized
117 STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
123 for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) {
124 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB,
126 if (status != IXGBE_SUCCESS)
128 if (value == IXGBE_CS4227_GLOBAL_ID_VALUE)
130 msec_delay(IXGBE_CS4227_CHECK_DELAY);
132 if (value != IXGBE_CS4227_GLOBAL_ID_VALUE)
133 return IXGBE_ERR_PHY;
135 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
136 IXGBE_CS4227_SCRATCH_VALUE);
137 if (status != IXGBE_SUCCESS)
139 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
140 if (status != IXGBE_SUCCESS)
142 if (value != IXGBE_CS4227_SCRATCH_VALUE)
143 return IXGBE_ERR_PHY;
144 return IXGBE_SUCCESS;
148 * ixgbe_read_pe - Read register from port expander
149 * @hw: pointer to hardware structure
150 * @reg: register number to read
151 * @value: pointer to receive read value
153 * Returns status code
155 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
159 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
160 if (status != IXGBE_SUCCESS)
161 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
162 "port expander access failed with %d\n", status);
167 * ixgbe_write_pe - Write register to port expander
168 * @hw: pointer to hardware structure
169 * @reg: register number to write
170 * @value: value to write
172 * Returns status code
174 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
178 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
179 if (status != IXGBE_SUCCESS)
180 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
181 "port expander access failed with %d\n", status);
186 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
187 * @hw: pointer to hardware structure
191 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
196 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
197 if (status != IXGBE_SUCCESS)
199 reg |= IXGBE_PE_BIT1;
200 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
201 if (status != IXGBE_SUCCESS)
204 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
205 if (status != IXGBE_SUCCESS)
207 reg &= ~IXGBE_PE_BIT1;
208 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
209 if (status != IXGBE_SUCCESS)
212 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
213 if (status != IXGBE_SUCCESS)
215 reg &= ~IXGBE_PE_BIT1;
216 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
217 if (status != IXGBE_SUCCESS)
220 usec_delay(IXGBE_CS4227_RESET_HOLD);
222 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
223 if (status != IXGBE_SUCCESS)
225 reg |= IXGBE_PE_BIT1;
226 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
227 if (status != IXGBE_SUCCESS)
230 msec_delay(IXGBE_CS4227_RESET_DELAY);
232 return IXGBE_SUCCESS;
236 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
237 * @hw: pointer to hardware structure
239 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
241 u32 swfw_mask = hw->phy.phy_semaphore_mask;
245 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
246 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
247 if (status != IXGBE_SUCCESS) {
248 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
249 "semaphore failed with %d\n", status);
252 status = ixgbe_get_cs4227_status(hw);
253 if (status == IXGBE_SUCCESS) {
254 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
255 msec_delay(hw->eeprom.semaphore_delay);
258 ixgbe_reset_cs4227(hw);
259 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
260 msec_delay(hw->eeprom.semaphore_delay);
262 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
263 "Unable to initialize CS4227, err=%d\n", status);
267 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
268 * @hw: pointer to hardware structure
270 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
272 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
274 if (hw->bus.lan_id) {
275 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
276 esdp |= IXGBE_ESDP_SDP1_DIR;
278 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
279 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
280 IXGBE_WRITE_FLUSH(hw);
284 * ixgbe_identify_phy_x550em - Get PHY type based on device id
285 * @hw: pointer to hardware structure
289 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
291 switch (hw->device_id) {
292 case IXGBE_DEV_ID_X550EM_X_SFP:
293 /* set up for CS4227 usage */
294 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
295 ixgbe_setup_mux_ctl(hw);
296 ixgbe_check_cs4227(hw);
298 return ixgbe_identify_module_generic(hw);
300 case IXGBE_DEV_ID_X550EM_X_KX4:
301 hw->phy.type = ixgbe_phy_x550em_kx4;
303 case IXGBE_DEV_ID_X550EM_X_KR:
304 hw->phy.type = ixgbe_phy_x550em_kr;
306 case IXGBE_DEV_ID_X550EM_X_1G_T:
307 case IXGBE_DEV_ID_X550EM_X_10G_T:
308 return ixgbe_identify_phy_generic(hw);
312 return IXGBE_SUCCESS;
315 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
316 u32 device_type, u16 *phy_data)
318 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
319 return IXGBE_NOT_IMPLEMENTED;
322 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
323 u32 device_type, u16 phy_data)
325 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
326 return IXGBE_NOT_IMPLEMENTED;
330 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
331 * @hw: pointer to hardware structure
333 * Initialize the function pointers and for MAC type X550EM.
334 * Does not touch the hardware.
336 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
338 struct ixgbe_mac_info *mac = &hw->mac;
339 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
340 struct ixgbe_phy_info *phy = &hw->phy;
343 DEBUGFUNC("ixgbe_init_ops_X550EM");
345 /* Similar to X550 so start there. */
346 ret_val = ixgbe_init_ops_X550(hw);
348 /* Since this function eventually calls
349 * ixgbe_init_ops_540 by design, we are setting
350 * the pointers to NULL explicitly here to overwrite
351 * the values being set in the x540 function.
353 /* Thermal sensor not supported in x550EM */
354 mac->ops.get_thermal_sensor_data = NULL;
355 mac->ops.init_thermal_sensor_thresh = NULL;
356 mac->thermal_sensor_enabled = false;
358 /* FCOE not supported in x550EM */
359 mac->ops.get_san_mac_addr = NULL;
360 mac->ops.set_san_mac_addr = NULL;
361 mac->ops.get_wwn_prefix = NULL;
362 mac->ops.get_fcoe_boot_status = NULL;
364 /* IPsec not supported in x550EM */
365 mac->ops.disable_sec_rx_path = NULL;
366 mac->ops.enable_sec_rx_path = NULL;
368 /* AUTOC register is not present in x550EM. */
369 mac->ops.prot_autoc_read = NULL;
370 mac->ops.prot_autoc_write = NULL;
372 /* X550EM bus type is internal*/
373 hw->bus.type = ixgbe_bus_type_internal;
374 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
376 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
377 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
378 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
379 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
380 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
381 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
382 mac->ops.get_supported_physical_layer =
383 ixgbe_get_supported_physical_layer_X550em;
385 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
386 mac->ops.setup_fc = ixgbe_setup_fc_generic;
388 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
390 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
391 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
393 if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
394 mac->ops.setup_eee = NULL;
397 phy->ops.init = ixgbe_init_phy_ops_X550em;
398 phy->ops.identify = ixgbe_identify_phy_x550em;
399 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
400 phy->ops.set_phy_power = NULL;
404 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
405 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
406 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
407 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
408 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
409 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
410 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
411 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
417 * ixgbe_dmac_config_X550
418 * @hw: pointer to hardware structure
420 * Configure DMA coalescing. If enabling dmac, dmac is activated.
421 * When disabling dmac, dmac enable dmac bit is cleared.
423 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
425 u32 reg, high_pri_tc;
427 DEBUGFUNC("ixgbe_dmac_config_X550");
429 /* Disable DMA coalescing before configuring */
430 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
431 reg &= ~IXGBE_DMACR_DMAC_EN;
432 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
434 /* Disable DMA Coalescing if the watchdog timer is 0 */
435 if (!hw->mac.dmac_config.watchdog_timer)
438 ixgbe_dmac_config_tcs_X550(hw);
440 /* Configure DMA Coalescing Control Register */
441 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
443 /* Set the watchdog timer in units of 40.96 usec */
444 reg &= ~IXGBE_DMACR_DMACWT_MASK;
445 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
447 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
448 /* If fcoe is enabled, set high priority traffic class */
449 if (hw->mac.dmac_config.fcoe_en) {
450 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
451 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
452 IXGBE_DMACR_HIGH_PRI_TC_MASK);
454 reg |= IXGBE_DMACR_EN_MNG_IND;
456 /* Enable DMA coalescing after configuration */
457 reg |= IXGBE_DMACR_DMAC_EN;
458 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
461 return IXGBE_SUCCESS;
465 * ixgbe_dmac_config_tcs_X550
466 * @hw: pointer to hardware structure
468 * Configure DMA coalescing threshold per TC. The dmac enable bit must
469 * be cleared before configuring.
471 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
473 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
475 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
477 /* Configure DMA coalescing enabled */
478 switch (hw->mac.dmac_config.link_speed) {
479 case IXGBE_LINK_SPEED_100_FULL:
480 pb_headroom = IXGBE_DMACRXT_100M;
482 case IXGBE_LINK_SPEED_1GB_FULL:
483 pb_headroom = IXGBE_DMACRXT_1G;
486 pb_headroom = IXGBE_DMACRXT_10G;
490 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
491 IXGBE_MHADD_MFS_SHIFT) / 1024);
493 /* Set the per Rx packet buffer receive threshold */
494 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
495 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
496 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
498 if (tc < hw->mac.dmac_config.num_tcs) {
500 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
501 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
502 IXGBE_RXPBSIZE_SHIFT;
504 /* Calculate receive buffer threshold in kilobytes */
505 if (rx_pb_size > pb_headroom)
506 rx_pb_size = rx_pb_size - pb_headroom;
510 /* Minimum of MFS shall be set for DMCTH */
511 reg |= (rx_pb_size > maxframe_size_kb) ?
512 rx_pb_size : maxframe_size_kb;
514 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
516 return IXGBE_SUCCESS;
520 * ixgbe_dmac_update_tcs_X550
521 * @hw: pointer to hardware structure
523 * Disables dmac, updates per TC settings, and then enables dmac.
525 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
529 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
531 /* Disable DMA coalescing before configuring */
532 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
533 reg &= ~IXGBE_DMACR_DMAC_EN;
534 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
536 ixgbe_dmac_config_tcs_X550(hw);
538 /* Enable DMA coalescing after configuration */
539 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
540 reg |= IXGBE_DMACR_DMAC_EN;
541 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
543 return IXGBE_SUCCESS;
547 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
548 * @hw: pointer to hardware structure
550 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
551 * ixgbe_hw struct in order to set up EEPROM access.
553 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
555 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
559 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
561 if (eeprom->type == ixgbe_eeprom_uninitialized) {
562 eeprom->semaphore_delay = 10;
563 eeprom->type = ixgbe_flash;
565 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
566 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
567 IXGBE_EEC_SIZE_SHIFT);
568 eeprom->word_size = 1 << (eeprom_size +
569 IXGBE_EEPROM_WORD_SIZE_SHIFT);
571 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
572 eeprom->type, eeprom->word_size);
575 return IXGBE_SUCCESS;
579 * ixgbe_setup_eee_X550 - Enable/disable EEE support
580 * @hw: pointer to the HW structure
581 * @enable_eee: boolean flag to enable EEE
583 * Enable/disable EEE based on enable_eee flag.
584 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
588 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
595 DEBUGFUNC("ixgbe_setup_eee_X550");
597 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
598 /* Enable or disable EEE per flag */
600 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
602 if (hw->device_id == IXGBE_DEV_ID_X550T) {
603 /* Advertise EEE capability */
604 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
605 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
607 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
608 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
609 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
611 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
612 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
613 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
614 status = ixgbe_read_iosf_sb_reg_x550(hw,
615 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
616 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
617 if (status != IXGBE_SUCCESS)
620 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
621 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
623 status = ixgbe_write_iosf_sb_reg_x550(hw,
624 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
625 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
626 if (status != IXGBE_SUCCESS)
630 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
632 if (hw->device_id == IXGBE_DEV_ID_X550T) {
633 /* Disable advertised EEE capability */
634 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
635 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
637 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
638 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
639 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
641 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
642 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
643 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
644 status = ixgbe_read_iosf_sb_reg_x550(hw,
645 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
646 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
647 if (status != IXGBE_SUCCESS)
650 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
651 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
653 status = ixgbe_write_iosf_sb_reg_x550(hw,
654 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
655 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
656 if (status != IXGBE_SUCCESS)
660 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
662 return IXGBE_SUCCESS;
666 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
667 * @hw: pointer to hardware structure
668 * @enable: enable or disable source address pruning
669 * @pool: Rx pool to set source address pruning for
671 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
676 /* max rx pool is 63 */
680 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
681 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
684 pfflp |= (1ULL << pool);
686 pfflp &= ~(1ULL << pool);
688 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
689 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
693 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
694 * @hw: pointer to hardware structure
695 * @enable: enable or disable switch for Ethertype anti-spoofing
696 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
699 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
702 int vf_target_reg = vf >> 3;
703 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
706 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
708 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
710 pfvfspoof |= (1 << vf_target_shift);
712 pfvfspoof &= ~(1 << vf_target_shift);
714 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
718 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
720 * @hw: pointer to hardware structure
721 * @reg_addr: 32 bit PHY register to write
722 * @device_type: 3 bit device type
723 * @data: Data to write to the register
725 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
726 u32 device_type, u32 data)
728 u32 i, command, error;
730 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
731 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
733 /* Write IOSF control register */
734 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
736 /* Write IOSF data register */
737 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
739 * Check every 10 usec to see if the address cycle completed.
740 * The SB IOSF BUSY bit will clear when the operation is
743 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
746 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
747 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
751 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
752 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
753 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
754 ERROR_REPORT2(IXGBE_ERROR_POLLING,
755 "Failed to write, error %x\n", error);
756 return IXGBE_ERR_PHY;
759 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
760 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Write timed out\n");
761 return IXGBE_ERR_PHY;
764 return IXGBE_SUCCESS;
768 * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
770 * @hw: pointer to hardware structure
771 * @reg_addr: 32 bit PHY register to write
772 * @device_type: 3 bit device type
773 * @phy_data: Pointer to read data from the register
775 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
776 u32 device_type, u32 *data)
778 u32 i, command, error;
780 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
781 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
783 /* Write IOSF control register */
784 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
787 * Check every 10 usec to see if the address cycle completed.
788 * The SB IOSF BUSY bit will clear when the operation is
791 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
794 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
795 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
799 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
800 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
801 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
802 ERROR_REPORT2(IXGBE_ERROR_POLLING,
803 "Failed to read, error %x\n", error);
804 return IXGBE_ERR_PHY;
807 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
808 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Read timed out\n");
809 return IXGBE_ERR_PHY;
812 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
814 return IXGBE_SUCCESS;
818 * ixgbe_disable_mdd_X550
819 * @hw: pointer to hardware structure
821 * Disable malicious driver detection
823 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
827 DEBUGFUNC("ixgbe_disable_mdd_X550");
829 /* Disable MDD for TX DMA and interrupt */
830 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
831 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
832 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
834 /* Disable MDD for RX and interrupt */
835 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
836 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
837 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
841 * ixgbe_enable_mdd_X550
842 * @hw: pointer to hardware structure
844 * Enable malicious driver detection
846 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
850 DEBUGFUNC("ixgbe_enable_mdd_X550");
852 /* Enable MDD for TX DMA and interrupt */
853 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
854 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
855 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
857 /* Enable MDD for RX and interrupt */
858 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
859 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
860 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
864 * ixgbe_restore_mdd_vf_X550
865 * @hw: pointer to hardware structure
868 * Restore VF that was disabled during malicious driver detection event
870 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
872 u32 idx, reg, num_qs, start_q, bitmask;
874 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
876 /* Map VF to queues */
877 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
878 switch (reg & IXGBE_MRQC_MRQE_MASK) {
879 case IXGBE_MRQC_VMDQRT8TCEN:
880 num_qs = 8; /* 16 VFs / pools */
881 bitmask = 0x000000FF;
883 case IXGBE_MRQC_VMDQRSS32EN:
884 case IXGBE_MRQC_VMDQRT4TCEN:
885 num_qs = 4; /* 32 VFs / pools */
886 bitmask = 0x0000000F;
888 default: /* 64 VFs / pools */
890 bitmask = 0x00000003;
893 start_q = vf * num_qs;
895 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
898 reg |= (bitmask << (start_q % 32));
899 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
900 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
904 * ixgbe_mdd_event_X550
905 * @hw: pointer to hardware structure
906 * @vf_bitmap: vf bitmap of malicious vfs
908 * Handle malicious driver detection event.
910 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
913 u32 i, j, reg, q, shift, vf, idx;
915 DEBUGFUNC("ixgbe_mdd_event_X550");
917 /* figure out pool size for mapping to vf's */
918 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
919 switch (reg & IXGBE_MRQC_MRQE_MASK) {
920 case IXGBE_MRQC_VMDQRT8TCEN:
921 shift = 3; /* 16 VFs / pools */
923 case IXGBE_MRQC_VMDQRSS32EN:
924 case IXGBE_MRQC_VMDQRT4TCEN:
925 shift = 2; /* 32 VFs / pools */
928 shift = 1; /* 64 VFs / pools */
932 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
933 for (i = 0; i < 4; i++) {
934 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
935 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
940 /* Get malicious queue */
941 for (j = 0; j < 32 && wqbr; j++) {
943 if (!(wqbr & (1 << j)))
946 /* Get queue from bitmask */
949 /* Map queue to vf */
952 /* Set vf bit in vf_bitmap */
954 vf_bitmap[idx] |= (1 << (vf % 32));
961 * ixgbe_get_media_type_X550em - Get media type
962 * @hw: pointer to hardware structure
964 * Returns the media type (fiber, copper, backplane)
966 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
968 enum ixgbe_media_type media_type;
970 DEBUGFUNC("ixgbe_get_media_type_X550em");
972 /* Detect if there is a copper PHY attached. */
973 switch (hw->device_id) {
974 case IXGBE_DEV_ID_X550EM_X_KR:
975 case IXGBE_DEV_ID_X550EM_X_KX4:
976 media_type = ixgbe_media_type_backplane;
978 case IXGBE_DEV_ID_X550EM_X_SFP:
979 media_type = ixgbe_media_type_fiber;
981 case IXGBE_DEV_ID_X550EM_X_1G_T:
982 case IXGBE_DEV_ID_X550EM_X_10G_T:
983 media_type = ixgbe_media_type_copper;
986 media_type = ixgbe_media_type_unknown;
993 * ixgbe_setup_sfp_modules_X550em - Setup SFP module
994 * @hw: pointer to hardware structure
996 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
999 u16 reg_slice, edc_mode;
1002 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1004 switch (hw->phy.sfp_type) {
1005 case ixgbe_sfp_type_unknown:
1006 return IXGBE_SUCCESS;
1007 case ixgbe_sfp_type_not_present:
1008 return IXGBE_ERR_SFP_NOT_PRESENT;
1009 case ixgbe_sfp_type_da_cu_core0:
1010 case ixgbe_sfp_type_da_cu_core1:
1011 setup_linear = true;
1013 case ixgbe_sfp_type_srlr_core0:
1014 case ixgbe_sfp_type_srlr_core1:
1015 case ixgbe_sfp_type_da_act_lmt_core0:
1016 case ixgbe_sfp_type_da_act_lmt_core1:
1017 case ixgbe_sfp_type_1g_sx_core0:
1018 case ixgbe_sfp_type_1g_sx_core1:
1019 case ixgbe_sfp_type_1g_lx_core0:
1020 case ixgbe_sfp_type_1g_lx_core1:
1021 setup_linear = false;
1024 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1027 ixgbe_init_mac_link_ops_X550em(hw);
1028 hw->phy.ops.reset = NULL;
1030 /* The CS4227 slice address is the base address + the port-pair reg
1031 * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0.
1033 reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->bus.lan_id << 12);
1036 edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1038 edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1040 /* Configure CS4227 for connection type. */
1041 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1044 if (ret_val != IXGBE_SUCCESS)
1045 ret_val = ixgbe_write_i2c_combined(hw, 0x80, reg_slice,
1052 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1053 * @hw: pointer to hardware structure
1055 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1057 struct ixgbe_mac_info *mac = &hw->mac;
1059 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1061 switch (hw->mac.ops.get_media_type(hw)) {
1062 case ixgbe_media_type_fiber:
1063 /* CS4227 does not support autoneg, so disable the laser control
1064 * functions for SFP+ fiber
1066 mac->ops.disable_tx_laser = NULL;
1067 mac->ops.enable_tx_laser = NULL;
1068 mac->ops.flap_tx_laser = NULL;
1069 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1070 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1071 mac->ops.set_rate_select_speed =
1072 ixgbe_set_soft_rate_select_speed;
1074 case ixgbe_media_type_copper:
1075 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1076 mac->ops.check_link = ixgbe_check_link_t_X550em;
1084 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1085 * @hw: pointer to hardware structure
1086 * @speed: pointer to link speed
1087 * @autoneg: true when autoneg or autotry is enabled
1089 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1090 ixgbe_link_speed *speed,
1093 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1096 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1098 /* CS4227 SFP must not enable auto-negotiation */
1101 /* Check if 1G SFP module. */
1102 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1103 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1104 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1105 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1106 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1107 return IXGBE_SUCCESS;
1110 /* Link capabilities are based on SFP */
1111 if (hw->phy.multispeed_fiber)
1112 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1113 IXGBE_LINK_SPEED_1GB_FULL;
1115 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1117 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1118 IXGBE_LINK_SPEED_1GB_FULL;
1122 return IXGBE_SUCCESS;
1126 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1127 * @hw: pointer to hardware structure
1128 * @lsc: pointer to boolean flag which indicates whether external Base T
1129 * PHY interrupt is lsc
1131 * Determime if external Base T PHY interrupt cause is high temperature
1132 * failure alarm or link status change.
1134 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1135 * failure alarm, else return PHY access status.
1137 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1144 /* Vendor alarm triggered */
1145 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1146 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1149 if (status != IXGBE_SUCCESS ||
1150 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1153 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1154 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1155 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1158 if (status != IXGBE_SUCCESS ||
1159 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1160 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1163 /* High temperature failure alarm triggered */
1164 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1165 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1168 if (status != IXGBE_SUCCESS)
1171 /* If high temperature failure, then return over temp error and exit */
1172 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL)
1173 return IXGBE_ERR_OVERTEMP;
1175 /* Vendor alarm 2 triggered */
1176 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1177 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1179 if (status != IXGBE_SUCCESS ||
1180 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1183 /* link connect/disconnect event occurred */
1184 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1185 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1187 if (status != IXGBE_SUCCESS)
1191 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1194 return IXGBE_SUCCESS;
1198 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1199 * @hw: pointer to hardware structure
1201 * Enable link status change and temperature failure alarm for the external
1204 * Returns PHY access status
1206 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1212 /* Clear interrupt flags */
1213 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1215 /* Enable link status change alarm */
1216 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1217 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1219 if (status != IXGBE_SUCCESS)
1222 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1224 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1225 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1227 if (status != IXGBE_SUCCESS)
1230 /* Enables high temperature failure alarm */
1231 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1232 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1235 if (status != IXGBE_SUCCESS)
1238 reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;
1240 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1241 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1244 if (status != IXGBE_SUCCESS)
1247 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1248 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1249 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1252 if (status != IXGBE_SUCCESS)
1255 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1256 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1258 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1259 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1262 if (status != IXGBE_SUCCESS)
1265 /* Enable chip-wide vendor alarm */
1266 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1267 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1270 if (status != IXGBE_SUCCESS)
1273 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1275 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1276 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1283 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1284 * @hw: pointer to hardware structure
1286 * Initialize any function pointers that were not able to be
1287 * set during init_shared_code because the PHY/SFP type was
1288 * not known. Perform the SFP init if necessary.
1290 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1292 struct ixgbe_phy_info *phy = &hw->phy;
1295 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1297 hw->mac.ops.set_lan_id(hw);
1299 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1300 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1301 ixgbe_setup_mux_ctl(hw);
1304 /* Identify the PHY or SFP module */
1305 ret_val = phy->ops.identify(hw);
1306 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1309 /* Setup function pointers based on detected hardware */
1310 ixgbe_init_mac_link_ops_X550em(hw);
1311 if (phy->sfp_type != ixgbe_sfp_type_unknown)
1312 phy->ops.reset = NULL;
1314 /* Set functions pointers based on phy type */
1315 switch (hw->phy.type) {
1316 case ixgbe_phy_x550em_kx4:
1317 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
1318 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1319 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1321 case ixgbe_phy_x550em_kr:
1322 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1323 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1324 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1326 case ixgbe_phy_x550em_ext_t:
1327 phy->ops.setup_internal_link =
1328 ixgbe_setup_internal_phy_t_x550em;
1329 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1330 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1331 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1340 * ixgbe_reset_hw_X550em - Perform hardware reset
1341 * @hw: pointer to hardware structure
1343 * Resets the hardware by resetting the transmit and receive units, masks
1344 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1347 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1349 struct ixgbe_hic_hdr fw_cmd;
1350 ixgbe_link_speed link_speed;
1354 bool link_up = false;
1356 DEBUGFUNC("ixgbe_reset_hw_X550em");
1358 fw_cmd.cmd = FW_PHY_MGMT_REQ_CMD;
1360 fw_cmd.cmd_or_resp.cmd_resv = 0;
1361 fw_cmd.checksum = FW_DEFAULT_CHECKSUM;
1362 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
1364 IXGBE_HI_PHY_MGMT_REQ_TIMEOUT,
1367 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
1368 "PHY mgmt command failed with %d\n", status);
1369 else if (fw_cmd.cmd_or_resp.ret_status != FW_CEM_RESP_STATUS_SUCCESS)
1370 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
1371 "PHY mgmt command returned %d\n",
1372 fw_cmd.cmd_or_resp.ret_status);
1374 /* Call adapter stop to disable Tx/Rx and clear interrupts */
1375 status = hw->mac.ops.stop_adapter(hw);
1376 if (status != IXGBE_SUCCESS)
1379 /* flush pending Tx transactions */
1380 ixgbe_clear_tx_pending(hw);
1382 /* PHY ops must be identified and initialized prior to reset */
1384 /* Identify PHY and related function pointers */
1385 status = hw->phy.ops.init(hw);
1387 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1390 /* start the external PHY */
1391 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1392 status = ixgbe_init_ext_t_x550em(hw);
1397 /* Setup SFP module if there is one present. */
1398 if (hw->phy.sfp_setup_needed) {
1399 status = hw->mac.ops.setup_sfp(hw);
1400 hw->phy.sfp_setup_needed = false;
1403 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1407 if (!hw->phy.reset_disable && hw->phy.ops.reset)
1408 hw->phy.ops.reset(hw);
1411 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
1412 * If link reset is used when link is up, it might reset the PHY when
1413 * mng is using it. If link is down or the flag to force full link
1414 * reset is set, then perform link reset.
1416 ctrl = IXGBE_CTRL_LNK_RST;
1417 if (!hw->force_full_reset) {
1418 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1420 ctrl = IXGBE_CTRL_RST;
1423 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1424 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1425 IXGBE_WRITE_FLUSH(hw);
1427 /* Poll for reset bit to self-clear meaning reset is complete */
1428 for (i = 0; i < 10; i++) {
1430 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1431 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1435 if (ctrl & IXGBE_CTRL_RST_MASK) {
1436 status = IXGBE_ERR_RESET_FAILED;
1437 DEBUGOUT("Reset polling failed to complete.\n");
1442 /* Double resets are required for recovery from certain error
1443 * conditions. Between resets, it is necessary to stall to
1444 * allow time for any pending HW events to complete.
1446 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1447 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1451 /* Store the permanent mac address */
1452 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1454 /* Store MAC address from RAR0, clear receive address registers, and
1455 * clear the multicast table. Also reset num_rar_entries to 128,
1456 * since we modify this value when programming the SAN MAC address.
1458 hw->mac.num_rar_entries = 128;
1459 hw->mac.ops.init_rx_addrs(hw);
1462 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1463 ixgbe_setup_mux_ctl(hw);
1469 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1470 * @hw: pointer to hardware structure
1472 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1477 status = hw->phy.ops.read_reg(hw,
1478 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1479 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1482 if (status != IXGBE_SUCCESS)
1485 /* If PHY FW reset completed bit is set then this is the first
1486 * SW instance after a power on so the PHY FW must be un-stalled.
1488 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1489 status = hw->phy.ops.read_reg(hw,
1490 IXGBE_MDIO_GLOBAL_RES_PR_10,
1491 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1494 if (status != IXGBE_SUCCESS)
1497 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1499 status = hw->phy.ops.write_reg(hw,
1500 IXGBE_MDIO_GLOBAL_RES_PR_10,
1501 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1504 if (status != IXGBE_SUCCESS)
1512 * ixgbe_setup_kr_x550em - Configure the KR PHY.
1513 * @hw: pointer to hardware structure
1515 * Configures the integrated KR PHY.
1517 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1522 status = ixgbe_read_iosf_sb_reg_x550(hw,
1523 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1524 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1528 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1529 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ |
1530 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC);
1531 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1532 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1534 /* Advertise 10G support. */
1535 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1536 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1538 /* Advertise 1G support. */
1539 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1540 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1542 /* Restart auto-negotiation. */
1543 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1544 status = ixgbe_write_iosf_sb_reg_x550(hw,
1545 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1546 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1552 * ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1553 * @hw: pointer to hardware structure
1555 * Configures the integrated KX4 PHY.
1557 s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1562 status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1563 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, ®_val);
1567 reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1568 IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1570 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1572 /* Advertise 10G support. */
1573 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1574 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1576 /* Advertise 1G support. */
1577 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1578 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1580 /* Restart auto-negotiation. */
1581 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1582 status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1583 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, reg_val);
1589 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1590 * @hw: pointer to hardware structure
1591 * @speed: the link speed to force
1593 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
1594 * internal and external PHY at a specific speed, without autonegotiation.
1596 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1601 /* Disable AN and force speed to 10G Serial. */
1602 status = ixgbe_read_iosf_sb_reg_x550(hw,
1603 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1604 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1605 if (status != IXGBE_SUCCESS)
1608 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1609 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1611 /* Select forced link speed for internal PHY. */
1613 case IXGBE_LINK_SPEED_10GB_FULL:
1614 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1616 case IXGBE_LINK_SPEED_1GB_FULL:
1617 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1620 /* Other link speeds are not supported by internal KR PHY. */
1621 return IXGBE_ERR_LINK_SETUP;
1624 status = ixgbe_write_iosf_sb_reg_x550(hw,
1625 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1626 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1627 if (status != IXGBE_SUCCESS)
1630 /* Disable training protocol FSM. */
1631 status = ixgbe_read_iosf_sb_reg_x550(hw,
1632 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1633 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1634 if (status != IXGBE_SUCCESS)
1636 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1637 status = ixgbe_write_iosf_sb_reg_x550(hw,
1638 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1639 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1640 if (status != IXGBE_SUCCESS)
1643 /* Disable Flex from training TXFFE. */
1644 status = ixgbe_read_iosf_sb_reg_x550(hw,
1645 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1646 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1647 if (status != IXGBE_SUCCESS)
1649 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1650 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1651 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1652 status = ixgbe_write_iosf_sb_reg_x550(hw,
1653 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1654 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1655 if (status != IXGBE_SUCCESS)
1657 status = ixgbe_read_iosf_sb_reg_x550(hw,
1658 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1659 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1660 if (status != IXGBE_SUCCESS)
1662 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1663 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1664 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1665 status = ixgbe_write_iosf_sb_reg_x550(hw,
1666 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1667 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1668 if (status != IXGBE_SUCCESS)
1671 /* Enable override for coefficients. */
1672 status = ixgbe_read_iosf_sb_reg_x550(hw,
1673 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1674 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1675 if (status != IXGBE_SUCCESS)
1677 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1678 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1679 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1680 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1681 status = ixgbe_write_iosf_sb_reg_x550(hw,
1682 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1683 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1684 if (status != IXGBE_SUCCESS)
1687 /* Toggle port SW reset by AN reset. */
1688 status = ixgbe_read_iosf_sb_reg_x550(hw,
1689 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1690 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1691 if (status != IXGBE_SUCCESS)
1693 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1694 status = ixgbe_write_iosf_sb_reg_x550(hw,
1695 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1696 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1702 * ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
1703 * @hw: pointer to hardware structure
1705 * Configures the integrated KR PHY for SFP support.
1707 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1708 ixgbe_link_speed speed,
1709 bool autoneg_wait_to_complete)
1711 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1713 return ixgbe_setup_ixfi_x550em(hw, &speed);
1717 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1718 * @hw: point to hardware structure
1720 * Configures the link between the integrated KR PHY and the external X557 PHY
1721 * The driver will call this function when it gets a link status change
1722 * interrupt from the X557 PHY. This function configures the link speed
1723 * between the PHYs to match the link speed of the BASE-T link.
1725 * A return of a non-zero value indicates an error, and the base driver should
1726 * not report link up.
1728 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
1731 u16 autoneg_status, speed;
1732 ixgbe_link_speed force_speed;
1734 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1735 return IXGBE_ERR_CONFIG;
1737 /* read this twice back to back to indicate current status */
1738 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1739 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1741 if (status != IXGBE_SUCCESS)
1744 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1745 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1747 if (status != IXGBE_SUCCESS)
1750 /* If link is not up, then there is no setup necessary so return */
1751 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1752 return IXGBE_SUCCESS;
1754 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1755 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1758 /* clear everything but the speed and duplex bits */
1759 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1762 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1763 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1765 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1766 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1769 /* Internal PHY does not support anything else */
1770 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1773 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1777 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1778 * @hw: pointer to hardware structure
1780 * Configures the integrated KR PHY to use internal loopback mode.
1782 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1787 /* Disable AN and force speed to 10G Serial. */
1788 status = ixgbe_read_iosf_sb_reg_x550(hw,
1789 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1790 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1791 if (status != IXGBE_SUCCESS)
1793 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1794 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1795 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1796 status = ixgbe_write_iosf_sb_reg_x550(hw,
1797 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1798 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1799 if (status != IXGBE_SUCCESS)
1802 /* Set near-end loopback clocks. */
1803 status = ixgbe_read_iosf_sb_reg_x550(hw,
1804 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1805 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1806 if (status != IXGBE_SUCCESS)
1808 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1809 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1810 status = ixgbe_write_iosf_sb_reg_x550(hw,
1811 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1812 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1813 if (status != IXGBE_SUCCESS)
1816 /* Set loopback enable. */
1817 status = ixgbe_read_iosf_sb_reg_x550(hw,
1818 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1819 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1820 if (status != IXGBE_SUCCESS)
1822 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1823 status = ixgbe_write_iosf_sb_reg_x550(hw,
1824 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1825 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1826 if (status != IXGBE_SUCCESS)
1829 /* Training bypass. */
1830 status = ixgbe_read_iosf_sb_reg_x550(hw,
1831 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1832 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1833 if (status != IXGBE_SUCCESS)
1835 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
1836 status = ixgbe_write_iosf_sb_reg_x550(hw,
1837 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1838 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1844 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1845 * assuming that the semaphore is already obtained.
1846 * @hw: pointer to hardware structure
1847 * @offset: offset of word in the EEPROM to read
1848 * @data: word read from the EEPROM
1850 * Reads a 16 bit word from the EEPROM using the hostif.
1852 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1856 struct ixgbe_hic_read_shadow_ram buffer;
1858 DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
1859 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1860 buffer.hdr.req.buf_lenh = 0;
1861 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1862 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1864 /* convert offset from words to bytes */
1865 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1867 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1869 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1871 IXGBE_HI_COMMAND_TIMEOUT, false);
1876 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1877 FW_NVM_DATA_OFFSET);
1883 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1884 * @hw: pointer to hardware structure
1885 * @offset: offset of word in the EEPROM to read
1886 * @data: word read from the EEPROM
1888 * Reads a 16 bit word from the EEPROM using the hostif.
1890 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1893 s32 status = IXGBE_SUCCESS;
1895 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
1897 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1899 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
1900 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1902 status = IXGBE_ERR_SWFW_SYNC;
1909 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
1910 * @hw: pointer to hardware structure
1911 * @offset: offset of word in the EEPROM to read
1912 * @words: number of words
1913 * @data: word(s) read from the EEPROM
1915 * Reads a 16 bit word(s) from the EEPROM using the hostif.
1917 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1918 u16 offset, u16 words, u16 *data)
1920 struct ixgbe_hic_read_shadow_ram buffer;
1921 u32 current_word = 0;
1926 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
1928 /* Take semaphore for the entire operation. */
1929 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1931 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
1935 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
1936 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
1938 words_to_read = words;
1940 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1941 buffer.hdr.req.buf_lenh = 0;
1942 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1943 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1945 /* convert offset from words to bytes */
1946 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
1947 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
1949 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1951 IXGBE_HI_COMMAND_TIMEOUT,
1955 DEBUGOUT("Host interface command failed\n");
1959 for (i = 0; i < words_to_read; i++) {
1960 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
1962 u32 value = IXGBE_READ_REG(hw, reg);
1964 data[current_word] = (u16)(value & 0xffff);
1967 if (i < words_to_read) {
1969 data[current_word] = (u16)(value & 0xffff);
1973 words -= words_to_read;
1977 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1982 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1983 * @hw: pointer to hardware structure
1984 * @offset: offset of word in the EEPROM to write
1985 * @data: word write to the EEPROM
1987 * Write a 16 bit word to the EEPROM using the hostif.
1989 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1993 struct ixgbe_hic_write_shadow_ram buffer;
1995 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
1997 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
1998 buffer.hdr.req.buf_lenh = 0;
1999 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
2000 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2003 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2005 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2007 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2009 IXGBE_HI_COMMAND_TIMEOUT, false);
2015 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2016 * @hw: pointer to hardware structure
2017 * @offset: offset of word in the EEPROM to write
2018 * @data: word write to the EEPROM
2020 * Write a 16 bit word to the EEPROM using the hostif.
2022 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2025 s32 status = IXGBE_SUCCESS;
2027 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2029 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2031 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2032 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2034 DEBUGOUT("write ee hostif failed to get semaphore");
2035 status = IXGBE_ERR_SWFW_SYNC;
2042 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2043 * @hw: pointer to hardware structure
2044 * @offset: offset of word in the EEPROM to write
2045 * @words: number of words
2046 * @data: word(s) write to the EEPROM
2048 * Write a 16 bit word(s) to the EEPROM using the hostif.
2050 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2051 u16 offset, u16 words, u16 *data)
2053 s32 status = IXGBE_SUCCESS;
2056 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2058 /* Take semaphore for the entire operation. */
2059 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2060 if (status != IXGBE_SUCCESS) {
2061 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2065 for (i = 0; i < words; i++) {
2066 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2069 if (status != IXGBE_SUCCESS) {
2070 DEBUGOUT("Eeprom buffered write failed\n");
2075 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2082 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2083 * @hw: pointer to hardware structure
2084 * @ptr: pointer offset in eeprom
2085 * @size: size of section pointed by ptr, if 0 first word will be used as size
2086 * @csum: address of checksum to update
2088 * Returns error status for any failure
2090 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2091 u16 size, u16 *csum, u16 *buffer,
2096 u16 length, bufsz, i, start;
2099 bufsz = sizeof(buf) / sizeof(buf[0]);
2101 /* Read a chunk at the pointer location */
2103 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2105 DEBUGOUT("Failed to read EEPROM image\n");
2110 if (buffer_size < ptr)
2111 return IXGBE_ERR_PARAM;
2112 local_buffer = &buffer[ptr];
2120 length = local_buffer[0];
2122 /* Skip pointer section if length is invalid. */
2123 if (length == 0xFFFF || length == 0 ||
2124 (ptr + length) >= hw->eeprom.word_size)
2125 return IXGBE_SUCCESS;
2128 if (buffer && ((u32)start + (u32)length > buffer_size))
2129 return IXGBE_ERR_PARAM;
2131 for (i = start; length; i++, length--) {
2132 if (i == bufsz && !buffer) {
2138 /* Read a chunk at the pointer location */
2139 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2142 DEBUGOUT("Failed to read EEPROM image\n");
2146 *csum += local_buffer[i];
2148 return IXGBE_SUCCESS;
2152 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2153 * @hw: pointer to hardware structure
2154 * @buffer: pointer to buffer containing calculated checksum
2155 * @buffer_size: size of buffer
2157 * Returns a negative error code on error, or the 16-bit checksum
2159 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2161 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2165 u16 pointer, i, size;
2167 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2169 hw->eeprom.ops.init_params(hw);
2172 /* Read pointer area */
2173 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2174 IXGBE_EEPROM_LAST_WORD + 1,
2177 DEBUGOUT("Failed to read EEPROM image\n");
2180 local_buffer = eeprom_ptrs;
2182 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2183 return IXGBE_ERR_PARAM;
2184 local_buffer = buffer;
2188 * For X550 hardware include 0x0-0x41 in the checksum, skip the
2189 * checksum word itself
2191 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2192 if (i != IXGBE_EEPROM_CHECKSUM)
2193 checksum += local_buffer[i];
2196 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
2197 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2199 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2200 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2203 pointer = local_buffer[i];
2205 /* Skip pointer section if the pointer is invalid. */
2206 if (pointer == 0xFFFF || pointer == 0 ||
2207 pointer >= hw->eeprom.word_size)
2211 case IXGBE_PCIE_GENERAL_PTR:
2212 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2214 case IXGBE_PCIE_CONFIG0_PTR:
2215 case IXGBE_PCIE_CONFIG1_PTR:
2216 size = IXGBE_PCIE_CONFIG_SIZE;
2223 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2224 buffer, buffer_size);
2229 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2231 return (s32)checksum;
2235 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2236 * @hw: pointer to hardware structure
2238 * Returns a negative error code on error, or the 16-bit checksum
2240 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2242 return ixgbe_calc_checksum_X550(hw, NULL, 0);
2246 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2247 * @hw: pointer to hardware structure
2248 * @checksum_val: calculated checksum
2250 * Performs checksum calculation and validates the EEPROM checksum. If the
2251 * caller does not need checksum_val, the value can be NULL.
2253 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2257 u16 read_checksum = 0;
2259 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2261 /* Read the first word from the EEPROM. If this times out or fails, do
2262 * not continue or we could be in for a very long wait while every
2265 status = hw->eeprom.ops.read(hw, 0, &checksum);
2267 DEBUGOUT("EEPROM read failed\n");
2271 status = hw->eeprom.ops.calc_checksum(hw);
2275 checksum = (u16)(status & 0xffff);
2277 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2282 /* Verify read checksum from EEPROM is the same as
2283 * calculated checksum
2285 if (read_checksum != checksum) {
2286 status = IXGBE_ERR_EEPROM_CHECKSUM;
2287 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2288 "Invalid EEPROM checksum");
2291 /* If the user cares, return the calculated checksum */
2293 *checksum_val = checksum;
2299 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2300 * @hw: pointer to hardware structure
2302 * After writing EEPROM to shadow RAM using EEWR register, software calculates
2303 * checksum and updates the EEPROM and instructs the hardware to update
2306 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2311 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2313 /* Read the first word from the EEPROM. If this times out or fails, do
2314 * not continue or we could be in for a very long wait while every
2317 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2319 DEBUGOUT("EEPROM read failed\n");
2323 status = ixgbe_calc_eeprom_checksum_X550(hw);
2327 checksum = (u16)(status & 0xffff);
2329 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2334 status = ixgbe_update_flash_X550(hw);
2340 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2341 * @hw: pointer to hardware structure
2343 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2345 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2347 s32 status = IXGBE_SUCCESS;
2348 union ixgbe_hic_hdr2 buffer;
2350 DEBUGFUNC("ixgbe_update_flash_X550");
2352 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2353 buffer.req.buf_lenh = 0;
2354 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2355 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2357 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2359 IXGBE_HI_COMMAND_TIMEOUT, false);
2365 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2366 * @hw: pointer to hardware structure
2368 * Determines physical layer capabilities of the current configuration.
2370 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2372 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2373 u16 ext_ability = 0;
2375 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2377 hw->phy.ops.identify(hw);
2379 switch (hw->phy.type) {
2380 case ixgbe_phy_x550em_kr:
2381 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2382 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2384 case ixgbe_phy_x550em_kx4:
2385 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2386 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2388 case ixgbe_phy_x550em_ext_t:
2389 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2390 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2392 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2393 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2394 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2395 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2401 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2402 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2404 return physical_layer;
2408 * ixgbe_get_bus_info_x550em - Set PCI bus info
2409 * @hw: pointer to hardware structure
2411 * Sets bus link width and speed to unknown because X550em is
2414 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2417 DEBUGFUNC("ixgbe_get_bus_info_x550em");
2419 hw->bus.width = ixgbe_bus_width_unknown;
2420 hw->bus.speed = ixgbe_bus_speed_unknown;
2422 hw->mac.ops.set_lan_id(hw);
2424 return IXGBE_SUCCESS;
2428 * ixgbe_disable_rx_x550 - Disable RX unit
2430 * Enables the Rx DMA unit for x550
2432 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2434 u32 rxctrl, pfdtxgswc;
2436 struct ixgbe_hic_disable_rxen fw_cmd;
2438 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2440 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2441 if (rxctrl & IXGBE_RXCTRL_RXEN) {
2442 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2443 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2444 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2445 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2446 hw->mac.set_lben = true;
2448 hw->mac.set_lben = false;
2451 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2452 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2453 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2454 fw_cmd.port_number = (u8)hw->bus.lan_id;
2456 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2457 sizeof(struct ixgbe_hic_disable_rxen),
2458 IXGBE_HI_COMMAND_TIMEOUT, true);
2460 /* If we fail - disable RX using register write */
2462 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2463 if (rxctrl & IXGBE_RXCTRL_RXEN) {
2464 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2465 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2472 * ixgbe_enter_lplu_x550em - Transition to low power states
2473 * @hw: pointer to hardware structure
2475 * Configures Low Power Link Up on transition to low power states
2476 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2477 * X557 PHY immediately prior to entering LPLU.
2479 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2481 u16 autoneg_status, an_10g_cntl_reg, autoneg_reg, speed;
2483 ixgbe_link_speed lcd_speed;
2486 /* If blocked by MNG FW, then don't restart AN */
2487 if (ixgbe_check_reset_blocked(hw))
2488 return IXGBE_SUCCESS;
2490 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2491 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2494 if (status != IXGBE_SUCCESS)
2497 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2499 if (status != IXGBE_SUCCESS)
2502 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2503 * disabled, then force link down by entering low power mode.
2505 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS) ||
2506 !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2507 !(hw->wol_enabled || ixgbe_mng_present(hw)))
2508 return ixgbe_set_copper_phy_power(hw, FALSE);
2511 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2513 if (status != IXGBE_SUCCESS)
2516 /* If no valid LCD link speed, then force link down and exit. */
2517 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2518 return ixgbe_set_copper_phy_power(hw, FALSE);
2520 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2521 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2524 if (status != IXGBE_SUCCESS)
2527 /* clear everything but the speed bits */
2528 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2530 /* If current speed is already LCD, then exit. */
2531 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2532 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2533 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2534 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2537 /* Clear AN completed indication */
2538 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2539 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2542 if (status != IXGBE_SUCCESS)
2545 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2546 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2549 if (status != IXGBE_SUCCESS)
2552 status = hw->phy.ops.read_reg(hw,
2553 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2554 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2557 if (status != IXGBE_SUCCESS)
2560 save_autoneg = hw->phy.autoneg_advertised;
2562 /* Setup link at least common link speed */
2563 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
2565 /* restore autoneg from before setting lplu speed */
2566 hw->phy.autoneg_advertised = save_autoneg;
2572 * ixgbe_get_lcd_x550em - Determine lowest common denominator
2573 * @hw: pointer to hardware structure
2574 * @lcd_speed: pointer to lowest common link speed
2576 * Determine lowest common link speed with link partner.
2578 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2582 u16 word = hw->eeprom.ctrl_word_3;
2584 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2586 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2587 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2590 if (status != IXGBE_SUCCESS)
2593 /* If link partner advertised 1G, return 1G */
2594 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2595 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2599 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2600 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2601 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2604 /* Link partner not capable of lower speeds, return 10G */
2605 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2610 * ixgbe_setup_fc_X550em - Set up flow control
2611 * @hw: pointer to hardware structure
2613 * Called at init time to set up flow control.
2615 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
2617 s32 ret_val = IXGBE_SUCCESS;
2618 u32 pause, asm_dir, reg_val;
2620 DEBUGFUNC("ixgbe_setup_fc_X550em");
2622 /* Validate the requested mode */
2623 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2624 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2625 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2626 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2630 /* 10gig parts do not have a word in the EEPROM to determine the
2631 * default flow control setting, so we explicitly set it to full.
2633 if (hw->fc.requested_mode == ixgbe_fc_default)
2634 hw->fc.requested_mode = ixgbe_fc_full;
2636 /* Determine PAUSE and ASM_DIR bits. */
2637 switch (hw->fc.requested_mode) {
2642 case ixgbe_fc_tx_pause:
2646 case ixgbe_fc_rx_pause:
2647 /* Rx Flow control is enabled and Tx Flow control is
2648 * disabled by software override. Since there really
2649 * isn't a way to advertise that we are capable of RX
2650 * Pause ONLY, we will advertise that we support both
2651 * symmetric and asymmetric Rx PAUSE, as such we fall
2652 * through to the fc_full statement. Later, we will
2653 * disable the adapter's ability to send PAUSE frames.
2660 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2661 "Flow control param set incorrectly\n");
2662 ret_val = IXGBE_ERR_CONFIG;
2666 if (hw->phy.media_type == ixgbe_media_type_backplane) {
2667 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
2668 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2669 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2670 if (ret_val != IXGBE_SUCCESS)
2672 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2673 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2675 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2677 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2678 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
2679 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2680 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2682 /* Not all devices fully support AN. */
2683 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR)
2684 hw->fc.disable_fc_autoneg = true;
2692 * ixgbe_set_mux - Set mux for port 1 access with CS4227
2693 * @hw: pointer to hardware structure
2694 * @state: set mux if 1, clear if 0
2696 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2700 if (!hw->bus.lan_id)
2702 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2704 esdp |= IXGBE_ESDP_SDP1;
2706 esdp &= ~IXGBE_ESDP_SDP1;
2707 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2708 IXGBE_WRITE_FLUSH(hw);
2712 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2713 * @hw: pointer to hardware structure
2714 * @mask: Mask to specify which semaphore to acquire
2716 * Acquires the SWFW semaphore and sets the I2C MUX
2718 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2722 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
2724 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2728 if (mask & IXGBE_GSSR_I2C_MASK)
2729 ixgbe_set_mux(hw, 1);
2731 return IXGBE_SUCCESS;
2735 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2736 * @hw: pointer to hardware structure
2737 * @mask: Mask to specify which semaphore to release
2739 * Releases the SWFW semaphore and sets the I2C MUX
2741 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2743 DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
2745 if (mask & IXGBE_GSSR_I2C_MASK)
2746 ixgbe_set_mux(hw, 0);
2748 ixgbe_release_swfw_sync_X540(hw, mask);
2752 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2753 * @hw: pointer to hardware structure
2755 * Handle external Base T PHY interrupt. If high temperature
2756 * failure alarm then return error, else if link status change
2757 * then setup internal/external PHY link
2759 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2760 * failure alarm, else return PHY access status.
2762 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2767 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2769 if (status != IXGBE_SUCCESS)
2773 return ixgbe_setup_internal_phy_t_x550em(hw);
2775 return IXGBE_SUCCESS;
2779 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
2780 * @hw: pointer to hardware structure
2781 * @speed: new link speed
2782 * @autoneg_wait_to_complete: true when waiting for completion is needed
2784 * Setup internal/external PHY link speed based on link speed, then set
2785 * external PHY auto advertised link speed.
2787 * Returns error status for any failure
2789 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
2790 ixgbe_link_speed speed,
2791 bool autoneg_wait_to_complete)
2794 ixgbe_link_speed force_speed;
2796 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
2798 /* Setup internal/external PHY link speed to iXFI (10G), unless
2799 * only 1G is auto advertised then setup KX link.
2801 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2802 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2804 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2806 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
2808 if (status != IXGBE_SUCCESS)
2811 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
2815 * ixgbe_check_link_t_X550em - Determine link and speed status
2816 * @hw: pointer to hardware structure
2817 * @speed: pointer to link speed
2818 * @link_up: true when link is up
2819 * @link_up_wait_to_complete: bool used to wait for link up or not
2821 * Check that both the MAC and X557 external PHY have link.
2823 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
2824 bool *link_up, bool link_up_wait_to_complete)
2829 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2830 return IXGBE_ERR_CONFIG;
2832 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
2833 link_up_wait_to_complete);
2835 /* If check link fails or MAC link is not up, then return */
2836 if (status != IXGBE_SUCCESS || !(*link_up))
2839 /* MAC link is up, so check external PHY link.
2840 * Read this twice back to back to indicate current status.
2842 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2843 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2846 if (status != IXGBE_SUCCESS)
2849 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2850 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2853 if (status != IXGBE_SUCCESS)
2856 /* If external PHY link is not up, then indicate link not up */
2857 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
2860 return IXGBE_SUCCESS;
2864 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
2865 * @hw: pointer to hardware structure
2867 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
2871 status = ixgbe_reset_phy_generic(hw);
2873 if (status != IXGBE_SUCCESS)
2876 /* Configure Link Status Alarm and Temperature Threshold interrupts */
2877 return ixgbe_enable_lasi_ext_t_x550em(hw);