drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  44 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw);
  45
  46 /**
  47  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  48  *  @hw: pointer to hardware structure
  49  *
  50  *  Initialize the function pointers and assign the MAC type for X550.
  51  *  Does not touch the hardware.
  52  **/
  53 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  54 {
  55         struct ixgbe_mac_info *mac = &hw->mac;
  56         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  57         s32 ret_val;
  58
  59         DEBUGFUNC("ixgbe_init_ops_X550");
  60
  61         ret_val = ixgbe_init_ops_X540(hw);
  62         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  63         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  64         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  65         mac->ops.setup_eee = NULL;
  66         mac->ops.set_source_address_pruning =
  67                         ixgbe_set_source_address_pruning_X550;
  68         mac->ops.set_ethertype_anti_spoofing =
  69                         ixgbe_set_ethertype_anti_spoofing_X550;
  70
  71         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  72         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  73         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  74         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  75         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  76         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  77         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  78         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  79         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  80
  81         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  82         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  83         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  84         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  85         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  86         /* Manageability interface */
  87         mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_x550;
  88         switch (hw->device_id) {
  89         case IXGBE_DEV_ID_X550EM_X_10G_T:
  90         case IXGBE_DEV_ID_X550EM_A_10G_T:
  91                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  92                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  93                 break;
  94         default:
  95                 break;
  96         }
  97         return ret_val;
  98 }
  99
 100 /**
 101  * ixgbe_read_cs4227 - Read CS4227 register
 102  * @hw: pointer to hardware structure
 103  * @reg: register number to write
 104  * @value: pointer to receive value read
 105  *
 106  * Returns status code
 107  **/
 108 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
 109 {
 110         return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
 111 }
 112
 113 /**
 114  * ixgbe_write_cs4227 - Write CS4227 register
 115  * @hw: pointer to hardware structure
 116  * @reg: register number to write
 117  * @value: value to write to register
 118  *
 119  * Returns status code
 120  **/
 121 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 122 {
 123         return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
 124 }
 125
 126 /**
 127  * ixgbe_read_pe - Read register from port expander
 128  * @hw: pointer to hardware structure
 129  * @reg: register number to read
 130  * @value: pointer to receive read value
 131  *
 132  * Returns status code
 133  **/
 134 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 135 {
 136         s32 status;
 137
 138         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 139         if (status != IXGBE_SUCCESS)
 140                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 141                               "port expander access failed with %d\n", status);
 142         return status;
 143 }
 144
 145 /**
 146  * ixgbe_write_pe - Write register to port expander
 147  * @hw: pointer to hardware structure
 148  * @reg: register number to write
 149  * @value: value to write
 150  *
 151  * Returns status code
 152  **/
 153 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 154 {
 155         s32 status;
 156
 157         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 158         if (status != IXGBE_SUCCESS)
 159                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 160                               "port expander access failed with %d\n", status);
 161         return status;
 162 }
 163
 164 /**
 165  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 166  * @hw: pointer to hardware structure
 167  *
 168  * This function assumes that the caller has acquired the proper semaphore.
 169  * Returns error code
 170  **/
 171 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 172 {
 173         s32 status;
 174         u32 retry;
 175         u16 value;
 176         u8 reg;
 177
 178         /* Trigger hard reset. */
 179         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 180         if (status != IXGBE_SUCCESS)
 181                 return status;
 182         reg |= IXGBE_PE_BIT1;
 183         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 184         if (status != IXGBE_SUCCESS)
 185                 return status;
 186
 187         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 188         if (status != IXGBE_SUCCESS)
 189                 return status;
 190         reg &= ~IXGBE_PE_BIT1;
 191         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 192         if (status != IXGBE_SUCCESS)
 193                 return status;
 194
 195         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 196         if (status != IXGBE_SUCCESS)
 197                 return status;
 198         reg &= ~IXGBE_PE_BIT1;
 199         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 200         if (status != IXGBE_SUCCESS)
 201                 return status;
 202
 203         usec_delay(IXGBE_CS4227_RESET_HOLD);
 204
 205         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 206         if (status != IXGBE_SUCCESS)
 207                 return status;
 208         reg |= IXGBE_PE_BIT1;
 209         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 210         if (status != IXGBE_SUCCESS)
 211                 return status;
 212
 213         /* Wait for the reset to complete. */
 214         msec_delay(IXGBE_CS4227_RESET_DELAY);
 215         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 216                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 217                                            &value);
 218                 if (status == IXGBE_SUCCESS &&
 219                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 220                         break;
 221                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 222         }
 223         if (retry == IXGBE_CS4227_RETRIES) {
 224                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 225                         "CS4227 reset did not complete.");
 226                 return IXGBE_ERR_PHY;
 227         }
 228
 229         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 230         if (status != IXGBE_SUCCESS ||
 231             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 232                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 233                         "CS4227 EEPROM did not load successfully.");
 234                 return IXGBE_ERR_PHY;
 235         }
 236
 237         return IXGBE_SUCCESS;
 238 }
 239
 240 /**
 241  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 242  * @hw: pointer to hardware structure
 243  **/
 244 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 245 {
 246         s32 status = IXGBE_SUCCESS;
 247         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 248         u16 value = 0;
 249         u8 retry;
 250
 251         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 252                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 253                 if (status != IXGBE_SUCCESS) {
 254                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 255                                 "semaphore failed with %d", status);
 256                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 257                         continue;
 258                 }
 259
 260                 /* Get status of reset flow. */
 261                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 262
 263                 if (status == IXGBE_SUCCESS &&
 264                     value == IXGBE_CS4227_RESET_COMPLETE)
 265                         goto out;
 266
 267                 if (status != IXGBE_SUCCESS ||
 268                     value != IXGBE_CS4227_RESET_PENDING)
 269                         break;
 270
 271                 /* Reset is pending. Wait and check again. */
 272                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 273                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 274         }
 275
 276         /* If still pending, assume other instance failed. */
 277         if (retry == IXGBE_CS4227_RETRIES) {
 278                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 279                 if (status != IXGBE_SUCCESS) {
 280                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 281                                       "semaphore failed with %d", status);
 282                         return;
 283                 }
 284         }
 285
 286         /* Reset the CS4227. */
 287         status = ixgbe_reset_cs4227(hw);
 288         if (status != IXGBE_SUCCESS) {
 289                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 290                         "CS4227 reset failed: %d", status);
 291                 goto out;
 292         }
 293
 294         /* Reset takes so long, temporarily release semaphore in case the
 295          * other driver instance is waiting for the reset indication.
 296          */
 297         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 298                            IXGBE_CS4227_RESET_PENDING);
 299         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 300         msec_delay(10);
 301         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 302         if (status != IXGBE_SUCCESS) {
 303                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 304                         "semaphore failed with %d", status);
 305                 return;
 306         }
 307
 308         /* Record completion for next time. */
 309         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 310                 IXGBE_CS4227_RESET_COMPLETE);
 311
 312 out:
 313         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 314         msec_delay(hw->eeprom.semaphore_delay);
 315 }
 316
 317 /**
 318  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 319  * @hw: pointer to hardware structure
 320  **/
 321 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 322 {
 323         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 324
 325         if (hw->bus.lan_id) {
 326                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 327                 esdp |= IXGBE_ESDP_SDP1_DIR;
 328         }
 329         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 330         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 331         IXGBE_WRITE_FLUSH(hw);
 332 }
 333
 334 /**
 335  * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
 336  * @hw: pointer to hardware structure
 337  * @reg_addr: 32 bit address of PHY register to read
 338  * @dev_type: always unused
 339  * @phy_data: Pointer to read data from PHY register
 340  */
 341 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 342                                      u32 dev_type, u16 *phy_data)
 343 {
 344         u32 i, data, command;
 345         UNREFERENCED_1PARAMETER(dev_type);
 346
 347         /* Setup and write the read command */
 348         command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 349                   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 350                   IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
 351                   IXGBE_MSCA_MDI_COMMAND;
 352
 353         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 354
 355         /* Check every 10 usec to see if the access completed.
 356          * The MDI Command bit will clear when the operation is
 357          * complete
 358          */
 359         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 360                 usec_delay(10);
 361
 362                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 363                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 364                         break;
 365         }
 366
 367         if (command & IXGBE_MSCA_MDI_COMMAND) {
 368                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 369                               "PHY read command did not complete.\n");
 370                 return IXGBE_ERR_PHY;
 371         }
 372
 373         /* Read operation is complete.  Get the data from MSRWD */
 374         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 375         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 376         *phy_data = (u16)data;
 377
 378         return IXGBE_SUCCESS;
 379 }
 380
 381 /**
 382  * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
 383  * @hw: pointer to hardware structure
 384  * @reg_addr: 32 bit PHY register to write
 385  * @dev_type: always unused
 386  * @phy_data: Data to write to the PHY register
 387  */
 388 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 389                                       u32 dev_type, u16 phy_data)
 390 {
 391         u32 i, command;
 392         UNREFERENCED_1PARAMETER(dev_type);
 393
 394         /* Put the data in the MDI single read and write data register*/
 395         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 396
 397         /* Setup and write the write command */
 398         command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 399                   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 400                   IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
 401                   IXGBE_MSCA_MDI_COMMAND;
 402
 403         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 404
 405         /* Check every 10 usec to see if the access completed.
 406          * The MDI Command bit will clear when the operation is
 407          * complete
 408          */
 409         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 410                 usec_delay(10);
 411
 412                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 413                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 414                         break;
 415         }
 416
 417         if (command & IXGBE_MSCA_MDI_COMMAND) {
 418                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 419                               "PHY write cmd didn't complete\n");
 420                 return IXGBE_ERR_PHY;
 421         }
 422
 423         return IXGBE_SUCCESS;
 424 }
 425
 426 /**
 427  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 428  * @hw: pointer to hardware structure
 429  *
 430  * Returns error code
 431  */
 432 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 433 {
 434         hw->mac.ops.set_lan_id(hw);
 435
 436         ixgbe_read_mng_if_sel_x550em(hw);
 437
 438         switch (hw->device_id) {
 439         case IXGBE_DEV_ID_X550EM_A_SFP:
 440                 return ixgbe_identify_module_generic(hw);
 441         case IXGBE_DEV_ID_X550EM_X_SFP:
 442                 /* set up for CS4227 usage */
 443                 ixgbe_setup_mux_ctl(hw);
 444                 ixgbe_check_cs4227(hw);
 445                 /* Fallthrough */
 446
 447         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 448                 return ixgbe_identify_module_generic(hw);
 449                 break;
 450         case IXGBE_DEV_ID_X550EM_X_KX4:
 451                 hw->phy.type = ixgbe_phy_x550em_kx4;
 452                 break;
 453         case IXGBE_DEV_ID_X550EM_X_XFI:
 454                 hw->phy.type = ixgbe_phy_x550em_xfi;
 455                 break;
 456         case IXGBE_DEV_ID_X550EM_X_KR:
 457         case IXGBE_DEV_ID_X550EM_A_KR:
 458         case IXGBE_DEV_ID_X550EM_A_KR_L:
 459                 hw->phy.type = ixgbe_phy_x550em_kr;
 460                 break;
 461         case IXGBE_DEV_ID_X550EM_A_10G_T:
 462         case IXGBE_DEV_ID_X550EM_X_1G_T:
 463         case IXGBE_DEV_ID_X550EM_X_10G_T:
 464                 return ixgbe_identify_phy_generic(hw);
 465         case IXGBE_DEV_ID_X550EM_A_1G_T:
 466         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 467                 hw->phy.type = ixgbe_phy_fw;
 468                 hw->phy.ops.read_reg = NULL;
 469                 hw->phy.ops.write_reg = NULL;
 470                 if (hw->bus.lan_id)
 471                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 472                 else
 473                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 474                 break;
 475         default:
 476                 break;
 477         }
 478         return IXGBE_SUCCESS;
 479 }
 480
 481 /**
 482  * ixgbe_fw_phy_activity - Perform an activity on a PHY
 483  * @hw: pointer to hardware structure
 484  * @activity: activity to perform
 485  * @data: Pointer to 4 32-bit words of data
 486  */
 487 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,
 488                           u32 (*data)[FW_PHY_ACT_DATA_COUNT])
 489 {
 490         union {
 491                 struct ixgbe_hic_phy_activity_req cmd;
 492                 struct ixgbe_hic_phy_activity_resp rsp;
 493         } hic;
 494         u16 retries = FW_PHY_ACT_RETRIES;
 495         s32 rc;
 496         u16 i;
 497
 498         do {
 499                 memset(&hic, 0, sizeof(hic));
 500                 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD;
 501                 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN;
 502                 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 503                 hic.cmd.port_number = hw->bus.lan_id;
 504                 hic.cmd.activity_id = IXGBE_CPU_TO_LE16(activity);
 505                 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
 506                         hic.cmd.data[i] = IXGBE_CPU_TO_BE32((*data)[i]);
 507
 508                 rc = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
 509                                                   sizeof(hic.cmd),
 510                                                   IXGBE_HI_COMMAND_TIMEOUT,
 511                                                   true);
 512                 if (rc != IXGBE_SUCCESS)
 513                         return rc;
 514                 if (hic.rsp.hdr.cmd_or_resp.ret_status ==
 515                     FW_CEM_RESP_STATUS_SUCCESS) {
 516                         for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
 517                                 (*data)[i] = IXGBE_BE32_TO_CPU(hic.rsp.data[i]);
 518                         return IXGBE_SUCCESS;
 519                 }
 520                 usec_delay(20);
 521                 --retries;
 522         } while (retries > 0);
 523
 524         return IXGBE_ERR_HOST_INTERFACE_COMMAND;
 525 }
 526
 527 static const struct {
 528         u16 fw_speed;
 529         ixgbe_link_speed phy_speed;
 530 } ixgbe_fw_map[] = {
 531         { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL },
 532         { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL },
 533         { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL },
 534         { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL },
 535         { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL },
 536         { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL },
 537 };
 538
 539 /**
 540  * ixgbe_get_phy_id_fw - Get the phy ID via firmware command
 541  * @hw: pointer to hardware structure
 542  *
 543  * Returns error code
 544  */
 545 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw)
 546 {
 547         u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
 548         u16 phy_speeds;
 549         u16 phy_id_lo;
 550         s32 rc;
 551         u16 i;
 552
 553         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info);
 554         if (rc)
 555                 return rc;
 556
 557         hw->phy.speeds_supported = 0;
 558         phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK;
 559         for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
 560                 if (phy_speeds & ixgbe_fw_map[i].fw_speed)
 561                         hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed;
 562         }
 563         if (!hw->phy.autoneg_advertised)
 564                 hw->phy.autoneg_advertised = hw->phy.speeds_supported;
 565
 566         hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK;
 567         phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK;
 568         hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK;
 569         hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK;
 570         if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK)
 571                 return IXGBE_ERR_PHY_ADDR_INVALID;
 572         return IXGBE_SUCCESS;
 573 }
 574
 575 /**
 576  * ixgbe_identify_phy_fw - Get PHY type based on firmware command
 577  * @hw: pointer to hardware structure
 578  *
 579  * Returns error code
 580  */
 581 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw)
 582 {
 583         if (hw->bus.lan_id)
 584                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 585         else
 586                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 587
 588         hw->phy.type = ixgbe_phy_fw;
 589         hw->phy.ops.read_reg = NULL;
 590         hw->phy.ops.write_reg = NULL;
 591         return ixgbe_get_phy_id_fw(hw);
 592 }
 593
 594 /**
 595  * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY
 596  * @hw: pointer to hardware structure
 597  *
 598  * Returns error code
 599  */
 600 s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw)
 601 {
 602         u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
 603
 604         setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF;
 605         return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup);
 606 }
 607
 608 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 609                                      u32 device_type, u16 *phy_data)
 610 {
 611         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 612         return IXGBE_NOT_IMPLEMENTED;
 613 }
 614
 615 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 616                                       u32 device_type, u16 phy_data)
 617 {
 618         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 619         return IXGBE_NOT_IMPLEMENTED;
 620 }
 621
 622 /**
 623  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 624  * @hw: pointer to the hardware structure
 625  * @addr: I2C bus address to read from
 626  * @reg: I2C device register to read from
 627  * @val: pointer to location to receive read value
 628  *
 629  * Returns an error code on error.
 630  **/
 631 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 632                                            u16 reg, u16 *val)
 633 {
 634         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 635 }
 636
 637 /**
 638  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 639  * @hw: pointer to the hardware structure
 640  * @addr: I2C bus address to read from
 641  * @reg: I2C device register to read from
 642  * @val: pointer to location to receive read value
 643  *
 644  * Returns an error code on error.
 645  **/
 646 STATIC s32
 647 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 648                                          u16 reg, u16 *val)
 649 {
 650         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 651 }
 652
 653 /**
 654  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 655  * @hw: pointer to the hardware structure
 656  * @addr: I2C bus address to write to
 657  * @reg: I2C device register to write to
 658  * @val: value to write
 659  *
 660  * Returns an error code on error.
 661  **/
 662 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 663                                             u8 addr, u16 reg, u16 val)
 664 {
 665         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 666 }
 667
 668 /**
 669  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 670  * @hw: pointer to the hardware structure
 671  * @addr: I2C bus address to write to
 672  * @reg: I2C device register to write to
 673  * @val: value to write
 674  *
 675  * Returns an error code on error.
 676  **/
 677 STATIC s32
 678 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 679                                           u8 addr, u16 reg, u16 val)
 680 {
 681         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 682 }
 683
 684 /**
 685 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 686 *  @hw: pointer to hardware structure
 687 *
 688 *  Initialize the function pointers and for MAC type X550EM.
 689 *  Does not touch the hardware.
 690 **/
 691 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 692 {
 693         struct ixgbe_mac_info *mac = &hw->mac;
 694         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 695         struct ixgbe_phy_info *phy = &hw->phy;
 696         s32 ret_val;
 697
 698         DEBUGFUNC("ixgbe_init_ops_X550EM");
 699
 700         /* Similar to X550 so start there. */
 701         ret_val = ixgbe_init_ops_X550(hw);
 702
 703         /* Since this function eventually calls
 704          * ixgbe_init_ops_540 by design, we are setting
 705          * the pointers to NULL explicitly here to overwrite
 706          * the values being set in the x540 function.
 707          */
 708         /* Thermal sensor not supported in x550EM */
 709         mac->ops.get_thermal_sensor_data = NULL;
 710         mac->ops.init_thermal_sensor_thresh = NULL;
 711         mac->thermal_sensor_enabled = false;
 712
 713         /* FCOE not supported in x550EM */
 714         mac->ops.get_san_mac_addr = NULL;
 715         mac->ops.set_san_mac_addr = NULL;
 716         mac->ops.get_wwn_prefix = NULL;
 717         mac->ops.get_fcoe_boot_status = NULL;
 718
 719         /* IPsec not supported in x550EM */
 720         mac->ops.disable_sec_rx_path = NULL;
 721         mac->ops.enable_sec_rx_path = NULL;
 722
 723         /* AUTOC register is not present in x550EM. */
 724         mac->ops.prot_autoc_read = NULL;
 725         mac->ops.prot_autoc_write = NULL;
 726
 727         /* X550EM bus type is internal*/
 728         hw->bus.type = ixgbe_bus_type_internal;
 729         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 730
 731
 732         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 733         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 734         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 735         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 736         mac->ops.get_supported_physical_layer =
 737                                     ixgbe_get_supported_physical_layer_X550em;
 738
 739         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 740                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 741         else
 742                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 743
 744         /* PHY */
 745         phy->ops.init = ixgbe_init_phy_ops_X550em;
 746         switch (hw->device_id) {
 747         case IXGBE_DEV_ID_X550EM_A_1G_T:
 748         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 749                 mac->ops.setup_fc = NULL;
 750                 phy->ops.identify = ixgbe_identify_phy_fw;
 751                 phy->ops.set_phy_power = NULL;
 752                 phy->ops.get_firmware_version = NULL;
 753                 break;
 754         default:
 755                 phy->ops.identify = ixgbe_identify_phy_x550em;
 756         }
 757
 758         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 759                 phy->ops.set_phy_power = NULL;
 760
 761
 762         /* EEPROM */
 763         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 764         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 765         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 766         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 767         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 768         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 769         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 770         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 771
 772         return ret_val;
 773 }
 774
 775 /**
 776  * ixgbe_setup_fw_link - Setup firmware-controlled PHYs
 777  * @hw: pointer to hardware structure
 778  */
 779 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw)
 780 {
 781         u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
 782         s32 rc;
 783         u16 i;
 784
 785         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
 786                 return 0;
 787
 788         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
 789                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
 790                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
 791                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
 792         }
 793
 794         switch (hw->fc.requested_mode) {
 795         case ixgbe_fc_full:
 796                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX <<
 797                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 798                 break;
 799         case ixgbe_fc_rx_pause:
 800                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX <<
 801                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 802                 break;
 803         case ixgbe_fc_tx_pause:
 804                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX <<
 805                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 806                 break;
 807         default:
 808                 break;
 809         }
 810
 811         for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
 812                 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)
 813                         setup[0] |= ixgbe_fw_map[i].fw_speed;
 814         }
 815         setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN;
 816
 817         if (hw->phy.eee_speeds_advertised)
 818                 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE;
 819
 820         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup);
 821         if (rc)
 822                 return rc;
 823         if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN)
 824                 return IXGBE_ERR_OVERTEMP;
 825         return IXGBE_SUCCESS;
 826 }
 827
 828 /**
 829  * ixgbe_fc_autoneg_fw _ Set up flow control for FW-controlled PHYs
 830  * @hw: pointer to hardware structure
 831  *
 832  *  Called at init time to set up flow control.
 833  */
 834 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw)
 835 {
 836         if (hw->fc.requested_mode == ixgbe_fc_default)
 837                 hw->fc.requested_mode = ixgbe_fc_full;
 838
 839         return ixgbe_setup_fw_link(hw);
 840 }
 841
 842 /**
 843  * ixgbe_setup_eee_fw - Enable/disable EEE support
 844  * @hw: pointer to the HW structure
 845  * @enable_eee: boolean flag to enable EEE
 846  *
 847  * Enable/disable EEE based on enable_eee flag.
 848  * This function controls EEE for firmware-based PHY implementations.
 849  */
 850 static s32 ixgbe_setup_eee_fw(struct ixgbe_hw *hw, bool enable_eee)
 851 {
 852         if (!!hw->phy.eee_speeds_advertised == enable_eee)
 853                 return IXGBE_SUCCESS;
 854         if (enable_eee)
 855                 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
 856         else
 857                 hw->phy.eee_speeds_advertised = 0;
 858         return hw->phy.ops.setup_link(hw);
 859 }
 860
 861 /**
 862 *  ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
 863 *  @hw: pointer to hardware structure
 864 *
 865 *  Initialize the function pointers and for MAC type X550EM_a.
 866 *  Does not touch the hardware.
 867 **/
 868 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
 869 {
 870         struct ixgbe_mac_info *mac = &hw->mac;
 871         s32 ret_val;
 872
 873         DEBUGFUNC("ixgbe_init_ops_X550EM_a");
 874
 875         /* Start with generic X550EM init */
 876         ret_val = ixgbe_init_ops_X550EM(hw);
 877
 878         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
 879             hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) {
 880                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 881                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 882         } else {
 883                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
 884                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
 885         }
 886         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
 887         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
 888
 889         switch (mac->ops.get_media_type(hw)) {
 890         case ixgbe_media_type_fiber:
 891                 mac->ops.setup_fc = NULL;
 892                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
 893                 break;
 894         case ixgbe_media_type_backplane:
 895                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
 896                 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
 897                 break;
 898         default:
 899                 break;
 900         }
 901
 902         switch (hw->device_id) {
 903         case IXGBE_DEV_ID_X550EM_A_1G_T:
 904         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 905                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
 906                 mac->ops.setup_fc = ixgbe_fc_autoneg_fw;
 907                 mac->ops.setup_eee = ixgbe_setup_eee_fw;
 908                 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL |
 909                                                IXGBE_LINK_SPEED_1GB_FULL;
 910                 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
 911                 break;
 912         default:
 913                 break;
 914         }
 915
 916         return ret_val;
 917 }
 918
 919 /**
 920 *  ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
 921 *  @hw: pointer to hardware structure
 922 *
 923 *  Initialize the function pointers and for MAC type X550EM_x.
 924 *  Does not touch the hardware.
 925 **/
 926 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
 927 {
 928         struct ixgbe_mac_info *mac = &hw->mac;
 929         struct ixgbe_link_info *link = &hw->link;
 930         s32 ret_val;
 931
 932         DEBUGFUNC("ixgbe_init_ops_X550EM_x");
 933
 934         /* Start with generic X550EM init */
 935         ret_val = ixgbe_init_ops_X550EM(hw);
 936
 937         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 938         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 939         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 940         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 941         link->ops.read_link = ixgbe_read_i2c_combined_generic;
 942         link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
 943         link->ops.write_link = ixgbe_write_i2c_combined_generic;
 944         link->ops.write_link_unlocked =
 945                                       ixgbe_write_i2c_combined_generic_unlocked;
 946         link->addr = IXGBE_CS4227;
 947
 948
 949         return ret_val;
 950 }
 951
 952 /**
 953  *  ixgbe_dmac_config_X550
 954  *  @hw: pointer to hardware structure
 955  *
 956  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 957  *  When disabling dmac, dmac enable dmac bit is cleared.
 958  **/
 959 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 960 {
 961         u32 reg, high_pri_tc;
 962
 963         DEBUGFUNC("ixgbe_dmac_config_X550");
 964
 965         /* Disable DMA coalescing before configuring */
 966         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 967         reg &= ~IXGBE_DMACR_DMAC_EN;
 968         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 969
 970         /* Disable DMA Coalescing if the watchdog timer is 0 */
 971         if (!hw->mac.dmac_config.watchdog_timer)
 972                 goto out;
 973
 974         ixgbe_dmac_config_tcs_X550(hw);
 975
 976         /* Configure DMA Coalescing Control Register */
 977         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 978
 979         /* Set the watchdog timer in units of 40.96 usec */
 980         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 981         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 982
 983         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 984         /* If fcoe is enabled, set high priority traffic class */
 985         if (hw->mac.dmac_config.fcoe_en) {
 986                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 987                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 988                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 989         }
 990         reg |= IXGBE_DMACR_EN_MNG_IND;
 991
 992         /* Enable DMA coalescing after configuration */
 993         reg |= IXGBE_DMACR_DMAC_EN;
 994         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 995
 996 out:
 997         return IXGBE_SUCCESS;
 998 }
 999
1000 /**
1001  *  ixgbe_dmac_config_tcs_X550
1002  *  @hw: pointer to hardware structure
1003  *
1004  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
1005  *  be cleared before configuring.
1006  **/
1007 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
1008 {
1009         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
1010
1011         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
1012
1013         /* Configure DMA coalescing enabled */
1014         switch (hw->mac.dmac_config.link_speed) {
1015         case IXGBE_LINK_SPEED_10_FULL:
1016         case IXGBE_LINK_SPEED_100_FULL:
1017                 pb_headroom = IXGBE_DMACRXT_100M;
1018                 break;
1019         case IXGBE_LINK_SPEED_1GB_FULL:
1020                 pb_headroom = IXGBE_DMACRXT_1G;
1021                 break;
1022         default:
1023                 pb_headroom = IXGBE_DMACRXT_10G;
1024                 break;
1025         }
1026
1027         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
1028                              IXGBE_MHADD_MFS_SHIFT) / 1024);
1029
1030         /* Set the per Rx packet buffer receive threshold */
1031         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
1032                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
1033                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
1034
1035                 if (tc < hw->mac.dmac_config.num_tcs) {
1036                         /* Get Rx PB size */
1037                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
1038                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
1039                                 IXGBE_RXPBSIZE_SHIFT;
1040
1041                         /* Calculate receive buffer threshold in kilobytes */
1042                         if (rx_pb_size > pb_headroom)
1043                                 rx_pb_size = rx_pb_size - pb_headroom;
1044                         else
1045                                 rx_pb_size = 0;
1046
1047                         /* Minimum of MFS shall be set for DMCTH */
1048                         reg |= (rx_pb_size > maxframe_size_kb) ?
1049                                 rx_pb_size : maxframe_size_kb;
1050                 }
1051                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
1052         }
1053         return IXGBE_SUCCESS;
1054 }
1055
1056 /**
1057  *  ixgbe_dmac_update_tcs_X550
1058  *  @hw: pointer to hardware structure
1059  *
1060  *  Disables dmac, updates per TC settings, and then enables dmac.
1061  **/
1062 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
1063 {
1064         u32 reg;
1065
1066         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
1067
1068         /* Disable DMA coalescing before configuring */
1069         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
1070         reg &= ~IXGBE_DMACR_DMAC_EN;
1071         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
1072
1073         ixgbe_dmac_config_tcs_X550(hw);
1074
1075         /* Enable DMA coalescing after configuration */
1076         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
1077         reg |= IXGBE_DMACR_DMAC_EN;
1078         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
1079
1080         return IXGBE_SUCCESS;
1081 }
1082
1083 /**
1084  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
1085  *  @hw: pointer to hardware structure
1086  *
1087  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
1088  *  ixgbe_hw struct in order to set up EEPROM access.
1089  **/
1090 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
1091 {
1092         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1093         u32 eec;
1094         u16 eeprom_size;
1095
1096         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
1097
1098         if (eeprom->type == ixgbe_eeprom_uninitialized) {
1099                 eeprom->semaphore_delay = 10;
1100                 eeprom->type = ixgbe_flash;
1101
1102                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1103                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1104                                     IXGBE_EEC_SIZE_SHIFT);
1105                 eeprom->word_size = 1 << (eeprom_size +
1106                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
1107
1108                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
1109                           eeprom->type, eeprom->word_size);
1110         }
1111
1112         return IXGBE_SUCCESS;
1113 }
1114
1115 /**
1116  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1117  * @hw: pointer to hardware structure
1118  * @enable: enable or disable source address pruning
1119  * @pool: Rx pool to set source address pruning for
1120  **/
1121 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1122                                            unsigned int pool)
1123 {
1124         u64 pfflp;
1125
1126         /* max rx pool is 63 */
1127         if (pool > 63)
1128                 return;
1129
1130         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1131         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1132
1133         if (enable)
1134                 pfflp |= (1ULL << pool);
1135         else
1136                 pfflp &= ~(1ULL << pool);
1137
1138         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1139         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1140 }
1141
1142 /**
1143  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1144  *  @hw: pointer to hardware structure
1145  *  @enable: enable or disable switch for Ethertype anti-spoofing
1146  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1147  *
1148  **/
1149 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1150                 bool enable, int vf)
1151 {
1152         int vf_target_reg = vf >> 3;
1153         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1154         u32 pfvfspoof;
1155
1156         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1157
1158         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1159         if (enable)
1160                 pfvfspoof |= (1 << vf_target_shift);
1161         else
1162                 pfvfspoof &= ~(1 << vf_target_shift);
1163
1164         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1165 }
1166
1167 /**
1168  * ixgbe_iosf_wait - Wait for IOSF command completion
1169  * @hw: pointer to hardware structure
1170  * @ctrl: pointer to location to receive final IOSF control value
1171  *
1172  * Returns failing status on timeout
1173  *
1174  * Note: ctrl can be NULL if the IOSF control register value is not needed
1175  **/
1176 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1177 {
1178         u32 i, command = 0;
1179
1180         /* Check every 10 usec to see if the address cycle completed.
1181          * The SB IOSF BUSY bit will clear when the operation is
1182          * complete
1183          */
1184         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1185                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1186                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1187                         break;
1188                 usec_delay(10);
1189         }
1190         if (ctrl)
1191                 *ctrl = command;
1192         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1193                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1194                 return IXGBE_ERR_PHY;
1195         }
1196
1197         return IXGBE_SUCCESS;
1198 }
1199
1200 /**
1201  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register
1202  *  of the IOSF device
1203  *  @hw: pointer to hardware structure
1204  *  @reg_addr: 32 bit PHY register to write
1205  *  @device_type: 3 bit device type
1206  *  @data: Data to write to the register
1207  **/
1208 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1209                             u32 device_type, u32 data)
1210 {
1211         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1212         u32 command, error;
1213         s32 ret;
1214
1215         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1216         if (ret != IXGBE_SUCCESS)
1217                 return ret;
1218
1219         ret = ixgbe_iosf_wait(hw, NULL);
1220         if (ret != IXGBE_SUCCESS)
1221                 goto out;
1222
1223         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1224                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1225
1226         /* Write IOSF control register */
1227         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1228
1229         /* Write IOSF data register */
1230         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1231
1232         ret = ixgbe_iosf_wait(hw, &command);
1233
1234         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1235                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1236                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1237                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1238                               "Failed to write, error %x\n", error);
1239                 ret = IXGBE_ERR_PHY;
1240         }
1241
1242 out:
1243         ixgbe_release_swfw_semaphore(hw, gssr);
1244         return ret;
1245 }
1246
1247 /**
1248  *  ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device
1249  *  @hw: pointer to hardware structure
1250  *  @reg_addr: 32 bit PHY register to write
1251  *  @device_type: 3 bit device type
1252  *  @data: Pointer to read data from the register
1253  **/
1254 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1255                            u32 device_type, u32 *data)
1256 {
1257         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1258         u32 command, error;
1259         s32 ret;
1260
1261         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1262         if (ret != IXGBE_SUCCESS)
1263                 return ret;
1264
1265         ret = ixgbe_iosf_wait(hw, NULL);
1266         if (ret != IXGBE_SUCCESS)
1267                 goto out;
1268
1269         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1270                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1271
1272         /* Write IOSF control register */
1273         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1274
1275         ret = ixgbe_iosf_wait(hw, &command);
1276
1277         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1278                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1279                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1280                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1281                                 "Failed to read, error %x\n", error);
1282                 ret = IXGBE_ERR_PHY;
1283         }
1284
1285         if (ret == IXGBE_SUCCESS)
1286                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1287
1288 out:
1289         ixgbe_release_swfw_semaphore(hw, gssr);
1290         return ret;
1291 }
1292
1293 /**
1294  * ixgbe_get_phy_token - Get the token for shared phy access
1295  * @hw: Pointer to hardware structure
1296  */
1297
1298 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1299 {
1300         struct ixgbe_hic_phy_token_req token_cmd;
1301         s32 status;
1302
1303         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1304         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1305         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1306         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1307         token_cmd.port_number = hw->bus.lan_id;
1308         token_cmd.command_type = FW_PHY_TOKEN_REQ;
1309         token_cmd.pad = 0;
1310         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1311                                               sizeof(token_cmd),
1312                                               IXGBE_HI_COMMAND_TIMEOUT,
1313                                               true);
1314         if (status)
1315                 return status;
1316         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1317                 return IXGBE_SUCCESS;
1318         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1319                 return IXGBE_ERR_FW_RESP_INVALID;
1320
1321         return IXGBE_ERR_TOKEN_RETRY;
1322 }
1323
1324 /**
1325  * ixgbe_put_phy_token - Put the token for shared phy access
1326  * @hw: Pointer to hardware structure
1327  */
1328
1329 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1330 {
1331         struct ixgbe_hic_phy_token_req token_cmd;
1332         s32 status;
1333
1334         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1335         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1336         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1337         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1338         token_cmd.port_number = hw->bus.lan_id;
1339         token_cmd.command_type = FW_PHY_TOKEN_REL;
1340         token_cmd.pad = 0;
1341         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1342                                               sizeof(token_cmd),
1343                                               IXGBE_HI_COMMAND_TIMEOUT,
1344                                               true);
1345         if (status)
1346                 return status;
1347         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1348                 return IXGBE_SUCCESS;
1349
1350         DEBUGOUT("Put PHY Token host interface command failed");
1351         return IXGBE_ERR_FW_RESP_INVALID;
1352 }
1353
1354 /**
1355  *  ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1356  *  of the IOSF device
1357  *  @hw: pointer to hardware structure
1358  *  @reg_addr: 32 bit PHY register to write
1359  *  @device_type: 3 bit device type
1360  *  @data: Data to write to the register
1361  **/
1362 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1363                                   u32 device_type, u32 data)
1364 {
1365         struct ixgbe_hic_internal_phy_req write_cmd;
1366         s32 status;
1367         UNREFERENCED_1PARAMETER(device_type);
1368
1369         memset(&write_cmd, 0, sizeof(write_cmd));
1370         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1371         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1372         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1373         write_cmd.port_number = hw->bus.lan_id;
1374         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1375         write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1376         write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1377
1378         status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1379                                               sizeof(write_cmd),
1380                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1381
1382         return status;
1383 }
1384
1385 /**
1386  *  ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device
1387  *  @hw: pointer to hardware structure
1388  *  @reg_addr: 32 bit PHY register to write
1389  *  @device_type: 3 bit device type
1390  *  @data: Pointer to read data from the register
1391  **/
1392 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1393                                  u32 device_type, u32 *data)
1394 {
1395         union {
1396                 struct ixgbe_hic_internal_phy_req cmd;
1397                 struct ixgbe_hic_internal_phy_resp rsp;
1398         } hic;
1399         s32 status;
1400         UNREFERENCED_1PARAMETER(device_type);
1401
1402         memset(&hic, 0, sizeof(hic));
1403         hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1404         hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1405         hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1406         hic.cmd.port_number = hw->bus.lan_id;
1407         hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1408         hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1409
1410         status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1411                                               sizeof(hic.cmd),
1412                                               IXGBE_HI_COMMAND_TIMEOUT, true);
1413
1414         /* Extract the register value from the response. */
1415         *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1416
1417         return status;
1418 }
1419
1420 /**
1421  *  ixgbe_disable_mdd_X550
1422  *  @hw: pointer to hardware structure
1423  *
1424  *  Disable malicious driver detection
1425  **/
1426 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1427 {
1428         u32 reg;
1429
1430         DEBUGFUNC("ixgbe_disable_mdd_X550");
1431
1432         /* Disable MDD for TX DMA and interrupt */
1433         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1434         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1435         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1436
1437         /* Disable MDD for RX and interrupt */
1438         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1439         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1440         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1441 }
1442
1443 /**
1444  *  ixgbe_enable_mdd_X550
1445  *  @hw: pointer to hardware structure
1446  *
1447  *  Enable malicious driver detection
1448  **/
1449 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1450 {
1451         u32 reg;
1452
1453         DEBUGFUNC("ixgbe_enable_mdd_X550");
1454
1455         /* Enable MDD for TX DMA and interrupt */
1456         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1457         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1458         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1459
1460         /* Enable MDD for RX and interrupt */
1461         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1462         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1463         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1464 }
1465
1466 /**
1467  *  ixgbe_restore_mdd_vf_X550
1468  *  @hw: pointer to hardware structure
1469  *  @vf: vf index
1470  *
1471  *  Restore VF that was disabled during malicious driver detection event
1472  **/
1473 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1474 {
1475         u32 idx, reg, num_qs, start_q, bitmask;
1476
1477         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1478
1479         /* Map VF to queues */
1480         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1481         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1482         case IXGBE_MRQC_VMDQRT8TCEN:
1483                 num_qs = 8;  /* 16 VFs / pools */
1484                 bitmask = 0x000000FF;
1485                 break;
1486         case IXGBE_MRQC_VMDQRSS32EN:
1487         case IXGBE_MRQC_VMDQRT4TCEN:
1488                 num_qs = 4;  /* 32 VFs / pools */
1489                 bitmask = 0x0000000F;
1490                 break;
1491         default:            /* 64 VFs / pools */
1492                 num_qs = 2;
1493                 bitmask = 0x00000003;
1494                 break;
1495         }
1496         start_q = vf * num_qs;
1497
1498         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1499         idx = start_q / 32;
1500         reg = 0;
1501         reg |= (bitmask << (start_q % 32));
1502         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1503         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1504 }
1505
1506 /**
1507  *  ixgbe_mdd_event_X550
1508  *  @hw: pointer to hardware structure
1509  *  @vf_bitmap: vf bitmap of malicious vfs
1510  *
1511  *  Handle malicious driver detection event.
1512  **/
1513 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1514 {
1515         u32 wqbr;
1516         u32 i, j, reg, q, shift, vf, idx;
1517
1518         DEBUGFUNC("ixgbe_mdd_event_X550");
1519
1520         /* figure out pool size for mapping to vf's */
1521         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1522         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1523         case IXGBE_MRQC_VMDQRT8TCEN:
1524                 shift = 3;  /* 16 VFs / pools */
1525                 break;
1526         case IXGBE_MRQC_VMDQRSS32EN:
1527         case IXGBE_MRQC_VMDQRT4TCEN:
1528                 shift = 2;  /* 32 VFs / pools */
1529                 break;
1530         default:
1531                 shift = 1;  /* 64 VFs / pools */
1532                 break;
1533         }
1534
1535         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1536         for (i = 0; i < 4; i++) {
1537                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1538                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1539
1540                 if (!wqbr)
1541                         continue;
1542
1543                 /* Get malicious queue */
1544                 for (j = 0; j < 32 && wqbr; j++) {
1545
1546                         if (!(wqbr & (1 << j)))
1547                                 continue;
1548
1549                         /* Get queue from bitmask */
1550                         q = j + (i * 32);
1551
1552                         /* Map queue to vf */
1553                         vf = (q >> shift);
1554
1555                         /* Set vf bit in vf_bitmap */
1556                         idx = vf / 32;
1557                         vf_bitmap[idx] |= (1 << (vf % 32));
1558                         wqbr &= ~(1 << j);
1559                 }
1560         }
1561 }
1562
1563 /**
1564  *  ixgbe_get_media_type_X550em - Get media type
1565  *  @hw: pointer to hardware structure
1566  *
1567  *  Returns the media type (fiber, copper, backplane)
1568  */
1569 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1570 {
1571         enum ixgbe_media_type media_type;
1572
1573         DEBUGFUNC("ixgbe_get_media_type_X550em");
1574
1575         /* Detect if there is a copper PHY attached. */
1576         switch (hw->device_id) {
1577         case IXGBE_DEV_ID_X550EM_X_KR:
1578         case IXGBE_DEV_ID_X550EM_X_KX4:
1579         case IXGBE_DEV_ID_X550EM_X_XFI:
1580         case IXGBE_DEV_ID_X550EM_A_KR:
1581         case IXGBE_DEV_ID_X550EM_A_KR_L:
1582                 media_type = ixgbe_media_type_backplane;
1583                 break;
1584         case IXGBE_DEV_ID_X550EM_X_SFP:
1585         case IXGBE_DEV_ID_X550EM_A_SFP:
1586         case IXGBE_DEV_ID_X550EM_A_SFP_N:
1587         case IXGBE_DEV_ID_X550EM_A_QSFP:
1588         case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1589                 media_type = ixgbe_media_type_fiber;
1590                 break;
1591         case IXGBE_DEV_ID_X550EM_X_1G_T:
1592         case IXGBE_DEV_ID_X550EM_X_10G_T:
1593         case IXGBE_DEV_ID_X550EM_A_10G_T:
1594                 media_type = ixgbe_media_type_copper;
1595                 break;
1596         case IXGBE_DEV_ID_X550EM_A_SGMII:
1597         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1598                 media_type = ixgbe_media_type_backplane;
1599                 hw->phy.type = ixgbe_phy_sgmii;
1600                 break;
1601         case IXGBE_DEV_ID_X550EM_A_1G_T:
1602         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1603                 media_type = ixgbe_media_type_copper;
1604                 break;
1605         default:
1606                 media_type = ixgbe_media_type_unknown;
1607                 break;
1608         }
1609         return media_type;
1610 }
1611
1612 /**
1613  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1614  *  @hw: pointer to hardware structure
1615  *  @linear: true if SFP module is linear
1616  */
1617 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1618 {
1619         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1620
1621         switch (hw->phy.sfp_type) {
1622         case ixgbe_sfp_type_not_present:
1623                 return IXGBE_ERR_SFP_NOT_PRESENT;
1624         case ixgbe_sfp_type_da_cu_core0:
1625         case ixgbe_sfp_type_da_cu_core1:
1626                 *linear = true;
1627                 break;
1628         case ixgbe_sfp_type_srlr_core0:
1629         case ixgbe_sfp_type_srlr_core1:
1630         case ixgbe_sfp_type_da_act_lmt_core0:
1631         case ixgbe_sfp_type_da_act_lmt_core1:
1632         case ixgbe_sfp_type_1g_sx_core0:
1633         case ixgbe_sfp_type_1g_sx_core1:
1634         case ixgbe_sfp_type_1g_lx_core0:
1635         case ixgbe_sfp_type_1g_lx_core1:
1636                 *linear = false;
1637                 break;
1638         case ixgbe_sfp_type_unknown:
1639         case ixgbe_sfp_type_1g_cu_core0:
1640         case ixgbe_sfp_type_1g_cu_core1:
1641         default:
1642                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1643         }
1644
1645         return IXGBE_SUCCESS;
1646 }
1647
1648 /**
1649  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1650  *  @hw: pointer to hardware structure
1651  *
1652  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1653  **/
1654 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1655 {
1656         s32 status;
1657         bool linear;
1658
1659         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1660
1661         status = ixgbe_identify_module_generic(hw);
1662
1663         if (status != IXGBE_SUCCESS)
1664                 return status;
1665
1666         /* Check if SFP module is supported */
1667         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1668
1669         return status;
1670 }
1671
1672 /**
1673  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1674  *  @hw: pointer to hardware structure
1675  */
1676 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1677 {
1678         s32 status;
1679         bool linear;
1680
1681         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1682
1683         /* Check if SFP module is supported */
1684         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1685
1686         if (status != IXGBE_SUCCESS)
1687                 return status;
1688
1689         ixgbe_init_mac_link_ops_X550em(hw);
1690         hw->phy.ops.reset = NULL;
1691
1692         return IXGBE_SUCCESS;
1693 }
1694
1695 /**
1696 *  ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1697 *  internal PHY
1698 *  @hw: pointer to hardware structure
1699 **/
1700 STATIC s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1701 {
1702         s32 status;
1703         u32 link_ctrl;
1704
1705         /* Restart auto-negotiation. */
1706         status = hw->mac.ops.read_iosf_sb_reg(hw,
1707                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1708                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1709
1710         if (status) {
1711                 DEBUGOUT("Auto-negotiation did not complete\n");
1712                 return status;
1713         }
1714
1715         link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1716         status = hw->mac.ops.write_iosf_sb_reg(hw,
1717                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1718                                         IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1719
1720         if (hw->mac.type == ixgbe_mac_X550EM_a) {
1721                 u32 flx_mask_st20;
1722
1723                 /* Indicate to FW that AN restart has been asserted */
1724                 status = hw->mac.ops.read_iosf_sb_reg(hw,
1725                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1726                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1727
1728                 if (status) {
1729                         DEBUGOUT("Auto-negotiation did not complete\n");
1730                         return status;
1731                 }
1732
1733                 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1734                 status = hw->mac.ops.write_iosf_sb_reg(hw,
1735                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1736                                 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1737         }
1738
1739         return status;
1740 }
1741
1742 /**
1743  * ixgbe_setup_sgmii - Set up link for sgmii
1744  * @hw: pointer to hardware structure
1745  */
1746 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1747                              bool autoneg_wait)
1748 {
1749         struct ixgbe_mac_info *mac = &hw->mac;
1750         u32 lval, sval, flx_val;
1751         s32 rc;
1752
1753         rc = mac->ops.read_iosf_sb_reg(hw,
1754                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1755                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1756         if (rc)
1757                 return rc;
1758
1759         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1760         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1761         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1762         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1763         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1764         rc = mac->ops.write_iosf_sb_reg(hw,
1765                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1766                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1767         if (rc)
1768                 return rc;
1769
1770         rc = mac->ops.read_iosf_sb_reg(hw,
1771                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1772                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1773         if (rc)
1774                 return rc;
1775
1776         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1777         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1778         rc = mac->ops.write_iosf_sb_reg(hw,
1779                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1780                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1781         if (rc)
1782                 return rc;
1783
1784         rc = mac->ops.read_iosf_sb_reg(hw,
1785                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1786                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1787         if (rc)
1788                 return rc;
1789
1790         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1791         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1792         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1793         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1794         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1795
1796         rc = mac->ops.write_iosf_sb_reg(hw,
1797                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1798                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1799         if (rc)
1800                 return rc;
1801
1802         rc = ixgbe_restart_an_internal_phy_x550em(hw);
1803         if (rc)
1804                 return rc;
1805
1806         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1807 }
1808
1809 /**
1810  * ixgbe_setup_sgmii_fw - Set up link for sgmii with firmware-controlled PHYs
1811  * @hw: pointer to hardware structure
1812  */
1813 STATIC s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1814                                 bool autoneg_wait)
1815 {
1816         struct ixgbe_mac_info *mac = &hw->mac;
1817         u32 lval, sval, flx_val;
1818         s32 rc;
1819
1820         rc = mac->ops.read_iosf_sb_reg(hw,
1821                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1822                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1823         if (rc)
1824                 return rc;
1825
1826         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1827         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1828         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1829         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1830         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1831         rc = mac->ops.write_iosf_sb_reg(hw,
1832                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1833                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1834         if (rc)
1835                 return rc;
1836
1837         rc = mac->ops.read_iosf_sb_reg(hw,
1838                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1839                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1840         if (rc)
1841                 return rc;
1842
1843         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1844         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1845         rc = mac->ops.write_iosf_sb_reg(hw,
1846                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1847                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1848         if (rc)
1849                 return rc;
1850
1851         rc = mac->ops.write_iosf_sb_reg(hw,
1852                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1853                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1854         if (rc)
1855                 return rc;
1856
1857         rc = mac->ops.read_iosf_sb_reg(hw,
1858                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1859                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1860         if (rc)
1861                 return rc;
1862
1863         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1864         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
1865         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1866         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1867         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1868
1869         rc = mac->ops.write_iosf_sb_reg(hw,
1870                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1871                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1872         if (rc)
1873                 return rc;
1874
1875         rc = ixgbe_restart_an_internal_phy_x550em(hw);
1876
1877         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1878 }
1879
1880 /**
1881  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1882  *  @hw: pointer to hardware structure
1883  */
1884 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1885 {
1886         struct ixgbe_mac_info *mac = &hw->mac;
1887
1888         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1889
1890         switch (hw->mac.ops.get_media_type(hw)) {
1891         case ixgbe_media_type_fiber:
1892                 /* CS4227 does not support autoneg, so disable the laser control
1893                  * functions for SFP+ fiber
1894                  */
1895                 mac->ops.disable_tx_laser = NULL;
1896                 mac->ops.enable_tx_laser = NULL;
1897                 mac->ops.flap_tx_laser = NULL;
1898                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1899                 mac->ops.set_rate_select_speed =
1900                                         ixgbe_set_soft_rate_select_speed;
1901
1902                 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1903                     (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1904                         mac->ops.setup_mac_link =
1905                                                 ixgbe_setup_mac_link_sfp_x550a;
1906                 else
1907                         mac->ops.setup_mac_link =
1908                                                 ixgbe_setup_mac_link_sfp_x550em;
1909                 break;
1910         case ixgbe_media_type_copper:
1911                 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1912                         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
1913                             hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
1914                                 mac->ops.setup_link = ixgbe_setup_sgmii_fw;
1915                                 mac->ops.check_link =
1916                                                    ixgbe_check_mac_link_generic;
1917                         } else {
1918                                 mac->ops.setup_link =
1919                                                   ixgbe_setup_mac_link_t_X550em;
1920                         }
1921                 } else {
1922                         mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1923                         mac->ops.check_link = ixgbe_check_link_t_X550em;
1924                 }
1925                 break;
1926         case ixgbe_media_type_backplane:
1927                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1928                     hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1929                         mac->ops.setup_link = ixgbe_setup_sgmii;
1930                 break;
1931         default:
1932                 break;
1933         }
1934 }
1935
1936 /**
1937  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1938  *  @hw: pointer to hardware structure
1939  *  @speed: pointer to link speed
1940  *  @autoneg: true when autoneg or autotry is enabled
1941  */
1942 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1943                                        ixgbe_link_speed *speed,
1944                                        bool *autoneg)
1945 {
1946         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1947
1948
1949         if (hw->phy.type == ixgbe_phy_fw) {
1950                 *autoneg = true;
1951                 *speed = hw->phy.speeds_supported;
1952                 return 0;
1953         }
1954
1955         /* SFP */
1956         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1957
1958                 /* CS4227 SFP must not enable auto-negotiation */
1959                 *autoneg = false;
1960
1961                 /* Check if 1G SFP module. */
1962                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1963                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1964                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1965                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1966                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1967                         return IXGBE_SUCCESS;
1968                 }
1969
1970                 /* Link capabilities are based on SFP */
1971                 if (hw->phy.multispeed_fiber)
1972                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1973                                  IXGBE_LINK_SPEED_1GB_FULL;
1974                 else
1975                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1976         } else {
1977                 switch (hw->phy.type) {
1978                 case ixgbe_phy_ext_1g_t:
1979                 case ixgbe_phy_sgmii:
1980                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1981                         break;
1982                 case ixgbe_phy_x550em_kr:
1983                         if (hw->mac.type == ixgbe_mac_X550EM_a) {
1984                                 /* check different backplane modes */
1985                                 if (hw->phy.nw_mng_if_sel &
1986                                            IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
1987                                         *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
1988                                         break;
1989                                 } else if (hw->device_id ==
1990                                                    IXGBE_DEV_ID_X550EM_A_KR_L) {
1991                                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1992                                         break;
1993                                 }
1994                         }
1995                         /* fall through */
1996                 default:
1997                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1998                                  IXGBE_LINK_SPEED_1GB_FULL;
1999                         break;
2000                 }
2001                 *autoneg = true;
2002         }
2003
2004         return IXGBE_SUCCESS;
2005 }
2006
2007 /**
2008  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
2009  * @hw: pointer to hardware structure
2010  * @lsc: pointer to boolean flag which indicates whether external Base T
2011  *       PHY interrupt is lsc
2012  *
2013  * Determime if external Base T PHY interrupt cause is high temperature
2014  * failure alarm or link status change.
2015  *
2016  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2017  * failure alarm, else return PHY access status.
2018  */
2019 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
2020 {
2021         u32 status;
2022         u16 reg;
2023
2024         *lsc = false;
2025
2026         /* Vendor alarm triggered */
2027         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2028                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2029                                       &reg);
2030
2031         if (status != IXGBE_SUCCESS ||
2032             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
2033                 return status;
2034
2035         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
2036         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
2037                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2038                                       &reg);
2039
2040         if (status != IXGBE_SUCCESS ||
2041             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2042             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
2043                 return status;
2044
2045         /* Global alarm triggered */
2046         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
2047                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2048                                       &reg);
2049
2050         if (status != IXGBE_SUCCESS)
2051                 return status;
2052
2053         /* If high temperature failure, then return over temp error and exit */
2054         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
2055                 /* power down the PHY in case the PHY FW didn't already */
2056                 ixgbe_set_copper_phy_power(hw, false);
2057                 return IXGBE_ERR_OVERTEMP;
2058         } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
2059                 /*  device fault alarm triggered */
2060                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
2061                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2062                                           &reg);
2063
2064                 if (status != IXGBE_SUCCESS)
2065                         return status;
2066
2067                 /* if device fault was due to high temp alarm handle and exit */
2068                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
2069                         /* power down the PHY in case the PHY FW didn't */
2070                         ixgbe_set_copper_phy_power(hw, false);
2071                         return IXGBE_ERR_OVERTEMP;
2072                 }
2073         }
2074
2075         /* Vendor alarm 2 triggered */
2076         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2077                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2078
2079         if (status != IXGBE_SUCCESS ||
2080             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
2081                 return status;
2082
2083         /* link connect/disconnect event occurred */
2084         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
2085                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2086
2087         if (status != IXGBE_SUCCESS)
2088                 return status;
2089
2090         /* Indicate LSC */
2091         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2092                 *lsc = true;
2093
2094         return IXGBE_SUCCESS;
2095 }
2096
2097 /**
2098  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2099  * @hw: pointer to hardware structure
2100  *
2101  * Enable link status change and temperature failure alarm for the external
2102  * Base T PHY
2103  *
2104  * Returns PHY access status
2105  */
2106 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2107 {
2108         u32 status;
2109         u16 reg;
2110         bool lsc;
2111
2112         /* Clear interrupt flags */
2113         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2114
2115         /* Enable link status change alarm */
2116
2117         /* Enable the LASI interrupts on X552 devices to receive notifications
2118          * of the link configurations of the external PHY and correspondingly
2119          * support the configuration of the internal iXFI link, since iXFI does
2120          * not support auto-negotiation. This is not required for X553 devices
2121          * having KR support, which performs auto-negotiations and which is used
2122          * as the internal link to the external PHY. Hence adding a check here
2123          * to avoid enabling LASI interrupts for X553 devices.
2124          */
2125         if (hw->mac.type != ixgbe_mac_X550EM_a) {
2126                 status = hw->phy.ops.read_reg(hw,
2127                                         IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2128                                         IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2129
2130                 if (status != IXGBE_SUCCESS)
2131                         return status;
2132
2133                 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2134
2135                 status = hw->phy.ops.write_reg(hw,
2136                                         IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2137                                         IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
2138
2139                 if (status != IXGBE_SUCCESS)
2140                         return status;
2141         }
2142
2143         /* Enable high temperature failure and global fault alarms */
2144         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2145                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2146                                       &reg);
2147
2148         if (status != IXGBE_SUCCESS)
2149                 return status;
2150
2151         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2152                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2153
2154         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2155                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2156                                        reg);
2157
2158         if (status != IXGBE_SUCCESS)
2159                 return status;
2160
2161         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2162         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2163                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2164                                       &reg);
2165
2166         if (status != IXGBE_SUCCESS)
2167                 return status;
2168
2169         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2170                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2171
2172         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2173                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2174                                        reg);
2175
2176         if (status != IXGBE_SUCCESS)
2177                 return status;
2178
2179         /* Enable chip-wide vendor alarm */
2180         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2181                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2182                                       &reg);
2183
2184         if (status != IXGBE_SUCCESS)
2185                 return status;
2186
2187         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2188
2189         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2190                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2191                                        reg);
2192
2193         return status;
2194 }
2195
2196 /**
2197  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2198  *  @hw: pointer to hardware structure
2199  *  @speed: link speed
2200  *
2201  *  Configures the integrated KR PHY.
2202  **/
2203 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2204                                        ixgbe_link_speed speed)
2205 {
2206         s32 status;
2207         u32 reg_val;
2208
2209         status = hw->mac.ops.read_iosf_sb_reg(hw,
2210                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2211                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2212         if (status)
2213                 return status;
2214
2215         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2216         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2217                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2218
2219         /* Advertise 10G support. */
2220         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2221                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2222
2223         /* Advertise 1G support. */
2224         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2225                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2226
2227         status = hw->mac.ops.write_iosf_sb_reg(hw,
2228                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2229                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2230
2231         if (hw->mac.type == ixgbe_mac_X550EM_a) {
2232                 /* Set lane mode  to KR auto negotiation */
2233                 status = hw->mac.ops.read_iosf_sb_reg(hw,
2234                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2235                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2236
2237                 if (status)
2238                         return status;
2239
2240                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2241                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2242                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2243                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2244                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2245
2246                 status = hw->mac.ops.write_iosf_sb_reg(hw,
2247                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2248                                     IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2249         }
2250
2251         return ixgbe_restart_an_internal_phy_x550em(hw);
2252 }
2253
2254 /**
2255  * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs
2256  * @hw: pointer to hardware structure
2257  */
2258 static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw)
2259 {
2260         u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
2261         s32 rc;
2262
2263         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2264                 return IXGBE_SUCCESS;
2265
2266         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store);
2267         if (rc)
2268                 return rc;
2269         memset(store, 0, sizeof(store));
2270
2271         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store);
2272         if (rc)
2273                 return rc;
2274
2275         return ixgbe_setup_fw_link(hw);
2276 }
2277
2278 /**
2279  * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp
2280  * @hw: pointer to hardware structure
2281  */
2282 static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw)
2283 {
2284         u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
2285         s32 rc;
2286
2287         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store);
2288         if (rc)
2289                 return rc;
2290
2291         if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) {
2292                 ixgbe_shutdown_fw_phy(hw);
2293                 return IXGBE_ERR_OVERTEMP;
2294         }
2295         return IXGBE_SUCCESS;
2296 }
2297
2298 /**
2299  *  ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2300  *  @hw: pointer to hardware structure
2301  *
2302  *  Read NW_MNG_IF_SEL register and save field values, and check for valid field
2303  *  values.
2304  **/
2305 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2306 {
2307         /* Save NW management interface connected on board. This is used
2308          * to determine internal PHY mode.
2309          */
2310         hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2311
2312         /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2313          * PHY address. This register field was has only been used for X552.
2314          */
2315         if (hw->mac.type == ixgbe_mac_X550EM_a &&
2316             hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2317                 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2318                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2319                                IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2320         }
2321
2322         return IXGBE_SUCCESS;
2323 }
2324
2325 /**
2326  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2327  *  @hw: pointer to hardware structure
2328  *
2329  *  Initialize any function pointers that were not able to be
2330  *  set during init_shared_code because the PHY/SFP type was
2331  *  not known.  Perform the SFP init if necessary.
2332  */
2333 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2334 {
2335         struct ixgbe_phy_info *phy = &hw->phy;
2336         s32 ret_val;
2337
2338         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2339
2340         hw->mac.ops.set_lan_id(hw);
2341         ixgbe_read_mng_if_sel_x550em(hw);
2342
2343         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2344                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2345                 ixgbe_setup_mux_ctl(hw);
2346                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2347         }
2348
2349         switch (hw->device_id) {
2350         case IXGBE_DEV_ID_X550EM_A_1G_T:
2351         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2352                 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2353                 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2354                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2355                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2356                 phy->ops.check_overtemp = ixgbe_check_overtemp_fw;
2357                 if (hw->bus.lan_id)
2358                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2359                 else
2360                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2361
2362                 break;
2363         case IXGBE_DEV_ID_X550EM_A_10G_T:
2364         case IXGBE_DEV_ID_X550EM_A_SFP:
2365                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2366                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2367                 if (hw->bus.lan_id)
2368                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2369                 else
2370                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2371                 break;
2372         case IXGBE_DEV_ID_X550EM_X_SFP:
2373                 /* set up for CS4227 usage */
2374                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2375                 break;
2376         default:
2377                 break;
2378         }
2379
2380         /* Identify the PHY or SFP module */
2381         ret_val = phy->ops.identify(hw);
2382         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED ||
2383             ret_val == IXGBE_ERR_PHY_ADDR_INVALID)
2384                 return ret_val;
2385
2386         /* Setup function pointers based on detected hardware */
2387         ixgbe_init_mac_link_ops_X550em(hw);
2388         if (phy->sfp_type != ixgbe_sfp_type_unknown)
2389                 phy->ops.reset = NULL;
2390
2391         /* Set functions pointers based on phy type */
2392         switch (hw->phy.type) {
2393         case ixgbe_phy_x550em_kx4:
2394                 phy->ops.setup_link = NULL;
2395                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2396                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2397                 break;
2398         case ixgbe_phy_x550em_kr:
2399                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2400                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2401                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2402                 break;
2403         case ixgbe_phy_ext_1g_t:
2404                 /* link is managed by FW */
2405                 phy->ops.setup_link = NULL;
2406                 break;
2407         case ixgbe_phy_x550em_xfi:
2408                 /* link is managed by HW */
2409                 phy->ops.setup_link = NULL;
2410                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2411                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2412                 break;
2413         case ixgbe_phy_x550em_ext_t:
2414                 /* If internal link mode is XFI, then setup iXFI internal link,
2415                  * else setup KR now.
2416                  */
2417                 phy->ops.setup_internal_link =
2418                                               ixgbe_setup_internal_phy_t_x550em;
2419
2420                 /* setup SW LPLU only for first revision of X550EM_x */
2421                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2422                     !(IXGBE_FUSES0_REV_MASK &
2423                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2424                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2425
2426                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2427                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2428                 break;
2429         case ixgbe_phy_sgmii:
2430                 phy->ops.setup_link = NULL;
2431                 break;
2432         case ixgbe_phy_fw:
2433                 phy->ops.setup_link = ixgbe_setup_fw_link;
2434                 phy->ops.reset = ixgbe_reset_phy_fw;
2435                 break;
2436         default:
2437                 break;
2438         }
2439         return ret_val;
2440 }
2441
2442 /**
2443  * ixgbe_set_mdio_speed - Set MDIO clock speed
2444  *  @hw: pointer to hardware structure
2445  */
2446 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2447 {
2448         u32 hlreg0;
2449
2450         switch (hw->device_id) {
2451         case IXGBE_DEV_ID_X550EM_X_10G_T:
2452         case IXGBE_DEV_ID_X550EM_A_SGMII:
2453         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2454         case IXGBE_DEV_ID_X550EM_A_10G_T:
2455         case IXGBE_DEV_ID_X550EM_A_SFP:
2456         case IXGBE_DEV_ID_X550EM_A_QSFP:
2457                 /* Config MDIO clock speed before the first MDIO PHY access */
2458                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2459                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2460                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2461                 break;
2462         case IXGBE_DEV_ID_X550EM_A_1G_T:
2463         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2464                 /* Select fast MDIO clock speed for these devices */
2465                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2466                 hlreg0 |= IXGBE_HLREG0_MDCSPD;
2467                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2468                 break;
2469         default:
2470                 break;
2471         }
2472 }
2473
2474 /**
2475  *  ixgbe_reset_hw_X550em - Perform hardware reset
2476  *  @hw: pointer to hardware structure
2477  *
2478  *  Resets the hardware by resetting the transmit and receive units, masks
2479  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2480  *  reset.
2481  */
2482 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2483 {
2484         ixgbe_link_speed link_speed;
2485         s32 status;
2486         u32 ctrl = 0;
2487         u32 i;
2488         bool link_up = false;
2489
2490         DEBUGFUNC("ixgbe_reset_hw_X550em");
2491
2492         /* Call adapter stop to disable Tx/Rx and clear interrupts */
2493         status = hw->mac.ops.stop_adapter(hw);
2494         if (status != IXGBE_SUCCESS)
2495                 return status;
2496
2497         /* flush pending Tx transactions */
2498         ixgbe_clear_tx_pending(hw);
2499
2500         ixgbe_set_mdio_speed(hw);
2501
2502         /* PHY ops must be identified and initialized prior to reset */
2503         status = hw->phy.ops.init(hw);
2504
2505         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2506                 return status;
2507
2508         /* start the external PHY */
2509         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2510                 status = ixgbe_init_ext_t_x550em(hw);
2511                 if (status)
2512                         return status;
2513         }
2514
2515         /* Setup SFP module if there is one present. */
2516         if (hw->phy.sfp_setup_needed) {
2517                 status = hw->mac.ops.setup_sfp(hw);
2518                 hw->phy.sfp_setup_needed = false;
2519         }
2520
2521         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2522                 return status;
2523
2524         /* Reset PHY */
2525         if (!hw->phy.reset_disable && hw->phy.ops.reset) {
2526                 if (hw->phy.ops.reset(hw) == IXGBE_ERR_OVERTEMP)
2527                         return IXGBE_ERR_OVERTEMP;
2528         }
2529
2530 mac_reset_top:
2531         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2532          * If link reset is used when link is up, it might reset the PHY when
2533          * mng is using it.  If link is down or the flag to force full link
2534          * reset is set, then perform link reset.
2535          */
2536         ctrl = IXGBE_CTRL_LNK_RST;
2537         if (!hw->force_full_reset) {
2538                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2539                 if (link_up)
2540                         ctrl = IXGBE_CTRL_RST;
2541         }
2542
2543         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2544         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2545         IXGBE_WRITE_FLUSH(hw);
2546
2547         /* Poll for reset bit to self-clear meaning reset is complete */
2548         for (i = 0; i < 10; i++) {
2549                 usec_delay(1);
2550                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2551                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2552                         break;
2553         }
2554
2555         if (ctrl & IXGBE_CTRL_RST_MASK) {
2556                 status = IXGBE_ERR_RESET_FAILED;
2557                 DEBUGOUT("Reset polling failed to complete.\n");
2558         }
2559
2560         msec_delay(50);
2561
2562         /* Double resets are required for recovery from certain error
2563          * conditions.  Between resets, it is necessary to stall to
2564          * allow time for any pending HW events to complete.
2565          */
2566         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2567                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2568                 goto mac_reset_top;
2569         }
2570
2571         /* Store the permanent mac address */
2572         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2573
2574         /* Store MAC address from RAR0, clear receive address registers, and
2575          * clear the multicast table.  Also reset num_rar_entries to 128,
2576          * since we modify this value when programming the SAN MAC address.
2577          */
2578         hw->mac.num_rar_entries = 128;
2579         hw->mac.ops.init_rx_addrs(hw);
2580
2581         ixgbe_set_mdio_speed(hw);
2582
2583         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2584                 ixgbe_setup_mux_ctl(hw);
2585
2586         return status;
2587 }
2588
2589 /**
2590  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2591  * @hw: pointer to hardware structure
2592  */
2593 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2594 {
2595         u32 status;
2596         u16 reg;
2597
2598         status = hw->phy.ops.read_reg(hw,
2599                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2600                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2601                                       &reg);
2602
2603         if (status != IXGBE_SUCCESS)
2604                 return status;
2605
2606         /* If PHY FW reset completed bit is set then this is the first
2607          * SW instance after a power on so the PHY FW must be un-stalled.
2608          */
2609         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2610                 status = hw->phy.ops.read_reg(hw,
2611                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2612                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2613                                         &reg);
2614
2615                 if (status != IXGBE_SUCCESS)
2616                         return status;
2617
2618                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2619
2620                 status = hw->phy.ops.write_reg(hw,
2621                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2622                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2623                                         reg);
2624
2625                 if (status != IXGBE_SUCCESS)
2626                         return status;
2627         }
2628
2629         return status;
2630 }
2631
2632 /**
2633  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
2634  *  @hw: pointer to hardware structure
2635  **/
2636 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2637 {
2638         /* leave link alone for 2.5G */
2639         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL)
2640                 return IXGBE_SUCCESS;
2641
2642         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2643 }
2644
2645 /**
2646  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2647  *  @hw: pointer to hardware structure
2648  *
2649  *  Configure the external PHY and the integrated KR PHY for SFP support.
2650  **/
2651 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2652                                     ixgbe_link_speed speed,
2653                                     bool autoneg_wait_to_complete)
2654 {
2655         s32 ret_val;
2656         u16 reg_slice, reg_val;
2657         bool setup_linear = false;
2658         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2659
2660         /* Check if SFP module is supported and linear */
2661         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2662
2663         /* If no SFP module present, then return success. Return success since
2664          * there is no reason to configure CS4227 and SFP not present error is
2665          * not excepted in the setup MAC link flow.
2666          */
2667         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2668                 return IXGBE_SUCCESS;
2669
2670         if (ret_val != IXGBE_SUCCESS)
2671                 return ret_val;
2672
2673         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2674                 /* Configure CS4227 LINE side to 10G SR. */
2675                 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
2676                             (hw->bus.lan_id << 12);
2677                 reg_val = IXGBE_CS4227_SPEED_10G;
2678                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2679                                                   reg_val);
2680
2681                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2682                             (hw->bus.lan_id << 12);
2683                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2684                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2685                                                   reg_val);
2686
2687                 /* Configure CS4227 for HOST connection rate then type. */
2688                 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
2689                             (hw->bus.lan_id << 12);
2690                 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
2691                 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
2692                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2693                                                   reg_val);
2694
2695                 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
2696                             (hw->bus.lan_id << 12);
2697                 if (setup_linear)
2698                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2699                 else
2700                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2701                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2702                                                   reg_val);
2703
2704                 /* Setup XFI internal link. */
2705                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2706         } else {
2707                 /* Configure internal PHY for KR/KX. */
2708                 ixgbe_setup_kr_speed_x550em(hw, speed);
2709
2710                 /* Configure CS4227 LINE side to proper mode. */
2711                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2712                             (hw->bus.lan_id << 12);
2713                 if (setup_linear)
2714                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2715                 else
2716                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2717                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2718                                                   reg_val);
2719         }
2720         return ret_val;
2721 }
2722
2723 /**
2724  *  ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
2725  *  @hw: pointer to hardware structure
2726  *  @speed: the link speed to force
2727  *
2728  *  Configures the integrated PHY for native SFI mode. Used to connect the
2729  *  internal PHY directly to an SFP cage, without autonegotiation.
2730  **/
2731 STATIC s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2732 {
2733         struct ixgbe_mac_info *mac = &hw->mac;
2734         s32 status;
2735         u32 reg_val;
2736
2737         /* Disable all AN and force speed to 10G Serial. */
2738         status = mac->ops.read_iosf_sb_reg(hw,
2739                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2740                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2741         if (status != IXGBE_SUCCESS)
2742                 return status;
2743
2744         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2745         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2746         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2747         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2748
2749         /* Select forced link speed for internal PHY. */
2750         switch (*speed) {
2751         case IXGBE_LINK_SPEED_10GB_FULL:
2752                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
2753                 break;
2754         case IXGBE_LINK_SPEED_1GB_FULL:
2755                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2756                 break;
2757         default:
2758                 /* Other link speeds are not supported by internal PHY. */
2759                 return IXGBE_ERR_LINK_SETUP;
2760         }
2761
2762         status = mac->ops.write_iosf_sb_reg(hw,
2763                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2764                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2765
2766         /* Toggle port SW reset by AN reset. */
2767         status = ixgbe_restart_an_internal_phy_x550em(hw);
2768
2769         return status;
2770 }
2771
2772 /**
2773  *  ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2774  *  @hw: pointer to hardware structure
2775  *
2776  *  Configure the the integrated PHY for SFP support.
2777  **/
2778 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2779                                     ixgbe_link_speed speed,
2780                                     bool autoneg_wait_to_complete)
2781 {
2782         s32 ret_val;
2783         u16 reg_phy_ext;
2784         bool setup_linear = false;
2785         u32 reg_slice, reg_phy_int, slice_offset;
2786
2787         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2788
2789         /* Check if SFP module is supported and linear */
2790         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2791
2792         /* If no SFP module present, then return success. Return success since
2793          * SFP not present error is not excepted in the setup MAC link flow.
2794          */
2795         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2796                 return IXGBE_SUCCESS;
2797
2798         if (ret_val != IXGBE_SUCCESS)
2799                 return ret_val;
2800
2801         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2802                 /* Configure internal PHY for native SFI based on module type */
2803                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2804                                    IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2805                                    IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_phy_int);
2806
2807                 if (ret_val != IXGBE_SUCCESS)
2808                         return ret_val;
2809
2810                 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
2811                 if (!setup_linear)
2812                         reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
2813
2814                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2815                                    IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2816                                    IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2817
2818                 if (ret_val != IXGBE_SUCCESS)
2819                         return ret_val;
2820
2821                 /* Setup SFI internal link. */
2822                 ret_val = ixgbe_setup_sfi_x550a(hw, &speed);
2823         } else {
2824                 /* Configure internal PHY for KR/KX. */
2825                 ixgbe_setup_kr_speed_x550em(hw, speed);
2826
2827                 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2828                         /* Find Address */
2829                         DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2830                         return IXGBE_ERR_PHY_ADDR_INVALID;
2831                 }
2832
2833                 /* Get external PHY SKU id */
2834                 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,
2835                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2836
2837                 if (ret_val != IXGBE_SUCCESS)
2838                         return ret_val;
2839
2840                 /* When configuring quad port CS4223, the MAC instance is part
2841                  * of the slice offset.
2842                  */
2843                 if (reg_phy_ext == IXGBE_CS4223_SKU_ID)
2844                         slice_offset = (hw->bus.lan_id +
2845                                         (hw->bus.instance_id << 1)) << 12;
2846                 else
2847                         slice_offset = hw->bus.lan_id << 12;
2848
2849                 /* Configure CS4227/CS4223 LINE side to proper mode. */
2850                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2851
2852                 ret_val = hw->phy.ops.read_reg(hw, reg_slice,
2853                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2854
2855                 if (ret_val != IXGBE_SUCCESS)
2856                         return ret_val;
2857
2858                 reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) |
2859                                  (IXGBE_CS4227_EDC_MODE_SR << 1));
2860
2861                 if (setup_linear)
2862                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2863                 else
2864                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2865                 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2866                                          IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2867
2868                 /* Flush previous write with a read */
2869                 ret_val = hw->phy.ops.read_reg(hw, reg_slice,
2870                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2871         }
2872         return ret_val;
2873 }
2874
2875 /**
2876  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2877  *  @hw: pointer to hardware structure
2878  *
2879  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2880  **/
2881 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2882 {
2883         struct ixgbe_mac_info *mac = &hw->mac;
2884         s32 status;
2885         u32 reg_val;
2886
2887         /* Disable training protocol FSM. */
2888         status = mac->ops.read_iosf_sb_reg(hw,
2889                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2890                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2891         if (status != IXGBE_SUCCESS)
2892                 return status;
2893         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2894         status = mac->ops.write_iosf_sb_reg(hw,
2895                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2896                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2897         if (status != IXGBE_SUCCESS)
2898                 return status;
2899
2900         /* Disable Flex from training TXFFE. */
2901         status = mac->ops.read_iosf_sb_reg(hw,
2902                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2903                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2904         if (status != IXGBE_SUCCESS)
2905                 return status;
2906         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2907         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2908         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2909         status = mac->ops.write_iosf_sb_reg(hw,
2910                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2911                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2912         if (status != IXGBE_SUCCESS)
2913                 return status;
2914         status = mac->ops.read_iosf_sb_reg(hw,
2915                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2916                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2917         if (status != IXGBE_SUCCESS)
2918                 return status;
2919         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2920         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2921         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2922         status = mac->ops.write_iosf_sb_reg(hw,
2923                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2924                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2925         if (status != IXGBE_SUCCESS)
2926                 return status;
2927
2928         /* Enable override for coefficients. */
2929         status = mac->ops.read_iosf_sb_reg(hw,
2930                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2931                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2932         if (status != IXGBE_SUCCESS)
2933                 return status;
2934         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2935         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2936         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2937         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2938         status = mac->ops.write_iosf_sb_reg(hw,
2939                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2940                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2941         return status;
2942 }
2943
2944 /**
2945  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2946  *  @hw: pointer to hardware structure
2947  *  @speed: the link speed to force
2948  *
2949  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
2950  *  internal and external PHY at a specific speed, without autonegotiation.
2951  **/
2952 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2953 {
2954         struct ixgbe_mac_info *mac = &hw->mac;
2955         s32 status;
2956         u32 reg_val;
2957
2958         /* iXFI is only supported with X552 */
2959         if (mac->type != ixgbe_mac_X550EM_x)
2960                 return IXGBE_ERR_LINK_SETUP;
2961
2962         /* Disable AN and force speed to 10G Serial. */
2963         status = mac->ops.read_iosf_sb_reg(hw,
2964                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2965                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2966         if (status != IXGBE_SUCCESS)
2967                 return status;
2968
2969         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2970         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2971
2972         /* Select forced link speed for internal PHY. */
2973         switch (*speed) {
2974         case IXGBE_LINK_SPEED_10GB_FULL:
2975                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2976                 break;
2977         case IXGBE_LINK_SPEED_1GB_FULL:
2978                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2979                 break;
2980         default:
2981                 /* Other link speeds are not supported by internal KR PHY. */
2982                 return IXGBE_ERR_LINK_SETUP;
2983         }
2984
2985         status = mac->ops.write_iosf_sb_reg(hw,
2986                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2987                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2988         if (status != IXGBE_SUCCESS)
2989                 return status;
2990
2991         /* Additional configuration needed for x550em_x */
2992         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2993                 status = ixgbe_setup_ixfi_x550em_x(hw);
2994                 if (status != IXGBE_SUCCESS)
2995                         return status;
2996         }
2997
2998         /* Toggle port SW reset by AN reset. */
2999         status = ixgbe_restart_an_internal_phy_x550em(hw);
3000
3001         return status;
3002 }
3003
3004 /**
3005  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
3006  * @hw: address of hardware structure
3007  * @link_up: address of boolean to indicate link status
3008  *
3009  * Returns error code if unable to get link status.
3010  */
3011 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
3012 {
3013         u32 ret;
3014         u16 autoneg_status;
3015
3016         *link_up = false;
3017
3018         /* read this twice back to back to indicate current status */
3019         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3020                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3021                                    &autoneg_status);
3022         if (ret != IXGBE_SUCCESS)
3023                 return ret;
3024
3025         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3026                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3027                                    &autoneg_status);
3028         if (ret != IXGBE_SUCCESS)
3029                 return ret;
3030
3031         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
3032
3033         return IXGBE_SUCCESS;
3034 }
3035
3036 /**
3037  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
3038  * @hw: point to hardware structure
3039  *
3040  * Configures the link between the integrated KR PHY and the external X557 PHY
3041  * The driver will call this function when it gets a link status change
3042  * interrupt from the X557 PHY. This function configures the link speed
3043  * between the PHYs to match the link speed of the BASE-T link.
3044  *
3045  * A return of a non-zero value indicates an error, and the base driver should
3046  * not report link up.
3047  */
3048 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
3049 {
3050         ixgbe_link_speed force_speed;
3051         bool link_up;
3052         u32 status;
3053         u16 speed;
3054
3055         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3056                 return IXGBE_ERR_CONFIG;
3057
3058         if (hw->mac.type == ixgbe_mac_X550EM_x &&
3059             !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3060                 /* If link is down, there is no setup necessary so return  */
3061                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3062                 if (status != IXGBE_SUCCESS)
3063                         return status;
3064
3065                 if (!link_up)
3066                         return IXGBE_SUCCESS;
3067
3068                 status = hw->phy.ops.read_reg(hw,
3069                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3070                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3071                                               &speed);
3072                 if (status != IXGBE_SUCCESS)
3073                         return status;
3074
3075                 /* If link is still down - no setup is required so return */
3076                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3077                 if (status != IXGBE_SUCCESS)
3078                         return status;
3079                 if (!link_up)
3080                         return IXGBE_SUCCESS;
3081
3082                 /* clear everything but the speed and duplex bits */
3083                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
3084
3085                 switch (speed) {
3086                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
3087                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3088                         break;
3089                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
3090                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3091                         break;
3092                 default:
3093                         /* Internal PHY does not support anything else */
3094                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
3095                 }
3096
3097                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
3098         } else {
3099                 speed = IXGBE_LINK_SPEED_10GB_FULL |
3100                         IXGBE_LINK_SPEED_1GB_FULL;
3101                 return ixgbe_setup_kr_speed_x550em(hw, speed);
3102         }
3103 }
3104
3105 /**
3106  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
3107  *  @hw: pointer to hardware structure
3108  *
3109  *  Configures the integrated KR PHY to use internal loopback mode.
3110  **/
3111 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
3112 {
3113         s32 status;
3114         u32 reg_val;
3115
3116         /* Disable AN and force speed to 10G Serial. */
3117         status = hw->mac.ops.read_iosf_sb_reg(hw,
3118                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3119                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3120         if (status != IXGBE_SUCCESS)
3121                 return status;
3122         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3123         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3124         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3125         status = hw->mac.ops.write_iosf_sb_reg(hw,
3126                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3127                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3128         if (status != IXGBE_SUCCESS)
3129                 return status;
3130
3131         /* Set near-end loopback clocks. */
3132         status = hw->mac.ops.read_iosf_sb_reg(hw,
3133                                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3134                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3135         if (status != IXGBE_SUCCESS)
3136                 return status;
3137         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3138         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3139         status = hw->mac.ops.write_iosf_sb_reg(hw,
3140                                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3141                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3142         if (status != IXGBE_SUCCESS)
3143                 return status;
3144
3145         /* Set loopback enable. */
3146         status = hw->mac.ops.read_iosf_sb_reg(hw,
3147                                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3148                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3149         if (status != IXGBE_SUCCESS)
3150                 return status;
3151         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3152         status = hw->mac.ops.write_iosf_sb_reg(hw,
3153                                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3154                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3155         if (status != IXGBE_SUCCESS)
3156                 return status;
3157
3158         /* Training bypass. */
3159         status = hw->mac.ops.read_iosf_sb_reg(hw,
3160                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3161                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3162         if (status != IXGBE_SUCCESS)
3163                 return status;
3164         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3165         status = hw->mac.ops.write_iosf_sb_reg(hw,
3166                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3167                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3168
3169         return status;
3170 }
3171
3172 /**
3173  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3174  *  assuming that the semaphore is already obtained.
3175  *  @hw: pointer to hardware structure
3176  *  @offset: offset of  word in the EEPROM to read
3177  *  @data: word read from the EEPROM
3178  *
3179  *  Reads a 16 bit word from the EEPROM using the hostif.
3180  **/
3181 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
3182 {
3183         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3184         struct ixgbe_hic_read_shadow_ram buffer;
3185         s32 status;
3186
3187         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3188         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3189         buffer.hdr.req.buf_lenh = 0;
3190         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3191         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3192
3193         /* convert offset from words to bytes */
3194         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3195         /* one word */
3196         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3197
3198         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3199         if (status)
3200                 return status;
3201
3202         status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3203                                     IXGBE_HI_COMMAND_TIMEOUT);
3204         if (!status) {
3205                 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3206                                                   FW_NVM_DATA_OFFSET);
3207         }
3208
3209         hw->mac.ops.release_swfw_sync(hw, mask);
3210         return status;
3211 }
3212
3213 /**
3214  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3215  *  @hw: pointer to hardware structure
3216  *  @offset: offset of  word in the EEPROM to read
3217  *  @words: number of words
3218  *  @data: word(s) read from the EEPROM
3219  *
3220  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
3221  **/
3222 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3223                                      u16 offset, u16 words, u16 *data)
3224 {
3225         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3226         struct ixgbe_hic_read_shadow_ram buffer;
3227         u32 current_word = 0;
3228         u16 words_to_read;
3229         s32 status;
3230         u32 i;
3231
3232         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3233
3234         /* Take semaphore for the entire operation. */
3235         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3236         if (status) {
3237                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3238                 return status;
3239         }
3240
3241         while (words) {
3242                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3243                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3244                 else
3245                         words_to_read = words;
3246
3247                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3248                 buffer.hdr.req.buf_lenh = 0;
3249                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3250                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3251
3252                 /* convert offset from words to bytes */
3253                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3254                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3255
3256                 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3257                                             IXGBE_HI_COMMAND_TIMEOUT);
3258
3259                 if (status) {
3260                         DEBUGOUT("Host interface command failed\n");
3261                         goto out;
3262                 }
3263
3264                 for (i = 0; i < words_to_read; i++) {
3265                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3266                                   2 * i;
3267                         u32 value = IXGBE_READ_REG(hw, reg);
3268
3269                         data[current_word] = (u16)(value & 0xffff);
3270                         current_word++;
3271                         i++;
3272                         if (i < words_to_read) {
3273                                 value >>= 16;
3274                                 data[current_word] = (u16)(value & 0xffff);
3275                                 current_word++;
3276                         }
3277                 }
3278                 words -= words_to_read;
3279         }
3280
3281 out:
3282         hw->mac.ops.release_swfw_sync(hw, mask);
3283         return status;
3284 }
3285
3286 /**
3287  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3288  *  @hw: pointer to hardware structure
3289  *  @offset: offset of  word in the EEPROM to write
3290  *  @data: word write to the EEPROM
3291  *
3292  *  Write a 16 bit word to the EEPROM using the hostif.
3293  **/
3294 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3295                                     u16 data)
3296 {
3297         s32 status;
3298         struct ixgbe_hic_write_shadow_ram buffer;
3299
3300         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3301
3302         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3303         buffer.hdr.req.buf_lenh = 0;
3304         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3305         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3306
3307          /* one word */
3308         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3309         buffer.data = data;
3310         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3311
3312         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3313                                               sizeof(buffer),
3314                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3315
3316         return status;
3317 }
3318
3319 /**
3320  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3321  *  @hw: pointer to hardware structure
3322  *  @offset: offset of  word in the EEPROM to write
3323  *  @data: word write to the EEPROM
3324  *
3325  *  Write a 16 bit word to the EEPROM using the hostif.
3326  **/
3327 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3328                                u16 data)
3329 {
3330         s32 status = IXGBE_SUCCESS;
3331
3332         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3333
3334         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3335             IXGBE_SUCCESS) {
3336                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3337                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3338         } else {
3339                 DEBUGOUT("write ee hostif failed to get semaphore");
3340                 status = IXGBE_ERR_SWFW_SYNC;
3341         }
3342
3343         return status;
3344 }
3345
3346 /**
3347  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3348  *  @hw: pointer to hardware structure
3349  *  @offset: offset of  word in the EEPROM to write
3350  *  @words: number of words
3351  *  @data: word(s) write to the EEPROM
3352  *
3353  *  Write a 16 bit word(s) to the EEPROM using the hostif.
3354  **/
3355 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3356                                       u16 offset, u16 words, u16 *data)
3357 {
3358         s32 status = IXGBE_SUCCESS;
3359         u32 i = 0;
3360
3361         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3362
3363         /* Take semaphore for the entire operation. */
3364         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3365         if (status != IXGBE_SUCCESS) {
3366                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3367                 goto out;
3368         }
3369
3370         for (i = 0; i < words; i++) {
3371                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3372                                                          data[i]);
3373
3374                 if (status != IXGBE_SUCCESS) {
3375                         DEBUGOUT("Eeprom buffered write failed\n");
3376                         break;
3377                 }
3378         }
3379
3380         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3381 out:
3382
3383         return status;
3384 }
3385
3386 /**
3387  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3388  * @hw: pointer to hardware structure
3389  * @ptr: pointer offset in eeprom
3390  * @size: size of section pointed by ptr, if 0 first word will be used as size
3391  * @csum: address of checksum to update
3392  *
3393  * Returns error status for any failure
3394  */
3395 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3396                                    u16 size, u16 *csum, u16 *buffer,
3397                                    u32 buffer_size)
3398 {
3399         u16 buf[256];
3400         s32 status;
3401         u16 length, bufsz, i, start;
3402         u16 *local_buffer;
3403
3404         bufsz = sizeof(buf) / sizeof(buf[0]);
3405
3406         /* Read a chunk at the pointer location */
3407         if (!buffer) {
3408                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3409                 if (status) {
3410                         DEBUGOUT("Failed to read EEPROM image\n");
3411                         return status;
3412                 }
3413                 local_buffer = buf;
3414         } else {
3415                 if (buffer_size < ptr)
3416                         return  IXGBE_ERR_PARAM;
3417                 local_buffer = &buffer[ptr];
3418         }
3419
3420         if (size) {
3421                 start = 0;
3422                 length = size;
3423         } else {
3424                 start = 1;
3425                 length = local_buffer[0];
3426
3427                 /* Skip pointer section if length is invalid. */
3428                 if (length == 0xFFFF || length == 0 ||
3429                     (ptr + length) >= hw->eeprom.word_size)
3430                         return IXGBE_SUCCESS;
3431         }
3432
3433         if (buffer && ((u32)start + (u32)length > buffer_size))
3434                 return IXGBE_ERR_PARAM;
3435
3436         for (i = start; length; i++, length--) {
3437                 if (i == bufsz && !buffer) {
3438                         ptr += bufsz;
3439                         i = 0;
3440                         if (length < bufsz)
3441                                 bufsz = length;
3442
3443                         /* Read a chunk at the pointer location */
3444                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3445                                                                   bufsz, buf);
3446                         if (status) {
3447                                 DEBUGOUT("Failed to read EEPROM image\n");
3448                                 return status;
3449                         }
3450                 }
3451                 *csum += local_buffer[i];
3452         }
3453         return IXGBE_SUCCESS;
3454 }
3455
3456 /**
3457  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3458  *  @hw: pointer to hardware structure
3459  *  @buffer: pointer to buffer containing calculated checksum
3460  *  @buffer_size: size of buffer
3461  *
3462  *  Returns a negative error code on error, or the 16-bit checksum
3463  **/
3464 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3465 {
3466         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3467         u16 *local_buffer;
3468         s32 status;
3469         u16 checksum = 0;
3470         u16 pointer, i, size;
3471
3472         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3473
3474         hw->eeprom.ops.init_params(hw);
3475
3476         if (!buffer) {
3477                 /* Read pointer area */
3478                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3479                                                      IXGBE_EEPROM_LAST_WORD + 1,
3480                                                      eeprom_ptrs);
3481                 if (status) {
3482                         DEBUGOUT("Failed to read EEPROM image\n");
3483                         return status;
3484                 }
3485                 local_buffer = eeprom_ptrs;
3486         } else {
3487                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3488                         return IXGBE_ERR_PARAM;
3489                 local_buffer = buffer;
3490         }
3491
3492         /*
3493          * For X550 hardware include 0x0-0x41 in the checksum, skip the
3494          * checksum word itself
3495          */
3496         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3497                 if (i != IXGBE_EEPROM_CHECKSUM)
3498                         checksum += local_buffer[i];
3499
3500         /*
3501          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
3502          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3503          */
3504         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3505                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3506                         continue;
3507
3508                 pointer = local_buffer[i];
3509
3510                 /* Skip pointer section if the pointer is invalid. */
3511                 if (pointer == 0xFFFF || pointer == 0 ||
3512                     pointer >= hw->eeprom.word_size)
3513                         continue;
3514
3515                 switch (i) {
3516                 case IXGBE_PCIE_GENERAL_PTR:
3517                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3518                         break;
3519                 case IXGBE_PCIE_CONFIG0_PTR:
3520                 case IXGBE_PCIE_CONFIG1_PTR:
3521                         size = IXGBE_PCIE_CONFIG_SIZE;
3522                         break;
3523                 default:
3524                         size = 0;
3525                         break;
3526                 }
3527
3528                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3529                                                 buffer, buffer_size);
3530                 if (status)
3531                         return status;
3532         }
3533
3534         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3535
3536         return (s32)checksum;
3537 }
3538
3539 /**
3540  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3541  *  @hw: pointer to hardware structure
3542  *
3543  *  Returns a negative error code on error, or the 16-bit checksum
3544  **/
3545 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3546 {
3547         return ixgbe_calc_checksum_X550(hw, NULL, 0);
3548 }
3549
3550 /**
3551  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3552  *  @hw: pointer to hardware structure
3553  *  @checksum_val: calculated checksum
3554  *
3555  *  Performs checksum calculation and validates the EEPROM checksum.  If the
3556  *  caller does not need checksum_val, the value can be NULL.
3557  **/
3558 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3559 {
3560         s32 status;
3561         u16 checksum;
3562         u16 read_checksum = 0;
3563
3564         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3565
3566         /* Read the first word from the EEPROM. If this times out or fails, do
3567          * not continue or we could be in for a very long wait while every
3568          * EEPROM read fails
3569          */
3570         status = hw->eeprom.ops.read(hw, 0, &checksum);
3571         if (status) {
3572                 DEBUGOUT("EEPROM read failed\n");
3573                 return status;
3574         }
3575
3576         status = hw->eeprom.ops.calc_checksum(hw);
3577         if (status < 0)
3578                 return status;
3579
3580         checksum = (u16)(status & 0xffff);
3581
3582         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3583                                            &read_checksum);
3584         if (status)
3585                 return status;
3586
3587         /* Verify read checksum from EEPROM is the same as
3588          * calculated checksum
3589          */
3590         if (read_checksum != checksum) {
3591                 status = IXGBE_ERR_EEPROM_CHECKSUM;
3592                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3593                              "Invalid EEPROM checksum");
3594         }
3595
3596         /* If the user cares, return the calculated checksum */
3597         if (checksum_val)
3598                 *checksum_val = checksum;
3599
3600         return status;
3601 }
3602
3603 /**
3604  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3605  * @hw: pointer to hardware structure
3606  *
3607  * After writing EEPROM to shadow RAM using EEWR register, software calculates
3608  * checksum and updates the EEPROM and instructs the hardware to update
3609  * the flash.
3610  **/
3611 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3612 {
3613         s32 status;
3614         u16 checksum = 0;
3615
3616         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3617
3618         /* Read the first word from the EEPROM. If this times out or fails, do
3619          * not continue or we could be in for a very long wait while every
3620          * EEPROM read fails
3621          */
3622         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3623         if (status) {
3624                 DEBUGOUT("EEPROM read failed\n");
3625                 return status;
3626         }
3627
3628         status = ixgbe_calc_eeprom_checksum_X550(hw);
3629         if (status < 0)
3630                 return status;
3631
3632         checksum = (u16)(status & 0xffff);
3633
3634         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3635                                             checksum);
3636         if (status)
3637                 return status;
3638
3639         status = ixgbe_update_flash_X550(hw);
3640
3641         return status;
3642 }
3643
3644 /**
3645  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3646  *  @hw: pointer to hardware structure
3647  *
3648  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3649  **/
3650 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3651 {
3652         s32 status = IXGBE_SUCCESS;
3653         union ixgbe_hic_hdr2 buffer;
3654
3655         DEBUGFUNC("ixgbe_update_flash_X550");
3656
3657         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3658         buffer.req.buf_lenh = 0;
3659         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3660         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3661
3662         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3663                                               sizeof(buffer),
3664                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3665
3666         return status;
3667 }
3668
3669 /**
3670  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3671  *  @hw: pointer to hardware structure
3672  *
3673  *  Determines physical layer capabilities of the current configuration.
3674  **/
3675 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3676 {
3677         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3678         u16 ext_ability = 0;
3679
3680         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3681
3682         hw->phy.ops.identify(hw);
3683
3684         switch (hw->phy.type) {
3685         case ixgbe_phy_x550em_kr:
3686         case ixgbe_phy_x550em_xfi:
3687                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3688                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3689                 break;
3690         case ixgbe_phy_x550em_kx4:
3691                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3692                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3693                 break;
3694         case ixgbe_phy_x550em_ext_t:
3695                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3696                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3697                                      &ext_ability);
3698                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3699                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3700                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3701                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3702                 break;
3703         case ixgbe_phy_fw:
3704                 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_1GB_FULL)
3705                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3706                 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_100_FULL)
3707                         physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
3708                 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_10_FULL)
3709                         physical_layer |= IXGBE_PHYSICAL_LAYER_10BASE_T;
3710                 break;
3711         case ixgbe_phy_sgmii:
3712                 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3713                 break;
3714         case ixgbe_phy_ext_1g_t:
3715                 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3716                 break;
3717         default:
3718                 break;
3719         }
3720
3721         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3722                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3723
3724         return physical_layer;
3725 }
3726
3727 /**
3728  * ixgbe_get_bus_info_x550em - Set PCI bus info
3729  * @hw: pointer to hardware structure
3730  *
3731  * Sets bus link width and speed to unknown because X550em is
3732  * not a PCI device.
3733  **/
3734 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3735 {
3736
3737         DEBUGFUNC("ixgbe_get_bus_info_x550em");
3738
3739         hw->bus.width = ixgbe_bus_width_unknown;
3740         hw->bus.speed = ixgbe_bus_speed_unknown;
3741
3742         hw->mac.ops.set_lan_id(hw);
3743
3744         return IXGBE_SUCCESS;
3745 }
3746
3747 /**
3748  * ixgbe_disable_rx_x550 - Disable RX unit
3749  *
3750  * Enables the Rx DMA unit for x550
3751  **/
3752 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3753 {
3754         u32 rxctrl, pfdtxgswc;
3755         s32 status;
3756         struct ixgbe_hic_disable_rxen fw_cmd;
3757
3758         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3759
3760         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3761         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3762                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3763                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3764                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3765                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3766                         hw->mac.set_lben = true;
3767                 } else {
3768                         hw->mac.set_lben = false;
3769                 }
3770
3771                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3772                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3773                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3774                 fw_cmd.port_number = (u8)hw->bus.lan_id;
3775
3776                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3777                                         sizeof(struct ixgbe_hic_disable_rxen),
3778                                         IXGBE_HI_COMMAND_TIMEOUT, true);
3779
3780                 /* If we fail - disable RX using register write */
3781                 if (status) {
3782                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3783                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3784                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3785                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3786                         }
3787                 }
3788         }
3789 }
3790
3791 /**
3792  * ixgbe_enter_lplu_x550em - Transition to low power states
3793  *  @hw: pointer to hardware structure
3794  *
3795  * Configures Low Power Link Up on transition to low power states
3796  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3797  * X557 PHY immediately prior to entering LPLU.
3798  **/
3799 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3800 {
3801         u16 an_10g_cntl_reg, autoneg_reg, speed;
3802         s32 status;
3803         ixgbe_link_speed lcd_speed;
3804         u32 save_autoneg;
3805         bool link_up;
3806
3807         /* SW LPLU not required on later HW revisions. */
3808         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3809             (IXGBE_FUSES0_REV_MASK &
3810              IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3811                 return IXGBE_SUCCESS;
3812
3813         /* If blocked by MNG FW, then don't restart AN */
3814         if (ixgbe_check_reset_blocked(hw))
3815                 return IXGBE_SUCCESS;
3816
3817         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3818         if (status != IXGBE_SUCCESS)
3819                 return status;
3820
3821         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3822
3823         if (status != IXGBE_SUCCESS)
3824                 return status;
3825
3826         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3827          * disabled, then force link down by entering low power mode.
3828          */
3829         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3830             !(hw->wol_enabled || ixgbe_mng_present(hw)))
3831                 return ixgbe_set_copper_phy_power(hw, FALSE);
3832
3833         /* Determine LCD */
3834         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3835
3836         if (status != IXGBE_SUCCESS)
3837                 return status;
3838
3839         /* If no valid LCD link speed, then force link down and exit. */
3840         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3841                 return ixgbe_set_copper_phy_power(hw, FALSE);
3842
3843         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3844                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3845                                       &speed);
3846
3847         if (status != IXGBE_SUCCESS)
3848                 return status;
3849
3850         /* If no link now, speed is invalid so take link down */
3851         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3852         if (status != IXGBE_SUCCESS)
3853                 return ixgbe_set_copper_phy_power(hw, false);
3854
3855         /* clear everything but the speed bits */
3856         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3857
3858         /* If current speed is already LCD, then exit. */
3859         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3860              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3861             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3862              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3863                 return status;
3864
3865         /* Clear AN completed indication */
3866         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3867                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3868                                       &autoneg_reg);
3869
3870         if (status != IXGBE_SUCCESS)
3871                 return status;
3872
3873         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3874                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3875                              &an_10g_cntl_reg);
3876
3877         if (status != IXGBE_SUCCESS)
3878                 return status;
3879
3880         status = hw->phy.ops.read_reg(hw,
3881                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3882                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3883                              &autoneg_reg);
3884
3885         if (status != IXGBE_SUCCESS)
3886                 return status;
3887
3888         save_autoneg = hw->phy.autoneg_advertised;
3889
3890         /* Setup link at least common link speed */
3891         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3892
3893         /* restore autoneg from before setting lplu speed */
3894         hw->phy.autoneg_advertised = save_autoneg;
3895
3896         return status;
3897 }
3898
3899 /**
3900  * ixgbe_get_lcd_x550em - Determine lowest common denominator
3901  *  @hw: pointer to hardware structure
3902  *  @lcd_speed: pointer to lowest common link speed
3903  *
3904  * Determine lowest common link speed with link partner.
3905  **/
3906 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3907 {
3908         u16 an_lp_status;
3909         s32 status;
3910         u16 word = hw->eeprom.ctrl_word_3;
3911
3912         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3913
3914         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3915                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3916                                       &an_lp_status);
3917
3918         if (status != IXGBE_SUCCESS)
3919                 return status;
3920
3921         /* If link partner advertised 1G, return 1G */
3922         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3923                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3924                 return status;
3925         }
3926
3927         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3928         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3929             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3930                 return status;
3931
3932         /* Link partner not capable of lower speeds, return 10G */
3933         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3934         return status;
3935 }
3936
3937 /**
3938  *  ixgbe_setup_fc_X550em - Set up flow control
3939  *  @hw: pointer to hardware structure
3940  *
3941  *  Called at init time to set up flow control.
3942  **/
3943 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3944 {
3945         s32 ret_val = IXGBE_SUCCESS;
3946         u32 pause, asm_dir, reg_val;
3947
3948         DEBUGFUNC("ixgbe_setup_fc_X550em");
3949
3950         /* Validate the requested mode */
3951         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3952                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3953                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3954                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3955                 goto out;
3956         }
3957
3958         /* 10gig parts do not have a word in the EEPROM to determine the
3959          * default flow control setting, so we explicitly set it to full.
3960          */
3961         if (hw->fc.requested_mode == ixgbe_fc_default)
3962                 hw->fc.requested_mode = ixgbe_fc_full;
3963
3964         /* Determine PAUSE and ASM_DIR bits. */
3965         switch (hw->fc.requested_mode) {
3966         case ixgbe_fc_none:
3967                 pause = 0;
3968                 asm_dir = 0;
3969                 break;
3970         case ixgbe_fc_tx_pause:
3971                 pause = 0;
3972                 asm_dir = 1;
3973                 break;
3974         case ixgbe_fc_rx_pause:
3975                 /* Rx Flow control is enabled and Tx Flow control is
3976                  * disabled by software override. Since there really
3977                  * isn't a way to advertise that we are capable of RX
3978                  * Pause ONLY, we will advertise that we support both
3979                  * symmetric and asymmetric Rx PAUSE, as such we fall
3980                  * through to the fc_full statement.  Later, we will
3981                  * disable the adapter's ability to send PAUSE frames.
3982                  */
3983         case ixgbe_fc_full:
3984                 pause = 1;
3985                 asm_dir = 1;
3986                 break;
3987         default:
3988                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3989                         "Flow control param set incorrectly\n");
3990                 ret_val = IXGBE_ERR_CONFIG;
3991                 goto out;
3992         }
3993
3994         switch (hw->device_id) {
3995         case IXGBE_DEV_ID_X550EM_X_KR:
3996         case IXGBE_DEV_ID_X550EM_A_KR:
3997         case IXGBE_DEV_ID_X550EM_A_KR_L:
3998                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
3999                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4000                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
4001                 if (ret_val != IXGBE_SUCCESS)
4002                         goto out;
4003                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4004                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4005                 if (pause)
4006                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4007                 if (asm_dir)
4008                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4009                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
4010                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4011                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
4012
4013                 /* This device does not fully support AN. */
4014                 hw->fc.disable_fc_autoneg = true;
4015                 break;
4016         default:
4017                 break;
4018         }
4019
4020 out:
4021         return ret_val;
4022 }
4023
4024 /**
4025  *  ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
4026  *  @hw: pointer to hardware structure
4027  *
4028  *  Enable flow control according to IEEE clause 37.
4029  **/
4030 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
4031 {
4032         u32 link_s1, lp_an_page_low, an_cntl_1;
4033         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4034         ixgbe_link_speed speed;
4035         bool link_up;
4036
4037         /* AN should have completed when the cable was plugged in.
4038          * Look for reasons to bail out.  Bail out if:
4039          * - FC autoneg is disabled, or if
4040          * - link is not up.
4041          */
4042         if (hw->fc.disable_fc_autoneg) {
4043                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4044                              "Flow control autoneg is disabled");
4045                 goto out;
4046         }
4047
4048         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4049         if (!link_up) {
4050                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4051                 goto out;
4052         }
4053
4054         /* Check at auto-negotiation has completed */
4055         status = hw->mac.ops.read_iosf_sb_reg(hw,
4056                                         IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4057                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4058
4059         if (status != IXGBE_SUCCESS ||
4060             (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4061                 DEBUGOUT("Auto-Negotiation did not complete\n");
4062                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4063                 goto out;
4064         }
4065
4066         /* Read the 10g AN autoc and LP ability registers and resolve
4067          * local flow control settings accordingly
4068          */
4069         status = hw->mac.ops.read_iosf_sb_reg(hw,
4070                                 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4071                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
4072
4073         if (status != IXGBE_SUCCESS) {
4074                 DEBUGOUT("Auto-Negotiation did not complete\n");
4075                 goto out;
4076         }
4077
4078         status = hw->mac.ops.read_iosf_sb_reg(hw,
4079                                 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
4080                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
4081
4082         if (status != IXGBE_SUCCESS) {
4083                 DEBUGOUT("Auto-Negotiation did not complete\n");
4084                 goto out;
4085         }
4086
4087         status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
4088                                     IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
4089                                     IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
4090                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
4091                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
4092
4093 out:
4094         if (status == IXGBE_SUCCESS) {
4095                 hw->fc.fc_was_autonegged = true;
4096         } else {
4097                 hw->fc.fc_was_autonegged = false;
4098                 hw->fc.current_mode = hw->fc.requested_mode;
4099         }
4100 }
4101
4102 /**
4103  *  ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
4104  *  @hw: pointer to hardware structure
4105  *
4106  **/
4107 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
4108 {
4109         hw->fc.fc_was_autonegged = false;
4110         hw->fc.current_mode = hw->fc.requested_mode;
4111 }
4112
4113 /**
4114  *  ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
4115  *  @hw: pointer to hardware structure
4116  *
4117  *  Enable flow control according to IEEE clause 37.
4118  **/
4119 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
4120 {
4121         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4122         u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
4123         ixgbe_link_speed speed;
4124         bool link_up;
4125
4126         /* AN should have completed when the cable was plugged in.
4127          * Look for reasons to bail out.  Bail out if:
4128          * - FC autoneg is disabled, or if
4129          * - link is not up.
4130          */
4131         if (hw->fc.disable_fc_autoneg) {
4132                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4133                              "Flow control autoneg is disabled");
4134                 goto out;
4135         }
4136
4137         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4138         if (!link_up) {
4139                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4140                 goto out;
4141         }
4142
4143         /* Check if auto-negotiation has completed */
4144         status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info);
4145         if (status != IXGBE_SUCCESS ||
4146             !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) {
4147                 DEBUGOUT("Auto-Negotiation did not complete\n");
4148                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4149                 goto out;
4150         }
4151
4152         /* Negotiate the flow control */
4153         status = ixgbe_negotiate_fc(hw, info[0], info[0],
4154                                     FW_PHY_ACT_GET_LINK_INFO_FC_RX,
4155                                     FW_PHY_ACT_GET_LINK_INFO_FC_TX,
4156                                     FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX,
4157                                     FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX);
4158
4159 out:
4160         if (status == IXGBE_SUCCESS) {
4161                 hw->fc.fc_was_autonegged = true;
4162         } else {
4163                 hw->fc.fc_was_autonegged = false;
4164                 hw->fc.current_mode = hw->fc.requested_mode;
4165         }
4166 }
4167
4168 /**
4169  *  ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4170  *  @hw: pointer to hardware structure
4171  *
4172  *  Called at init time to set up flow control.
4173  **/
4174 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4175 {
4176         s32 status = IXGBE_SUCCESS;
4177         u32 an_cntl = 0;
4178
4179         DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4180
4181         /* Validate the requested mode */
4182         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4183                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4184                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4185                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4186         }
4187
4188         if (hw->fc.requested_mode == ixgbe_fc_default)
4189                 hw->fc.requested_mode = ixgbe_fc_full;
4190
4191         /* Set up the 1G and 10G flow control advertisement registers so the
4192          * HW will be able to do FC autoneg once the cable is plugged in.  If
4193          * we link at 10G, the 1G advertisement is harmless and vice versa.
4194          */
4195         status = hw->mac.ops.read_iosf_sb_reg(hw,
4196                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4197                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4198
4199         if (status != IXGBE_SUCCESS) {
4200                 DEBUGOUT("Auto-Negotiation did not complete\n");
4201                 return status;
4202         }
4203
4204         /* The possible values of fc.requested_mode are:
4205          * 0: Flow control is completely disabled
4206          * 1: Rx flow control is enabled (we can receive pause frames,
4207          *    but not send pause frames).
4208          * 2: Tx flow control is enabled (we can send pause frames but
4209          *    we do not support receiving pause frames).
4210          * 3: Both Rx and Tx flow control (symmetric) are enabled.
4211          * other: Invalid.
4212          */
4213         switch (hw->fc.requested_mode) {
4214         case ixgbe_fc_none:
4215                 /* Flow control completely disabled by software override. */
4216                 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4217                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4218                 break;
4219         case ixgbe_fc_tx_pause:
4220                 /* Tx Flow control is enabled, and Rx Flow control is
4221                  * disabled by software override.
4222                  */
4223                 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4224                 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4225                 break;
4226         case ixgbe_fc_rx_pause:
4227                 /* Rx Flow control is enabled and Tx Flow control is
4228                  * disabled by software override. Since there really
4229                  * isn't a way to advertise that we are capable of RX
4230                  * Pause ONLY, we will advertise that we support both
4231                  * symmetric and asymmetric Rx PAUSE, as such we fall
4232                  * through to the fc_full statement.  Later, we will
4233                  * disable the adapter's ability to send PAUSE frames.
4234                  */
4235         case ixgbe_fc_full:
4236                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4237                 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4238                            IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4239                 break;
4240         default:
4241                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4242                               "Flow control param set incorrectly\n");
4243                 return IXGBE_ERR_CONFIG;
4244         }
4245
4246         status = hw->mac.ops.write_iosf_sb_reg(hw,
4247                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4248                                         IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4249
4250         /* Restart auto-negotiation. */
4251         status = ixgbe_restart_an_internal_phy_x550em(hw);
4252
4253         return status;
4254 }
4255
4256 /**
4257  * ixgbe_set_mux - Set mux for port 1 access with CS4227
4258  * @hw: pointer to hardware structure
4259  * @state: set mux if 1, clear if 0
4260  */
4261 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4262 {
4263         u32 esdp;
4264
4265         if (!hw->bus.lan_id)
4266                 return;
4267         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4268         if (state)
4269                 esdp |= IXGBE_ESDP_SDP1;
4270         else
4271                 esdp &= ~IXGBE_ESDP_SDP1;
4272         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4273         IXGBE_WRITE_FLUSH(hw);
4274 }
4275
4276 /**
4277  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4278  *  @hw: pointer to hardware structure
4279  *  @mask: Mask to specify which semaphore to acquire
4280  *
4281  *  Acquires the SWFW semaphore and sets the I2C MUX
4282  **/
4283 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4284 {
4285         s32 status;
4286
4287         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4288
4289         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4290         if (status)
4291                 return status;
4292
4293         if (mask & IXGBE_GSSR_I2C_MASK)
4294                 ixgbe_set_mux(hw, 1);
4295
4296         return IXGBE_SUCCESS;
4297 }
4298
4299 /**
4300  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4301  *  @hw: pointer to hardware structure
4302  *  @mask: Mask to specify which semaphore to release
4303  *
4304  *  Releases the SWFW semaphore and sets the I2C MUX
4305  **/
4306 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4307 {
4308         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4309
4310         if (mask & IXGBE_GSSR_I2C_MASK)
4311                 ixgbe_set_mux(hw, 0);
4312
4313         ixgbe_release_swfw_sync_X540(hw, mask);
4314 }
4315
4316 /**
4317  *  ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4318  *  @hw: pointer to hardware structure
4319  *  @mask: Mask to specify which semaphore to acquire
4320  *
4321  *  Acquires the SWFW semaphore and get the shared phy token as needed
4322  */
4323 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4324 {
4325         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4326         int retries = FW_PHY_TOKEN_RETRIES;
4327         s32 status = IXGBE_SUCCESS;
4328
4329         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4330
4331         while (--retries) {
4332                 status = IXGBE_SUCCESS;
4333                 if (hmask)
4334                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4335                 if (status)
4336                         return status;
4337                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4338                         return IXGBE_SUCCESS;
4339
4340                 status = ixgbe_get_phy_token(hw);
4341                 if (status == IXGBE_SUCCESS)
4342                         return IXGBE_SUCCESS;
4343
4344                 if (hmask)
4345                         ixgbe_release_swfw_sync_X540(hw, hmask);
4346                 if (status != IXGBE_ERR_TOKEN_RETRY)
4347                         return status;
4348         }
4349
4350         return status;
4351 }
4352
4353 /**
4354  *  ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4355  *  @hw: pointer to hardware structure
4356  *  @mask: Mask to specify which semaphore to release
4357  *
4358  *  Releases the SWFW semaphore and puts the shared phy token as needed
4359  */
4360 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4361 {
4362         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4363
4364         DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4365
4366         if (mask & IXGBE_GSSR_TOKEN_SM)
4367                 ixgbe_put_phy_token(hw);
4368
4369         if (hmask)
4370                 ixgbe_release_swfw_sync_X540(hw, hmask);
4371 }
4372
4373 /**
4374  *  ixgbe_read_phy_reg_x550a  - Reads specified PHY register
4375  *  @hw: pointer to hardware structure
4376  *  @reg_addr: 32 bit address of PHY register to read
4377  *  @phy_data: Pointer to read data from PHY register
4378  *
4379  *  Reads a value from a specified PHY register using the SWFW lock and PHY
4380  *  Token. The PHY Token is needed since the MDIO is shared between to MAC
4381  *  instances.
4382  **/
4383 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4384                                u32 device_type, u16 *phy_data)
4385 {
4386         s32 status;
4387         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4388
4389         DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4390
4391         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4392                 return IXGBE_ERR_SWFW_SYNC;
4393
4394         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4395
4396         hw->mac.ops.release_swfw_sync(hw, mask);
4397
4398         return status;
4399 }
4400
4401 /**
4402  *  ixgbe_write_phy_reg_x550a - Writes specified PHY register
4403  *  @hw: pointer to hardware structure
4404  *  @reg_addr: 32 bit PHY register to write
4405  *  @device_type: 5 bit device type
4406  *  @phy_data: Data to write to the PHY register
4407  *
4408  *  Writes a value to specified PHY register using the SWFW lock and PHY Token.
4409  *  The PHY Token is needed since the MDIO is shared between to MAC instances.
4410  **/
4411 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4412                                 u32 device_type, u16 phy_data)
4413 {
4414         s32 status;
4415         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4416
4417         DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4418
4419         if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4420                 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
4421                                                  phy_data);
4422                 hw->mac.ops.release_swfw_sync(hw, mask);
4423         } else {
4424                 status = IXGBE_ERR_SWFW_SYNC;
4425         }
4426
4427         return status;
4428 }
4429
4430 /**
4431  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4432  * @hw: pointer to hardware structure
4433  *
4434  * Handle external Base T PHY interrupt. If high temperature
4435  * failure alarm then return error, else if link status change
4436  * then setup internal/external PHY link
4437  *
4438  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4439  * failure alarm, else return PHY access status.
4440  */
4441 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4442 {
4443         bool lsc;
4444         u32 status;
4445
4446         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4447
4448         if (status != IXGBE_SUCCESS)
4449                 return status;
4450
4451         if (lsc)
4452                 return ixgbe_setup_internal_phy(hw);
4453
4454         return IXGBE_SUCCESS;
4455 }
4456
4457 /**
4458  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4459  * @hw: pointer to hardware structure
4460  * @speed: new link speed
4461  * @autoneg_wait_to_complete: true when waiting for completion is needed
4462  *
4463  * Setup internal/external PHY link speed based on link speed, then set
4464  * external PHY auto advertised link speed.
4465  *
4466  * Returns error status for any failure
4467  **/
4468 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4469                                   ixgbe_link_speed speed,
4470                                   bool autoneg_wait_to_complete)
4471 {
4472         s32 status;
4473         ixgbe_link_speed force_speed;
4474
4475         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4476
4477         /* Setup internal/external PHY link speed to iXFI (10G), unless
4478          * only 1G is auto advertised then setup KX link.
4479          */
4480         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4481                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4482         else
4483                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4484
4485         /* If X552 and internal link mode is XFI, then setup XFI internal link.
4486          */
4487         if (hw->mac.type == ixgbe_mac_X550EM_x &&
4488             !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4489                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4490
4491                 if (status != IXGBE_SUCCESS)
4492                         return status;
4493         }
4494
4495         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4496 }
4497
4498 /**
4499  * ixgbe_check_link_t_X550em - Determine link and speed status
4500  * @hw: pointer to hardware structure
4501  * @speed: pointer to link speed
4502  * @link_up: true when link is up
4503  * @link_up_wait_to_complete: bool used to wait for link up or not
4504  *
4505  * Check that both the MAC and X557 external PHY have link.
4506  **/
4507 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4508                               bool *link_up, bool link_up_wait_to_complete)
4509 {
4510         u32 status;
4511         u16 i, autoneg_status = 0;
4512
4513         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4514                 return IXGBE_ERR_CONFIG;
4515
4516         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4517                                               link_up_wait_to_complete);
4518
4519         /* If check link fails or MAC link is not up, then return */
4520         if (status != IXGBE_SUCCESS || !(*link_up))
4521                 return status;
4522
4523         /* MAC link is up, so check external PHY link.
4524          * X557 PHY. Link status is latching low, and can only be used to detect
4525          * link drop, and not the current status of the link without performing
4526          * back-to-back reads.
4527          */
4528         for (i = 0; i < 2; i++) {
4529                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4530                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4531                                               &autoneg_status);
4532
4533                 if (status != IXGBE_SUCCESS)
4534                         return status;
4535         }
4536
4537         /* If external PHY link is not up, then indicate link not up */
4538         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4539                 *link_up = false;
4540
4541         return IXGBE_SUCCESS;
4542 }
4543
4544 /**
4545  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4546  *  @hw: pointer to hardware structure
4547  **/
4548 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4549 {
4550         s32 status;
4551
4552         status = ixgbe_reset_phy_generic(hw);
4553
4554         if (status != IXGBE_SUCCESS)
4555                 return status;
4556
4557         /* Configure Link Status Alarm and Temperature Threshold interrupts */
4558         return ixgbe_enable_lasi_ext_t_x550em(hw);
4559 }
4560
4561 /**
4562  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4563  *  @hw: pointer to hardware structure
4564  *  @led_idx: led number to turn on
4565  **/
4566 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4567 {
4568         u16 phy_data;
4569
4570         DEBUGFUNC("ixgbe_led_on_t_X550em");
4571
4572         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4573                 return IXGBE_ERR_PARAM;
4574
4575         /* To turn on the LED, set mode to ON. */
4576         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4577                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4578         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4579         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4580                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4581
4582         return IXGBE_SUCCESS;
4583 }
4584
4585 /**
4586  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4587  *  @hw: pointer to hardware structure
4588  *  @led_idx: led number to turn off
4589  **/
4590 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4591 {
4592         u16 phy_data;
4593
4594         DEBUGFUNC("ixgbe_led_off_t_X550em");
4595
4596         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4597                 return IXGBE_ERR_PARAM;
4598
4599         /* To turn on the LED, set mode to ON. */
4600         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4601                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4602         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4603         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4604                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4605
4606         return IXGBE_SUCCESS;
4607 }
4608
4609 /**
4610  *  ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware
4611  *  @hw: pointer to the HW structure
4612  *  @maj: driver version major number
4613  *  @min: driver version minor number
4614  *  @build: driver version build number
4615  *  @sub: driver version sub build number
4616  *  @len: length of driver_ver string
4617  *  @driver_ver: driver string
4618  *
4619  *  Sends driver version number to firmware through the manageability
4620  *  block.  On success return IXGBE_SUCCESS
4621  *  else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4622  *  semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4623  **/
4624 s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,
4625                               u8 build, u8 sub, u16 len, const char *driver_ver)
4626 {
4627         struct ixgbe_hic_drv_info2 fw_cmd;
4628         s32 ret_val = IXGBE_SUCCESS;
4629         int i;
4630
4631         DEBUGFUNC("ixgbe_set_fw_drv_ver_x550");
4632
4633         if ((len == 0) || (driver_ver == NULL) ||
4634            (len > sizeof(fw_cmd.driver_string)))
4635                 return IXGBE_ERR_INVALID_ARGUMENT;
4636
4637         fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4638         fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len;
4639         fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4640         fw_cmd.port_num = (u8)hw->bus.func;
4641         fw_cmd.ver_maj = maj;
4642         fw_cmd.ver_min = min;
4643         fw_cmd.ver_build = build;
4644         fw_cmd.ver_sub = sub;
4645         fw_cmd.hdr.checksum = 0;
4646         memcpy(fw_cmd.driver_string, driver_ver, len);
4647         fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4648                                 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4649
4650         for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4651                 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4652                                                        sizeof(fw_cmd),
4653                                                        IXGBE_HI_COMMAND_TIMEOUT,
4654                                                        true);
4655                 if (ret_val != IXGBE_SUCCESS)
4656                         continue;
4657
4658                 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4659                     FW_CEM_RESP_STATUS_SUCCESS)
4660                         ret_val = IXGBE_SUCCESS;
4661                 else
4662                         ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4663
4664                 break;
4665         }
4666
4667         return ret_val;
4668 }