drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42
  43 /**
  44  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  45  *  @hw: pointer to hardware structure
  46  *
  47  *  Initialize the function pointers and assign the MAC type for X550.
  48  *  Does not touch the hardware.
  49  **/
  50 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  51 {
  52         struct ixgbe_mac_info *mac = &hw->mac;
  53         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  54         s32 ret_val;
  55
  56         DEBUGFUNC("ixgbe_init_ops_X550");
  57
  58         ret_val = ixgbe_init_ops_X540(hw);
  59         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  60         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  61         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  62         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  63         mac->ops.set_source_address_pruning =
  64                         ixgbe_set_source_address_pruning_X550;
  65         mac->ops.set_ethertype_anti_spoofing =
  66                         ixgbe_set_ethertype_anti_spoofing_X550;
  67
  68         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  69         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  70         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  71         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  72         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  73         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  74         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  75         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  76         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  77
  78         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  79         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  80         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  81         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  82         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  83         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
  84                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  85                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  86         }
  87         return ret_val;
  88 }
  89
  90 /**
  91  * ixgbe_read_cs4227 - Read CS4227 register
  92  * @hw: pointer to hardware structure
  93  * @reg: register number to write
  94  * @value: pointer to receive value read
  95  *
  96  * Returns status code
  97  **/
  98 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  99 {
 100         return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 101 }
 102
 103 /**
 104  * ixgbe_write_cs4227 - Write CS4227 register
 105  * @hw: pointer to hardware structure
 106  * @reg: register number to write
 107  * @value: value to write to register
 108  *
 109  * Returns status code
 110  **/
 111 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 112 {
 113         return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 114 }
 115
 116 /**
 117  * ixgbe_read_pe - Read register from port expander
 118  * @hw: pointer to hardware structure
 119  * @reg: register number to read
 120  * @value: pointer to receive read value
 121  *
 122  * Returns status code
 123  **/
 124 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 125 {
 126         s32 status;
 127
 128         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 129         if (status != IXGBE_SUCCESS)
 130                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 131                               "port expander access failed with %d\n", status);
 132         return status;
 133 }
 134
 135 /**
 136  * ixgbe_write_pe - Write register to port expander
 137  * @hw: pointer to hardware structure
 138  * @reg: register number to write
 139  * @value: value to write
 140  *
 141  * Returns status code
 142  **/
 143 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 144 {
 145         s32 status;
 146
 147         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 148         if (status != IXGBE_SUCCESS)
 149                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 150                               "port expander access failed with %d\n", status);
 151         return status;
 152 }
 153
 154 /**
 155  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 156  * @hw: pointer to hardware structure
 157  *
 158  * This function assumes that the caller has acquired the proper semaphore.
 159  * Returns error code
 160  **/
 161 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 162 {
 163         s32 status;
 164         u32 retry;
 165         u16 value;
 166         u8 reg;
 167
 168         /* Trigger hard reset. */
 169         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 170         if (status != IXGBE_SUCCESS)
 171                 return status;
 172         reg |= IXGBE_PE_BIT1;
 173         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 174         if (status != IXGBE_SUCCESS)
 175                 return status;
 176
 177         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 178         if (status != IXGBE_SUCCESS)
 179                 return status;
 180         reg &= ~IXGBE_PE_BIT1;
 181         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 182         if (status != IXGBE_SUCCESS)
 183                 return status;
 184
 185         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 186         if (status != IXGBE_SUCCESS)
 187                 return status;
 188         reg &= ~IXGBE_PE_BIT1;
 189         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 190         if (status != IXGBE_SUCCESS)
 191                 return status;
 192
 193         usec_delay(IXGBE_CS4227_RESET_HOLD);
 194
 195         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 196         if (status != IXGBE_SUCCESS)
 197                 return status;
 198         reg |= IXGBE_PE_BIT1;
 199         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 200         if (status != IXGBE_SUCCESS)
 201                 return status;
 202
 203         /* Wait for the reset to complete. */
 204         msec_delay(IXGBE_CS4227_RESET_DELAY);
 205         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 206                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 207                                            &value);
 208                 if (status == IXGBE_SUCCESS &&
 209                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 210                         break;
 211                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 212         }
 213         if (retry == IXGBE_CS4227_RETRIES) {
 214                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 215                         "CS4227 reset did not complete.");
 216                 return IXGBE_ERR_PHY;
 217         }
 218
 219         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 220         if (status != IXGBE_SUCCESS ||
 221             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 222                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 223                         "CS4227 EEPROM did not load successfully.");
 224                 return IXGBE_ERR_PHY;
 225         }
 226
 227         return IXGBE_SUCCESS;
 228 }
 229
 230 /**
 231  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 232  * @hw: pointer to hardware structure
 233  **/
 234 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 235 {
 236         s32 status = IXGBE_SUCCESS;
 237         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 238         u16 value = 0;
 239         u8 retry;
 240
 241         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 242                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 243                 if (status != IXGBE_SUCCESS) {
 244                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 245                                 "semaphore failed with %d", status);
 246                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 247                         continue;
 248                 }
 249
 250                 /* Get status of reset flow. */
 251                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 252
 253                 if (status == IXGBE_SUCCESS &&
 254                     value == IXGBE_CS4227_RESET_COMPLETE)
 255                         goto out;
 256
 257                 if (status != IXGBE_SUCCESS ||
 258                     value != IXGBE_CS4227_RESET_PENDING)
 259                         break;
 260
 261                 /* Reset is pending. Wait and check again. */
 262                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 263                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 264         }
 265
 266         /* If still pending, assume other instance failed. */
 267         if (retry == IXGBE_CS4227_RETRIES) {
 268                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 269                 if (status != IXGBE_SUCCESS) {
 270                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 271                                       "semaphore failed with %d", status);
 272                         return;
 273                 }
 274         }
 275
 276         /* Reset the CS4227. */
 277         status = ixgbe_reset_cs4227(hw);
 278         if (status != IXGBE_SUCCESS) {
 279                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 280                         "CS4227 reset failed: %d", status);
 281                 goto out;
 282         }
 283
 284         /* Reset takes so long, temporarily release semaphore in case the
 285          * other driver instance is waiting for the reset indication.
 286          */
 287         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 288                            IXGBE_CS4227_RESET_PENDING);
 289         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 290         msec_delay(10);
 291         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 292         if (status != IXGBE_SUCCESS) {
 293                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 294                         "semaphore failed with %d", status);
 295                 return;
 296         }
 297
 298         /* Record completion for next time. */
 299         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 300                 IXGBE_CS4227_RESET_COMPLETE);
 301
 302 out:
 303         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 304         msec_delay(hw->eeprom.semaphore_delay);
 305 }
 306
 307 /**
 308  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 309  * @hw: pointer to hardware structure
 310  **/
 311 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 312 {
 313         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 314
 315         if (hw->bus.lan_id) {
 316                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 317                 esdp |= IXGBE_ESDP_SDP1_DIR;
 318         }
 319         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 320         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 321         IXGBE_WRITE_FLUSH(hw);
 322 }
 323
 324 /**
 325  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 326  * @hw: pointer to hardware structure
 327  *
 328  * Returns error code
 329  */
 330 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 331 {
 332         switch (hw->device_id) {
 333         case IXGBE_DEV_ID_X550EM_X_SFP:
 334                 /* set up for CS4227 usage */
 335                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 336                 ixgbe_setup_mux_ctl(hw);
 337                 ixgbe_check_cs4227(hw);
 338
 339                 return ixgbe_identify_module_generic(hw);
 340                 break;
 341         case IXGBE_DEV_ID_X550EM_X_KX4:
 342                 hw->phy.type = ixgbe_phy_x550em_kx4;
 343                 break;
 344         case IXGBE_DEV_ID_X550EM_X_KR:
 345                 hw->phy.type = ixgbe_phy_x550em_kr;
 346                 break;
 347         case IXGBE_DEV_ID_X550EM_X_1G_T:
 348         case IXGBE_DEV_ID_X550EM_X_10G_T:
 349                 return ixgbe_identify_phy_generic(hw);
 350         default:
 351                 break;
 352         }
 353         return IXGBE_SUCCESS;
 354 }
 355
 356 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 357                                      u32 device_type, u16 *phy_data)
 358 {
 359         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 360         return IXGBE_NOT_IMPLEMENTED;
 361 }
 362
 363 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 364                                       u32 device_type, u16 phy_data)
 365 {
 366         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 367         return IXGBE_NOT_IMPLEMENTED;
 368 }
 369
 370 /**
 371 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 372 *  @hw: pointer to hardware structure
 373 *
 374 *  Initialize the function pointers and for MAC type X550EM.
 375 *  Does not touch the hardware.
 376 **/
 377 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 378 {
 379         struct ixgbe_mac_info *mac = &hw->mac;
 380         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 381         struct ixgbe_phy_info *phy = &hw->phy;
 382         s32 ret_val;
 383
 384         DEBUGFUNC("ixgbe_init_ops_X550EM");
 385
 386         /* Similar to X550 so start there. */
 387         ret_val = ixgbe_init_ops_X550(hw);
 388
 389         /* Since this function eventually calls
 390          * ixgbe_init_ops_540 by design, we are setting
 391          * the pointers to NULL explicitly here to overwrite
 392          * the values being set in the x540 function.
 393          */
 394         /* Thermal sensor not supported in x550EM */
 395         mac->ops.get_thermal_sensor_data = NULL;
 396         mac->ops.init_thermal_sensor_thresh = NULL;
 397         mac->thermal_sensor_enabled = false;
 398
 399         /* FCOE not supported in x550EM */
 400         mac->ops.get_san_mac_addr = NULL;
 401         mac->ops.set_san_mac_addr = NULL;
 402         mac->ops.get_wwn_prefix = NULL;
 403         mac->ops.get_fcoe_boot_status = NULL;
 404
 405         /* IPsec not supported in x550EM */
 406         mac->ops.disable_sec_rx_path = NULL;
 407         mac->ops.enable_sec_rx_path = NULL;
 408
 409         /* AUTOC register is not present in x550EM. */
 410         mac->ops.prot_autoc_read = NULL;
 411         mac->ops.prot_autoc_write = NULL;
 412
 413         /* X550EM bus type is internal*/
 414         hw->bus.type = ixgbe_bus_type_internal;
 415         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 416
 417         if (hw->mac.type == ixgbe_mac_X550EM_x) {
 418                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 419                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 420                 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 421                 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 422         }
 423
 424         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 425         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 426         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 427         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 428         mac->ops.get_supported_physical_layer =
 429                                     ixgbe_get_supported_physical_layer_X550em;
 430
 431         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 432                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 433         else
 434                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 435
 436
 437         if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
 438                 mac->ops.setup_eee = NULL;
 439
 440         /* PHY */
 441         phy->ops.init = ixgbe_init_phy_ops_X550em;
 442         phy->ops.identify = ixgbe_identify_phy_x550em;
 443         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 444                 phy->ops.set_phy_power = NULL;
 445
 446
 447         /* EEPROM */
 448         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 449         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 450         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 451         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 452         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 453         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 454         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 455         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 456
 457         return ret_val;
 458 }
 459
 460 /**
 461  *  ixgbe_dmac_config_X550
 462  *  @hw: pointer to hardware structure
 463  *
 464  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 465  *  When disabling dmac, dmac enable dmac bit is cleared.
 466  **/
 467 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 468 {
 469         u32 reg, high_pri_tc;
 470
 471         DEBUGFUNC("ixgbe_dmac_config_X550");
 472
 473         /* Disable DMA coalescing before configuring */
 474         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 475         reg &= ~IXGBE_DMACR_DMAC_EN;
 476         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 477
 478         /* Disable DMA Coalescing if the watchdog timer is 0 */
 479         if (!hw->mac.dmac_config.watchdog_timer)
 480                 goto out;
 481
 482         ixgbe_dmac_config_tcs_X550(hw);
 483
 484         /* Configure DMA Coalescing Control Register */
 485         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 486
 487         /* Set the watchdog timer in units of 40.96 usec */
 488         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 489         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 490
 491         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 492         /* If fcoe is enabled, set high priority traffic class */
 493         if (hw->mac.dmac_config.fcoe_en) {
 494                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 495                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 496                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 497         }
 498         reg |= IXGBE_DMACR_EN_MNG_IND;
 499
 500         /* Enable DMA coalescing after configuration */
 501         reg |= IXGBE_DMACR_DMAC_EN;
 502         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 503
 504 out:
 505         return IXGBE_SUCCESS;
 506 }
 507
 508 /**
 509  *  ixgbe_dmac_config_tcs_X550
 510  *  @hw: pointer to hardware structure
 511  *
 512  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 513  *  be cleared before configuring.
 514  **/
 515 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 516 {
 517         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 518
 519         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 520
 521         /* Configure DMA coalescing enabled */
 522         switch (hw->mac.dmac_config.link_speed) {
 523         case IXGBE_LINK_SPEED_100_FULL:
 524                 pb_headroom = IXGBE_DMACRXT_100M;
 525                 break;
 526         case IXGBE_LINK_SPEED_1GB_FULL:
 527                 pb_headroom = IXGBE_DMACRXT_1G;
 528                 break;
 529         default:
 530                 pb_headroom = IXGBE_DMACRXT_10G;
 531                 break;
 532         }
 533
 534         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 535                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 536
 537         /* Set the per Rx packet buffer receive threshold */
 538         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 539                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 540                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 541
 542                 if (tc < hw->mac.dmac_config.num_tcs) {
 543                         /* Get Rx PB size */
 544                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 545                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 546                                 IXGBE_RXPBSIZE_SHIFT;
 547
 548                         /* Calculate receive buffer threshold in kilobytes */
 549                         if (rx_pb_size > pb_headroom)
 550                                 rx_pb_size = rx_pb_size - pb_headroom;
 551                         else
 552                                 rx_pb_size = 0;
 553
 554                         /* Minimum of MFS shall be set for DMCTH */
 555                         reg |= (rx_pb_size > maxframe_size_kb) ?
 556                                 rx_pb_size : maxframe_size_kb;
 557                 }
 558                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 559         }
 560         return IXGBE_SUCCESS;
 561 }
 562
 563 /**
 564  *  ixgbe_dmac_update_tcs_X550
 565  *  @hw: pointer to hardware structure
 566  *
 567  *  Disables dmac, updates per TC settings, and then enables dmac.
 568  **/
 569 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 570 {
 571         u32 reg;
 572
 573         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 574
 575         /* Disable DMA coalescing before configuring */
 576         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 577         reg &= ~IXGBE_DMACR_DMAC_EN;
 578         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 579
 580         ixgbe_dmac_config_tcs_X550(hw);
 581
 582         /* Enable DMA coalescing after configuration */
 583         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 584         reg |= IXGBE_DMACR_DMAC_EN;
 585         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 586
 587         return IXGBE_SUCCESS;
 588 }
 589
 590 /**
 591  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 592  *  @hw: pointer to hardware structure
 593  *
 594  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 595  *  ixgbe_hw struct in order to set up EEPROM access.
 596  **/
 597 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 598 {
 599         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 600         u32 eec;
 601         u16 eeprom_size;
 602
 603         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 604
 605         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 606                 eeprom->semaphore_delay = 10;
 607                 eeprom->type = ixgbe_flash;
 608
 609                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 610                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 611                                     IXGBE_EEC_SIZE_SHIFT);
 612                 eeprom->word_size = 1 << (eeprom_size +
 613                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 614
 615                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 616                           eeprom->type, eeprom->word_size);
 617         }
 618
 619         return IXGBE_SUCCESS;
 620 }
 621
 622 /**
 623  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 624  *  @hw: pointer to the HW structure
 625  *  @enable_eee: boolean flag to enable EEE
 626  *
 627  *  Enable/disable EEE based on enable_eee flag.
 628  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 629  *  are modified.
 630  *
 631  **/
 632 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 633 {
 634         u32 eeer;
 635         u16 autoneg_eee_reg;
 636         u32 link_reg;
 637         s32 status;
 638         u32 fuse;
 639
 640         DEBUGFUNC("ixgbe_setup_eee_X550");
 641
 642         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 643         /* Enable or disable EEE per flag */
 644         if (enable_eee) {
 645                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 646
 647                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 648                         /* Advertise EEE capability */
 649                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 650                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 651
 652                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 653                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 654                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 655
 656                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 657                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 658                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 659                         /* Not supported on first revision. */
 660                         fuse = IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0));
 661                         if (!(fuse & IXGBE_FUSES0_REV1))
 662                                 return IXGBE_SUCCESS;
 663
 664                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 665                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 666                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 667                         if (status != IXGBE_SUCCESS)
 668                                 return status;
 669
 670                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 671                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 672
 673                         /* Don't advertise FEC capability when EEE enabled. */
 674                         link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 675
 676                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 677                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 678                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 679                         if (status != IXGBE_SUCCESS)
 680                                 return status;
 681                 }
 682         } else {
 683                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 684
 685                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 686                         /* Disable advertised EEE capability */
 687                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 688                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 689
 690                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 691                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 692                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 693
 694                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 695                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 696                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 697                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 698                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 699                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 700                         if (status != IXGBE_SUCCESS)
 701                                 return status;
 702
 703                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 704                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 705
 706                         /* Advertise FEC capability when EEE is disabled. */
 707                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 708
 709                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 710                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 711                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 712                         if (status != IXGBE_SUCCESS)
 713                                 return status;
 714                 }
 715         }
 716         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 717
 718         return IXGBE_SUCCESS;
 719 }
 720
 721 /**
 722  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 723  * @hw: pointer to hardware structure
 724  * @enable: enable or disable source address pruning
 725  * @pool: Rx pool to set source address pruning for
 726  **/
 727 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 728                                            unsigned int pool)
 729 {
 730         u64 pfflp;
 731
 732         /* max rx pool is 63 */
 733         if (pool > 63)
 734                 return;
 735
 736         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 737         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 738
 739         if (enable)
 740                 pfflp |= (1ULL << pool);
 741         else
 742                 pfflp &= ~(1ULL << pool);
 743
 744         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 745         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 746 }
 747
 748 /**
 749  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 750  *  @hw: pointer to hardware structure
 751  *  @enable: enable or disable switch for Ethertype anti-spoofing
 752  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 753  *
 754  **/
 755 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 756                 bool enable, int vf)
 757 {
 758         int vf_target_reg = vf >> 3;
 759         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 760         u32 pfvfspoof;
 761
 762         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 763
 764         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 765         if (enable)
 766                 pfvfspoof |= (1 << vf_target_shift);
 767         else
 768                 pfvfspoof &= ~(1 << vf_target_shift);
 769
 770         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 771 }
 772
 773 /**
 774  * ixgbe_iosf_wait - Wait for IOSF command completion
 775  * @hw: pointer to hardware structure
 776  * @ctrl: pointer to location to receive final IOSF control value
 777  *
 778  * Returns failing status on timeout
 779  *
 780  * Note: ctrl can be NULL if the IOSF control register value is not needed
 781  **/
 782 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
 783 {
 784         u32 i, command = 0;
 785
 786         /* Check every 10 usec to see if the address cycle completed.
 787          * The SB IOSF BUSY bit will clear when the operation is
 788          * complete
 789          */
 790         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 791                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 792                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 793                         break;
 794                 usec_delay(10);
 795         }
 796         if (ctrl)
 797                 *ctrl = command;
 798         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 799                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
 800                 return IXGBE_ERR_PHY;
 801         }
 802
 803         return IXGBE_SUCCESS;
 804 }
 805
 806 /**
 807  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 808  *  device
 809  *  @hw: pointer to hardware structure
 810  *  @reg_addr: 32 bit PHY register to write
 811  *  @device_type: 3 bit device type
 812  *  @data: Data to write to the register
 813  **/
 814 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 815                             u32 device_type, u32 data)
 816 {
 817         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 818         u32 command, error;
 819         s32 ret;
 820
 821         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
 822         if (ret != IXGBE_SUCCESS)
 823                 return ret;
 824
 825         ret = ixgbe_iosf_wait(hw, NULL);
 826         if (ret != IXGBE_SUCCESS)
 827                 goto out;
 828
 829         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 830                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 831
 832         /* Write IOSF control register */
 833         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 834
 835         /* Write IOSF data register */
 836         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 837
 838         ret = ixgbe_iosf_wait(hw, &command);
 839
 840         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 841                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 842                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 843                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 844                               "Failed to write, error %x\n", error);
 845                 ret = IXGBE_ERR_PHY;
 846         }
 847
 848 out:
 849         ixgbe_release_swfw_semaphore(hw, gssr);
 850         return ret;
 851 }
 852
 853 /**
 854  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 855  *  device
 856  *  @hw: pointer to hardware structure
 857  *  @reg_addr: 32 bit PHY register to write
 858  *  @device_type: 3 bit device type
 859  *  @phy_data: Pointer to read data from the register
 860  **/
 861 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 862                            u32 device_type, u32 *data)
 863 {
 864         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 865         u32 command, error;
 866         s32 ret;
 867
 868         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
 869         if (ret != IXGBE_SUCCESS)
 870                 return ret;
 871
 872         ret = ixgbe_iosf_wait(hw, NULL);
 873         if (ret != IXGBE_SUCCESS)
 874                 goto out;
 875
 876         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 877                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 878
 879         /* Write IOSF control register */
 880         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 881
 882         ret = ixgbe_iosf_wait(hw, &command);
 883
 884         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 885                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 886                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 887                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 888                                 "Failed to read, error %x\n", error);
 889                 ret = IXGBE_ERR_PHY;
 890         }
 891
 892         if (ret == IXGBE_SUCCESS)
 893                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 894
 895 out:
 896         ixgbe_release_swfw_semaphore(hw, gssr);
 897         return ret;
 898 }
 899
 900 /**
 901  *  ixgbe_disable_mdd_X550
 902  *  @hw: pointer to hardware structure
 903  *
 904  *  Disable malicious driver detection
 905  **/
 906 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
 907 {
 908         u32 reg;
 909
 910         DEBUGFUNC("ixgbe_disable_mdd_X550");
 911
 912         /* Disable MDD for TX DMA and interrupt */
 913         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 914         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 915         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 916
 917         /* Disable MDD for RX and interrupt */
 918         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 919         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 920         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 921 }
 922
 923 /**
 924  *  ixgbe_enable_mdd_X550
 925  *  @hw: pointer to hardware structure
 926  *
 927  *  Enable malicious driver detection
 928  **/
 929 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
 930 {
 931         u32 reg;
 932
 933         DEBUGFUNC("ixgbe_enable_mdd_X550");
 934
 935         /* Enable MDD for TX DMA and interrupt */
 936         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 937         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 938         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 939
 940         /* Enable MDD for RX and interrupt */
 941         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 942         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 943         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 944 }
 945
 946 /**
 947  *  ixgbe_restore_mdd_vf_X550
 948  *  @hw: pointer to hardware structure
 949  *  @vf: vf index
 950  *
 951  *  Restore VF that was disabled during malicious driver detection event
 952  **/
 953 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
 954 {
 955         u32 idx, reg, num_qs, start_q, bitmask;
 956
 957         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
 958
 959         /* Map VF to queues */
 960         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 961         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 962         case IXGBE_MRQC_VMDQRT8TCEN:
 963                 num_qs = 8;  /* 16 VFs / pools */
 964                 bitmask = 0x000000FF;
 965                 break;
 966         case IXGBE_MRQC_VMDQRSS32EN:
 967         case IXGBE_MRQC_VMDQRT4TCEN:
 968                 num_qs = 4;  /* 32 VFs / pools */
 969                 bitmask = 0x0000000F;
 970                 break;
 971         default:            /* 64 VFs / pools */
 972                 num_qs = 2;
 973                 bitmask = 0x00000003;
 974                 break;
 975         }
 976         start_q = vf * num_qs;
 977
 978         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
 979         idx = start_q / 32;
 980         reg = 0;
 981         reg |= (bitmask << (start_q % 32));
 982         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
 983         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
 984 }
 985
 986 /**
 987  *  ixgbe_mdd_event_X550
 988  *  @hw: pointer to hardware structure
 989  *  @vf_bitmap: vf bitmap of malicious vfs
 990  *
 991  *  Handle malicious driver detection event.
 992  **/
 993 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
 994 {
 995         u32 wqbr;
 996         u32 i, j, reg, q, shift, vf, idx;
 997
 998         DEBUGFUNC("ixgbe_mdd_event_X550");
 999
1000         /* figure out pool size for mapping to vf's */
1001         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1002         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1003         case IXGBE_MRQC_VMDQRT8TCEN:
1004                 shift = 3;  /* 16 VFs / pools */
1005                 break;
1006         case IXGBE_MRQC_VMDQRSS32EN:
1007         case IXGBE_MRQC_VMDQRT4TCEN:
1008                 shift = 2;  /* 32 VFs / pools */
1009                 break;
1010         default:
1011                 shift = 1;  /* 64 VFs / pools */
1012                 break;
1013         }
1014
1015         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1016         for (i = 0; i < 4; i++) {
1017                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1018                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1019
1020                 if (!wqbr)
1021                         continue;
1022
1023                 /* Get malicious queue */
1024                 for (j = 0; j < 32 && wqbr; j++) {
1025
1026                         if (!(wqbr & (1 << j)))
1027                                 continue;
1028
1029                         /* Get queue from bitmask */
1030                         q = j + (i * 32);
1031
1032                         /* Map queue to vf */
1033                         vf = (q >> shift);
1034
1035                         /* Set vf bit in vf_bitmap */
1036                         idx = vf / 32;
1037                         vf_bitmap[idx] |= (1 << (vf % 32));
1038                         wqbr &= ~(1 << j);
1039                 }
1040         }
1041 }
1042
1043 /**
1044  *  ixgbe_get_media_type_X550em - Get media type
1045  *  @hw: pointer to hardware structure
1046  *
1047  *  Returns the media type (fiber, copper, backplane)
1048  */
1049 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1050 {
1051         enum ixgbe_media_type media_type;
1052
1053         DEBUGFUNC("ixgbe_get_media_type_X550em");
1054
1055         /* Detect if there is a copper PHY attached. */
1056         switch (hw->device_id) {
1057         case IXGBE_DEV_ID_X550EM_X_KR:
1058         case IXGBE_DEV_ID_X550EM_X_KX4:
1059                 media_type = ixgbe_media_type_backplane;
1060                 break;
1061         case IXGBE_DEV_ID_X550EM_X_SFP:
1062                 media_type = ixgbe_media_type_fiber;
1063                 break;
1064         case IXGBE_DEV_ID_X550EM_X_1G_T:
1065         case IXGBE_DEV_ID_X550EM_X_10G_T:
1066                 media_type = ixgbe_media_type_copper;
1067                 break;
1068         default:
1069                 media_type = ixgbe_media_type_unknown;
1070                 break;
1071         }
1072         return media_type;
1073 }
1074
1075 /**
1076  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1077  *  @hw: pointer to hardware structure
1078  *  @linear: true if SFP module is linear
1079  */
1080 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1081 {
1082         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1083
1084         switch (hw->phy.sfp_type) {
1085         case ixgbe_sfp_type_not_present:
1086                 return IXGBE_ERR_SFP_NOT_PRESENT;
1087         case ixgbe_sfp_type_da_cu_core0:
1088         case ixgbe_sfp_type_da_cu_core1:
1089                 *linear = true;
1090                 break;
1091         case ixgbe_sfp_type_srlr_core0:
1092         case ixgbe_sfp_type_srlr_core1:
1093         case ixgbe_sfp_type_da_act_lmt_core0:
1094         case ixgbe_sfp_type_da_act_lmt_core1:
1095         case ixgbe_sfp_type_1g_sx_core0:
1096         case ixgbe_sfp_type_1g_sx_core1:
1097         case ixgbe_sfp_type_1g_lx_core0:
1098         case ixgbe_sfp_type_1g_lx_core1:
1099                 *linear = false;
1100                 break;
1101         case ixgbe_sfp_type_unknown:
1102         case ixgbe_sfp_type_1g_cu_core0:
1103         case ixgbe_sfp_type_1g_cu_core1:
1104         default:
1105                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1106         }
1107
1108         return IXGBE_SUCCESS;
1109 }
1110
1111 /**
1112  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1113  *  @hw: pointer to hardware structure
1114  *
1115  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1116  **/
1117 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1118 {
1119         s32 status;
1120         bool linear;
1121
1122         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1123
1124         status = ixgbe_identify_module_generic(hw);
1125
1126         if (status != IXGBE_SUCCESS)
1127                 return status;
1128
1129         /* Check if SFP module is supported */
1130         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1131
1132         return status;
1133 }
1134
1135 /**
1136  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1137  *  @hw: pointer to hardware structure
1138  */
1139 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1140 {
1141         s32 status;
1142         bool linear;
1143
1144         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1145
1146         /* Check if SFP module is supported */
1147         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1148
1149         if (status != IXGBE_SUCCESS)
1150                 return status;
1151
1152         ixgbe_init_mac_link_ops_X550em(hw);
1153         hw->phy.ops.reset = NULL;
1154
1155         return IXGBE_SUCCESS;
1156 }
1157
1158 /**
1159  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1160  *  @hw: pointer to hardware structure
1161  */
1162 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1163 {
1164         struct ixgbe_mac_info *mac = &hw->mac;
1165
1166         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1167
1168          switch (hw->mac.ops.get_media_type(hw)) {
1169          case ixgbe_media_type_fiber:
1170                 /* CS4227 does not support autoneg, so disable the laser control
1171                  * functions for SFP+ fiber
1172                  */
1173                 mac->ops.disable_tx_laser = NULL;
1174                 mac->ops.enable_tx_laser = NULL;
1175                 mac->ops.flap_tx_laser = NULL;
1176                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1177                 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1178                 mac->ops.set_rate_select_speed =
1179                                         ixgbe_set_soft_rate_select_speed;
1180                 break;
1181         case ixgbe_media_type_copper:
1182                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1183                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1184                 break;
1185         default:
1186                 break;
1187          }
1188 }
1189
1190 /**
1191  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1192  *  @hw: pointer to hardware structure
1193  *  @speed: pointer to link speed
1194  *  @autoneg: true when autoneg or autotry is enabled
1195  */
1196 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1197                                        ixgbe_link_speed *speed,
1198                                        bool *autoneg)
1199 {
1200         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1201
1202         /* SFP */
1203         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1204
1205                 /* CS4227 SFP must not enable auto-negotiation */
1206                 *autoneg = false;
1207
1208                 /* Check if 1G SFP module. */
1209                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1210                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1211                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1212                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1213                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1214                         return IXGBE_SUCCESS;
1215                 }
1216
1217                 /* Link capabilities are based on SFP */
1218                 if (hw->phy.multispeed_fiber)
1219                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1220                                  IXGBE_LINK_SPEED_1GB_FULL;
1221                 else
1222                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1223         } else {
1224                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1225                          IXGBE_LINK_SPEED_1GB_FULL;
1226                 *autoneg = true;
1227         }
1228
1229         return IXGBE_SUCCESS;
1230 }
1231
1232 /**
1233  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1234  * @hw: pointer to hardware structure
1235  * @lsc: pointer to boolean flag which indicates whether external Base T
1236  *       PHY interrupt is lsc
1237  *
1238  * Determime if external Base T PHY interrupt cause is high temperature
1239  * failure alarm or link status change.
1240  *
1241  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1242  * failure alarm, else return PHY access status.
1243  */
1244 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1245 {
1246         u32 status;
1247         u16 reg;
1248
1249         *lsc = false;
1250
1251         /* Vendor alarm triggered */
1252         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1253                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1254                                       &reg);
1255
1256         if (status != IXGBE_SUCCESS ||
1257             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1258                 return status;
1259
1260         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1261         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1262                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1263                                       &reg);
1264
1265         if (status != IXGBE_SUCCESS ||
1266             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1267             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1268                 return status;
1269
1270         /* High temperature failure alarm triggered */
1271         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1272                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1273                                       &reg);
1274
1275         if (status != IXGBE_SUCCESS)
1276                 return status;
1277
1278         /* If high temperature failure, then return over temp error and exit */
1279         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1280                 /* power down the PHY in case the PHY FW didn't already */
1281                 ixgbe_set_copper_phy_power(hw, false);
1282                 return IXGBE_ERR_OVERTEMP;
1283         }
1284
1285         /* Vendor alarm 2 triggered */
1286         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1287                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1288
1289         if (status != IXGBE_SUCCESS ||
1290             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1291                 return status;
1292
1293         /* link connect/disconnect event occurred */
1294         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1295                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1296
1297         if (status != IXGBE_SUCCESS)
1298                 return status;
1299
1300         /* Indicate LSC */
1301         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1302                 *lsc = true;
1303
1304         return IXGBE_SUCCESS;
1305 }
1306
1307 /**
1308  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1309  * @hw: pointer to hardware structure
1310  *
1311  * Enable link status change and temperature failure alarm for the external
1312  * Base T PHY
1313  *
1314  * Returns PHY access status
1315  */
1316 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1317 {
1318         u32 status;
1319         u16 reg;
1320         bool lsc;
1321
1322         /* Clear interrupt flags */
1323         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1324
1325         /* Enable link status change alarm */
1326         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1327                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1328
1329         if (status != IXGBE_SUCCESS)
1330                 return status;
1331
1332         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1333
1334         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1335                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1336
1337         if (status != IXGBE_SUCCESS)
1338                 return status;
1339
1340         /* Enables high temperature failure alarm */
1341         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1342                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1343                                       &reg);
1344
1345         if (status != IXGBE_SUCCESS)
1346                 return status;
1347
1348         reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;
1349
1350         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1351                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1352                                        reg);
1353
1354         if (status != IXGBE_SUCCESS)
1355                 return status;
1356
1357         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1358         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1359                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1360                                       &reg);
1361
1362         if (status != IXGBE_SUCCESS)
1363                 return status;
1364
1365         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1366                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1367
1368         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1369                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1370                                        reg);
1371
1372         if (status != IXGBE_SUCCESS)
1373                 return status;
1374
1375         /* Enable chip-wide vendor alarm */
1376         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1377                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1378                                       &reg);
1379
1380         if (status != IXGBE_SUCCESS)
1381                 return status;
1382
1383         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1384
1385         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1386                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1387                                        reg);
1388
1389         return status;
1390 }
1391
1392 /**
1393  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1394  *  @hw: pointer to hardware structure
1395  *  @speed: link speed
1396  *
1397  *  Configures the integrated KR PHY.
1398  **/
1399 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1400                                        ixgbe_link_speed speed)
1401 {
1402         s32 status;
1403         u32 reg_val;
1404
1405         status = ixgbe_read_iosf_sb_reg_x550(hw,
1406                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1407                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1408         if (status)
1409                 return status;
1410
1411         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1412         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1413                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1414
1415         /* Advertise 10G support. */
1416         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1417                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1418
1419         /* Advertise 1G support. */
1420         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1421                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1422
1423         /* Restart auto-negotiation. */
1424         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1425         status = ixgbe_write_iosf_sb_reg_x550(hw,
1426                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1427                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1428
1429         return status;
1430 }
1431
1432 /**
1433  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1434  *  @hw: pointer to hardware structure
1435  *
1436  *  Initialize any function pointers that were not able to be
1437  *  set during init_shared_code because the PHY/SFP type was
1438  *  not known.  Perform the SFP init if necessary.
1439  */
1440 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1441 {
1442         struct ixgbe_phy_info *phy = &hw->phy;
1443         ixgbe_link_speed speed;
1444         s32 ret_val;
1445
1446         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1447
1448         hw->mac.ops.set_lan_id(hw);
1449
1450         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1451                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1452                 ixgbe_setup_mux_ctl(hw);
1453
1454                 /* Save NW management interface connected on board. This is used
1455                  * to determine internal PHY mode.
1456                  */
1457                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1458                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
1459         }
1460
1461         /* Identify the PHY or SFP module */
1462         ret_val = phy->ops.identify(hw);
1463         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1464                 return ret_val;
1465
1466         /* Setup function pointers based on detected hardware */
1467         ixgbe_init_mac_link_ops_X550em(hw);
1468         if (phy->sfp_type != ixgbe_sfp_type_unknown)
1469                 phy->ops.reset = NULL;
1470
1471         /* Set functions pointers based on phy type */
1472         switch (hw->phy.type) {
1473         case ixgbe_phy_x550em_kx4:
1474                 phy->ops.setup_link = NULL;
1475                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1476                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1477                 break;
1478         case ixgbe_phy_x550em_kr:
1479                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1480                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1481                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1482                 break;
1483         case ixgbe_phy_x550em_ext_t:
1484                 /* Save NW management interface connected on board. This is used
1485                  * to determine internal PHY mode
1486                  */
1487                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1488
1489                 /* If internal link mode is XFI, then setup iXFI internal link,
1490                  * else setup KR now.
1491                  */
1492                 if (!(phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1493                         phy->ops.setup_internal_link =
1494                                               ixgbe_setup_internal_phy_t_x550em;
1495                 } else {
1496                         speed = IXGBE_LINK_SPEED_10GB_FULL |
1497                                 IXGBE_LINK_SPEED_1GB_FULL;
1498                         ret_val = ixgbe_setup_kr_speed_x550em(hw, speed);
1499                 }
1500
1501                 /* setup SW LPLU only for first revision */
1502                 if (!(IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw,
1503                                                        IXGBE_FUSES0_GROUP(0))))
1504                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1505
1506                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1507                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1508                 break;
1509         default:
1510                 break;
1511         }
1512         return ret_val;
1513 }
1514
1515 /**
1516  *  ixgbe_reset_hw_X550em - Perform hardware reset
1517  *  @hw: pointer to hardware structure
1518  *
1519  *  Resets the hardware by resetting the transmit and receive units, masks
1520  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1521  *  reset.
1522  */
1523 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1524 {
1525         ixgbe_link_speed link_speed;
1526         s32 status;
1527         u32 ctrl = 0;
1528         u32 i;
1529         u32 hlreg0;
1530         bool link_up = false;
1531
1532         DEBUGFUNC("ixgbe_reset_hw_X550em");
1533
1534         /* Call adapter stop to disable Tx/Rx and clear interrupts */
1535         status = hw->mac.ops.stop_adapter(hw);
1536         if (status != IXGBE_SUCCESS)
1537                 return status;
1538
1539         /* flush pending Tx transactions */
1540         ixgbe_clear_tx_pending(hw);
1541
1542         /* PHY ops must be identified and initialized prior to reset */
1543
1544         /* Identify PHY and related function pointers */
1545         status = hw->phy.ops.init(hw);
1546
1547         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1548                 return status;
1549
1550         /* start the external PHY */
1551         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1552                 status = ixgbe_init_ext_t_x550em(hw);
1553                 if (status)
1554                         return status;
1555         }
1556
1557         /* Setup SFP module if there is one present. */
1558         if (hw->phy.sfp_setup_needed) {
1559                 status = hw->mac.ops.setup_sfp(hw);
1560                 hw->phy.sfp_setup_needed = false;
1561         }
1562
1563         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1564                 return status;
1565
1566         /* Reset PHY */
1567         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1568                 hw->phy.ops.reset(hw);
1569
1570 mac_reset_top:
1571         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1572          * If link reset is used when link is up, it might reset the PHY when
1573          * mng is using it.  If link is down or the flag to force full link
1574          * reset is set, then perform link reset.
1575          */
1576         ctrl = IXGBE_CTRL_LNK_RST;
1577         if (!hw->force_full_reset) {
1578                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1579                 if (link_up)
1580                         ctrl = IXGBE_CTRL_RST;
1581         }
1582
1583         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1584         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1585         IXGBE_WRITE_FLUSH(hw);
1586
1587         /* Poll for reset bit to self-clear meaning reset is complete */
1588         for (i = 0; i < 10; i++) {
1589                 usec_delay(1);
1590                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1591                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1592                         break;
1593         }
1594
1595         if (ctrl & IXGBE_CTRL_RST_MASK) {
1596                 status = IXGBE_ERR_RESET_FAILED;
1597                 DEBUGOUT("Reset polling failed to complete.\n");
1598         }
1599
1600         msec_delay(50);
1601
1602         /* Double resets are required for recovery from certain error
1603          * conditions.  Between resets, it is necessary to stall to
1604          * allow time for any pending HW events to complete.
1605          */
1606         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1607                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1608                 goto mac_reset_top;
1609         }
1610
1611         /* Store the permanent mac address */
1612         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1613
1614         /* Store MAC address from RAR0, clear receive address registers, and
1615          * clear the multicast table.  Also reset num_rar_entries to 128,
1616          * since we modify this value when programming the SAN MAC address.
1617          */
1618         hw->mac.num_rar_entries = 128;
1619         hw->mac.ops.init_rx_addrs(hw);
1620
1621         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
1622                 /* Config MDIO clock speed. */
1623                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1624                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
1625                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1626         }
1627
1628         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1629                 ixgbe_setup_mux_ctl(hw);
1630
1631         return status;
1632 }
1633
1634 /**
1635  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1636  * @hw: pointer to hardware structure
1637  */
1638 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1639 {
1640         u32 status;
1641         u16 reg;
1642
1643         status = hw->phy.ops.read_reg(hw,
1644                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1645                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1646                                       &reg);
1647
1648         if (status != IXGBE_SUCCESS)
1649                 return status;
1650
1651         /* If PHY FW reset completed bit is set then this is the first
1652          * SW instance after a power on so the PHY FW must be un-stalled.
1653          */
1654         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1655                 status = hw->phy.ops.read_reg(hw,
1656                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1657                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1658                                         &reg);
1659
1660                 if (status != IXGBE_SUCCESS)
1661                         return status;
1662
1663                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1664
1665                 status = hw->phy.ops.write_reg(hw,
1666                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1667                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1668                                         reg);
1669
1670                 if (status != IXGBE_SUCCESS)
1671                         return status;
1672         }
1673
1674         return status;
1675 }
1676
1677 /**
1678  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1679  *  @hw: pointer to hardware structure
1680  *
1681  *  Configures the integrated KR PHY.
1682  **/
1683 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1684 {
1685         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
1686 }
1687
1688 /**
1689  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
1690  *  @hw: pointer to hardware structure
1691  *
1692  *  Configure the external PHY and the integrated KR PHY for SFP support.
1693  **/
1694 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1695                                     ixgbe_link_speed speed,
1696                                     bool autoneg_wait_to_complete)
1697 {
1698         s32 ret_val;
1699         u16 reg_slice, reg_val;
1700         bool setup_linear = false;
1701         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1702
1703         /* Check if SFP module is supported and linear */
1704         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1705
1706         /* If no SFP module present, then return success. Return success since
1707          * there is no reason to configure CS4227 and SFP not present error is
1708          * not excepted in the setup MAC link flow.
1709          */
1710         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1711                 return IXGBE_SUCCESS;
1712
1713         if (ret_val != IXGBE_SUCCESS)
1714                 return ret_val;
1715
1716         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1717                 /* Configure CS4227 LINE side to 10G SR. */
1718                 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
1719                             (hw->bus.lan_id << 12);
1720                 reg_val = IXGBE_CS4227_SPEED_10G;
1721                 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1722                                                    reg_val);
1723
1724                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
1725                             (hw->bus.lan_id << 12);
1726                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1727                 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1728                                                    reg_val);
1729
1730                 /* Configure CS4227 for HOST connection rate then type. */
1731                 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
1732                             (hw->bus.lan_id << 12);
1733                 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
1734                 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
1735                 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1736                                                    reg_val);
1737
1738                 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
1739                             (hw->bus.lan_id << 12);
1740                 if (setup_linear)
1741                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1742                 else
1743                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1744                 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1745                                                    reg_val);
1746
1747                 /* Setup XFI internal link. */
1748                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
1749         } else {
1750                 /* Configure internal PHY for KR/KX. */
1751                 ixgbe_setup_kr_speed_x550em(hw, speed);
1752
1753                 /* Configure CS4227 LINE side to proper mode. */
1754                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
1755                             (hw->bus.lan_id << 12);
1756                 if (setup_linear)
1757                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1758                 else
1759                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1760                 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1761                                                    reg_val);
1762         }
1763         return ret_val;
1764 }
1765
1766 /**
1767  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1768  *  @hw: pointer to hardware structure
1769  *  @speed: the link speed to force
1770  *
1771  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1772  *  internal and external PHY at a specific speed, without autonegotiation.
1773  **/
1774 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1775 {
1776         s32 status;
1777         u32 reg_val;
1778
1779         /* Disable AN and force speed to 10G Serial. */
1780         status = ixgbe_read_iosf_sb_reg_x550(hw,
1781                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1782                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1783         if (status != IXGBE_SUCCESS)
1784                 return status;
1785
1786         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1787         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1788
1789         /* Select forced link speed for internal PHY. */
1790         switch (*speed) {
1791         case IXGBE_LINK_SPEED_10GB_FULL:
1792                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1793                 break;
1794         case IXGBE_LINK_SPEED_1GB_FULL:
1795                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1796                 break;
1797         default:
1798                 /* Other link speeds are not supported by internal KR PHY. */
1799                 return IXGBE_ERR_LINK_SETUP;
1800         }
1801
1802         status = ixgbe_write_iosf_sb_reg_x550(hw,
1803                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1804                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1805         if (status != IXGBE_SUCCESS)
1806                 return status;
1807
1808         /* Disable training protocol FSM. */
1809         status = ixgbe_read_iosf_sb_reg_x550(hw,
1810                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1811                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1812         if (status != IXGBE_SUCCESS)
1813                 return status;
1814         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1815         status = ixgbe_write_iosf_sb_reg_x550(hw,
1816                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1817                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1818         if (status != IXGBE_SUCCESS)
1819                 return status;
1820
1821         /* Disable Flex from training TXFFE. */
1822         status = ixgbe_read_iosf_sb_reg_x550(hw,
1823                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1824                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1825         if (status != IXGBE_SUCCESS)
1826                 return status;
1827         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1828         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1829         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1830         status = ixgbe_write_iosf_sb_reg_x550(hw,
1831                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1832                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1833         if (status != IXGBE_SUCCESS)
1834                 return status;
1835         status = ixgbe_read_iosf_sb_reg_x550(hw,
1836                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1837                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1838         if (status != IXGBE_SUCCESS)
1839                 return status;
1840         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1841         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1842         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1843         status = ixgbe_write_iosf_sb_reg_x550(hw,
1844                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1845                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1846         if (status != IXGBE_SUCCESS)
1847                 return status;
1848
1849         /* Enable override for coefficients. */
1850         status = ixgbe_read_iosf_sb_reg_x550(hw,
1851                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1852                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1853         if (status != IXGBE_SUCCESS)
1854                 return status;
1855         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1856         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1857         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1858         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1859         status = ixgbe_write_iosf_sb_reg_x550(hw,
1860                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1861                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1862         if (status != IXGBE_SUCCESS)
1863                 return status;
1864
1865         /* Toggle port SW reset by AN reset. */
1866         status = ixgbe_read_iosf_sb_reg_x550(hw,
1867                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1868                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1869         if (status != IXGBE_SUCCESS)
1870                 return status;
1871         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1872         status = ixgbe_write_iosf_sb_reg_x550(hw,
1873                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1874                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1875
1876         return status;
1877 }
1878
1879 /**
1880  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
1881  * @hw: address of hardware structure
1882  * @link_up: address of boolean to indicate link status
1883  *
1884  * Returns error code if unable to get link status.
1885  */
1886 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
1887 {
1888         u32 ret;
1889         u16 autoneg_status;
1890
1891         *link_up = false;
1892
1893         /* read this twice back to back to indicate current status */
1894         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1895                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1896                                    &autoneg_status);
1897         if (ret != IXGBE_SUCCESS)
1898                 return ret;
1899
1900         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1901                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1902                                    &autoneg_status);
1903         if (ret != IXGBE_SUCCESS)
1904                 return ret;
1905
1906         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
1907
1908         return IXGBE_SUCCESS;
1909 }
1910
1911 /**
1912  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1913  * @hw: point to hardware structure
1914  *
1915  * Configures the link between the integrated KR PHY and the external X557 PHY
1916  * The driver will call this function when it gets a link status change
1917  * interrupt from the X557 PHY. This function configures the link speed
1918  * between the PHYs to match the link speed of the BASE-T link.
1919  *
1920  * A return of a non-zero value indicates an error, and the base driver should
1921  * not report link up.
1922  */
1923 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
1924 {
1925         ixgbe_link_speed force_speed;
1926         bool link_up;
1927         u32 status;
1928         u16 speed;
1929
1930         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1931                 return IXGBE_ERR_CONFIG;
1932
1933         /* If link is not up, then there is no setup necessary so return  */
1934         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1935         if (status != IXGBE_SUCCESS)
1936                 return status;
1937
1938         if (!link_up)
1939                 return IXGBE_SUCCESS;
1940
1941         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1942                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1943                                       &speed);
1944         if (status != IXGBE_SUCCESS)
1945                 return status;
1946
1947         /* If link is not still up, then no setup is necessary so return */
1948         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1949         if (status != IXGBE_SUCCESS)
1950                 return status;
1951         if (!link_up)
1952                 return IXGBE_SUCCESS;
1953
1954         /* clear everything but the speed and duplex bits */
1955         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1956
1957         switch (speed) {
1958         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1959                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1960                 break;
1961         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1962                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1963                 break;
1964         default:
1965                 /* Internal PHY does not support anything else */
1966                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1967         }
1968
1969         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1970 }
1971
1972 /**
1973  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1974  *  @hw: pointer to hardware structure
1975  *
1976  *  Configures the integrated KR PHY to use internal loopback mode.
1977  **/
1978 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1979 {
1980         s32 status;
1981         u32 reg_val;
1982
1983         /* Disable AN and force speed to 10G Serial. */
1984         status = ixgbe_read_iosf_sb_reg_x550(hw,
1985                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1986                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1987         if (status != IXGBE_SUCCESS)
1988                 return status;
1989         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1990         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1991         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1992         status = ixgbe_write_iosf_sb_reg_x550(hw,
1993                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1994                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1995         if (status != IXGBE_SUCCESS)
1996                 return status;
1997
1998         /* Set near-end loopback clocks. */
1999         status = ixgbe_read_iosf_sb_reg_x550(hw,
2000                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2001                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2002         if (status != IXGBE_SUCCESS)
2003                 return status;
2004         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2005         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2006         status = ixgbe_write_iosf_sb_reg_x550(hw,
2007                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2008                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2009         if (status != IXGBE_SUCCESS)
2010                 return status;
2011
2012         /* Set loopback enable. */
2013         status = ixgbe_read_iosf_sb_reg_x550(hw,
2014                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2015                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2016         if (status != IXGBE_SUCCESS)
2017                 return status;
2018         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2019         status = ixgbe_write_iosf_sb_reg_x550(hw,
2020                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2021                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2022         if (status != IXGBE_SUCCESS)
2023                 return status;
2024
2025         /* Training bypass. */
2026         status = ixgbe_read_iosf_sb_reg_x550(hw,
2027                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2028                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2029         if (status != IXGBE_SUCCESS)
2030                 return status;
2031         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2032         status = ixgbe_write_iosf_sb_reg_x550(hw,
2033                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2034                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2035
2036         return status;
2037 }
2038
2039 /**
2040  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2041  *  assuming that the semaphore is already obtained.
2042  *  @hw: pointer to hardware structure
2043  *  @offset: offset of  word in the EEPROM to read
2044  *  @data: word read from the EEPROM
2045  *
2046  *  Reads a 16 bit word from the EEPROM using the hostif.
2047  **/
2048 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2049                                    u16 *data)
2050 {
2051         s32 status;
2052         struct ixgbe_hic_read_shadow_ram buffer;
2053
2054         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2055         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2056         buffer.hdr.req.buf_lenh = 0;
2057         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2058         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2059
2060         /* convert offset from words to bytes */
2061         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2062         /* one word */
2063         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2064
2065         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2066                                               sizeof(buffer),
2067                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2068
2069         if (status)
2070                 return status;
2071
2072         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2073                                           FW_NVM_DATA_OFFSET);
2074
2075         return 0;
2076 }
2077
2078 /**
2079  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2080  *  @hw: pointer to hardware structure
2081  *  @offset: offset of  word in the EEPROM to read
2082  *  @data: word read from the EEPROM
2083  *
2084  *  Reads a 16 bit word from the EEPROM using the hostif.
2085  **/
2086 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2087                               u16 *data)
2088 {
2089         s32 status = IXGBE_SUCCESS;
2090
2091         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2092
2093         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2094             IXGBE_SUCCESS) {
2095                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2096                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2097         } else {
2098                 status = IXGBE_ERR_SWFW_SYNC;
2099         }
2100
2101         return status;
2102 }
2103
2104 /**
2105  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2106  *  @hw: pointer to hardware structure
2107  *  @offset: offset of  word in the EEPROM to read
2108  *  @words: number of words
2109  *  @data: word(s) read from the EEPROM
2110  *
2111  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
2112  **/
2113 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2114                                      u16 offset, u16 words, u16 *data)
2115 {
2116         struct ixgbe_hic_read_shadow_ram buffer;
2117         u32 current_word = 0;
2118         u16 words_to_read;
2119         s32 status;
2120         u32 i;
2121
2122         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2123
2124         /* Take semaphore for the entire operation. */
2125         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2126         if (status) {
2127                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2128                 return status;
2129         }
2130         while (words) {
2131                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2132                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2133                 else
2134                         words_to_read = words;
2135
2136                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2137                 buffer.hdr.req.buf_lenh = 0;
2138                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2139                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2140
2141                 /* convert offset from words to bytes */
2142                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2143                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2144
2145                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2146                                                       sizeof(buffer),
2147                                                       IXGBE_HI_COMMAND_TIMEOUT,
2148                                                       false);
2149
2150                 if (status) {
2151                         DEBUGOUT("Host interface command failed\n");
2152                         goto out;
2153                 }
2154
2155                 for (i = 0; i < words_to_read; i++) {
2156                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
2157                                   2 * i;
2158                         u32 value = IXGBE_READ_REG(hw, reg);
2159
2160                         data[current_word] = (u16)(value & 0xffff);
2161                         current_word++;
2162                         i++;
2163                         if (i < words_to_read) {
2164                                 value >>= 16;
2165                                 data[current_word] = (u16)(value & 0xffff);
2166                                 current_word++;
2167                         }
2168                 }
2169                 words -= words_to_read;
2170         }
2171
2172 out:
2173         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2174         return status;
2175 }
2176
2177 /**
2178  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2179  *  @hw: pointer to hardware structure
2180  *  @offset: offset of  word in the EEPROM to write
2181  *  @data: word write to the EEPROM
2182  *
2183  *  Write a 16 bit word to the EEPROM using the hostif.
2184  **/
2185 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2186                                     u16 data)
2187 {
2188         s32 status;
2189         struct ixgbe_hic_write_shadow_ram buffer;
2190
2191         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
2192
2193         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
2194         buffer.hdr.req.buf_lenh = 0;
2195         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
2196         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2197
2198          /* one word */
2199         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2200         buffer.data = data;
2201         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2202
2203         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2204                                               sizeof(buffer),
2205                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2206
2207         return status;
2208 }
2209
2210 /**
2211  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2212  *  @hw: pointer to hardware structure
2213  *  @offset: offset of  word in the EEPROM to write
2214  *  @data: word write to the EEPROM
2215  *
2216  *  Write a 16 bit word to the EEPROM using the hostif.
2217  **/
2218 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2219                                u16 data)
2220 {
2221         s32 status = IXGBE_SUCCESS;
2222
2223         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2224
2225         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2226             IXGBE_SUCCESS) {
2227                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2228                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2229         } else {
2230                 DEBUGOUT("write ee hostif failed to get semaphore");
2231                 status = IXGBE_ERR_SWFW_SYNC;
2232         }
2233
2234         return status;
2235 }
2236
2237 /**
2238  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2239  *  @hw: pointer to hardware structure
2240  *  @offset: offset of  word in the EEPROM to write
2241  *  @words: number of words
2242  *  @data: word(s) write to the EEPROM
2243  *
2244  *  Write a 16 bit word(s) to the EEPROM using the hostif.
2245  **/
2246 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2247                                       u16 offset, u16 words, u16 *data)
2248 {
2249         s32 status = IXGBE_SUCCESS;
2250         u32 i = 0;
2251
2252         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2253
2254         /* Take semaphore for the entire operation. */
2255         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2256         if (status != IXGBE_SUCCESS) {
2257                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2258                 goto out;
2259         }
2260
2261         for (i = 0; i < words; i++) {
2262                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2263                                                          data[i]);
2264
2265                 if (status != IXGBE_SUCCESS) {
2266                         DEBUGOUT("Eeprom buffered write failed\n");
2267                         break;
2268                 }
2269         }
2270
2271         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2272 out:
2273
2274         return status;
2275 }
2276
2277 /**
2278  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2279  * @hw: pointer to hardware structure
2280  * @ptr: pointer offset in eeprom
2281  * @size: size of section pointed by ptr, if 0 first word will be used as size
2282  * @csum: address of checksum to update
2283  *
2284  * Returns error status for any failure
2285  */
2286 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2287                                    u16 size, u16 *csum, u16 *buffer,
2288                                    u32 buffer_size)
2289 {
2290         u16 buf[256];
2291         s32 status;
2292         u16 length, bufsz, i, start;
2293         u16 *local_buffer;
2294
2295         bufsz = sizeof(buf) / sizeof(buf[0]);
2296
2297         /* Read a chunk at the pointer location */
2298         if (!buffer) {
2299                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2300                 if (status) {
2301                         DEBUGOUT("Failed to read EEPROM image\n");
2302                         return status;
2303                 }
2304                 local_buffer = buf;
2305         } else {
2306                 if (buffer_size < ptr)
2307                         return  IXGBE_ERR_PARAM;
2308                 local_buffer = &buffer[ptr];
2309         }
2310
2311         if (size) {
2312                 start = 0;
2313                 length = size;
2314         } else {
2315                 start = 1;
2316                 length = local_buffer[0];
2317
2318                 /* Skip pointer section if length is invalid. */
2319                 if (length == 0xFFFF || length == 0 ||
2320                     (ptr + length) >= hw->eeprom.word_size)
2321                         return IXGBE_SUCCESS;
2322         }
2323
2324         if (buffer && ((u32)start + (u32)length > buffer_size))
2325                 return IXGBE_ERR_PARAM;
2326
2327         for (i = start; length; i++, length--) {
2328                 if (i == bufsz && !buffer) {
2329                         ptr += bufsz;
2330                         i = 0;
2331                         if (length < bufsz)
2332                                 bufsz = length;
2333
2334                         /* Read a chunk at the pointer location */
2335                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2336                                                                   bufsz, buf);
2337                         if (status) {
2338                                 DEBUGOUT("Failed to read EEPROM image\n");
2339                                 return status;
2340                         }
2341                 }
2342                 *csum += local_buffer[i];
2343         }
2344         return IXGBE_SUCCESS;
2345 }
2346
2347 /**
2348  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2349  *  @hw: pointer to hardware structure
2350  *  @buffer: pointer to buffer containing calculated checksum
2351  *  @buffer_size: size of buffer
2352  *
2353  *  Returns a negative error code on error, or the 16-bit checksum
2354  **/
2355 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2356 {
2357         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2358         u16 *local_buffer;
2359         s32 status;
2360         u16 checksum = 0;
2361         u16 pointer, i, size;
2362
2363         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2364
2365         hw->eeprom.ops.init_params(hw);
2366
2367         if (!buffer) {
2368                 /* Read pointer area */
2369                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2370                                                      IXGBE_EEPROM_LAST_WORD + 1,
2371                                                      eeprom_ptrs);
2372                 if (status) {
2373                         DEBUGOUT("Failed to read EEPROM image\n");
2374                         return status;
2375                 }
2376                 local_buffer = eeprom_ptrs;
2377         } else {
2378                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2379                         return IXGBE_ERR_PARAM;
2380                 local_buffer = buffer;
2381         }
2382
2383         /*
2384          * For X550 hardware include 0x0-0x41 in the checksum, skip the
2385          * checksum word itself
2386          */
2387         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2388                 if (i != IXGBE_EEPROM_CHECKSUM)
2389                         checksum += local_buffer[i];
2390
2391         /*
2392          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
2393          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2394          */
2395         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2396                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2397                         continue;
2398
2399                 pointer = local_buffer[i];
2400
2401                 /* Skip pointer section if the pointer is invalid. */
2402                 if (pointer == 0xFFFF || pointer == 0 ||
2403                     pointer >= hw->eeprom.word_size)
2404                         continue;
2405
2406                 switch (i) {
2407                 case IXGBE_PCIE_GENERAL_PTR:
2408                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2409                         break;
2410                 case IXGBE_PCIE_CONFIG0_PTR:
2411                 case IXGBE_PCIE_CONFIG1_PTR:
2412                         size = IXGBE_PCIE_CONFIG_SIZE;
2413                         break;
2414                 default:
2415                         size = 0;
2416                         break;
2417                 }
2418
2419                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2420                                                 buffer, buffer_size);
2421                 if (status)
2422                         return status;
2423         }
2424
2425         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2426
2427         return (s32)checksum;
2428 }
2429
2430 /**
2431  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2432  *  @hw: pointer to hardware structure
2433  *
2434  *  Returns a negative error code on error, or the 16-bit checksum
2435  **/
2436 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2437 {
2438         return ixgbe_calc_checksum_X550(hw, NULL, 0);
2439 }
2440
2441 /**
2442  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2443  *  @hw: pointer to hardware structure
2444  *  @checksum_val: calculated checksum
2445  *
2446  *  Performs checksum calculation and validates the EEPROM checksum.  If the
2447  *  caller does not need checksum_val, the value can be NULL.
2448  **/
2449 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2450 {
2451         s32 status;
2452         u16 checksum;
2453         u16 read_checksum = 0;
2454
2455         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2456
2457         /* Read the first word from the EEPROM. If this times out or fails, do
2458          * not continue or we could be in for a very long wait while every
2459          * EEPROM read fails
2460          */
2461         status = hw->eeprom.ops.read(hw, 0, &checksum);
2462         if (status) {
2463                 DEBUGOUT("EEPROM read failed\n");
2464                 return status;
2465         }
2466
2467         status = hw->eeprom.ops.calc_checksum(hw);
2468         if (status < 0)
2469                 return status;
2470
2471         checksum = (u16)(status & 0xffff);
2472
2473         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2474                                            &read_checksum);
2475         if (status)
2476                 return status;
2477
2478         /* Verify read checksum from EEPROM is the same as
2479          * calculated checksum
2480          */
2481         if (read_checksum != checksum) {
2482                 status = IXGBE_ERR_EEPROM_CHECKSUM;
2483                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2484                              "Invalid EEPROM checksum");
2485         }
2486
2487         /* If the user cares, return the calculated checksum */
2488         if (checksum_val)
2489                 *checksum_val = checksum;
2490
2491         return status;
2492 }
2493
2494 /**
2495  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2496  * @hw: pointer to hardware structure
2497  *
2498  * After writing EEPROM to shadow RAM using EEWR register, software calculates
2499  * checksum and updates the EEPROM and instructs the hardware to update
2500  * the flash.
2501  **/
2502 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2503 {
2504         s32 status;
2505         u16 checksum = 0;
2506
2507         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2508
2509         /* Read the first word from the EEPROM. If this times out or fails, do
2510          * not continue or we could be in for a very long wait while every
2511          * EEPROM read fails
2512          */
2513         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2514         if (status) {
2515                 DEBUGOUT("EEPROM read failed\n");
2516                 return status;
2517         }
2518
2519         status = ixgbe_calc_eeprom_checksum_X550(hw);
2520         if (status < 0)
2521                 return status;
2522
2523         checksum = (u16)(status & 0xffff);
2524
2525         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2526                                             checksum);
2527         if (status)
2528                 return status;
2529
2530         status = ixgbe_update_flash_X550(hw);
2531
2532         return status;
2533 }
2534
2535 /**
2536  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2537  *  @hw: pointer to hardware structure
2538  *
2539  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2540  **/
2541 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2542 {
2543         s32 status = IXGBE_SUCCESS;
2544         union ixgbe_hic_hdr2 buffer;
2545
2546         DEBUGFUNC("ixgbe_update_flash_X550");
2547
2548         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2549         buffer.req.buf_lenh = 0;
2550         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2551         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2552
2553         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2554                                               sizeof(buffer),
2555                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2556
2557         return status;
2558 }
2559
2560 /**
2561  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2562  *  @hw: pointer to hardware structure
2563  *
2564  *  Determines physical layer capabilities of the current configuration.
2565  **/
2566 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2567 {
2568         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2569         u16 ext_ability = 0;
2570
2571         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2572
2573         hw->phy.ops.identify(hw);
2574
2575         switch (hw->phy.type) {
2576         case ixgbe_phy_x550em_kr:
2577                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2578                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2579                 break;
2580         case ixgbe_phy_x550em_kx4:
2581                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2582                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2583                 break;
2584         case ixgbe_phy_x550em_ext_t:
2585                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2586                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2587                                      &ext_ability);
2588                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2589                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2590                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2591                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2592                 break;
2593         default:
2594                 break;
2595         }
2596
2597         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2598                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2599
2600         return physical_layer;
2601 }
2602
2603 /**
2604  * ixgbe_get_bus_info_x550em - Set PCI bus info
2605  * @hw: pointer to hardware structure
2606  *
2607  * Sets bus link width and speed to unknown because X550em is
2608  * not a PCI device.
2609  **/
2610 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2611 {
2612
2613         DEBUGFUNC("ixgbe_get_bus_info_x550em");
2614
2615         hw->bus.width = ixgbe_bus_width_unknown;
2616         hw->bus.speed = ixgbe_bus_speed_unknown;
2617
2618         hw->mac.ops.set_lan_id(hw);
2619
2620         return IXGBE_SUCCESS;
2621 }
2622
2623 /**
2624  * ixgbe_disable_rx_x550 - Disable RX unit
2625  *
2626  * Enables the Rx DMA unit for x550
2627  **/
2628 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2629 {
2630         u32 rxctrl, pfdtxgswc;
2631         s32 status;
2632         struct ixgbe_hic_disable_rxen fw_cmd;
2633
2634         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2635
2636         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2637         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2638                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2639                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2640                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2641                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2642                         hw->mac.set_lben = true;
2643                 } else {
2644                         hw->mac.set_lben = false;
2645                 }
2646
2647                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2648                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2649                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2650                 fw_cmd.port_number = (u8)hw->bus.lan_id;
2651
2652                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2653                                         sizeof(struct ixgbe_hic_disable_rxen),
2654                                         IXGBE_HI_COMMAND_TIMEOUT, true);
2655
2656                 /* If we fail - disable RX using register write */
2657                 if (status) {
2658                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2659                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2660                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2661                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2662                         }
2663                 }
2664         }
2665 }
2666
2667 /**
2668  * ixgbe_enter_lplu_x550em - Transition to low power states
2669  *  @hw: pointer to hardware structure
2670  *
2671  * Configures Low Power Link Up on transition to low power states
2672  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2673  * X557 PHY immediately prior to entering LPLU.
2674  **/
2675 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2676 {
2677         u16 an_10g_cntl_reg, autoneg_reg, speed;
2678         s32 status;
2679         ixgbe_link_speed lcd_speed;
2680         u32 save_autoneg;
2681         bool link_up;
2682
2683         /* SW LPLU not required on later HW revisions. */
2684         if (IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)))
2685                 return IXGBE_SUCCESS;
2686
2687         /* If blocked by MNG FW, then don't restart AN */
2688         if (ixgbe_check_reset_blocked(hw))
2689                 return IXGBE_SUCCESS;
2690
2691         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2692         if (status != IXGBE_SUCCESS)
2693                 return status;
2694
2695         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2696
2697         if (status != IXGBE_SUCCESS)
2698                 return status;
2699
2700         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2701          * disabled, then force link down by entering low power mode.
2702          */
2703         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2704             !(hw->wol_enabled || ixgbe_mng_present(hw)))
2705                 return ixgbe_set_copper_phy_power(hw, FALSE);
2706
2707         /* Determine LCD */
2708         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2709
2710         if (status != IXGBE_SUCCESS)
2711                 return status;
2712
2713         /* If no valid LCD link speed, then force link down and exit. */
2714         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2715                 return ixgbe_set_copper_phy_power(hw, FALSE);
2716
2717         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2718                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2719                                       &speed);
2720
2721         if (status != IXGBE_SUCCESS)
2722                 return status;
2723
2724         /* If no link now, speed is invalid so take link down */
2725         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2726         if (status != IXGBE_SUCCESS)
2727                 return ixgbe_set_copper_phy_power(hw, false);
2728
2729         /* clear everything but the speed bits */
2730         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2731
2732         /* If current speed is already LCD, then exit. */
2733         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2734              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2735             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2736              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2737                 return status;
2738
2739         /* Clear AN completed indication */
2740         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2741                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2742                                       &autoneg_reg);
2743
2744         if (status != IXGBE_SUCCESS)
2745                 return status;
2746
2747         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2748                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2749                              &an_10g_cntl_reg);
2750
2751         if (status != IXGBE_SUCCESS)
2752                 return status;
2753
2754         status = hw->phy.ops.read_reg(hw,
2755                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2756                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2757                              &autoneg_reg);
2758
2759         if (status != IXGBE_SUCCESS)
2760                 return status;
2761
2762         save_autoneg = hw->phy.autoneg_advertised;
2763
2764         /* Setup link at least common link speed */
2765         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
2766
2767         /* restore autoneg from before setting lplu speed */
2768         hw->phy.autoneg_advertised = save_autoneg;
2769
2770         return status;
2771 }
2772
2773 /**
2774  * ixgbe_get_lcd_x550em - Determine lowest common denominator
2775  *  @hw: pointer to hardware structure
2776  *  @lcd_speed: pointer to lowest common link speed
2777  *
2778  * Determine lowest common link speed with link partner.
2779  **/
2780 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2781 {
2782         u16 an_lp_status;
2783         s32 status;
2784         u16 word = hw->eeprom.ctrl_word_3;
2785
2786         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2787
2788         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2789                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2790                                       &an_lp_status);
2791
2792         if (status != IXGBE_SUCCESS)
2793                 return status;
2794
2795         /* If link partner advertised 1G, return 1G */
2796         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2797                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2798                 return status;
2799         }
2800
2801         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2802         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2803             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2804                 return status;
2805
2806         /* Link partner not capable of lower speeds, return 10G */
2807         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2808         return status;
2809 }
2810
2811 /**
2812  *  ixgbe_setup_fc_X550em - Set up flow control
2813  *  @hw: pointer to hardware structure
2814  *
2815  *  Called at init time to set up flow control.
2816  **/
2817 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
2818 {
2819         s32 ret_val = IXGBE_SUCCESS;
2820         u32 pause, asm_dir, reg_val;
2821
2822         DEBUGFUNC("ixgbe_setup_fc_X550em");
2823
2824         /* Validate the requested mode */
2825         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2826                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2827                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2828                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2829                 goto out;
2830         }
2831
2832         /* 10gig parts do not have a word in the EEPROM to determine the
2833          * default flow control setting, so we explicitly set it to full.
2834          */
2835         if (hw->fc.requested_mode == ixgbe_fc_default)
2836                 hw->fc.requested_mode = ixgbe_fc_full;
2837
2838         /* Determine PAUSE and ASM_DIR bits. */
2839         switch (hw->fc.requested_mode) {
2840         case ixgbe_fc_none:
2841                 pause = 0;
2842                 asm_dir = 0;
2843                 break;
2844         case ixgbe_fc_tx_pause:
2845                 pause = 0;
2846                 asm_dir = 1;
2847                 break;
2848         case ixgbe_fc_rx_pause:
2849                 /* Rx Flow control is enabled and Tx Flow control is
2850                  * disabled by software override. Since there really
2851                  * isn't a way to advertise that we are capable of RX
2852                  * Pause ONLY, we will advertise that we support both
2853                  * symmetric and asymmetric Rx PAUSE, as such we fall
2854                  * through to the fc_full statement.  Later, we will
2855                  * disable the adapter's ability to send PAUSE frames.
2856                  */
2857         case ixgbe_fc_full:
2858                 pause = 1;
2859                 asm_dir = 1;
2860                 break;
2861         default:
2862                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2863                         "Flow control param set incorrectly\n");
2864                 ret_val = IXGBE_ERR_CONFIG;
2865                 goto out;
2866         }
2867
2868         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
2869                 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
2870                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2871                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2872                 if (ret_val != IXGBE_SUCCESS)
2873                         goto out;
2874                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2875                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2876                 if (pause)
2877                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2878                 if (asm_dir)
2879                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2880                 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
2881                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2882                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2883
2884                 /* This device does not fully support AN. */
2885                 hw->fc.disable_fc_autoneg = true;
2886         }
2887
2888 out:
2889         return ret_val;
2890 }
2891
2892 /**
2893  * ixgbe_set_mux - Set mux for port 1 access with CS4227
2894  * @hw: pointer to hardware structure
2895  * @state: set mux if 1, clear if 0
2896  */
2897 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2898 {
2899         u32 esdp;
2900
2901         if (!hw->bus.lan_id)
2902                 return;
2903         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2904         if (state)
2905                 esdp |= IXGBE_ESDP_SDP1;
2906         else
2907                 esdp &= ~IXGBE_ESDP_SDP1;
2908         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2909         IXGBE_WRITE_FLUSH(hw);
2910 }
2911
2912 /**
2913  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2914  *  @hw: pointer to hardware structure
2915  *  @mask: Mask to specify which semaphore to acquire
2916  *
2917  *  Acquires the SWFW semaphore and sets the I2C MUX
2918  **/
2919 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2920 {
2921         s32 status;
2922
2923         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
2924
2925         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2926         if (status)
2927                 return status;
2928
2929         if (mask & IXGBE_GSSR_I2C_MASK)
2930                 ixgbe_set_mux(hw, 1);
2931
2932         return IXGBE_SUCCESS;
2933 }
2934
2935 /**
2936  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2937  *  @hw: pointer to hardware structure
2938  *  @mask: Mask to specify which semaphore to release
2939  *
2940  *  Releases the SWFW semaphore and sets the I2C MUX
2941  **/
2942 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2943 {
2944         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
2945
2946         if (mask & IXGBE_GSSR_I2C_MASK)
2947                 ixgbe_set_mux(hw, 0);
2948
2949         ixgbe_release_swfw_sync_X540(hw, mask);
2950 }
2951
2952 /**
2953  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2954  * @hw: pointer to hardware structure
2955  *
2956  * Handle external Base T PHY interrupt. If high temperature
2957  * failure alarm then return error, else if link status change
2958  * then setup internal/external PHY link
2959  *
2960  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2961  * failure alarm, else return PHY access status.
2962  */
2963 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2964 {
2965         bool lsc;
2966         u32 status;
2967
2968         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2969
2970         if (status != IXGBE_SUCCESS)
2971                 return status;
2972
2973         if (lsc)
2974                 return ixgbe_setup_internal_phy(hw);
2975
2976         return IXGBE_SUCCESS;
2977 }
2978
2979 /**
2980  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
2981  * @hw: pointer to hardware structure
2982  * @speed: new link speed
2983  * @autoneg_wait_to_complete: true when waiting for completion is needed
2984  *
2985  * Setup internal/external PHY link speed based on link speed, then set
2986  * external PHY auto advertised link speed.
2987  *
2988  * Returns error status for any failure
2989  **/
2990 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
2991                                   ixgbe_link_speed speed,
2992                                   bool autoneg_wait_to_complete)
2993 {
2994         s32 status;
2995         ixgbe_link_speed force_speed;
2996
2997         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
2998
2999         /* Setup internal/external PHY link speed to iXFI (10G), unless
3000          * only 1G is auto advertised then setup KX link.
3001          */
3002         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
3003                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3004         else
3005                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3006
3007         /* If internal link mode is XFI, then setup XFI internal link. */
3008         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3009                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
3010
3011                 if (status != IXGBE_SUCCESS)
3012                         return status;
3013         }
3014
3015         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
3016 }
3017
3018 /**
3019  * ixgbe_check_link_t_X550em - Determine link and speed status
3020  * @hw: pointer to hardware structure
3021  * @speed: pointer to link speed
3022  * @link_up: true when link is up
3023  * @link_up_wait_to_complete: bool used to wait for link up or not
3024  *
3025  * Check that both the MAC and X557 external PHY have link.
3026  **/
3027 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3028                               bool *link_up, bool link_up_wait_to_complete)
3029 {
3030         u32 status;
3031         u16 autoneg_status;
3032
3033         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3034                 return IXGBE_ERR_CONFIG;
3035
3036         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
3037                                               link_up_wait_to_complete);
3038
3039         /* If check link fails or MAC link is not up, then return */
3040         if (status != IXGBE_SUCCESS || !(*link_up))
3041                 return status;
3042
3043         /* MAC link is up, so check external PHY link.
3044          * Read this twice back to back to indicate current status.
3045          */
3046         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3047                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3048                                       &autoneg_status);
3049
3050         if (status != IXGBE_SUCCESS)
3051                 return status;
3052
3053         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3054                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3055                                       &autoneg_status);
3056
3057         if (status != IXGBE_SUCCESS)
3058                 return status;
3059
3060         /* If external PHY link is not up, then indicate link not up */
3061         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
3062                 *link_up = false;
3063
3064         return IXGBE_SUCCESS;
3065 }
3066
3067 /**
3068  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
3069  *  @hw: pointer to hardware structure
3070  **/
3071 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
3072 {
3073         s32 status;
3074
3075         status = ixgbe_reset_phy_generic(hw);
3076
3077         if (status != IXGBE_SUCCESS)
3078                 return status;
3079
3080         /* Configure Link Status Alarm and Temperature Threshold interrupts */
3081         return ixgbe_enable_lasi_ext_t_x550em(hw);
3082 }
3083
3084 /**
3085  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
3086  *  @hw: pointer to hardware structure
3087  *  @led_idx: led number to turn on
3088  **/
3089 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3090 {
3091         u16 phy_data;
3092
3093         DEBUGFUNC("ixgbe_led_on_t_X550em");
3094
3095         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3096                 return IXGBE_ERR_PARAM;
3097
3098         /* To turn on the LED, set mode to ON. */
3099         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3100                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3101         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
3102         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3103                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3104
3105         return IXGBE_SUCCESS;
3106 }
3107
3108 /**
3109  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
3110  *  @hw: pointer to hardware structure
3111  *  @led_idx: led number to turn off
3112  **/
3113 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3114 {
3115         u16 phy_data;
3116
3117         DEBUGFUNC("ixgbe_led_off_t_X550em");
3118
3119         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3120                 return IXGBE_ERR_PARAM;
3121
3122         /* To turn on the LED, set mode to ON. */
3123         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3124                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3125         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
3126         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3127                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3128
3129         return IXGBE_SUCCESS;
3130 }