drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42
  43 /**
  44  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  45  *  @hw: pointer to hardware structure
  46  *
  47  *  Initialize the function pointers and assign the MAC type for X550.
  48  *  Does not touch the hardware.
  49  **/
  50 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  51 {
  52         struct ixgbe_mac_info *mac = &hw->mac;
  53         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  54         s32 ret_val;
  55
  56         DEBUGFUNC("ixgbe_init_ops_X550");
  57
  58         ret_val = ixgbe_init_ops_X540(hw);
  59         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  60         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  61         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  62         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  63         mac->ops.set_source_address_pruning =
  64                         ixgbe_set_source_address_pruning_X550;
  65         mac->ops.set_ethertype_anti_spoofing =
  66                         ixgbe_set_ethertype_anti_spoofing_X550;
  67
  68         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  69         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  70         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  71         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  72         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  73         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  74         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  75         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  76         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  77
  78         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  79         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  80         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  81         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  82         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  83         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
  84                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  85                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  86         }
  87         return ret_val;
  88 }
  89
  90 /**
  91  * ixgbe_read_cs4227 - Read CS4227 register
  92  * @hw: pointer to hardware structure
  93  * @reg: register number to write
  94  * @value: pointer to receive value read
  95  *
  96  * Returns status code
  97  **/
  98 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  99 {
 100         return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 101 }
 102
 103 /**
 104  * ixgbe_write_cs4227 - Write CS4227 register
 105  * @hw: pointer to hardware structure
 106  * @reg: register number to write
 107  * @value: value to write to register
 108  *
 109  * Returns status code
 110  **/
 111 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 112 {
 113         return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 114 }
 115
 116 /**
 117  * ixgbe_read_pe - Read register from port expander
 118  * @hw: pointer to hardware structure
 119  * @reg: register number to read
 120  * @value: pointer to receive read value
 121  *
 122  * Returns status code
 123  **/
 124 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 125 {
 126         s32 status;
 127
 128         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 129         if (status != IXGBE_SUCCESS)
 130                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 131                               "port expander access failed with %d\n", status);
 132         return status;
 133 }
 134
 135 /**
 136  * ixgbe_write_pe - Write register to port expander
 137  * @hw: pointer to hardware structure
 138  * @reg: register number to write
 139  * @value: value to write
 140  *
 141  * Returns status code
 142  **/
 143 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 144 {
 145         s32 status;
 146
 147         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 148         if (status != IXGBE_SUCCESS)
 149                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 150                               "port expander access failed with %d\n", status);
 151         return status;
 152 }
 153
 154 /**
 155  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 156  * @hw: pointer to hardware structure
 157  *
 158  * This function assumes that the caller has acquired the proper semaphore.
 159  * Returns error code
 160  **/
 161 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 162 {
 163         s32 status;
 164         u32 retry;
 165         u16 value;
 166         u8 reg;
 167
 168         /* Trigger hard reset. */
 169         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 170         if (status != IXGBE_SUCCESS)
 171                 return status;
 172         reg |= IXGBE_PE_BIT1;
 173         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 174         if (status != IXGBE_SUCCESS)
 175                 return status;
 176
 177         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 178         if (status != IXGBE_SUCCESS)
 179                 return status;
 180         reg &= ~IXGBE_PE_BIT1;
 181         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 182         if (status != IXGBE_SUCCESS)
 183                 return status;
 184
 185         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 186         if (status != IXGBE_SUCCESS)
 187                 return status;
 188         reg &= ~IXGBE_PE_BIT1;
 189         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 190         if (status != IXGBE_SUCCESS)
 191                 return status;
 192
 193         usec_delay(IXGBE_CS4227_RESET_HOLD);
 194
 195         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 196         if (status != IXGBE_SUCCESS)
 197                 return status;
 198         reg |= IXGBE_PE_BIT1;
 199         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 200         if (status != IXGBE_SUCCESS)
 201                 return status;
 202
 203         /* Wait for the reset to complete. */
 204         msec_delay(IXGBE_CS4227_RESET_DELAY);
 205         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 206                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 207                                            &value);
 208                 if (status == IXGBE_SUCCESS &&
 209                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 210                         break;
 211                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 212         }
 213         if (retry == IXGBE_CS4227_RETRIES) {
 214                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 215                         "CS4227 reset did not complete.");
 216                 return IXGBE_ERR_PHY;
 217         }
 218
 219         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 220         if (status != IXGBE_SUCCESS ||
 221             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 222                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 223                         "CS4227 EEPROM did not load successfully.");
 224                 return IXGBE_ERR_PHY;
 225         }
 226
 227         return IXGBE_SUCCESS;
 228 }
 229
 230 /**
 231  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 232  * @hw: pointer to hardware structure
 233  **/
 234 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 235 {
 236         s32 status = IXGBE_SUCCESS;
 237         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 238         u16 value = 0;
 239         u8 retry;
 240
 241         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 242                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 243                 if (status != IXGBE_SUCCESS) {
 244                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 245                                 "semaphore failed with %d", status);
 246                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 247                         continue;
 248                 }
 249
 250                 /* Get status of reset flow. */
 251                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 252
 253                 if (status == IXGBE_SUCCESS &&
 254                     value == IXGBE_CS4227_RESET_COMPLETE)
 255                         goto out;
 256
 257                 if (status != IXGBE_SUCCESS ||
 258                     value != IXGBE_CS4227_RESET_PENDING)
 259                         break;
 260
 261                 /* Reset is pending. Wait and check again. */
 262                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 263                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 264         }
 265
 266         /* If still pending, assume other instance failed. */
 267         if (retry == IXGBE_CS4227_RETRIES) {
 268                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 269                 if (status != IXGBE_SUCCESS) {
 270                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 271                                       "semaphore failed with %d", status);
 272                         return;
 273                 }
 274         }
 275
 276         /* Reset the CS4227. */
 277         status = ixgbe_reset_cs4227(hw);
 278         if (status != IXGBE_SUCCESS) {
 279                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 280                         "CS4227 reset failed: %d", status);
 281                 goto out;
 282         }
 283
 284         /* Reset takes so long, temporarily release semaphore in case the
 285          * other driver instance is waiting for the reset indication.
 286          */
 287         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 288                            IXGBE_CS4227_RESET_PENDING);
 289         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 290         msec_delay(10);
 291         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 292         if (status != IXGBE_SUCCESS) {
 293                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 294                         "semaphore failed with %d", status);
 295                 return;
 296         }
 297
 298         /* Record completion for next time. */
 299         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 300                 IXGBE_CS4227_RESET_COMPLETE);
 301
 302 out:
 303         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 304         msec_delay(hw->eeprom.semaphore_delay);
 305 }
 306
 307 /**
 308  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 309  * @hw: pointer to hardware structure
 310  **/
 311 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 312 {
 313         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 314
 315         if (hw->bus.lan_id) {
 316                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 317                 esdp |= IXGBE_ESDP_SDP1_DIR;
 318         }
 319         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 320         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 321         IXGBE_WRITE_FLUSH(hw);
 322 }
 323
 324 /**
 325  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 326  * @hw: pointer to hardware structure
 327  *
 328  * Returns error code
 329  */
 330 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 331 {
 332         switch (hw->device_id) {
 333         case IXGBE_DEV_ID_X550EM_X_SFP:
 334                 /* set up for CS4227 usage */
 335                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 336                 ixgbe_setup_mux_ctl(hw);
 337                 ixgbe_check_cs4227(hw);
 338
 339                 return ixgbe_identify_module_generic(hw);
 340                 break;
 341         case IXGBE_DEV_ID_X550EM_X_KX4:
 342                 hw->phy.type = ixgbe_phy_x550em_kx4;
 343                 break;
 344         case IXGBE_DEV_ID_X550EM_X_KR:
 345                 hw->phy.type = ixgbe_phy_x550em_kr;
 346                 break;
 347         case IXGBE_DEV_ID_X550EM_X_1G_T:
 348         case IXGBE_DEV_ID_X550EM_X_10G_T:
 349                 return ixgbe_identify_phy_generic(hw);
 350         default:
 351                 break;
 352         }
 353         return IXGBE_SUCCESS;
 354 }
 355
 356 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 357                                      u32 device_type, u16 *phy_data)
 358 {
 359         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 360         return IXGBE_NOT_IMPLEMENTED;
 361 }
 362
 363 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 364                                       u32 device_type, u16 phy_data)
 365 {
 366         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 367         return IXGBE_NOT_IMPLEMENTED;
 368 }
 369
 370 /**
 371 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 372 *  @hw: pointer to hardware structure
 373 *
 374 *  Initialize the function pointers and for MAC type X550EM.
 375 *  Does not touch the hardware.
 376 **/
 377 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 378 {
 379         struct ixgbe_mac_info *mac = &hw->mac;
 380         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 381         struct ixgbe_phy_info *phy = &hw->phy;
 382         s32 ret_val;
 383
 384         DEBUGFUNC("ixgbe_init_ops_X550EM");
 385
 386         /* Similar to X550 so start there. */
 387         ret_val = ixgbe_init_ops_X550(hw);
 388
 389         /* Since this function eventually calls
 390          * ixgbe_init_ops_540 by design, we are setting
 391          * the pointers to NULL explicitly here to overwrite
 392          * the values being set in the x540 function.
 393          */
 394         /* Thermal sensor not supported in x550EM */
 395         mac->ops.get_thermal_sensor_data = NULL;
 396         mac->ops.init_thermal_sensor_thresh = NULL;
 397         mac->thermal_sensor_enabled = false;
 398
 399         /* FCOE not supported in x550EM */
 400         mac->ops.get_san_mac_addr = NULL;
 401         mac->ops.set_san_mac_addr = NULL;
 402         mac->ops.get_wwn_prefix = NULL;
 403         mac->ops.get_fcoe_boot_status = NULL;
 404
 405         /* IPsec not supported in x550EM */
 406         mac->ops.disable_sec_rx_path = NULL;
 407         mac->ops.enable_sec_rx_path = NULL;
 408
 409         /* AUTOC register is not present in x550EM. */
 410         mac->ops.prot_autoc_read = NULL;
 411         mac->ops.prot_autoc_write = NULL;
 412
 413         /* X550EM bus type is internal*/
 414         hw->bus.type = ixgbe_bus_type_internal;
 415         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 416
 417         if (hw->mac.type == ixgbe_mac_X550EM_x) {
 418                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 419                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 420                 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 421                 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 422         }
 423
 424         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 425         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 426         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 427         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 428         mac->ops.get_supported_physical_layer =
 429                                     ixgbe_get_supported_physical_layer_X550em;
 430
 431         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 432                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 433         else
 434                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 435
 436
 437         if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
 438                 mac->ops.setup_eee = NULL;
 439
 440         /* PHY */
 441         phy->ops.init = ixgbe_init_phy_ops_X550em;
 442         phy->ops.identify = ixgbe_identify_phy_x550em;
 443         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 444                 phy->ops.set_phy_power = NULL;
 445
 446
 447         /* EEPROM */
 448         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 449         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 450         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 451         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 452         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 453         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 454         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 455         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 456
 457         return ret_val;
 458 }
 459
 460 /**
 461  *  ixgbe_dmac_config_X550
 462  *  @hw: pointer to hardware structure
 463  *
 464  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 465  *  When disabling dmac, dmac enable dmac bit is cleared.
 466  **/
 467 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 468 {
 469         u32 reg, high_pri_tc;
 470
 471         DEBUGFUNC("ixgbe_dmac_config_X550");
 472
 473         /* Disable DMA coalescing before configuring */
 474         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 475         reg &= ~IXGBE_DMACR_DMAC_EN;
 476         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 477
 478         /* Disable DMA Coalescing if the watchdog timer is 0 */
 479         if (!hw->mac.dmac_config.watchdog_timer)
 480                 goto out;
 481
 482         ixgbe_dmac_config_tcs_X550(hw);
 483
 484         /* Configure DMA Coalescing Control Register */
 485         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 486
 487         /* Set the watchdog timer in units of 40.96 usec */
 488         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 489         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 490
 491         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 492         /* If fcoe is enabled, set high priority traffic class */
 493         if (hw->mac.dmac_config.fcoe_en) {
 494                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 495                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 496                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 497         }
 498         reg |= IXGBE_DMACR_EN_MNG_IND;
 499
 500         /* Enable DMA coalescing after configuration */
 501         reg |= IXGBE_DMACR_DMAC_EN;
 502         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 503
 504 out:
 505         return IXGBE_SUCCESS;
 506 }
 507
 508 /**
 509  *  ixgbe_dmac_config_tcs_X550
 510  *  @hw: pointer to hardware structure
 511  *
 512  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 513  *  be cleared before configuring.
 514  **/
 515 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 516 {
 517         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 518
 519         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 520
 521         /* Configure DMA coalescing enabled */
 522         switch (hw->mac.dmac_config.link_speed) {
 523         case IXGBE_LINK_SPEED_100_FULL:
 524                 pb_headroom = IXGBE_DMACRXT_100M;
 525                 break;
 526         case IXGBE_LINK_SPEED_1GB_FULL:
 527                 pb_headroom = IXGBE_DMACRXT_1G;
 528                 break;
 529         default:
 530                 pb_headroom = IXGBE_DMACRXT_10G;
 531                 break;
 532         }
 533
 534         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 535                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 536
 537         /* Set the per Rx packet buffer receive threshold */
 538         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 539                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 540                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 541
 542                 if (tc < hw->mac.dmac_config.num_tcs) {
 543                         /* Get Rx PB size */
 544                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 545                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 546                                 IXGBE_RXPBSIZE_SHIFT;
 547
 548                         /* Calculate receive buffer threshold in kilobytes */
 549                         if (rx_pb_size > pb_headroom)
 550                                 rx_pb_size = rx_pb_size - pb_headroom;
 551                         else
 552                                 rx_pb_size = 0;
 553
 554                         /* Minimum of MFS shall be set for DMCTH */
 555                         reg |= (rx_pb_size > maxframe_size_kb) ?
 556                                 rx_pb_size : maxframe_size_kb;
 557                 }
 558                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 559         }
 560         return IXGBE_SUCCESS;
 561 }
 562
 563 /**
 564  *  ixgbe_dmac_update_tcs_X550
 565  *  @hw: pointer to hardware structure
 566  *
 567  *  Disables dmac, updates per TC settings, and then enables dmac.
 568  **/
 569 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 570 {
 571         u32 reg;
 572
 573         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 574
 575         /* Disable DMA coalescing before configuring */
 576         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 577         reg &= ~IXGBE_DMACR_DMAC_EN;
 578         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 579
 580         ixgbe_dmac_config_tcs_X550(hw);
 581
 582         /* Enable DMA coalescing after configuration */
 583         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 584         reg |= IXGBE_DMACR_DMAC_EN;
 585         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 586
 587         return IXGBE_SUCCESS;
 588 }
 589
 590 /**
 591  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 592  *  @hw: pointer to hardware structure
 593  *
 594  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 595  *  ixgbe_hw struct in order to set up EEPROM access.
 596  **/
 597 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 598 {
 599         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 600         u32 eec;
 601         u16 eeprom_size;
 602
 603         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 604
 605         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 606                 eeprom->semaphore_delay = 10;
 607                 eeprom->type = ixgbe_flash;
 608
 609                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 610                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 611                                     IXGBE_EEC_SIZE_SHIFT);
 612                 eeprom->word_size = 1 << (eeprom_size +
 613                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 614
 615                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 616                           eeprom->type, eeprom->word_size);
 617         }
 618
 619         return IXGBE_SUCCESS;
 620 }
 621
 622 /**
 623  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 624  *  @hw: pointer to the HW structure
 625  *  @enable_eee: boolean flag to enable EEE
 626  *
 627  *  Enable/disable EEE based on enable_eee flag.
 628  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 629  *  are modified.
 630  *
 631  **/
 632 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 633 {
 634         u32 eeer;
 635         u16 autoneg_eee_reg;
 636         u32 link_reg;
 637         s32 status;
 638         u32 fuse;
 639
 640         DEBUGFUNC("ixgbe_setup_eee_X550");
 641
 642         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 643         /* Enable or disable EEE per flag */
 644         if (enable_eee) {
 645                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 646
 647                 if (hw->mac.type == ixgbe_mac_X550) {
 648                         /* Advertise EEE capability */
 649                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 650                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 651
 652                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 653                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 654                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 655
 656                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 657                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 658                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 659                         /* Not supported on first revision. */
 660                         fuse = IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0));
 661                         if (!(fuse & IXGBE_FUSES0_REV1))
 662                                 return IXGBE_SUCCESS;
 663
 664                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 665                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 666                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 667                         if (status != IXGBE_SUCCESS)
 668                                 return status;
 669
 670                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 671                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 672
 673                         /* Don't advertise FEC capability when EEE enabled. */
 674                         link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 675
 676                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 677                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 678                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 679                         if (status != IXGBE_SUCCESS)
 680                                 return status;
 681                 }
 682         } else {
 683                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 684
 685                 if (hw->mac.type == ixgbe_mac_X550) {
 686                         /* Disable advertised EEE capability */
 687                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 688                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 689
 690                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 691                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 692                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 693
 694                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 695                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 696                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 697                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 698                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 699                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 700                         if (status != IXGBE_SUCCESS)
 701                                 return status;
 702
 703                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 704                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 705
 706                         /* Advertise FEC capability when EEE is disabled. */
 707                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 708
 709                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 710                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 711                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 712                         if (status != IXGBE_SUCCESS)
 713                                 return status;
 714                 }
 715         }
 716         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 717
 718         return IXGBE_SUCCESS;
 719 }
 720
 721 /**
 722  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 723  * @hw: pointer to hardware structure
 724  * @enable: enable or disable source address pruning
 725  * @pool: Rx pool to set source address pruning for
 726  **/
 727 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 728                                            unsigned int pool)
 729 {
 730         u64 pfflp;
 731
 732         /* max rx pool is 63 */
 733         if (pool > 63)
 734                 return;
 735
 736         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 737         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 738
 739         if (enable)
 740                 pfflp |= (1ULL << pool);
 741         else
 742                 pfflp &= ~(1ULL << pool);
 743
 744         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 745         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 746 }
 747
 748 /**
 749  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 750  *  @hw: pointer to hardware structure
 751  *  @enable: enable or disable switch for Ethertype anti-spoofing
 752  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 753  *
 754  **/
 755 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 756                 bool enable, int vf)
 757 {
 758         int vf_target_reg = vf >> 3;
 759         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 760         u32 pfvfspoof;
 761
 762         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 763
 764         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 765         if (enable)
 766                 pfvfspoof |= (1 << vf_target_shift);
 767         else
 768                 pfvfspoof &= ~(1 << vf_target_shift);
 769
 770         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 771 }
 772
 773 /**
 774  * ixgbe_iosf_wait - Wait for IOSF command completion
 775  * @hw: pointer to hardware structure
 776  * @ctrl: pointer to location to receive final IOSF control value
 777  *
 778  * Returns failing status on timeout
 779  *
 780  * Note: ctrl can be NULL if the IOSF control register value is not needed
 781  **/
 782 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
 783 {
 784         u32 i, command = 0;
 785
 786         /* Check every 10 usec to see if the address cycle completed.
 787          * The SB IOSF BUSY bit will clear when the operation is
 788          * complete
 789          */
 790         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 791                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 792                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 793                         break;
 794                 usec_delay(10);
 795         }
 796         if (ctrl)
 797                 *ctrl = command;
 798         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 799                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
 800                 return IXGBE_ERR_PHY;
 801         }
 802
 803         return IXGBE_SUCCESS;
 804 }
 805
 806 /**
 807  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 808  *  device
 809  *  @hw: pointer to hardware structure
 810  *  @reg_addr: 32 bit PHY register to write
 811  *  @device_type: 3 bit device type
 812  *  @data: Data to write to the register
 813  **/
 814 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 815                             u32 device_type, u32 data)
 816 {
 817         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 818         u32 command, error;
 819         s32 ret;
 820
 821         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
 822         if (ret != IXGBE_SUCCESS)
 823                 return ret;
 824
 825         ret = ixgbe_iosf_wait(hw, NULL);
 826         if (ret != IXGBE_SUCCESS)
 827                 goto out;
 828
 829         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 830                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 831
 832         /* Write IOSF control register */
 833         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 834
 835         /* Write IOSF data register */
 836         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 837
 838         ret = ixgbe_iosf_wait(hw, &command);
 839
 840         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 841                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 842                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 843                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 844                               "Failed to write, error %x\n", error);
 845                 ret = IXGBE_ERR_PHY;
 846         }
 847
 848 out:
 849         ixgbe_release_swfw_semaphore(hw, gssr);
 850         return ret;
 851 }
 852
 853 /**
 854  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 855  *  device
 856  *  @hw: pointer to hardware structure
 857  *  @reg_addr: 32 bit PHY register to write
 858  *  @device_type: 3 bit device type
 859  *  @phy_data: Pointer to read data from the register
 860  **/
 861 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 862                            u32 device_type, u32 *data)
 863 {
 864         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 865         u32 command, error;
 866         s32 ret;
 867
 868         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
 869         if (ret != IXGBE_SUCCESS)
 870                 return ret;
 871
 872         ret = ixgbe_iosf_wait(hw, NULL);
 873         if (ret != IXGBE_SUCCESS)
 874                 goto out;
 875
 876         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 877                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 878
 879         /* Write IOSF control register */
 880         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 881
 882         ret = ixgbe_iosf_wait(hw, &command);
 883
 884         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 885                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 886                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 887                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 888                                 "Failed to read, error %x\n", error);
 889                 ret = IXGBE_ERR_PHY;
 890         }
 891
 892         if (ret == IXGBE_SUCCESS)
 893                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 894
 895 out:
 896         ixgbe_release_swfw_semaphore(hw, gssr);
 897         return ret;
 898 }
 899
 900 /**
 901  *  ixgbe_disable_mdd_X550
 902  *  @hw: pointer to hardware structure
 903  *
 904  *  Disable malicious driver detection
 905  **/
 906 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
 907 {
 908         u32 reg;
 909
 910         DEBUGFUNC("ixgbe_disable_mdd_X550");
 911
 912         /* Disable MDD for TX DMA and interrupt */
 913         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 914         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 915         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 916
 917         /* Disable MDD for RX and interrupt */
 918         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 919         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 920         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 921 }
 922
 923 /**
 924  *  ixgbe_enable_mdd_X550
 925  *  @hw: pointer to hardware structure
 926  *
 927  *  Enable malicious driver detection
 928  **/
 929 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
 930 {
 931         u32 reg;
 932
 933         DEBUGFUNC("ixgbe_enable_mdd_X550");
 934
 935         /* Enable MDD for TX DMA and interrupt */
 936         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 937         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 938         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 939
 940         /* Enable MDD for RX and interrupt */
 941         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 942         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 943         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 944 }
 945
 946 /**
 947  *  ixgbe_restore_mdd_vf_X550
 948  *  @hw: pointer to hardware structure
 949  *  @vf: vf index
 950  *
 951  *  Restore VF that was disabled during malicious driver detection event
 952  **/
 953 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
 954 {
 955         u32 idx, reg, num_qs, start_q, bitmask;
 956
 957         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
 958
 959         /* Map VF to queues */
 960         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 961         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 962         case IXGBE_MRQC_VMDQRT8TCEN:
 963                 num_qs = 8;  /* 16 VFs / pools */
 964                 bitmask = 0x000000FF;
 965                 break;
 966         case IXGBE_MRQC_VMDQRSS32EN:
 967         case IXGBE_MRQC_VMDQRT4TCEN:
 968                 num_qs = 4;  /* 32 VFs / pools */
 969                 bitmask = 0x0000000F;
 970                 break;
 971         default:            /* 64 VFs / pools */
 972                 num_qs = 2;
 973                 bitmask = 0x00000003;
 974                 break;
 975         }
 976         start_q = vf * num_qs;
 977
 978         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
 979         idx = start_q / 32;
 980         reg = 0;
 981         reg |= (bitmask << (start_q % 32));
 982         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
 983         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
 984 }
 985
 986 /**
 987  *  ixgbe_mdd_event_X550
 988  *  @hw: pointer to hardware structure
 989  *  @vf_bitmap: vf bitmap of malicious vfs
 990  *
 991  *  Handle malicious driver detection event.
 992  **/
 993 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
 994 {
 995         u32 wqbr;
 996         u32 i, j, reg, q, shift, vf, idx;
 997
 998         DEBUGFUNC("ixgbe_mdd_event_X550");
 999
1000         /* figure out pool size for mapping to vf's */
1001         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1002         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1003         case IXGBE_MRQC_VMDQRT8TCEN:
1004                 shift = 3;  /* 16 VFs / pools */
1005                 break;
1006         case IXGBE_MRQC_VMDQRSS32EN:
1007         case IXGBE_MRQC_VMDQRT4TCEN:
1008                 shift = 2;  /* 32 VFs / pools */
1009                 break;
1010         default:
1011                 shift = 1;  /* 64 VFs / pools */
1012                 break;
1013         }
1014
1015         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1016         for (i = 0; i < 4; i++) {
1017                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1018                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1019
1020                 if (!wqbr)
1021                         continue;
1022
1023                 /* Get malicious queue */
1024                 for (j = 0; j < 32 && wqbr; j++) {
1025
1026                         if (!(wqbr & (1 << j)))
1027                                 continue;
1028
1029                         /* Get queue from bitmask */
1030                         q = j + (i * 32);
1031
1032                         /* Map queue to vf */
1033                         vf = (q >> shift);
1034
1035                         /* Set vf bit in vf_bitmap */
1036                         idx = vf / 32;
1037                         vf_bitmap[idx] |= (1 << (vf % 32));
1038                         wqbr &= ~(1 << j);
1039                 }
1040         }
1041 }
1042
1043 /**
1044  *  ixgbe_get_media_type_X550em - Get media type
1045  *  @hw: pointer to hardware structure
1046  *
1047  *  Returns the media type (fiber, copper, backplane)
1048  */
1049 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1050 {
1051         enum ixgbe_media_type media_type;
1052
1053         DEBUGFUNC("ixgbe_get_media_type_X550em");
1054
1055         /* Detect if there is a copper PHY attached. */
1056         switch (hw->device_id) {
1057         case IXGBE_DEV_ID_X550EM_X_KR:
1058         case IXGBE_DEV_ID_X550EM_X_KX4:
1059                 media_type = ixgbe_media_type_backplane;
1060                 break;
1061         case IXGBE_DEV_ID_X550EM_X_SFP:
1062                 media_type = ixgbe_media_type_fiber;
1063                 break;
1064         case IXGBE_DEV_ID_X550EM_X_1G_T:
1065         case IXGBE_DEV_ID_X550EM_X_10G_T:
1066                 media_type = ixgbe_media_type_copper;
1067                 break;
1068         default:
1069                 media_type = ixgbe_media_type_unknown;
1070                 break;
1071         }
1072         return media_type;
1073 }
1074
1075 /**
1076  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1077  *  @hw: pointer to hardware structure
1078  *  @linear: true if SFP module is linear
1079  */
1080 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1081 {
1082         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1083
1084         switch (hw->phy.sfp_type) {
1085         case ixgbe_sfp_type_not_present:
1086                 return IXGBE_ERR_SFP_NOT_PRESENT;
1087         case ixgbe_sfp_type_da_cu_core0:
1088         case ixgbe_sfp_type_da_cu_core1:
1089                 *linear = true;
1090                 break;
1091         case ixgbe_sfp_type_srlr_core0:
1092         case ixgbe_sfp_type_srlr_core1:
1093         case ixgbe_sfp_type_da_act_lmt_core0:
1094         case ixgbe_sfp_type_da_act_lmt_core1:
1095         case ixgbe_sfp_type_1g_sx_core0:
1096         case ixgbe_sfp_type_1g_sx_core1:
1097         case ixgbe_sfp_type_1g_lx_core0:
1098         case ixgbe_sfp_type_1g_lx_core1:
1099                 *linear = false;
1100                 break;
1101         case ixgbe_sfp_type_unknown:
1102         case ixgbe_sfp_type_1g_cu_core0:
1103         case ixgbe_sfp_type_1g_cu_core1:
1104         default:
1105                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1106         }
1107
1108         return IXGBE_SUCCESS;
1109 }
1110
1111 /**
1112  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1113  *  @hw: pointer to hardware structure
1114  *
1115  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1116  **/
1117 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1118 {
1119         s32 status;
1120         bool linear;
1121
1122         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1123
1124         status = ixgbe_identify_module_generic(hw);
1125
1126         if (status != IXGBE_SUCCESS)
1127                 return status;
1128
1129         /* Check if SFP module is supported */
1130         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1131
1132         return status;
1133 }
1134
1135 /**
1136  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1137  *  @hw: pointer to hardware structure
1138  */
1139 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1140 {
1141         s32 status;
1142         bool linear;
1143
1144         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1145
1146         /* Check if SFP module is supported */
1147         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1148
1149         if (status != IXGBE_SUCCESS)
1150                 return status;
1151
1152         ixgbe_init_mac_link_ops_X550em(hw);
1153         hw->phy.ops.reset = NULL;
1154
1155         return IXGBE_SUCCESS;
1156 }
1157
1158 /**
1159  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1160  *  @hw: pointer to hardware structure
1161  */
1162 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1163 {
1164         struct ixgbe_mac_info *mac = &hw->mac;
1165
1166         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1167
1168          switch (hw->mac.ops.get_media_type(hw)) {
1169          case ixgbe_media_type_fiber:
1170                 /* CS4227 does not support autoneg, so disable the laser control
1171                  * functions for SFP+ fiber
1172                  */
1173                 mac->ops.disable_tx_laser = NULL;
1174                 mac->ops.enable_tx_laser = NULL;
1175                 mac->ops.flap_tx_laser = NULL;
1176                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1177                 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1178                 mac->ops.set_rate_select_speed =
1179                                         ixgbe_set_soft_rate_select_speed;
1180                 break;
1181         case ixgbe_media_type_copper:
1182                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1183                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1184                 break;
1185         default:
1186                 break;
1187          }
1188 }
1189
1190 /**
1191  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1192  *  @hw: pointer to hardware structure
1193  *  @speed: pointer to link speed
1194  *  @autoneg: true when autoneg or autotry is enabled
1195  */
1196 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1197                                        ixgbe_link_speed *speed,
1198                                        bool *autoneg)
1199 {
1200         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1201
1202         /* SFP */
1203         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1204
1205                 /* CS4227 SFP must not enable auto-negotiation */
1206                 *autoneg = false;
1207
1208                 /* Check if 1G SFP module. */
1209                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1210                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1211                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1212                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1213                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1214                         return IXGBE_SUCCESS;
1215                 }
1216
1217                 /* Link capabilities are based on SFP */
1218                 if (hw->phy.multispeed_fiber)
1219                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1220                                  IXGBE_LINK_SPEED_1GB_FULL;
1221                 else
1222                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1223         } else {
1224                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1225                          IXGBE_LINK_SPEED_1GB_FULL;
1226                 *autoneg = true;
1227         }
1228
1229         return IXGBE_SUCCESS;
1230 }
1231
1232 /**
1233  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1234  * @hw: pointer to hardware structure
1235  * @lsc: pointer to boolean flag which indicates whether external Base T
1236  *       PHY interrupt is lsc
1237  *
1238  * Determime if external Base T PHY interrupt cause is high temperature
1239  * failure alarm or link status change.
1240  *
1241  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1242  * failure alarm, else return PHY access status.
1243  */
1244 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1245 {
1246         u32 status;
1247         u16 reg;
1248
1249         *lsc = false;
1250
1251         /* Vendor alarm triggered */
1252         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1253                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1254                                       &reg);
1255
1256         if (status != IXGBE_SUCCESS ||
1257             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1258                 return status;
1259
1260         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1261         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1262                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1263                                       &reg);
1264
1265         if (status != IXGBE_SUCCESS ||
1266             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1267             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1268                 return status;
1269
1270         /* Global alarm triggered */
1271         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1272                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1273                                       &reg);
1274
1275         if (status != IXGBE_SUCCESS)
1276                 return status;
1277
1278         /* If high temperature failure, then return over temp error and exit */
1279         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1280                 /* power down the PHY in case the PHY FW didn't already */
1281                 ixgbe_set_copper_phy_power(hw, false);
1282                 return IXGBE_ERR_OVERTEMP;
1283         } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1284                 /*  device fault alarm triggered */
1285                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1286                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1287                                           &reg);
1288
1289                 if (status != IXGBE_SUCCESS)
1290                         return status;
1291
1292                 /* if device fault was due to high temp alarm handle and exit */
1293                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1294                         /* power down the PHY in case the PHY FW didn't */
1295                         ixgbe_set_copper_phy_power(hw, false);
1296                         return IXGBE_ERR_OVERTEMP;
1297                 }
1298         }
1299
1300         /* Vendor alarm 2 triggered */
1301         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1302                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1303
1304         if (status != IXGBE_SUCCESS ||
1305             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1306                 return status;
1307
1308         /* link connect/disconnect event occurred */
1309         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1310                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1311
1312         if (status != IXGBE_SUCCESS)
1313                 return status;
1314
1315         /* Indicate LSC */
1316         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1317                 *lsc = true;
1318
1319         return IXGBE_SUCCESS;
1320 }
1321
1322 /**
1323  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1324  * @hw: pointer to hardware structure
1325  *
1326  * Enable link status change and temperature failure alarm for the external
1327  * Base T PHY
1328  *
1329  * Returns PHY access status
1330  */
1331 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1332 {
1333         u32 status;
1334         u16 reg;
1335         bool lsc;
1336
1337         /* Clear interrupt flags */
1338         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1339
1340         /* Enable link status change alarm */
1341         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1342                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1343
1344         if (status != IXGBE_SUCCESS)
1345                 return status;
1346
1347         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1348
1349         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1350                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1351
1352         if (status != IXGBE_SUCCESS)
1353                 return status;
1354
1355         /* Enable high temperature failure and global fault alarms */
1356         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1357                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1358                                       &reg);
1359
1360         if (status != IXGBE_SUCCESS)
1361                 return status;
1362
1363         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
1364                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
1365
1366         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1367                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1368                                        reg);
1369
1370         if (status != IXGBE_SUCCESS)
1371                 return status;
1372
1373         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1374         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1375                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1376                                       &reg);
1377
1378         if (status != IXGBE_SUCCESS)
1379                 return status;
1380
1381         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1382                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1383
1384         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1385                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1386                                        reg);
1387
1388         if (status != IXGBE_SUCCESS)
1389                 return status;
1390
1391         /* Enable chip-wide vendor alarm */
1392         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1393                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1394                                       &reg);
1395
1396         if (status != IXGBE_SUCCESS)
1397                 return status;
1398
1399         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1400
1401         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1402                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1403                                        reg);
1404
1405         return status;
1406 }
1407
1408 /**
1409  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1410  *  @hw: pointer to hardware structure
1411  *  @speed: link speed
1412  *
1413  *  Configures the integrated KR PHY.
1414  **/
1415 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1416                                        ixgbe_link_speed speed)
1417 {
1418         s32 status;
1419         u32 reg_val;
1420
1421         status = ixgbe_read_iosf_sb_reg_x550(hw,
1422                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1423                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1424         if (status)
1425                 return status;
1426
1427         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1428         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1429                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1430
1431         /* Advertise 10G support. */
1432         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1433                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1434
1435         /* Advertise 1G support. */
1436         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1437                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1438
1439         /* Restart auto-negotiation. */
1440         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1441         status = ixgbe_write_iosf_sb_reg_x550(hw,
1442                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1443                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1444
1445         return status;
1446 }
1447
1448 /**
1449  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1450  *  @hw: pointer to hardware structure
1451  *
1452  *  Initialize any function pointers that were not able to be
1453  *  set during init_shared_code because the PHY/SFP type was
1454  *  not known.  Perform the SFP init if necessary.
1455  */
1456 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1457 {
1458         struct ixgbe_phy_info *phy = &hw->phy;
1459         s32 ret_val;
1460
1461         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1462
1463         hw->mac.ops.set_lan_id(hw);
1464
1465         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1466                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1467                 ixgbe_setup_mux_ctl(hw);
1468
1469                 /* Save NW management interface connected on board. This is used
1470                  * to determine internal PHY mode.
1471                  */
1472                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1473                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
1474         }
1475
1476         /* Identify the PHY or SFP module */
1477         ret_val = phy->ops.identify(hw);
1478         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1479                 return ret_val;
1480
1481         /* Setup function pointers based on detected hardware */
1482         ixgbe_init_mac_link_ops_X550em(hw);
1483         if (phy->sfp_type != ixgbe_sfp_type_unknown)
1484                 phy->ops.reset = NULL;
1485
1486         /* Set functions pointers based on phy type */
1487         switch (hw->phy.type) {
1488         case ixgbe_phy_x550em_kx4:
1489                 phy->ops.setup_link = NULL;
1490                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1491                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1492                 break;
1493         case ixgbe_phy_x550em_kr:
1494                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1495                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1496                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1497                 break;
1498         case ixgbe_phy_x550em_ext_t:
1499                 /* Save NW management interface connected on board. This is used
1500                  * to determine internal PHY mode
1501                  */
1502                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1503
1504                 /* If internal link mode is XFI, then setup iXFI internal link,
1505                  * else setup KR now.
1506                  */
1507                 phy->ops.setup_internal_link =
1508                                               ixgbe_setup_internal_phy_t_x550em;
1509
1510                 /* setup SW LPLU only for first revision */
1511                 if (!(IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw,
1512                                                        IXGBE_FUSES0_GROUP(0))))
1513                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1514
1515                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1516                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1517                 break;
1518         default:
1519                 break;
1520         }
1521         return ret_val;
1522 }
1523
1524 /**
1525  *  ixgbe_reset_hw_X550em - Perform hardware reset
1526  *  @hw: pointer to hardware structure
1527  *
1528  *  Resets the hardware by resetting the transmit and receive units, masks
1529  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1530  *  reset.
1531  */
1532 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1533 {
1534         ixgbe_link_speed link_speed;
1535         s32 status;
1536         u32 ctrl = 0;
1537         u32 i;
1538         u32 hlreg0;
1539         bool link_up = false;
1540
1541         DEBUGFUNC("ixgbe_reset_hw_X550em");
1542
1543         /* Call adapter stop to disable Tx/Rx and clear interrupts */
1544         status = hw->mac.ops.stop_adapter(hw);
1545         if (status != IXGBE_SUCCESS)
1546                 return status;
1547
1548         /* flush pending Tx transactions */
1549         ixgbe_clear_tx_pending(hw);
1550
1551         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
1552                 /* Config MDIO clock speed before the first MDIO PHY access */
1553                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1554                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
1555                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1556         }
1557
1558         /* PHY ops must be identified and initialized prior to reset */
1559         status = hw->phy.ops.init(hw);
1560
1561         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1562                 return status;
1563
1564         /* start the external PHY */
1565         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1566                 status = ixgbe_init_ext_t_x550em(hw);
1567                 if (status)
1568                         return status;
1569         }
1570
1571         /* Setup SFP module if there is one present. */
1572         if (hw->phy.sfp_setup_needed) {
1573                 status = hw->mac.ops.setup_sfp(hw);
1574                 hw->phy.sfp_setup_needed = false;
1575         }
1576
1577         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1578                 return status;
1579
1580         /* Reset PHY */
1581         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1582                 hw->phy.ops.reset(hw);
1583
1584 mac_reset_top:
1585         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1586          * If link reset is used when link is up, it might reset the PHY when
1587          * mng is using it.  If link is down or the flag to force full link
1588          * reset is set, then perform link reset.
1589          */
1590         ctrl = IXGBE_CTRL_LNK_RST;
1591         if (!hw->force_full_reset) {
1592                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1593                 if (link_up)
1594                         ctrl = IXGBE_CTRL_RST;
1595         }
1596
1597         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1598         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1599         IXGBE_WRITE_FLUSH(hw);
1600
1601         /* Poll for reset bit to self-clear meaning reset is complete */
1602         for (i = 0; i < 10; i++) {
1603                 usec_delay(1);
1604                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1605                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1606                         break;
1607         }
1608
1609         if (ctrl & IXGBE_CTRL_RST_MASK) {
1610                 status = IXGBE_ERR_RESET_FAILED;
1611                 DEBUGOUT("Reset polling failed to complete.\n");
1612         }
1613
1614         msec_delay(50);
1615
1616         /* Double resets are required for recovery from certain error
1617          * conditions.  Between resets, it is necessary to stall to
1618          * allow time for any pending HW events to complete.
1619          */
1620         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1621                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1622                 goto mac_reset_top;
1623         }
1624
1625         /* Store the permanent mac address */
1626         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1627
1628         /* Store MAC address from RAR0, clear receive address registers, and
1629          * clear the multicast table.  Also reset num_rar_entries to 128,
1630          * since we modify this value when programming the SAN MAC address.
1631          */
1632         hw->mac.num_rar_entries = 128;
1633         hw->mac.ops.init_rx_addrs(hw);
1634
1635         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1636                 ixgbe_setup_mux_ctl(hw);
1637
1638         return status;
1639 }
1640
1641 /**
1642  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1643  * @hw: pointer to hardware structure
1644  */
1645 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1646 {
1647         u32 status;
1648         u16 reg;
1649
1650         status = hw->phy.ops.read_reg(hw,
1651                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1652                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1653                                       &reg);
1654
1655         if (status != IXGBE_SUCCESS)
1656                 return status;
1657
1658         /* If PHY FW reset completed bit is set then this is the first
1659          * SW instance after a power on so the PHY FW must be un-stalled.
1660          */
1661         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1662                 status = hw->phy.ops.read_reg(hw,
1663                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1664                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1665                                         &reg);
1666
1667                 if (status != IXGBE_SUCCESS)
1668                         return status;
1669
1670                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1671
1672                 status = hw->phy.ops.write_reg(hw,
1673                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1674                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1675                                         reg);
1676
1677                 if (status != IXGBE_SUCCESS)
1678                         return status;
1679         }
1680
1681         return status;
1682 }
1683
1684 /**
1685  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1686  *  @hw: pointer to hardware structure
1687  *
1688  *  Configures the integrated KR PHY.
1689  **/
1690 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1691 {
1692         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
1693 }
1694
1695 /**
1696  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
1697  *  @hw: pointer to hardware structure
1698  *
1699  *  Configure the external PHY and the integrated KR PHY for SFP support.
1700  **/
1701 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1702                                     ixgbe_link_speed speed,
1703                                     bool autoneg_wait_to_complete)
1704 {
1705         s32 ret_val;
1706         u16 reg_slice, reg_val;
1707         bool setup_linear = false;
1708         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1709
1710         /* Check if SFP module is supported and linear */
1711         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1712
1713         /* If no SFP module present, then return success. Return success since
1714          * there is no reason to configure CS4227 and SFP not present error is
1715          * not excepted in the setup MAC link flow.
1716          */
1717         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1718                 return IXGBE_SUCCESS;
1719
1720         if (ret_val != IXGBE_SUCCESS)
1721                 return ret_val;
1722
1723         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1724                 /* Configure CS4227 LINE side to 10G SR. */
1725                 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
1726                             (hw->bus.lan_id << 12);
1727                 reg_val = IXGBE_CS4227_SPEED_10G;
1728                 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1729                                                    reg_val);
1730
1731                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
1732                             (hw->bus.lan_id << 12);
1733                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1734                 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1735                                                    reg_val);
1736
1737                 /* Configure CS4227 for HOST connection rate then type. */
1738                 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
1739                             (hw->bus.lan_id << 12);
1740                 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
1741                 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
1742                 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1743                                                    reg_val);
1744
1745                 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
1746                             (hw->bus.lan_id << 12);
1747                 if (setup_linear)
1748                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1749                 else
1750                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1751                 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1752                                                    reg_val);
1753
1754                 /* Setup XFI internal link. */
1755                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
1756         } else {
1757                 /* Configure internal PHY for KR/KX. */
1758                 ixgbe_setup_kr_speed_x550em(hw, speed);
1759
1760                 /* Configure CS4227 LINE side to proper mode. */
1761                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
1762                             (hw->bus.lan_id << 12);
1763                 if (setup_linear)
1764                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1765                 else
1766                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1767                 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1768                                                    reg_val);
1769         }
1770         return ret_val;
1771 }
1772
1773 /**
1774  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
1775  *  @hw: pointer to hardware structure
1776  *
1777  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
1778  **/
1779 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
1780 {
1781         s32 status;
1782         u32 reg_val;
1783
1784         /* Disable training protocol FSM. */
1785         status = ixgbe_read_iosf_sb_reg_x550(hw,
1786                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1787                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1788         if (status != IXGBE_SUCCESS)
1789                 return status;
1790         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1791         status = ixgbe_write_iosf_sb_reg_x550(hw,
1792                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1793                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1794         if (status != IXGBE_SUCCESS)
1795                 return status;
1796
1797         /* Disable Flex from training TXFFE. */
1798         status = ixgbe_read_iosf_sb_reg_x550(hw,
1799                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1800                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1801         if (status != IXGBE_SUCCESS)
1802                 return status;
1803         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1804         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1805         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1806         status = ixgbe_write_iosf_sb_reg_x550(hw,
1807                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1808                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1809         if (status != IXGBE_SUCCESS)
1810                 return status;
1811         status = ixgbe_read_iosf_sb_reg_x550(hw,
1812                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1813                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1814         if (status != IXGBE_SUCCESS)
1815                 return status;
1816         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1817         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1818         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1819         status = ixgbe_write_iosf_sb_reg_x550(hw,
1820                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1821                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1822         if (status != IXGBE_SUCCESS)
1823                 return status;
1824
1825         /* Enable override for coefficients. */
1826         status = ixgbe_read_iosf_sb_reg_x550(hw,
1827                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1828                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1829         if (status != IXGBE_SUCCESS)
1830                 return status;
1831         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1832         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1833         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1834         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1835         status = ixgbe_write_iosf_sb_reg_x550(hw,
1836                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1837                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1838         return status;
1839 }
1840
1841 /**
1842  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1843  *  @hw: pointer to hardware structure
1844  *  @speed: the link speed to force
1845  *
1846  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1847  *  internal and external PHY at a specific speed, without autonegotiation.
1848  **/
1849 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1850 {
1851         s32 status;
1852         u32 reg_val;
1853
1854         /* Disable AN and force speed to 10G Serial. */
1855         status = ixgbe_read_iosf_sb_reg_x550(hw,
1856                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1857                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1858         if (status != IXGBE_SUCCESS)
1859                 return status;
1860
1861         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1862         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1863
1864         /* Select forced link speed for internal PHY. */
1865         switch (*speed) {
1866         case IXGBE_LINK_SPEED_10GB_FULL:
1867                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1868                 break;
1869         case IXGBE_LINK_SPEED_1GB_FULL:
1870                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1871                 break;
1872         default:
1873                 /* Other link speeds are not supported by internal KR PHY. */
1874                 return IXGBE_ERR_LINK_SETUP;
1875         }
1876
1877         status = ixgbe_write_iosf_sb_reg_x550(hw,
1878                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1879                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1880         if (status != IXGBE_SUCCESS)
1881                 return status;
1882
1883         /* Additional configuration needed for x550em_x */
1884         if (hw->mac.type == ixgbe_mac_X550EM_x) {
1885                 status = ixgbe_setup_ixfi_x550em_x(hw);
1886                 if (status != IXGBE_SUCCESS)
1887                         return status;
1888         }
1889
1890         /* Toggle port SW reset by AN reset. */
1891         status = ixgbe_read_iosf_sb_reg_x550(hw,
1892                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1893                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1894         if (status != IXGBE_SUCCESS)
1895                 return status;
1896         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1897         status = ixgbe_write_iosf_sb_reg_x550(hw,
1898                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1899                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1900
1901         return status;
1902 }
1903
1904 /**
1905  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
1906  * @hw: address of hardware structure
1907  * @link_up: address of boolean to indicate link status
1908  *
1909  * Returns error code if unable to get link status.
1910  */
1911 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
1912 {
1913         u32 ret;
1914         u16 autoneg_status;
1915
1916         *link_up = false;
1917
1918         /* read this twice back to back to indicate current status */
1919         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1920                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1921                                    &autoneg_status);
1922         if (ret != IXGBE_SUCCESS)
1923                 return ret;
1924
1925         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1926                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1927                                    &autoneg_status);
1928         if (ret != IXGBE_SUCCESS)
1929                 return ret;
1930
1931         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
1932
1933         return IXGBE_SUCCESS;
1934 }
1935
1936 /**
1937  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1938  * @hw: point to hardware structure
1939  *
1940  * Configures the link between the integrated KR PHY and the external X557 PHY
1941  * The driver will call this function when it gets a link status change
1942  * interrupt from the X557 PHY. This function configures the link speed
1943  * between the PHYs to match the link speed of the BASE-T link.
1944  *
1945  * A return of a non-zero value indicates an error, and the base driver should
1946  * not report link up.
1947  */
1948 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
1949 {
1950         ixgbe_link_speed force_speed;
1951         bool link_up;
1952         u32 status;
1953         u16 speed;
1954
1955         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1956                 return IXGBE_ERR_CONFIG;
1957
1958         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1959                 /* If link is down, there is no setup necessary so return  */
1960                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1961                 if (status != IXGBE_SUCCESS)
1962                         return status;
1963
1964                 if (!link_up)
1965                         return IXGBE_SUCCESS;
1966
1967                 status = hw->phy.ops.read_reg(hw,
1968                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1969                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1970                                               &speed);
1971                 if (status != IXGBE_SUCCESS)
1972                         return status;
1973
1974                 /* If link is still down - no setup is required so return */
1975                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1976                 if (status != IXGBE_SUCCESS)
1977                         return status;
1978                 if (!link_up)
1979                         return IXGBE_SUCCESS;
1980
1981                 /* clear everything but the speed and duplex bits */
1982                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1983
1984                 switch (speed) {
1985                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1986                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1987                         break;
1988                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1989                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1990                         break;
1991                 default:
1992                         /* Internal PHY does not support anything else */
1993                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
1994                 }
1995
1996                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1997         } else {
1998                 speed = IXGBE_LINK_SPEED_10GB_FULL |
1999                         IXGBE_LINK_SPEED_1GB_FULL;
2000                 return ixgbe_setup_kr_speed_x550em(hw, speed);
2001         }
2002 }
2003
2004 /**
2005  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
2006  *  @hw: pointer to hardware structure
2007  *
2008  *  Configures the integrated KR PHY to use internal loopback mode.
2009  **/
2010 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
2011 {
2012         s32 status;
2013         u32 reg_val;
2014
2015         /* Disable AN and force speed to 10G Serial. */
2016         status = ixgbe_read_iosf_sb_reg_x550(hw,
2017                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2018                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2019         if (status != IXGBE_SUCCESS)
2020                 return status;
2021         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2022         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2023         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2024         status = ixgbe_write_iosf_sb_reg_x550(hw,
2025                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2026                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2027         if (status != IXGBE_SUCCESS)
2028                 return status;
2029
2030         /* Set near-end loopback clocks. */
2031         status = ixgbe_read_iosf_sb_reg_x550(hw,
2032                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2033                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2034         if (status != IXGBE_SUCCESS)
2035                 return status;
2036         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2037         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2038         status = ixgbe_write_iosf_sb_reg_x550(hw,
2039                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2040                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2041         if (status != IXGBE_SUCCESS)
2042                 return status;
2043
2044         /* Set loopback enable. */
2045         status = ixgbe_read_iosf_sb_reg_x550(hw,
2046                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2047                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2048         if (status != IXGBE_SUCCESS)
2049                 return status;
2050         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2051         status = ixgbe_write_iosf_sb_reg_x550(hw,
2052                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2053                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2054         if (status != IXGBE_SUCCESS)
2055                 return status;
2056
2057         /* Training bypass. */
2058         status = ixgbe_read_iosf_sb_reg_x550(hw,
2059                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2060                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2061         if (status != IXGBE_SUCCESS)
2062                 return status;
2063         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2064         status = ixgbe_write_iosf_sb_reg_x550(hw,
2065                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2066                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2067
2068         return status;
2069 }
2070
2071 /**
2072  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2073  *  assuming that the semaphore is already obtained.
2074  *  @hw: pointer to hardware structure
2075  *  @offset: offset of  word in the EEPROM to read
2076  *  @data: word read from the EEPROM
2077  *
2078  *  Reads a 16 bit word from the EEPROM using the hostif.
2079  **/
2080 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2081                                    u16 *data)
2082 {
2083         s32 status;
2084         struct ixgbe_hic_read_shadow_ram buffer;
2085
2086         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2087         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2088         buffer.hdr.req.buf_lenh = 0;
2089         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2090         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2091
2092         /* convert offset from words to bytes */
2093         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2094         /* one word */
2095         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2096
2097         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2098                                               sizeof(buffer),
2099                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2100
2101         if (status)
2102                 return status;
2103
2104         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2105                                           FW_NVM_DATA_OFFSET);
2106
2107         return 0;
2108 }
2109
2110 /**
2111  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2112  *  @hw: pointer to hardware structure
2113  *  @offset: offset of  word in the EEPROM to read
2114  *  @data: word read from the EEPROM
2115  *
2116  *  Reads a 16 bit word from the EEPROM using the hostif.
2117  **/
2118 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2119                               u16 *data)
2120 {
2121         s32 status = IXGBE_SUCCESS;
2122
2123         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2124
2125         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2126             IXGBE_SUCCESS) {
2127                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2128                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2129         } else {
2130                 status = IXGBE_ERR_SWFW_SYNC;
2131         }
2132
2133         return status;
2134 }
2135
2136 /**
2137  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2138  *  @hw: pointer to hardware structure
2139  *  @offset: offset of  word in the EEPROM to read
2140  *  @words: number of words
2141  *  @data: word(s) read from the EEPROM
2142  *
2143  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
2144  **/
2145 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2146                                      u16 offset, u16 words, u16 *data)
2147 {
2148         struct ixgbe_hic_read_shadow_ram buffer;
2149         u32 current_word = 0;
2150         u16 words_to_read;
2151         s32 status;
2152         u32 i;
2153
2154         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2155
2156         /* Take semaphore for the entire operation. */
2157         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2158         if (status) {
2159                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2160                 return status;
2161         }
2162         while (words) {
2163                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2164                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2165                 else
2166                         words_to_read = words;
2167
2168                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2169                 buffer.hdr.req.buf_lenh = 0;
2170                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2171                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2172
2173                 /* convert offset from words to bytes */
2174                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2175                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2176
2177                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2178                                                       sizeof(buffer),
2179                                                       IXGBE_HI_COMMAND_TIMEOUT,
2180                                                       false);
2181
2182                 if (status) {
2183                         DEBUGOUT("Host interface command failed\n");
2184                         goto out;
2185                 }
2186
2187                 for (i = 0; i < words_to_read; i++) {
2188                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
2189                                   2 * i;
2190                         u32 value = IXGBE_READ_REG(hw, reg);
2191
2192                         data[current_word] = (u16)(value & 0xffff);
2193                         current_word++;
2194                         i++;
2195                         if (i < words_to_read) {
2196                                 value >>= 16;
2197                                 data[current_word] = (u16)(value & 0xffff);
2198                                 current_word++;
2199                         }
2200                 }
2201                 words -= words_to_read;
2202         }
2203
2204 out:
2205         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2206         return status;
2207 }
2208
2209 /**
2210  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2211  *  @hw: pointer to hardware structure
2212  *  @offset: offset of  word in the EEPROM to write
2213  *  @data: word write to the EEPROM
2214  *
2215  *  Write a 16 bit word to the EEPROM using the hostif.
2216  **/
2217 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2218                                     u16 data)
2219 {
2220         s32 status;
2221         struct ixgbe_hic_write_shadow_ram buffer;
2222
2223         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
2224
2225         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
2226         buffer.hdr.req.buf_lenh = 0;
2227         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
2228         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2229
2230          /* one word */
2231         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2232         buffer.data = data;
2233         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2234
2235         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2236                                               sizeof(buffer),
2237                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2238
2239         return status;
2240 }
2241
2242 /**
2243  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2244  *  @hw: pointer to hardware structure
2245  *  @offset: offset of  word in the EEPROM to write
2246  *  @data: word write to the EEPROM
2247  *
2248  *  Write a 16 bit word to the EEPROM using the hostif.
2249  **/
2250 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2251                                u16 data)
2252 {
2253         s32 status = IXGBE_SUCCESS;
2254
2255         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2256
2257         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2258             IXGBE_SUCCESS) {
2259                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2260                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2261         } else {
2262                 DEBUGOUT("write ee hostif failed to get semaphore");
2263                 status = IXGBE_ERR_SWFW_SYNC;
2264         }
2265
2266         return status;
2267 }
2268
2269 /**
2270  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2271  *  @hw: pointer to hardware structure
2272  *  @offset: offset of  word in the EEPROM to write
2273  *  @words: number of words
2274  *  @data: word(s) write to the EEPROM
2275  *
2276  *  Write a 16 bit word(s) to the EEPROM using the hostif.
2277  **/
2278 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2279                                       u16 offset, u16 words, u16 *data)
2280 {
2281         s32 status = IXGBE_SUCCESS;
2282         u32 i = 0;
2283
2284         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2285
2286         /* Take semaphore for the entire operation. */
2287         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2288         if (status != IXGBE_SUCCESS) {
2289                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2290                 goto out;
2291         }
2292
2293         for (i = 0; i < words; i++) {
2294                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2295                                                          data[i]);
2296
2297                 if (status != IXGBE_SUCCESS) {
2298                         DEBUGOUT("Eeprom buffered write failed\n");
2299                         break;
2300                 }
2301         }
2302
2303         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2304 out:
2305
2306         return status;
2307 }
2308
2309 /**
2310  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2311  * @hw: pointer to hardware structure
2312  * @ptr: pointer offset in eeprom
2313  * @size: size of section pointed by ptr, if 0 first word will be used as size
2314  * @csum: address of checksum to update
2315  *
2316  * Returns error status for any failure
2317  */
2318 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2319                                    u16 size, u16 *csum, u16 *buffer,
2320                                    u32 buffer_size)
2321 {
2322         u16 buf[256];
2323         s32 status;
2324         u16 length, bufsz, i, start;
2325         u16 *local_buffer;
2326
2327         bufsz = sizeof(buf) / sizeof(buf[0]);
2328
2329         /* Read a chunk at the pointer location */
2330         if (!buffer) {
2331                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2332                 if (status) {
2333                         DEBUGOUT("Failed to read EEPROM image\n");
2334                         return status;
2335                 }
2336                 local_buffer = buf;
2337         } else {
2338                 if (buffer_size < ptr)
2339                         return  IXGBE_ERR_PARAM;
2340                 local_buffer = &buffer[ptr];
2341         }
2342
2343         if (size) {
2344                 start = 0;
2345                 length = size;
2346         } else {
2347                 start = 1;
2348                 length = local_buffer[0];
2349
2350                 /* Skip pointer section if length is invalid. */
2351                 if (length == 0xFFFF || length == 0 ||
2352                     (ptr + length) >= hw->eeprom.word_size)
2353                         return IXGBE_SUCCESS;
2354         }
2355
2356         if (buffer && ((u32)start + (u32)length > buffer_size))
2357                 return IXGBE_ERR_PARAM;
2358
2359         for (i = start; length; i++, length--) {
2360                 if (i == bufsz && !buffer) {
2361                         ptr += bufsz;
2362                         i = 0;
2363                         if (length < bufsz)
2364                                 bufsz = length;
2365
2366                         /* Read a chunk at the pointer location */
2367                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2368                                                                   bufsz, buf);
2369                         if (status) {
2370                                 DEBUGOUT("Failed to read EEPROM image\n");
2371                                 return status;
2372                         }
2373                 }
2374                 *csum += local_buffer[i];
2375         }
2376         return IXGBE_SUCCESS;
2377 }
2378
2379 /**
2380  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2381  *  @hw: pointer to hardware structure
2382  *  @buffer: pointer to buffer containing calculated checksum
2383  *  @buffer_size: size of buffer
2384  *
2385  *  Returns a negative error code on error, or the 16-bit checksum
2386  **/
2387 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2388 {
2389         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2390         u16 *local_buffer;
2391         s32 status;
2392         u16 checksum = 0;
2393         u16 pointer, i, size;
2394
2395         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2396
2397         hw->eeprom.ops.init_params(hw);
2398
2399         if (!buffer) {
2400                 /* Read pointer area */
2401                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2402                                                      IXGBE_EEPROM_LAST_WORD + 1,
2403                                                      eeprom_ptrs);
2404                 if (status) {
2405                         DEBUGOUT("Failed to read EEPROM image\n");
2406                         return status;
2407                 }
2408                 local_buffer = eeprom_ptrs;
2409         } else {
2410                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2411                         return IXGBE_ERR_PARAM;
2412                 local_buffer = buffer;
2413         }
2414
2415         /*
2416          * For X550 hardware include 0x0-0x41 in the checksum, skip the
2417          * checksum word itself
2418          */
2419         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2420                 if (i != IXGBE_EEPROM_CHECKSUM)
2421                         checksum += local_buffer[i];
2422
2423         /*
2424          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
2425          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2426          */
2427         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2428                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2429                         continue;
2430
2431                 pointer = local_buffer[i];
2432
2433                 /* Skip pointer section if the pointer is invalid. */
2434                 if (pointer == 0xFFFF || pointer == 0 ||
2435                     pointer >= hw->eeprom.word_size)
2436                         continue;
2437
2438                 switch (i) {
2439                 case IXGBE_PCIE_GENERAL_PTR:
2440                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2441                         break;
2442                 case IXGBE_PCIE_CONFIG0_PTR:
2443                 case IXGBE_PCIE_CONFIG1_PTR:
2444                         size = IXGBE_PCIE_CONFIG_SIZE;
2445                         break;
2446                 default:
2447                         size = 0;
2448                         break;
2449                 }
2450
2451                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2452                                                 buffer, buffer_size);
2453                 if (status)
2454                         return status;
2455         }
2456
2457         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2458
2459         return (s32)checksum;
2460 }
2461
2462 /**
2463  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2464  *  @hw: pointer to hardware structure
2465  *
2466  *  Returns a negative error code on error, or the 16-bit checksum
2467  **/
2468 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2469 {
2470         return ixgbe_calc_checksum_X550(hw, NULL, 0);
2471 }
2472
2473 /**
2474  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2475  *  @hw: pointer to hardware structure
2476  *  @checksum_val: calculated checksum
2477  *
2478  *  Performs checksum calculation and validates the EEPROM checksum.  If the
2479  *  caller does not need checksum_val, the value can be NULL.
2480  **/
2481 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2482 {
2483         s32 status;
2484         u16 checksum;
2485         u16 read_checksum = 0;
2486
2487         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2488
2489         /* Read the first word from the EEPROM. If this times out or fails, do
2490          * not continue or we could be in for a very long wait while every
2491          * EEPROM read fails
2492          */
2493         status = hw->eeprom.ops.read(hw, 0, &checksum);
2494         if (status) {
2495                 DEBUGOUT("EEPROM read failed\n");
2496                 return status;
2497         }
2498
2499         status = hw->eeprom.ops.calc_checksum(hw);
2500         if (status < 0)
2501                 return status;
2502
2503         checksum = (u16)(status & 0xffff);
2504
2505         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2506                                            &read_checksum);
2507         if (status)
2508                 return status;
2509
2510         /* Verify read checksum from EEPROM is the same as
2511          * calculated checksum
2512          */
2513         if (read_checksum != checksum) {
2514                 status = IXGBE_ERR_EEPROM_CHECKSUM;
2515                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2516                              "Invalid EEPROM checksum");
2517         }
2518
2519         /* If the user cares, return the calculated checksum */
2520         if (checksum_val)
2521                 *checksum_val = checksum;
2522
2523         return status;
2524 }
2525
2526 /**
2527  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2528  * @hw: pointer to hardware structure
2529  *
2530  * After writing EEPROM to shadow RAM using EEWR register, software calculates
2531  * checksum and updates the EEPROM and instructs the hardware to update
2532  * the flash.
2533  **/
2534 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2535 {
2536         s32 status;
2537         u16 checksum = 0;
2538
2539         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2540
2541         /* Read the first word from the EEPROM. If this times out or fails, do
2542          * not continue or we could be in for a very long wait while every
2543          * EEPROM read fails
2544          */
2545         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2546         if (status) {
2547                 DEBUGOUT("EEPROM read failed\n");
2548                 return status;
2549         }
2550
2551         status = ixgbe_calc_eeprom_checksum_X550(hw);
2552         if (status < 0)
2553                 return status;
2554
2555         checksum = (u16)(status & 0xffff);
2556
2557         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2558                                             checksum);
2559         if (status)
2560                 return status;
2561
2562         status = ixgbe_update_flash_X550(hw);
2563
2564         return status;
2565 }
2566
2567 /**
2568  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2569  *  @hw: pointer to hardware structure
2570  *
2571  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2572  **/
2573 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2574 {
2575         s32 status = IXGBE_SUCCESS;
2576         union ixgbe_hic_hdr2 buffer;
2577
2578         DEBUGFUNC("ixgbe_update_flash_X550");
2579
2580         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2581         buffer.req.buf_lenh = 0;
2582         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2583         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2584
2585         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2586                                               sizeof(buffer),
2587                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2588
2589         return status;
2590 }
2591
2592 /**
2593  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2594  *  @hw: pointer to hardware structure
2595  *
2596  *  Determines physical layer capabilities of the current configuration.
2597  **/
2598 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2599 {
2600         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2601         u16 ext_ability = 0;
2602
2603         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2604
2605         hw->phy.ops.identify(hw);
2606
2607         switch (hw->phy.type) {
2608         case ixgbe_phy_x550em_kr:
2609                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2610                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2611                 break;
2612         case ixgbe_phy_x550em_kx4:
2613                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2614                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2615                 break;
2616         case ixgbe_phy_x550em_ext_t:
2617                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2618                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2619                                      &ext_ability);
2620                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2621                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2622                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2623                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2624                 break;
2625         default:
2626                 break;
2627         }
2628
2629         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2630                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2631
2632         return physical_layer;
2633 }
2634
2635 /**
2636  * ixgbe_get_bus_info_x550em - Set PCI bus info
2637  * @hw: pointer to hardware structure
2638  *
2639  * Sets bus link width and speed to unknown because X550em is
2640  * not a PCI device.
2641  **/
2642 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2643 {
2644
2645         DEBUGFUNC("ixgbe_get_bus_info_x550em");
2646
2647         hw->bus.width = ixgbe_bus_width_unknown;
2648         hw->bus.speed = ixgbe_bus_speed_unknown;
2649
2650         hw->mac.ops.set_lan_id(hw);
2651
2652         return IXGBE_SUCCESS;
2653 }
2654
2655 /**
2656  * ixgbe_disable_rx_x550 - Disable RX unit
2657  *
2658  * Enables the Rx DMA unit for x550
2659  **/
2660 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2661 {
2662         u32 rxctrl, pfdtxgswc;
2663         s32 status;
2664         struct ixgbe_hic_disable_rxen fw_cmd;
2665
2666         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2667
2668         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2669         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2670                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2671                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2672                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2673                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2674                         hw->mac.set_lben = true;
2675                 } else {
2676                         hw->mac.set_lben = false;
2677                 }
2678
2679                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2680                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2681                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2682                 fw_cmd.port_number = (u8)hw->bus.lan_id;
2683
2684                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2685                                         sizeof(struct ixgbe_hic_disable_rxen),
2686                                         IXGBE_HI_COMMAND_TIMEOUT, true);
2687
2688                 /* If we fail - disable RX using register write */
2689                 if (status) {
2690                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2691                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2692                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2693                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2694                         }
2695                 }
2696         }
2697 }
2698
2699 /**
2700  * ixgbe_enter_lplu_x550em - Transition to low power states
2701  *  @hw: pointer to hardware structure
2702  *
2703  * Configures Low Power Link Up on transition to low power states
2704  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2705  * X557 PHY immediately prior to entering LPLU.
2706  **/
2707 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2708 {
2709         u16 an_10g_cntl_reg, autoneg_reg, speed;
2710         s32 status;
2711         ixgbe_link_speed lcd_speed;
2712         u32 save_autoneg;
2713         bool link_up;
2714
2715         /* SW LPLU not required on later HW revisions. */
2716         if (IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)))
2717                 return IXGBE_SUCCESS;
2718
2719         /* If blocked by MNG FW, then don't restart AN */
2720         if (ixgbe_check_reset_blocked(hw))
2721                 return IXGBE_SUCCESS;
2722
2723         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2724         if (status != IXGBE_SUCCESS)
2725                 return status;
2726
2727         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2728
2729         if (status != IXGBE_SUCCESS)
2730                 return status;
2731
2732         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2733          * disabled, then force link down by entering low power mode.
2734          */
2735         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2736             !(hw->wol_enabled || ixgbe_mng_present(hw)))
2737                 return ixgbe_set_copper_phy_power(hw, FALSE);
2738
2739         /* Determine LCD */
2740         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2741
2742         if (status != IXGBE_SUCCESS)
2743                 return status;
2744
2745         /* If no valid LCD link speed, then force link down and exit. */
2746         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2747                 return ixgbe_set_copper_phy_power(hw, FALSE);
2748
2749         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2750                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2751                                       &speed);
2752
2753         if (status != IXGBE_SUCCESS)
2754                 return status;
2755
2756         /* If no link now, speed is invalid so take link down */
2757         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2758         if (status != IXGBE_SUCCESS)
2759                 return ixgbe_set_copper_phy_power(hw, false);
2760
2761         /* clear everything but the speed bits */
2762         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2763
2764         /* If current speed is already LCD, then exit. */
2765         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2766              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2767             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2768              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2769                 return status;
2770
2771         /* Clear AN completed indication */
2772         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2773                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2774                                       &autoneg_reg);
2775
2776         if (status != IXGBE_SUCCESS)
2777                 return status;
2778
2779         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2780                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2781                              &an_10g_cntl_reg);
2782
2783         if (status != IXGBE_SUCCESS)
2784                 return status;
2785
2786         status = hw->phy.ops.read_reg(hw,
2787                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2788                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2789                              &autoneg_reg);
2790
2791         if (status != IXGBE_SUCCESS)
2792                 return status;
2793
2794         save_autoneg = hw->phy.autoneg_advertised;
2795
2796         /* Setup link at least common link speed */
2797         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
2798
2799         /* restore autoneg from before setting lplu speed */
2800         hw->phy.autoneg_advertised = save_autoneg;
2801
2802         return status;
2803 }
2804
2805 /**
2806  * ixgbe_get_lcd_x550em - Determine lowest common denominator
2807  *  @hw: pointer to hardware structure
2808  *  @lcd_speed: pointer to lowest common link speed
2809  *
2810  * Determine lowest common link speed with link partner.
2811  **/
2812 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2813 {
2814         u16 an_lp_status;
2815         s32 status;
2816         u16 word = hw->eeprom.ctrl_word_3;
2817
2818         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2819
2820         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2821                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2822                                       &an_lp_status);
2823
2824         if (status != IXGBE_SUCCESS)
2825                 return status;
2826
2827         /* If link partner advertised 1G, return 1G */
2828         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2829                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2830                 return status;
2831         }
2832
2833         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2834         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2835             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2836                 return status;
2837
2838         /* Link partner not capable of lower speeds, return 10G */
2839         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2840         return status;
2841 }
2842
2843 /**
2844  *  ixgbe_setup_fc_X550em - Set up flow control
2845  *  @hw: pointer to hardware structure
2846  *
2847  *  Called at init time to set up flow control.
2848  **/
2849 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
2850 {
2851         s32 ret_val = IXGBE_SUCCESS;
2852         u32 pause, asm_dir, reg_val;
2853
2854         DEBUGFUNC("ixgbe_setup_fc_X550em");
2855
2856         /* Validate the requested mode */
2857         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2858                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2859                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2860                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2861                 goto out;
2862         }
2863
2864         /* 10gig parts do not have a word in the EEPROM to determine the
2865          * default flow control setting, so we explicitly set it to full.
2866          */
2867         if (hw->fc.requested_mode == ixgbe_fc_default)
2868                 hw->fc.requested_mode = ixgbe_fc_full;
2869
2870         /* Determine PAUSE and ASM_DIR bits. */
2871         switch (hw->fc.requested_mode) {
2872         case ixgbe_fc_none:
2873                 pause = 0;
2874                 asm_dir = 0;
2875                 break;
2876         case ixgbe_fc_tx_pause:
2877                 pause = 0;
2878                 asm_dir = 1;
2879                 break;
2880         case ixgbe_fc_rx_pause:
2881                 /* Rx Flow control is enabled and Tx Flow control is
2882                  * disabled by software override. Since there really
2883                  * isn't a way to advertise that we are capable of RX
2884                  * Pause ONLY, we will advertise that we support both
2885                  * symmetric and asymmetric Rx PAUSE, as such we fall
2886                  * through to the fc_full statement.  Later, we will
2887                  * disable the adapter's ability to send PAUSE frames.
2888                  */
2889         case ixgbe_fc_full:
2890                 pause = 1;
2891                 asm_dir = 1;
2892                 break;
2893         default:
2894                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2895                         "Flow control param set incorrectly\n");
2896                 ret_val = IXGBE_ERR_CONFIG;
2897                 goto out;
2898         }
2899
2900         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
2901                 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
2902                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2903                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2904                 if (ret_val != IXGBE_SUCCESS)
2905                         goto out;
2906                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2907                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2908                 if (pause)
2909                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2910                 if (asm_dir)
2911                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2912                 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
2913                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2914                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2915
2916                 /* This device does not fully support AN. */
2917                 hw->fc.disable_fc_autoneg = true;
2918         }
2919
2920 out:
2921         return ret_val;
2922 }
2923
2924 /**
2925  * ixgbe_set_mux - Set mux for port 1 access with CS4227
2926  * @hw: pointer to hardware structure
2927  * @state: set mux if 1, clear if 0
2928  */
2929 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2930 {
2931         u32 esdp;
2932
2933         if (!hw->bus.lan_id)
2934                 return;
2935         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2936         if (state)
2937                 esdp |= IXGBE_ESDP_SDP1;
2938         else
2939                 esdp &= ~IXGBE_ESDP_SDP1;
2940         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2941         IXGBE_WRITE_FLUSH(hw);
2942 }
2943
2944 /**
2945  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2946  *  @hw: pointer to hardware structure
2947  *  @mask: Mask to specify which semaphore to acquire
2948  *
2949  *  Acquires the SWFW semaphore and sets the I2C MUX
2950  **/
2951 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2952 {
2953         s32 status;
2954
2955         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
2956
2957         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2958         if (status)
2959                 return status;
2960
2961         if (mask & IXGBE_GSSR_I2C_MASK)
2962                 ixgbe_set_mux(hw, 1);
2963
2964         return IXGBE_SUCCESS;
2965 }
2966
2967 /**
2968  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2969  *  @hw: pointer to hardware structure
2970  *  @mask: Mask to specify which semaphore to release
2971  *
2972  *  Releases the SWFW semaphore and sets the I2C MUX
2973  **/
2974 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2975 {
2976         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
2977
2978         if (mask & IXGBE_GSSR_I2C_MASK)
2979                 ixgbe_set_mux(hw, 0);
2980
2981         ixgbe_release_swfw_sync_X540(hw, mask);
2982 }
2983
2984 /**
2985  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2986  * @hw: pointer to hardware structure
2987  *
2988  * Handle external Base T PHY interrupt. If high temperature
2989  * failure alarm then return error, else if link status change
2990  * then setup internal/external PHY link
2991  *
2992  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2993  * failure alarm, else return PHY access status.
2994  */
2995 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2996 {
2997         bool lsc;
2998         u32 status;
2999
3000         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
3001
3002         if (status != IXGBE_SUCCESS)
3003                 return status;
3004
3005         if (lsc)
3006                 return ixgbe_setup_internal_phy(hw);
3007
3008         return IXGBE_SUCCESS;
3009 }
3010
3011 /**
3012  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
3013  * @hw: pointer to hardware structure
3014  * @speed: new link speed
3015  * @autoneg_wait_to_complete: true when waiting for completion is needed
3016  *
3017  * Setup internal/external PHY link speed based on link speed, then set
3018  * external PHY auto advertised link speed.
3019  *
3020  * Returns error status for any failure
3021  **/
3022 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
3023                                   ixgbe_link_speed speed,
3024                                   bool autoneg_wait_to_complete)
3025 {
3026         s32 status;
3027         ixgbe_link_speed force_speed;
3028
3029         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
3030
3031         /* Setup internal/external PHY link speed to iXFI (10G), unless
3032          * only 1G is auto advertised then setup KX link.
3033          */
3034         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
3035                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3036         else
3037                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3038
3039         /* If internal link mode is XFI, then setup XFI internal link. */
3040         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3041                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
3042
3043                 if (status != IXGBE_SUCCESS)
3044                         return status;
3045         }
3046
3047         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
3048 }
3049
3050 /**
3051  * ixgbe_check_link_t_X550em - Determine link and speed status
3052  * @hw: pointer to hardware structure
3053  * @speed: pointer to link speed
3054  * @link_up: true when link is up
3055  * @link_up_wait_to_complete: bool used to wait for link up or not
3056  *
3057  * Check that both the MAC and X557 external PHY have link.
3058  **/
3059 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3060                               bool *link_up, bool link_up_wait_to_complete)
3061 {
3062         u32 status;
3063         u16 autoneg_status;
3064
3065         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3066                 return IXGBE_ERR_CONFIG;
3067
3068         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
3069                                               link_up_wait_to_complete);
3070
3071         /* If check link fails or MAC link is not up, then return */
3072         if (status != IXGBE_SUCCESS || !(*link_up))
3073                 return status;
3074
3075         /* MAC link is up, so check external PHY link.
3076          * Read this twice back to back to indicate current status.
3077          */
3078         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3079                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3080                                       &autoneg_status);
3081
3082         if (status != IXGBE_SUCCESS)
3083                 return status;
3084
3085         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3086                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3087                                       &autoneg_status);
3088
3089         if (status != IXGBE_SUCCESS)
3090                 return status;
3091
3092         /* If external PHY link is not up, then indicate link not up */
3093         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
3094                 *link_up = false;
3095
3096         return IXGBE_SUCCESS;
3097 }
3098
3099 /**
3100  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
3101  *  @hw: pointer to hardware structure
3102  **/
3103 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
3104 {
3105         s32 status;
3106
3107         status = ixgbe_reset_phy_generic(hw);
3108
3109         if (status != IXGBE_SUCCESS)
3110                 return status;
3111
3112         /* Configure Link Status Alarm and Temperature Threshold interrupts */
3113         return ixgbe_enable_lasi_ext_t_x550em(hw);
3114 }
3115
3116 /**
3117  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
3118  *  @hw: pointer to hardware structure
3119  *  @led_idx: led number to turn on
3120  **/
3121 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3122 {
3123         u16 phy_data;
3124
3125         DEBUGFUNC("ixgbe_led_on_t_X550em");
3126
3127         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3128                 return IXGBE_ERR_PARAM;
3129
3130         /* To turn on the LED, set mode to ON. */
3131         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3132                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3133         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
3134         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3135                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3136
3137         return IXGBE_SUCCESS;
3138 }
3139
3140 /**
3141  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
3142  *  @hw: pointer to hardware structure
3143  *  @led_idx: led number to turn off
3144  **/
3145 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3146 {
3147         u16 phy_data;
3148
3149         DEBUGFUNC("ixgbe_led_off_t_X550em");
3150
3151         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3152                 return IXGBE_ERR_PARAM;
3153
3154         /* To turn on the LED, set mode to ON. */
3155         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3156                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3157         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
3158         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3159                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3160
3161         return IXGBE_SUCCESS;
3162 }
3163