1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
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16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
44 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw);
47 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
48 * @hw: pointer to hardware structure
50 * Initialize the function pointers and assign the MAC type for X550.
51 * Does not touch the hardware.
53 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
55 struct ixgbe_mac_info *mac = &hw->mac;
56 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
59 DEBUGFUNC("ixgbe_init_ops_X550");
61 ret_val = ixgbe_init_ops_X540(hw);
62 mac->ops.dmac_config = ixgbe_dmac_config_X550;
63 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
64 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
65 mac->ops.setup_eee = ixgbe_setup_eee_X550;
66 mac->ops.set_source_address_pruning =
67 ixgbe_set_source_address_pruning_X550;
68 mac->ops.set_ethertype_anti_spoofing =
69 ixgbe_set_ethertype_anti_spoofing_X550;
71 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
72 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
73 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
74 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
75 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
76 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
77 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
78 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
79 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
81 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
82 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
83 mac->ops.mdd_event = ixgbe_mdd_event_X550;
84 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
85 mac->ops.disable_rx = ixgbe_disable_rx_x550;
86 switch (hw->device_id) {
87 case IXGBE_DEV_ID_X550EM_X_10G_T:
88 case IXGBE_DEV_ID_X550EM_A_10G_T:
89 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
90 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
99 * ixgbe_read_cs4227 - Read CS4227 register
100 * @hw: pointer to hardware structure
101 * @reg: register number to write
102 * @value: pointer to receive value read
104 * Returns status code
106 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
108 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
112 * ixgbe_write_cs4227 - Write CS4227 register
113 * @hw: pointer to hardware structure
114 * @reg: register number to write
115 * @value: value to write to register
117 * Returns status code
119 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
121 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
125 * ixgbe_read_pe - Read register from port expander
126 * @hw: pointer to hardware structure
127 * @reg: register number to read
128 * @value: pointer to receive read value
130 * Returns status code
132 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
136 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
137 if (status != IXGBE_SUCCESS)
138 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
139 "port expander access failed with %d\n", status);
144 * ixgbe_write_pe - Write register to port expander
145 * @hw: pointer to hardware structure
146 * @reg: register number to write
147 * @value: value to write
149 * Returns status code
151 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
155 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
156 if (status != IXGBE_SUCCESS)
157 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
158 "port expander access failed with %d\n", status);
163 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
164 * @hw: pointer to hardware structure
166 * This function assumes that the caller has acquired the proper semaphore.
169 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
176 /* Trigger hard reset. */
177 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
178 if (status != IXGBE_SUCCESS)
180 reg |= IXGBE_PE_BIT1;
181 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
182 if (status != IXGBE_SUCCESS)
185 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
186 if (status != IXGBE_SUCCESS)
188 reg &= ~IXGBE_PE_BIT1;
189 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
190 if (status != IXGBE_SUCCESS)
193 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
194 if (status != IXGBE_SUCCESS)
196 reg &= ~IXGBE_PE_BIT1;
197 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
198 if (status != IXGBE_SUCCESS)
201 usec_delay(IXGBE_CS4227_RESET_HOLD);
203 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
204 if (status != IXGBE_SUCCESS)
206 reg |= IXGBE_PE_BIT1;
207 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
208 if (status != IXGBE_SUCCESS)
211 /* Wait for the reset to complete. */
212 msec_delay(IXGBE_CS4227_RESET_DELAY);
213 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
214 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
216 if (status == IXGBE_SUCCESS &&
217 value == IXGBE_CS4227_EEPROM_LOAD_OK)
219 msec_delay(IXGBE_CS4227_CHECK_DELAY);
221 if (retry == IXGBE_CS4227_RETRIES) {
222 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
223 "CS4227 reset did not complete.");
224 return IXGBE_ERR_PHY;
227 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
228 if (status != IXGBE_SUCCESS ||
229 !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
230 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
231 "CS4227 EEPROM did not load successfully.");
232 return IXGBE_ERR_PHY;
235 return IXGBE_SUCCESS;
239 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
240 * @hw: pointer to hardware structure
242 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
244 s32 status = IXGBE_SUCCESS;
245 u32 swfw_mask = hw->phy.phy_semaphore_mask;
249 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
250 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
251 if (status != IXGBE_SUCCESS) {
252 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
253 "semaphore failed with %d", status);
254 msec_delay(IXGBE_CS4227_CHECK_DELAY);
258 /* Get status of reset flow. */
259 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
261 if (status == IXGBE_SUCCESS &&
262 value == IXGBE_CS4227_RESET_COMPLETE)
265 if (status != IXGBE_SUCCESS ||
266 value != IXGBE_CS4227_RESET_PENDING)
269 /* Reset is pending. Wait and check again. */
270 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
271 msec_delay(IXGBE_CS4227_CHECK_DELAY);
274 /* If still pending, assume other instance failed. */
275 if (retry == IXGBE_CS4227_RETRIES) {
276 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
277 if (status != IXGBE_SUCCESS) {
278 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
279 "semaphore failed with %d", status);
284 /* Reset the CS4227. */
285 status = ixgbe_reset_cs4227(hw);
286 if (status != IXGBE_SUCCESS) {
287 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
288 "CS4227 reset failed: %d", status);
292 /* Reset takes so long, temporarily release semaphore in case the
293 * other driver instance is waiting for the reset indication.
295 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
296 IXGBE_CS4227_RESET_PENDING);
297 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
299 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
300 if (status != IXGBE_SUCCESS) {
301 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
302 "semaphore failed with %d", status);
306 /* Record completion for next time. */
307 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
308 IXGBE_CS4227_RESET_COMPLETE);
311 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
312 msec_delay(hw->eeprom.semaphore_delay);
316 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
317 * @hw: pointer to hardware structure
319 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
321 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
323 if (hw->bus.lan_id) {
324 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
325 esdp |= IXGBE_ESDP_SDP1_DIR;
327 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
328 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
329 IXGBE_WRITE_FLUSH(hw);
333 * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
334 * @hw: pointer to hardware structure
335 * @reg_addr: 32 bit address of PHY register to read
336 * @dev_type: always unused
337 * @phy_data: Pointer to read data from PHY register
339 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
340 u32 dev_type, u16 *phy_data)
342 u32 i, data, command;
343 UNREFERENCED_1PARAMETER(dev_type);
345 /* Setup and write the read command */
346 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
347 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
348 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
349 IXGBE_MSCA_MDI_COMMAND;
351 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
353 /* Check every 10 usec to see if the access completed.
354 * The MDI Command bit will clear when the operation is
357 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
360 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
361 if (!(command & IXGBE_MSCA_MDI_COMMAND))
365 if (command & IXGBE_MSCA_MDI_COMMAND) {
366 ERROR_REPORT1(IXGBE_ERROR_POLLING,
367 "PHY read command did not complete.\n");
368 return IXGBE_ERR_PHY;
371 /* Read operation is complete. Get the data from MSRWD */
372 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
373 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
374 *phy_data = (u16)data;
376 return IXGBE_SUCCESS;
380 * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
381 * @hw: pointer to hardware structure
382 * @reg_addr: 32 bit PHY register to write
383 * @dev_type: always unused
384 * @phy_data: Data to write to the PHY register
386 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
387 u32 dev_type, u16 phy_data)
390 UNREFERENCED_1PARAMETER(dev_type);
392 /* Put the data in the MDI single read and write data register*/
393 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
395 /* Setup and write the write command */
396 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
397 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
398 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
399 IXGBE_MSCA_MDI_COMMAND;
401 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
403 /* Check every 10 usec to see if the access completed.
404 * The MDI Command bit will clear when the operation is
407 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
410 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
411 if (!(command & IXGBE_MSCA_MDI_COMMAND))
415 if (command & IXGBE_MSCA_MDI_COMMAND) {
416 ERROR_REPORT1(IXGBE_ERROR_POLLING,
417 "PHY write cmd didn't complete\n");
418 return IXGBE_ERR_PHY;
421 return IXGBE_SUCCESS;
425 * ixgbe_identify_phy_x550em - Get PHY type based on device id
426 * @hw: pointer to hardware structure
430 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
432 hw->mac.ops.set_lan_id(hw);
434 ixgbe_read_mng_if_sel_x550em(hw);
436 switch (hw->device_id) {
437 case IXGBE_DEV_ID_X550EM_A_SFP:
438 return ixgbe_identify_module_generic(hw);
439 case IXGBE_DEV_ID_X550EM_X_SFP:
440 /* set up for CS4227 usage */
441 ixgbe_setup_mux_ctl(hw);
442 ixgbe_check_cs4227(hw);
445 case IXGBE_DEV_ID_X550EM_A_SFP_N:
446 return ixgbe_identify_module_generic(hw);
448 case IXGBE_DEV_ID_X550EM_X_KX4:
449 hw->phy.type = ixgbe_phy_x550em_kx4;
451 case IXGBE_DEV_ID_X550EM_X_KR:
452 case IXGBE_DEV_ID_X550EM_A_KR:
453 case IXGBE_DEV_ID_X550EM_A_KR_L:
454 hw->phy.type = ixgbe_phy_x550em_kr;
456 case IXGBE_DEV_ID_X550EM_A_10G_T:
457 case IXGBE_DEV_ID_X550EM_A_1G_T:
458 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
459 case IXGBE_DEV_ID_X550EM_X_1G_T:
460 case IXGBE_DEV_ID_X550EM_X_10G_T:
461 return ixgbe_identify_phy_generic(hw);
465 return IXGBE_SUCCESS;
468 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
469 u32 device_type, u16 *phy_data)
471 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
472 return IXGBE_NOT_IMPLEMENTED;
475 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
476 u32 device_type, u16 phy_data)
478 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
479 return IXGBE_NOT_IMPLEMENTED;
483 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
484 * @hw: pointer to the hardware structure
485 * @addr: I2C bus address to read from
486 * @reg: I2C device register to read from
487 * @val: pointer to location to receive read value
489 * Returns an error code on error.
491 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
494 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
498 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
499 * @hw: pointer to the hardware structure
500 * @addr: I2C bus address to read from
501 * @reg: I2C device register to read from
502 * @val: pointer to location to receive read value
504 * Returns an error code on error.
507 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
510 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
514 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
515 * @hw: pointer to the hardware structure
516 * @addr: I2C bus address to write to
517 * @reg: I2C device register to write to
518 * @val: value to write
520 * Returns an error code on error.
522 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
523 u8 addr, u16 reg, u16 val)
525 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
529 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
530 * @hw: pointer to the hardware structure
531 * @addr: I2C bus address to write to
532 * @reg: I2C device register to write to
533 * @val: value to write
535 * Returns an error code on error.
538 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
539 u8 addr, u16 reg, u16 val)
541 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
545 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
546 * @hw: pointer to hardware structure
548 * Initialize the function pointers and for MAC type X550EM.
549 * Does not touch the hardware.
551 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
553 struct ixgbe_mac_info *mac = &hw->mac;
554 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
555 struct ixgbe_phy_info *phy = &hw->phy;
558 DEBUGFUNC("ixgbe_init_ops_X550EM");
560 /* Similar to X550 so start there. */
561 ret_val = ixgbe_init_ops_X550(hw);
563 /* Since this function eventually calls
564 * ixgbe_init_ops_540 by design, we are setting
565 * the pointers to NULL explicitly here to overwrite
566 * the values being set in the x540 function.
568 /* Thermal sensor not supported in x550EM */
569 mac->ops.get_thermal_sensor_data = NULL;
570 mac->ops.init_thermal_sensor_thresh = NULL;
571 mac->thermal_sensor_enabled = false;
573 /* FCOE not supported in x550EM */
574 mac->ops.get_san_mac_addr = NULL;
575 mac->ops.set_san_mac_addr = NULL;
576 mac->ops.get_wwn_prefix = NULL;
577 mac->ops.get_fcoe_boot_status = NULL;
579 /* IPsec not supported in x550EM */
580 mac->ops.disable_sec_rx_path = NULL;
581 mac->ops.enable_sec_rx_path = NULL;
583 /* AUTOC register is not present in x550EM. */
584 mac->ops.prot_autoc_read = NULL;
585 mac->ops.prot_autoc_write = NULL;
587 /* X550EM bus type is internal*/
588 hw->bus.type = ixgbe_bus_type_internal;
589 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
592 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
593 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
594 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
595 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
596 mac->ops.get_supported_physical_layer =
597 ixgbe_get_supported_physical_layer_X550em;
599 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
600 mac->ops.setup_fc = ixgbe_setup_fc_generic;
602 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
604 switch (hw->device_id) {
605 case IXGBE_DEV_ID_X550EM_X_KR:
606 case IXGBE_DEV_ID_X550EM_A_KR:
607 case IXGBE_DEV_ID_X550EM_A_KR_L:
610 mac->ops.setup_eee = NULL;
614 phy->ops.init = ixgbe_init_phy_ops_X550em;
615 phy->ops.identify = ixgbe_identify_phy_x550em;
616 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
617 phy->ops.set_phy_power = NULL;
621 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
622 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
623 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
624 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
625 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
626 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
627 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
628 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
634 * ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
635 * @hw: pointer to hardware structure
637 * Initialize the function pointers and for MAC type X550EM_a.
638 * Does not touch the hardware.
640 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
642 struct ixgbe_mac_info *mac = &hw->mac;
645 DEBUGFUNC("ixgbe_init_ops_X550EM_a");
647 /* Start with generic X550EM init */
648 ret_val = ixgbe_init_ops_X550EM(hw);
650 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
651 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) {
652 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
653 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
655 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
656 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
658 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
659 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
661 switch (mac->ops.get_media_type(hw)) {
662 case ixgbe_media_type_fiber:
663 mac->ops.setup_fc = ixgbe_setup_fc_fiber_x550em_a;
664 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
666 case ixgbe_media_type_backplane:
667 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
668 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
674 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T) ||
675 (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)) {
676 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
677 mac->ops.setup_fc = ixgbe_setup_fc_sgmii_x550em_a;
684 * ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
685 * @hw: pointer to hardware structure
687 * Initialize the function pointers and for MAC type X550EM_x.
688 * Does not touch the hardware.
690 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
692 struct ixgbe_mac_info *mac = &hw->mac;
693 struct ixgbe_link_info *link = &hw->link;
696 DEBUGFUNC("ixgbe_init_ops_X550EM_x");
698 /* Start with generic X550EM init */
699 ret_val = ixgbe_init_ops_X550EM(hw);
701 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
702 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
703 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
704 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
705 link->ops.read_link = ixgbe_read_i2c_combined_generic;
706 link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
707 link->ops.write_link = ixgbe_write_i2c_combined_generic;
708 link->ops.write_link_unlocked =
709 ixgbe_write_i2c_combined_generic_unlocked;
710 link->addr = IXGBE_CS4227;
716 * ixgbe_dmac_config_X550
717 * @hw: pointer to hardware structure
719 * Configure DMA coalescing. If enabling dmac, dmac is activated.
720 * When disabling dmac, dmac enable dmac bit is cleared.
722 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
724 u32 reg, high_pri_tc;
726 DEBUGFUNC("ixgbe_dmac_config_X550");
728 /* Disable DMA coalescing before configuring */
729 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
730 reg &= ~IXGBE_DMACR_DMAC_EN;
731 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
733 /* Disable DMA Coalescing if the watchdog timer is 0 */
734 if (!hw->mac.dmac_config.watchdog_timer)
737 ixgbe_dmac_config_tcs_X550(hw);
739 /* Configure DMA Coalescing Control Register */
740 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
742 /* Set the watchdog timer in units of 40.96 usec */
743 reg &= ~IXGBE_DMACR_DMACWT_MASK;
744 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
746 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
747 /* If fcoe is enabled, set high priority traffic class */
748 if (hw->mac.dmac_config.fcoe_en) {
749 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
750 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
751 IXGBE_DMACR_HIGH_PRI_TC_MASK);
753 reg |= IXGBE_DMACR_EN_MNG_IND;
755 /* Enable DMA coalescing after configuration */
756 reg |= IXGBE_DMACR_DMAC_EN;
757 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
760 return IXGBE_SUCCESS;
764 * ixgbe_dmac_config_tcs_X550
765 * @hw: pointer to hardware structure
767 * Configure DMA coalescing threshold per TC. The dmac enable bit must
768 * be cleared before configuring.
770 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
772 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
774 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
776 /* Configure DMA coalescing enabled */
777 switch (hw->mac.dmac_config.link_speed) {
778 case IXGBE_LINK_SPEED_10_FULL:
779 case IXGBE_LINK_SPEED_100_FULL:
780 pb_headroom = IXGBE_DMACRXT_100M;
782 case IXGBE_LINK_SPEED_1GB_FULL:
783 pb_headroom = IXGBE_DMACRXT_1G;
786 pb_headroom = IXGBE_DMACRXT_10G;
790 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
791 IXGBE_MHADD_MFS_SHIFT) / 1024);
793 /* Set the per Rx packet buffer receive threshold */
794 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
795 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
796 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
798 if (tc < hw->mac.dmac_config.num_tcs) {
800 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
801 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
802 IXGBE_RXPBSIZE_SHIFT;
804 /* Calculate receive buffer threshold in kilobytes */
805 if (rx_pb_size > pb_headroom)
806 rx_pb_size = rx_pb_size - pb_headroom;
810 /* Minimum of MFS shall be set for DMCTH */
811 reg |= (rx_pb_size > maxframe_size_kb) ?
812 rx_pb_size : maxframe_size_kb;
814 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
816 return IXGBE_SUCCESS;
820 * ixgbe_dmac_update_tcs_X550
821 * @hw: pointer to hardware structure
823 * Disables dmac, updates per TC settings, and then enables dmac.
825 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
829 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
831 /* Disable DMA coalescing before configuring */
832 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
833 reg &= ~IXGBE_DMACR_DMAC_EN;
834 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
836 ixgbe_dmac_config_tcs_X550(hw);
838 /* Enable DMA coalescing after configuration */
839 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
840 reg |= IXGBE_DMACR_DMAC_EN;
841 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
843 return IXGBE_SUCCESS;
847 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
848 * @hw: pointer to hardware structure
850 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
851 * ixgbe_hw struct in order to set up EEPROM access.
853 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
855 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
859 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
861 if (eeprom->type == ixgbe_eeprom_uninitialized) {
862 eeprom->semaphore_delay = 10;
863 eeprom->type = ixgbe_flash;
865 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
866 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
867 IXGBE_EEC_SIZE_SHIFT);
868 eeprom->word_size = 1 << (eeprom_size +
869 IXGBE_EEPROM_WORD_SIZE_SHIFT);
871 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
872 eeprom->type, eeprom->word_size);
875 return IXGBE_SUCCESS;
879 * ixgbe_enable_eee_x550 - Enable EEE support
880 * @hw: pointer to hardware structure
882 STATIC s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
888 if (hw->mac.type == ixgbe_mac_X550) {
889 /* Advertise EEE capability */
890 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
891 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
894 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
895 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
896 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
898 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
899 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
901 return IXGBE_SUCCESS;
904 switch (hw->device_id) {
905 case IXGBE_DEV_ID_X550EM_X_KR:
906 case IXGBE_DEV_ID_X550EM_A_KR:
907 case IXGBE_DEV_ID_X550EM_A_KR_L:
908 status = hw->mac.ops.read_iosf_sb_reg(hw,
909 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
910 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
911 if (status != IXGBE_SUCCESS)
914 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
915 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
917 /* Don't advertise FEC capability when EEE enabled. */
918 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
920 status = hw->mac.ops.write_iosf_sb_reg(hw,
921 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
922 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
923 if (status != IXGBE_SUCCESS)
930 return IXGBE_SUCCESS;
934 * ixgbe_disable_eee_x550 - Disable EEE support
935 * @hw: pointer to hardware structure
937 STATIC s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
943 if (hw->mac.type == ixgbe_mac_X550) {
944 /* Disable advertised EEE capability */
945 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
946 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
949 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
950 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
951 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
953 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
954 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
956 return IXGBE_SUCCESS;
959 switch (hw->device_id) {
960 case IXGBE_DEV_ID_X550EM_X_KR:
961 case IXGBE_DEV_ID_X550EM_A_KR:
962 case IXGBE_DEV_ID_X550EM_A_KR_L:
963 status = hw->mac.ops.read_iosf_sb_reg(hw,
964 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
965 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
966 if (status != IXGBE_SUCCESS)
969 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
970 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
972 /* Advertise FEC capability when EEE is disabled. */
973 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
975 status = hw->mac.ops.write_iosf_sb_reg(hw,
976 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
977 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
978 if (status != IXGBE_SUCCESS)
985 return IXGBE_SUCCESS;
989 * ixgbe_setup_eee_X550 - Enable/disable EEE support
990 * @hw: pointer to the HW structure
991 * @enable_eee: boolean flag to enable EEE
993 * Enable/disable EEE based on enable_eee flag.
994 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
998 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
1003 DEBUGFUNC("ixgbe_setup_eee_X550");
1005 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
1006 /* Enable or disable EEE per flag */
1008 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1010 /* Not supported on first revision of X550EM_x. */
1011 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
1012 !(IXGBE_FUSES0_REV_MASK &
1013 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
1014 return IXGBE_SUCCESS;
1015 status = ixgbe_enable_eee_x550(hw);
1019 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1021 status = ixgbe_disable_eee_x550(hw);
1025 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
1027 return IXGBE_SUCCESS;
1031 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1032 * @hw: pointer to hardware structure
1033 * @enable: enable or disable source address pruning
1034 * @pool: Rx pool to set source address pruning for
1036 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1041 /* max rx pool is 63 */
1045 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1046 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1049 pfflp |= (1ULL << pool);
1051 pfflp &= ~(1ULL << pool);
1053 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1054 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1058 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1059 * @hw: pointer to hardware structure
1060 * @enable: enable or disable switch for Ethertype anti-spoofing
1061 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1064 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1065 bool enable, int vf)
1067 int vf_target_reg = vf >> 3;
1068 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1071 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1073 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1075 pfvfspoof |= (1 << vf_target_shift);
1077 pfvfspoof &= ~(1 << vf_target_shift);
1079 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1083 * ixgbe_iosf_wait - Wait for IOSF command completion
1084 * @hw: pointer to hardware structure
1085 * @ctrl: pointer to location to receive final IOSF control value
1087 * Returns failing status on timeout
1089 * Note: ctrl can be NULL if the IOSF control register value is not needed
1091 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1095 /* Check every 10 usec to see if the address cycle completed.
1096 * The SB IOSF BUSY bit will clear when the operation is
1099 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1100 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1101 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1107 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1108 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1109 return IXGBE_ERR_PHY;
1112 return IXGBE_SUCCESS;
1116 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register
1117 * of the IOSF device
1118 * @hw: pointer to hardware structure
1119 * @reg_addr: 32 bit PHY register to write
1120 * @device_type: 3 bit device type
1121 * @data: Data to write to the register
1123 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1124 u32 device_type, u32 data)
1126 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1130 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1131 if (ret != IXGBE_SUCCESS)
1134 ret = ixgbe_iosf_wait(hw, NULL);
1135 if (ret != IXGBE_SUCCESS)
1138 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1139 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1141 /* Write IOSF control register */
1142 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1144 /* Write IOSF data register */
1145 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1147 ret = ixgbe_iosf_wait(hw, &command);
1149 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1150 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1151 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1152 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1153 "Failed to write, error %x\n", error);
1154 ret = IXGBE_ERR_PHY;
1158 ixgbe_release_swfw_semaphore(hw, gssr);
1163 * ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device
1164 * @hw: pointer to hardware structure
1165 * @reg_addr: 32 bit PHY register to write
1166 * @device_type: 3 bit device type
1167 * @data: Pointer to read data from the register
1169 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1170 u32 device_type, u32 *data)
1172 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1176 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1177 if (ret != IXGBE_SUCCESS)
1180 ret = ixgbe_iosf_wait(hw, NULL);
1181 if (ret != IXGBE_SUCCESS)
1184 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1185 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1187 /* Write IOSF control register */
1188 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1190 ret = ixgbe_iosf_wait(hw, &command);
1192 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1193 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1194 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1195 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1196 "Failed to read, error %x\n", error);
1197 ret = IXGBE_ERR_PHY;
1200 if (ret == IXGBE_SUCCESS)
1201 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1204 ixgbe_release_swfw_semaphore(hw, gssr);
1209 * ixgbe_get_phy_token - Get the token for shared phy access
1210 * @hw: Pointer to hardware structure
1213 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1215 struct ixgbe_hic_phy_token_req token_cmd;
1218 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1219 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1220 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1221 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1222 token_cmd.port_number = hw->bus.lan_id;
1223 token_cmd.command_type = FW_PHY_TOKEN_REQ;
1225 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1227 IXGBE_HI_COMMAND_TIMEOUT,
1231 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1232 return IXGBE_SUCCESS;
1233 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1234 return IXGBE_ERR_FW_RESP_INVALID;
1236 return IXGBE_ERR_TOKEN_RETRY;
1240 * ixgbe_put_phy_token - Put the token for shared phy access
1241 * @hw: Pointer to hardware structure
1244 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1246 struct ixgbe_hic_phy_token_req token_cmd;
1249 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1250 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1251 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1252 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1253 token_cmd.port_number = hw->bus.lan_id;
1254 token_cmd.command_type = FW_PHY_TOKEN_REL;
1256 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1258 IXGBE_HI_COMMAND_TIMEOUT,
1262 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1263 return IXGBE_SUCCESS;
1265 DEBUGOUT("Put PHY Token host interface command failed");
1266 return IXGBE_ERR_FW_RESP_INVALID;
1270 * ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1271 * of the IOSF device
1272 * @hw: pointer to hardware structure
1273 * @reg_addr: 32 bit PHY register to write
1274 * @device_type: 3 bit device type
1275 * @data: Data to write to the register
1277 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1278 u32 device_type, u32 data)
1280 struct ixgbe_hic_internal_phy_req write_cmd;
1282 UNREFERENCED_1PARAMETER(device_type);
1284 memset(&write_cmd, 0, sizeof(write_cmd));
1285 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1286 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1287 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1288 write_cmd.port_number = hw->bus.lan_id;
1289 write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1290 write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1291 write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1293 status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1295 IXGBE_HI_COMMAND_TIMEOUT, false);
1301 * ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device
1302 * @hw: pointer to hardware structure
1303 * @reg_addr: 32 bit PHY register to write
1304 * @device_type: 3 bit device type
1305 * @data: Pointer to read data from the register
1307 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1308 u32 device_type, u32 *data)
1311 struct ixgbe_hic_internal_phy_req cmd;
1312 struct ixgbe_hic_internal_phy_resp rsp;
1315 UNREFERENCED_1PARAMETER(device_type);
1317 memset(&hic, 0, sizeof(hic));
1318 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1319 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1320 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1321 hic.cmd.port_number = hw->bus.lan_id;
1322 hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1323 hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1325 status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1327 IXGBE_HI_COMMAND_TIMEOUT, true);
1329 /* Extract the register value from the response. */
1330 *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1336 * ixgbe_disable_mdd_X550
1337 * @hw: pointer to hardware structure
1339 * Disable malicious driver detection
1341 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1345 DEBUGFUNC("ixgbe_disable_mdd_X550");
1347 /* Disable MDD for TX DMA and interrupt */
1348 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1349 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1350 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1352 /* Disable MDD for RX and interrupt */
1353 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1354 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1355 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1359 * ixgbe_enable_mdd_X550
1360 * @hw: pointer to hardware structure
1362 * Enable malicious driver detection
1364 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1368 DEBUGFUNC("ixgbe_enable_mdd_X550");
1370 /* Enable MDD for TX DMA and interrupt */
1371 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1372 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1373 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1375 /* Enable MDD for RX and interrupt */
1376 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1377 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1378 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1382 * ixgbe_restore_mdd_vf_X550
1383 * @hw: pointer to hardware structure
1386 * Restore VF that was disabled during malicious driver detection event
1388 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1390 u32 idx, reg, num_qs, start_q, bitmask;
1392 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1394 /* Map VF to queues */
1395 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1396 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1397 case IXGBE_MRQC_VMDQRT8TCEN:
1398 num_qs = 8; /* 16 VFs / pools */
1399 bitmask = 0x000000FF;
1401 case IXGBE_MRQC_VMDQRSS32EN:
1402 case IXGBE_MRQC_VMDQRT4TCEN:
1403 num_qs = 4; /* 32 VFs / pools */
1404 bitmask = 0x0000000F;
1406 default: /* 64 VFs / pools */
1408 bitmask = 0x00000003;
1411 start_q = vf * num_qs;
1413 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1416 reg |= (bitmask << (start_q % 32));
1417 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1418 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1422 * ixgbe_mdd_event_X550
1423 * @hw: pointer to hardware structure
1424 * @vf_bitmap: vf bitmap of malicious vfs
1426 * Handle malicious driver detection event.
1428 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1431 u32 i, j, reg, q, shift, vf, idx;
1433 DEBUGFUNC("ixgbe_mdd_event_X550");
1435 /* figure out pool size for mapping to vf's */
1436 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1437 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1438 case IXGBE_MRQC_VMDQRT8TCEN:
1439 shift = 3; /* 16 VFs / pools */
1441 case IXGBE_MRQC_VMDQRSS32EN:
1442 case IXGBE_MRQC_VMDQRT4TCEN:
1443 shift = 2; /* 32 VFs / pools */
1446 shift = 1; /* 64 VFs / pools */
1450 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1451 for (i = 0; i < 4; i++) {
1452 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1453 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1458 /* Get malicious queue */
1459 for (j = 0; j < 32 && wqbr; j++) {
1461 if (!(wqbr & (1 << j)))
1464 /* Get queue from bitmask */
1467 /* Map queue to vf */
1470 /* Set vf bit in vf_bitmap */
1472 vf_bitmap[idx] |= (1 << (vf % 32));
1479 * ixgbe_get_media_type_X550em - Get media type
1480 * @hw: pointer to hardware structure
1482 * Returns the media type (fiber, copper, backplane)
1484 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1486 enum ixgbe_media_type media_type;
1488 DEBUGFUNC("ixgbe_get_media_type_X550em");
1490 /* Detect if there is a copper PHY attached. */
1491 switch (hw->device_id) {
1492 case IXGBE_DEV_ID_X550EM_X_KR:
1493 case IXGBE_DEV_ID_X550EM_X_KX4:
1494 case IXGBE_DEV_ID_X550EM_A_KR:
1495 case IXGBE_DEV_ID_X550EM_A_KR_L:
1496 media_type = ixgbe_media_type_backplane;
1498 case IXGBE_DEV_ID_X550EM_X_SFP:
1499 case IXGBE_DEV_ID_X550EM_A_SFP:
1500 case IXGBE_DEV_ID_X550EM_A_SFP_N:
1501 case IXGBE_DEV_ID_X550EM_A_QSFP:
1502 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1503 media_type = ixgbe_media_type_fiber;
1505 case IXGBE_DEV_ID_X550EM_X_1G_T:
1506 case IXGBE_DEV_ID_X550EM_X_10G_T:
1507 case IXGBE_DEV_ID_X550EM_A_10G_T:
1508 media_type = ixgbe_media_type_copper;
1510 case IXGBE_DEV_ID_X550EM_A_SGMII:
1511 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1512 media_type = ixgbe_media_type_backplane;
1513 hw->phy.type = ixgbe_phy_sgmii;
1515 case IXGBE_DEV_ID_X550EM_A_1G_T:
1516 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1517 media_type = ixgbe_media_type_copper;
1520 media_type = ixgbe_media_type_unknown;
1527 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1528 * @hw: pointer to hardware structure
1529 * @linear: true if SFP module is linear
1531 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1533 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1535 switch (hw->phy.sfp_type) {
1536 case ixgbe_sfp_type_not_present:
1537 return IXGBE_ERR_SFP_NOT_PRESENT;
1538 case ixgbe_sfp_type_da_cu_core0:
1539 case ixgbe_sfp_type_da_cu_core1:
1542 case ixgbe_sfp_type_srlr_core0:
1543 case ixgbe_sfp_type_srlr_core1:
1544 case ixgbe_sfp_type_da_act_lmt_core0:
1545 case ixgbe_sfp_type_da_act_lmt_core1:
1546 case ixgbe_sfp_type_1g_sx_core0:
1547 case ixgbe_sfp_type_1g_sx_core1:
1548 case ixgbe_sfp_type_1g_lx_core0:
1549 case ixgbe_sfp_type_1g_lx_core1:
1552 case ixgbe_sfp_type_unknown:
1553 case ixgbe_sfp_type_1g_cu_core0:
1554 case ixgbe_sfp_type_1g_cu_core1:
1556 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1559 return IXGBE_SUCCESS;
1563 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1564 * @hw: pointer to hardware structure
1566 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1568 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1573 DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1575 status = ixgbe_identify_module_generic(hw);
1577 if (status != IXGBE_SUCCESS)
1580 /* Check if SFP module is supported */
1581 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1587 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1588 * @hw: pointer to hardware structure
1590 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1595 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1597 /* Check if SFP module is supported */
1598 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1600 if (status != IXGBE_SUCCESS)
1603 ixgbe_init_mac_link_ops_X550em(hw);
1604 hw->phy.ops.reset = NULL;
1606 return IXGBE_SUCCESS;
1610 * ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1612 * @hw: pointer to hardware structure
1614 STATIC s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1619 /* Restart auto-negotiation. */
1620 status = hw->mac.ops.read_iosf_sb_reg(hw,
1621 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1622 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1625 DEBUGOUT("Auto-negotiation did not complete\n");
1629 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1630 status = hw->mac.ops.write_iosf_sb_reg(hw,
1631 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1632 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1634 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1637 /* Indicate to FW that AN restart has been asserted */
1638 status = hw->mac.ops.read_iosf_sb_reg(hw,
1639 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1640 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1643 DEBUGOUT("Auto-negotiation did not complete\n");
1647 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1648 status = hw->mac.ops.write_iosf_sb_reg(hw,
1649 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1650 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1657 * ixgbe_setup_sgmii - Set up link for sgmii
1658 * @hw: pointer to hardware structure
1660 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1663 struct ixgbe_mac_info *mac = &hw->mac;
1664 u32 lval, sval, flx_val;
1667 rc = mac->ops.read_iosf_sb_reg(hw,
1668 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1669 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1673 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1674 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1675 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1676 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1677 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1678 rc = mac->ops.write_iosf_sb_reg(hw,
1679 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1680 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1684 rc = mac->ops.read_iosf_sb_reg(hw,
1685 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1686 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1690 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1691 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1692 rc = mac->ops.write_iosf_sb_reg(hw,
1693 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1694 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1698 rc = mac->ops.read_iosf_sb_reg(hw,
1699 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1700 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1704 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1705 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1706 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1707 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1708 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1710 rc = mac->ops.write_iosf_sb_reg(hw,
1711 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1712 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1716 rc = ixgbe_restart_an_internal_phy_x550em(hw);
1720 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1724 * ixgbe_setup_sgmii_m88 - Set up link for sgmii with Marvell PHYs
1725 * @hw: pointer to hardware structure
1727 STATIC s32 ixgbe_setup_sgmii_m88(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1730 struct ixgbe_mac_info *mac = &hw->mac;
1731 u32 lval, sval, flx_val;
1734 rc = mac->ops.read_iosf_sb_reg(hw,
1735 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1736 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1740 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1741 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1742 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1743 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1744 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1745 rc = mac->ops.write_iosf_sb_reg(hw,
1746 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1747 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1751 rc = mac->ops.read_iosf_sb_reg(hw,
1752 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1753 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1757 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1758 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1759 rc = mac->ops.write_iosf_sb_reg(hw,
1760 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1761 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1765 rc = mac->ops.write_iosf_sb_reg(hw,
1766 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1767 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1771 rc = mac->ops.read_iosf_sb_reg(hw,
1772 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1773 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1777 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1778 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1779 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1780 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1781 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1783 rc = mac->ops.write_iosf_sb_reg(hw,
1784 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1785 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1789 rc = ixgbe_restart_an_internal_phy_x550em(hw);
1791 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1795 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1796 * @hw: pointer to hardware structure
1798 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1800 struct ixgbe_mac_info *mac = &hw->mac;
1802 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1804 switch (hw->mac.ops.get_media_type(hw)) {
1805 case ixgbe_media_type_fiber:
1806 /* CS4227 does not support autoneg, so disable the laser control
1807 * functions for SFP+ fiber
1809 mac->ops.disable_tx_laser = NULL;
1810 mac->ops.enable_tx_laser = NULL;
1811 mac->ops.flap_tx_laser = NULL;
1812 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1813 mac->ops.set_rate_select_speed =
1814 ixgbe_set_soft_rate_select_speed;
1815 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1816 (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1817 mac->ops.setup_mac_link =
1818 ixgbe_setup_mac_link_sfp_x550a;
1820 mac->ops.setup_mac_link =
1821 ixgbe_setup_mac_link_sfp_x550em;
1823 case ixgbe_media_type_copper:
1824 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1825 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
1826 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
1827 mac->ops.setup_link = ixgbe_setup_sgmii_m88;
1829 mac->ops.setup_link =
1830 ixgbe_setup_mac_link_t_X550em;
1833 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1834 mac->ops.check_link = ixgbe_check_link_t_X550em;
1837 case ixgbe_media_type_backplane:
1838 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1839 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1840 mac->ops.setup_link = ixgbe_setup_sgmii;
1848 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1849 * @hw: pointer to hardware structure
1850 * @speed: pointer to link speed
1851 * @autoneg: true when autoneg or autotry is enabled
1853 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1854 ixgbe_link_speed *speed,
1857 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1860 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1862 /* CS4227 SFP must not enable auto-negotiation */
1865 /* Check if 1G SFP module. */
1866 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1867 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1868 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1869 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1870 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1871 return IXGBE_SUCCESS;
1874 /* Link capabilities are based on SFP */
1875 if (hw->phy.multispeed_fiber)
1876 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1877 IXGBE_LINK_SPEED_1GB_FULL;
1879 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1881 switch (hw->phy.type) {
1883 *speed = IXGBE_LINK_SPEED_1GB_FULL |
1884 IXGBE_LINK_SPEED_100_FULL |
1885 IXGBE_LINK_SPEED_10_FULL;
1887 case ixgbe_phy_sgmii:
1888 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1890 case ixgbe_phy_x550em_kr:
1891 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1892 /* check different backplane modes */
1893 if (hw->phy.nw_mng_if_sel &
1894 IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
1895 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
1897 } else if (hw->device_id ==
1898 IXGBE_DEV_ID_X550EM_A_KR_L) {
1899 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1905 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1906 IXGBE_LINK_SPEED_1GB_FULL;
1912 return IXGBE_SUCCESS;
1916 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1917 * @hw: pointer to hardware structure
1918 * @lsc: pointer to boolean flag which indicates whether external Base T
1919 * PHY interrupt is lsc
1921 * Determime if external Base T PHY interrupt cause is high temperature
1922 * failure alarm or link status change.
1924 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1925 * failure alarm, else return PHY access status.
1927 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1934 /* Vendor alarm triggered */
1935 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1936 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1939 if (status != IXGBE_SUCCESS ||
1940 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1943 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1944 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1945 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1948 if (status != IXGBE_SUCCESS ||
1949 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1950 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1953 /* Global alarm triggered */
1954 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1955 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1958 if (status != IXGBE_SUCCESS)
1961 /* If high temperature failure, then return over temp error and exit */
1962 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1963 /* power down the PHY in case the PHY FW didn't already */
1964 ixgbe_set_copper_phy_power(hw, false);
1965 return IXGBE_ERR_OVERTEMP;
1966 } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1967 /* device fault alarm triggered */
1968 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1969 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1972 if (status != IXGBE_SUCCESS)
1975 /* if device fault was due to high temp alarm handle and exit */
1976 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1977 /* power down the PHY in case the PHY FW didn't */
1978 ixgbe_set_copper_phy_power(hw, false);
1979 return IXGBE_ERR_OVERTEMP;
1983 /* Vendor alarm 2 triggered */
1984 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1985 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1987 if (status != IXGBE_SUCCESS ||
1988 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1991 /* link connect/disconnect event occurred */
1992 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1993 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1995 if (status != IXGBE_SUCCESS)
1999 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2002 return IXGBE_SUCCESS;
2006 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2007 * @hw: pointer to hardware structure
2009 * Enable link status change and temperature failure alarm for the external
2012 * Returns PHY access status
2014 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2020 /* Clear interrupt flags */
2021 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2023 /* Enable link status change alarm */
2024 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2025 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
2027 if (status != IXGBE_SUCCESS)
2030 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2032 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2033 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
2035 if (status != IXGBE_SUCCESS)
2038 /* Enable high temperature failure and global fault alarms */
2039 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2040 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2043 if (status != IXGBE_SUCCESS)
2046 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2047 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2049 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2050 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2053 if (status != IXGBE_SUCCESS)
2056 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2057 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2058 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2061 if (status != IXGBE_SUCCESS)
2064 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2065 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2067 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2068 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2071 if (status != IXGBE_SUCCESS)
2074 /* Enable chip-wide vendor alarm */
2075 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2076 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2079 if (status != IXGBE_SUCCESS)
2082 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2084 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2085 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2092 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2093 * @hw: pointer to hardware structure
2094 * @speed: link speed
2096 * Configures the integrated KR PHY.
2098 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2099 ixgbe_link_speed speed)
2104 status = hw->mac.ops.read_iosf_sb_reg(hw,
2105 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2106 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2110 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2111 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2112 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2114 /* Advertise 10G support. */
2115 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2116 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2118 /* Advertise 1G support. */
2119 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2120 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2122 status = hw->mac.ops.write_iosf_sb_reg(hw,
2123 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2124 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2126 if (hw->mac.type == ixgbe_mac_X550EM_a) {
2127 /* Set lane mode to KR auto negotiation */
2128 status = hw->mac.ops.read_iosf_sb_reg(hw,
2129 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2130 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2135 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2136 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2137 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2138 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2139 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2141 status = hw->mac.ops.write_iosf_sb_reg(hw,
2142 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2143 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2146 return ixgbe_restart_an_internal_phy_x550em(hw);
2150 * ixgbe_setup_m88 - setup m88 PHY
2151 * @hw: pointer to hardware structure
2153 STATIC s32 ixgbe_setup_m88(struct ixgbe_hw *hw)
2155 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2159 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2160 return IXGBE_SUCCESS;
2162 rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2166 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2169 if (reg & IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN) {
2170 reg &= ~IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN;
2171 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2175 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, ®);
2178 if (reg & IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN) {
2179 reg &= ~IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN;
2180 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0,
2184 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 2);
2188 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2192 if (reg & IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN) {
2193 reg &= ~IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN;
2194 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2196 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2200 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2204 reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2205 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2209 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2215 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2219 if (!(reg & IXGBE_M88E1500_COPPER_CTRL_AN_EN)) {
2220 reg |= IXGBE_M88E1500_COPPER_CTRL_AN_EN;
2221 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2225 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, ®);
2228 reg &= ~IXGBE_M88E1500_1000T_CTRL_HALF_DUPLEX;
2229 reg &= ~IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2230 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
2231 reg |= IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2232 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, reg);
2234 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, ®);
2237 reg &= ~IXGBE_M88E1500_COPPER_AN_T4;
2238 reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_FD;
2239 reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_HD;
2240 reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_FD;
2241 reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_HD;
2243 /* Flow control auto negotiation configuration was moved from here to
2244 * the function ixgbe_setup_fc_sgmii_x550em_a()
2247 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
2248 reg |= IXGBE_M88E1500_COPPER_AN_100TX_FD;
2249 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL)
2250 reg |= IXGBE_M88E1500_COPPER_AN_10TX_FD;
2251 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, reg);
2253 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2256 reg |= IXGBE_M88E1500_COPPER_CTRL_RESTART_AN;
2257 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2260 hw->mac.ops.release_swfw_sync(hw, mask);
2264 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2265 hw->mac.ops.release_swfw_sync(hw, mask);
2270 * ixgbe_reset_phy_m88e1500 - Reset m88e1500 PHY
2271 * @hw: pointer to hardware structure
2273 * The PHY token must be held when calling this function.
2275 static s32 ixgbe_reset_phy_m88e1500(struct ixgbe_hw *hw)
2280 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2284 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2288 reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2289 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2297 * ixgbe_reset_phy_m88e1543 - Reset m88e1543 PHY
2298 * @hw: pointer to hardware structure
2300 * The PHY token must be held when calling this function.
2302 static s32 ixgbe_reset_phy_m88e1543(struct ixgbe_hw *hw)
2304 return hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2308 * ixgbe_reset_phy_m88 - Reset m88 PHY
2309 * @hw: pointer to hardware structure
2311 STATIC s32 ixgbe_reset_phy_m88(struct ixgbe_hw *hw)
2313 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2317 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2318 return IXGBE_SUCCESS;
2320 rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2324 switch (hw->phy.id) {
2325 case IXGBE_M88E1500_E_PHY_ID:
2326 rc = ixgbe_reset_phy_m88e1500(hw);
2328 case IXGBE_M88E1543_E_PHY_ID:
2329 rc = ixgbe_reset_phy_m88e1543(hw);
2336 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2340 reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2341 IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2342 IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2343 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2347 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 18);
2351 reg = IXGBE_M88E1500_GEN_CTRL_RESET |
2352 IXGBE_M88E1500_GEN_CTRL_MODE_SGMII_COPPER;
2353 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_GEN_CTRL, 0, reg);
2357 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2361 reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2362 IXGBE_M88E1500_FIBER_CTRL_AN_EN |
2363 IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2364 IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2365 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2369 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2373 reg = (IXGBE_M88E1500_MAC_CTRL_1_DWN_4X <<
2374 IXGBE_M88E1500_MAC_CTRL_1_DWN_SHIFT) |
2375 (IXGBE_M88E1500_MAC_CTRL_1_ED_TM <<
2376 IXGBE_M88E1500_MAC_CTRL_1_ED_SHIFT) |
2377 (IXGBE_M88E1500_MAC_CTRL_1_MDIX_AUTO <<
2378 IXGBE_M88E1500_MAC_CTRL_1_MDIX_SHIFT);
2379 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, reg);
2383 reg = IXGBE_M88E1500_COPPER_CTRL_RESET |
2384 IXGBE_M88E1500_COPPER_CTRL_AN_EN |
2385 IXGBE_M88E1500_COPPER_CTRL_RESTART_AN |
2386 IXGBE_M88E1500_COPPER_CTRL_FULL_DUPLEX |
2387 IXGBE_M88E1500_COPPER_CTRL_SPEED_MSB;
2388 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2392 hw->mac.ops.release_swfw_sync(hw, mask);
2394 /* In case of first reset set advertised speeds to default value */
2395 if (!hw->phy.autoneg_advertised)
2396 hw->phy.autoneg_advertised = IXGBE_LINK_SPEED_1GB_FULL |
2397 IXGBE_LINK_SPEED_100_FULL |
2398 IXGBE_LINK_SPEED_10_FULL;
2400 return ixgbe_setup_m88(hw);
2403 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2404 hw->mac.ops.release_swfw_sync(hw, mask);
2409 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2410 * @hw: pointer to hardware structure
2412 * Read NW_MNG_IF_SEL register and save field values, and check for valid field
2415 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2417 /* Save NW management interface connected on board. This is used
2418 * to determine internal PHY mode.
2420 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2422 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2423 * PHY address. This register field was has only been used for X552.
2425 if (hw->mac.type == ixgbe_mac_X550EM_a &&
2426 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2427 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2428 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2429 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2432 return IXGBE_SUCCESS;
2436 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2437 * @hw: pointer to hardware structure
2439 * Initialize any function pointers that were not able to be
2440 * set during init_shared_code because the PHY/SFP type was
2441 * not known. Perform the SFP init if necessary.
2443 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2445 struct ixgbe_phy_info *phy = &hw->phy;
2448 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2450 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2451 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2452 ixgbe_setup_mux_ctl(hw);
2453 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2456 switch (hw->device_id) {
2457 case IXGBE_DEV_ID_X550EM_A_1G_T:
2458 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2459 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2460 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2461 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2462 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2464 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2466 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2469 case IXGBE_DEV_ID_X550EM_A_10G_T:
2470 case IXGBE_DEV_ID_X550EM_A_SFP:
2471 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2472 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2474 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2476 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2478 case IXGBE_DEV_ID_X550EM_X_SFP:
2479 /* set up for CS4227 usage */
2480 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2486 /* Identify the PHY or SFP module */
2487 ret_val = phy->ops.identify(hw);
2488 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
2491 /* Setup function pointers based on detected hardware */
2492 ixgbe_init_mac_link_ops_X550em(hw);
2493 if (phy->sfp_type != ixgbe_sfp_type_unknown)
2494 phy->ops.reset = NULL;
2496 /* Set functions pointers based on phy type */
2497 switch (hw->phy.type) {
2498 case ixgbe_phy_x550em_kx4:
2499 phy->ops.setup_link = NULL;
2500 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2501 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2503 case ixgbe_phy_x550em_kr:
2504 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2505 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2506 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2508 case ixgbe_phy_x550em_ext_t:
2509 /* If internal link mode is XFI, then setup iXFI internal link,
2510 * else setup KR now.
2512 phy->ops.setup_internal_link =
2513 ixgbe_setup_internal_phy_t_x550em;
2515 /* setup SW LPLU only for first revision of X550EM_x */
2516 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2517 !(IXGBE_FUSES0_REV_MASK &
2518 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2519 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2521 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2522 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2524 case ixgbe_phy_sgmii:
2525 phy->ops.setup_link = NULL;
2528 phy->ops.setup_link = ixgbe_setup_m88;
2529 phy->ops.reset = ixgbe_reset_phy_m88;
2538 * ixgbe_set_mdio_speed - Set MDIO clock speed
2539 * @hw: pointer to hardware structure
2541 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2545 switch (hw->device_id) {
2546 case IXGBE_DEV_ID_X550EM_X_10G_T:
2547 case IXGBE_DEV_ID_X550EM_A_SGMII:
2548 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2549 case IXGBE_DEV_ID_X550EM_A_1G_T:
2550 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2551 case IXGBE_DEV_ID_X550EM_A_10G_T:
2552 case IXGBE_DEV_ID_X550EM_A_SFP:
2553 case IXGBE_DEV_ID_X550EM_A_QSFP:
2554 /* Config MDIO clock speed before the first MDIO PHY access */
2555 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2556 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2557 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2565 * ixgbe_reset_hw_X550em - Perform hardware reset
2566 * @hw: pointer to hardware structure
2568 * Resets the hardware by resetting the transmit and receive units, masks
2569 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2572 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2574 ixgbe_link_speed link_speed;
2578 bool link_up = false;
2580 DEBUGFUNC("ixgbe_reset_hw_X550em");
2582 /* Call adapter stop to disable Tx/Rx and clear interrupts */
2583 status = hw->mac.ops.stop_adapter(hw);
2584 if (status != IXGBE_SUCCESS)
2587 /* flush pending Tx transactions */
2588 ixgbe_clear_tx_pending(hw);
2590 ixgbe_set_mdio_speed(hw);
2592 /* PHY ops must be identified and initialized prior to reset */
2593 status = hw->phy.ops.init(hw);
2595 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2598 /* start the external PHY */
2599 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2600 status = ixgbe_init_ext_t_x550em(hw);
2605 /* Setup SFP module if there is one present. */
2606 if (hw->phy.sfp_setup_needed) {
2607 status = hw->mac.ops.setup_sfp(hw);
2608 hw->phy.sfp_setup_needed = false;
2611 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2615 if (!hw->phy.reset_disable && hw->phy.ops.reset)
2616 hw->phy.ops.reset(hw);
2619 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
2620 * If link reset is used when link is up, it might reset the PHY when
2621 * mng is using it. If link is down or the flag to force full link
2622 * reset is set, then perform link reset.
2624 ctrl = IXGBE_CTRL_LNK_RST;
2625 if (!hw->force_full_reset) {
2626 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2628 ctrl = IXGBE_CTRL_RST;
2631 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2632 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2633 IXGBE_WRITE_FLUSH(hw);
2635 /* Poll for reset bit to self-clear meaning reset is complete */
2636 for (i = 0; i < 10; i++) {
2638 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2639 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2643 if (ctrl & IXGBE_CTRL_RST_MASK) {
2644 status = IXGBE_ERR_RESET_FAILED;
2645 DEBUGOUT("Reset polling failed to complete.\n");
2650 /* Double resets are required for recovery from certain error
2651 * conditions. Between resets, it is necessary to stall to
2652 * allow time for any pending HW events to complete.
2654 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2655 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2659 /* Store the permanent mac address */
2660 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2662 /* Store MAC address from RAR0, clear receive address registers, and
2663 * clear the multicast table. Also reset num_rar_entries to 128,
2664 * since we modify this value when programming the SAN MAC address.
2666 hw->mac.num_rar_entries = 128;
2667 hw->mac.ops.init_rx_addrs(hw);
2669 ixgbe_set_mdio_speed(hw);
2671 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2672 ixgbe_setup_mux_ctl(hw);
2678 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2679 * @hw: pointer to hardware structure
2681 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2686 status = hw->phy.ops.read_reg(hw,
2687 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2688 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2691 if (status != IXGBE_SUCCESS)
2694 /* If PHY FW reset completed bit is set then this is the first
2695 * SW instance after a power on so the PHY FW must be un-stalled.
2697 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2698 status = hw->phy.ops.read_reg(hw,
2699 IXGBE_MDIO_GLOBAL_RES_PR_10,
2700 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2703 if (status != IXGBE_SUCCESS)
2706 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2708 status = hw->phy.ops.write_reg(hw,
2709 IXGBE_MDIO_GLOBAL_RES_PR_10,
2710 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2713 if (status != IXGBE_SUCCESS)
2721 * ixgbe_setup_kr_x550em - Configure the KR PHY.
2722 * @hw: pointer to hardware structure
2724 * Configures the integrated KR PHY for X550EM_x.
2726 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2728 if (hw->mac.type != ixgbe_mac_X550EM_x)
2729 return IXGBE_SUCCESS;
2731 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2735 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2736 * @hw: pointer to hardware structure
2738 * Configure the external PHY and the integrated KR PHY for SFP support.
2740 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2741 ixgbe_link_speed speed,
2742 bool autoneg_wait_to_complete)
2745 u16 reg_slice, reg_val;
2746 bool setup_linear = false;
2747 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2749 /* Check if SFP module is supported and linear */
2750 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2752 /* If no SFP module present, then return success. Return success since
2753 * there is no reason to configure CS4227 and SFP not present error is
2754 * not excepted in the setup MAC link flow.
2756 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2757 return IXGBE_SUCCESS;
2759 if (ret_val != IXGBE_SUCCESS)
2762 /* Configure internal PHY for KR/KX. */
2763 ixgbe_setup_kr_speed_x550em(hw, speed);
2765 /* Configure CS4227 LINE side to proper mode. */
2766 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2767 (hw->bus.lan_id << 12);
2769 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2771 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2772 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2778 * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
2779 * @hw: pointer to hardware structure
2780 * @speed: the link speed to force
2782 * Configures the integrated PHY for native SFI mode. Used to connect the
2783 * internal PHY directly to an SFP cage, without autonegotiation.
2785 STATIC s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2787 struct ixgbe_mac_info *mac = &hw->mac;
2791 /* Disable all AN and force speed to 10G Serial. */
2792 status = mac->ops.read_iosf_sb_reg(hw,
2793 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2794 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2795 if (status != IXGBE_SUCCESS)
2798 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2799 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2800 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2801 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2803 /* Select forced link speed for internal PHY. */
2805 case IXGBE_LINK_SPEED_10GB_FULL:
2806 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
2808 case IXGBE_LINK_SPEED_1GB_FULL:
2809 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2812 /* Other link speeds are not supported by internal PHY. */
2813 return IXGBE_ERR_LINK_SETUP;
2816 status = mac->ops.write_iosf_sb_reg(hw,
2817 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2818 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2820 /* Toggle port SW reset by AN reset. */
2821 status = ixgbe_restart_an_internal_phy_x550em(hw);
2827 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2828 * @hw: pointer to hardware structure
2830 * Configure the the integrated PHY for SFP support.
2832 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2833 ixgbe_link_speed speed,
2834 bool autoneg_wait_to_complete)
2838 bool setup_linear = false;
2839 u32 reg_slice, reg_phy_int, slice_offset;
2841 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2843 /* Check if SFP module is supported and linear */
2844 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2846 /* If no SFP module present, then return success. Return success since
2847 * SFP not present error is not excepted in the setup MAC link flow.
2849 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2850 return IXGBE_SUCCESS;
2852 if (ret_val != IXGBE_SUCCESS)
2855 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2856 /* Configure internal PHY for native SFI based on module type */
2857 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2858 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2859 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int);
2861 if (ret_val != IXGBE_SUCCESS)
2864 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
2866 reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
2868 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2869 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2870 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2872 if (ret_val != IXGBE_SUCCESS)
2875 /* Setup SFI internal link. */
2876 ret_val = ixgbe_setup_sfi_x550a(hw, &speed);
2878 /* Configure internal PHY for KR/KX. */
2879 ixgbe_setup_kr_speed_x550em(hw, speed);
2881 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2883 DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2884 return IXGBE_ERR_PHY_ADDR_INVALID;
2887 /* Get external PHY device id */
2888 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_GLOBAL_ID_MSB,
2889 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
2891 if (ret_val != IXGBE_SUCCESS)
2894 /* When configuring quad port CS4223, the MAC instance is part
2895 * of the slice offset.
2897 if (reg_phy_ext == IXGBE_CS4223_PHY_ID)
2898 slice_offset = (hw->bus.lan_id +
2899 (hw->bus.instance_id << 1)) << 12;
2901 slice_offset = hw->bus.lan_id << 12;
2903 /* Configure CS4227/CS4223 LINE side to proper mode. */
2904 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2906 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2908 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2909 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2910 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2916 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2917 * @hw: pointer to hardware structure
2919 * iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2921 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2923 struct ixgbe_mac_info *mac = &hw->mac;
2927 /* Disable training protocol FSM. */
2928 status = mac->ops.read_iosf_sb_reg(hw,
2929 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2930 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2931 if (status != IXGBE_SUCCESS)
2933 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2934 status = mac->ops.write_iosf_sb_reg(hw,
2935 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2936 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2937 if (status != IXGBE_SUCCESS)
2940 /* Disable Flex from training TXFFE. */
2941 status = mac->ops.read_iosf_sb_reg(hw,
2942 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2943 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2944 if (status != IXGBE_SUCCESS)
2946 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2947 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2948 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2949 status = mac->ops.write_iosf_sb_reg(hw,
2950 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2951 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2952 if (status != IXGBE_SUCCESS)
2954 status = mac->ops.read_iosf_sb_reg(hw,
2955 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2956 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2957 if (status != IXGBE_SUCCESS)
2959 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2960 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2961 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2962 status = mac->ops.write_iosf_sb_reg(hw,
2963 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2964 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2965 if (status != IXGBE_SUCCESS)
2968 /* Enable override for coefficients. */
2969 status = mac->ops.read_iosf_sb_reg(hw,
2970 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2971 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2972 if (status != IXGBE_SUCCESS)
2974 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2975 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2976 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2977 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2978 status = mac->ops.write_iosf_sb_reg(hw,
2979 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2980 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2985 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2986 * @hw: pointer to hardware structure
2987 * @speed: the link speed to force
2989 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
2990 * internal and external PHY at a specific speed, without autonegotiation.
2992 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2994 struct ixgbe_mac_info *mac = &hw->mac;
2998 /* Disable AN and force speed to 10G Serial. */
2999 status = mac->ops.read_iosf_sb_reg(hw,
3000 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3001 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3002 if (status != IXGBE_SUCCESS)
3005 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3006 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3008 /* Select forced link speed for internal PHY. */
3010 case IXGBE_LINK_SPEED_10GB_FULL:
3011 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3013 case IXGBE_LINK_SPEED_1GB_FULL:
3014 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
3017 /* Other link speeds are not supported by internal KR PHY. */
3018 return IXGBE_ERR_LINK_SETUP;
3021 status = mac->ops.write_iosf_sb_reg(hw,
3022 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3023 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3024 if (status != IXGBE_SUCCESS)
3027 /* Additional configuration needed for x550em_x */
3028 if (hw->mac.type == ixgbe_mac_X550EM_x) {
3029 status = ixgbe_setup_ixfi_x550em_x(hw);
3030 if (status != IXGBE_SUCCESS)
3034 /* Toggle port SW reset by AN reset. */
3035 status = ixgbe_restart_an_internal_phy_x550em(hw);
3041 * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
3042 * @hw: address of hardware structure
3043 * @link_up: address of boolean to indicate link status
3045 * Returns error code if unable to get link status.
3047 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
3054 /* read this twice back to back to indicate current status */
3055 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3056 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3058 if (ret != IXGBE_SUCCESS)
3061 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3062 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3064 if (ret != IXGBE_SUCCESS)
3067 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
3069 return IXGBE_SUCCESS;
3073 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
3074 * @hw: point to hardware structure
3076 * Configures the link between the integrated KR PHY and the external X557 PHY
3077 * The driver will call this function when it gets a link status change
3078 * interrupt from the X557 PHY. This function configures the link speed
3079 * between the PHYs to match the link speed of the BASE-T link.
3081 * A return of a non-zero value indicates an error, and the base driver should
3082 * not report link up.
3084 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
3086 ixgbe_link_speed force_speed;
3091 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3092 return IXGBE_ERR_CONFIG;
3094 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3095 /* If link is down, there is no setup necessary so return */
3096 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3097 if (status != IXGBE_SUCCESS)
3101 return IXGBE_SUCCESS;
3103 status = hw->phy.ops.read_reg(hw,
3104 IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3105 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3107 if (status != IXGBE_SUCCESS)
3110 /* If link is still down - no setup is required so return */
3111 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3112 if (status != IXGBE_SUCCESS)
3115 return IXGBE_SUCCESS;
3117 /* clear everything but the speed and duplex bits */
3118 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
3121 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
3122 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3124 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
3125 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3128 /* Internal PHY does not support anything else */
3129 return IXGBE_ERR_INVALID_LINK_SETTINGS;
3132 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
3134 speed = IXGBE_LINK_SPEED_10GB_FULL |
3135 IXGBE_LINK_SPEED_1GB_FULL;
3136 return ixgbe_setup_kr_speed_x550em(hw, speed);
3141 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
3142 * @hw: pointer to hardware structure
3144 * Configures the integrated KR PHY to use internal loopback mode.
3146 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
3151 /* Disable AN and force speed to 10G Serial. */
3152 status = hw->mac.ops.read_iosf_sb_reg(hw,
3153 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3154 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3155 if (status != IXGBE_SUCCESS)
3157 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3158 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3159 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3160 status = hw->mac.ops.write_iosf_sb_reg(hw,
3161 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3162 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3163 if (status != IXGBE_SUCCESS)
3166 /* Set near-end loopback clocks. */
3167 status = hw->mac.ops.read_iosf_sb_reg(hw,
3168 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3169 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3170 if (status != IXGBE_SUCCESS)
3172 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3173 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3174 status = hw->mac.ops.write_iosf_sb_reg(hw,
3175 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3176 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3177 if (status != IXGBE_SUCCESS)
3180 /* Set loopback enable. */
3181 status = hw->mac.ops.read_iosf_sb_reg(hw,
3182 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3183 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3184 if (status != IXGBE_SUCCESS)
3186 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3187 status = hw->mac.ops.write_iosf_sb_reg(hw,
3188 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3189 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3190 if (status != IXGBE_SUCCESS)
3193 /* Training bypass. */
3194 status = hw->mac.ops.read_iosf_sb_reg(hw,
3195 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3196 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3197 if (status != IXGBE_SUCCESS)
3199 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3200 status = hw->mac.ops.write_iosf_sb_reg(hw,
3201 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3202 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3208 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3209 * assuming that the semaphore is already obtained.
3210 * @hw: pointer to hardware structure
3211 * @offset: offset of word in the EEPROM to read
3212 * @data: word read from the EEPROM
3214 * Reads a 16 bit word from the EEPROM using the hostif.
3216 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
3218 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3219 struct ixgbe_hic_read_shadow_ram buffer;
3222 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3223 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3224 buffer.hdr.req.buf_lenh = 0;
3225 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3226 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3228 /* convert offset from words to bytes */
3229 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3231 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3233 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3237 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3238 IXGBE_HI_COMMAND_TIMEOUT);
3240 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3241 FW_NVM_DATA_OFFSET);
3244 hw->mac.ops.release_swfw_sync(hw, mask);
3249 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3250 * @hw: pointer to hardware structure
3251 * @offset: offset of word in the EEPROM to read
3252 * @words: number of words
3253 * @data: word(s) read from the EEPROM
3255 * Reads a 16 bit word(s) from the EEPROM using the hostif.
3257 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3258 u16 offset, u16 words, u16 *data)
3260 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3261 struct ixgbe_hic_read_shadow_ram buffer;
3262 u32 current_word = 0;
3267 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3269 /* Take semaphore for the entire operation. */
3270 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3272 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3276 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3277 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3279 words_to_read = words;
3281 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3282 buffer.hdr.req.buf_lenh = 0;
3283 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3284 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3286 /* convert offset from words to bytes */
3287 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3288 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3290 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3291 IXGBE_HI_COMMAND_TIMEOUT);
3294 DEBUGOUT("Host interface command failed\n");
3298 for (i = 0; i < words_to_read; i++) {
3299 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3301 u32 value = IXGBE_READ_REG(hw, reg);
3303 data[current_word] = (u16)(value & 0xffff);
3306 if (i < words_to_read) {
3308 data[current_word] = (u16)(value & 0xffff);
3312 words -= words_to_read;
3316 hw->mac.ops.release_swfw_sync(hw, mask);
3321 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3322 * @hw: pointer to hardware structure
3323 * @offset: offset of word in the EEPROM to write
3324 * @data: word write to the EEPROM
3326 * Write a 16 bit word to the EEPROM using the hostif.
3328 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3332 struct ixgbe_hic_write_shadow_ram buffer;
3334 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3336 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3337 buffer.hdr.req.buf_lenh = 0;
3338 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3339 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3342 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3344 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3346 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3348 IXGBE_HI_COMMAND_TIMEOUT, false);
3354 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3355 * @hw: pointer to hardware structure
3356 * @offset: offset of word in the EEPROM to write
3357 * @data: word write to the EEPROM
3359 * Write a 16 bit word to the EEPROM using the hostif.
3361 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3364 s32 status = IXGBE_SUCCESS;
3366 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3368 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3370 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3371 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3373 DEBUGOUT("write ee hostif failed to get semaphore");
3374 status = IXGBE_ERR_SWFW_SYNC;
3381 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3382 * @hw: pointer to hardware structure
3383 * @offset: offset of word in the EEPROM to write
3384 * @words: number of words
3385 * @data: word(s) write to the EEPROM
3387 * Write a 16 bit word(s) to the EEPROM using the hostif.
3389 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3390 u16 offset, u16 words, u16 *data)
3392 s32 status = IXGBE_SUCCESS;
3395 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3397 /* Take semaphore for the entire operation. */
3398 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3399 if (status != IXGBE_SUCCESS) {
3400 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3404 for (i = 0; i < words; i++) {
3405 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3408 if (status != IXGBE_SUCCESS) {
3409 DEBUGOUT("Eeprom buffered write failed\n");
3414 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3421 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3422 * @hw: pointer to hardware structure
3423 * @ptr: pointer offset in eeprom
3424 * @size: size of section pointed by ptr, if 0 first word will be used as size
3425 * @csum: address of checksum to update
3427 * Returns error status for any failure
3429 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3430 u16 size, u16 *csum, u16 *buffer,
3435 u16 length, bufsz, i, start;
3438 bufsz = sizeof(buf) / sizeof(buf[0]);
3440 /* Read a chunk at the pointer location */
3442 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3444 DEBUGOUT("Failed to read EEPROM image\n");
3449 if (buffer_size < ptr)
3450 return IXGBE_ERR_PARAM;
3451 local_buffer = &buffer[ptr];
3459 length = local_buffer[0];
3461 /* Skip pointer section if length is invalid. */
3462 if (length == 0xFFFF || length == 0 ||
3463 (ptr + length) >= hw->eeprom.word_size)
3464 return IXGBE_SUCCESS;
3467 if (buffer && ((u32)start + (u32)length > buffer_size))
3468 return IXGBE_ERR_PARAM;
3470 for (i = start; length; i++, length--) {
3471 if (i == bufsz && !buffer) {
3477 /* Read a chunk at the pointer location */
3478 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3481 DEBUGOUT("Failed to read EEPROM image\n");
3485 *csum += local_buffer[i];
3487 return IXGBE_SUCCESS;
3491 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3492 * @hw: pointer to hardware structure
3493 * @buffer: pointer to buffer containing calculated checksum
3494 * @buffer_size: size of buffer
3496 * Returns a negative error code on error, or the 16-bit checksum
3498 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3500 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3504 u16 pointer, i, size;
3506 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3508 hw->eeprom.ops.init_params(hw);
3511 /* Read pointer area */
3512 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3513 IXGBE_EEPROM_LAST_WORD + 1,
3516 DEBUGOUT("Failed to read EEPROM image\n");
3519 local_buffer = eeprom_ptrs;
3521 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3522 return IXGBE_ERR_PARAM;
3523 local_buffer = buffer;
3527 * For X550 hardware include 0x0-0x41 in the checksum, skip the
3528 * checksum word itself
3530 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3531 if (i != IXGBE_EEPROM_CHECKSUM)
3532 checksum += local_buffer[i];
3535 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
3536 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3538 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3539 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3542 pointer = local_buffer[i];
3544 /* Skip pointer section if the pointer is invalid. */
3545 if (pointer == 0xFFFF || pointer == 0 ||
3546 pointer >= hw->eeprom.word_size)
3550 case IXGBE_PCIE_GENERAL_PTR:
3551 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3553 case IXGBE_PCIE_CONFIG0_PTR:
3554 case IXGBE_PCIE_CONFIG1_PTR:
3555 size = IXGBE_PCIE_CONFIG_SIZE;
3562 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3563 buffer, buffer_size);
3568 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3570 return (s32)checksum;
3574 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3575 * @hw: pointer to hardware structure
3577 * Returns a negative error code on error, or the 16-bit checksum
3579 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3581 return ixgbe_calc_checksum_X550(hw, NULL, 0);
3585 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3586 * @hw: pointer to hardware structure
3587 * @checksum_val: calculated checksum
3589 * Performs checksum calculation and validates the EEPROM checksum. If the
3590 * caller does not need checksum_val, the value can be NULL.
3592 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3596 u16 read_checksum = 0;
3598 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3600 /* Read the first word from the EEPROM. If this times out or fails, do
3601 * not continue or we could be in for a very long wait while every
3604 status = hw->eeprom.ops.read(hw, 0, &checksum);
3606 DEBUGOUT("EEPROM read failed\n");
3610 status = hw->eeprom.ops.calc_checksum(hw);
3614 checksum = (u16)(status & 0xffff);
3616 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3621 /* Verify read checksum from EEPROM is the same as
3622 * calculated checksum
3624 if (read_checksum != checksum) {
3625 status = IXGBE_ERR_EEPROM_CHECKSUM;
3626 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3627 "Invalid EEPROM checksum");
3630 /* If the user cares, return the calculated checksum */
3632 *checksum_val = checksum;
3638 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3639 * @hw: pointer to hardware structure
3641 * After writing EEPROM to shadow RAM using EEWR register, software calculates
3642 * checksum and updates the EEPROM and instructs the hardware to update
3645 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3650 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3652 /* Read the first word from the EEPROM. If this times out or fails, do
3653 * not continue or we could be in for a very long wait while every
3656 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3658 DEBUGOUT("EEPROM read failed\n");
3662 status = ixgbe_calc_eeprom_checksum_X550(hw);
3666 checksum = (u16)(status & 0xffff);
3668 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3673 status = ixgbe_update_flash_X550(hw);
3679 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3680 * @hw: pointer to hardware structure
3682 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3684 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3686 s32 status = IXGBE_SUCCESS;
3687 union ixgbe_hic_hdr2 buffer;
3689 DEBUGFUNC("ixgbe_update_flash_X550");
3691 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3692 buffer.req.buf_lenh = 0;
3693 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3694 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3696 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3698 IXGBE_HI_COMMAND_TIMEOUT, false);
3704 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3705 * @hw: pointer to hardware structure
3707 * Determines physical layer capabilities of the current configuration.
3709 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3711 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3712 u16 ext_ability = 0;
3714 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3716 hw->phy.ops.identify(hw);
3718 switch (hw->phy.type) {
3719 case ixgbe_phy_x550em_kr:
3720 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3721 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3723 case ixgbe_phy_x550em_kx4:
3724 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3725 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3727 case ixgbe_phy_x550em_ext_t:
3728 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3729 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3731 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3732 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3733 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3734 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3740 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3741 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3743 return physical_layer;
3747 * ixgbe_get_bus_info_x550em - Set PCI bus info
3748 * @hw: pointer to hardware structure
3750 * Sets bus link width and speed to unknown because X550em is
3753 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3756 DEBUGFUNC("ixgbe_get_bus_info_x550em");
3758 hw->bus.width = ixgbe_bus_width_unknown;
3759 hw->bus.speed = ixgbe_bus_speed_unknown;
3761 hw->mac.ops.set_lan_id(hw);
3763 return IXGBE_SUCCESS;
3767 * ixgbe_disable_rx_x550 - Disable RX unit
3769 * Enables the Rx DMA unit for x550
3771 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3773 u32 rxctrl, pfdtxgswc;
3775 struct ixgbe_hic_disable_rxen fw_cmd;
3777 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3779 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3780 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3781 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3782 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3783 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3784 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3785 hw->mac.set_lben = true;
3787 hw->mac.set_lben = false;
3790 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3791 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3792 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3793 fw_cmd.port_number = (u8)hw->bus.lan_id;
3795 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3796 sizeof(struct ixgbe_hic_disable_rxen),
3797 IXGBE_HI_COMMAND_TIMEOUT, true);
3799 /* If we fail - disable RX using register write */
3801 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3802 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3803 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3804 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3811 * ixgbe_enter_lplu_x550em - Transition to low power states
3812 * @hw: pointer to hardware structure
3814 * Configures Low Power Link Up on transition to low power states
3815 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3816 * X557 PHY immediately prior to entering LPLU.
3818 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3820 u16 an_10g_cntl_reg, autoneg_reg, speed;
3822 ixgbe_link_speed lcd_speed;
3826 /* SW LPLU not required on later HW revisions. */
3827 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3828 (IXGBE_FUSES0_REV_MASK &
3829 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3830 return IXGBE_SUCCESS;
3832 /* If blocked by MNG FW, then don't restart AN */
3833 if (ixgbe_check_reset_blocked(hw))
3834 return IXGBE_SUCCESS;
3836 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3837 if (status != IXGBE_SUCCESS)
3840 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3842 if (status != IXGBE_SUCCESS)
3845 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3846 * disabled, then force link down by entering low power mode.
3848 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3849 !(hw->wol_enabled || ixgbe_mng_present(hw)))
3850 return ixgbe_set_copper_phy_power(hw, FALSE);
3853 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3855 if (status != IXGBE_SUCCESS)
3858 /* If no valid LCD link speed, then force link down and exit. */
3859 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3860 return ixgbe_set_copper_phy_power(hw, FALSE);
3862 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3863 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3866 if (status != IXGBE_SUCCESS)
3869 /* If no link now, speed is invalid so take link down */
3870 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3871 if (status != IXGBE_SUCCESS)
3872 return ixgbe_set_copper_phy_power(hw, false);
3874 /* clear everything but the speed bits */
3875 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3877 /* If current speed is already LCD, then exit. */
3878 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3879 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3880 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3881 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3884 /* Clear AN completed indication */
3885 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3886 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3889 if (status != IXGBE_SUCCESS)
3892 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3893 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3896 if (status != IXGBE_SUCCESS)
3899 status = hw->phy.ops.read_reg(hw,
3900 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3901 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3904 if (status != IXGBE_SUCCESS)
3907 save_autoneg = hw->phy.autoneg_advertised;
3909 /* Setup link at least common link speed */
3910 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3912 /* restore autoneg from before setting lplu speed */
3913 hw->phy.autoneg_advertised = save_autoneg;
3919 * ixgbe_get_lcd_x550em - Determine lowest common denominator
3920 * @hw: pointer to hardware structure
3921 * @lcd_speed: pointer to lowest common link speed
3923 * Determine lowest common link speed with link partner.
3925 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3929 u16 word = hw->eeprom.ctrl_word_3;
3931 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3933 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3934 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3937 if (status != IXGBE_SUCCESS)
3940 /* If link partner advertised 1G, return 1G */
3941 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3942 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3946 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3947 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3948 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3951 /* Link partner not capable of lower speeds, return 10G */
3952 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3957 * ixgbe_setup_fc_X550em - Set up flow control
3958 * @hw: pointer to hardware structure
3960 * Called at init time to set up flow control.
3962 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3964 s32 ret_val = IXGBE_SUCCESS;
3965 u32 pause, asm_dir, reg_val;
3967 DEBUGFUNC("ixgbe_setup_fc_X550em");
3969 /* Validate the requested mode */
3970 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3971 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3972 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3973 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3977 /* 10gig parts do not have a word in the EEPROM to determine the
3978 * default flow control setting, so we explicitly set it to full.
3980 if (hw->fc.requested_mode == ixgbe_fc_default)
3981 hw->fc.requested_mode = ixgbe_fc_full;
3983 /* Determine PAUSE and ASM_DIR bits. */
3984 switch (hw->fc.requested_mode) {
3989 case ixgbe_fc_tx_pause:
3993 case ixgbe_fc_rx_pause:
3994 /* Rx Flow control is enabled and Tx Flow control is
3995 * disabled by software override. Since there really
3996 * isn't a way to advertise that we are capable of RX
3997 * Pause ONLY, we will advertise that we support both
3998 * symmetric and asymmetric Rx PAUSE, as such we fall
3999 * through to the fc_full statement. Later, we will
4000 * disable the adapter's ability to send PAUSE frames.
4007 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4008 "Flow control param set incorrectly\n");
4009 ret_val = IXGBE_ERR_CONFIG;
4013 switch (hw->device_id) {
4014 case IXGBE_DEV_ID_X550EM_X_KR:
4015 case IXGBE_DEV_ID_X550EM_A_KR:
4016 case IXGBE_DEV_ID_X550EM_A_KR_L:
4017 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
4018 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4019 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
4020 if (ret_val != IXGBE_SUCCESS)
4022 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4023 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4025 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4027 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4028 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
4029 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4030 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
4032 /* This device does not fully support AN. */
4033 hw->fc.disable_fc_autoneg = true;
4044 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
4045 * @hw: pointer to hardware structure
4047 * Enable flow control according to IEEE clause 37.
4049 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
4051 u32 link_s1, lp_an_page_low, an_cntl_1;
4052 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4053 ixgbe_link_speed speed;
4056 /* AN should have completed when the cable was plugged in.
4057 * Look for reasons to bail out. Bail out if:
4058 * - FC autoneg is disabled, or if
4061 if (hw->fc.disable_fc_autoneg) {
4062 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4063 "Flow control autoneg is disabled");
4067 hw->mac.ops.check_link(hw, &speed, &link_up, false);
4069 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4073 /* Check at auto-negotiation has completed */
4074 status = hw->mac.ops.read_iosf_sb_reg(hw,
4075 IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4076 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4078 if (status != IXGBE_SUCCESS ||
4079 (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4080 DEBUGOUT("Auto-Negotiation did not complete\n");
4081 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4085 /* Read the 10g AN autoc and LP ability registers and resolve
4086 * local flow control settings accordingly
4088 status = hw->mac.ops.read_iosf_sb_reg(hw,
4089 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4090 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
4092 if (status != IXGBE_SUCCESS) {
4093 DEBUGOUT("Auto-Negotiation did not complete\n");
4097 status = hw->mac.ops.read_iosf_sb_reg(hw,
4098 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
4099 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
4101 if (status != IXGBE_SUCCESS) {
4102 DEBUGOUT("Auto-Negotiation did not complete\n");
4106 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
4107 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
4108 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
4109 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
4110 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
4113 if (status == IXGBE_SUCCESS) {
4114 hw->fc.fc_was_autonegged = true;
4116 hw->fc.fc_was_autonegged = false;
4117 hw->fc.current_mode = hw->fc.requested_mode;
4122 * ixgbe_fc_autoneg_fiber_x550em_a - Enable flow control IEEE clause 37
4123 * @hw: pointer to hardware structure
4125 * Enable flow control according to IEEE clause 37.
4127 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
4129 u32 link_s1, pcs_an_lp, pcs_an;
4130 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4131 ixgbe_link_speed speed;
4134 /* AN should have completed when the cable was plugged in.
4135 * Look for reasons to bail out. Bail out if:
4136 * - FC autoneg is disabled, or if
4139 if (hw->fc.disable_fc_autoneg) {
4140 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4141 "Flow control autoneg is disabled");
4145 hw->mac.ops.check_link(hw, &speed, &link_up, false);
4147 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4151 /* Check if auto-negotiation has completed */
4152 status = hw->mac.ops.read_iosf_sb_reg(hw,
4153 IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4154 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4156 if (status != IXGBE_SUCCESS ||
4157 (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4158 DEBUGOUT("Auto-Negotiation did not complete\n");
4159 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4163 /* Determine advertised flow control */
4164 status = hw->mac.ops.read_iosf_sb_reg(hw,
4165 IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id),
4166 IXGBE_SB_IOSF_TARGET_KR_PHY, &pcs_an);
4168 if (status != IXGBE_SUCCESS) {
4169 DEBUGOUT("Auto-Negotiation did not complete\n");
4173 /* Determine link parter flow control */
4174 status = hw->mac.ops.read_iosf_sb_reg(hw,
4175 IXGBE_KRM_PCS_KX_AN_LP(hw->bus.lan_id),
4176 IXGBE_SB_IOSF_TARGET_KR_PHY, &pcs_an_lp);
4178 if (status != IXGBE_SUCCESS) {
4179 DEBUGOUT("Auto-Negotiation did not complete\n");
4183 status = ixgbe_negotiate_fc(hw, pcs_an, pcs_an_lp,
4184 IXGBE_KRM_PCS_KX_AN_SYM_PAUSE,
4185 IXGBE_KRM_PCS_KX_AN_ASM_PAUSE,
4186 IXGBE_KRM_PCS_KX_AN_LP_SYM_PAUSE,
4187 IXGBE_KRM_PCS_KX_AN_LP_ASM_PAUSE);
4190 if (status == IXGBE_SUCCESS) {
4191 hw->fc.fc_was_autonegged = true;
4193 hw->fc.fc_was_autonegged = false;
4194 hw->fc.current_mode = hw->fc.requested_mode;
4199 * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
4200 * @hw: pointer to hardware structure
4202 * Enable flow control according to IEEE clause 37.
4204 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
4206 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4207 u16 reg, pcs_an_lp, pcs_an;
4208 ixgbe_link_speed speed;
4211 /* AN should have completed when the cable was plugged in.
4212 * Look for reasons to bail out. Bail out if:
4213 * - FC autoneg is disabled, or if
4216 if (hw->fc.disable_fc_autoneg) {
4217 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4218 "Flow control autoneg is disabled");
4222 hw->mac.ops.check_link(hw, &speed, &link_up, false);
4224 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4228 /* Check if auto-negotiation has completed */
4229 status = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_STATUS,
4230 IXGBE_MDIO_ZERO_DEV_TYPE, ®);
4231 if (status != IXGBE_SUCCESS ||
4232 (reg & IXGBE_M88E1500_COPPER_STATUS_AN_DONE) == 0) {
4233 DEBUGOUT("Auto-Negotiation did not complete\n");
4234 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4238 /* Get the advertized flow control */
4239 status = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_AN,
4240 IXGBE_MDIO_ZERO_DEV_TYPE, &pcs_an);
4241 if (status != IXGBE_SUCCESS)
4244 /* Get link partner's flow control */
4245 status = hw->phy.ops.read_reg(hw,
4246 IXGBE_M88E1500_COPPER_AN_LP_ABILITY,
4247 IXGBE_MDIO_ZERO_DEV_TYPE, &pcs_an_lp);
4248 if (status != IXGBE_SUCCESS)
4251 /* Negotiate the flow control */
4252 status = ixgbe_negotiate_fc(hw, (u32)pcs_an, (u32)pcs_an_lp,
4253 IXGBE_M88E1500_COPPER_AN_PAUSE,
4254 IXGBE_M88E1500_COPPER_AN_AS_PAUSE,
4255 IXGBE_M88E1500_COPPER_AN_LP_PAUSE,
4256 IXGBE_M88E1500_COPPER_AN_LP_AS_PAUSE);
4259 if (status == IXGBE_SUCCESS) {
4260 hw->fc.fc_was_autonegged = true;
4262 hw->fc.fc_was_autonegged = false;
4263 hw->fc.current_mode = hw->fc.requested_mode;
4268 * ixgbe_setup_fc_sgmii_x550em_a - Set up flow control
4269 * @hw: pointer to hardware structure
4271 * Called at init time to set up flow control.
4273 s32 ixgbe_setup_fc_sgmii_x550em_a(struct ixgbe_hw *hw)
4278 /* Validate the requested mode */
4279 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4280 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4281 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4282 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4285 if (hw->fc.requested_mode == ixgbe_fc_default)
4286 hw->fc.requested_mode = ixgbe_fc_full;
4288 /* Read contents of the Auto-Negotiation register, page 0 reg 4 */
4289 rc = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_AN,
4290 IXGBE_MDIO_ZERO_DEV_TYPE, ®);
4294 /* Disable all the settings related to Flow control Auto-negotiation */
4295 reg &= ~IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4296 reg &= ~IXGBE_M88E1500_COPPER_AN_PAUSE;
4298 /* Configure the Asymmetric and symmetric pause according to the user
4301 switch (hw->fc.requested_mode) {
4303 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
4304 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4306 case ixgbe_fc_rx_pause:
4307 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
4308 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4310 case ixgbe_fc_tx_pause:
4311 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4317 /* Write back to the Auto-Negotiation register with newly configured
4320 hw->phy.ops.write_reg(hw, IXGBE_M88E1500_COPPER_AN,
4321 IXGBE_MDIO_ZERO_DEV_TYPE, reg);
4323 /* In this section of the code we restart Auto-negotiation */
4325 /* Read the CONTROL register, Page 0 reg 0 */
4326 rc = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_CTRL,
4327 IXGBE_MDIO_ZERO_DEV_TYPE, ®);
4331 /* Set the bit to restart Auto-Neg. The bit to enable Auto-neg is ON
4334 reg |= IXGBE_M88E1500_COPPER_CTRL_RESTART_AN;
4336 /* write the new values to the register to restart Auto-Negotiation */
4337 hw->phy.ops.write_reg(hw, IXGBE_M88E1500_COPPER_CTRL,
4338 IXGBE_MDIO_ZERO_DEV_TYPE, reg);
4345 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4346 * @hw: pointer to hardware structure
4348 * Called at init time to set up flow control.
4350 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4352 s32 status = IXGBE_SUCCESS;
4355 DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4357 /* Validate the requested mode */
4358 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4359 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4360 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4361 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4364 if (hw->fc.requested_mode == ixgbe_fc_default)
4365 hw->fc.requested_mode = ixgbe_fc_full;
4367 /* Set up the 1G and 10G flow control advertisement registers so the
4368 * HW will be able to do FC autoneg once the cable is plugged in. If
4369 * we link at 10G, the 1G advertisement is harmless and vice versa.
4371 status = hw->mac.ops.read_iosf_sb_reg(hw,
4372 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4373 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4375 if (status != IXGBE_SUCCESS) {
4376 DEBUGOUT("Auto-Negotiation did not complete\n");
4380 /* The possible values of fc.requested_mode are:
4381 * 0: Flow control is completely disabled
4382 * 1: Rx flow control is enabled (we can receive pause frames,
4383 * but not send pause frames).
4384 * 2: Tx flow control is enabled (we can send pause frames but
4385 * we do not support receiving pause frames).
4386 * 3: Both Rx and Tx flow control (symmetric) are enabled.
4389 switch (hw->fc.requested_mode) {
4391 /* Flow control completely disabled by software override. */
4392 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4393 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4395 case ixgbe_fc_tx_pause:
4396 /* Tx Flow control is enabled, and Rx Flow control is
4397 * disabled by software override.
4399 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4400 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4402 case ixgbe_fc_rx_pause:
4403 /* Rx Flow control is enabled and Tx Flow control is
4404 * disabled by software override. Since there really
4405 * isn't a way to advertise that we are capable of RX
4406 * Pause ONLY, we will advertise that we support both
4407 * symmetric and asymmetric Rx PAUSE, as such we fall
4408 * through to the fc_full statement. Later, we will
4409 * disable the adapter's ability to send PAUSE frames.
4412 /* Flow control (both Rx and Tx) is enabled by SW override. */
4413 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4414 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4417 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4418 "Flow control param set incorrectly\n");
4419 return IXGBE_ERR_CONFIG;
4422 status = hw->mac.ops.write_iosf_sb_reg(hw,
4423 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4424 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4426 /* Restart auto-negotiation. */
4427 status = ixgbe_restart_an_internal_phy_x550em(hw);
4433 * ixgbe_setup_fc_fiber_x550em_a - Set up flow control
4434 * @hw: pointer to hardware structure
4436 * Called at init time to set up flow control.
4438 s32 ixgbe_setup_fc_fiber_x550em_a(struct ixgbe_hw *hw)
4440 struct ixgbe_mac_info *mac = &hw->mac;
4441 s32 rc = IXGBE_SUCCESS;
4442 u32 an_cntl4, lctrl, pcs_an;
4444 DEBUGFUNC("ixgbe_setup_fc_fiber_x550em_a");
4446 /* Validate the requested mode */
4447 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4448 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4449 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4450 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4453 /* Enable clause 37 auto-negotiation in KRM_LINK_CTRL_1 */
4454 if (hw->fc.requested_mode == ixgbe_fc_default)
4455 hw->fc.requested_mode = ixgbe_fc_full;
4457 rc = mac->ops.read_iosf_sb_reg(hw,
4458 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4459 IXGBE_SB_IOSF_TARGET_KR_PHY, &lctrl);
4463 lctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
4464 lctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
4466 rc = mac->ops.write_iosf_sb_reg(hw,
4467 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4468 IXGBE_SB_IOSF_TARGET_KR_PHY, lctrl);
4472 /* Enable clause 37 over 73 in KRM_AN_CNTL_4 */
4473 rc = mac->ops.read_iosf_sb_reg(hw,
4474 IXGBE_KRM_AN_CNTL_4(hw->bus.lan_id),
4475 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl4);
4479 an_cntl4 |= IXGBE_KRM_AN_CNTL_4_ECSR_AN37_OVER_73;
4481 rc = mac->ops.write_iosf_sb_reg(hw,
4482 IXGBE_KRM_AN_CNTL_4(hw->bus.lan_id),
4483 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl4);
4487 rc = hw->mac.ops.read_iosf_sb_reg(hw,
4488 IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id),
4489 IXGBE_SB_IOSF_TARGET_KR_PHY, &pcs_an);
4494 /* The possible values of fc.requested_mode are:
4495 * 0: Flow control is completely disabled
4496 * 1: Rx flow control is enabled (we can receive pause frames,
4497 * but not send pause frames).
4498 * 2: Tx flow control is enabled (we can send pause frames but
4499 * we do not support receiving pause frames).
4500 * 3: Both Rx and Tx flow control (symmetric) are enabled.
4503 switch (hw->fc.requested_mode) {
4505 /* Flow control completely disabled by software override. */
4506 pcs_an &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4507 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4509 case ixgbe_fc_tx_pause:
4510 /* Tx Flow control is enabled, and Rx Flow control is
4511 * disabled by software override.
4513 pcs_an |= IXGBE_KRM_PCS_KX_AN_ASM_PAUSE;
4514 pcs_an &= ~IXGBE_KRM_PCS_KX_AN_SYM_PAUSE;
4516 case ixgbe_fc_rx_pause:
4517 /* Rx Flow control is enabled and Tx Flow control is
4518 * disabled by software override. Since there really
4519 * isn't a way to advertise that we are capable of RX
4520 * Pause ONLY, we will advertise that we support both
4521 * symmetric and asymmetric Rx PAUSE, as such we fall
4522 * through to the fc_full statement. Later, we will
4523 * disable the adapter's ability to send PAUSE frames.
4526 /* Flow control (both Rx and Tx) is enabled by SW override. */
4527 pcs_an |= IXGBE_KRM_PCS_KX_AN_SYM_PAUSE |
4528 IXGBE_KRM_PCS_KX_AN_ASM_PAUSE;
4531 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4532 "Flow control param set incorrectly\n");
4533 return IXGBE_ERR_CONFIG;
4536 rc = hw->mac.ops.write_iosf_sb_reg(hw,
4537 IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id),
4538 IXGBE_SB_IOSF_TARGET_KR_PHY, pcs_an);
4540 /* Restart auto-negotiation. */
4541 rc = ixgbe_restart_an_internal_phy_x550em(hw);
4547 * ixgbe_set_mux - Set mux for port 1 access with CS4227
4548 * @hw: pointer to hardware structure
4549 * @state: set mux if 1, clear if 0
4551 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4555 if (!hw->bus.lan_id)
4557 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4559 esdp |= IXGBE_ESDP_SDP1;
4561 esdp &= ~IXGBE_ESDP_SDP1;
4562 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4563 IXGBE_WRITE_FLUSH(hw);
4567 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4568 * @hw: pointer to hardware structure
4569 * @mask: Mask to specify which semaphore to acquire
4571 * Acquires the SWFW semaphore and sets the I2C MUX
4573 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4577 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4579 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4583 if (mask & IXGBE_GSSR_I2C_MASK)
4584 ixgbe_set_mux(hw, 1);
4586 return IXGBE_SUCCESS;
4590 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4591 * @hw: pointer to hardware structure
4592 * @mask: Mask to specify which semaphore to release
4594 * Releases the SWFW semaphore and sets the I2C MUX
4596 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4598 DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4600 if (mask & IXGBE_GSSR_I2C_MASK)
4601 ixgbe_set_mux(hw, 0);
4603 ixgbe_release_swfw_sync_X540(hw, mask);
4607 * ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4608 * @hw: pointer to hardware structure
4609 * @mask: Mask to specify which semaphore to acquire
4611 * Acquires the SWFW semaphore and get the shared phy token as needed
4613 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4615 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4616 int retries = FW_PHY_TOKEN_RETRIES;
4617 s32 status = IXGBE_SUCCESS;
4619 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4622 status = IXGBE_SUCCESS;
4624 status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4627 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4628 return IXGBE_SUCCESS;
4630 status = ixgbe_get_phy_token(hw);
4631 if (status == IXGBE_SUCCESS)
4632 return IXGBE_SUCCESS;
4635 ixgbe_release_swfw_sync_X540(hw, hmask);
4636 if (status != IXGBE_ERR_TOKEN_RETRY)
4644 * ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4645 * @hw: pointer to hardware structure
4646 * @mask: Mask to specify which semaphore to release
4648 * Releases the SWFW semaphore and puts the shared phy token as needed
4650 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4652 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4654 DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4656 if (mask & IXGBE_GSSR_TOKEN_SM)
4657 ixgbe_put_phy_token(hw);
4660 ixgbe_release_swfw_sync_X540(hw, hmask);
4664 * ixgbe_read_phy_reg_x550a - Reads specified PHY register
4665 * @hw: pointer to hardware structure
4666 * @reg_addr: 32 bit address of PHY register to read
4667 * @phy_data: Pointer to read data from PHY register
4669 * Reads a value from a specified PHY register using the SWFW lock and PHY
4670 * Token. The PHY Token is needed since the MDIO is shared between to MAC
4673 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4674 u32 device_type, u16 *phy_data)
4677 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4679 DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4681 if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4682 return IXGBE_ERR_SWFW_SYNC;
4684 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4686 hw->mac.ops.release_swfw_sync(hw, mask);
4692 * ixgbe_write_phy_reg_x550a - Writes specified PHY register
4693 * @hw: pointer to hardware structure
4694 * @reg_addr: 32 bit PHY register to write
4695 * @device_type: 5 bit device type
4696 * @phy_data: Data to write to the PHY register
4698 * Writes a value to specified PHY register using the SWFW lock and PHY Token.
4699 * The PHY Token is needed since the MDIO is shared between to MAC instances.
4701 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4702 u32 device_type, u16 phy_data)
4705 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4707 DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4709 if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4710 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
4712 hw->mac.ops.release_swfw_sync(hw, mask);
4714 status = IXGBE_ERR_SWFW_SYNC;
4721 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4722 * @hw: pointer to hardware structure
4724 * Handle external Base T PHY interrupt. If high temperature
4725 * failure alarm then return error, else if link status change
4726 * then setup internal/external PHY link
4728 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4729 * failure alarm, else return PHY access status.
4731 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4736 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4738 if (status != IXGBE_SUCCESS)
4742 return ixgbe_setup_internal_phy(hw);
4744 return IXGBE_SUCCESS;
4748 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4749 * @hw: pointer to hardware structure
4750 * @speed: new link speed
4751 * @autoneg_wait_to_complete: true when waiting for completion is needed
4753 * Setup internal/external PHY link speed based on link speed, then set
4754 * external PHY auto advertised link speed.
4756 * Returns error status for any failure
4758 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4759 ixgbe_link_speed speed,
4760 bool autoneg_wait_to_complete)
4763 ixgbe_link_speed force_speed;
4765 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4767 /* Setup internal/external PHY link speed to iXFI (10G), unless
4768 * only 1G is auto advertised then setup KX link.
4770 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4771 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4773 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4775 /* If internal link mode is XFI, then setup XFI internal link. */
4776 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4777 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4779 if (status != IXGBE_SUCCESS)
4783 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4787 * ixgbe_check_link_t_X550em - Determine link and speed status
4788 * @hw: pointer to hardware structure
4789 * @speed: pointer to link speed
4790 * @link_up: true when link is up
4791 * @link_up_wait_to_complete: bool used to wait for link up or not
4793 * Check that both the MAC and X557 external PHY have link.
4795 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4796 bool *link_up, bool link_up_wait_to_complete)
4801 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4802 return IXGBE_ERR_CONFIG;
4804 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4805 link_up_wait_to_complete);
4807 /* If check link fails or MAC link is not up, then return */
4808 if (status != IXGBE_SUCCESS || !(*link_up))
4811 /* MAC link is up, so check external PHY link.
4812 * Read this twice back to back to indicate current status.
4814 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4815 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4818 if (status != IXGBE_SUCCESS)
4821 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4822 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4825 if (status != IXGBE_SUCCESS)
4828 /* If external PHY link is not up, then indicate link not up */
4829 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4832 return IXGBE_SUCCESS;
4836 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4837 * @hw: pointer to hardware structure
4839 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4843 status = ixgbe_reset_phy_generic(hw);
4845 if (status != IXGBE_SUCCESS)
4848 /* Configure Link Status Alarm and Temperature Threshold interrupts */
4849 return ixgbe_enable_lasi_ext_t_x550em(hw);
4853 * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4854 * @hw: pointer to hardware structure
4855 * @led_idx: led number to turn on
4857 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4861 DEBUGFUNC("ixgbe_led_on_t_X550em");
4863 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4864 return IXGBE_ERR_PARAM;
4866 /* To turn on the LED, set mode to ON. */
4867 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4868 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4869 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4870 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4871 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4873 return IXGBE_SUCCESS;
4877 * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4878 * @hw: pointer to hardware structure
4879 * @led_idx: led number to turn off
4881 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4885 DEBUGFUNC("ixgbe_led_off_t_X550em");
4887 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4888 return IXGBE_ERR_PARAM;
4890 /* To turn on the LED, set mode to ON. */
4891 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4892 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4893 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4894 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4895 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4897 return IXGBE_SUCCESS;