drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  44 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw);
  45
  46 /**
  47  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  48  *  @hw: pointer to hardware structure
  49  *
  50  *  Initialize the function pointers and assign the MAC type for X550.
  51  *  Does not touch the hardware.
  52  **/
  53 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  54 {
  55         struct ixgbe_mac_info *mac = &hw->mac;
  56         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  57         s32 ret_val;
  58
  59         DEBUGFUNC("ixgbe_init_ops_X550");
  60
  61         ret_val = ixgbe_init_ops_X540(hw);
  62         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  63         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  64         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  65         mac->ops.setup_eee = NULL;
  66         mac->ops.set_source_address_pruning =
  67                         ixgbe_set_source_address_pruning_X550;
  68         mac->ops.set_ethertype_anti_spoofing =
  69                         ixgbe_set_ethertype_anti_spoofing_X550;
  70
  71         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  72         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  73         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  74         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  75         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  76         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  77         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  78         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  79         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  80
  81         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  82         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  83         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  84         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  85         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  86         /* Manageability interface */
  87         mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_x550;
  88         switch (hw->device_id) {
  89         case IXGBE_DEV_ID_X550EM_X_10G_T:
  90         case IXGBE_DEV_ID_X550EM_A_10G_T:
  91                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  92                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  93                 break;
  94         default:
  95                 break;
  96         }
  97         return ret_val;
  98 }
  99
 100 /**
 101  * ixgbe_read_cs4227 - Read CS4227 register
 102  * @hw: pointer to hardware structure
 103  * @reg: register number to write
 104  * @value: pointer to receive value read
 105  *
 106  * Returns status code
 107  **/
 108 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
 109 {
 110         return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
 111 }
 112
 113 /**
 114  * ixgbe_write_cs4227 - Write CS4227 register
 115  * @hw: pointer to hardware structure
 116  * @reg: register number to write
 117  * @value: value to write to register
 118  *
 119  * Returns status code
 120  **/
 121 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 122 {
 123         return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
 124 }
 125
 126 /**
 127  * ixgbe_read_pe - Read register from port expander
 128  * @hw: pointer to hardware structure
 129  * @reg: register number to read
 130  * @value: pointer to receive read value
 131  *
 132  * Returns status code
 133  **/
 134 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 135 {
 136         s32 status;
 137
 138         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 139         if (status != IXGBE_SUCCESS)
 140                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 141                               "port expander access failed with %d\n", status);
 142         return status;
 143 }
 144
 145 /**
 146  * ixgbe_write_pe - Write register to port expander
 147  * @hw: pointer to hardware structure
 148  * @reg: register number to write
 149  * @value: value to write
 150  *
 151  * Returns status code
 152  **/
 153 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 154 {
 155         s32 status;
 156
 157         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 158         if (status != IXGBE_SUCCESS)
 159                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 160                               "port expander access failed with %d\n", status);
 161         return status;
 162 }
 163
 164 /**
 165  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 166  * @hw: pointer to hardware structure
 167  *
 168  * This function assumes that the caller has acquired the proper semaphore.
 169  * Returns error code
 170  **/
 171 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 172 {
 173         s32 status;
 174         u32 retry;
 175         u16 value;
 176         u8 reg;
 177
 178         /* Trigger hard reset. */
 179         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 180         if (status != IXGBE_SUCCESS)
 181                 return status;
 182         reg |= IXGBE_PE_BIT1;
 183         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 184         if (status != IXGBE_SUCCESS)
 185                 return status;
 186
 187         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 188         if (status != IXGBE_SUCCESS)
 189                 return status;
 190         reg &= ~IXGBE_PE_BIT1;
 191         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 192         if (status != IXGBE_SUCCESS)
 193                 return status;
 194
 195         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 196         if (status != IXGBE_SUCCESS)
 197                 return status;
 198         reg &= ~IXGBE_PE_BIT1;
 199         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 200         if (status != IXGBE_SUCCESS)
 201                 return status;
 202
 203         usec_delay(IXGBE_CS4227_RESET_HOLD);
 204
 205         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 206         if (status != IXGBE_SUCCESS)
 207                 return status;
 208         reg |= IXGBE_PE_BIT1;
 209         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 210         if (status != IXGBE_SUCCESS)
 211                 return status;
 212
 213         /* Wait for the reset to complete. */
 214         msec_delay(IXGBE_CS4227_RESET_DELAY);
 215         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 216                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 217                                            &value);
 218                 if (status == IXGBE_SUCCESS &&
 219                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 220                         break;
 221                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 222         }
 223         if (retry == IXGBE_CS4227_RETRIES) {
 224                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 225                         "CS4227 reset did not complete.");
 226                 return IXGBE_ERR_PHY;
 227         }
 228
 229         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 230         if (status != IXGBE_SUCCESS ||
 231             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 232                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 233                         "CS4227 EEPROM did not load successfully.");
 234                 return IXGBE_ERR_PHY;
 235         }
 236
 237         return IXGBE_SUCCESS;
 238 }
 239
 240 /**
 241  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 242  * @hw: pointer to hardware structure
 243  **/
 244 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 245 {
 246         s32 status = IXGBE_SUCCESS;
 247         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 248         u16 value = 0;
 249         u8 retry;
 250
 251         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 252                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 253                 if (status != IXGBE_SUCCESS) {
 254                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 255                                 "semaphore failed with %d", status);
 256                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 257                         continue;
 258                 }
 259
 260                 /* Get status of reset flow. */
 261                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 262
 263                 if (status == IXGBE_SUCCESS &&
 264                     value == IXGBE_CS4227_RESET_COMPLETE)
 265                         goto out;
 266
 267                 if (status != IXGBE_SUCCESS ||
 268                     value != IXGBE_CS4227_RESET_PENDING)
 269                         break;
 270
 271                 /* Reset is pending. Wait and check again. */
 272                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 273                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 274         }
 275
 276         /* If still pending, assume other instance failed. */
 277         if (retry == IXGBE_CS4227_RETRIES) {
 278                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 279                 if (status != IXGBE_SUCCESS) {
 280                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 281                                       "semaphore failed with %d", status);
 282                         return;
 283                 }
 284         }
 285
 286         /* Reset the CS4227. */
 287         status = ixgbe_reset_cs4227(hw);
 288         if (status != IXGBE_SUCCESS) {
 289                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 290                         "CS4227 reset failed: %d", status);
 291                 goto out;
 292         }
 293
 294         /* Reset takes so long, temporarily release semaphore in case the
 295          * other driver instance is waiting for the reset indication.
 296          */
 297         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 298                            IXGBE_CS4227_RESET_PENDING);
 299         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 300         msec_delay(10);
 301         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 302         if (status != IXGBE_SUCCESS) {
 303                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 304                         "semaphore failed with %d", status);
 305                 return;
 306         }
 307
 308         /* Record completion for next time. */
 309         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 310                 IXGBE_CS4227_RESET_COMPLETE);
 311
 312 out:
 313         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 314         msec_delay(hw->eeprom.semaphore_delay);
 315 }
 316
 317 /**
 318  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 319  * @hw: pointer to hardware structure
 320  **/
 321 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 322 {
 323         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 324
 325         if (hw->bus.lan_id) {
 326                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 327                 esdp |= IXGBE_ESDP_SDP1_DIR;
 328         }
 329         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 330         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 331         IXGBE_WRITE_FLUSH(hw);
 332 }
 333
 334 /**
 335  * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
 336  * @hw: pointer to hardware structure
 337  * @reg_addr: 32 bit address of PHY register to read
 338  * @dev_type: always unused
 339  * @phy_data: Pointer to read data from PHY register
 340  */
 341 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 342                                      u32 dev_type, u16 *phy_data)
 343 {
 344         u32 i, data, command;
 345         UNREFERENCED_1PARAMETER(dev_type);
 346
 347         /* Setup and write the read command */
 348         command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 349                   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 350                   IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
 351                   IXGBE_MSCA_MDI_COMMAND;
 352
 353         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 354
 355         /* Check every 10 usec to see if the access completed.
 356          * The MDI Command bit will clear when the operation is
 357          * complete
 358          */
 359         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 360                 usec_delay(10);
 361
 362                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 363                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 364                         break;
 365         }
 366
 367         if (command & IXGBE_MSCA_MDI_COMMAND) {
 368                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 369                               "PHY read command did not complete.\n");
 370                 return IXGBE_ERR_PHY;
 371         }
 372
 373         /* Read operation is complete.  Get the data from MSRWD */
 374         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 375         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 376         *phy_data = (u16)data;
 377
 378         return IXGBE_SUCCESS;
 379 }
 380
 381 /**
 382  * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
 383  * @hw: pointer to hardware structure
 384  * @reg_addr: 32 bit PHY register to write
 385  * @dev_type: always unused
 386  * @phy_data: Data to write to the PHY register
 387  */
 388 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 389                                       u32 dev_type, u16 phy_data)
 390 {
 391         u32 i, command;
 392         UNREFERENCED_1PARAMETER(dev_type);
 393
 394         /* Put the data in the MDI single read and write data register*/
 395         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 396
 397         /* Setup and write the write command */
 398         command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 399                   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 400                   IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
 401                   IXGBE_MSCA_MDI_COMMAND;
 402
 403         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 404
 405         /* Check every 10 usec to see if the access completed.
 406          * The MDI Command bit will clear when the operation is
 407          * complete
 408          */
 409         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 410                 usec_delay(10);
 411
 412                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 413                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 414                         break;
 415         }
 416
 417         if (command & IXGBE_MSCA_MDI_COMMAND) {
 418                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 419                               "PHY write cmd didn't complete\n");
 420                 return IXGBE_ERR_PHY;
 421         }
 422
 423         return IXGBE_SUCCESS;
 424 }
 425
 426 /**
 427  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 428  * @hw: pointer to hardware structure
 429  *
 430  * Returns error code
 431  */
 432 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 433 {
 434         hw->mac.ops.set_lan_id(hw);
 435
 436         ixgbe_read_mng_if_sel_x550em(hw);
 437
 438         switch (hw->device_id) {
 439         case IXGBE_DEV_ID_X550EM_A_SFP:
 440                 return ixgbe_identify_module_generic(hw);
 441         case IXGBE_DEV_ID_X550EM_X_SFP:
 442                 /* set up for CS4227 usage */
 443                 ixgbe_setup_mux_ctl(hw);
 444                 ixgbe_check_cs4227(hw);
 445                 /* Fallthrough */
 446
 447         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 448                 return ixgbe_identify_module_generic(hw);
 449                 break;
 450         case IXGBE_DEV_ID_X550EM_X_KX4:
 451                 hw->phy.type = ixgbe_phy_x550em_kx4;
 452                 break;
 453         case IXGBE_DEV_ID_X550EM_X_KR:
 454         case IXGBE_DEV_ID_X550EM_A_KR:
 455         case IXGBE_DEV_ID_X550EM_A_KR_L:
 456                 hw->phy.type = ixgbe_phy_x550em_kr;
 457                 break;
 458         case IXGBE_DEV_ID_X550EM_A_10G_T:
 459         case IXGBE_DEV_ID_X550EM_X_1G_T:
 460         case IXGBE_DEV_ID_X550EM_X_10G_T:
 461                 return ixgbe_identify_phy_generic(hw);
 462         case IXGBE_DEV_ID_X550EM_A_1G_T:
 463         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 464                 hw->phy.type = ixgbe_phy_fw;
 465                 hw->phy.ops.read_reg = NULL;
 466                 hw->phy.ops.write_reg = NULL;
 467                 if (hw->bus.lan_id)
 468                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 469                 else
 470                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 471                 break;
 472         default:
 473                 break;
 474         }
 475         return IXGBE_SUCCESS;
 476 }
 477
 478 /**
 479  * ixgbe_fw_phy_activity - Perform an activity on a PHY
 480  * @hw: pointer to hardware structure
 481  * @activity: activity to perform
 482  * @data: Pointer to 4 32-bit words of data
 483  */
 484 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,
 485                           u32 (*data)[FW_PHY_ACT_DATA_COUNT])
 486 {
 487         union {
 488                 struct ixgbe_hic_phy_activity_req cmd;
 489                 struct ixgbe_hic_phy_activity_resp rsp;
 490         } hic;
 491         u16 retries = FW_PHY_ACT_RETRIES;
 492         s32 rc;
 493         u16 i;
 494
 495         do {
 496                 memset(&hic, 0, sizeof(hic));
 497                 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD;
 498                 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN;
 499                 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 500                 hic.cmd.port_number = hw->bus.lan_id;
 501                 hic.cmd.activity_id = IXGBE_CPU_TO_LE16(activity);
 502                 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
 503                         hic.cmd.data[i] = IXGBE_CPU_TO_BE32((*data)[i]);
 504
 505                 rc = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
 506                                                   sizeof(hic.cmd),
 507                                                   IXGBE_HI_COMMAND_TIMEOUT,
 508                                                   true);
 509                 if (rc != IXGBE_SUCCESS)
 510                         return rc;
 511                 if (hic.rsp.hdr.cmd_or_resp.ret_status ==
 512                     FW_CEM_RESP_STATUS_SUCCESS) {
 513                         for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
 514                                 (*data)[i] = IXGBE_BE32_TO_CPU(hic.rsp.data[i]);
 515                         return IXGBE_SUCCESS;
 516                 }
 517                 usec_delay(20);
 518                 --retries;
 519         } while (retries > 0);
 520
 521         return IXGBE_ERR_HOST_INTERFACE_COMMAND;
 522 }
 523
 524 static const struct {
 525         u16 fw_speed;
 526         ixgbe_link_speed phy_speed;
 527 } ixgbe_fw_map[] = {
 528         { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL },
 529         { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL },
 530         { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL },
 531         { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL },
 532         { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL },
 533         { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL },
 534 };
 535
 536 /**
 537  * ixgbe_get_phy_id_fw - Get the phy ID via firmware command
 538  * @hw: pointer to hardware structure
 539  *
 540  * Returns error code
 541  */
 542 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw)
 543 {
 544         u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
 545         u16 phy_speeds;
 546         u16 phy_id_lo;
 547         s32 rc;
 548         u16 i;
 549
 550         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info);
 551         if (rc)
 552                 return rc;
 553
 554         hw->phy.speeds_supported = 0;
 555         phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK;
 556         for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
 557                 if (phy_speeds & ixgbe_fw_map[i].fw_speed)
 558                         hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed;
 559         }
 560         if (!hw->phy.autoneg_advertised)
 561                 hw->phy.autoneg_advertised = hw->phy.speeds_supported;
 562
 563         hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK;
 564         phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK;
 565         hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK;
 566         hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK;
 567         if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK)
 568                 return IXGBE_ERR_PHY_ADDR_INVALID;
 569         return IXGBE_SUCCESS;
 570 }
 571
 572 /**
 573  * ixgbe_identify_phy_fw - Get PHY type based on firmware command
 574  * @hw: pointer to hardware structure
 575  *
 576  * Returns error code
 577  */
 578 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw)
 579 {
 580         if (hw->bus.lan_id)
 581                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 582         else
 583                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 584
 585         hw->phy.type = ixgbe_phy_fw;
 586         hw->phy.ops.read_reg = NULL;
 587         hw->phy.ops.write_reg = NULL;
 588         return ixgbe_get_phy_id_fw(hw);
 589 }
 590
 591 /**
 592  * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY
 593  * @hw: pointer to hardware structure
 594  *
 595  * Returns error code
 596  */
 597 s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw)
 598 {
 599         u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
 600
 601         setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF;
 602         return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup);
 603 }
 604
 605 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 606                                      u32 device_type, u16 *phy_data)
 607 {
 608         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 609         return IXGBE_NOT_IMPLEMENTED;
 610 }
 611
 612 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 613                                       u32 device_type, u16 phy_data)
 614 {
 615         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 616         return IXGBE_NOT_IMPLEMENTED;
 617 }
 618
 619 /**
 620  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 621  * @hw: pointer to the hardware structure
 622  * @addr: I2C bus address to read from
 623  * @reg: I2C device register to read from
 624  * @val: pointer to location to receive read value
 625  *
 626  * Returns an error code on error.
 627  **/
 628 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 629                                            u16 reg, u16 *val)
 630 {
 631         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 632 }
 633
 634 /**
 635  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 636  * @hw: pointer to the hardware structure
 637  * @addr: I2C bus address to read from
 638  * @reg: I2C device register to read from
 639  * @val: pointer to location to receive read value
 640  *
 641  * Returns an error code on error.
 642  **/
 643 STATIC s32
 644 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 645                                          u16 reg, u16 *val)
 646 {
 647         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 648 }
 649
 650 /**
 651  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 652  * @hw: pointer to the hardware structure
 653  * @addr: I2C bus address to write to
 654  * @reg: I2C device register to write to
 655  * @val: value to write
 656  *
 657  * Returns an error code on error.
 658  **/
 659 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 660                                             u8 addr, u16 reg, u16 val)
 661 {
 662         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 663 }
 664
 665 /**
 666  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 667  * @hw: pointer to the hardware structure
 668  * @addr: I2C bus address to write to
 669  * @reg: I2C device register to write to
 670  * @val: value to write
 671  *
 672  * Returns an error code on error.
 673  **/
 674 STATIC s32
 675 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 676                                           u8 addr, u16 reg, u16 val)
 677 {
 678         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 679 }
 680
 681 /**
 682 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 683 *  @hw: pointer to hardware structure
 684 *
 685 *  Initialize the function pointers and for MAC type X550EM.
 686 *  Does not touch the hardware.
 687 **/
 688 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 689 {
 690         struct ixgbe_mac_info *mac = &hw->mac;
 691         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 692         struct ixgbe_phy_info *phy = &hw->phy;
 693         s32 ret_val;
 694
 695         DEBUGFUNC("ixgbe_init_ops_X550EM");
 696
 697         /* Similar to X550 so start there. */
 698         ret_val = ixgbe_init_ops_X550(hw);
 699
 700         /* Since this function eventually calls
 701          * ixgbe_init_ops_540 by design, we are setting
 702          * the pointers to NULL explicitly here to overwrite
 703          * the values being set in the x540 function.
 704          */
 705         /* Thermal sensor not supported in x550EM */
 706         mac->ops.get_thermal_sensor_data = NULL;
 707         mac->ops.init_thermal_sensor_thresh = NULL;
 708         mac->thermal_sensor_enabled = false;
 709
 710         /* FCOE not supported in x550EM */
 711         mac->ops.get_san_mac_addr = NULL;
 712         mac->ops.set_san_mac_addr = NULL;
 713         mac->ops.get_wwn_prefix = NULL;
 714         mac->ops.get_fcoe_boot_status = NULL;
 715
 716         /* IPsec not supported in x550EM */
 717         mac->ops.disable_sec_rx_path = NULL;
 718         mac->ops.enable_sec_rx_path = NULL;
 719
 720         /* AUTOC register is not present in x550EM. */
 721         mac->ops.prot_autoc_read = NULL;
 722         mac->ops.prot_autoc_write = NULL;
 723
 724         /* X550EM bus type is internal*/
 725         hw->bus.type = ixgbe_bus_type_internal;
 726         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 727
 728
 729         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 730         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 731         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 732         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 733         mac->ops.get_supported_physical_layer =
 734                                     ixgbe_get_supported_physical_layer_X550em;
 735
 736         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 737                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 738         else
 739                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 740
 741         /* PHY */
 742         phy->ops.init = ixgbe_init_phy_ops_X550em;
 743         switch (hw->device_id) {
 744         case IXGBE_DEV_ID_X550EM_A_1G_T:
 745         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 746                 mac->ops.setup_fc = NULL;
 747                 phy->ops.identify = ixgbe_identify_phy_fw;
 748                 phy->ops.set_phy_power = NULL;
 749                 phy->ops.get_firmware_version = NULL;
 750                 break;
 751         default:
 752                 phy->ops.identify = ixgbe_identify_phy_x550em;
 753         }
 754
 755         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 756                 phy->ops.set_phy_power = NULL;
 757
 758
 759         /* EEPROM */
 760         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 761         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 762         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 763         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 764         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 765         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 766         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 767         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 768
 769         return ret_val;
 770 }
 771
 772 /**
 773  * ixgbe_setup_fw_link - Setup firmware-controlled PHYs
 774  * @hw: pointer to hardware structure
 775  */
 776 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw)
 777 {
 778         u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
 779         s32 rc;
 780         u16 i;
 781
 782         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
 783                 return 0;
 784
 785         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
 786                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
 787                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
 788                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
 789         }
 790
 791         switch (hw->fc.requested_mode) {
 792         case ixgbe_fc_full:
 793                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX <<
 794                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 795                 break;
 796         case ixgbe_fc_rx_pause:
 797                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX <<
 798                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 799                 break;
 800         case ixgbe_fc_tx_pause:
 801                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX <<
 802                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 803                 break;
 804         default:
 805                 break;
 806         }
 807
 808         for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
 809                 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)
 810                         setup[0] |= ixgbe_fw_map[i].fw_speed;
 811         }
 812         setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN;
 813
 814         if (hw->phy.eee_speeds_advertised)
 815                 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE;
 816
 817         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup);
 818         if (rc)
 819                 return rc;
 820         if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN)
 821                 return IXGBE_ERR_OVERTEMP;
 822         return IXGBE_SUCCESS;
 823 }
 824
 825 /**
 826  * ixgbe_fc_autoneg_fw _ Set up flow control for FW-controlled PHYs
 827  * @hw: pointer to hardware structure
 828  *
 829  *  Called at init time to set up flow control.
 830  */
 831 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw)
 832 {
 833         if (hw->fc.requested_mode == ixgbe_fc_default)
 834                 hw->fc.requested_mode = ixgbe_fc_full;
 835
 836         return ixgbe_setup_fw_link(hw);
 837 }
 838
 839 /**
 840  * ixgbe_setup_eee_fw - Enable/disable EEE support
 841  * @hw: pointer to the HW structure
 842  * @enable_eee: boolean flag to enable EEE
 843  *
 844  * Enable/disable EEE based on enable_eee flag.
 845  * This function controls EEE for firmware-based PHY implementations.
 846  */
 847 static s32 ixgbe_setup_eee_fw(struct ixgbe_hw *hw, bool enable_eee)
 848 {
 849         if (!!hw->phy.eee_speeds_advertised == enable_eee)
 850                 return IXGBE_SUCCESS;
 851         if (enable_eee)
 852                 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
 853         else
 854                 hw->phy.eee_speeds_advertised = 0;
 855         return hw->phy.ops.setup_link(hw);
 856 }
 857
 858 /**
 859 *  ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
 860 *  @hw: pointer to hardware structure
 861 *
 862 *  Initialize the function pointers and for MAC type X550EM_a.
 863 *  Does not touch the hardware.
 864 **/
 865 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
 866 {
 867         struct ixgbe_mac_info *mac = &hw->mac;
 868         s32 ret_val;
 869
 870         DEBUGFUNC("ixgbe_init_ops_X550EM_a");
 871
 872         /* Start with generic X550EM init */
 873         ret_val = ixgbe_init_ops_X550EM(hw);
 874
 875         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
 876             hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) {
 877                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 878                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 879         } else {
 880                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
 881                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
 882         }
 883         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
 884         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
 885
 886         switch (mac->ops.get_media_type(hw)) {
 887         case ixgbe_media_type_fiber:
 888                 mac->ops.setup_fc = NULL;
 889                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
 890                 break;
 891         case ixgbe_media_type_backplane:
 892                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
 893                 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
 894                 break;
 895         default:
 896                 break;
 897         }
 898
 899         switch (hw->device_id) {
 900         case IXGBE_DEV_ID_X550EM_A_1G_T:
 901         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 902                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
 903                 mac->ops.setup_fc = ixgbe_fc_autoneg_fw;
 904                 mac->ops.setup_eee = ixgbe_setup_eee_fw;
 905                 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL |
 906                                                IXGBE_LINK_SPEED_1GB_FULL;
 907                 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
 908                 break;
 909         default:
 910                 break;
 911         }
 912
 913         return ret_val;
 914 }
 915
 916 /**
 917 *  ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
 918 *  @hw: pointer to hardware structure
 919 *
 920 *  Initialize the function pointers and for MAC type X550EM_x.
 921 *  Does not touch the hardware.
 922 **/
 923 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
 924 {
 925         struct ixgbe_mac_info *mac = &hw->mac;
 926         struct ixgbe_link_info *link = &hw->link;
 927         s32 ret_val;
 928
 929         DEBUGFUNC("ixgbe_init_ops_X550EM_x");
 930
 931         /* Start with generic X550EM init */
 932         ret_val = ixgbe_init_ops_X550EM(hw);
 933
 934         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 935         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 936         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 937         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 938         link->ops.read_link = ixgbe_read_i2c_combined_generic;
 939         link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
 940         link->ops.write_link = ixgbe_write_i2c_combined_generic;
 941         link->ops.write_link_unlocked =
 942                                       ixgbe_write_i2c_combined_generic_unlocked;
 943         link->addr = IXGBE_CS4227;
 944
 945
 946         return ret_val;
 947 }
 948
 949 /**
 950  *  ixgbe_dmac_config_X550
 951  *  @hw: pointer to hardware structure
 952  *
 953  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 954  *  When disabling dmac, dmac enable dmac bit is cleared.
 955  **/
 956 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 957 {
 958         u32 reg, high_pri_tc;
 959
 960         DEBUGFUNC("ixgbe_dmac_config_X550");
 961
 962         /* Disable DMA coalescing before configuring */
 963         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 964         reg &= ~IXGBE_DMACR_DMAC_EN;
 965         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 966
 967         /* Disable DMA Coalescing if the watchdog timer is 0 */
 968         if (!hw->mac.dmac_config.watchdog_timer)
 969                 goto out;
 970
 971         ixgbe_dmac_config_tcs_X550(hw);
 972
 973         /* Configure DMA Coalescing Control Register */
 974         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 975
 976         /* Set the watchdog timer in units of 40.96 usec */
 977         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 978         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 979
 980         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 981         /* If fcoe is enabled, set high priority traffic class */
 982         if (hw->mac.dmac_config.fcoe_en) {
 983                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 984                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 985                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 986         }
 987         reg |= IXGBE_DMACR_EN_MNG_IND;
 988
 989         /* Enable DMA coalescing after configuration */
 990         reg |= IXGBE_DMACR_DMAC_EN;
 991         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 992
 993 out:
 994         return IXGBE_SUCCESS;
 995 }
 996
 997 /**
 998  *  ixgbe_dmac_config_tcs_X550
 999  *  @hw: pointer to hardware structure
1000  *
1001  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
1002  *  be cleared before configuring.
1003  **/
1004 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
1005 {
1006         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
1007
1008         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
1009
1010         /* Configure DMA coalescing enabled */
1011         switch (hw->mac.dmac_config.link_speed) {
1012         case IXGBE_LINK_SPEED_10_FULL:
1013         case IXGBE_LINK_SPEED_100_FULL:
1014                 pb_headroom = IXGBE_DMACRXT_100M;
1015                 break;
1016         case IXGBE_LINK_SPEED_1GB_FULL:
1017                 pb_headroom = IXGBE_DMACRXT_1G;
1018                 break;
1019         default:
1020                 pb_headroom = IXGBE_DMACRXT_10G;
1021                 break;
1022         }
1023
1024         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
1025                              IXGBE_MHADD_MFS_SHIFT) / 1024);
1026
1027         /* Set the per Rx packet buffer receive threshold */
1028         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
1029                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
1030                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
1031
1032                 if (tc < hw->mac.dmac_config.num_tcs) {
1033                         /* Get Rx PB size */
1034                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
1035                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
1036                                 IXGBE_RXPBSIZE_SHIFT;
1037
1038                         /* Calculate receive buffer threshold in kilobytes */
1039                         if (rx_pb_size > pb_headroom)
1040                                 rx_pb_size = rx_pb_size - pb_headroom;
1041                         else
1042                                 rx_pb_size = 0;
1043
1044                         /* Minimum of MFS shall be set for DMCTH */
1045                         reg |= (rx_pb_size > maxframe_size_kb) ?
1046                                 rx_pb_size : maxframe_size_kb;
1047                 }
1048                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
1049         }
1050         return IXGBE_SUCCESS;
1051 }
1052
1053 /**
1054  *  ixgbe_dmac_update_tcs_X550
1055  *  @hw: pointer to hardware structure
1056  *
1057  *  Disables dmac, updates per TC settings, and then enables dmac.
1058  **/
1059 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
1060 {
1061         u32 reg;
1062
1063         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
1064
1065         /* Disable DMA coalescing before configuring */
1066         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
1067         reg &= ~IXGBE_DMACR_DMAC_EN;
1068         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
1069
1070         ixgbe_dmac_config_tcs_X550(hw);
1071
1072         /* Enable DMA coalescing after configuration */
1073         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
1074         reg |= IXGBE_DMACR_DMAC_EN;
1075         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
1076
1077         return IXGBE_SUCCESS;
1078 }
1079
1080 /**
1081  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
1082  *  @hw: pointer to hardware structure
1083  *
1084  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
1085  *  ixgbe_hw struct in order to set up EEPROM access.
1086  **/
1087 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
1088 {
1089         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1090         u32 eec;
1091         u16 eeprom_size;
1092
1093         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
1094
1095         if (eeprom->type == ixgbe_eeprom_uninitialized) {
1096                 eeprom->semaphore_delay = 10;
1097                 eeprom->type = ixgbe_flash;
1098
1099                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1100                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1101                                     IXGBE_EEC_SIZE_SHIFT);
1102                 eeprom->word_size = 1 << (eeprom_size +
1103                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
1104
1105                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
1106                           eeprom->type, eeprom->word_size);
1107         }
1108
1109         return IXGBE_SUCCESS;
1110 }
1111
1112 /**
1113  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1114  * @hw: pointer to hardware structure
1115  * @enable: enable or disable source address pruning
1116  * @pool: Rx pool to set source address pruning for
1117  **/
1118 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1119                                            unsigned int pool)
1120 {
1121         u64 pfflp;
1122
1123         /* max rx pool is 63 */
1124         if (pool > 63)
1125                 return;
1126
1127         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1128         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1129
1130         if (enable)
1131                 pfflp |= (1ULL << pool);
1132         else
1133                 pfflp &= ~(1ULL << pool);
1134
1135         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1136         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1137 }
1138
1139 /**
1140  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1141  *  @hw: pointer to hardware structure
1142  *  @enable: enable or disable switch for Ethertype anti-spoofing
1143  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1144  *
1145  **/
1146 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1147                 bool enable, int vf)
1148 {
1149         int vf_target_reg = vf >> 3;
1150         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1151         u32 pfvfspoof;
1152
1153         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1154
1155         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1156         if (enable)
1157                 pfvfspoof |= (1 << vf_target_shift);
1158         else
1159                 pfvfspoof &= ~(1 << vf_target_shift);
1160
1161         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1162 }
1163
1164 /**
1165  * ixgbe_iosf_wait - Wait for IOSF command completion
1166  * @hw: pointer to hardware structure
1167  * @ctrl: pointer to location to receive final IOSF control value
1168  *
1169  * Returns failing status on timeout
1170  *
1171  * Note: ctrl can be NULL if the IOSF control register value is not needed
1172  **/
1173 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1174 {
1175         u32 i, command = 0;
1176
1177         /* Check every 10 usec to see if the address cycle completed.
1178          * The SB IOSF BUSY bit will clear when the operation is
1179          * complete
1180          */
1181         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1182                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1183                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1184                         break;
1185                 usec_delay(10);
1186         }
1187         if (ctrl)
1188                 *ctrl = command;
1189         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1190                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1191                 return IXGBE_ERR_PHY;
1192         }
1193
1194         return IXGBE_SUCCESS;
1195 }
1196
1197 /**
1198  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register
1199  *  of the IOSF device
1200  *  @hw: pointer to hardware structure
1201  *  @reg_addr: 32 bit PHY register to write
1202  *  @device_type: 3 bit device type
1203  *  @data: Data to write to the register
1204  **/
1205 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1206                             u32 device_type, u32 data)
1207 {
1208         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1209         u32 command, error;
1210         s32 ret;
1211
1212         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1213         if (ret != IXGBE_SUCCESS)
1214                 return ret;
1215
1216         ret = ixgbe_iosf_wait(hw, NULL);
1217         if (ret != IXGBE_SUCCESS)
1218                 goto out;
1219
1220         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1221                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1222
1223         /* Write IOSF control register */
1224         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1225
1226         /* Write IOSF data register */
1227         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1228
1229         ret = ixgbe_iosf_wait(hw, &command);
1230
1231         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1232                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1233                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1234                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1235                               "Failed to write, error %x\n", error);
1236                 ret = IXGBE_ERR_PHY;
1237         }
1238
1239 out:
1240         ixgbe_release_swfw_semaphore(hw, gssr);
1241         return ret;
1242 }
1243
1244 /**
1245  *  ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device
1246  *  @hw: pointer to hardware structure
1247  *  @reg_addr: 32 bit PHY register to write
1248  *  @device_type: 3 bit device type
1249  *  @data: Pointer to read data from the register
1250  **/
1251 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1252                            u32 device_type, u32 *data)
1253 {
1254         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1255         u32 command, error;
1256         s32 ret;
1257
1258         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1259         if (ret != IXGBE_SUCCESS)
1260                 return ret;
1261
1262         ret = ixgbe_iosf_wait(hw, NULL);
1263         if (ret != IXGBE_SUCCESS)
1264                 goto out;
1265
1266         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1267                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1268
1269         /* Write IOSF control register */
1270         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1271
1272         ret = ixgbe_iosf_wait(hw, &command);
1273
1274         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1275                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1276                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1277                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1278                                 "Failed to read, error %x\n", error);
1279                 ret = IXGBE_ERR_PHY;
1280         }
1281
1282         if (ret == IXGBE_SUCCESS)
1283                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1284
1285 out:
1286         ixgbe_release_swfw_semaphore(hw, gssr);
1287         return ret;
1288 }
1289
1290 /**
1291  * ixgbe_get_phy_token - Get the token for shared phy access
1292  * @hw: Pointer to hardware structure
1293  */
1294
1295 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1296 {
1297         struct ixgbe_hic_phy_token_req token_cmd;
1298         s32 status;
1299
1300         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1301         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1302         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1303         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1304         token_cmd.port_number = hw->bus.lan_id;
1305         token_cmd.command_type = FW_PHY_TOKEN_REQ;
1306         token_cmd.pad = 0;
1307         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1308                                               sizeof(token_cmd),
1309                                               IXGBE_HI_COMMAND_TIMEOUT,
1310                                               true);
1311         if (status)
1312                 return status;
1313         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1314                 return IXGBE_SUCCESS;
1315         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1316                 return IXGBE_ERR_FW_RESP_INVALID;
1317
1318         return IXGBE_ERR_TOKEN_RETRY;
1319 }
1320
1321 /**
1322  * ixgbe_put_phy_token - Put the token for shared phy access
1323  * @hw: Pointer to hardware structure
1324  */
1325
1326 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1327 {
1328         struct ixgbe_hic_phy_token_req token_cmd;
1329         s32 status;
1330
1331         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1332         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1333         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1334         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1335         token_cmd.port_number = hw->bus.lan_id;
1336         token_cmd.command_type = FW_PHY_TOKEN_REL;
1337         token_cmd.pad = 0;
1338         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1339                                               sizeof(token_cmd),
1340                                               IXGBE_HI_COMMAND_TIMEOUT,
1341                                               true);
1342         if (status)
1343                 return status;
1344         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1345                 return IXGBE_SUCCESS;
1346
1347         DEBUGOUT("Put PHY Token host interface command failed");
1348         return IXGBE_ERR_FW_RESP_INVALID;
1349 }
1350
1351 /**
1352  *  ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1353  *  of the IOSF device
1354  *  @hw: pointer to hardware structure
1355  *  @reg_addr: 32 bit PHY register to write
1356  *  @device_type: 3 bit device type
1357  *  @data: Data to write to the register
1358  **/
1359 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1360                                   u32 device_type, u32 data)
1361 {
1362         struct ixgbe_hic_internal_phy_req write_cmd;
1363         s32 status;
1364         UNREFERENCED_1PARAMETER(device_type);
1365
1366         memset(&write_cmd, 0, sizeof(write_cmd));
1367         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1368         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1369         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1370         write_cmd.port_number = hw->bus.lan_id;
1371         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1372         write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1373         write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1374
1375         status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1376                                               sizeof(write_cmd),
1377                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1378
1379         return status;
1380 }
1381
1382 /**
1383  *  ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device
1384  *  @hw: pointer to hardware structure
1385  *  @reg_addr: 32 bit PHY register to write
1386  *  @device_type: 3 bit device type
1387  *  @data: Pointer to read data from the register
1388  **/
1389 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1390                                  u32 device_type, u32 *data)
1391 {
1392         union {
1393                 struct ixgbe_hic_internal_phy_req cmd;
1394                 struct ixgbe_hic_internal_phy_resp rsp;
1395         } hic;
1396         s32 status;
1397         UNREFERENCED_1PARAMETER(device_type);
1398
1399         memset(&hic, 0, sizeof(hic));
1400         hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1401         hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1402         hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1403         hic.cmd.port_number = hw->bus.lan_id;
1404         hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1405         hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1406
1407         status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1408                                               sizeof(hic.cmd),
1409                                               IXGBE_HI_COMMAND_TIMEOUT, true);
1410
1411         /* Extract the register value from the response. */
1412         *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1413
1414         return status;
1415 }
1416
1417 /**
1418  *  ixgbe_disable_mdd_X550
1419  *  @hw: pointer to hardware structure
1420  *
1421  *  Disable malicious driver detection
1422  **/
1423 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1424 {
1425         u32 reg;
1426
1427         DEBUGFUNC("ixgbe_disable_mdd_X550");
1428
1429         /* Disable MDD for TX DMA and interrupt */
1430         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1431         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1432         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1433
1434         /* Disable MDD for RX and interrupt */
1435         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1436         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1437         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1438 }
1439
1440 /**
1441  *  ixgbe_enable_mdd_X550
1442  *  @hw: pointer to hardware structure
1443  *
1444  *  Enable malicious driver detection
1445  **/
1446 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1447 {
1448         u32 reg;
1449
1450         DEBUGFUNC("ixgbe_enable_mdd_X550");
1451
1452         /* Enable MDD for TX DMA and interrupt */
1453         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1454         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1455         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1456
1457         /* Enable MDD for RX and interrupt */
1458         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1459         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1460         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1461 }
1462
1463 /**
1464  *  ixgbe_restore_mdd_vf_X550
1465  *  @hw: pointer to hardware structure
1466  *  @vf: vf index
1467  *
1468  *  Restore VF that was disabled during malicious driver detection event
1469  **/
1470 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1471 {
1472         u32 idx, reg, num_qs, start_q, bitmask;
1473
1474         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1475
1476         /* Map VF to queues */
1477         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1478         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1479         case IXGBE_MRQC_VMDQRT8TCEN:
1480                 num_qs = 8;  /* 16 VFs / pools */
1481                 bitmask = 0x000000FF;
1482                 break;
1483         case IXGBE_MRQC_VMDQRSS32EN:
1484         case IXGBE_MRQC_VMDQRT4TCEN:
1485                 num_qs = 4;  /* 32 VFs / pools */
1486                 bitmask = 0x0000000F;
1487                 break;
1488         default:            /* 64 VFs / pools */
1489                 num_qs = 2;
1490                 bitmask = 0x00000003;
1491                 break;
1492         }
1493         start_q = vf * num_qs;
1494
1495         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1496         idx = start_q / 32;
1497         reg = 0;
1498         reg |= (bitmask << (start_q % 32));
1499         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1500         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1501 }
1502
1503 /**
1504  *  ixgbe_mdd_event_X550
1505  *  @hw: pointer to hardware structure
1506  *  @vf_bitmap: vf bitmap of malicious vfs
1507  *
1508  *  Handle malicious driver detection event.
1509  **/
1510 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1511 {
1512         u32 wqbr;
1513         u32 i, j, reg, q, shift, vf, idx;
1514
1515         DEBUGFUNC("ixgbe_mdd_event_X550");
1516
1517         /* figure out pool size for mapping to vf's */
1518         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1519         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1520         case IXGBE_MRQC_VMDQRT8TCEN:
1521                 shift = 3;  /* 16 VFs / pools */
1522                 break;
1523         case IXGBE_MRQC_VMDQRSS32EN:
1524         case IXGBE_MRQC_VMDQRT4TCEN:
1525                 shift = 2;  /* 32 VFs / pools */
1526                 break;
1527         default:
1528                 shift = 1;  /* 64 VFs / pools */
1529                 break;
1530         }
1531
1532         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1533         for (i = 0; i < 4; i++) {
1534                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1535                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1536
1537                 if (!wqbr)
1538                         continue;
1539
1540                 /* Get malicious queue */
1541                 for (j = 0; j < 32 && wqbr; j++) {
1542
1543                         if (!(wqbr & (1 << j)))
1544                                 continue;
1545
1546                         /* Get queue from bitmask */
1547                         q = j + (i * 32);
1548
1549                         /* Map queue to vf */
1550                         vf = (q >> shift);
1551
1552                         /* Set vf bit in vf_bitmap */
1553                         idx = vf / 32;
1554                         vf_bitmap[idx] |= (1 << (vf % 32));
1555                         wqbr &= ~(1 << j);
1556                 }
1557         }
1558 }
1559
1560 /**
1561  *  ixgbe_get_media_type_X550em - Get media type
1562  *  @hw: pointer to hardware structure
1563  *
1564  *  Returns the media type (fiber, copper, backplane)
1565  */
1566 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1567 {
1568         enum ixgbe_media_type media_type;
1569
1570         DEBUGFUNC("ixgbe_get_media_type_X550em");
1571
1572         /* Detect if there is a copper PHY attached. */
1573         switch (hw->device_id) {
1574         case IXGBE_DEV_ID_X550EM_X_KR:
1575         case IXGBE_DEV_ID_X550EM_X_KX4:
1576         case IXGBE_DEV_ID_X550EM_A_KR:
1577         case IXGBE_DEV_ID_X550EM_A_KR_L:
1578                 media_type = ixgbe_media_type_backplane;
1579                 break;
1580         case IXGBE_DEV_ID_X550EM_X_SFP:
1581         case IXGBE_DEV_ID_X550EM_A_SFP:
1582         case IXGBE_DEV_ID_X550EM_A_SFP_N:
1583         case IXGBE_DEV_ID_X550EM_A_QSFP:
1584         case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1585                 media_type = ixgbe_media_type_fiber;
1586                 break;
1587         case IXGBE_DEV_ID_X550EM_X_1G_T:
1588         case IXGBE_DEV_ID_X550EM_X_10G_T:
1589         case IXGBE_DEV_ID_X550EM_A_10G_T:
1590                 media_type = ixgbe_media_type_copper;
1591                 break;
1592         case IXGBE_DEV_ID_X550EM_A_SGMII:
1593         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1594                 media_type = ixgbe_media_type_backplane;
1595                 hw->phy.type = ixgbe_phy_sgmii;
1596                 break;
1597         case IXGBE_DEV_ID_X550EM_A_1G_T:
1598         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1599                 media_type = ixgbe_media_type_copper;
1600                 break;
1601         default:
1602                 media_type = ixgbe_media_type_unknown;
1603                 break;
1604         }
1605         return media_type;
1606 }
1607
1608 /**
1609  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1610  *  @hw: pointer to hardware structure
1611  *  @linear: true if SFP module is linear
1612  */
1613 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1614 {
1615         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1616
1617         switch (hw->phy.sfp_type) {
1618         case ixgbe_sfp_type_not_present:
1619                 return IXGBE_ERR_SFP_NOT_PRESENT;
1620         case ixgbe_sfp_type_da_cu_core0:
1621         case ixgbe_sfp_type_da_cu_core1:
1622                 *linear = true;
1623                 break;
1624         case ixgbe_sfp_type_srlr_core0:
1625         case ixgbe_sfp_type_srlr_core1:
1626         case ixgbe_sfp_type_da_act_lmt_core0:
1627         case ixgbe_sfp_type_da_act_lmt_core1:
1628         case ixgbe_sfp_type_1g_sx_core0:
1629         case ixgbe_sfp_type_1g_sx_core1:
1630         case ixgbe_sfp_type_1g_lx_core0:
1631         case ixgbe_sfp_type_1g_lx_core1:
1632                 *linear = false;
1633                 break;
1634         case ixgbe_sfp_type_unknown:
1635         case ixgbe_sfp_type_1g_cu_core0:
1636         case ixgbe_sfp_type_1g_cu_core1:
1637         default:
1638                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1639         }
1640
1641         return IXGBE_SUCCESS;
1642 }
1643
1644 /**
1645  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1646  *  @hw: pointer to hardware structure
1647  *
1648  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1649  **/
1650 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1651 {
1652         s32 status;
1653         bool linear;
1654
1655         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1656
1657         status = ixgbe_identify_module_generic(hw);
1658
1659         if (status != IXGBE_SUCCESS)
1660                 return status;
1661
1662         /* Check if SFP module is supported */
1663         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1664
1665         return status;
1666 }
1667
1668 /**
1669  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1670  *  @hw: pointer to hardware structure
1671  */
1672 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1673 {
1674         s32 status;
1675         bool linear;
1676
1677         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1678
1679         /* Check if SFP module is supported */
1680         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1681
1682         if (status != IXGBE_SUCCESS)
1683                 return status;
1684
1685         ixgbe_init_mac_link_ops_X550em(hw);
1686         hw->phy.ops.reset = NULL;
1687
1688         return IXGBE_SUCCESS;
1689 }
1690
1691 /**
1692 *  ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1693 *  internal PHY
1694 *  @hw: pointer to hardware structure
1695 **/
1696 STATIC s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1697 {
1698         s32 status;
1699         u32 link_ctrl;
1700
1701         /* Restart auto-negotiation. */
1702         status = hw->mac.ops.read_iosf_sb_reg(hw,
1703                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1704                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1705
1706         if (status) {
1707                 DEBUGOUT("Auto-negotiation did not complete\n");
1708                 return status;
1709         }
1710
1711         link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1712         status = hw->mac.ops.write_iosf_sb_reg(hw,
1713                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1714                                         IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1715
1716         if (hw->mac.type == ixgbe_mac_X550EM_a) {
1717                 u32 flx_mask_st20;
1718
1719                 /* Indicate to FW that AN restart has been asserted */
1720                 status = hw->mac.ops.read_iosf_sb_reg(hw,
1721                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1722                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1723
1724                 if (status) {
1725                         DEBUGOUT("Auto-negotiation did not complete\n");
1726                         return status;
1727                 }
1728
1729                 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1730                 status = hw->mac.ops.write_iosf_sb_reg(hw,
1731                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1732                                 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1733         }
1734
1735         return status;
1736 }
1737
1738 /**
1739  * ixgbe_setup_sgmii - Set up link for sgmii
1740  * @hw: pointer to hardware structure
1741  */
1742 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1743                              bool autoneg_wait)
1744 {
1745         struct ixgbe_mac_info *mac = &hw->mac;
1746         u32 lval, sval, flx_val;
1747         s32 rc;
1748
1749         rc = mac->ops.read_iosf_sb_reg(hw,
1750                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1751                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1752         if (rc)
1753                 return rc;
1754
1755         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1756         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1757         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1758         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1759         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1760         rc = mac->ops.write_iosf_sb_reg(hw,
1761                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1762                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1763         if (rc)
1764                 return rc;
1765
1766         rc = mac->ops.read_iosf_sb_reg(hw,
1767                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1768                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1769         if (rc)
1770                 return rc;
1771
1772         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1773         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1774         rc = mac->ops.write_iosf_sb_reg(hw,
1775                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1776                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1777         if (rc)
1778                 return rc;
1779
1780         rc = mac->ops.read_iosf_sb_reg(hw,
1781                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1782                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1783         if (rc)
1784                 return rc;
1785
1786         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1787         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1788         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1789         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1790         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1791
1792         rc = mac->ops.write_iosf_sb_reg(hw,
1793                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1794                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1795         if (rc)
1796                 return rc;
1797
1798         rc = ixgbe_restart_an_internal_phy_x550em(hw);
1799         if (rc)
1800                 return rc;
1801
1802         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1803 }
1804
1805 /**
1806  * ixgbe_setup_sgmii_fw - Set up link for sgmii with firmware-controlled PHYs
1807  * @hw: pointer to hardware structure
1808  */
1809 STATIC s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1810                                 bool autoneg_wait)
1811 {
1812         struct ixgbe_mac_info *mac = &hw->mac;
1813         u32 lval, sval, flx_val;
1814         s32 rc;
1815
1816         rc = mac->ops.read_iosf_sb_reg(hw,
1817                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1818                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1819         if (rc)
1820                 return rc;
1821
1822         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1823         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1824         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1825         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1826         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1827         rc = mac->ops.write_iosf_sb_reg(hw,
1828                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1829                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1830         if (rc)
1831                 return rc;
1832
1833         rc = mac->ops.read_iosf_sb_reg(hw,
1834                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1835                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1836         if (rc)
1837                 return rc;
1838
1839         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1840         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1841         rc = mac->ops.write_iosf_sb_reg(hw,
1842                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1843                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1844         if (rc)
1845                 return rc;
1846
1847         rc = mac->ops.write_iosf_sb_reg(hw,
1848                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1849                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1850         if (rc)
1851                 return rc;
1852
1853         rc = mac->ops.read_iosf_sb_reg(hw,
1854                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1855                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1856         if (rc)
1857                 return rc;
1858
1859         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1860         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
1861         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1862         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1863         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1864
1865         rc = mac->ops.write_iosf_sb_reg(hw,
1866                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1867                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1868         if (rc)
1869                 return rc;
1870
1871         rc = ixgbe_restart_an_internal_phy_x550em(hw);
1872
1873         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1874 }
1875
1876 /**
1877  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1878  *  @hw: pointer to hardware structure
1879  */
1880 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1881 {
1882         struct ixgbe_mac_info *mac = &hw->mac;
1883
1884         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1885
1886         switch (hw->mac.ops.get_media_type(hw)) {
1887         case ixgbe_media_type_fiber:
1888                 /* CS4227 does not support autoneg, so disable the laser control
1889                  * functions for SFP+ fiber
1890                  */
1891                 mac->ops.disable_tx_laser = NULL;
1892                 mac->ops.enable_tx_laser = NULL;
1893                 mac->ops.flap_tx_laser = NULL;
1894                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1895                 mac->ops.set_rate_select_speed =
1896                                         ixgbe_set_soft_rate_select_speed;
1897
1898                 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1899                     (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1900                         mac->ops.setup_mac_link =
1901                                                 ixgbe_setup_mac_link_sfp_x550a;
1902                 else
1903                         mac->ops.setup_mac_link =
1904                                                 ixgbe_setup_mac_link_sfp_x550em;
1905                 break;
1906         case ixgbe_media_type_copper:
1907                 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1908                         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
1909                             hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
1910                                 mac->ops.setup_link = ixgbe_setup_sgmii_fw;
1911                                 mac->ops.check_link =
1912                                                    ixgbe_check_mac_link_generic;
1913                         } else {
1914                                 mac->ops.setup_link =
1915                                                   ixgbe_setup_mac_link_t_X550em;
1916                         }
1917                 } else {
1918                         mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1919                         mac->ops.check_link = ixgbe_check_link_t_X550em;
1920                 }
1921                 break;
1922         case ixgbe_media_type_backplane:
1923                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1924                     hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1925                         mac->ops.setup_link = ixgbe_setup_sgmii;
1926                 break;
1927         default:
1928                 break;
1929         }
1930 }
1931
1932 /**
1933  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1934  *  @hw: pointer to hardware structure
1935  *  @speed: pointer to link speed
1936  *  @autoneg: true when autoneg or autotry is enabled
1937  */
1938 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1939                                        ixgbe_link_speed *speed,
1940                                        bool *autoneg)
1941 {
1942         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1943
1944
1945         if (hw->phy.type == ixgbe_phy_fw) {
1946                 *autoneg = true;
1947                 *speed = hw->phy.speeds_supported;
1948                 return 0;
1949         }
1950
1951         /* SFP */
1952         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1953
1954                 /* CS4227 SFP must not enable auto-negotiation */
1955                 *autoneg = false;
1956
1957                 /* Check if 1G SFP module. */
1958                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1959                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1960                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1961                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1962                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1963                         return IXGBE_SUCCESS;
1964                 }
1965
1966                 /* Link capabilities are based on SFP */
1967                 if (hw->phy.multispeed_fiber)
1968                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1969                                  IXGBE_LINK_SPEED_1GB_FULL;
1970                 else
1971                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1972         } else {
1973                 switch (hw->phy.type) {
1974                 case ixgbe_phy_sgmii:
1975                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1976                         break;
1977                 case ixgbe_phy_x550em_kr:
1978                         if (hw->mac.type == ixgbe_mac_X550EM_a) {
1979                                 /* check different backplane modes */
1980                                 if (hw->phy.nw_mng_if_sel &
1981                                            IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
1982                                         *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
1983                                         break;
1984                                 } else if (hw->device_id ==
1985                                                    IXGBE_DEV_ID_X550EM_A_KR_L) {
1986                                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1987                                         break;
1988                                 }
1989                         }
1990                         /* fall through */
1991                 default:
1992                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1993                                  IXGBE_LINK_SPEED_1GB_FULL;
1994                         break;
1995                 }
1996                 *autoneg = true;
1997         }
1998
1999         return IXGBE_SUCCESS;
2000 }
2001
2002 /**
2003  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
2004  * @hw: pointer to hardware structure
2005  * @lsc: pointer to boolean flag which indicates whether external Base T
2006  *       PHY interrupt is lsc
2007  *
2008  * Determime if external Base T PHY interrupt cause is high temperature
2009  * failure alarm or link status change.
2010  *
2011  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2012  * failure alarm, else return PHY access status.
2013  */
2014 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
2015 {
2016         u32 status;
2017         u16 reg;
2018
2019         *lsc = false;
2020
2021         /* Vendor alarm triggered */
2022         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2023                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2024                                       &reg);
2025
2026         if (status != IXGBE_SUCCESS ||
2027             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
2028                 return status;
2029
2030         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
2031         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
2032                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2033                                       &reg);
2034
2035         if (status != IXGBE_SUCCESS ||
2036             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2037             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
2038                 return status;
2039
2040         /* Global alarm triggered */
2041         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
2042                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2043                                       &reg);
2044
2045         if (status != IXGBE_SUCCESS)
2046                 return status;
2047
2048         /* If high temperature failure, then return over temp error and exit */
2049         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
2050                 /* power down the PHY in case the PHY FW didn't already */
2051                 ixgbe_set_copper_phy_power(hw, false);
2052                 return IXGBE_ERR_OVERTEMP;
2053         } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
2054                 /*  device fault alarm triggered */
2055                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
2056                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2057                                           &reg);
2058
2059                 if (status != IXGBE_SUCCESS)
2060                         return status;
2061
2062                 /* if device fault was due to high temp alarm handle and exit */
2063                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
2064                         /* power down the PHY in case the PHY FW didn't */
2065                         ixgbe_set_copper_phy_power(hw, false);
2066                         return IXGBE_ERR_OVERTEMP;
2067                 }
2068         }
2069
2070         /* Vendor alarm 2 triggered */
2071         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2072                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2073
2074         if (status != IXGBE_SUCCESS ||
2075             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
2076                 return status;
2077
2078         /* link connect/disconnect event occurred */
2079         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
2080                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2081
2082         if (status != IXGBE_SUCCESS)
2083                 return status;
2084
2085         /* Indicate LSC */
2086         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2087                 *lsc = true;
2088
2089         return IXGBE_SUCCESS;
2090 }
2091
2092 /**
2093  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2094  * @hw: pointer to hardware structure
2095  *
2096  * Enable link status change and temperature failure alarm for the external
2097  * Base T PHY
2098  *
2099  * Returns PHY access status
2100  */
2101 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2102 {
2103         u32 status;
2104         u16 reg;
2105         bool lsc;
2106
2107         /* Clear interrupt flags */
2108         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2109
2110         /* Enable link status change alarm */
2111
2112         /* Enable the LASI interrupts on X552 devices to receive notifications
2113          * of the link configurations of the external PHY and correspondingly
2114          * support the configuration of the internal iXFI link, since iXFI does
2115          * not support auto-negotiation. This is not required for X553 devices
2116          * having KR support, which performs auto-negotiations and which is used
2117          * as the internal link to the external PHY. Hence adding a check here
2118          * to avoid enabling LASI interrupts for X553 devices.
2119          */
2120         if (hw->mac.type != ixgbe_mac_X550EM_a) {
2121                 status = hw->phy.ops.read_reg(hw,
2122                                         IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2123                                         IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
2124
2125                 if (status != IXGBE_SUCCESS)
2126                         return status;
2127
2128                 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2129
2130                 status = hw->phy.ops.write_reg(hw,
2131                                         IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2132                                         IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
2133
2134                 if (status != IXGBE_SUCCESS)
2135                         return status;
2136         }
2137
2138         /* Enable high temperature failure and global fault alarms */
2139         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2140                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2141                                       &reg);
2142
2143         if (status != IXGBE_SUCCESS)
2144                 return status;
2145
2146         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2147                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2148
2149         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2150                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2151                                        reg);
2152
2153         if (status != IXGBE_SUCCESS)
2154                 return status;
2155
2156         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2157         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2158                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2159                                       &reg);
2160
2161         if (status != IXGBE_SUCCESS)
2162                 return status;
2163
2164         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2165                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2166
2167         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2168                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2169                                        reg);
2170
2171         if (status != IXGBE_SUCCESS)
2172                 return status;
2173
2174         /* Enable chip-wide vendor alarm */
2175         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2176                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2177                                       &reg);
2178
2179         if (status != IXGBE_SUCCESS)
2180                 return status;
2181
2182         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2183
2184         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2185                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2186                                        reg);
2187
2188         return status;
2189 }
2190
2191 /**
2192  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2193  *  @hw: pointer to hardware structure
2194  *  @speed: link speed
2195  *
2196  *  Configures the integrated KR PHY.
2197  **/
2198 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2199                                        ixgbe_link_speed speed)
2200 {
2201         s32 status;
2202         u32 reg_val;
2203
2204         status = hw->mac.ops.read_iosf_sb_reg(hw,
2205                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2206                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2207         if (status)
2208                 return status;
2209
2210         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2211         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2212                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2213
2214         /* Advertise 10G support. */
2215         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2216                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2217
2218         /* Advertise 1G support. */
2219         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2220                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2221
2222         status = hw->mac.ops.write_iosf_sb_reg(hw,
2223                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2224                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2225
2226         if (hw->mac.type == ixgbe_mac_X550EM_a) {
2227                 /* Set lane mode  to KR auto negotiation */
2228                 status = hw->mac.ops.read_iosf_sb_reg(hw,
2229                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2230                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2231
2232                 if (status)
2233                         return status;
2234
2235                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2236                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2237                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2238                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2239                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2240
2241                 status = hw->mac.ops.write_iosf_sb_reg(hw,
2242                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2243                                     IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2244         }
2245
2246         return ixgbe_restart_an_internal_phy_x550em(hw);
2247 }
2248
2249 /**
2250  * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs
2251  * @hw: pointer to hardware structure
2252  */
2253 static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw)
2254 {
2255         u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
2256         s32 rc;
2257
2258         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2259                 return IXGBE_SUCCESS;
2260
2261         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store);
2262         if (rc)
2263                 return rc;
2264         memset(store, 0, sizeof(store));
2265
2266         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store);
2267         if (rc)
2268                 return rc;
2269
2270         return ixgbe_setup_fw_link(hw);
2271 }
2272
2273 /**
2274  * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp
2275  * @hw: pointer to hardware structure
2276  */
2277 static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw)
2278 {
2279         u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
2280         s32 rc;
2281
2282         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store);
2283         if (rc)
2284                 return rc;
2285
2286         if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) {
2287                 ixgbe_shutdown_fw_phy(hw);
2288                 return IXGBE_ERR_OVERTEMP;
2289         }
2290         return IXGBE_SUCCESS;
2291 }
2292
2293 /**
2294  *  ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2295  *  @hw: pointer to hardware structure
2296  *
2297  *  Read NW_MNG_IF_SEL register and save field values, and check for valid field
2298  *  values.
2299  **/
2300 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2301 {
2302         /* Save NW management interface connected on board. This is used
2303          * to determine internal PHY mode.
2304          */
2305         hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2306
2307         /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2308          * PHY address. This register field was has only been used for X552.
2309          */
2310         if (hw->mac.type == ixgbe_mac_X550EM_a &&
2311             hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2312                 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2313                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2314                                IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2315         }
2316
2317         return IXGBE_SUCCESS;
2318 }
2319
2320 /**
2321  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2322  *  @hw: pointer to hardware structure
2323  *
2324  *  Initialize any function pointers that were not able to be
2325  *  set during init_shared_code because the PHY/SFP type was
2326  *  not known.  Perform the SFP init if necessary.
2327  */
2328 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2329 {
2330         struct ixgbe_phy_info *phy = &hw->phy;
2331         s32 ret_val;
2332
2333         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2334
2335         hw->mac.ops.set_lan_id(hw);
2336         ixgbe_read_mng_if_sel_x550em(hw);
2337
2338         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2339                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2340                 ixgbe_setup_mux_ctl(hw);
2341                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2342         }
2343
2344         switch (hw->device_id) {
2345         case IXGBE_DEV_ID_X550EM_A_1G_T:
2346         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2347                 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2348                 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2349                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2350                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2351                 phy->ops.check_overtemp = ixgbe_check_overtemp_fw;
2352                 if (hw->bus.lan_id)
2353                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2354                 else
2355                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2356
2357                 break;
2358         case IXGBE_DEV_ID_X550EM_A_10G_T:
2359         case IXGBE_DEV_ID_X550EM_A_SFP:
2360                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2361                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2362                 if (hw->bus.lan_id)
2363                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2364                 else
2365                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2366                 break;
2367         case IXGBE_DEV_ID_X550EM_X_SFP:
2368                 /* set up for CS4227 usage */
2369                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2370                 break;
2371         default:
2372                 break;
2373         }
2374
2375         /* Identify the PHY or SFP module */
2376         ret_val = phy->ops.identify(hw);
2377         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED ||
2378             ret_val == IXGBE_ERR_PHY_ADDR_INVALID)
2379                 return ret_val;
2380
2381         /* Setup function pointers based on detected hardware */
2382         ixgbe_init_mac_link_ops_X550em(hw);
2383         if (phy->sfp_type != ixgbe_sfp_type_unknown)
2384                 phy->ops.reset = NULL;
2385
2386         /* Set functions pointers based on phy type */
2387         switch (hw->phy.type) {
2388         case ixgbe_phy_x550em_kx4:
2389                 phy->ops.setup_link = NULL;
2390                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2391                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2392                 break;
2393         case ixgbe_phy_x550em_kr:
2394                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2395                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2396                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2397                 break;
2398         case ixgbe_phy_x550em_ext_t:
2399                 /* If internal link mode is XFI, then setup iXFI internal link,
2400                  * else setup KR now.
2401                  */
2402                 phy->ops.setup_internal_link =
2403                                               ixgbe_setup_internal_phy_t_x550em;
2404
2405                 /* setup SW LPLU only for first revision of X550EM_x */
2406                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2407                     !(IXGBE_FUSES0_REV_MASK &
2408                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2409                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2410
2411                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2412                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2413                 break;
2414         case ixgbe_phy_sgmii:
2415                 phy->ops.setup_link = NULL;
2416                 break;
2417         case ixgbe_phy_fw:
2418                 phy->ops.setup_link = ixgbe_setup_fw_link;
2419                 phy->ops.reset = ixgbe_reset_phy_fw;
2420                 break;
2421         default:
2422                 break;
2423         }
2424         return ret_val;
2425 }
2426
2427 /**
2428  * ixgbe_set_mdio_speed - Set MDIO clock speed
2429  *  @hw: pointer to hardware structure
2430  */
2431 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2432 {
2433         u32 hlreg0;
2434
2435         switch (hw->device_id) {
2436         case IXGBE_DEV_ID_X550EM_X_10G_T:
2437         case IXGBE_DEV_ID_X550EM_A_SGMII:
2438         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2439         case IXGBE_DEV_ID_X550EM_A_10G_T:
2440         case IXGBE_DEV_ID_X550EM_A_SFP:
2441         case IXGBE_DEV_ID_X550EM_A_QSFP:
2442                 /* Config MDIO clock speed before the first MDIO PHY access */
2443                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2444                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2445                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2446                 break;
2447         case IXGBE_DEV_ID_X550EM_A_1G_T:
2448         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2449                 /* Select fast MDIO clock speed for these devices */
2450                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2451                 hlreg0 |= IXGBE_HLREG0_MDCSPD;
2452                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2453                 break;
2454         default:
2455                 break;
2456         }
2457 }
2458
2459 /**
2460  *  ixgbe_reset_hw_X550em - Perform hardware reset
2461  *  @hw: pointer to hardware structure
2462  *
2463  *  Resets the hardware by resetting the transmit and receive units, masks
2464  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2465  *  reset.
2466  */
2467 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2468 {
2469         ixgbe_link_speed link_speed;
2470         s32 status;
2471         u32 ctrl = 0;
2472         u32 i;
2473         bool link_up = false;
2474
2475         DEBUGFUNC("ixgbe_reset_hw_X550em");
2476
2477         /* Call adapter stop to disable Tx/Rx and clear interrupts */
2478         status = hw->mac.ops.stop_adapter(hw);
2479         if (status != IXGBE_SUCCESS)
2480                 return status;
2481
2482         /* flush pending Tx transactions */
2483         ixgbe_clear_tx_pending(hw);
2484
2485         ixgbe_set_mdio_speed(hw);
2486
2487         /* PHY ops must be identified and initialized prior to reset */
2488         status = hw->phy.ops.init(hw);
2489
2490         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2491                 return status;
2492
2493         /* start the external PHY */
2494         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2495                 status = ixgbe_init_ext_t_x550em(hw);
2496                 if (status)
2497                         return status;
2498         }
2499
2500         /* Setup SFP module if there is one present. */
2501         if (hw->phy.sfp_setup_needed) {
2502                 status = hw->mac.ops.setup_sfp(hw);
2503                 hw->phy.sfp_setup_needed = false;
2504         }
2505
2506         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2507                 return status;
2508
2509         /* Reset PHY */
2510         if (!hw->phy.reset_disable && hw->phy.ops.reset) {
2511                 if (hw->phy.ops.reset(hw) == IXGBE_ERR_OVERTEMP)
2512                         return IXGBE_ERR_OVERTEMP;
2513         }
2514
2515 mac_reset_top:
2516         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2517          * If link reset is used when link is up, it might reset the PHY when
2518          * mng is using it.  If link is down or the flag to force full link
2519          * reset is set, then perform link reset.
2520          */
2521         ctrl = IXGBE_CTRL_LNK_RST;
2522         if (!hw->force_full_reset) {
2523                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2524                 if (link_up)
2525                         ctrl = IXGBE_CTRL_RST;
2526         }
2527
2528         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2529         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2530         IXGBE_WRITE_FLUSH(hw);
2531
2532         /* Poll for reset bit to self-clear meaning reset is complete */
2533         for (i = 0; i < 10; i++) {
2534                 usec_delay(1);
2535                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2536                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2537                         break;
2538         }
2539
2540         if (ctrl & IXGBE_CTRL_RST_MASK) {
2541                 status = IXGBE_ERR_RESET_FAILED;
2542                 DEBUGOUT("Reset polling failed to complete.\n");
2543         }
2544
2545         msec_delay(50);
2546
2547         /* Double resets are required for recovery from certain error
2548          * conditions.  Between resets, it is necessary to stall to
2549          * allow time for any pending HW events to complete.
2550          */
2551         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2552                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2553                 goto mac_reset_top;
2554         }
2555
2556         /* Store the permanent mac address */
2557         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2558
2559         /* Store MAC address from RAR0, clear receive address registers, and
2560          * clear the multicast table.  Also reset num_rar_entries to 128,
2561          * since we modify this value when programming the SAN MAC address.
2562          */
2563         hw->mac.num_rar_entries = 128;
2564         hw->mac.ops.init_rx_addrs(hw);
2565
2566         ixgbe_set_mdio_speed(hw);
2567
2568         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2569                 ixgbe_setup_mux_ctl(hw);
2570
2571         return status;
2572 }
2573
2574 /**
2575  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2576  * @hw: pointer to hardware structure
2577  */
2578 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2579 {
2580         u32 status;
2581         u16 reg;
2582
2583         status = hw->phy.ops.read_reg(hw,
2584                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2585                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2586                                       &reg);
2587
2588         if (status != IXGBE_SUCCESS)
2589                 return status;
2590
2591         /* If PHY FW reset completed bit is set then this is the first
2592          * SW instance after a power on so the PHY FW must be un-stalled.
2593          */
2594         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2595                 status = hw->phy.ops.read_reg(hw,
2596                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2597                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2598                                         &reg);
2599
2600                 if (status != IXGBE_SUCCESS)
2601                         return status;
2602
2603                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2604
2605                 status = hw->phy.ops.write_reg(hw,
2606                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2607                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2608                                         reg);
2609
2610                 if (status != IXGBE_SUCCESS)
2611                         return status;
2612         }
2613
2614         return status;
2615 }
2616
2617 /**
2618  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
2619  *  @hw: pointer to hardware structure
2620  *
2621  *  Configures the integrated KR PHY for X550EM_x.
2622  **/
2623 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2624 {
2625         if (hw->mac.type != ixgbe_mac_X550EM_x)
2626                 return IXGBE_SUCCESS;
2627
2628         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2629 }
2630
2631 /**
2632  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2633  *  @hw: pointer to hardware structure
2634  *
2635  *  Configure the external PHY and the integrated KR PHY for SFP support.
2636  **/
2637 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2638                                     ixgbe_link_speed speed,
2639                                     bool autoneg_wait_to_complete)
2640 {
2641         s32 ret_val;
2642         u16 reg_slice, reg_val;
2643         bool setup_linear = false;
2644         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2645
2646         /* Check if SFP module is supported and linear */
2647         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2648
2649         /* If no SFP module present, then return success. Return success since
2650          * there is no reason to configure CS4227 and SFP not present error is
2651          * not excepted in the setup MAC link flow.
2652          */
2653         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2654                 return IXGBE_SUCCESS;
2655
2656         if (ret_val != IXGBE_SUCCESS)
2657                 return ret_val;
2658
2659         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2660                 /* Configure CS4227 LINE side to 10G SR. */
2661                 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
2662                             (hw->bus.lan_id << 12);
2663                 reg_val = IXGBE_CS4227_SPEED_10G;
2664                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2665                                                   reg_val);
2666
2667                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2668                             (hw->bus.lan_id << 12);
2669                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2670                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2671                                                   reg_val);
2672
2673                 /* Configure CS4227 for HOST connection rate then type. */
2674                 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
2675                             (hw->bus.lan_id << 12);
2676                 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
2677                 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
2678                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2679                                                   reg_val);
2680
2681                 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
2682                             (hw->bus.lan_id << 12);
2683                 if (setup_linear)
2684                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2685                 else
2686                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2687                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2688                                                   reg_val);
2689
2690                 /* Setup XFI internal link. */
2691                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2692         } else {
2693                 /* Configure internal PHY for KR/KX. */
2694                 ixgbe_setup_kr_speed_x550em(hw, speed);
2695
2696                 /* Configure CS4227 LINE side to proper mode. */
2697                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2698                             (hw->bus.lan_id << 12);
2699                 if (setup_linear)
2700                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2701                 else
2702                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2703                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2704                                                   reg_val);
2705         }
2706         return ret_val;
2707 }
2708
2709 /**
2710  *  ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
2711  *  @hw: pointer to hardware structure
2712  *  @speed: the link speed to force
2713  *
2714  *  Configures the integrated PHY for native SFI mode. Used to connect the
2715  *  internal PHY directly to an SFP cage, without autonegotiation.
2716  **/
2717 STATIC s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2718 {
2719         struct ixgbe_mac_info *mac = &hw->mac;
2720         s32 status;
2721         u32 reg_val;
2722
2723         /* Disable all AN and force speed to 10G Serial. */
2724         status = mac->ops.read_iosf_sb_reg(hw,
2725                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2726                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2727         if (status != IXGBE_SUCCESS)
2728                 return status;
2729
2730         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2731         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2732         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2733         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2734
2735         /* Select forced link speed for internal PHY. */
2736         switch (*speed) {
2737         case IXGBE_LINK_SPEED_10GB_FULL:
2738                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
2739                 break;
2740         case IXGBE_LINK_SPEED_1GB_FULL:
2741                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2742                 break;
2743         default:
2744                 /* Other link speeds are not supported by internal PHY. */
2745                 return IXGBE_ERR_LINK_SETUP;
2746         }
2747
2748         status = mac->ops.write_iosf_sb_reg(hw,
2749                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2750                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2751
2752         /* Toggle port SW reset by AN reset. */
2753         status = ixgbe_restart_an_internal_phy_x550em(hw);
2754
2755         return status;
2756 }
2757
2758 /**
2759  *  ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2760  *  @hw: pointer to hardware structure
2761  *
2762  *  Configure the the integrated PHY for SFP support.
2763  **/
2764 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2765                                     ixgbe_link_speed speed,
2766                                     bool autoneg_wait_to_complete)
2767 {
2768         s32 ret_val;
2769         u16 reg_phy_ext;
2770         bool setup_linear = false;
2771         u32 reg_slice, reg_phy_int, slice_offset;
2772
2773         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2774
2775         /* Check if SFP module is supported and linear */
2776         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2777
2778         /* If no SFP module present, then return success. Return success since
2779          * SFP not present error is not excepted in the setup MAC link flow.
2780          */
2781         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2782                 return IXGBE_SUCCESS;
2783
2784         if (ret_val != IXGBE_SUCCESS)
2785                 return ret_val;
2786
2787         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2788                 /* Configure internal PHY for native SFI based on module type */
2789                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2790                                    IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2791                                    IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_phy_int);
2792
2793                 if (ret_val != IXGBE_SUCCESS)
2794                         return ret_val;
2795
2796                 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
2797                 if (!setup_linear)
2798                         reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
2799
2800                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2801                                    IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2802                                    IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2803
2804                 if (ret_val != IXGBE_SUCCESS)
2805                         return ret_val;
2806
2807                 /* Setup SFI internal link. */
2808                 ret_val = ixgbe_setup_sfi_x550a(hw, &speed);
2809         } else {
2810                 /* Configure internal PHY for KR/KX. */
2811                 ixgbe_setup_kr_speed_x550em(hw, speed);
2812
2813                 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2814                         /* Find Address */
2815                         DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2816                         return IXGBE_ERR_PHY_ADDR_INVALID;
2817                 }
2818
2819                 /* Get external PHY SKU id */
2820                 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,
2821                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2822
2823                 if (ret_val != IXGBE_SUCCESS)
2824                         return ret_val;
2825
2826                 /* When configuring quad port CS4223, the MAC instance is part
2827                  * of the slice offset.
2828                  */
2829                 if (reg_phy_ext == IXGBE_CS4223_SKU_ID)
2830                         slice_offset = (hw->bus.lan_id +
2831                                         (hw->bus.instance_id << 1)) << 12;
2832                 else
2833                         slice_offset = hw->bus.lan_id << 12;
2834
2835                 /* Configure CS4227/CS4223 LINE side to proper mode. */
2836                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2837                 if (setup_linear)
2838                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2839                 else
2840                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2841                 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2842                                          IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2843         }
2844         return ret_val;
2845 }
2846
2847 /**
2848  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2849  *  @hw: pointer to hardware structure
2850  *
2851  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2852  **/
2853 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2854 {
2855         struct ixgbe_mac_info *mac = &hw->mac;
2856         s32 status;
2857         u32 reg_val;
2858
2859         /* Disable training protocol FSM. */
2860         status = mac->ops.read_iosf_sb_reg(hw,
2861                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2862                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2863         if (status != IXGBE_SUCCESS)
2864                 return status;
2865         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2866         status = mac->ops.write_iosf_sb_reg(hw,
2867                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2868                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2869         if (status != IXGBE_SUCCESS)
2870                 return status;
2871
2872         /* Disable Flex from training TXFFE. */
2873         status = mac->ops.read_iosf_sb_reg(hw,
2874                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2875                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2876         if (status != IXGBE_SUCCESS)
2877                 return status;
2878         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2879         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2880         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2881         status = mac->ops.write_iosf_sb_reg(hw,
2882                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2883                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2884         if (status != IXGBE_SUCCESS)
2885                 return status;
2886         status = mac->ops.read_iosf_sb_reg(hw,
2887                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2888                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2889         if (status != IXGBE_SUCCESS)
2890                 return status;
2891         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2892         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2893         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2894         status = mac->ops.write_iosf_sb_reg(hw,
2895                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2896                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2897         if (status != IXGBE_SUCCESS)
2898                 return status;
2899
2900         /* Enable override for coefficients. */
2901         status = mac->ops.read_iosf_sb_reg(hw,
2902                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2903                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2904         if (status != IXGBE_SUCCESS)
2905                 return status;
2906         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2907         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2908         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2909         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2910         status = mac->ops.write_iosf_sb_reg(hw,
2911                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2912                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2913         return status;
2914 }
2915
2916 /**
2917  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2918  *  @hw: pointer to hardware structure
2919  *  @speed: the link speed to force
2920  *
2921  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
2922  *  internal and external PHY at a specific speed, without autonegotiation.
2923  **/
2924 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2925 {
2926         struct ixgbe_mac_info *mac = &hw->mac;
2927         s32 status;
2928         u32 reg_val;
2929
2930         /* iXFI is only supported with X552 */
2931         if (mac->type != ixgbe_mac_X550EM_x)
2932                 return IXGBE_ERR_LINK_SETUP;
2933
2934         /* Disable AN and force speed to 10G Serial. */
2935         status = mac->ops.read_iosf_sb_reg(hw,
2936                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2937                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2938         if (status != IXGBE_SUCCESS)
2939                 return status;
2940
2941         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2942         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2943
2944         /* Select forced link speed for internal PHY. */
2945         switch (*speed) {
2946         case IXGBE_LINK_SPEED_10GB_FULL:
2947                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2948                 break;
2949         case IXGBE_LINK_SPEED_1GB_FULL:
2950                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2951                 break;
2952         default:
2953                 /* Other link speeds are not supported by internal KR PHY. */
2954                 return IXGBE_ERR_LINK_SETUP;
2955         }
2956
2957         status = mac->ops.write_iosf_sb_reg(hw,
2958                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2959                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2960         if (status != IXGBE_SUCCESS)
2961                 return status;
2962
2963         /* Additional configuration needed for x550em_x */
2964         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2965                 status = ixgbe_setup_ixfi_x550em_x(hw);
2966                 if (status != IXGBE_SUCCESS)
2967                         return status;
2968         }
2969
2970         /* Toggle port SW reset by AN reset. */
2971         status = ixgbe_restart_an_internal_phy_x550em(hw);
2972
2973         return status;
2974 }
2975
2976 /**
2977  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2978  * @hw: address of hardware structure
2979  * @link_up: address of boolean to indicate link status
2980  *
2981  * Returns error code if unable to get link status.
2982  */
2983 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2984 {
2985         u32 ret;
2986         u16 autoneg_status;
2987
2988         *link_up = false;
2989
2990         /* read this twice back to back to indicate current status */
2991         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2992                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2993                                    &autoneg_status);
2994         if (ret != IXGBE_SUCCESS)
2995                 return ret;
2996
2997         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2998                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2999                                    &autoneg_status);
3000         if (ret != IXGBE_SUCCESS)
3001                 return ret;
3002
3003         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
3004
3005         return IXGBE_SUCCESS;
3006 }
3007
3008 /**
3009  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
3010  * @hw: point to hardware structure
3011  *
3012  * Configures the link between the integrated KR PHY and the external X557 PHY
3013  * The driver will call this function when it gets a link status change
3014  * interrupt from the X557 PHY. This function configures the link speed
3015  * between the PHYs to match the link speed of the BASE-T link.
3016  *
3017  * A return of a non-zero value indicates an error, and the base driver should
3018  * not report link up.
3019  */
3020 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
3021 {
3022         ixgbe_link_speed force_speed;
3023         bool link_up;
3024         u32 status;
3025         u16 speed;
3026
3027         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3028                 return IXGBE_ERR_CONFIG;
3029
3030         if (hw->mac.type == ixgbe_mac_X550EM_x &&
3031             !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3032                 /* If link is down, there is no setup necessary so return  */
3033                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3034                 if (status != IXGBE_SUCCESS)
3035                         return status;
3036
3037                 if (!link_up)
3038                         return IXGBE_SUCCESS;
3039
3040                 status = hw->phy.ops.read_reg(hw,
3041                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3042                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3043                                               &speed);
3044                 if (status != IXGBE_SUCCESS)
3045                         return status;
3046
3047                 /* If link is still down - no setup is required so return */
3048                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3049                 if (status != IXGBE_SUCCESS)
3050                         return status;
3051                 if (!link_up)
3052                         return IXGBE_SUCCESS;
3053
3054                 /* clear everything but the speed and duplex bits */
3055                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
3056
3057                 switch (speed) {
3058                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
3059                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3060                         break;
3061                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
3062                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3063                         break;
3064                 default:
3065                         /* Internal PHY does not support anything else */
3066                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
3067                 }
3068
3069                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
3070         } else {
3071                 speed = IXGBE_LINK_SPEED_10GB_FULL |
3072                         IXGBE_LINK_SPEED_1GB_FULL;
3073                 return ixgbe_setup_kr_speed_x550em(hw, speed);
3074         }
3075 }
3076
3077 /**
3078  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
3079  *  @hw: pointer to hardware structure
3080  *
3081  *  Configures the integrated KR PHY to use internal loopback mode.
3082  **/
3083 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
3084 {
3085         s32 status;
3086         u32 reg_val;
3087
3088         /* Disable AN and force speed to 10G Serial. */
3089         status = hw->mac.ops.read_iosf_sb_reg(hw,
3090                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3091                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3092         if (status != IXGBE_SUCCESS)
3093                 return status;
3094         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3095         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3096         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3097         status = hw->mac.ops.write_iosf_sb_reg(hw,
3098                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3099                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3100         if (status != IXGBE_SUCCESS)
3101                 return status;
3102
3103         /* Set near-end loopback clocks. */
3104         status = hw->mac.ops.read_iosf_sb_reg(hw,
3105                                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3106                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3107         if (status != IXGBE_SUCCESS)
3108                 return status;
3109         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3110         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3111         status = hw->mac.ops.write_iosf_sb_reg(hw,
3112                                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3113                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3114         if (status != IXGBE_SUCCESS)
3115                 return status;
3116
3117         /* Set loopback enable. */
3118         status = hw->mac.ops.read_iosf_sb_reg(hw,
3119                                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3120                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3121         if (status != IXGBE_SUCCESS)
3122                 return status;
3123         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3124         status = hw->mac.ops.write_iosf_sb_reg(hw,
3125                                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3126                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3127         if (status != IXGBE_SUCCESS)
3128                 return status;
3129
3130         /* Training bypass. */
3131         status = hw->mac.ops.read_iosf_sb_reg(hw,
3132                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3133                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3134         if (status != IXGBE_SUCCESS)
3135                 return status;
3136         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3137         status = hw->mac.ops.write_iosf_sb_reg(hw,
3138                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3139                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3140
3141         return status;
3142 }
3143
3144 /**
3145  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3146  *  assuming that the semaphore is already obtained.
3147  *  @hw: pointer to hardware structure
3148  *  @offset: offset of  word in the EEPROM to read
3149  *  @data: word read from the EEPROM
3150  *
3151  *  Reads a 16 bit word from the EEPROM using the hostif.
3152  **/
3153 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
3154 {
3155         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3156         struct ixgbe_hic_read_shadow_ram buffer;
3157         s32 status;
3158
3159         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3160         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3161         buffer.hdr.req.buf_lenh = 0;
3162         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3163         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3164
3165         /* convert offset from words to bytes */
3166         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3167         /* one word */
3168         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3169
3170         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3171         if (status)
3172                 return status;
3173
3174         status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3175                                     IXGBE_HI_COMMAND_TIMEOUT);
3176         if (!status) {
3177                 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3178                                                   FW_NVM_DATA_OFFSET);
3179         }
3180
3181         hw->mac.ops.release_swfw_sync(hw, mask);
3182         return status;
3183 }
3184
3185 /**
3186  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3187  *  @hw: pointer to hardware structure
3188  *  @offset: offset of  word in the EEPROM to read
3189  *  @words: number of words
3190  *  @data: word(s) read from the EEPROM
3191  *
3192  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
3193  **/
3194 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3195                                      u16 offset, u16 words, u16 *data)
3196 {
3197         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3198         struct ixgbe_hic_read_shadow_ram buffer;
3199         u32 current_word = 0;
3200         u16 words_to_read;
3201         s32 status;
3202         u32 i;
3203
3204         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3205
3206         /* Take semaphore for the entire operation. */
3207         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3208         if (status) {
3209                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3210                 return status;
3211         }
3212
3213         while (words) {
3214                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3215                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3216                 else
3217                         words_to_read = words;
3218
3219                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3220                 buffer.hdr.req.buf_lenh = 0;
3221                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3222                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3223
3224                 /* convert offset from words to bytes */
3225                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3226                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3227
3228                 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3229                                             IXGBE_HI_COMMAND_TIMEOUT);
3230
3231                 if (status) {
3232                         DEBUGOUT("Host interface command failed\n");
3233                         goto out;
3234                 }
3235
3236                 for (i = 0; i < words_to_read; i++) {
3237                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3238                                   2 * i;
3239                         u32 value = IXGBE_READ_REG(hw, reg);
3240
3241                         data[current_word] = (u16)(value & 0xffff);
3242                         current_word++;
3243                         i++;
3244                         if (i < words_to_read) {
3245                                 value >>= 16;
3246                                 data[current_word] = (u16)(value & 0xffff);
3247                                 current_word++;
3248                         }
3249                 }
3250                 words -= words_to_read;
3251         }
3252
3253 out:
3254         hw->mac.ops.release_swfw_sync(hw, mask);
3255         return status;
3256 }
3257
3258 /**
3259  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3260  *  @hw: pointer to hardware structure
3261  *  @offset: offset of  word in the EEPROM to write
3262  *  @data: word write to the EEPROM
3263  *
3264  *  Write a 16 bit word to the EEPROM using the hostif.
3265  **/
3266 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3267                                     u16 data)
3268 {
3269         s32 status;
3270         struct ixgbe_hic_write_shadow_ram buffer;
3271
3272         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3273
3274         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3275         buffer.hdr.req.buf_lenh = 0;
3276         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3277         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3278
3279          /* one word */
3280         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3281         buffer.data = data;
3282         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3283
3284         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3285                                               sizeof(buffer),
3286                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3287
3288         return status;
3289 }
3290
3291 /**
3292  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3293  *  @hw: pointer to hardware structure
3294  *  @offset: offset of  word in the EEPROM to write
3295  *  @data: word write to the EEPROM
3296  *
3297  *  Write a 16 bit word to the EEPROM using the hostif.
3298  **/
3299 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3300                                u16 data)
3301 {
3302         s32 status = IXGBE_SUCCESS;
3303
3304         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3305
3306         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3307             IXGBE_SUCCESS) {
3308                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3309                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3310         } else {
3311                 DEBUGOUT("write ee hostif failed to get semaphore");
3312                 status = IXGBE_ERR_SWFW_SYNC;
3313         }
3314
3315         return status;
3316 }
3317
3318 /**
3319  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3320  *  @hw: pointer to hardware structure
3321  *  @offset: offset of  word in the EEPROM to write
3322  *  @words: number of words
3323  *  @data: word(s) write to the EEPROM
3324  *
3325  *  Write a 16 bit word(s) to the EEPROM using the hostif.
3326  **/
3327 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3328                                       u16 offset, u16 words, u16 *data)
3329 {
3330         s32 status = IXGBE_SUCCESS;
3331         u32 i = 0;
3332
3333         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3334
3335         /* Take semaphore for the entire operation. */
3336         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3337         if (status != IXGBE_SUCCESS) {
3338                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3339                 goto out;
3340         }
3341
3342         for (i = 0; i < words; i++) {
3343                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3344                                                          data[i]);
3345
3346                 if (status != IXGBE_SUCCESS) {
3347                         DEBUGOUT("Eeprom buffered write failed\n");
3348                         break;
3349                 }
3350         }
3351
3352         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3353 out:
3354
3355         return status;
3356 }
3357
3358 /**
3359  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3360  * @hw: pointer to hardware structure
3361  * @ptr: pointer offset in eeprom
3362  * @size: size of section pointed by ptr, if 0 first word will be used as size
3363  * @csum: address of checksum to update
3364  *
3365  * Returns error status for any failure
3366  */
3367 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3368                                    u16 size, u16 *csum, u16 *buffer,
3369                                    u32 buffer_size)
3370 {
3371         u16 buf[256];
3372         s32 status;
3373         u16 length, bufsz, i, start;
3374         u16 *local_buffer;
3375
3376         bufsz = sizeof(buf) / sizeof(buf[0]);
3377
3378         /* Read a chunk at the pointer location */
3379         if (!buffer) {
3380                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3381                 if (status) {
3382                         DEBUGOUT("Failed to read EEPROM image\n");
3383                         return status;
3384                 }
3385                 local_buffer = buf;
3386         } else {
3387                 if (buffer_size < ptr)
3388                         return  IXGBE_ERR_PARAM;
3389                 local_buffer = &buffer[ptr];
3390         }
3391
3392         if (size) {
3393                 start = 0;
3394                 length = size;
3395         } else {
3396                 start = 1;
3397                 length = local_buffer[0];
3398
3399                 /* Skip pointer section if length is invalid. */
3400                 if (length == 0xFFFF || length == 0 ||
3401                     (ptr + length) >= hw->eeprom.word_size)
3402                         return IXGBE_SUCCESS;
3403         }
3404
3405         if (buffer && ((u32)start + (u32)length > buffer_size))
3406                 return IXGBE_ERR_PARAM;
3407
3408         for (i = start; length; i++, length--) {
3409                 if (i == bufsz && !buffer) {
3410                         ptr += bufsz;
3411                         i = 0;
3412                         if (length < bufsz)
3413                                 bufsz = length;
3414
3415                         /* Read a chunk at the pointer location */
3416                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3417                                                                   bufsz, buf);
3418                         if (status) {
3419                                 DEBUGOUT("Failed to read EEPROM image\n");
3420                                 return status;
3421                         }
3422                 }
3423                 *csum += local_buffer[i];
3424         }
3425         return IXGBE_SUCCESS;
3426 }
3427
3428 /**
3429  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3430  *  @hw: pointer to hardware structure
3431  *  @buffer: pointer to buffer containing calculated checksum
3432  *  @buffer_size: size of buffer
3433  *
3434  *  Returns a negative error code on error, or the 16-bit checksum
3435  **/
3436 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3437 {
3438         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3439         u16 *local_buffer;
3440         s32 status;
3441         u16 checksum = 0;
3442         u16 pointer, i, size;
3443
3444         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3445
3446         hw->eeprom.ops.init_params(hw);
3447
3448         if (!buffer) {
3449                 /* Read pointer area */
3450                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3451                                                      IXGBE_EEPROM_LAST_WORD + 1,
3452                                                      eeprom_ptrs);
3453                 if (status) {
3454                         DEBUGOUT("Failed to read EEPROM image\n");
3455                         return status;
3456                 }
3457                 local_buffer = eeprom_ptrs;
3458         } else {
3459                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3460                         return IXGBE_ERR_PARAM;
3461                 local_buffer = buffer;
3462         }
3463
3464         /*
3465          * For X550 hardware include 0x0-0x41 in the checksum, skip the
3466          * checksum word itself
3467          */
3468         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3469                 if (i != IXGBE_EEPROM_CHECKSUM)
3470                         checksum += local_buffer[i];
3471
3472         /*
3473          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
3474          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3475          */
3476         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3477                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3478                         continue;
3479
3480                 pointer = local_buffer[i];
3481
3482                 /* Skip pointer section if the pointer is invalid. */
3483                 if (pointer == 0xFFFF || pointer == 0 ||
3484                     pointer >= hw->eeprom.word_size)
3485                         continue;
3486
3487                 switch (i) {
3488                 case IXGBE_PCIE_GENERAL_PTR:
3489                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3490                         break;
3491                 case IXGBE_PCIE_CONFIG0_PTR:
3492                 case IXGBE_PCIE_CONFIG1_PTR:
3493                         size = IXGBE_PCIE_CONFIG_SIZE;
3494                         break;
3495                 default:
3496                         size = 0;
3497                         break;
3498                 }
3499
3500                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3501                                                 buffer, buffer_size);
3502                 if (status)
3503                         return status;
3504         }
3505
3506         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3507
3508         return (s32)checksum;
3509 }
3510
3511 /**
3512  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3513  *  @hw: pointer to hardware structure
3514  *
3515  *  Returns a negative error code on error, or the 16-bit checksum
3516  **/
3517 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3518 {
3519         return ixgbe_calc_checksum_X550(hw, NULL, 0);
3520 }
3521
3522 /**
3523  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3524  *  @hw: pointer to hardware structure
3525  *  @checksum_val: calculated checksum
3526  *
3527  *  Performs checksum calculation and validates the EEPROM checksum.  If the
3528  *  caller does not need checksum_val, the value can be NULL.
3529  **/
3530 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3531 {
3532         s32 status;
3533         u16 checksum;
3534         u16 read_checksum = 0;
3535
3536         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3537
3538         /* Read the first word from the EEPROM. If this times out or fails, do
3539          * not continue or we could be in for a very long wait while every
3540          * EEPROM read fails
3541          */
3542         status = hw->eeprom.ops.read(hw, 0, &checksum);
3543         if (status) {
3544                 DEBUGOUT("EEPROM read failed\n");
3545                 return status;
3546         }
3547
3548         status = hw->eeprom.ops.calc_checksum(hw);
3549         if (status < 0)
3550                 return status;
3551
3552         checksum = (u16)(status & 0xffff);
3553
3554         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3555                                            &read_checksum);
3556         if (status)
3557                 return status;
3558
3559         /* Verify read checksum from EEPROM is the same as
3560          * calculated checksum
3561          */
3562         if (read_checksum != checksum) {
3563                 status = IXGBE_ERR_EEPROM_CHECKSUM;
3564                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3565                              "Invalid EEPROM checksum");
3566         }
3567
3568         /* If the user cares, return the calculated checksum */
3569         if (checksum_val)
3570                 *checksum_val = checksum;
3571
3572         return status;
3573 }
3574
3575 /**
3576  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3577  * @hw: pointer to hardware structure
3578  *
3579  * After writing EEPROM to shadow RAM using EEWR register, software calculates
3580  * checksum and updates the EEPROM and instructs the hardware to update
3581  * the flash.
3582  **/
3583 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3584 {
3585         s32 status;
3586         u16 checksum = 0;
3587
3588         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3589
3590         /* Read the first word from the EEPROM. If this times out or fails, do
3591          * not continue or we could be in for a very long wait while every
3592          * EEPROM read fails
3593          */
3594         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3595         if (status) {
3596                 DEBUGOUT("EEPROM read failed\n");
3597                 return status;
3598         }
3599
3600         status = ixgbe_calc_eeprom_checksum_X550(hw);
3601         if (status < 0)
3602                 return status;
3603
3604         checksum = (u16)(status & 0xffff);
3605
3606         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3607                                             checksum);
3608         if (status)
3609                 return status;
3610
3611         status = ixgbe_update_flash_X550(hw);
3612
3613         return status;
3614 }
3615
3616 /**
3617  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3618  *  @hw: pointer to hardware structure
3619  *
3620  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3621  **/
3622 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3623 {
3624         s32 status = IXGBE_SUCCESS;
3625         union ixgbe_hic_hdr2 buffer;
3626
3627         DEBUGFUNC("ixgbe_update_flash_X550");
3628
3629         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3630         buffer.req.buf_lenh = 0;
3631         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3632         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3633
3634         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3635                                               sizeof(buffer),
3636                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3637
3638         return status;
3639 }
3640
3641 /**
3642  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3643  *  @hw: pointer to hardware structure
3644  *
3645  *  Determines physical layer capabilities of the current configuration.
3646  **/
3647 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3648 {
3649         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3650         u16 ext_ability = 0;
3651
3652         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3653
3654         hw->phy.ops.identify(hw);
3655
3656         switch (hw->phy.type) {
3657         case ixgbe_phy_x550em_kr:
3658                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3659                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3660                 break;
3661         case ixgbe_phy_x550em_kx4:
3662                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3663                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3664                 break;
3665         case ixgbe_phy_x550em_ext_t:
3666                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3667                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3668                                      &ext_ability);
3669                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3670                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3671                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3672                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3673                 break;
3674         case ixgbe_phy_fw:
3675                 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_1GB_FULL)
3676                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3677                 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_100_FULL)
3678                         physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
3679                 if (hw->phy.speeds_supported & IXGBE_LINK_SPEED_10_FULL)
3680                         physical_layer |= IXGBE_PHYSICAL_LAYER_10BASE_T;
3681                 break;
3682         default:
3683                 break;
3684         }
3685
3686         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3687                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3688
3689         return physical_layer;
3690 }
3691
3692 /**
3693  * ixgbe_get_bus_info_x550em - Set PCI bus info
3694  * @hw: pointer to hardware structure
3695  *
3696  * Sets bus link width and speed to unknown because X550em is
3697  * not a PCI device.
3698  **/
3699 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3700 {
3701
3702         DEBUGFUNC("ixgbe_get_bus_info_x550em");
3703
3704         hw->bus.width = ixgbe_bus_width_unknown;
3705         hw->bus.speed = ixgbe_bus_speed_unknown;
3706
3707         hw->mac.ops.set_lan_id(hw);
3708
3709         return IXGBE_SUCCESS;
3710 }
3711
3712 /**
3713  * ixgbe_disable_rx_x550 - Disable RX unit
3714  *
3715  * Enables the Rx DMA unit for x550
3716  **/
3717 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3718 {
3719         u32 rxctrl, pfdtxgswc;
3720         s32 status;
3721         struct ixgbe_hic_disable_rxen fw_cmd;
3722
3723         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3724
3725         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3726         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3727                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3728                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3729                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3730                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3731                         hw->mac.set_lben = true;
3732                 } else {
3733                         hw->mac.set_lben = false;
3734                 }
3735
3736                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3737                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3738                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3739                 fw_cmd.port_number = (u8)hw->bus.lan_id;
3740
3741                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3742                                         sizeof(struct ixgbe_hic_disable_rxen),
3743                                         IXGBE_HI_COMMAND_TIMEOUT, true);
3744
3745                 /* If we fail - disable RX using register write */
3746                 if (status) {
3747                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3748                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3749                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3750                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3751                         }
3752                 }
3753         }
3754 }
3755
3756 /**
3757  * ixgbe_enter_lplu_x550em - Transition to low power states
3758  *  @hw: pointer to hardware structure
3759  *
3760  * Configures Low Power Link Up on transition to low power states
3761  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3762  * X557 PHY immediately prior to entering LPLU.
3763  **/
3764 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3765 {
3766         u16 an_10g_cntl_reg, autoneg_reg, speed;
3767         s32 status;
3768         ixgbe_link_speed lcd_speed;
3769         u32 save_autoneg;
3770         bool link_up;
3771
3772         /* SW LPLU not required on later HW revisions. */
3773         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3774             (IXGBE_FUSES0_REV_MASK &
3775              IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3776                 return IXGBE_SUCCESS;
3777
3778         /* If blocked by MNG FW, then don't restart AN */
3779         if (ixgbe_check_reset_blocked(hw))
3780                 return IXGBE_SUCCESS;
3781
3782         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3783         if (status != IXGBE_SUCCESS)
3784                 return status;
3785
3786         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3787
3788         if (status != IXGBE_SUCCESS)
3789                 return status;
3790
3791         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3792          * disabled, then force link down by entering low power mode.
3793          */
3794         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3795             !(hw->wol_enabled || ixgbe_mng_present(hw)))
3796                 return ixgbe_set_copper_phy_power(hw, FALSE);
3797
3798         /* Determine LCD */
3799         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3800
3801         if (status != IXGBE_SUCCESS)
3802                 return status;
3803
3804         /* If no valid LCD link speed, then force link down and exit. */
3805         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3806                 return ixgbe_set_copper_phy_power(hw, FALSE);
3807
3808         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3809                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3810                                       &speed);
3811
3812         if (status != IXGBE_SUCCESS)
3813                 return status;
3814
3815         /* If no link now, speed is invalid so take link down */
3816         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3817         if (status != IXGBE_SUCCESS)
3818                 return ixgbe_set_copper_phy_power(hw, false);
3819
3820         /* clear everything but the speed bits */
3821         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3822
3823         /* If current speed is already LCD, then exit. */
3824         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3825              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3826             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3827              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3828                 return status;
3829
3830         /* Clear AN completed indication */
3831         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3832                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3833                                       &autoneg_reg);
3834
3835         if (status != IXGBE_SUCCESS)
3836                 return status;
3837
3838         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3839                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3840                              &an_10g_cntl_reg);
3841
3842         if (status != IXGBE_SUCCESS)
3843                 return status;
3844
3845         status = hw->phy.ops.read_reg(hw,
3846                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3847                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3848                              &autoneg_reg);
3849
3850         if (status != IXGBE_SUCCESS)
3851                 return status;
3852
3853         save_autoneg = hw->phy.autoneg_advertised;
3854
3855         /* Setup link at least common link speed */
3856         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3857
3858         /* restore autoneg from before setting lplu speed */
3859         hw->phy.autoneg_advertised = save_autoneg;
3860
3861         return status;
3862 }
3863
3864 /**
3865  * ixgbe_get_lcd_x550em - Determine lowest common denominator
3866  *  @hw: pointer to hardware structure
3867  *  @lcd_speed: pointer to lowest common link speed
3868  *
3869  * Determine lowest common link speed with link partner.
3870  **/
3871 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3872 {
3873         u16 an_lp_status;
3874         s32 status;
3875         u16 word = hw->eeprom.ctrl_word_3;
3876
3877         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3878
3879         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3880                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3881                                       &an_lp_status);
3882
3883         if (status != IXGBE_SUCCESS)
3884                 return status;
3885
3886         /* If link partner advertised 1G, return 1G */
3887         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3888                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3889                 return status;
3890         }
3891
3892         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3893         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3894             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3895                 return status;
3896
3897         /* Link partner not capable of lower speeds, return 10G */
3898         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3899         return status;
3900 }
3901
3902 /**
3903  *  ixgbe_setup_fc_X550em - Set up flow control
3904  *  @hw: pointer to hardware structure
3905  *
3906  *  Called at init time to set up flow control.
3907  **/
3908 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3909 {
3910         s32 ret_val = IXGBE_SUCCESS;
3911         u32 pause, asm_dir, reg_val;
3912
3913         DEBUGFUNC("ixgbe_setup_fc_X550em");
3914
3915         /* Validate the requested mode */
3916         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3917                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3918                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3919                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3920                 goto out;
3921         }
3922
3923         /* 10gig parts do not have a word in the EEPROM to determine the
3924          * default flow control setting, so we explicitly set it to full.
3925          */
3926         if (hw->fc.requested_mode == ixgbe_fc_default)
3927                 hw->fc.requested_mode = ixgbe_fc_full;
3928
3929         /* Determine PAUSE and ASM_DIR bits. */
3930         switch (hw->fc.requested_mode) {
3931         case ixgbe_fc_none:
3932                 pause = 0;
3933                 asm_dir = 0;
3934                 break;
3935         case ixgbe_fc_tx_pause:
3936                 pause = 0;
3937                 asm_dir = 1;
3938                 break;
3939         case ixgbe_fc_rx_pause:
3940                 /* Rx Flow control is enabled and Tx Flow control is
3941                  * disabled by software override. Since there really
3942                  * isn't a way to advertise that we are capable of RX
3943                  * Pause ONLY, we will advertise that we support both
3944                  * symmetric and asymmetric Rx PAUSE, as such we fall
3945                  * through to the fc_full statement.  Later, we will
3946                  * disable the adapter's ability to send PAUSE frames.
3947                  */
3948         case ixgbe_fc_full:
3949                 pause = 1;
3950                 asm_dir = 1;
3951                 break;
3952         default:
3953                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3954                         "Flow control param set incorrectly\n");
3955                 ret_val = IXGBE_ERR_CONFIG;
3956                 goto out;
3957         }
3958
3959         switch (hw->device_id) {
3960         case IXGBE_DEV_ID_X550EM_X_KR:
3961         case IXGBE_DEV_ID_X550EM_A_KR:
3962         case IXGBE_DEV_ID_X550EM_A_KR_L:
3963                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
3964                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3965                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3966                 if (ret_val != IXGBE_SUCCESS)
3967                         goto out;
3968                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3969                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3970                 if (pause)
3971                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3972                 if (asm_dir)
3973                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3974                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
3975                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3976                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3977
3978                 /* This device does not fully support AN. */
3979                 hw->fc.disable_fc_autoneg = true;
3980                 break;
3981         default:
3982                 break;
3983         }
3984
3985 out:
3986         return ret_val;
3987 }
3988
3989 /**
3990  *  ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
3991  *  @hw: pointer to hardware structure
3992  *
3993  *  Enable flow control according to IEEE clause 37.
3994  **/
3995 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
3996 {
3997         u32 link_s1, lp_an_page_low, an_cntl_1;
3998         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
3999         ixgbe_link_speed speed;
4000         bool link_up;
4001
4002         /* AN should have completed when the cable was plugged in.
4003          * Look for reasons to bail out.  Bail out if:
4004          * - FC autoneg is disabled, or if
4005          * - link is not up.
4006          */
4007         if (hw->fc.disable_fc_autoneg) {
4008                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4009                              "Flow control autoneg is disabled");
4010                 goto out;
4011         }
4012
4013         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4014         if (!link_up) {
4015                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4016                 goto out;
4017         }
4018
4019         /* Check at auto-negotiation has completed */
4020         status = hw->mac.ops.read_iosf_sb_reg(hw,
4021                                         IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4022                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4023
4024         if (status != IXGBE_SUCCESS ||
4025             (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4026                 DEBUGOUT("Auto-Negotiation did not complete\n");
4027                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4028                 goto out;
4029         }
4030
4031         /* Read the 10g AN autoc and LP ability registers and resolve
4032          * local flow control settings accordingly
4033          */
4034         status = hw->mac.ops.read_iosf_sb_reg(hw,
4035                                 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4036                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
4037
4038         if (status != IXGBE_SUCCESS) {
4039                 DEBUGOUT("Auto-Negotiation did not complete\n");
4040                 goto out;
4041         }
4042
4043         status = hw->mac.ops.read_iosf_sb_reg(hw,
4044                                 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
4045                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
4046
4047         if (status != IXGBE_SUCCESS) {
4048                 DEBUGOUT("Auto-Negotiation did not complete\n");
4049                 goto out;
4050         }
4051
4052         status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
4053                                     IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
4054                                     IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
4055                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
4056                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
4057
4058 out:
4059         if (status == IXGBE_SUCCESS) {
4060                 hw->fc.fc_was_autonegged = true;
4061         } else {
4062                 hw->fc.fc_was_autonegged = false;
4063                 hw->fc.current_mode = hw->fc.requested_mode;
4064         }
4065 }
4066
4067 /**
4068  *  ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
4069  *  @hw: pointer to hardware structure
4070  *
4071  **/
4072 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
4073 {
4074         hw->fc.fc_was_autonegged = false;
4075         hw->fc.current_mode = hw->fc.requested_mode;
4076 }
4077
4078 /**
4079  *  ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
4080  *  @hw: pointer to hardware structure
4081  *
4082  *  Enable flow control according to IEEE clause 37.
4083  **/
4084 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
4085 {
4086         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4087         u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
4088         ixgbe_link_speed speed;
4089         bool link_up;
4090
4091         /* AN should have completed when the cable was plugged in.
4092          * Look for reasons to bail out.  Bail out if:
4093          * - FC autoneg is disabled, or if
4094          * - link is not up.
4095          */
4096         if (hw->fc.disable_fc_autoneg) {
4097                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4098                              "Flow control autoneg is disabled");
4099                 goto out;
4100         }
4101
4102         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4103         if (!link_up) {
4104                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4105                 goto out;
4106         }
4107
4108         /* Check if auto-negotiation has completed */
4109         status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info);
4110         if (status != IXGBE_SUCCESS ||
4111             !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) {
4112                 DEBUGOUT("Auto-Negotiation did not complete\n");
4113                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4114                 goto out;
4115         }
4116
4117         /* Negotiate the flow control */
4118         status = ixgbe_negotiate_fc(hw, info[0], info[0],
4119                                     FW_PHY_ACT_GET_LINK_INFO_FC_RX,
4120                                     FW_PHY_ACT_GET_LINK_INFO_FC_TX,
4121                                     FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX,
4122                                     FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX);
4123
4124 out:
4125         if (status == IXGBE_SUCCESS) {
4126                 hw->fc.fc_was_autonegged = true;
4127         } else {
4128                 hw->fc.fc_was_autonegged = false;
4129                 hw->fc.current_mode = hw->fc.requested_mode;
4130         }
4131 }
4132
4133 /**
4134  *  ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4135  *  @hw: pointer to hardware structure
4136  *
4137  *  Called at init time to set up flow control.
4138  **/
4139 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4140 {
4141         s32 status = IXGBE_SUCCESS;
4142         u32 an_cntl = 0;
4143
4144         DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4145
4146         /* Validate the requested mode */
4147         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4148                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4149                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4150                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4151         }
4152
4153         if (hw->fc.requested_mode == ixgbe_fc_default)
4154                 hw->fc.requested_mode = ixgbe_fc_full;
4155
4156         /* Set up the 1G and 10G flow control advertisement registers so the
4157          * HW will be able to do FC autoneg once the cable is plugged in.  If
4158          * we link at 10G, the 1G advertisement is harmless and vice versa.
4159          */
4160         status = hw->mac.ops.read_iosf_sb_reg(hw,
4161                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4162                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4163
4164         if (status != IXGBE_SUCCESS) {
4165                 DEBUGOUT("Auto-Negotiation did not complete\n");
4166                 return status;
4167         }
4168
4169         /* The possible values of fc.requested_mode are:
4170          * 0: Flow control is completely disabled
4171          * 1: Rx flow control is enabled (we can receive pause frames,
4172          *    but not send pause frames).
4173          * 2: Tx flow control is enabled (we can send pause frames but
4174          *    we do not support receiving pause frames).
4175          * 3: Both Rx and Tx flow control (symmetric) are enabled.
4176          * other: Invalid.
4177          */
4178         switch (hw->fc.requested_mode) {
4179         case ixgbe_fc_none:
4180                 /* Flow control completely disabled by software override. */
4181                 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4182                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4183                 break;
4184         case ixgbe_fc_tx_pause:
4185                 /* Tx Flow control is enabled, and Rx Flow control is
4186                  * disabled by software override.
4187                  */
4188                 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4189                 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4190                 break;
4191         case ixgbe_fc_rx_pause:
4192                 /* Rx Flow control is enabled and Tx Flow control is
4193                  * disabled by software override. Since there really
4194                  * isn't a way to advertise that we are capable of RX
4195                  * Pause ONLY, we will advertise that we support both
4196                  * symmetric and asymmetric Rx PAUSE, as such we fall
4197                  * through to the fc_full statement.  Later, we will
4198                  * disable the adapter's ability to send PAUSE frames.
4199                  */
4200         case ixgbe_fc_full:
4201                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4202                 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4203                            IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4204                 break;
4205         default:
4206                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4207                               "Flow control param set incorrectly\n");
4208                 return IXGBE_ERR_CONFIG;
4209         }
4210
4211         status = hw->mac.ops.write_iosf_sb_reg(hw,
4212                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4213                                         IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4214
4215         /* Restart auto-negotiation. */
4216         status = ixgbe_restart_an_internal_phy_x550em(hw);
4217
4218         return status;
4219 }
4220
4221 /**
4222  * ixgbe_set_mux - Set mux for port 1 access with CS4227
4223  * @hw: pointer to hardware structure
4224  * @state: set mux if 1, clear if 0
4225  */
4226 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4227 {
4228         u32 esdp;
4229
4230         if (!hw->bus.lan_id)
4231                 return;
4232         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4233         if (state)
4234                 esdp |= IXGBE_ESDP_SDP1;
4235         else
4236                 esdp &= ~IXGBE_ESDP_SDP1;
4237         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4238         IXGBE_WRITE_FLUSH(hw);
4239 }
4240
4241 /**
4242  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4243  *  @hw: pointer to hardware structure
4244  *  @mask: Mask to specify which semaphore to acquire
4245  *
4246  *  Acquires the SWFW semaphore and sets the I2C MUX
4247  **/
4248 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4249 {
4250         s32 status;
4251
4252         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4253
4254         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4255         if (status)
4256                 return status;
4257
4258         if (mask & IXGBE_GSSR_I2C_MASK)
4259                 ixgbe_set_mux(hw, 1);
4260
4261         return IXGBE_SUCCESS;
4262 }
4263
4264 /**
4265  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4266  *  @hw: pointer to hardware structure
4267  *  @mask: Mask to specify which semaphore to release
4268  *
4269  *  Releases the SWFW semaphore and sets the I2C MUX
4270  **/
4271 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4272 {
4273         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4274
4275         if (mask & IXGBE_GSSR_I2C_MASK)
4276                 ixgbe_set_mux(hw, 0);
4277
4278         ixgbe_release_swfw_sync_X540(hw, mask);
4279 }
4280
4281 /**
4282  *  ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4283  *  @hw: pointer to hardware structure
4284  *  @mask: Mask to specify which semaphore to acquire
4285  *
4286  *  Acquires the SWFW semaphore and get the shared phy token as needed
4287  */
4288 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4289 {
4290         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4291         int retries = FW_PHY_TOKEN_RETRIES;
4292         s32 status = IXGBE_SUCCESS;
4293
4294         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4295
4296         while (--retries) {
4297                 status = IXGBE_SUCCESS;
4298                 if (hmask)
4299                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4300                 if (status)
4301                         return status;
4302                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4303                         return IXGBE_SUCCESS;
4304
4305                 status = ixgbe_get_phy_token(hw);
4306                 if (status == IXGBE_SUCCESS)
4307                         return IXGBE_SUCCESS;
4308
4309                 if (hmask)
4310                         ixgbe_release_swfw_sync_X540(hw, hmask);
4311                 if (status != IXGBE_ERR_TOKEN_RETRY)
4312                         return status;
4313         }
4314
4315         return status;
4316 }
4317
4318 /**
4319  *  ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4320  *  @hw: pointer to hardware structure
4321  *  @mask: Mask to specify which semaphore to release
4322  *
4323  *  Releases the SWFW semaphore and puts the shared phy token as needed
4324  */
4325 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4326 {
4327         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4328
4329         DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4330
4331         if (mask & IXGBE_GSSR_TOKEN_SM)
4332                 ixgbe_put_phy_token(hw);
4333
4334         if (hmask)
4335                 ixgbe_release_swfw_sync_X540(hw, hmask);
4336 }
4337
4338 /**
4339  *  ixgbe_read_phy_reg_x550a  - Reads specified PHY register
4340  *  @hw: pointer to hardware structure
4341  *  @reg_addr: 32 bit address of PHY register to read
4342  *  @phy_data: Pointer to read data from PHY register
4343  *
4344  *  Reads a value from a specified PHY register using the SWFW lock and PHY
4345  *  Token. The PHY Token is needed since the MDIO is shared between to MAC
4346  *  instances.
4347  **/
4348 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4349                                u32 device_type, u16 *phy_data)
4350 {
4351         s32 status;
4352         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4353
4354         DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4355
4356         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4357                 return IXGBE_ERR_SWFW_SYNC;
4358
4359         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4360
4361         hw->mac.ops.release_swfw_sync(hw, mask);
4362
4363         return status;
4364 }
4365
4366 /**
4367  *  ixgbe_write_phy_reg_x550a - Writes specified PHY register
4368  *  @hw: pointer to hardware structure
4369  *  @reg_addr: 32 bit PHY register to write
4370  *  @device_type: 5 bit device type
4371  *  @phy_data: Data to write to the PHY register
4372  *
4373  *  Writes a value to specified PHY register using the SWFW lock and PHY Token.
4374  *  The PHY Token is needed since the MDIO is shared between to MAC instances.
4375  **/
4376 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4377                                 u32 device_type, u16 phy_data)
4378 {
4379         s32 status;
4380         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4381
4382         DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4383
4384         if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4385                 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
4386                                                  phy_data);
4387                 hw->mac.ops.release_swfw_sync(hw, mask);
4388         } else {
4389                 status = IXGBE_ERR_SWFW_SYNC;
4390         }
4391
4392         return status;
4393 }
4394
4395 /**
4396  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4397  * @hw: pointer to hardware structure
4398  *
4399  * Handle external Base T PHY interrupt. If high temperature
4400  * failure alarm then return error, else if link status change
4401  * then setup internal/external PHY link
4402  *
4403  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4404  * failure alarm, else return PHY access status.
4405  */
4406 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4407 {
4408         bool lsc;
4409         u32 status;
4410
4411         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4412
4413         if (status != IXGBE_SUCCESS)
4414                 return status;
4415
4416         if (lsc)
4417                 return ixgbe_setup_internal_phy(hw);
4418
4419         return IXGBE_SUCCESS;
4420 }
4421
4422 /**
4423  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4424  * @hw: pointer to hardware structure
4425  * @speed: new link speed
4426  * @autoneg_wait_to_complete: true when waiting for completion is needed
4427  *
4428  * Setup internal/external PHY link speed based on link speed, then set
4429  * external PHY auto advertised link speed.
4430  *
4431  * Returns error status for any failure
4432  **/
4433 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4434                                   ixgbe_link_speed speed,
4435                                   bool autoneg_wait_to_complete)
4436 {
4437         s32 status;
4438         ixgbe_link_speed force_speed;
4439
4440         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4441
4442         /* Setup internal/external PHY link speed to iXFI (10G), unless
4443          * only 1G is auto advertised then setup KX link.
4444          */
4445         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4446                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4447         else
4448                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4449
4450         /* If X552 and internal link mode is XFI, then setup XFI internal link.
4451          */
4452         if (hw->mac.type == ixgbe_mac_X550EM_x &&
4453             !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4454                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4455
4456                 if (status != IXGBE_SUCCESS)
4457                         return status;
4458         }
4459
4460         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4461 }
4462
4463 /**
4464  * ixgbe_check_link_t_X550em - Determine link and speed status
4465  * @hw: pointer to hardware structure
4466  * @speed: pointer to link speed
4467  * @link_up: true when link is up
4468  * @link_up_wait_to_complete: bool used to wait for link up or not
4469  *
4470  * Check that both the MAC and X557 external PHY have link.
4471  **/
4472 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4473                               bool *link_up, bool link_up_wait_to_complete)
4474 {
4475         u32 status;
4476         u16 i, autoneg_status = 0;
4477
4478         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4479                 return IXGBE_ERR_CONFIG;
4480
4481         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4482                                               link_up_wait_to_complete);
4483
4484         /* If check link fails or MAC link is not up, then return */
4485         if (status != IXGBE_SUCCESS || !(*link_up))
4486                 return status;
4487
4488         /* MAC link is up, so check external PHY link.
4489          * X557 PHY. Link status is latching low, and can only be used to detect
4490          * link drop, and not the current status of the link without performing
4491          * back-to-back reads.
4492          */
4493         for (i = 0; i < 2; i++) {
4494                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4495                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4496                                               &autoneg_status);
4497
4498                 if (status != IXGBE_SUCCESS)
4499                         return status;
4500         }
4501
4502         /* If external PHY link is not up, then indicate link not up */
4503         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4504                 *link_up = false;
4505
4506         return IXGBE_SUCCESS;
4507 }
4508
4509 /**
4510  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4511  *  @hw: pointer to hardware structure
4512  **/
4513 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4514 {
4515         s32 status;
4516
4517         status = ixgbe_reset_phy_generic(hw);
4518
4519         if (status != IXGBE_SUCCESS)
4520                 return status;
4521
4522         /* Configure Link Status Alarm and Temperature Threshold interrupts */
4523         return ixgbe_enable_lasi_ext_t_x550em(hw);
4524 }
4525
4526 /**
4527  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4528  *  @hw: pointer to hardware structure
4529  *  @led_idx: led number to turn on
4530  **/
4531 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4532 {
4533         u16 phy_data;
4534
4535         DEBUGFUNC("ixgbe_led_on_t_X550em");
4536
4537         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4538                 return IXGBE_ERR_PARAM;
4539
4540         /* To turn on the LED, set mode to ON. */
4541         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4542                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4543         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4544         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4545                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4546
4547         return IXGBE_SUCCESS;
4548 }
4549
4550 /**
4551  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4552  *  @hw: pointer to hardware structure
4553  *  @led_idx: led number to turn off
4554  **/
4555 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4556 {
4557         u16 phy_data;
4558
4559         DEBUGFUNC("ixgbe_led_off_t_X550em");
4560
4561         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4562                 return IXGBE_ERR_PARAM;
4563
4564         /* To turn on the LED, set mode to ON. */
4565         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4566                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4567         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4568         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4569                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4570
4571         return IXGBE_SUCCESS;
4572 }
4573
4574 /**
4575  *  ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware
4576  *  @hw: pointer to the HW structure
4577  *  @maj: driver version major number
4578  *  @min: driver version minor number
4579  *  @build: driver version build number
4580  *  @sub: driver version sub build number
4581  *  @len: length of driver_ver string
4582  *  @driver_ver: driver string
4583  *
4584  *  Sends driver version number to firmware through the manageability
4585  *  block.  On success return IXGBE_SUCCESS
4586  *  else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4587  *  semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4588  **/
4589 s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,
4590                               u8 build, u8 sub, u16 len, const char *driver_ver)
4591 {
4592         struct ixgbe_hic_drv_info2 fw_cmd;
4593         s32 ret_val = IXGBE_SUCCESS;
4594         int i;
4595
4596         DEBUGFUNC("ixgbe_set_fw_drv_ver_x550");
4597
4598         if ((len == 0) || (driver_ver == NULL) ||
4599            (len > sizeof(fw_cmd.driver_string)))
4600                 return IXGBE_ERR_INVALID_ARGUMENT;
4601
4602         fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4603         fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len;
4604         fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4605         fw_cmd.port_num = (u8)hw->bus.func;
4606         fw_cmd.ver_maj = maj;
4607         fw_cmd.ver_min = min;
4608         fw_cmd.ver_build = build;
4609         fw_cmd.ver_sub = sub;
4610         fw_cmd.hdr.checksum = 0;
4611         memcpy(fw_cmd.driver_string, driver_ver, len);
4612         fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4613                                 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4614
4615         for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4616                 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4617                                                        sizeof(fw_cmd),
4618                                                        IXGBE_HI_COMMAND_TIMEOUT,
4619                                                        true);
4620                 if (ret_val != IXGBE_SUCCESS)
4621                         continue;
4622
4623                 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4624                     FW_CEM_RESP_STATUS_SUCCESS)
4625                         ret_val = IXGBE_SUCCESS;
4626                 else
4627                         ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4628
4629                 break;
4630         }
4631
4632         return ret_val;
4633 }