1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
43 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
44 * @hw: pointer to hardware structure
46 * Initialize the function pointers and assign the MAC type for X550.
47 * Does not touch the hardware.
49 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
51 struct ixgbe_mac_info *mac = &hw->mac;
52 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
55 DEBUGFUNC("ixgbe_init_ops_X550");
57 ret_val = ixgbe_init_ops_X540(hw);
58 mac->ops.dmac_config = ixgbe_dmac_config_X550;
59 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
60 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
61 mac->ops.setup_eee = ixgbe_setup_eee_X550;
62 mac->ops.set_source_address_pruning =
63 ixgbe_set_source_address_pruning_X550;
64 mac->ops.set_ethertype_anti_spoofing =
65 ixgbe_set_ethertype_anti_spoofing_X550;
67 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
68 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
69 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
70 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
71 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
72 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
73 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
74 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
75 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
77 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
78 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
79 mac->ops.mdd_event = ixgbe_mdd_event_X550;
80 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
81 mac->ops.disable_rx = ixgbe_disable_rx_x550;
86 * ixgbe_read_cs4227 - Read CS4227 register
87 * @hw: pointer to hardware structure
88 * @reg: register number to write
89 * @value: pointer to receive value read
93 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
95 return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
99 * ixgbe_write_cs4227 - Write CS4227 register
100 * @hw: pointer to hardware structure
101 * @reg: register number to write
102 * @value: value to write to register
104 * Returns status code
106 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
108 return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
112 * ixgbe_get_cs4227_status - Return CS4227 status
113 * @hw: pointer to hardware structure
115 * Returns error if CS4227 not successfully initialized
117 STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
123 for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) {
124 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB,
126 if (status != IXGBE_SUCCESS)
128 if (value == IXGBE_CS4227_GLOBAL_ID_VALUE)
130 msec_delay(IXGBE_CS4227_CHECK_DELAY);
132 if (value != IXGBE_CS4227_GLOBAL_ID_VALUE)
133 return IXGBE_ERR_PHY;
135 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
136 IXGBE_CS4227_SCRATCH_VALUE);
137 if (status != IXGBE_SUCCESS)
139 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
140 if (status != IXGBE_SUCCESS)
142 if (value != IXGBE_CS4227_SCRATCH_VALUE)
143 return IXGBE_ERR_PHY;
144 return IXGBE_SUCCESS;
148 * ixgbe_read_pe - Read register from port expander
149 * @hw: pointer to hardware structure
150 * @reg: register number to read
151 * @value: pointer to receive read value
153 * Returns status code
155 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
159 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
160 if (status != IXGBE_SUCCESS)
161 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
162 "port expander access failed with %d\n", status);
167 * ixgbe_write_pe - Write register to port expander
168 * @hw: pointer to hardware structure
169 * @reg: register number to write
170 * @value: value to write
172 * Returns status code
174 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
178 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
179 if (status != IXGBE_SUCCESS)
180 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
181 "port expander access failed with %d\n", status);
186 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
187 * @hw: pointer to hardware structure
191 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
196 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
197 if (status != IXGBE_SUCCESS)
199 reg |= IXGBE_PE_BIT1;
200 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
201 if (status != IXGBE_SUCCESS)
204 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
205 if (status != IXGBE_SUCCESS)
207 reg &= ~IXGBE_PE_BIT1;
208 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
209 if (status != IXGBE_SUCCESS)
212 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
213 if (status != IXGBE_SUCCESS)
215 reg &= ~IXGBE_PE_BIT1;
216 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
217 if (status != IXGBE_SUCCESS)
220 usec_delay(IXGBE_CS4227_RESET_HOLD);
222 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
223 if (status != IXGBE_SUCCESS)
225 reg |= IXGBE_PE_BIT1;
226 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
227 if (status != IXGBE_SUCCESS)
230 msec_delay(IXGBE_CS4227_RESET_DELAY);
232 return IXGBE_SUCCESS;
236 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
237 * @hw: pointer to hardware structure
239 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
241 u32 swfw_mask = hw->phy.phy_semaphore_mask;
245 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
246 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
247 if (status != IXGBE_SUCCESS) {
248 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
249 "semaphore failed with %d\n", status);
252 status = ixgbe_get_cs4227_status(hw);
253 if (status == IXGBE_SUCCESS) {
254 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
255 msec_delay(hw->eeprom.semaphore_delay);
258 ixgbe_reset_cs4227(hw);
259 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
260 msec_delay(hw->eeprom.semaphore_delay);
262 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
263 "Unable to initialize CS4227, err=%d\n", status);
267 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
268 * @hw: pointer to hardware structure
270 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
272 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
274 if (hw->bus.lan_id) {
275 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
276 esdp |= IXGBE_ESDP_SDP1_DIR;
278 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
279 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
280 IXGBE_WRITE_FLUSH(hw);
284 * ixgbe_identify_phy_x550em - Get PHY type based on device id
285 * @hw: pointer to hardware structure
289 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
291 switch (hw->device_id) {
292 case IXGBE_DEV_ID_X550EM_X_SFP:
293 /* set up for CS4227 usage */
294 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
295 ixgbe_setup_mux_ctl(hw);
296 ixgbe_check_cs4227(hw);
298 return ixgbe_identify_module_generic(hw);
300 case IXGBE_DEV_ID_X550EM_X_KX4:
301 hw->phy.type = ixgbe_phy_x550em_kx4;
303 case IXGBE_DEV_ID_X550EM_X_KR:
304 hw->phy.type = ixgbe_phy_x550em_kr;
306 case IXGBE_DEV_ID_X550EM_X_1G_T:
307 case IXGBE_DEV_ID_X550EM_X_10G_T:
308 return ixgbe_identify_phy_generic(hw);
312 return IXGBE_SUCCESS;
315 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
316 u32 device_type, u16 *phy_data)
318 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
319 return IXGBE_NOT_IMPLEMENTED;
322 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
323 u32 device_type, u16 phy_data)
325 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
326 return IXGBE_NOT_IMPLEMENTED;
330 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
331 * @hw: pointer to hardware structure
333 * Initialize the function pointers and for MAC type X550EM.
334 * Does not touch the hardware.
336 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
338 struct ixgbe_mac_info *mac = &hw->mac;
339 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
340 struct ixgbe_phy_info *phy = &hw->phy;
343 DEBUGFUNC("ixgbe_init_ops_X550EM");
345 /* Similar to X550 so start there. */
346 ret_val = ixgbe_init_ops_X550(hw);
348 /* Since this function eventually calls
349 * ixgbe_init_ops_540 by design, we are setting
350 * the pointers to NULL explicitly here to overwrite
351 * the values being set in the x540 function.
353 /* Thermal sensor not supported in x550EM */
354 mac->ops.get_thermal_sensor_data = NULL;
355 mac->ops.init_thermal_sensor_thresh = NULL;
356 mac->thermal_sensor_enabled = false;
358 /* FCOE not supported in x550EM */
359 mac->ops.get_san_mac_addr = NULL;
360 mac->ops.set_san_mac_addr = NULL;
361 mac->ops.get_wwn_prefix = NULL;
362 mac->ops.get_fcoe_boot_status = NULL;
364 /* IPsec not supported in x550EM */
365 mac->ops.disable_sec_rx_path = NULL;
366 mac->ops.enable_sec_rx_path = NULL;
368 /* AUTOC register is not present in x550EM. */
369 mac->ops.prot_autoc_read = NULL;
370 mac->ops.prot_autoc_write = NULL;
372 /* X550EM bus type is internal*/
373 hw->bus.type = ixgbe_bus_type_internal;
374 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
376 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
377 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
378 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
379 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
380 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
381 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
382 mac->ops.get_supported_physical_layer =
383 ixgbe_get_supported_physical_layer_X550em;
385 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
386 mac->ops.setup_fc = ixgbe_setup_fc_generic;
388 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
390 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
391 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
394 phy->ops.init = ixgbe_init_phy_ops_X550em;
395 phy->ops.identify = ixgbe_identify_phy_x550em;
396 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
397 phy->ops.set_phy_power = NULL;
401 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
402 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
403 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
404 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
405 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
406 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
407 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
408 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
414 * ixgbe_dmac_config_X550
415 * @hw: pointer to hardware structure
417 * Configure DMA coalescing. If enabling dmac, dmac is activated.
418 * When disabling dmac, dmac enable dmac bit is cleared.
420 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
422 u32 reg, high_pri_tc;
424 DEBUGFUNC("ixgbe_dmac_config_X550");
426 /* Disable DMA coalescing before configuring */
427 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
428 reg &= ~IXGBE_DMACR_DMAC_EN;
429 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
431 /* Disable DMA Coalescing if the watchdog timer is 0 */
432 if (!hw->mac.dmac_config.watchdog_timer)
435 ixgbe_dmac_config_tcs_X550(hw);
437 /* Configure DMA Coalescing Control Register */
438 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
440 /* Set the watchdog timer in units of 40.96 usec */
441 reg &= ~IXGBE_DMACR_DMACWT_MASK;
442 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
444 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
445 /* If fcoe is enabled, set high priority traffic class */
446 if (hw->mac.dmac_config.fcoe_en) {
447 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
448 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
449 IXGBE_DMACR_HIGH_PRI_TC_MASK);
451 reg |= IXGBE_DMACR_EN_MNG_IND;
453 /* Enable DMA coalescing after configuration */
454 reg |= IXGBE_DMACR_DMAC_EN;
455 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
458 return IXGBE_SUCCESS;
462 * ixgbe_dmac_config_tcs_X550
463 * @hw: pointer to hardware structure
465 * Configure DMA coalescing threshold per TC. The dmac enable bit must
466 * be cleared before configuring.
468 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
470 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
472 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
474 /* Configure DMA coalescing enabled */
475 switch (hw->mac.dmac_config.link_speed) {
476 case IXGBE_LINK_SPEED_100_FULL:
477 pb_headroom = IXGBE_DMACRXT_100M;
479 case IXGBE_LINK_SPEED_1GB_FULL:
480 pb_headroom = IXGBE_DMACRXT_1G;
483 pb_headroom = IXGBE_DMACRXT_10G;
487 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
488 IXGBE_MHADD_MFS_SHIFT) / 1024);
490 /* Set the per Rx packet buffer receive threshold */
491 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
492 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
493 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
495 if (tc < hw->mac.dmac_config.num_tcs) {
497 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
498 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
499 IXGBE_RXPBSIZE_SHIFT;
501 /* Calculate receive buffer threshold in kilobytes */
502 if (rx_pb_size > pb_headroom)
503 rx_pb_size = rx_pb_size - pb_headroom;
507 /* Minimum of MFS shall be set for DMCTH */
508 reg |= (rx_pb_size > maxframe_size_kb) ?
509 rx_pb_size : maxframe_size_kb;
511 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
513 return IXGBE_SUCCESS;
517 * ixgbe_dmac_update_tcs_X550
518 * @hw: pointer to hardware structure
520 * Disables dmac, updates per TC settings, and then enables dmac.
522 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
526 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
528 /* Disable DMA coalescing before configuring */
529 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
530 reg &= ~IXGBE_DMACR_DMAC_EN;
531 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
533 ixgbe_dmac_config_tcs_X550(hw);
535 /* Enable DMA coalescing after configuration */
536 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
537 reg |= IXGBE_DMACR_DMAC_EN;
538 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
540 return IXGBE_SUCCESS;
544 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
545 * @hw: pointer to hardware structure
547 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
548 * ixgbe_hw struct in order to set up EEPROM access.
550 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
552 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
556 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
558 if (eeprom->type == ixgbe_eeprom_uninitialized) {
559 eeprom->semaphore_delay = 10;
560 eeprom->type = ixgbe_flash;
562 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
563 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
564 IXGBE_EEC_SIZE_SHIFT);
565 eeprom->word_size = 1 << (eeprom_size +
566 IXGBE_EEPROM_WORD_SIZE_SHIFT);
568 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
569 eeprom->type, eeprom->word_size);
572 return IXGBE_SUCCESS;
576 * ixgbe_setup_eee_X550 - Enable/disable EEE support
577 * @hw: pointer to the HW structure
578 * @enable_eee: boolean flag to enable EEE
580 * Enable/disable EEE based on enable_eee flag.
581 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
585 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
592 DEBUGFUNC("ixgbe_setup_eee_X550");
594 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
595 /* Enable or disable EEE per flag */
597 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
599 if (hw->device_id == IXGBE_DEV_ID_X550T) {
600 /* Advertise EEE capability */
601 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
602 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
604 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
605 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
606 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
608 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
609 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
610 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
611 status = ixgbe_read_iosf_sb_reg_x550(hw,
612 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
613 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
614 if (status != IXGBE_SUCCESS)
617 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
618 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
620 status = ixgbe_write_iosf_sb_reg_x550(hw,
621 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
622 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
623 if (status != IXGBE_SUCCESS)
627 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
629 if (hw->device_id == IXGBE_DEV_ID_X550T) {
630 /* Disable advertised EEE capability */
631 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
632 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
634 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
635 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
636 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
638 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
639 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
640 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
641 status = ixgbe_read_iosf_sb_reg_x550(hw,
642 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
643 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
644 if (status != IXGBE_SUCCESS)
647 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
648 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
650 status = ixgbe_write_iosf_sb_reg_x550(hw,
651 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
652 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
653 if (status != IXGBE_SUCCESS)
657 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
659 return IXGBE_SUCCESS;
663 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
664 * @hw: pointer to hardware structure
665 * @enable: enable or disable source address pruning
666 * @pool: Rx pool to set source address pruning for
668 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
673 /* max rx pool is 63 */
677 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
678 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
681 pfflp |= (1ULL << pool);
683 pfflp &= ~(1ULL << pool);
685 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
686 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
690 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
691 * @hw: pointer to hardware structure
692 * @enable: enable or disable switch for Ethertype anti-spoofing
693 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
696 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
699 int vf_target_reg = vf >> 3;
700 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
703 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
705 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
707 pfvfspoof |= (1 << vf_target_shift);
709 pfvfspoof &= ~(1 << vf_target_shift);
711 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
715 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
717 * @hw: pointer to hardware structure
718 * @reg_addr: 32 bit PHY register to write
719 * @device_type: 3 bit device type
720 * @data: Data to write to the register
722 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
723 u32 device_type, u32 data)
725 u32 i, command, error;
727 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
728 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
730 /* Write IOSF control register */
731 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
733 /* Write IOSF data register */
734 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
736 * Check every 10 usec to see if the address cycle completed.
737 * The SB IOSF BUSY bit will clear when the operation is
740 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
743 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
744 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
748 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
749 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
750 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
751 ERROR_REPORT2(IXGBE_ERROR_POLLING,
752 "Failed to write, error %x\n", error);
753 return IXGBE_ERR_PHY;
756 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
757 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Write timed out\n");
758 return IXGBE_ERR_PHY;
761 return IXGBE_SUCCESS;
765 * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
767 * @hw: pointer to hardware structure
768 * @reg_addr: 32 bit PHY register to write
769 * @device_type: 3 bit device type
770 * @phy_data: Pointer to read data from the register
772 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
773 u32 device_type, u32 *data)
775 u32 i, command, error;
777 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
778 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
780 /* Write IOSF control register */
781 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
784 * Check every 10 usec to see if the address cycle completed.
785 * The SB IOSF BUSY bit will clear when the operation is
788 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
791 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
792 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
796 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
797 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
798 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
799 ERROR_REPORT2(IXGBE_ERROR_POLLING,
800 "Failed to read, error %x\n", error);
801 return IXGBE_ERR_PHY;
804 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
805 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Read timed out\n");
806 return IXGBE_ERR_PHY;
809 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
811 return IXGBE_SUCCESS;
815 * ixgbe_disable_mdd_X550
816 * @hw: pointer to hardware structure
818 * Disable malicious driver detection
820 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
824 DEBUGFUNC("ixgbe_disable_mdd_X550");
826 /* Disable MDD for TX DMA and interrupt */
827 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
828 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
829 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
831 /* Disable MDD for RX and interrupt */
832 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
833 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
834 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
838 * ixgbe_enable_mdd_X550
839 * @hw: pointer to hardware structure
841 * Enable malicious driver detection
843 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
847 DEBUGFUNC("ixgbe_enable_mdd_X550");
849 /* Enable MDD for TX DMA and interrupt */
850 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
851 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
852 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
854 /* Enable MDD for RX and interrupt */
855 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
856 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
857 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
861 * ixgbe_restore_mdd_vf_X550
862 * @hw: pointer to hardware structure
865 * Restore VF that was disabled during malicious driver detection event
867 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
869 u32 idx, reg, num_qs, start_q, bitmask;
871 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
873 /* Map VF to queues */
874 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
875 switch (reg & IXGBE_MRQC_MRQE_MASK) {
876 case IXGBE_MRQC_VMDQRT8TCEN:
877 num_qs = 8; /* 16 VFs / pools */
878 bitmask = 0x000000FF;
880 case IXGBE_MRQC_VMDQRSS32EN:
881 case IXGBE_MRQC_VMDQRT4TCEN:
882 num_qs = 4; /* 32 VFs / pools */
883 bitmask = 0x0000000F;
885 default: /* 64 VFs / pools */
887 bitmask = 0x00000003;
890 start_q = vf * num_qs;
892 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
895 reg |= (bitmask << (start_q % 32));
896 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
897 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
901 * ixgbe_mdd_event_X550
902 * @hw: pointer to hardware structure
903 * @vf_bitmap: vf bitmap of malicious vfs
905 * Handle malicious driver detection event.
907 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
910 u32 i, j, reg, q, shift, vf, idx;
912 DEBUGFUNC("ixgbe_mdd_event_X550");
914 /* figure out pool size for mapping to vf's */
915 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
916 switch (reg & IXGBE_MRQC_MRQE_MASK) {
917 case IXGBE_MRQC_VMDQRT8TCEN:
918 shift = 3; /* 16 VFs / pools */
920 case IXGBE_MRQC_VMDQRSS32EN:
921 case IXGBE_MRQC_VMDQRT4TCEN:
922 shift = 2; /* 32 VFs / pools */
925 shift = 1; /* 64 VFs / pools */
929 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
930 for (i = 0; i < 4; i++) {
931 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
932 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
937 /* Get malicious queue */
938 for (j = 0; j < 32 && wqbr; j++) {
940 if (!(wqbr & (1 << j)))
943 /* Get queue from bitmask */
946 /* Map queue to vf */
949 /* Set vf bit in vf_bitmap */
951 vf_bitmap[idx] |= (1 << (vf % 32));
958 * ixgbe_get_media_type_X550em - Get media type
959 * @hw: pointer to hardware structure
961 * Returns the media type (fiber, copper, backplane)
963 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
965 enum ixgbe_media_type media_type;
967 DEBUGFUNC("ixgbe_get_media_type_X550em");
969 /* Detect if there is a copper PHY attached. */
970 switch (hw->device_id) {
971 case IXGBE_DEV_ID_X550EM_X_KR:
972 case IXGBE_DEV_ID_X550EM_X_KX4:
973 media_type = ixgbe_media_type_backplane;
975 case IXGBE_DEV_ID_X550EM_X_SFP:
976 media_type = ixgbe_media_type_fiber;
978 case IXGBE_DEV_ID_X550EM_X_1G_T:
979 case IXGBE_DEV_ID_X550EM_X_10G_T:
980 media_type = ixgbe_media_type_copper;
983 media_type = ixgbe_media_type_unknown;
990 * ixgbe_setup_sfp_modules_X550em - Setup SFP module
991 * @hw: pointer to hardware structure
993 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
996 u16 reg_slice, edc_mode;
999 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1001 switch (hw->phy.sfp_type) {
1002 case ixgbe_sfp_type_unknown:
1003 return IXGBE_SUCCESS;
1004 case ixgbe_sfp_type_not_present:
1005 return IXGBE_ERR_SFP_NOT_PRESENT;
1006 case ixgbe_sfp_type_da_cu_core0:
1007 case ixgbe_sfp_type_da_cu_core1:
1008 setup_linear = true;
1010 case ixgbe_sfp_type_srlr_core0:
1011 case ixgbe_sfp_type_srlr_core1:
1012 case ixgbe_sfp_type_da_act_lmt_core0:
1013 case ixgbe_sfp_type_da_act_lmt_core1:
1014 case ixgbe_sfp_type_1g_sx_core0:
1015 case ixgbe_sfp_type_1g_sx_core1:
1016 case ixgbe_sfp_type_1g_lx_core0:
1017 case ixgbe_sfp_type_1g_lx_core1:
1018 setup_linear = false;
1021 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1024 ixgbe_init_mac_link_ops_X550em(hw);
1025 hw->phy.ops.reset = NULL;
1027 /* The CS4227 slice address is the base address + the port-pair reg
1028 * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0.
1030 reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->bus.lan_id << 12);
1033 edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1035 edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1037 /* Configure CS4227 for connection type. */
1038 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1041 if (ret_val != IXGBE_SUCCESS)
1042 ret_val = ixgbe_write_i2c_combined(hw, 0x80, reg_slice,
1049 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1050 * @hw: pointer to hardware structure
1052 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1054 struct ixgbe_mac_info *mac = &hw->mac;
1056 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1058 switch (hw->mac.ops.get_media_type(hw)) {
1059 case ixgbe_media_type_fiber:
1060 /* CS4227 does not support autoneg, so disable the laser control
1061 * functions for SFP+ fiber
1063 mac->ops.disable_tx_laser = NULL;
1064 mac->ops.enable_tx_laser = NULL;
1065 mac->ops.flap_tx_laser = NULL;
1066 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1067 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1068 mac->ops.set_rate_select_speed =
1069 ixgbe_set_soft_rate_select_speed;
1071 case ixgbe_media_type_copper:
1072 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1073 mac->ops.check_link = ixgbe_check_link_t_X550em;
1081 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1082 * @hw: pointer to hardware structure
1083 * @speed: pointer to link speed
1084 * @autoneg: true when autoneg or autotry is enabled
1086 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1087 ixgbe_link_speed *speed,
1090 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1093 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1095 /* CS4227 SFP must not enable auto-negotiation */
1098 /* Check if 1G SFP module. */
1099 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1100 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1101 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1102 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1103 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1104 return IXGBE_SUCCESS;
1107 /* Link capabilities are based on SFP */
1108 if (hw->phy.multispeed_fiber)
1109 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1110 IXGBE_LINK_SPEED_1GB_FULL;
1112 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1114 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1115 IXGBE_LINK_SPEED_1GB_FULL;
1119 return IXGBE_SUCCESS;
1123 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1124 * @hw: pointer to hardware structure
1125 * @lsc: pointer to boolean flag which indicates whether external Base T
1126 * PHY interrupt is lsc
1128 * Determime if external Base T PHY interrupt cause is high temperature
1129 * failure alarm or link status change.
1131 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1132 * failure alarm, else return PHY access status.
1134 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1141 /* Vendor alarm triggered */
1142 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1143 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1146 if (status != IXGBE_SUCCESS ||
1147 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1150 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1151 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1152 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1155 if (status != IXGBE_SUCCESS ||
1156 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1157 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1160 /* High temperature failure alarm triggered */
1161 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1162 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1165 if (status != IXGBE_SUCCESS)
1168 /* If high temperature failure, then return over temp error and exit */
1169 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL)
1170 return IXGBE_ERR_OVERTEMP;
1172 /* Vendor alarm 2 triggered */
1173 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1174 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1176 if (status != IXGBE_SUCCESS ||
1177 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1180 /* link connect/disconnect event occurred */
1181 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1182 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1184 if (status != IXGBE_SUCCESS)
1188 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1191 return IXGBE_SUCCESS;
1195 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1196 * @hw: pointer to hardware structure
1198 * Enable link status change and temperature failure alarm for the external
1201 * Returns PHY access status
1203 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1209 /* Clear interrupt flags */
1210 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1212 /* Enable link status change alarm */
1213 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1214 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1216 if (status != IXGBE_SUCCESS)
1219 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1221 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1222 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1224 if (status != IXGBE_SUCCESS)
1227 /* Enables high temperature failure alarm */
1228 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1229 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1232 if (status != IXGBE_SUCCESS)
1235 reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;
1237 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1238 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1241 if (status != IXGBE_SUCCESS)
1244 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1245 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1246 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1249 if (status != IXGBE_SUCCESS)
1252 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1253 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1255 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1256 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1259 if (status != IXGBE_SUCCESS)
1262 /* Enable chip-wide vendor alarm */
1263 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1264 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1267 if (status != IXGBE_SUCCESS)
1270 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1272 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1273 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1280 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1281 * @hw: pointer to hardware structure
1283 * Initialize any function pointers that were not able to be
1284 * set during init_shared_code because the PHY/SFP type was
1285 * not known. Perform the SFP init if necessary.
1287 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1289 struct ixgbe_phy_info *phy = &hw->phy;
1292 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1294 hw->mac.ops.set_lan_id(hw);
1296 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1297 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1298 ixgbe_setup_mux_ctl(hw);
1301 /* Identify the PHY or SFP module */
1302 ret_val = phy->ops.identify(hw);
1303 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1306 /* Setup function pointers based on detected hardware */
1307 ixgbe_init_mac_link_ops_X550em(hw);
1308 if (phy->sfp_type != ixgbe_sfp_type_unknown)
1309 phy->ops.reset = NULL;
1311 /* Set functions pointers based on phy type */
1312 switch (hw->phy.type) {
1313 case ixgbe_phy_x550em_kx4:
1314 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
1315 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1316 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1318 case ixgbe_phy_x550em_kr:
1319 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1320 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1321 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1323 case ixgbe_phy_x550em_ext_t:
1324 phy->ops.setup_internal_link =
1325 ixgbe_setup_internal_phy_t_x550em;
1326 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1327 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1328 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1337 * ixgbe_reset_hw_X550em - Perform hardware reset
1338 * @hw: pointer to hardware structure
1340 * Resets the hardware by resetting the transmit and receive units, masks
1341 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1344 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1346 struct ixgbe_hic_hdr fw_cmd;
1347 ixgbe_link_speed link_speed;
1351 bool link_up = false;
1353 DEBUGFUNC("ixgbe_reset_hw_X550em");
1355 fw_cmd.cmd = FW_PHY_MGMT_REQ_CMD;
1357 fw_cmd.cmd_or_resp.cmd_resv = 0;
1358 fw_cmd.checksum = FW_DEFAULT_CHECKSUM;
1359 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
1361 IXGBE_HI_PHY_MGMT_REQ_TIMEOUT,
1364 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
1365 "PHY mgmt command failed with %d\n", status);
1366 else if (fw_cmd.cmd_or_resp.ret_status != FW_CEM_RESP_STATUS_SUCCESS)
1367 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
1368 "PHY mgmt command returned %d\n",
1369 fw_cmd.cmd_or_resp.ret_status);
1371 /* Call adapter stop to disable Tx/Rx and clear interrupts */
1372 status = hw->mac.ops.stop_adapter(hw);
1373 if (status != IXGBE_SUCCESS)
1376 /* flush pending Tx transactions */
1377 ixgbe_clear_tx_pending(hw);
1379 /* PHY ops must be identified and initialized prior to reset */
1381 /* Identify PHY and related function pointers */
1382 status = hw->phy.ops.init(hw);
1384 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1387 /* start the external PHY */
1388 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1389 status = ixgbe_init_ext_t_x550em(hw);
1394 /* Setup SFP module if there is one present. */
1395 if (hw->phy.sfp_setup_needed) {
1396 status = hw->mac.ops.setup_sfp(hw);
1397 hw->phy.sfp_setup_needed = false;
1400 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1404 if (!hw->phy.reset_disable && hw->phy.ops.reset)
1405 hw->phy.ops.reset(hw);
1408 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
1409 * If link reset is used when link is up, it might reset the PHY when
1410 * mng is using it. If link is down or the flag to force full link
1411 * reset is set, then perform link reset.
1413 ctrl = IXGBE_CTRL_LNK_RST;
1414 if (!hw->force_full_reset) {
1415 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1417 ctrl = IXGBE_CTRL_RST;
1420 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1421 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1422 IXGBE_WRITE_FLUSH(hw);
1424 /* Poll for reset bit to self-clear meaning reset is complete */
1425 for (i = 0; i < 10; i++) {
1427 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1428 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1432 if (ctrl & IXGBE_CTRL_RST_MASK) {
1433 status = IXGBE_ERR_RESET_FAILED;
1434 DEBUGOUT("Reset polling failed to complete.\n");
1439 /* Double resets are required for recovery from certain error
1440 * conditions. Between resets, it is necessary to stall to
1441 * allow time for any pending HW events to complete.
1443 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1444 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1448 /* Store the permanent mac address */
1449 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1451 /* Store MAC address from RAR0, clear receive address registers, and
1452 * clear the multicast table. Also reset num_rar_entries to 128,
1453 * since we modify this value when programming the SAN MAC address.
1455 hw->mac.num_rar_entries = 128;
1456 hw->mac.ops.init_rx_addrs(hw);
1459 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1460 ixgbe_setup_mux_ctl(hw);
1466 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1467 * @hw: pointer to hardware structure
1469 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1474 status = hw->phy.ops.read_reg(hw,
1475 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1476 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1479 if (status != IXGBE_SUCCESS)
1482 /* If PHY FW reset completed bit is set then this is the first
1483 * SW instance after a power on so the PHY FW must be un-stalled.
1485 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1486 status = hw->phy.ops.read_reg(hw,
1487 IXGBE_MDIO_GLOBAL_RES_PR_10,
1488 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1491 if (status != IXGBE_SUCCESS)
1494 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1496 status = hw->phy.ops.write_reg(hw,
1497 IXGBE_MDIO_GLOBAL_RES_PR_10,
1498 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1501 if (status != IXGBE_SUCCESS)
1509 * ixgbe_setup_kr_x550em - Configure the KR PHY.
1510 * @hw: pointer to hardware structure
1512 * Configures the integrated KR PHY.
1514 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1519 status = ixgbe_read_iosf_sb_reg_x550(hw,
1520 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1521 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1525 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1526 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ |
1527 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC);
1528 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1529 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1531 /* Advertise 10G support. */
1532 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1533 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1535 /* Advertise 1G support. */
1536 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1537 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1539 /* Restart auto-negotiation. */
1540 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1541 status = ixgbe_write_iosf_sb_reg_x550(hw,
1542 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1543 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1549 * ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1550 * @hw: pointer to hardware structure
1552 * Configures the integrated KX4 PHY.
1554 s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1559 status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1560 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, ®_val);
1564 reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1565 IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1567 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1569 /* Advertise 10G support. */
1570 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1571 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1573 /* Advertise 1G support. */
1574 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1575 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1577 /* Restart auto-negotiation. */
1578 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1579 status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1580 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, reg_val);
1586 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1587 * @hw: pointer to hardware structure
1588 * @speed: the link speed to force
1590 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
1591 * internal and external PHY at a specific speed, without autonegotiation.
1593 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1598 /* Disable AN and force speed to 10G Serial. */
1599 status = ixgbe_read_iosf_sb_reg_x550(hw,
1600 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1601 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1602 if (status != IXGBE_SUCCESS)
1605 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1606 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1608 /* Select forced link speed for internal PHY. */
1610 case IXGBE_LINK_SPEED_10GB_FULL:
1611 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1613 case IXGBE_LINK_SPEED_1GB_FULL:
1614 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1617 /* Other link speeds are not supported by internal KR PHY. */
1618 return IXGBE_ERR_LINK_SETUP;
1621 status = ixgbe_write_iosf_sb_reg_x550(hw,
1622 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1623 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1624 if (status != IXGBE_SUCCESS)
1627 /* Disable training protocol FSM. */
1628 status = ixgbe_read_iosf_sb_reg_x550(hw,
1629 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1630 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1631 if (status != IXGBE_SUCCESS)
1633 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1634 status = ixgbe_write_iosf_sb_reg_x550(hw,
1635 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1636 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1637 if (status != IXGBE_SUCCESS)
1640 /* Disable Flex from training TXFFE. */
1641 status = ixgbe_read_iosf_sb_reg_x550(hw,
1642 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1643 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1644 if (status != IXGBE_SUCCESS)
1646 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1647 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1648 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1649 status = ixgbe_write_iosf_sb_reg_x550(hw,
1650 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1651 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1652 if (status != IXGBE_SUCCESS)
1654 status = ixgbe_read_iosf_sb_reg_x550(hw,
1655 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1656 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1657 if (status != IXGBE_SUCCESS)
1659 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1660 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1661 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1662 status = ixgbe_write_iosf_sb_reg_x550(hw,
1663 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1664 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1665 if (status != IXGBE_SUCCESS)
1668 /* Enable override for coefficients. */
1669 status = ixgbe_read_iosf_sb_reg_x550(hw,
1670 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1671 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1672 if (status != IXGBE_SUCCESS)
1674 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1675 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1676 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1677 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1678 status = ixgbe_write_iosf_sb_reg_x550(hw,
1679 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1680 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1681 if (status != IXGBE_SUCCESS)
1684 /* Toggle port SW reset by AN reset. */
1685 status = ixgbe_read_iosf_sb_reg_x550(hw,
1686 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1687 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1688 if (status != IXGBE_SUCCESS)
1690 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1691 status = ixgbe_write_iosf_sb_reg_x550(hw,
1692 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1693 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1699 * ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
1700 * @hw: pointer to hardware structure
1702 * Configures the integrated KR PHY for SFP support.
1704 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1705 ixgbe_link_speed speed,
1706 bool autoneg_wait_to_complete)
1708 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1710 return ixgbe_setup_ixfi_x550em(hw, &speed);
1714 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1715 * @hw: point to hardware structure
1717 * Configures the link between the integrated KR PHY and the external X557 PHY
1718 * The driver will call this function when it gets a link status change
1719 * interrupt from the X557 PHY. This function configures the link speed
1720 * between the PHYs to match the link speed of the BASE-T link.
1722 * A return of a non-zero value indicates an error, and the base driver should
1723 * not report link up.
1725 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
1728 u16 autoneg_status, speed;
1729 ixgbe_link_speed force_speed;
1731 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1732 return IXGBE_ERR_CONFIG;
1734 /* read this twice back to back to indicate current status */
1735 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1736 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1738 if (status != IXGBE_SUCCESS)
1741 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1742 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1744 if (status != IXGBE_SUCCESS)
1747 /* If link is not up, then there is no setup necessary so return */
1748 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1749 return IXGBE_SUCCESS;
1751 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1752 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1755 /* clear everything but the speed and duplex bits */
1756 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1759 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1760 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1762 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1763 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1766 /* Internal PHY does not support anything else */
1767 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1770 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1774 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1775 * @hw: pointer to hardware structure
1777 * Configures the integrated KR PHY to use internal loopback mode.
1779 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1784 /* Disable AN and force speed to 10G Serial. */
1785 status = ixgbe_read_iosf_sb_reg_x550(hw,
1786 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1787 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1788 if (status != IXGBE_SUCCESS)
1790 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1791 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1792 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1793 status = ixgbe_write_iosf_sb_reg_x550(hw,
1794 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1795 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1796 if (status != IXGBE_SUCCESS)
1799 /* Set near-end loopback clocks. */
1800 status = ixgbe_read_iosf_sb_reg_x550(hw,
1801 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1802 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1803 if (status != IXGBE_SUCCESS)
1805 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1806 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1807 status = ixgbe_write_iosf_sb_reg_x550(hw,
1808 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1809 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1810 if (status != IXGBE_SUCCESS)
1813 /* Set loopback enable. */
1814 status = ixgbe_read_iosf_sb_reg_x550(hw,
1815 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1816 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1817 if (status != IXGBE_SUCCESS)
1819 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1820 status = ixgbe_write_iosf_sb_reg_x550(hw,
1821 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1822 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1823 if (status != IXGBE_SUCCESS)
1826 /* Training bypass. */
1827 status = ixgbe_read_iosf_sb_reg_x550(hw,
1828 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1829 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1830 if (status != IXGBE_SUCCESS)
1832 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
1833 status = ixgbe_write_iosf_sb_reg_x550(hw,
1834 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1835 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1841 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1842 * assuming that the semaphore is already obtained.
1843 * @hw: pointer to hardware structure
1844 * @offset: offset of word in the EEPROM to read
1845 * @data: word read from the EEPROM
1847 * Reads a 16 bit word from the EEPROM using the hostif.
1849 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1853 struct ixgbe_hic_read_shadow_ram buffer;
1855 DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
1856 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1857 buffer.hdr.req.buf_lenh = 0;
1858 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1859 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1861 /* convert offset from words to bytes */
1862 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1864 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1866 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1868 IXGBE_HI_COMMAND_TIMEOUT, false);
1873 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1874 FW_NVM_DATA_OFFSET);
1880 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1881 * @hw: pointer to hardware structure
1882 * @offset: offset of word in the EEPROM to read
1883 * @data: word read from the EEPROM
1885 * Reads a 16 bit word from the EEPROM using the hostif.
1887 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1890 s32 status = IXGBE_SUCCESS;
1892 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
1894 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1896 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
1897 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1899 status = IXGBE_ERR_SWFW_SYNC;
1906 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
1907 * @hw: pointer to hardware structure
1908 * @offset: offset of word in the EEPROM to read
1909 * @words: number of words
1910 * @data: word(s) read from the EEPROM
1912 * Reads a 16 bit word(s) from the EEPROM using the hostif.
1914 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1915 u16 offset, u16 words, u16 *data)
1917 struct ixgbe_hic_read_shadow_ram buffer;
1918 u32 current_word = 0;
1923 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
1925 /* Take semaphore for the entire operation. */
1926 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1928 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
1932 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
1933 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
1935 words_to_read = words;
1937 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1938 buffer.hdr.req.buf_lenh = 0;
1939 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1940 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1942 /* convert offset from words to bytes */
1943 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
1944 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
1946 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1948 IXGBE_HI_COMMAND_TIMEOUT,
1952 DEBUGOUT("Host interface command failed\n");
1956 for (i = 0; i < words_to_read; i++) {
1957 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
1959 u32 value = IXGBE_READ_REG(hw, reg);
1961 data[current_word] = (u16)(value & 0xffff);
1964 if (i < words_to_read) {
1966 data[current_word] = (u16)(value & 0xffff);
1970 words -= words_to_read;
1974 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1979 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1980 * @hw: pointer to hardware structure
1981 * @offset: offset of word in the EEPROM to write
1982 * @data: word write to the EEPROM
1984 * Write a 16 bit word to the EEPROM using the hostif.
1986 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1990 struct ixgbe_hic_write_shadow_ram buffer;
1992 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
1994 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
1995 buffer.hdr.req.buf_lenh = 0;
1996 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
1997 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2000 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2002 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2004 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2006 IXGBE_HI_COMMAND_TIMEOUT, false);
2012 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2013 * @hw: pointer to hardware structure
2014 * @offset: offset of word in the EEPROM to write
2015 * @data: word write to the EEPROM
2017 * Write a 16 bit word to the EEPROM using the hostif.
2019 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2022 s32 status = IXGBE_SUCCESS;
2024 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2026 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2028 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2029 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2031 DEBUGOUT("write ee hostif failed to get semaphore");
2032 status = IXGBE_ERR_SWFW_SYNC;
2039 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2040 * @hw: pointer to hardware structure
2041 * @offset: offset of word in the EEPROM to write
2042 * @words: number of words
2043 * @data: word(s) write to the EEPROM
2045 * Write a 16 bit word(s) to the EEPROM using the hostif.
2047 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2048 u16 offset, u16 words, u16 *data)
2050 s32 status = IXGBE_SUCCESS;
2053 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2055 /* Take semaphore for the entire operation. */
2056 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2057 if (status != IXGBE_SUCCESS) {
2058 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2062 for (i = 0; i < words; i++) {
2063 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2066 if (status != IXGBE_SUCCESS) {
2067 DEBUGOUT("Eeprom buffered write failed\n");
2072 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2079 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2080 * @hw: pointer to hardware structure
2081 * @ptr: pointer offset in eeprom
2082 * @size: size of section pointed by ptr, if 0 first word will be used as size
2083 * @csum: address of checksum to update
2085 * Returns error status for any failure
2087 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2088 u16 size, u16 *csum, u16 *buffer,
2093 u16 length, bufsz, i, start;
2096 bufsz = sizeof(buf) / sizeof(buf[0]);
2098 /* Read a chunk at the pointer location */
2100 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2102 DEBUGOUT("Failed to read EEPROM image\n");
2107 if (buffer_size < ptr)
2108 return IXGBE_ERR_PARAM;
2109 local_buffer = &buffer[ptr];
2117 length = local_buffer[0];
2119 /* Skip pointer section if length is invalid. */
2120 if (length == 0xFFFF || length == 0 ||
2121 (ptr + length) >= hw->eeprom.word_size)
2122 return IXGBE_SUCCESS;
2125 if (buffer && ((u32)start + (u32)length > buffer_size))
2126 return IXGBE_ERR_PARAM;
2128 for (i = start; length; i++, length--) {
2129 if (i == bufsz && !buffer) {
2135 /* Read a chunk at the pointer location */
2136 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2139 DEBUGOUT("Failed to read EEPROM image\n");
2143 *csum += local_buffer[i];
2145 return IXGBE_SUCCESS;
2149 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2150 * @hw: pointer to hardware structure
2151 * @buffer: pointer to buffer containing calculated checksum
2152 * @buffer_size: size of buffer
2154 * Returns a negative error code on error, or the 16-bit checksum
2156 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2158 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2162 u16 pointer, i, size;
2164 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2166 hw->eeprom.ops.init_params(hw);
2169 /* Read pointer area */
2170 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2171 IXGBE_EEPROM_LAST_WORD + 1,
2174 DEBUGOUT("Failed to read EEPROM image\n");
2177 local_buffer = eeprom_ptrs;
2179 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2180 return IXGBE_ERR_PARAM;
2181 local_buffer = buffer;
2185 * For X550 hardware include 0x0-0x41 in the checksum, skip the
2186 * checksum word itself
2188 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2189 if (i != IXGBE_EEPROM_CHECKSUM)
2190 checksum += local_buffer[i];
2193 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
2194 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2196 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2197 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2200 pointer = local_buffer[i];
2202 /* Skip pointer section if the pointer is invalid. */
2203 if (pointer == 0xFFFF || pointer == 0 ||
2204 pointer >= hw->eeprom.word_size)
2208 case IXGBE_PCIE_GENERAL_PTR:
2209 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2211 case IXGBE_PCIE_CONFIG0_PTR:
2212 case IXGBE_PCIE_CONFIG1_PTR:
2213 size = IXGBE_PCIE_CONFIG_SIZE;
2220 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2221 buffer, buffer_size);
2226 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2228 return (s32)checksum;
2232 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2233 * @hw: pointer to hardware structure
2235 * Returns a negative error code on error, or the 16-bit checksum
2237 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2239 return ixgbe_calc_checksum_X550(hw, NULL, 0);
2243 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2244 * @hw: pointer to hardware structure
2245 * @checksum_val: calculated checksum
2247 * Performs checksum calculation and validates the EEPROM checksum. If the
2248 * caller does not need checksum_val, the value can be NULL.
2250 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2254 u16 read_checksum = 0;
2256 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2258 /* Read the first word from the EEPROM. If this times out or fails, do
2259 * not continue or we could be in for a very long wait while every
2262 status = hw->eeprom.ops.read(hw, 0, &checksum);
2264 DEBUGOUT("EEPROM read failed\n");
2268 status = hw->eeprom.ops.calc_checksum(hw);
2272 checksum = (u16)(status & 0xffff);
2274 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2279 /* Verify read checksum from EEPROM is the same as
2280 * calculated checksum
2282 if (read_checksum != checksum) {
2283 status = IXGBE_ERR_EEPROM_CHECKSUM;
2284 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2285 "Invalid EEPROM checksum");
2288 /* If the user cares, return the calculated checksum */
2290 *checksum_val = checksum;
2296 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2297 * @hw: pointer to hardware structure
2299 * After writing EEPROM to shadow RAM using EEWR register, software calculates
2300 * checksum and updates the EEPROM and instructs the hardware to update
2303 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2308 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2310 /* Read the first word from the EEPROM. If this times out or fails, do
2311 * not continue or we could be in for a very long wait while every
2314 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2316 DEBUGOUT("EEPROM read failed\n");
2320 status = ixgbe_calc_eeprom_checksum_X550(hw);
2324 checksum = (u16)(status & 0xffff);
2326 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2331 status = ixgbe_update_flash_X550(hw);
2337 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2338 * @hw: pointer to hardware structure
2340 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2342 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2344 s32 status = IXGBE_SUCCESS;
2345 union ixgbe_hic_hdr2 buffer;
2347 DEBUGFUNC("ixgbe_update_flash_X550");
2349 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2350 buffer.req.buf_lenh = 0;
2351 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2352 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2354 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2356 IXGBE_HI_COMMAND_TIMEOUT, false);
2362 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2363 * @hw: pointer to hardware structure
2365 * Determines physical layer capabilities of the current configuration.
2367 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2369 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2370 u16 ext_ability = 0;
2372 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2374 hw->phy.ops.identify(hw);
2376 switch (hw->phy.type) {
2377 case ixgbe_phy_x550em_kr:
2378 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2379 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2381 case ixgbe_phy_x550em_kx4:
2382 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2383 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2385 case ixgbe_phy_x550em_ext_t:
2386 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2387 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2389 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2390 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2391 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2392 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2398 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2399 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2401 return physical_layer;
2405 * ixgbe_get_bus_info_x550em - Set PCI bus info
2406 * @hw: pointer to hardware structure
2408 * Sets bus link width and speed to unknown because X550em is
2411 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2414 DEBUGFUNC("ixgbe_get_bus_info_x550em");
2416 hw->bus.width = ixgbe_bus_width_unknown;
2417 hw->bus.speed = ixgbe_bus_speed_unknown;
2419 hw->mac.ops.set_lan_id(hw);
2421 return IXGBE_SUCCESS;
2425 * ixgbe_disable_rx_x550 - Disable RX unit
2427 * Enables the Rx DMA unit for x550
2429 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2431 u32 rxctrl, pfdtxgswc;
2433 struct ixgbe_hic_disable_rxen fw_cmd;
2435 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2437 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2438 if (rxctrl & IXGBE_RXCTRL_RXEN) {
2439 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2440 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2441 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2442 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2443 hw->mac.set_lben = true;
2445 hw->mac.set_lben = false;
2448 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2449 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2450 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2451 fw_cmd.port_number = (u8)hw->bus.lan_id;
2453 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2454 sizeof(struct ixgbe_hic_disable_rxen),
2455 IXGBE_HI_COMMAND_TIMEOUT, true);
2457 /* If we fail - disable RX using register write */
2459 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2460 if (rxctrl & IXGBE_RXCTRL_RXEN) {
2461 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2462 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2469 * ixgbe_enter_lplu_x550em - Transition to low power states
2470 * @hw: pointer to hardware structure
2472 * Configures Low Power Link Up on transition to low power states
2473 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2474 * X557 PHY immediately prior to entering LPLU.
2476 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2478 u16 autoneg_status, an_10g_cntl_reg, autoneg_reg, speed;
2480 ixgbe_link_speed lcd_speed;
2482 /* If blocked by MNG FW, then don't restart AN */
2483 if (ixgbe_check_reset_blocked(hw))
2484 return IXGBE_SUCCESS;
2486 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2487 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2490 if (status != IXGBE_SUCCESS)
2493 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2495 if (status != IXGBE_SUCCESS)
2498 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2499 * disabled, then force link down by entering low power mode.
2501 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS) ||
2502 !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2503 !(hw->wol_enabled || ixgbe_mng_present(hw)))
2504 return ixgbe_set_copper_phy_power(hw, FALSE);
2507 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2509 if (status != IXGBE_SUCCESS)
2512 /* If no valid LCD link speed, then force link down and exit. */
2513 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2514 return ixgbe_set_copper_phy_power(hw, FALSE);
2516 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2517 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2520 if (status != IXGBE_SUCCESS)
2523 /* clear everything but the speed bits */
2524 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2526 /* If current speed is already LCD, then exit. */
2527 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2528 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2529 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2530 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2533 /* Clear AN completed indication */
2534 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2535 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2538 if (status != IXGBE_SUCCESS)
2541 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2542 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2545 if (status != IXGBE_SUCCESS)
2548 status = hw->phy.ops.read_reg(hw,
2549 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2550 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2553 if (status != IXGBE_SUCCESS)
2556 /* Set AN advertizement to only include LCD */
2557 if (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL) {
2558 an_10g_cntl_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
2559 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
2562 if (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL) {
2563 an_10g_cntl_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
2564 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
2567 status = hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2568 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2571 if (status != IXGBE_SUCCESS)
2574 status = hw->phy.ops.write_reg(hw,
2575 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2576 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2579 if (status != IXGBE_SUCCESS)
2582 /* Restart PHY auto-negotiation. */
2583 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
2584 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
2586 if (status != IXGBE_SUCCESS)
2589 autoneg_reg |= IXGBE_MII_RESTART;
2591 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
2592 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
2594 if (status != IXGBE_SUCCESS)
2597 status = ixgbe_setup_ixfi_x550em(hw, &lcd_speed);
2603 * ixgbe_get_lcd_x550em - Determine lowest common denominator
2604 * @hw: pointer to hardware structure
2605 * @lcd_speed: pointer to lowest common link speed
2607 * Determine lowest common link speed with link partner.
2609 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2613 u16 word = hw->eeprom.ctrl_word_3;
2615 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2617 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2618 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2621 if (status != IXGBE_SUCCESS)
2624 /* If link partner advertised 1G, return 1G */
2625 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2626 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2630 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2631 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2632 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2635 /* Link partner not capable of lower speeds, return 10G */
2636 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2641 * ixgbe_setup_fc_X550em - Set up flow control
2642 * @hw: pointer to hardware structure
2644 * Called at init time to set up flow control.
2646 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
2648 s32 ret_val = IXGBE_SUCCESS;
2649 u32 pause, asm_dir, reg_val;
2651 DEBUGFUNC("ixgbe_setup_fc_X550em");
2653 /* Validate the requested mode */
2654 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2655 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2656 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2657 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2661 /* 10gig parts do not have a word in the EEPROM to determine the
2662 * default flow control setting, so we explicitly set it to full.
2664 if (hw->fc.requested_mode == ixgbe_fc_default)
2665 hw->fc.requested_mode = ixgbe_fc_full;
2667 /* Determine PAUSE and ASM_DIR bits. */
2668 switch (hw->fc.requested_mode) {
2673 case ixgbe_fc_tx_pause:
2677 case ixgbe_fc_rx_pause:
2678 /* Rx Flow control is enabled and Tx Flow control is
2679 * disabled by software override. Since there really
2680 * isn't a way to advertise that we are capable of RX
2681 * Pause ONLY, we will advertise that we support both
2682 * symmetric and asymmetric Rx PAUSE, as such we fall
2683 * through to the fc_full statement. Later, we will
2684 * disable the adapter's ability to send PAUSE frames.
2691 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2692 "Flow control param set incorrectly\n");
2693 ret_val = IXGBE_ERR_CONFIG;
2697 if (hw->phy.media_type == ixgbe_media_type_backplane) {
2698 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
2699 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2700 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2701 if (ret_val != IXGBE_SUCCESS)
2703 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2704 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2706 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2708 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2709 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
2710 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2711 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2713 /* Not all devices fully support AN. */
2714 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR)
2715 hw->fc.disable_fc_autoneg = true;
2723 * ixgbe_set_mux - Set mux for port 1 access with CS4227
2724 * @hw: pointer to hardware structure
2725 * @state: set mux if 1, clear if 0
2727 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2731 if (!hw->bus.lan_id)
2733 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2735 esdp |= IXGBE_ESDP_SDP1;
2737 esdp &= ~IXGBE_ESDP_SDP1;
2738 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2739 IXGBE_WRITE_FLUSH(hw);
2743 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2744 * @hw: pointer to hardware structure
2745 * @mask: Mask to specify which semaphore to acquire
2747 * Acquires the SWFW semaphore and sets the I2C MUX
2749 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2753 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
2755 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2759 if (mask & IXGBE_GSSR_I2C_MASK)
2760 ixgbe_set_mux(hw, 1);
2762 return IXGBE_SUCCESS;
2766 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2767 * @hw: pointer to hardware structure
2768 * @mask: Mask to specify which semaphore to release
2770 * Releases the SWFW semaphore and sets the I2C MUX
2772 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2774 DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
2776 if (mask & IXGBE_GSSR_I2C_MASK)
2777 ixgbe_set_mux(hw, 0);
2779 ixgbe_release_swfw_sync_X540(hw, mask);
2783 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2784 * @hw: pointer to hardware structure
2786 * Handle external Base T PHY interrupt. If high temperature
2787 * failure alarm then return error, else if link status change
2788 * then setup internal/external PHY link
2790 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2791 * failure alarm, else return PHY access status.
2793 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2798 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2800 if (status != IXGBE_SUCCESS)
2804 return ixgbe_setup_internal_phy_t_x550em(hw);
2806 return IXGBE_SUCCESS;
2810 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
2811 * @hw: pointer to hardware structure
2812 * @speed: new link speed
2813 * @autoneg_wait_to_complete: true when waiting for completion is needed
2815 * Setup internal/external PHY link speed based on link speed, then set
2816 * external PHY auto advertised link speed.
2818 * Returns error status for any failure
2820 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
2821 ixgbe_link_speed speed,
2822 bool autoneg_wait_to_complete)
2825 ixgbe_link_speed force_speed;
2827 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
2829 /* Setup internal/external PHY link speed to iXFI (10G), unless
2830 * only 1G is auto advertised then setup KX link.
2832 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2833 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2835 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2837 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
2839 if (status != IXGBE_SUCCESS)
2842 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
2846 * ixgbe_check_link_t_X550em - Determine link and speed status
2847 * @hw: pointer to hardware structure
2848 * @speed: pointer to link speed
2849 * @link_up: true when link is up
2850 * @link_up_wait_to_complete: bool used to wait for link up or not
2852 * Check that both the MAC and X557 external PHY have link.
2854 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
2855 bool *link_up, bool link_up_wait_to_complete)
2860 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2861 return IXGBE_ERR_CONFIG;
2863 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
2864 link_up_wait_to_complete);
2866 /* If check link fails or MAC link is not up, then return */
2867 if (status != IXGBE_SUCCESS || !(*link_up))
2870 /* MAC link is up, so check external PHY link.
2871 * Read this twice back to back to indicate current status.
2873 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2874 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2877 if (status != IXGBE_SUCCESS)
2880 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2881 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2884 if (status != IXGBE_SUCCESS)
2887 /* If external PHY link is not up, then indicate link not up */
2888 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
2891 return IXGBE_SUCCESS;
2895 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
2896 * @hw: pointer to hardware structure
2898 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
2902 status = ixgbe_reset_phy_generic(hw);
2904 if (status != IXGBE_SUCCESS)
2907 /* Configure Link Status Alarm and Temperature Threshold interrupts */
2908 return ixgbe_enable_lasi_ext_t_x550em(hw);